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1 | /* Print i386 instructions for GDB, the GNU debugger. |
1 | /* Print i386 instructions for GDB, the GNU debugger. |
2 | Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
- | |
3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
- | |
4 | Free Software Foundation, Inc. |
2 | Copyright (C) 1988-2015 Free Software Foundation, Inc. |
5 | 3 | ||
6 | This file is part of the GNU opcodes library. |
4 | This file is part of the GNU opcodes library. |
7 | 5 | ||
8 | This library is free software; you can redistribute it and/or modify |
6 | This library is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by |
7 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 3, or (at your option) |
8 | the Free Software Foundation; either version 3, or (at your option) |
11 | any later version. |
9 | any later version. |
12 | 10 | ||
13 | It is distributed in the hope that it will be useful, but WITHOUT |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
16 | License for more details. |
14 | License for more details. |
17 | 15 | ||
18 | You should have received a copy of the GNU General Public License |
16 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software |
17 | along with this program; if not, write to the Free Software |
20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ |
19 | MA 02110-1301, USA. */ |
22 | 20 | ||
23 | 21 | ||
24 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) |
25 | July 1988 |
23 | July 1988 |
26 | modified by John Hassey (hassey@dg-rtp.dg.com) |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) |
27 | x86-64 support added by Jan Hubicka (jh@suse.cz) |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) |
28 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ |
29 | 27 | ||
30 | /* The main tables describing the instructions is essentially a copy |
28 | /* The main tables describing the instructions is essentially a copy |
31 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 |
32 | Programmers Manual. Usually, there is a capital letter, followed |
30 | Programmers Manual. Usually, there is a capital letter, followed |
33 | by a small letter. The capital letter tell the addressing mode, |
31 | by a small letter. The capital letter tell the addressing mode, |
34 | and the small letter tells about the operand size. Refer to |
32 | and the small letter tells about the operand size. Refer to |
35 | the Intel manual for details. */ |
33 | the Intel manual for details. */ |
36 | 34 | ||
37 | #include "sysdep.h" |
35 | #include "sysdep.h" |
38 | #include "dis-asm.h" |
36 | #include "dis-asm.h" |
39 | #include "opintl.h" |
37 | #include "opintl.h" |
40 | #include "opcode/i386.h" |
38 | #include "opcode/i386.h" |
41 | #include "libiberty.h" |
39 | #include "libiberty.h" |
42 | 40 | ||
43 | #include |
41 | #include |
44 | 42 | ||
45 | static int print_insn (bfd_vma, disassemble_info *); |
43 | static int print_insn (bfd_vma, disassemble_info *); |
46 | static void dofloat (int); |
44 | static void dofloat (int); |
47 | static void OP_ST (int, int); |
45 | static void OP_ST (int, int); |
48 | static void OP_STi (int, int); |
46 | static void OP_STi (int, int); |
49 | static int putop (const char *, int); |
47 | static int putop (const char *, int); |
50 | static void oappend (const char *); |
48 | static void oappend (const char *); |
51 | static void append_seg (void); |
49 | static void append_seg (void); |
52 | static void OP_indirE (int, int); |
50 | static void OP_indirE (int, int); |
53 | static void print_operand_value (char *, int, bfd_vma); |
51 | static void print_operand_value (char *, int, bfd_vma); |
54 | static void OP_E_register (int, int); |
52 | static void OP_E_register (int, int); |
55 | static void OP_E_memory (int, int); |
53 | static void OP_E_memory (int, int); |
56 | static void print_displacement (char *, bfd_vma); |
54 | static void print_displacement (char *, bfd_vma); |
57 | static void OP_E (int, int); |
55 | static void OP_E (int, int); |
58 | static void OP_G (int, int); |
56 | static void OP_G (int, int); |
59 | static bfd_vma get64 (void); |
57 | static bfd_vma get64 (void); |
60 | static bfd_signed_vma get32 (void); |
58 | static bfd_signed_vma get32 (void); |
61 | static bfd_signed_vma get32s (void); |
59 | static bfd_signed_vma get32s (void); |
62 | static int get16 (void); |
60 | static int get16 (void); |
63 | static void set_op (bfd_vma, int); |
61 | static void set_op (bfd_vma, int); |
64 | static void OP_Skip_MODRM (int, int); |
62 | static void OP_Skip_MODRM (int, int); |
65 | static void OP_REG (int, int); |
63 | static void OP_REG (int, int); |
66 | static void OP_IMREG (int, int); |
64 | static void OP_IMREG (int, int); |
67 | static void OP_I (int, int); |
65 | static void OP_I (int, int); |
68 | static void OP_I64 (int, int); |
66 | static void OP_I64 (int, int); |
69 | static void OP_sI (int, int); |
67 | static void OP_sI (int, int); |
70 | static void OP_J (int, int); |
68 | static void OP_J (int, int); |
71 | static void OP_SEG (int, int); |
69 | static void OP_SEG (int, int); |
72 | static void OP_DIR (int, int); |
70 | static void OP_DIR (int, int); |
73 | static void OP_OFF (int, int); |
71 | static void OP_OFF (int, int); |
74 | static void OP_OFF64 (int, int); |
72 | static void OP_OFF64 (int, int); |
75 | static void ptr_reg (int, int); |
73 | static void ptr_reg (int, int); |
76 | static void OP_ESreg (int, int); |
74 | static void OP_ESreg (int, int); |
77 | static void OP_DSreg (int, int); |
75 | static void OP_DSreg (int, int); |
78 | static void OP_C (int, int); |
76 | static void OP_C (int, int); |
79 | static void OP_D (int, int); |
77 | static void OP_D (int, int); |
80 | static void OP_T (int, int); |
78 | static void OP_T (int, int); |
81 | static void OP_R (int, int); |
79 | static void OP_R (int, int); |
82 | static void OP_MMX (int, int); |
80 | static void OP_MMX (int, int); |
83 | static void OP_XMM (int, int); |
81 | static void OP_XMM (int, int); |
84 | static void OP_EM (int, int); |
82 | static void OP_EM (int, int); |
85 | static void OP_EX (int, int); |
83 | static void OP_EX (int, int); |
86 | static void OP_EMC (int,int); |
84 | static void OP_EMC (int,int); |
87 | static void OP_MXC (int,int); |
85 | static void OP_MXC (int,int); |
88 | static void OP_MS (int, int); |
86 | static void OP_MS (int, int); |
89 | static void OP_XS (int, int); |
87 | static void OP_XS (int, int); |
90 | static void OP_M (int, int); |
88 | static void OP_M (int, int); |
91 | static void OP_VEX (int, int); |
89 | static void OP_VEX (int, int); |
92 | static void OP_EX_Vex (int, int); |
90 | static void OP_EX_Vex (int, int); |
93 | static void OP_EX_VexW (int, int); |
91 | static void OP_EX_VexW (int, int); |
94 | static void OP_EX_VexImmW (int, int); |
92 | static void OP_EX_VexImmW (int, int); |
95 | static void OP_XMM_Vex (int, int); |
93 | static void OP_XMM_Vex (int, int); |
96 | static void OP_XMM_VexW (int, int); |
94 | static void OP_XMM_VexW (int, int); |
97 | static void OP_Rounding (int, int); |
95 | static void OP_Rounding (int, int); |
98 | static void OP_REG_VexI4 (int, int); |
96 | static void OP_REG_VexI4 (int, int); |
99 | static void PCLMUL_Fixup (int, int); |
97 | static void PCLMUL_Fixup (int, int); |
100 | static void VEXI4_Fixup (int, int); |
98 | static void VEXI4_Fixup (int, int); |
101 | static void VZERO_Fixup (int, int); |
99 | static void VZERO_Fixup (int, int); |
102 | static void VCMP_Fixup (int, int); |
100 | static void VCMP_Fixup (int, int); |
103 | static void VPCMP_Fixup (int, int); |
101 | static void VPCMP_Fixup (int, int); |
104 | static void OP_0f07 (int, int); |
102 | static void OP_0f07 (int, int); |
105 | static void OP_Monitor (int, int); |
103 | static void OP_Monitor (int, int); |
106 | static void OP_Mwait (int, int); |
104 | static void OP_Mwait (int, int); |
- | 105 | static void OP_Mwaitx (int, int); |
|
107 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup1 (int, int); |
108 | static void NOP_Fixup2 (int, int); |
107 | static void NOP_Fixup2 (int, int); |
109 | static void OP_3DNowSuffix (int, int); |
108 | static void OP_3DNowSuffix (int, int); |
110 | static void CMP_Fixup (int, int); |
109 | static void CMP_Fixup (int, int); |
111 | static void BadOp (void); |
110 | static void BadOp (void); |
112 | static void REP_Fixup (int, int); |
111 | static void REP_Fixup (int, int); |
113 | static void BND_Fixup (int, int); |
112 | static void BND_Fixup (int, int); |
114 | static void HLE_Fixup1 (int, int); |
113 | static void HLE_Fixup1 (int, int); |
115 | static void HLE_Fixup2 (int, int); |
114 | static void HLE_Fixup2 (int, int); |
116 | static void HLE_Fixup3 (int, int); |
115 | static void HLE_Fixup3 (int, int); |
117 | static void CMPXCHG8B_Fixup (int, int); |
116 | static void CMPXCHG8B_Fixup (int, int); |
118 | static void XMM_Fixup (int, int); |
117 | static void XMM_Fixup (int, int); |
119 | static void CRC32_Fixup (int, int); |
118 | static void CRC32_Fixup (int, int); |
120 | static void FXSAVE_Fixup (int, int); |
119 | static void FXSAVE_Fixup (int, int); |
121 | static void OP_LWPCB_E (int, int); |
120 | static void OP_LWPCB_E (int, int); |
122 | static void OP_LWP_E (int, int); |
121 | static void OP_LWP_E (int, int); |
123 | static void OP_Vex_2src_1 (int, int); |
122 | static void OP_Vex_2src_1 (int, int); |
124 | static void OP_Vex_2src_2 (int, int); |
123 | static void OP_Vex_2src_2 (int, int); |
125 | 124 | ||
126 | static void MOVBE_Fixup (int, int); |
125 | static void MOVBE_Fixup (int, int); |
127 | 126 | ||
128 | static void OP_Mask (int, int); |
127 | static void OP_Mask (int, int); |
129 | 128 | ||
130 | struct dis_private { |
129 | struct dis_private { |
131 | /* Points to first byte not fetched. */ |
130 | /* Points to first byte not fetched. */ |
132 | bfd_byte *max_fetched; |
131 | bfd_byte *max_fetched; |
133 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
132 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
134 | bfd_vma insn_start; |
133 | bfd_vma insn_start; |
135 | int orig_sizeflag; |
134 | int orig_sizeflag; |
136 | jmp_buf bailout; |
135 | OPCODES_SIGJMP_BUF bailout; |
137 | }; |
136 | }; |
138 | 137 | ||
139 | enum address_mode |
138 | enum address_mode |
140 | { |
139 | { |
141 | mode_16bit, |
140 | mode_16bit, |
142 | mode_32bit, |
141 | mode_32bit, |
143 | mode_64bit |
142 | mode_64bit |
144 | }; |
143 | }; |
145 | 144 | ||
146 | enum address_mode address_mode; |
145 | enum address_mode address_mode; |
147 | 146 | ||
148 | /* Flags for the prefixes for the current instruction. See below. */ |
147 | /* Flags for the prefixes for the current instruction. See below. */ |
149 | static int prefixes; |
148 | static int prefixes; |
150 | 149 | ||
151 | /* REX prefix the current instruction. See below. */ |
150 | /* REX prefix the current instruction. See below. */ |
152 | static int rex; |
151 | static int rex; |
153 | /* Bits of REX we've already used. */ |
152 | /* Bits of REX we've already used. */ |
154 | static int rex_used; |
153 | static int rex_used; |
155 | /* REX bits in original REX prefix ignored. */ |
154 | /* REX bits in original REX prefix ignored. */ |
156 | static int rex_ignored; |
155 | static int rex_ignored; |
157 | /* Mark parts used in the REX prefix. When we are testing for |
156 | /* Mark parts used in the REX prefix. When we are testing for |
158 | empty prefix (for 8bit register REX extension), just mask it |
157 | empty prefix (for 8bit register REX extension), just mask it |
159 | out. Otherwise test for REX bit is excuse for existence of REX |
158 | out. Otherwise test for REX bit is excuse for existence of REX |
160 | only in case value is nonzero. */ |
159 | only in case value is nonzero. */ |
161 | #define USED_REX(value) \ |
160 | #define USED_REX(value) \ |
162 | { \ |
161 | { \ |
163 | if (value) \ |
162 | if (value) \ |
164 | { \ |
163 | { \ |
165 | if ((rex & value)) \ |
164 | if ((rex & value)) \ |
166 | rex_used |= (value) | REX_OPCODE; \ |
165 | rex_used |= (value) | REX_OPCODE; \ |
167 | } \ |
166 | } \ |
168 | else \ |
167 | else \ |
169 | rex_used |= REX_OPCODE; \ |
168 | rex_used |= REX_OPCODE; \ |
170 | } |
169 | } |
171 | 170 | ||
172 | /* Flags for prefixes which we somehow handled when printing the |
171 | /* Flags for prefixes which we somehow handled when printing the |
173 | current instruction. */ |
172 | current instruction. */ |
174 | static int used_prefixes; |
173 | static int used_prefixes; |
175 | 174 | ||
176 | /* Flags stored in PREFIXES. */ |
175 | /* Flags stored in PREFIXES. */ |
177 | #define PREFIX_REPZ 1 |
176 | #define PREFIX_REPZ 1 |
178 | #define PREFIX_REPNZ 2 |
177 | #define PREFIX_REPNZ 2 |
179 | #define PREFIX_LOCK 4 |
178 | #define PREFIX_LOCK 4 |
180 | #define PREFIX_CS 8 |
179 | #define PREFIX_CS 8 |
181 | #define PREFIX_SS 0x10 |
180 | #define PREFIX_SS 0x10 |
182 | #define PREFIX_DS 0x20 |
181 | #define PREFIX_DS 0x20 |
183 | #define PREFIX_ES 0x40 |
182 | #define PREFIX_ES 0x40 |
184 | #define PREFIX_FS 0x80 |
183 | #define PREFIX_FS 0x80 |
185 | #define PREFIX_GS 0x100 |
184 | #define PREFIX_GS 0x100 |
186 | #define PREFIX_DATA 0x200 |
185 | #define PREFIX_DATA 0x200 |
187 | #define PREFIX_ADDR 0x400 |
186 | #define PREFIX_ADDR 0x400 |
188 | #define PREFIX_FWAIT 0x800 |
187 | #define PREFIX_FWAIT 0x800 |
189 | 188 | ||
190 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
189 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
191 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps |
190 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps |
192 | on error. */ |
191 | on error. */ |
193 | #define FETCH_DATA(info, addr) \ |
192 | #define FETCH_DATA(info, addr) \ |
194 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
193 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
195 | ? 1 : fetch_data ((info), (addr))) |
194 | ? 1 : fetch_data ((info), (addr))) |
196 | 195 | ||
197 | static int |
196 | static int |
198 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
197 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
199 | { |
198 | { |
200 | int status; |
199 | int status; |
201 | struct dis_private *priv = (struct dis_private *) info->private_data; |
200 | struct dis_private *priv = (struct dis_private *) info->private_data; |
202 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
201 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
203 | 202 | ||
204 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
203 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
205 | status = (*info->read_memory_func) (start, |
204 | status = (*info->read_memory_func) (start, |
206 | priv->max_fetched, |
205 | priv->max_fetched, |
207 | addr - priv->max_fetched, |
206 | addr - priv->max_fetched, |
208 | info); |
207 | info); |
209 | else |
208 | else |
210 | status = -1; |
209 | status = -1; |
211 | if (status != 0) |
210 | if (status != 0) |
212 | { |
211 | { |
213 | /* If we did manage to read at least one byte, then |
212 | /* If we did manage to read at least one byte, then |
214 | print_insn_i386 will do something sensible. Otherwise, print |
213 | print_insn_i386 will do something sensible. Otherwise, print |
215 | an error. We do that here because this is where we know |
214 | an error. We do that here because this is where we know |
216 | STATUS. */ |
215 | STATUS. */ |
217 | if (priv->max_fetched == priv->the_buffer) |
216 | if (priv->max_fetched == priv->the_buffer) |
218 | (*info->memory_error_func) (status, start, info); |
217 | (*info->memory_error_func) (status, start, info); |
219 | longjmp (priv->bailout, 1); |
218 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
220 | } |
219 | } |
221 | else |
220 | else |
222 | priv->max_fetched = addr; |
221 | priv->max_fetched = addr; |
223 | return 1; |
222 | return 1; |
224 | } |
223 | } |
- | 224 | ||
- | 225 | /* Possible values for prefix requirement. */ |
|
- | 226 | #define PREFIX_IGNORED_SHIFT 16 |
|
- | 227 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) |
|
- | 228 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) |
|
- | 229 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) |
|
- | 230 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) |
|
- | 231 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) |
|
- | 232 | ||
- | 233 | /* Opcode prefixes. */ |
|
- | 234 | #define PREFIX_OPCODE (PREFIX_REPZ \ |
|
- | 235 | | PREFIX_REPNZ \ |
|
- | 236 | | PREFIX_DATA) |
|
- | 237 | ||
- | 238 | /* Prefixes ignored. */ |
|
- | 239 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ |
|
- | 240 | | PREFIX_IGNORED_REPNZ \ |
|
- | 241 | | PREFIX_IGNORED_DATA) |
|
225 | 242 | ||
226 | #define XX { NULL, 0 } |
243 | #define XX { NULL, 0 } |
227 | #define Bad_Opcode NULL, { { NULL, 0 } } |
244 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
228 | 245 | ||
229 | #define Eb { OP_E, b_mode } |
246 | #define Eb { OP_E, b_mode } |
230 | #define Ebnd { OP_E, bnd_mode } |
247 | #define Ebnd { OP_E, bnd_mode } |
231 | #define EbS { OP_E, b_swap_mode } |
248 | #define EbS { OP_E, b_swap_mode } |
232 | #define Ev { OP_E, v_mode } |
249 | #define Ev { OP_E, v_mode } |
233 | #define Ev_bnd { OP_E, v_bnd_mode } |
250 | #define Ev_bnd { OP_E, v_bnd_mode } |
234 | #define EvS { OP_E, v_swap_mode } |
251 | #define EvS { OP_E, v_swap_mode } |
235 | #define Ed { OP_E, d_mode } |
252 | #define Ed { OP_E, d_mode } |
236 | #define Edq { OP_E, dq_mode } |
253 | #define Edq { OP_E, dq_mode } |
237 | #define Edqw { OP_E, dqw_mode } |
254 | #define Edqw { OP_E, dqw_mode } |
- | 255 | #define EdqwS { OP_E, dqw_swap_mode } |
|
238 | #define Edqb { OP_E, dqb_mode } |
256 | #define Edqb { OP_E, dqb_mode } |
- | 257 | #define Edb { OP_E, db_mode } |
|
- | 258 | #define Edw { OP_E, dw_mode } |
|
239 | #define Edqd { OP_E, dqd_mode } |
259 | #define Edqd { OP_E, dqd_mode } |
240 | #define Eq { OP_E, q_mode } |
260 | #define Eq { OP_E, q_mode } |
241 | #define indirEv { OP_indirE, stack_v_mode } |
261 | #define indirEv { OP_indirE, stack_v_mode } |
242 | #define indirEp { OP_indirE, f_mode } |
262 | #define indirEp { OP_indirE, f_mode } |
243 | #define stackEv { OP_E, stack_v_mode } |
263 | #define stackEv { OP_E, stack_v_mode } |
244 | #define Em { OP_E, m_mode } |
264 | #define Em { OP_E, m_mode } |
245 | #define Ew { OP_E, w_mode } |
265 | #define Ew { OP_E, w_mode } |
246 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ |
266 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ |
247 | #define Ma { OP_M, a_mode } |
267 | #define Ma { OP_M, a_mode } |
248 | #define Mb { OP_M, b_mode } |
268 | #define Mb { OP_M, b_mode } |
249 | #define Md { OP_M, d_mode } |
269 | #define Md { OP_M, d_mode } |
250 | #define Mo { OP_M, o_mode } |
270 | #define Mo { OP_M, o_mode } |
251 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
271 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
252 | #define Mq { OP_M, q_mode } |
272 | #define Mq { OP_M, q_mode } |
253 | #define Mx { OP_M, x_mode } |
273 | #define Mx { OP_M, x_mode } |
254 | #define Mxmm { OP_M, xmm_mode } |
274 | #define Mxmm { OP_M, xmm_mode } |
255 | #define Gb { OP_G, b_mode } |
275 | #define Gb { OP_G, b_mode } |
256 | #define Gbnd { OP_G, bnd_mode } |
276 | #define Gbnd { OP_G, bnd_mode } |
257 | #define Gv { OP_G, v_mode } |
277 | #define Gv { OP_G, v_mode } |
258 | #define Gd { OP_G, d_mode } |
278 | #define Gd { OP_G, d_mode } |
259 | #define Gdq { OP_G, dq_mode } |
279 | #define Gdq { OP_G, dq_mode } |
260 | #define Gm { OP_G, m_mode } |
280 | #define Gm { OP_G, m_mode } |
261 | #define Gw { OP_G, w_mode } |
281 | #define Gw { OP_G, w_mode } |
262 | #define Rd { OP_R, d_mode } |
282 | #define Rd { OP_R, d_mode } |
263 | #define Rdq { OP_R, dq_mode } |
283 | #define Rdq { OP_R, dq_mode } |
264 | #define Rm { OP_R, m_mode } |
284 | #define Rm { OP_R, m_mode } |
265 | #define Ib { OP_I, b_mode } |
285 | #define Ib { OP_I, b_mode } |
266 | #define sIb { OP_sI, b_mode } /* sign extened byte */ |
286 | #define sIb { OP_sI, b_mode } /* sign extened byte */ |
267 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
287 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
268 | #define Iv { OP_I, v_mode } |
288 | #define Iv { OP_I, v_mode } |
269 | #define sIv { OP_sI, v_mode } |
289 | #define sIv { OP_sI, v_mode } |
270 | #define Iq { OP_I, q_mode } |
290 | #define Iq { OP_I, q_mode } |
271 | #define Iv64 { OP_I64, v_mode } |
291 | #define Iv64 { OP_I64, v_mode } |
272 | #define Iw { OP_I, w_mode } |
292 | #define Iw { OP_I, w_mode } |
273 | #define I1 { OP_I, const_1_mode } |
293 | #define I1 { OP_I, const_1_mode } |
274 | #define Jb { OP_J, b_mode } |
294 | #define Jb { OP_J, b_mode } |
275 | #define Jv { OP_J, v_mode } |
295 | #define Jv { OP_J, v_mode } |
276 | #define Cm { OP_C, m_mode } |
296 | #define Cm { OP_C, m_mode } |
277 | #define Dm { OP_D, m_mode } |
297 | #define Dm { OP_D, m_mode } |
278 | #define Td { OP_T, d_mode } |
298 | #define Td { OP_T, d_mode } |
279 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
299 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
280 | 300 | ||
281 | #define RMeAX { OP_REG, eAX_reg } |
301 | #define RMeAX { OP_REG, eAX_reg } |
282 | #define RMeBX { OP_REG, eBX_reg } |
302 | #define RMeBX { OP_REG, eBX_reg } |
283 | #define RMeCX { OP_REG, eCX_reg } |
303 | #define RMeCX { OP_REG, eCX_reg } |
284 | #define RMeDX { OP_REG, eDX_reg } |
304 | #define RMeDX { OP_REG, eDX_reg } |
285 | #define RMeSP { OP_REG, eSP_reg } |
305 | #define RMeSP { OP_REG, eSP_reg } |
286 | #define RMeBP { OP_REG, eBP_reg } |
306 | #define RMeBP { OP_REG, eBP_reg } |
287 | #define RMeSI { OP_REG, eSI_reg } |
307 | #define RMeSI { OP_REG, eSI_reg } |
288 | #define RMeDI { OP_REG, eDI_reg } |
308 | #define RMeDI { OP_REG, eDI_reg } |
289 | #define RMrAX { OP_REG, rAX_reg } |
309 | #define RMrAX { OP_REG, rAX_reg } |
290 | #define RMrBX { OP_REG, rBX_reg } |
310 | #define RMrBX { OP_REG, rBX_reg } |
291 | #define RMrCX { OP_REG, rCX_reg } |
311 | #define RMrCX { OP_REG, rCX_reg } |
292 | #define RMrDX { OP_REG, rDX_reg } |
312 | #define RMrDX { OP_REG, rDX_reg } |
293 | #define RMrSP { OP_REG, rSP_reg } |
313 | #define RMrSP { OP_REG, rSP_reg } |
294 | #define RMrBP { OP_REG, rBP_reg } |
314 | #define RMrBP { OP_REG, rBP_reg } |
295 | #define RMrSI { OP_REG, rSI_reg } |
315 | #define RMrSI { OP_REG, rSI_reg } |
296 | #define RMrDI { OP_REG, rDI_reg } |
316 | #define RMrDI { OP_REG, rDI_reg } |
297 | #define RMAL { OP_REG, al_reg } |
317 | #define RMAL { OP_REG, al_reg } |
298 | #define RMCL { OP_REG, cl_reg } |
318 | #define RMCL { OP_REG, cl_reg } |
299 | #define RMDL { OP_REG, dl_reg } |
319 | #define RMDL { OP_REG, dl_reg } |
300 | #define RMBL { OP_REG, bl_reg } |
320 | #define RMBL { OP_REG, bl_reg } |
301 | #define RMAH { OP_REG, ah_reg } |
321 | #define RMAH { OP_REG, ah_reg } |
302 | #define RMCH { OP_REG, ch_reg } |
322 | #define RMCH { OP_REG, ch_reg } |
303 | #define RMDH { OP_REG, dh_reg } |
323 | #define RMDH { OP_REG, dh_reg } |
304 | #define RMBH { OP_REG, bh_reg } |
324 | #define RMBH { OP_REG, bh_reg } |
305 | #define RMAX { OP_REG, ax_reg } |
325 | #define RMAX { OP_REG, ax_reg } |
306 | #define RMDX { OP_REG, dx_reg } |
326 | #define RMDX { OP_REG, dx_reg } |
307 | 327 | ||
308 | #define eAX { OP_IMREG, eAX_reg } |
328 | #define eAX { OP_IMREG, eAX_reg } |
309 | #define eBX { OP_IMREG, eBX_reg } |
329 | #define eBX { OP_IMREG, eBX_reg } |
310 | #define eCX { OP_IMREG, eCX_reg } |
330 | #define eCX { OP_IMREG, eCX_reg } |
311 | #define eDX { OP_IMREG, eDX_reg } |
331 | #define eDX { OP_IMREG, eDX_reg } |
312 | #define eSP { OP_IMREG, eSP_reg } |
332 | #define eSP { OP_IMREG, eSP_reg } |
313 | #define eBP { OP_IMREG, eBP_reg } |
333 | #define eBP { OP_IMREG, eBP_reg } |
314 | #define eSI { OP_IMREG, eSI_reg } |
334 | #define eSI { OP_IMREG, eSI_reg } |
315 | #define eDI { OP_IMREG, eDI_reg } |
335 | #define eDI { OP_IMREG, eDI_reg } |
316 | #define AL { OP_IMREG, al_reg } |
336 | #define AL { OP_IMREG, al_reg } |
317 | #define CL { OP_IMREG, cl_reg } |
337 | #define CL { OP_IMREG, cl_reg } |
318 | #define DL { OP_IMREG, dl_reg } |
338 | #define DL { OP_IMREG, dl_reg } |
319 | #define BL { OP_IMREG, bl_reg } |
339 | #define BL { OP_IMREG, bl_reg } |
320 | #define AH { OP_IMREG, ah_reg } |
340 | #define AH { OP_IMREG, ah_reg } |
321 | #define CH { OP_IMREG, ch_reg } |
341 | #define CH { OP_IMREG, ch_reg } |
322 | #define DH { OP_IMREG, dh_reg } |
342 | #define DH { OP_IMREG, dh_reg } |
323 | #define BH { OP_IMREG, bh_reg } |
343 | #define BH { OP_IMREG, bh_reg } |
324 | #define AX { OP_IMREG, ax_reg } |
344 | #define AX { OP_IMREG, ax_reg } |
325 | #define DX { OP_IMREG, dx_reg } |
345 | #define DX { OP_IMREG, dx_reg } |
326 | #define zAX { OP_IMREG, z_mode_ax_reg } |
346 | #define zAX { OP_IMREG, z_mode_ax_reg } |
327 | #define indirDX { OP_IMREG, indir_dx_reg } |
347 | #define indirDX { OP_IMREG, indir_dx_reg } |
328 | 348 | ||
329 | #define Sw { OP_SEG, w_mode } |
349 | #define Sw { OP_SEG, w_mode } |
330 | #define Sv { OP_SEG, v_mode } |
350 | #define Sv { OP_SEG, v_mode } |
331 | #define Ap { OP_DIR, 0 } |
351 | #define Ap { OP_DIR, 0 } |
332 | #define Ob { OP_OFF64, b_mode } |
352 | #define Ob { OP_OFF64, b_mode } |
333 | #define Ov { OP_OFF64, v_mode } |
353 | #define Ov { OP_OFF64, v_mode } |
334 | #define Xb { OP_DSreg, eSI_reg } |
354 | #define Xb { OP_DSreg, eSI_reg } |
335 | #define Xv { OP_DSreg, eSI_reg } |
355 | #define Xv { OP_DSreg, eSI_reg } |
336 | #define Xz { OP_DSreg, eSI_reg } |
356 | #define Xz { OP_DSreg, eSI_reg } |
337 | #define Yb { OP_ESreg, eDI_reg } |
357 | #define Yb { OP_ESreg, eDI_reg } |
338 | #define Yv { OP_ESreg, eDI_reg } |
358 | #define Yv { OP_ESreg, eDI_reg } |
339 | #define DSBX { OP_DSreg, eBX_reg } |
359 | #define DSBX { OP_DSreg, eBX_reg } |
340 | 360 | ||
341 | #define es { OP_REG, es_reg } |
361 | #define es { OP_REG, es_reg } |
342 | #define ss { OP_REG, ss_reg } |
362 | #define ss { OP_REG, ss_reg } |
343 | #define cs { OP_REG, cs_reg } |
363 | #define cs { OP_REG, cs_reg } |
344 | #define ds { OP_REG, ds_reg } |
364 | #define ds { OP_REG, ds_reg } |
345 | #define fs { OP_REG, fs_reg } |
365 | #define fs { OP_REG, fs_reg } |
346 | #define gs { OP_REG, gs_reg } |
366 | #define gs { OP_REG, gs_reg } |
347 | 367 | ||
348 | #define MX { OP_MMX, 0 } |
368 | #define MX { OP_MMX, 0 } |
349 | #define XM { OP_XMM, 0 } |
369 | #define XM { OP_XMM, 0 } |
350 | #define XMScalar { OP_XMM, scalar_mode } |
370 | #define XMScalar { OP_XMM, scalar_mode } |
351 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
371 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
352 | #define XMM { OP_XMM, xmm_mode } |
372 | #define XMM { OP_XMM, xmm_mode } |
353 | #define XMxmmq { OP_XMM, xmmq_mode } |
373 | #define XMxmmq { OP_XMM, xmmq_mode } |
354 | #define EM { OP_EM, v_mode } |
374 | #define EM { OP_EM, v_mode } |
355 | #define EMS { OP_EM, v_swap_mode } |
375 | #define EMS { OP_EM, v_swap_mode } |
356 | #define EMd { OP_EM, d_mode } |
376 | #define EMd { OP_EM, d_mode } |
357 | #define EMx { OP_EM, x_mode } |
377 | #define EMx { OP_EM, x_mode } |
358 | #define EXw { OP_EX, w_mode } |
378 | #define EXw { OP_EX, w_mode } |
359 | #define EXd { OP_EX, d_mode } |
379 | #define EXd { OP_EX, d_mode } |
360 | #define EXdScalar { OP_EX, d_scalar_mode } |
380 | #define EXdScalar { OP_EX, d_scalar_mode } |
361 | #define EXdS { OP_EX, d_swap_mode } |
381 | #define EXdS { OP_EX, d_swap_mode } |
362 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
382 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
363 | #define EXq { OP_EX, q_mode } |
383 | #define EXq { OP_EX, q_mode } |
364 | #define EXqScalar { OP_EX, q_scalar_mode } |
384 | #define EXqScalar { OP_EX, q_scalar_mode } |
365 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } |
385 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } |
366 | #define EXqS { OP_EX, q_swap_mode } |
386 | #define EXqS { OP_EX, q_swap_mode } |
367 | #define EXx { OP_EX, x_mode } |
387 | #define EXx { OP_EX, x_mode } |
368 | #define EXxS { OP_EX, x_swap_mode } |
388 | #define EXxS { OP_EX, x_swap_mode } |
369 | #define EXxmm { OP_EX, xmm_mode } |
389 | #define EXxmm { OP_EX, xmm_mode } |
370 | #define EXymm { OP_EX, ymm_mode } |
390 | #define EXymm { OP_EX, ymm_mode } |
371 | #define EXxmmq { OP_EX, xmmq_mode } |
391 | #define EXxmmq { OP_EX, xmmq_mode } |
372 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
392 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
373 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
393 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
374 | #define EXxmm_mw { OP_EX, xmm_mw_mode } |
394 | #define EXxmm_mw { OP_EX, xmm_mw_mode } |
375 | #define EXxmm_md { OP_EX, xmm_md_mode } |
395 | #define EXxmm_md { OP_EX, xmm_md_mode } |
376 | #define EXxmm_mq { OP_EX, xmm_mq_mode } |
396 | #define EXxmm_mq { OP_EX, xmm_mq_mode } |
377 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
397 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
378 | #define EXxmmdw { OP_EX, xmmdw_mode } |
398 | #define EXxmmdw { OP_EX, xmmdw_mode } |
379 | #define EXxmmqd { OP_EX, xmmqd_mode } |
399 | #define EXxmmqd { OP_EX, xmmqd_mode } |
380 | #define EXymmq { OP_EX, ymmq_mode } |
400 | #define EXymmq { OP_EX, ymmq_mode } |
381 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
401 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
382 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
402 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
383 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
403 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
384 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } |
404 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } |
385 | #define MS { OP_MS, v_mode } |
405 | #define MS { OP_MS, v_mode } |
386 | #define XS { OP_XS, v_mode } |
406 | #define XS { OP_XS, v_mode } |
387 | #define EMCq { OP_EMC, q_mode } |
407 | #define EMCq { OP_EMC, q_mode } |
388 | #define MXC { OP_MXC, 0 } |
408 | #define MXC { OP_MXC, 0 } |
389 | #define OPSUF { OP_3DNowSuffix, 0 } |
409 | #define OPSUF { OP_3DNowSuffix, 0 } |
390 | #define CMP { CMP_Fixup, 0 } |
410 | #define CMP { CMP_Fixup, 0 } |
391 | #define XMM0 { XMM_Fixup, 0 } |
411 | #define XMM0 { XMM_Fixup, 0 } |
392 | #define FXSAVE { FXSAVE_Fixup, 0 } |
412 | #define FXSAVE { FXSAVE_Fixup, 0 } |
393 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
413 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
394 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } |
414 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } |
395 | 415 | ||
396 | #define Vex { OP_VEX, vex_mode } |
416 | #define Vex { OP_VEX, vex_mode } |
397 | #define VexScalar { OP_VEX, vex_scalar_mode } |
417 | #define VexScalar { OP_VEX, vex_scalar_mode } |
398 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
418 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
399 | #define Vex128 { OP_VEX, vex128_mode } |
419 | #define Vex128 { OP_VEX, vex128_mode } |
400 | #define Vex256 { OP_VEX, vex256_mode } |
420 | #define Vex256 { OP_VEX, vex256_mode } |
401 | #define VexGdq { OP_VEX, dq_mode } |
421 | #define VexGdq { OP_VEX, dq_mode } |
402 | #define VexI4 { VEXI4_Fixup, 0} |
422 | #define VexI4 { VEXI4_Fixup, 0} |
403 | #define EXdVex { OP_EX_Vex, d_mode } |
423 | #define EXdVex { OP_EX_Vex, d_mode } |
404 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
424 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
405 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
425 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
406 | #define EXqVex { OP_EX_Vex, q_mode } |
426 | #define EXqVex { OP_EX_Vex, q_mode } |
407 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
427 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
408 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
428 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
409 | #define EXVexW { OP_EX_VexW, x_mode } |
429 | #define EXVexW { OP_EX_VexW, x_mode } |
410 | #define EXdVexW { OP_EX_VexW, d_mode } |
430 | #define EXdVexW { OP_EX_VexW, d_mode } |
411 | #define EXqVexW { OP_EX_VexW, q_mode } |
431 | #define EXqVexW { OP_EX_VexW, q_mode } |
412 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
432 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
413 | #define XMVex { OP_XMM_Vex, 0 } |
433 | #define XMVex { OP_XMM_Vex, 0 } |
414 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
434 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
415 | #define XMVexW { OP_XMM_VexW, 0 } |
435 | #define XMVexW { OP_XMM_VexW, 0 } |
416 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
436 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
417 | #define PCLMUL { PCLMUL_Fixup, 0 } |
437 | #define PCLMUL { PCLMUL_Fixup, 0 } |
418 | #define VZERO { VZERO_Fixup, 0 } |
438 | #define VZERO { VZERO_Fixup, 0 } |
419 | #define VCMP { VCMP_Fixup, 0 } |
439 | #define VCMP { VCMP_Fixup, 0 } |
420 | #define VPCMP { VPCMP_Fixup, 0 } |
440 | #define VPCMP { VPCMP_Fixup, 0 } |
421 | 441 | ||
422 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } |
442 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } |
423 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
443 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
424 | 444 | ||
425 | #define XMask { OP_Mask, mask_mode } |
445 | #define XMask { OP_Mask, mask_mode } |
426 | #define MaskG { OP_G, mask_mode } |
446 | #define MaskG { OP_G, mask_mode } |
427 | #define MaskE { OP_E, mask_mode } |
447 | #define MaskE { OP_E, mask_mode } |
- | 448 | #define MaskBDE { OP_E, mask_bd_mode } |
|
428 | #define MaskR { OP_R, mask_mode } |
449 | #define MaskR { OP_R, mask_mode } |
429 | #define MaskVex { OP_VEX, mask_mode } |
450 | #define MaskVex { OP_VEX, mask_mode } |
430 | 451 | ||
431 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
452 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
- | 453 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
|
432 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
454 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
- | 455 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
|
433 | 456 | ||
434 | /* Used handle "rep" prefix for string instructions. */ |
457 | /* Used handle "rep" prefix for string instructions. */ |
435 | #define Xbr { REP_Fixup, eSI_reg } |
458 | #define Xbr { REP_Fixup, eSI_reg } |
436 | #define Xvr { REP_Fixup, eSI_reg } |
459 | #define Xvr { REP_Fixup, eSI_reg } |
437 | #define Ybr { REP_Fixup, eDI_reg } |
460 | #define Ybr { REP_Fixup, eDI_reg } |
438 | #define Yvr { REP_Fixup, eDI_reg } |
461 | #define Yvr { REP_Fixup, eDI_reg } |
439 | #define Yzr { REP_Fixup, eDI_reg } |
462 | #define Yzr { REP_Fixup, eDI_reg } |
440 | #define indirDXr { REP_Fixup, indir_dx_reg } |
463 | #define indirDXr { REP_Fixup, indir_dx_reg } |
441 | #define ALr { REP_Fixup, al_reg } |
464 | #define ALr { REP_Fixup, al_reg } |
442 | #define eAXr { REP_Fixup, eAX_reg } |
465 | #define eAXr { REP_Fixup, eAX_reg } |
443 | 466 | ||
444 | /* Used handle HLE prefix for lockable instructions. */ |
467 | /* Used handle HLE prefix for lockable instructions. */ |
445 | #define Ebh1 { HLE_Fixup1, b_mode } |
468 | #define Ebh1 { HLE_Fixup1, b_mode } |
446 | #define Evh1 { HLE_Fixup1, v_mode } |
469 | #define Evh1 { HLE_Fixup1, v_mode } |
447 | #define Ebh2 { HLE_Fixup2, b_mode } |
470 | #define Ebh2 { HLE_Fixup2, b_mode } |
448 | #define Evh2 { HLE_Fixup2, v_mode } |
471 | #define Evh2 { HLE_Fixup2, v_mode } |
449 | #define Ebh3 { HLE_Fixup3, b_mode } |
472 | #define Ebh3 { HLE_Fixup3, b_mode } |
450 | #define Evh3 { HLE_Fixup3, v_mode } |
473 | #define Evh3 { HLE_Fixup3, v_mode } |
451 | 474 | ||
452 | #define BND { BND_Fixup, 0 } |
475 | #define BND { BND_Fixup, 0 } |
453 | 476 | ||
454 | #define cond_jump_flag { NULL, cond_jump_mode } |
477 | #define cond_jump_flag { NULL, cond_jump_mode } |
455 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } |
478 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } |
456 | 479 | ||
457 | /* bits in sizeflag */ |
480 | /* bits in sizeflag */ |
458 | #define SUFFIX_ALWAYS 4 |
481 | #define SUFFIX_ALWAYS 4 |
459 | #define AFLAG 2 |
482 | #define AFLAG 2 |
460 | #define DFLAG 1 |
483 | #define DFLAG 1 |
461 | 484 | ||
462 | enum |
485 | enum |
463 | { |
486 | { |
464 | /* byte operand */ |
487 | /* byte operand */ |
465 | b_mode = 1, |
488 | b_mode = 1, |
466 | /* byte operand with operand swapped */ |
489 | /* byte operand with operand swapped */ |
467 | b_swap_mode, |
490 | b_swap_mode, |
468 | /* byte operand, sign extend like 'T' suffix */ |
491 | /* byte operand, sign extend like 'T' suffix */ |
469 | b_T_mode, |
492 | b_T_mode, |
470 | /* operand size depends on prefixes */ |
493 | /* operand size depends on prefixes */ |
471 | v_mode, |
494 | v_mode, |
472 | /* operand size depends on prefixes with operand swapped */ |
495 | /* operand size depends on prefixes with operand swapped */ |
473 | v_swap_mode, |
496 | v_swap_mode, |
474 | /* word operand */ |
497 | /* word operand */ |
475 | w_mode, |
498 | w_mode, |
476 | /* double word operand */ |
499 | /* double word operand */ |
477 | d_mode, |
500 | d_mode, |
478 | /* double word operand with operand swapped */ |
501 | /* double word operand with operand swapped */ |
479 | d_swap_mode, |
502 | d_swap_mode, |
480 | /* quad word operand */ |
503 | /* quad word operand */ |
481 | q_mode, |
504 | q_mode, |
482 | /* quad word operand with operand swapped */ |
505 | /* quad word operand with operand swapped */ |
483 | q_swap_mode, |
506 | q_swap_mode, |
484 | /* ten-byte operand */ |
507 | /* ten-byte operand */ |
485 | t_mode, |
508 | t_mode, |
486 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
509 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
487 | broadcast enabled. */ |
510 | broadcast enabled. */ |
488 | x_mode, |
511 | x_mode, |
489 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
512 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
490 | evex_x_gscat_mode, |
513 | evex_x_gscat_mode, |
491 | /* Similar to x_mode, but with disabled broadcast. */ |
514 | /* Similar to x_mode, but with disabled broadcast. */ |
492 | evex_x_nobcst_mode, |
515 | evex_x_nobcst_mode, |
493 | /* Similar to x_mode, but with operands swapped and disabled broadcast |
516 | /* Similar to x_mode, but with operands swapped and disabled broadcast |
494 | in EVEX. */ |
517 | in EVEX. */ |
495 | x_swap_mode, |
518 | x_swap_mode, |
496 | /* 16-byte XMM operand */ |
519 | /* 16-byte XMM operand */ |
497 | xmm_mode, |
520 | xmm_mode, |
498 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
521 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
499 | memory operand (depending on vector length). Broadcast isn't |
522 | memory operand (depending on vector length). Broadcast isn't |
500 | allowed. */ |
523 | allowed. */ |
501 | xmmq_mode, |
524 | xmmq_mode, |
502 | /* Same as xmmq_mode, but broadcast is allowed. */ |
525 | /* Same as xmmq_mode, but broadcast is allowed. */ |
503 | evex_half_bcst_xmmq_mode, |
526 | evex_half_bcst_xmmq_mode, |
504 | /* XMM register or byte memory operand */ |
527 | /* XMM register or byte memory operand */ |
505 | xmm_mb_mode, |
528 | xmm_mb_mode, |
506 | /* XMM register or word memory operand */ |
529 | /* XMM register or word memory operand */ |
507 | xmm_mw_mode, |
530 | xmm_mw_mode, |
508 | /* XMM register or double word memory operand */ |
531 | /* XMM register or double word memory operand */ |
509 | xmm_md_mode, |
532 | xmm_md_mode, |
510 | /* XMM register or quad word memory operand */ |
533 | /* XMM register or quad word memory operand */ |
511 | xmm_mq_mode, |
534 | xmm_mq_mode, |
512 | /* XMM register or double/quad word memory operand, depending on |
535 | /* XMM register or double/quad word memory operand, depending on |
513 | VEX.W. */ |
536 | VEX.W. */ |
514 | xmm_mdq_mode, |
537 | xmm_mdq_mode, |
515 | /* 16-byte XMM, word, double word or quad word operand. */ |
538 | /* 16-byte XMM, word, double word or quad word operand. */ |
516 | xmmdw_mode, |
539 | xmmdw_mode, |
517 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
540 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
518 | xmmqd_mode, |
541 | xmmqd_mode, |
519 | /* 32-byte YMM operand */ |
542 | /* 32-byte YMM operand */ |
520 | ymm_mode, |
543 | ymm_mode, |
521 | /* quad word, ymmword or zmmword memory operand. */ |
544 | /* quad word, ymmword or zmmword memory operand. */ |
522 | ymmq_mode, |
545 | ymmq_mode, |
523 | /* 32-byte YMM or 16-byte word operand */ |
546 | /* 32-byte YMM or 16-byte word operand */ |
524 | ymmxmm_mode, |
547 | ymmxmm_mode, |
525 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
548 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
526 | m_mode, |
549 | m_mode, |
527 | /* pair of v_mode operands */ |
550 | /* pair of v_mode operands */ |
528 | a_mode, |
551 | a_mode, |
529 | cond_jump_mode, |
552 | cond_jump_mode, |
530 | loop_jcxz_mode, |
553 | loop_jcxz_mode, |
531 | v_bnd_mode, |
554 | v_bnd_mode, |
532 | /* operand size depends on REX prefixes. */ |
555 | /* operand size depends on REX prefixes. */ |
533 | dq_mode, |
556 | dq_mode, |
534 | /* registers like dq_mode, memory like w_mode. */ |
557 | /* registers like dq_mode, memory like w_mode. */ |
535 | dqw_mode, |
558 | dqw_mode, |
- | 559 | dqw_swap_mode, |
|
536 | bnd_mode, |
560 | bnd_mode, |
537 | /* 4- or 6-byte pointer operand */ |
561 | /* 4- or 6-byte pointer operand */ |
538 | f_mode, |
562 | f_mode, |
539 | const_1_mode, |
563 | const_1_mode, |
540 | /* v_mode for stack-related opcodes. */ |
564 | /* v_mode for stack-related opcodes. */ |
541 | stack_v_mode, |
565 | stack_v_mode, |
542 | /* non-quad operand size depends on prefixes */ |
566 | /* non-quad operand size depends on prefixes */ |
543 | z_mode, |
567 | z_mode, |
544 | /* 16-byte operand */ |
568 | /* 16-byte operand */ |
545 | o_mode, |
569 | o_mode, |
546 | /* registers like dq_mode, memory like b_mode. */ |
570 | /* registers like dq_mode, memory like b_mode. */ |
547 | dqb_mode, |
571 | dqb_mode, |
- | 572 | /* registers like d_mode, memory like b_mode. */ |
|
- | 573 | db_mode, |
|
- | 574 | /* registers like d_mode, memory like w_mode. */ |
|
- | 575 | dw_mode, |
|
548 | /* registers like dq_mode, memory like d_mode. */ |
576 | /* registers like dq_mode, memory like d_mode. */ |
549 | dqd_mode, |
577 | dqd_mode, |
550 | /* normal vex mode */ |
578 | /* normal vex mode */ |
551 | vex_mode, |
579 | vex_mode, |
552 | /* 128bit vex mode */ |
580 | /* 128bit vex mode */ |
553 | vex128_mode, |
581 | vex128_mode, |
554 | /* 256bit vex mode */ |
582 | /* 256bit vex mode */ |
555 | vex256_mode, |
583 | vex256_mode, |
556 | /* operand size depends on the VEX.W bit. */ |
584 | /* operand size depends on the VEX.W bit. */ |
557 | vex_w_dq_mode, |
585 | vex_w_dq_mode, |
558 | 586 | ||
559 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
587 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
560 | vex_vsib_d_w_dq_mode, |
588 | vex_vsib_d_w_dq_mode, |
- | 589 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
|
- | 590 | vex_vsib_d_w_d_mode, |
|
561 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
591 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
562 | vex_vsib_q_w_dq_mode, |
592 | vex_vsib_q_w_dq_mode, |
- | 593 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
|
- | 594 | vex_vsib_q_w_d_mode, |
|
563 | 595 | ||
564 | /* scalar, ignore vector length. */ |
596 | /* scalar, ignore vector length. */ |
565 | scalar_mode, |
597 | scalar_mode, |
566 | /* like d_mode, ignore vector length. */ |
598 | /* like d_mode, ignore vector length. */ |
567 | d_scalar_mode, |
599 | d_scalar_mode, |
568 | /* like d_swap_mode, ignore vector length. */ |
600 | /* like d_swap_mode, ignore vector length. */ |
569 | d_scalar_swap_mode, |
601 | d_scalar_swap_mode, |
570 | /* like q_mode, ignore vector length. */ |
602 | /* like q_mode, ignore vector length. */ |
571 | q_scalar_mode, |
603 | q_scalar_mode, |
572 | /* like q_swap_mode, ignore vector length. */ |
604 | /* like q_swap_mode, ignore vector length. */ |
573 | q_scalar_swap_mode, |
605 | q_scalar_swap_mode, |
574 | /* like vex_mode, ignore vector length. */ |
606 | /* like vex_mode, ignore vector length. */ |
575 | vex_scalar_mode, |
607 | vex_scalar_mode, |
576 | /* like vex_w_dq_mode, ignore vector length. */ |
608 | /* like vex_w_dq_mode, ignore vector length. */ |
577 | vex_scalar_w_dq_mode, |
609 | vex_scalar_w_dq_mode, |
578 | 610 | ||
579 | /* Static rounding. */ |
611 | /* Static rounding. */ |
580 | evex_rounding_mode, |
612 | evex_rounding_mode, |
581 | /* Supress all exceptions. */ |
613 | /* Supress all exceptions. */ |
582 | evex_sae_mode, |
614 | evex_sae_mode, |
583 | 615 | ||
584 | /* Mask register operand. */ |
616 | /* Mask register operand. */ |
585 | mask_mode, |
617 | mask_mode, |
- | 618 | /* Mask register operand. */ |
|
- | 619 | mask_bd_mode, |
|
586 | 620 | ||
587 | es_reg, |
621 | es_reg, |
588 | cs_reg, |
622 | cs_reg, |
589 | ss_reg, |
623 | ss_reg, |
590 | ds_reg, |
624 | ds_reg, |
591 | fs_reg, |
625 | fs_reg, |
592 | gs_reg, |
626 | gs_reg, |
593 | 627 | ||
594 | eAX_reg, |
628 | eAX_reg, |
595 | eCX_reg, |
629 | eCX_reg, |
596 | eDX_reg, |
630 | eDX_reg, |
597 | eBX_reg, |
631 | eBX_reg, |
598 | eSP_reg, |
632 | eSP_reg, |
599 | eBP_reg, |
633 | eBP_reg, |
600 | eSI_reg, |
634 | eSI_reg, |
601 | eDI_reg, |
635 | eDI_reg, |
602 | 636 | ||
603 | al_reg, |
637 | al_reg, |
604 | cl_reg, |
638 | cl_reg, |
605 | dl_reg, |
639 | dl_reg, |
606 | bl_reg, |
640 | bl_reg, |
607 | ah_reg, |
641 | ah_reg, |
608 | ch_reg, |
642 | ch_reg, |
609 | dh_reg, |
643 | dh_reg, |
610 | bh_reg, |
644 | bh_reg, |
611 | 645 | ||
612 | ax_reg, |
646 | ax_reg, |
613 | cx_reg, |
647 | cx_reg, |
614 | dx_reg, |
648 | dx_reg, |
615 | bx_reg, |
649 | bx_reg, |
616 | sp_reg, |
650 | sp_reg, |
617 | bp_reg, |
651 | bp_reg, |
618 | si_reg, |
652 | si_reg, |
619 | di_reg, |
653 | di_reg, |
620 | 654 | ||
621 | rAX_reg, |
655 | rAX_reg, |
622 | rCX_reg, |
656 | rCX_reg, |
623 | rDX_reg, |
657 | rDX_reg, |
624 | rBX_reg, |
658 | rBX_reg, |
625 | rSP_reg, |
659 | rSP_reg, |
626 | rBP_reg, |
660 | rBP_reg, |
627 | rSI_reg, |
661 | rSI_reg, |
628 | rDI_reg, |
662 | rDI_reg, |
629 | 663 | ||
630 | z_mode_ax_reg, |
664 | z_mode_ax_reg, |
631 | indir_dx_reg |
665 | indir_dx_reg |
632 | }; |
666 | }; |
633 | 667 | ||
634 | enum |
668 | enum |
635 | { |
669 | { |
636 | FLOATCODE = 1, |
670 | FLOATCODE = 1, |
637 | USE_REG_TABLE, |
671 | USE_REG_TABLE, |
638 | USE_MOD_TABLE, |
672 | USE_MOD_TABLE, |
639 | USE_RM_TABLE, |
673 | USE_RM_TABLE, |
640 | USE_PREFIX_TABLE, |
674 | USE_PREFIX_TABLE, |
641 | USE_X86_64_TABLE, |
675 | USE_X86_64_TABLE, |
642 | USE_3BYTE_TABLE, |
676 | USE_3BYTE_TABLE, |
643 | USE_XOP_8F_TABLE, |
677 | USE_XOP_8F_TABLE, |
644 | USE_VEX_C4_TABLE, |
678 | USE_VEX_C4_TABLE, |
645 | USE_VEX_C5_TABLE, |
679 | USE_VEX_C5_TABLE, |
646 | USE_VEX_LEN_TABLE, |
680 | USE_VEX_LEN_TABLE, |
647 | USE_VEX_W_TABLE, |
681 | USE_VEX_W_TABLE, |
648 | USE_EVEX_TABLE |
682 | USE_EVEX_TABLE |
649 | }; |
683 | }; |
650 | 684 | ||
651 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
685 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
- | 686 | ||
652 | 687 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
|
653 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
688 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P |
654 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
689 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
655 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) |
690 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) |
656 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) |
691 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) |
657 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) |
692 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) |
658 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
693 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
659 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) |
694 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) |
- | 695 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
|
660 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
696 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
661 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
697 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
662 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) |
698 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) |
663 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) |
699 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) |
664 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
700 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
665 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
701 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
666 | 702 | ||
667 | enum |
703 | enum |
668 | { |
704 | { |
669 | REG_80 = 0, |
705 | REG_80 = 0, |
670 | REG_81, |
706 | REG_81, |
671 | REG_82, |
707 | REG_82, |
672 | REG_8F, |
708 | REG_8F, |
673 | REG_C0, |
709 | REG_C0, |
674 | REG_C1, |
710 | REG_C1, |
675 | REG_C6, |
711 | REG_C6, |
676 | REG_C7, |
712 | REG_C7, |
677 | REG_D0, |
713 | REG_D0, |
678 | REG_D1, |
714 | REG_D1, |
679 | REG_D2, |
715 | REG_D2, |
680 | REG_D3, |
716 | REG_D3, |
681 | REG_F6, |
717 | REG_F6, |
682 | REG_F7, |
718 | REG_F7, |
683 | REG_FE, |
719 | REG_FE, |
684 | REG_FF, |
720 | REG_FF, |
685 | REG_0F00, |
721 | REG_0F00, |
686 | REG_0F01, |
722 | REG_0F01, |
687 | REG_0F0D, |
723 | REG_0F0D, |
688 | REG_0F18, |
724 | REG_0F18, |
689 | REG_0F71, |
725 | REG_0F71, |
690 | REG_0F72, |
726 | REG_0F72, |
691 | REG_0F73, |
727 | REG_0F73, |
692 | REG_0FA6, |
728 | REG_0FA6, |
693 | REG_0FA7, |
729 | REG_0FA7, |
694 | REG_0FAE, |
730 | REG_0FAE, |
695 | REG_0FBA, |
731 | REG_0FBA, |
696 | REG_0FC7, |
732 | REG_0FC7, |
697 | REG_VEX_0F71, |
733 | REG_VEX_0F71, |
698 | REG_VEX_0F72, |
734 | REG_VEX_0F72, |
699 | REG_VEX_0F73, |
735 | REG_VEX_0F73, |
700 | REG_VEX_0FAE, |
736 | REG_VEX_0FAE, |
701 | REG_VEX_0F38F3, |
737 | REG_VEX_0F38F3, |
702 | REG_XOP_LWPCB, |
738 | REG_XOP_LWPCB, |
703 | REG_XOP_LWP, |
739 | REG_XOP_LWP, |
704 | REG_XOP_TBM_01, |
740 | REG_XOP_TBM_01, |
705 | REG_XOP_TBM_02, |
741 | REG_XOP_TBM_02, |
- | 742 | ||
706 | 743 | REG_EVEX_0F71, |
|
707 | REG_EVEX_0F72, |
744 | REG_EVEX_0F72, |
708 | REG_EVEX_0F73, |
745 | REG_EVEX_0F73, |
709 | REG_EVEX_0F38C6, |
746 | REG_EVEX_0F38C6, |
710 | REG_EVEX_0F38C7 |
747 | REG_EVEX_0F38C7 |
711 | }; |
748 | }; |
712 | 749 | ||
713 | enum |
750 | enum |
714 | { |
751 | { |
715 | MOD_8D = 0, |
752 | MOD_8D = 0, |
716 | MOD_C6_REG_7, |
753 | MOD_C6_REG_7, |
717 | MOD_C7_REG_7, |
754 | MOD_C7_REG_7, |
- | 755 | MOD_FF_REG_3, |
|
- | 756 | MOD_FF_REG_5, |
|
718 | MOD_0F01_REG_0, |
757 | MOD_0F01_REG_0, |
719 | MOD_0F01_REG_1, |
758 | MOD_0F01_REG_1, |
720 | MOD_0F01_REG_2, |
759 | MOD_0F01_REG_2, |
721 | MOD_0F01_REG_3, |
760 | MOD_0F01_REG_3, |
- | 761 | MOD_0F01_REG_5, |
|
722 | MOD_0F01_REG_7, |
762 | MOD_0F01_REG_7, |
723 | MOD_0F12_PREFIX_0, |
763 | MOD_0F12_PREFIX_0, |
724 | MOD_0F13, |
764 | MOD_0F13, |
725 | MOD_0F16_PREFIX_0, |
765 | MOD_0F16_PREFIX_0, |
726 | MOD_0F17, |
766 | MOD_0F17, |
727 | MOD_0F18_REG_0, |
767 | MOD_0F18_REG_0, |
728 | MOD_0F18_REG_1, |
768 | MOD_0F18_REG_1, |
729 | MOD_0F18_REG_2, |
769 | MOD_0F18_REG_2, |
730 | MOD_0F18_REG_3, |
770 | MOD_0F18_REG_3, |
731 | MOD_0F18_REG_4, |
771 | MOD_0F18_REG_4, |
732 | MOD_0F18_REG_5, |
772 | MOD_0F18_REG_5, |
733 | MOD_0F18_REG_6, |
773 | MOD_0F18_REG_6, |
734 | MOD_0F18_REG_7, |
774 | MOD_0F18_REG_7, |
735 | MOD_0F1A_PREFIX_0, |
775 | MOD_0F1A_PREFIX_0, |
736 | MOD_0F1B_PREFIX_0, |
776 | MOD_0F1B_PREFIX_0, |
737 | MOD_0F1B_PREFIX_1, |
777 | MOD_0F1B_PREFIX_1, |
738 | MOD_0F20, |
- | |
739 | MOD_0F21, |
- | |
740 | MOD_0F22, |
- | |
741 | MOD_0F23, |
- | |
742 | MOD_0F24, |
778 | MOD_0F24, |
743 | MOD_0F26, |
779 | MOD_0F26, |
744 | MOD_0F2B_PREFIX_0, |
780 | MOD_0F2B_PREFIX_0, |
745 | MOD_0F2B_PREFIX_1, |
781 | MOD_0F2B_PREFIX_1, |
746 | MOD_0F2B_PREFIX_2, |
782 | MOD_0F2B_PREFIX_2, |
747 | MOD_0F2B_PREFIX_3, |
783 | MOD_0F2B_PREFIX_3, |
748 | MOD_0F51, |
784 | MOD_0F51, |
749 | MOD_0F71_REG_2, |
785 | MOD_0F71_REG_2, |
750 | MOD_0F71_REG_4, |
786 | MOD_0F71_REG_4, |
751 | MOD_0F71_REG_6, |
787 | MOD_0F71_REG_6, |
752 | MOD_0F72_REG_2, |
788 | MOD_0F72_REG_2, |
753 | MOD_0F72_REG_4, |
789 | MOD_0F72_REG_4, |
754 | MOD_0F72_REG_6, |
790 | MOD_0F72_REG_6, |
755 | MOD_0F73_REG_2, |
791 | MOD_0F73_REG_2, |
756 | MOD_0F73_REG_3, |
792 | MOD_0F73_REG_3, |
757 | MOD_0F73_REG_6, |
793 | MOD_0F73_REG_6, |
758 | MOD_0F73_REG_7, |
794 | MOD_0F73_REG_7, |
759 | MOD_0FAE_REG_0, |
795 | MOD_0FAE_REG_0, |
760 | MOD_0FAE_REG_1, |
796 | MOD_0FAE_REG_1, |
761 | MOD_0FAE_REG_2, |
797 | MOD_0FAE_REG_2, |
762 | MOD_0FAE_REG_3, |
798 | MOD_0FAE_REG_3, |
763 | MOD_0FAE_REG_4, |
799 | MOD_0FAE_REG_4, |
764 | MOD_0FAE_REG_5, |
800 | MOD_0FAE_REG_5, |
765 | MOD_0FAE_REG_6, |
801 | MOD_0FAE_REG_6, |
766 | MOD_0FAE_REG_7, |
802 | MOD_0FAE_REG_7, |
767 | MOD_0FB2, |
803 | MOD_0FB2, |
768 | MOD_0FB4, |
804 | MOD_0FB4, |
769 | MOD_0FB5, |
805 | MOD_0FB5, |
- | 806 | MOD_0FC3, |
|
- | 807 | MOD_0FC7_REG_3, |
|
- | 808 | MOD_0FC7_REG_4, |
|
- | 809 | MOD_0FC7_REG_5, |
|
770 | MOD_0FC7_REG_6, |
810 | MOD_0FC7_REG_6, |
771 | MOD_0FC7_REG_7, |
811 | MOD_0FC7_REG_7, |
772 | MOD_0FD7, |
812 | MOD_0FD7, |
773 | MOD_0FE7_PREFIX_2, |
813 | MOD_0FE7_PREFIX_2, |
774 | MOD_0FF0_PREFIX_3, |
814 | MOD_0FF0_PREFIX_3, |
775 | MOD_0F382A_PREFIX_2, |
815 | MOD_0F382A_PREFIX_2, |
776 | MOD_62_32BIT, |
816 | MOD_62_32BIT, |
777 | MOD_C4_32BIT, |
817 | MOD_C4_32BIT, |
778 | MOD_C5_32BIT, |
818 | MOD_C5_32BIT, |
779 | MOD_VEX_0F12_PREFIX_0, |
819 | MOD_VEX_0F12_PREFIX_0, |
780 | MOD_VEX_0F13, |
820 | MOD_VEX_0F13, |
781 | MOD_VEX_0F16_PREFIX_0, |
821 | MOD_VEX_0F16_PREFIX_0, |
782 | MOD_VEX_0F17, |
822 | MOD_VEX_0F17, |
783 | MOD_VEX_0F2B, |
823 | MOD_VEX_0F2B, |
- | 824 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
|
- | 825 | MOD_VEX_W_1_0F41_P_0_LEN_1, |
|
- | 826 | MOD_VEX_W_0_0F41_P_2_LEN_1, |
|
- | 827 | MOD_VEX_W_1_0F41_P_2_LEN_1, |
|
- | 828 | MOD_VEX_W_0_0F42_P_0_LEN_1, |
|
- | 829 | MOD_VEX_W_1_0F42_P_0_LEN_1, |
|
- | 830 | MOD_VEX_W_0_0F42_P_2_LEN_1, |
|
- | 831 | MOD_VEX_W_1_0F42_P_2_LEN_1, |
|
- | 832 | MOD_VEX_W_0_0F44_P_0_LEN_1, |
|
- | 833 | MOD_VEX_W_1_0F44_P_0_LEN_1, |
|
- | 834 | MOD_VEX_W_0_0F44_P_2_LEN_1, |
|
- | 835 | MOD_VEX_W_1_0F44_P_2_LEN_1, |
|
- | 836 | MOD_VEX_W_0_0F45_P_0_LEN_1, |
|
- | 837 | MOD_VEX_W_1_0F45_P_0_LEN_1, |
|
- | 838 | MOD_VEX_W_0_0F45_P_2_LEN_1, |
|
- | 839 | MOD_VEX_W_1_0F45_P_2_LEN_1, |
|
- | 840 | MOD_VEX_W_0_0F46_P_0_LEN_1, |
|
- | 841 | MOD_VEX_W_1_0F46_P_0_LEN_1, |
|
- | 842 | MOD_VEX_W_0_0F46_P_2_LEN_1, |
|
- | 843 | MOD_VEX_W_1_0F46_P_2_LEN_1, |
|
- | 844 | MOD_VEX_W_0_0F47_P_0_LEN_1, |
|
- | 845 | MOD_VEX_W_1_0F47_P_0_LEN_1, |
|
- | 846 | MOD_VEX_W_0_0F47_P_2_LEN_1, |
|
- | 847 | MOD_VEX_W_1_0F47_P_2_LEN_1, |
|
- | 848 | MOD_VEX_W_0_0F4A_P_0_LEN_1, |
|
- | 849 | MOD_VEX_W_1_0F4A_P_0_LEN_1, |
|
- | 850 | MOD_VEX_W_0_0F4A_P_2_LEN_1, |
|
- | 851 | MOD_VEX_W_1_0F4A_P_2_LEN_1, |
|
- | 852 | MOD_VEX_W_0_0F4B_P_0_LEN_1, |
|
- | 853 | MOD_VEX_W_1_0F4B_P_0_LEN_1, |
|
- | 854 | MOD_VEX_W_0_0F4B_P_2_LEN_1, |
|
784 | MOD_VEX_0F50, |
855 | MOD_VEX_0F50, |
785 | MOD_VEX_0F71_REG_2, |
856 | MOD_VEX_0F71_REG_2, |
786 | MOD_VEX_0F71_REG_4, |
857 | MOD_VEX_0F71_REG_4, |
787 | MOD_VEX_0F71_REG_6, |
858 | MOD_VEX_0F71_REG_6, |
788 | MOD_VEX_0F72_REG_2, |
859 | MOD_VEX_0F72_REG_2, |
789 | MOD_VEX_0F72_REG_4, |
860 | MOD_VEX_0F72_REG_4, |
790 | MOD_VEX_0F72_REG_6, |
861 | MOD_VEX_0F72_REG_6, |
791 | MOD_VEX_0F73_REG_2, |
862 | MOD_VEX_0F73_REG_2, |
792 | MOD_VEX_0F73_REG_3, |
863 | MOD_VEX_0F73_REG_3, |
793 | MOD_VEX_0F73_REG_6, |
864 | MOD_VEX_0F73_REG_6, |
794 | MOD_VEX_0F73_REG_7, |
865 | MOD_VEX_0F73_REG_7, |
- | 866 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
|
- | 867 | MOD_VEX_W_1_0F91_P_0_LEN_0, |
|
- | 868 | MOD_VEX_W_0_0F91_P_2_LEN_0, |
|
- | 869 | MOD_VEX_W_1_0F91_P_2_LEN_0, |
|
- | 870 | MOD_VEX_W_0_0F92_P_0_LEN_0, |
|
- | 871 | MOD_VEX_W_0_0F92_P_2_LEN_0, |
|
- | 872 | MOD_VEX_W_0_0F92_P_3_LEN_0, |
|
- | 873 | MOD_VEX_W_1_0F92_P_3_LEN_0, |
|
- | 874 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
|
- | 875 | MOD_VEX_W_0_0F93_P_2_LEN_0, |
|
- | 876 | MOD_VEX_W_0_0F93_P_3_LEN_0, |
|
- | 877 | MOD_VEX_W_1_0F93_P_3_LEN_0, |
|
- | 878 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
|
- | 879 | MOD_VEX_W_1_0F98_P_0_LEN_0, |
|
- | 880 | MOD_VEX_W_0_0F98_P_2_LEN_0, |
|
- | 881 | MOD_VEX_W_1_0F98_P_2_LEN_0, |
|
- | 882 | MOD_VEX_W_0_0F99_P_0_LEN_0, |
|
- | 883 | MOD_VEX_W_1_0F99_P_0_LEN_0, |
|
- | 884 | MOD_VEX_W_0_0F99_P_2_LEN_0, |
|
- | 885 | MOD_VEX_W_1_0F99_P_2_LEN_0, |
|
795 | MOD_VEX_0FAE_REG_2, |
886 | MOD_VEX_0FAE_REG_2, |
796 | MOD_VEX_0FAE_REG_3, |
887 | MOD_VEX_0FAE_REG_3, |
797 | MOD_VEX_0FD7_PREFIX_2, |
888 | MOD_VEX_0FD7_PREFIX_2, |
798 | MOD_VEX_0FE7_PREFIX_2, |
889 | MOD_VEX_0FE7_PREFIX_2, |
799 | MOD_VEX_0FF0_PREFIX_3, |
890 | MOD_VEX_0FF0_PREFIX_3, |
800 | MOD_VEX_0F381A_PREFIX_2, |
891 | MOD_VEX_0F381A_PREFIX_2, |
801 | MOD_VEX_0F382A_PREFIX_2, |
892 | MOD_VEX_0F382A_PREFIX_2, |
802 | MOD_VEX_0F382C_PREFIX_2, |
893 | MOD_VEX_0F382C_PREFIX_2, |
803 | MOD_VEX_0F382D_PREFIX_2, |
894 | MOD_VEX_0F382D_PREFIX_2, |
804 | MOD_VEX_0F382E_PREFIX_2, |
895 | MOD_VEX_0F382E_PREFIX_2, |
805 | MOD_VEX_0F382F_PREFIX_2, |
896 | MOD_VEX_0F382F_PREFIX_2, |
806 | MOD_VEX_0F385A_PREFIX_2, |
897 | MOD_VEX_0F385A_PREFIX_2, |
807 | MOD_VEX_0F388C_PREFIX_2, |
898 | MOD_VEX_0F388C_PREFIX_2, |
808 | MOD_VEX_0F388E_PREFIX_2, |
899 | MOD_VEX_0F388E_PREFIX_2, |
- | 900 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
|
- | 901 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, |
|
- | 902 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, |
|
- | 903 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, |
|
- | 904 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, |
|
- | 905 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, |
|
- | 906 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, |
|
- | 907 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, |
|
809 | 908 | ||
810 | MOD_EVEX_0F10_PREFIX_1, |
909 | MOD_EVEX_0F10_PREFIX_1, |
811 | MOD_EVEX_0F10_PREFIX_3, |
910 | MOD_EVEX_0F10_PREFIX_3, |
812 | MOD_EVEX_0F11_PREFIX_1, |
911 | MOD_EVEX_0F11_PREFIX_1, |
813 | MOD_EVEX_0F11_PREFIX_3, |
912 | MOD_EVEX_0F11_PREFIX_3, |
814 | MOD_EVEX_0F12_PREFIX_0, |
913 | MOD_EVEX_0F12_PREFIX_0, |
815 | MOD_EVEX_0F16_PREFIX_0, |
914 | MOD_EVEX_0F16_PREFIX_0, |
816 | MOD_EVEX_0F38C6_REG_1, |
915 | MOD_EVEX_0F38C6_REG_1, |
817 | MOD_EVEX_0F38C6_REG_2, |
916 | MOD_EVEX_0F38C6_REG_2, |
818 | MOD_EVEX_0F38C6_REG_5, |
917 | MOD_EVEX_0F38C6_REG_5, |
819 | MOD_EVEX_0F38C6_REG_6, |
918 | MOD_EVEX_0F38C6_REG_6, |
820 | MOD_EVEX_0F38C7_REG_1, |
919 | MOD_EVEX_0F38C7_REG_1, |
821 | MOD_EVEX_0F38C7_REG_2, |
920 | MOD_EVEX_0F38C7_REG_2, |
822 | MOD_EVEX_0F38C7_REG_5, |
921 | MOD_EVEX_0F38C7_REG_5, |
823 | MOD_EVEX_0F38C7_REG_6 |
922 | MOD_EVEX_0F38C7_REG_6 |
824 | }; |
923 | }; |
825 | 924 | ||
826 | enum |
925 | enum |
827 | { |
926 | { |
828 | RM_C6_REG_7 = 0, |
927 | RM_C6_REG_7 = 0, |
829 | RM_C7_REG_7, |
928 | RM_C7_REG_7, |
830 | RM_0F01_REG_0, |
929 | RM_0F01_REG_0, |
831 | RM_0F01_REG_1, |
930 | RM_0F01_REG_1, |
832 | RM_0F01_REG_2, |
931 | RM_0F01_REG_2, |
833 | RM_0F01_REG_3, |
932 | RM_0F01_REG_3, |
- | 933 | RM_0F01_REG_5, |
|
834 | RM_0F01_REG_7, |
934 | RM_0F01_REG_7, |
835 | RM_0FAE_REG_5, |
935 | RM_0FAE_REG_5, |
836 | RM_0FAE_REG_6, |
936 | RM_0FAE_REG_6, |
837 | RM_0FAE_REG_7 |
937 | RM_0FAE_REG_7 |
838 | }; |
938 | }; |
839 | 939 | ||
840 | enum |
940 | enum |
841 | { |
941 | { |
842 | PREFIX_90 = 0, |
942 | PREFIX_90 = 0, |
843 | PREFIX_0F10, |
943 | PREFIX_0F10, |
844 | PREFIX_0F11, |
944 | PREFIX_0F11, |
845 | PREFIX_0F12, |
945 | PREFIX_0F12, |
846 | PREFIX_0F16, |
946 | PREFIX_0F16, |
847 | PREFIX_0F1A, |
947 | PREFIX_0F1A, |
848 | PREFIX_0F1B, |
948 | PREFIX_0F1B, |
849 | PREFIX_0F2A, |
949 | PREFIX_0F2A, |
850 | PREFIX_0F2B, |
950 | PREFIX_0F2B, |
851 | PREFIX_0F2C, |
951 | PREFIX_0F2C, |
852 | PREFIX_0F2D, |
952 | PREFIX_0F2D, |
853 | PREFIX_0F2E, |
953 | PREFIX_0F2E, |
854 | PREFIX_0F2F, |
954 | PREFIX_0F2F, |
855 | PREFIX_0F51, |
955 | PREFIX_0F51, |
856 | PREFIX_0F52, |
956 | PREFIX_0F52, |
857 | PREFIX_0F53, |
957 | PREFIX_0F53, |
858 | PREFIX_0F58, |
958 | PREFIX_0F58, |
859 | PREFIX_0F59, |
959 | PREFIX_0F59, |
860 | PREFIX_0F5A, |
960 | PREFIX_0F5A, |
861 | PREFIX_0F5B, |
961 | PREFIX_0F5B, |
862 | PREFIX_0F5C, |
962 | PREFIX_0F5C, |
863 | PREFIX_0F5D, |
963 | PREFIX_0F5D, |
864 | PREFIX_0F5E, |
964 | PREFIX_0F5E, |
865 | PREFIX_0F5F, |
965 | PREFIX_0F5F, |
866 | PREFIX_0F60, |
966 | PREFIX_0F60, |
867 | PREFIX_0F61, |
967 | PREFIX_0F61, |
868 | PREFIX_0F62, |
968 | PREFIX_0F62, |
869 | PREFIX_0F6C, |
969 | PREFIX_0F6C, |
870 | PREFIX_0F6D, |
970 | PREFIX_0F6D, |
871 | PREFIX_0F6F, |
971 | PREFIX_0F6F, |
872 | PREFIX_0F70, |
972 | PREFIX_0F70, |
873 | PREFIX_0F73_REG_3, |
973 | PREFIX_0F73_REG_3, |
874 | PREFIX_0F73_REG_7, |
974 | PREFIX_0F73_REG_7, |
875 | PREFIX_0F78, |
975 | PREFIX_0F78, |
876 | PREFIX_0F79, |
976 | PREFIX_0F79, |
877 | PREFIX_0F7C, |
977 | PREFIX_0F7C, |
878 | PREFIX_0F7D, |
978 | PREFIX_0F7D, |
879 | PREFIX_0F7E, |
979 | PREFIX_0F7E, |
880 | PREFIX_0F7F, |
980 | PREFIX_0F7F, |
881 | PREFIX_0FAE_REG_0, |
981 | PREFIX_0FAE_REG_0, |
882 | PREFIX_0FAE_REG_1, |
982 | PREFIX_0FAE_REG_1, |
883 | PREFIX_0FAE_REG_2, |
983 | PREFIX_0FAE_REG_2, |
884 | PREFIX_0FAE_REG_3, |
984 | PREFIX_0FAE_REG_3, |
- | 985 | PREFIX_0FAE_REG_6, |
|
- | 986 | PREFIX_0FAE_REG_7, |
|
- | 987 | PREFIX_RM_0_0FAE_REG_7, |
|
885 | PREFIX_0FB8, |
988 | PREFIX_0FB8, |
886 | PREFIX_0FBC, |
989 | PREFIX_0FBC, |
887 | PREFIX_0FBD, |
990 | PREFIX_0FBD, |
888 | PREFIX_0FC2, |
991 | PREFIX_0FC2, |
889 | PREFIX_0FC3, |
992 | PREFIX_MOD_0_0FC3, |
- | 993 | PREFIX_MOD_0_0FC7_REG_6, |
|
890 | PREFIX_0FC7_REG_6, |
994 | PREFIX_MOD_3_0FC7_REG_6, |
- | 995 | PREFIX_MOD_3_0FC7_REG_7, |
|
891 | PREFIX_0FD0, |
996 | PREFIX_0FD0, |
892 | PREFIX_0FD6, |
997 | PREFIX_0FD6, |
893 | PREFIX_0FE6, |
998 | PREFIX_0FE6, |
894 | PREFIX_0FE7, |
999 | PREFIX_0FE7, |
895 | PREFIX_0FF0, |
1000 | PREFIX_0FF0, |
896 | PREFIX_0FF7, |
1001 | PREFIX_0FF7, |
897 | PREFIX_0F3810, |
1002 | PREFIX_0F3810, |
898 | PREFIX_0F3814, |
1003 | PREFIX_0F3814, |
899 | PREFIX_0F3815, |
1004 | PREFIX_0F3815, |
900 | PREFIX_0F3817, |
1005 | PREFIX_0F3817, |
901 | PREFIX_0F3820, |
1006 | PREFIX_0F3820, |
902 | PREFIX_0F3821, |
1007 | PREFIX_0F3821, |
903 | PREFIX_0F3822, |
1008 | PREFIX_0F3822, |
904 | PREFIX_0F3823, |
1009 | PREFIX_0F3823, |
905 | PREFIX_0F3824, |
1010 | PREFIX_0F3824, |
906 | PREFIX_0F3825, |
1011 | PREFIX_0F3825, |
907 | PREFIX_0F3828, |
1012 | PREFIX_0F3828, |
908 | PREFIX_0F3829, |
1013 | PREFIX_0F3829, |
909 | PREFIX_0F382A, |
1014 | PREFIX_0F382A, |
910 | PREFIX_0F382B, |
1015 | PREFIX_0F382B, |
911 | PREFIX_0F3830, |
1016 | PREFIX_0F3830, |
912 | PREFIX_0F3831, |
1017 | PREFIX_0F3831, |
913 | PREFIX_0F3832, |
1018 | PREFIX_0F3832, |
914 | PREFIX_0F3833, |
1019 | PREFIX_0F3833, |
915 | PREFIX_0F3834, |
1020 | PREFIX_0F3834, |
916 | PREFIX_0F3835, |
1021 | PREFIX_0F3835, |
917 | PREFIX_0F3837, |
1022 | PREFIX_0F3837, |
918 | PREFIX_0F3838, |
1023 | PREFIX_0F3838, |
919 | PREFIX_0F3839, |
1024 | PREFIX_0F3839, |
920 | PREFIX_0F383A, |
1025 | PREFIX_0F383A, |
921 | PREFIX_0F383B, |
1026 | PREFIX_0F383B, |
922 | PREFIX_0F383C, |
1027 | PREFIX_0F383C, |
923 | PREFIX_0F383D, |
1028 | PREFIX_0F383D, |
924 | PREFIX_0F383E, |
1029 | PREFIX_0F383E, |
925 | PREFIX_0F383F, |
1030 | PREFIX_0F383F, |
926 | PREFIX_0F3840, |
1031 | PREFIX_0F3840, |
927 | PREFIX_0F3841, |
1032 | PREFIX_0F3841, |
928 | PREFIX_0F3880, |
1033 | PREFIX_0F3880, |
929 | PREFIX_0F3881, |
1034 | PREFIX_0F3881, |
930 | PREFIX_0F3882, |
1035 | PREFIX_0F3882, |
931 | PREFIX_0F38C8, |
1036 | PREFIX_0F38C8, |
932 | PREFIX_0F38C9, |
1037 | PREFIX_0F38C9, |
933 | PREFIX_0F38CA, |
1038 | PREFIX_0F38CA, |
934 | PREFIX_0F38CB, |
1039 | PREFIX_0F38CB, |
935 | PREFIX_0F38CC, |
1040 | PREFIX_0F38CC, |
936 | PREFIX_0F38CD, |
1041 | PREFIX_0F38CD, |
937 | PREFIX_0F38DB, |
1042 | PREFIX_0F38DB, |
938 | PREFIX_0F38DC, |
1043 | PREFIX_0F38DC, |
939 | PREFIX_0F38DD, |
1044 | PREFIX_0F38DD, |
940 | PREFIX_0F38DE, |
1045 | PREFIX_0F38DE, |
941 | PREFIX_0F38DF, |
1046 | PREFIX_0F38DF, |
942 | PREFIX_0F38F0, |
1047 | PREFIX_0F38F0, |
943 | PREFIX_0F38F1, |
1048 | PREFIX_0F38F1, |
944 | PREFIX_0F38F6, |
1049 | PREFIX_0F38F6, |
945 | PREFIX_0F3A08, |
1050 | PREFIX_0F3A08, |
946 | PREFIX_0F3A09, |
1051 | PREFIX_0F3A09, |
947 | PREFIX_0F3A0A, |
1052 | PREFIX_0F3A0A, |
948 | PREFIX_0F3A0B, |
1053 | PREFIX_0F3A0B, |
949 | PREFIX_0F3A0C, |
1054 | PREFIX_0F3A0C, |
950 | PREFIX_0F3A0D, |
1055 | PREFIX_0F3A0D, |
951 | PREFIX_0F3A0E, |
1056 | PREFIX_0F3A0E, |
952 | PREFIX_0F3A14, |
1057 | PREFIX_0F3A14, |
953 | PREFIX_0F3A15, |
1058 | PREFIX_0F3A15, |
954 | PREFIX_0F3A16, |
1059 | PREFIX_0F3A16, |
955 | PREFIX_0F3A17, |
1060 | PREFIX_0F3A17, |
956 | PREFIX_0F3A20, |
1061 | PREFIX_0F3A20, |
957 | PREFIX_0F3A21, |
1062 | PREFIX_0F3A21, |
958 | PREFIX_0F3A22, |
1063 | PREFIX_0F3A22, |
959 | PREFIX_0F3A40, |
1064 | PREFIX_0F3A40, |
960 | PREFIX_0F3A41, |
1065 | PREFIX_0F3A41, |
961 | PREFIX_0F3A42, |
1066 | PREFIX_0F3A42, |
962 | PREFIX_0F3A44, |
1067 | PREFIX_0F3A44, |
963 | PREFIX_0F3A60, |
1068 | PREFIX_0F3A60, |
964 | PREFIX_0F3A61, |
1069 | PREFIX_0F3A61, |
965 | PREFIX_0F3A62, |
1070 | PREFIX_0F3A62, |
966 | PREFIX_0F3A63, |
1071 | PREFIX_0F3A63, |
967 | PREFIX_0F3ACC, |
1072 | PREFIX_0F3ACC, |
968 | PREFIX_0F3ADF, |
1073 | PREFIX_0F3ADF, |
969 | PREFIX_VEX_0F10, |
1074 | PREFIX_VEX_0F10, |
970 | PREFIX_VEX_0F11, |
1075 | PREFIX_VEX_0F11, |
971 | PREFIX_VEX_0F12, |
1076 | PREFIX_VEX_0F12, |
972 | PREFIX_VEX_0F16, |
1077 | PREFIX_VEX_0F16, |
973 | PREFIX_VEX_0F2A, |
1078 | PREFIX_VEX_0F2A, |
974 | PREFIX_VEX_0F2C, |
1079 | PREFIX_VEX_0F2C, |
975 | PREFIX_VEX_0F2D, |
1080 | PREFIX_VEX_0F2D, |
976 | PREFIX_VEX_0F2E, |
1081 | PREFIX_VEX_0F2E, |
977 | PREFIX_VEX_0F2F, |
1082 | PREFIX_VEX_0F2F, |
978 | PREFIX_VEX_0F41, |
1083 | PREFIX_VEX_0F41, |
979 | PREFIX_VEX_0F42, |
1084 | PREFIX_VEX_0F42, |
980 | PREFIX_VEX_0F44, |
1085 | PREFIX_VEX_0F44, |
981 | PREFIX_VEX_0F45, |
1086 | PREFIX_VEX_0F45, |
982 | PREFIX_VEX_0F46, |
1087 | PREFIX_VEX_0F46, |
983 | PREFIX_VEX_0F47, |
1088 | PREFIX_VEX_0F47, |
- | 1089 | PREFIX_VEX_0F4A, |
|
984 | PREFIX_VEX_0F4B, |
1090 | PREFIX_VEX_0F4B, |
985 | PREFIX_VEX_0F51, |
1091 | PREFIX_VEX_0F51, |
986 | PREFIX_VEX_0F52, |
1092 | PREFIX_VEX_0F52, |
987 | PREFIX_VEX_0F53, |
1093 | PREFIX_VEX_0F53, |
988 | PREFIX_VEX_0F58, |
1094 | PREFIX_VEX_0F58, |
989 | PREFIX_VEX_0F59, |
1095 | PREFIX_VEX_0F59, |
990 | PREFIX_VEX_0F5A, |
1096 | PREFIX_VEX_0F5A, |
991 | PREFIX_VEX_0F5B, |
1097 | PREFIX_VEX_0F5B, |
992 | PREFIX_VEX_0F5C, |
1098 | PREFIX_VEX_0F5C, |
993 | PREFIX_VEX_0F5D, |
1099 | PREFIX_VEX_0F5D, |
994 | PREFIX_VEX_0F5E, |
1100 | PREFIX_VEX_0F5E, |
995 | PREFIX_VEX_0F5F, |
1101 | PREFIX_VEX_0F5F, |
996 | PREFIX_VEX_0F60, |
1102 | PREFIX_VEX_0F60, |
997 | PREFIX_VEX_0F61, |
1103 | PREFIX_VEX_0F61, |
998 | PREFIX_VEX_0F62, |
1104 | PREFIX_VEX_0F62, |
999 | PREFIX_VEX_0F63, |
1105 | PREFIX_VEX_0F63, |
1000 | PREFIX_VEX_0F64, |
1106 | PREFIX_VEX_0F64, |
1001 | PREFIX_VEX_0F65, |
1107 | PREFIX_VEX_0F65, |
1002 | PREFIX_VEX_0F66, |
1108 | PREFIX_VEX_0F66, |
1003 | PREFIX_VEX_0F67, |
1109 | PREFIX_VEX_0F67, |
1004 | PREFIX_VEX_0F68, |
1110 | PREFIX_VEX_0F68, |
1005 | PREFIX_VEX_0F69, |
1111 | PREFIX_VEX_0F69, |
1006 | PREFIX_VEX_0F6A, |
1112 | PREFIX_VEX_0F6A, |
1007 | PREFIX_VEX_0F6B, |
1113 | PREFIX_VEX_0F6B, |
1008 | PREFIX_VEX_0F6C, |
1114 | PREFIX_VEX_0F6C, |
1009 | PREFIX_VEX_0F6D, |
1115 | PREFIX_VEX_0F6D, |
1010 | PREFIX_VEX_0F6E, |
1116 | PREFIX_VEX_0F6E, |
1011 | PREFIX_VEX_0F6F, |
1117 | PREFIX_VEX_0F6F, |
1012 | PREFIX_VEX_0F70, |
1118 | PREFIX_VEX_0F70, |
1013 | PREFIX_VEX_0F71_REG_2, |
1119 | PREFIX_VEX_0F71_REG_2, |
1014 | PREFIX_VEX_0F71_REG_4, |
1120 | PREFIX_VEX_0F71_REG_4, |
1015 | PREFIX_VEX_0F71_REG_6, |
1121 | PREFIX_VEX_0F71_REG_6, |
1016 | PREFIX_VEX_0F72_REG_2, |
1122 | PREFIX_VEX_0F72_REG_2, |
1017 | PREFIX_VEX_0F72_REG_4, |
1123 | PREFIX_VEX_0F72_REG_4, |
1018 | PREFIX_VEX_0F72_REG_6, |
1124 | PREFIX_VEX_0F72_REG_6, |
1019 | PREFIX_VEX_0F73_REG_2, |
1125 | PREFIX_VEX_0F73_REG_2, |
1020 | PREFIX_VEX_0F73_REG_3, |
1126 | PREFIX_VEX_0F73_REG_3, |
1021 | PREFIX_VEX_0F73_REG_6, |
1127 | PREFIX_VEX_0F73_REG_6, |
1022 | PREFIX_VEX_0F73_REG_7, |
1128 | PREFIX_VEX_0F73_REG_7, |
1023 | PREFIX_VEX_0F74, |
1129 | PREFIX_VEX_0F74, |
1024 | PREFIX_VEX_0F75, |
1130 | PREFIX_VEX_0F75, |
1025 | PREFIX_VEX_0F76, |
1131 | PREFIX_VEX_0F76, |
1026 | PREFIX_VEX_0F77, |
1132 | PREFIX_VEX_0F77, |
1027 | PREFIX_VEX_0F7C, |
1133 | PREFIX_VEX_0F7C, |
1028 | PREFIX_VEX_0F7D, |
1134 | PREFIX_VEX_0F7D, |
1029 | PREFIX_VEX_0F7E, |
1135 | PREFIX_VEX_0F7E, |
1030 | PREFIX_VEX_0F7F, |
1136 | PREFIX_VEX_0F7F, |
1031 | PREFIX_VEX_0F90, |
1137 | PREFIX_VEX_0F90, |
1032 | PREFIX_VEX_0F91, |
1138 | PREFIX_VEX_0F91, |
1033 | PREFIX_VEX_0F92, |
1139 | PREFIX_VEX_0F92, |
1034 | PREFIX_VEX_0F93, |
1140 | PREFIX_VEX_0F93, |
1035 | PREFIX_VEX_0F98, |
1141 | PREFIX_VEX_0F98, |
- | 1142 | PREFIX_VEX_0F99, |
|
1036 | PREFIX_VEX_0FC2, |
1143 | PREFIX_VEX_0FC2, |
1037 | PREFIX_VEX_0FC4, |
1144 | PREFIX_VEX_0FC4, |
1038 | PREFIX_VEX_0FC5, |
1145 | PREFIX_VEX_0FC5, |
1039 | PREFIX_VEX_0FD0, |
1146 | PREFIX_VEX_0FD0, |
1040 | PREFIX_VEX_0FD1, |
1147 | PREFIX_VEX_0FD1, |
1041 | PREFIX_VEX_0FD2, |
1148 | PREFIX_VEX_0FD2, |
1042 | PREFIX_VEX_0FD3, |
1149 | PREFIX_VEX_0FD3, |
1043 | PREFIX_VEX_0FD4, |
1150 | PREFIX_VEX_0FD4, |
1044 | PREFIX_VEX_0FD5, |
1151 | PREFIX_VEX_0FD5, |
1045 | PREFIX_VEX_0FD6, |
1152 | PREFIX_VEX_0FD6, |
1046 | PREFIX_VEX_0FD7, |
1153 | PREFIX_VEX_0FD7, |
1047 | PREFIX_VEX_0FD8, |
1154 | PREFIX_VEX_0FD8, |
1048 | PREFIX_VEX_0FD9, |
1155 | PREFIX_VEX_0FD9, |
1049 | PREFIX_VEX_0FDA, |
1156 | PREFIX_VEX_0FDA, |
1050 | PREFIX_VEX_0FDB, |
1157 | PREFIX_VEX_0FDB, |
1051 | PREFIX_VEX_0FDC, |
1158 | PREFIX_VEX_0FDC, |
1052 | PREFIX_VEX_0FDD, |
1159 | PREFIX_VEX_0FDD, |
1053 | PREFIX_VEX_0FDE, |
1160 | PREFIX_VEX_0FDE, |
1054 | PREFIX_VEX_0FDF, |
1161 | PREFIX_VEX_0FDF, |
1055 | PREFIX_VEX_0FE0, |
1162 | PREFIX_VEX_0FE0, |
1056 | PREFIX_VEX_0FE1, |
1163 | PREFIX_VEX_0FE1, |
1057 | PREFIX_VEX_0FE2, |
1164 | PREFIX_VEX_0FE2, |
1058 | PREFIX_VEX_0FE3, |
1165 | PREFIX_VEX_0FE3, |
1059 | PREFIX_VEX_0FE4, |
1166 | PREFIX_VEX_0FE4, |
1060 | PREFIX_VEX_0FE5, |
1167 | PREFIX_VEX_0FE5, |
1061 | PREFIX_VEX_0FE6, |
1168 | PREFIX_VEX_0FE6, |
1062 | PREFIX_VEX_0FE7, |
1169 | PREFIX_VEX_0FE7, |
1063 | PREFIX_VEX_0FE8, |
1170 | PREFIX_VEX_0FE8, |
1064 | PREFIX_VEX_0FE9, |
1171 | PREFIX_VEX_0FE9, |
1065 | PREFIX_VEX_0FEA, |
1172 | PREFIX_VEX_0FEA, |
1066 | PREFIX_VEX_0FEB, |
1173 | PREFIX_VEX_0FEB, |
1067 | PREFIX_VEX_0FEC, |
1174 | PREFIX_VEX_0FEC, |
1068 | PREFIX_VEX_0FED, |
1175 | PREFIX_VEX_0FED, |
1069 | PREFIX_VEX_0FEE, |
1176 | PREFIX_VEX_0FEE, |
1070 | PREFIX_VEX_0FEF, |
1177 | PREFIX_VEX_0FEF, |
1071 | PREFIX_VEX_0FF0, |
1178 | PREFIX_VEX_0FF0, |
1072 | PREFIX_VEX_0FF1, |
1179 | PREFIX_VEX_0FF1, |
1073 | PREFIX_VEX_0FF2, |
1180 | PREFIX_VEX_0FF2, |
1074 | PREFIX_VEX_0FF3, |
1181 | PREFIX_VEX_0FF3, |
1075 | PREFIX_VEX_0FF4, |
1182 | PREFIX_VEX_0FF4, |
1076 | PREFIX_VEX_0FF5, |
1183 | PREFIX_VEX_0FF5, |
1077 | PREFIX_VEX_0FF6, |
1184 | PREFIX_VEX_0FF6, |
1078 | PREFIX_VEX_0FF7, |
1185 | PREFIX_VEX_0FF7, |
1079 | PREFIX_VEX_0FF8, |
1186 | PREFIX_VEX_0FF8, |
1080 | PREFIX_VEX_0FF9, |
1187 | PREFIX_VEX_0FF9, |
1081 | PREFIX_VEX_0FFA, |
1188 | PREFIX_VEX_0FFA, |
1082 | PREFIX_VEX_0FFB, |
1189 | PREFIX_VEX_0FFB, |
1083 | PREFIX_VEX_0FFC, |
1190 | PREFIX_VEX_0FFC, |
1084 | PREFIX_VEX_0FFD, |
1191 | PREFIX_VEX_0FFD, |
1085 | PREFIX_VEX_0FFE, |
1192 | PREFIX_VEX_0FFE, |
1086 | PREFIX_VEX_0F3800, |
1193 | PREFIX_VEX_0F3800, |
1087 | PREFIX_VEX_0F3801, |
1194 | PREFIX_VEX_0F3801, |
1088 | PREFIX_VEX_0F3802, |
1195 | PREFIX_VEX_0F3802, |
1089 | PREFIX_VEX_0F3803, |
1196 | PREFIX_VEX_0F3803, |
1090 | PREFIX_VEX_0F3804, |
1197 | PREFIX_VEX_0F3804, |
1091 | PREFIX_VEX_0F3805, |
1198 | PREFIX_VEX_0F3805, |
1092 | PREFIX_VEX_0F3806, |
1199 | PREFIX_VEX_0F3806, |
1093 | PREFIX_VEX_0F3807, |
1200 | PREFIX_VEX_0F3807, |
1094 | PREFIX_VEX_0F3808, |
1201 | PREFIX_VEX_0F3808, |
1095 | PREFIX_VEX_0F3809, |
1202 | PREFIX_VEX_0F3809, |
1096 | PREFIX_VEX_0F380A, |
1203 | PREFIX_VEX_0F380A, |
1097 | PREFIX_VEX_0F380B, |
1204 | PREFIX_VEX_0F380B, |
1098 | PREFIX_VEX_0F380C, |
1205 | PREFIX_VEX_0F380C, |
1099 | PREFIX_VEX_0F380D, |
1206 | PREFIX_VEX_0F380D, |
1100 | PREFIX_VEX_0F380E, |
1207 | PREFIX_VEX_0F380E, |
1101 | PREFIX_VEX_0F380F, |
1208 | PREFIX_VEX_0F380F, |
1102 | PREFIX_VEX_0F3813, |
1209 | PREFIX_VEX_0F3813, |
1103 | PREFIX_VEX_0F3816, |
1210 | PREFIX_VEX_0F3816, |
1104 | PREFIX_VEX_0F3817, |
1211 | PREFIX_VEX_0F3817, |
1105 | PREFIX_VEX_0F3818, |
1212 | PREFIX_VEX_0F3818, |
1106 | PREFIX_VEX_0F3819, |
1213 | PREFIX_VEX_0F3819, |
1107 | PREFIX_VEX_0F381A, |
1214 | PREFIX_VEX_0F381A, |
1108 | PREFIX_VEX_0F381C, |
1215 | PREFIX_VEX_0F381C, |
1109 | PREFIX_VEX_0F381D, |
1216 | PREFIX_VEX_0F381D, |
1110 | PREFIX_VEX_0F381E, |
1217 | PREFIX_VEX_0F381E, |
1111 | PREFIX_VEX_0F3820, |
1218 | PREFIX_VEX_0F3820, |
1112 | PREFIX_VEX_0F3821, |
1219 | PREFIX_VEX_0F3821, |
1113 | PREFIX_VEX_0F3822, |
1220 | PREFIX_VEX_0F3822, |
1114 | PREFIX_VEX_0F3823, |
1221 | PREFIX_VEX_0F3823, |
1115 | PREFIX_VEX_0F3824, |
1222 | PREFIX_VEX_0F3824, |
1116 | PREFIX_VEX_0F3825, |
1223 | PREFIX_VEX_0F3825, |
1117 | PREFIX_VEX_0F3828, |
1224 | PREFIX_VEX_0F3828, |
1118 | PREFIX_VEX_0F3829, |
1225 | PREFIX_VEX_0F3829, |
1119 | PREFIX_VEX_0F382A, |
1226 | PREFIX_VEX_0F382A, |
1120 | PREFIX_VEX_0F382B, |
1227 | PREFIX_VEX_0F382B, |
1121 | PREFIX_VEX_0F382C, |
1228 | PREFIX_VEX_0F382C, |
1122 | PREFIX_VEX_0F382D, |
1229 | PREFIX_VEX_0F382D, |
1123 | PREFIX_VEX_0F382E, |
1230 | PREFIX_VEX_0F382E, |
1124 | PREFIX_VEX_0F382F, |
1231 | PREFIX_VEX_0F382F, |
1125 | PREFIX_VEX_0F3830, |
1232 | PREFIX_VEX_0F3830, |
1126 | PREFIX_VEX_0F3831, |
1233 | PREFIX_VEX_0F3831, |
1127 | PREFIX_VEX_0F3832, |
1234 | PREFIX_VEX_0F3832, |
1128 | PREFIX_VEX_0F3833, |
1235 | PREFIX_VEX_0F3833, |
1129 | PREFIX_VEX_0F3834, |
1236 | PREFIX_VEX_0F3834, |
1130 | PREFIX_VEX_0F3835, |
1237 | PREFIX_VEX_0F3835, |
1131 | PREFIX_VEX_0F3836, |
1238 | PREFIX_VEX_0F3836, |
1132 | PREFIX_VEX_0F3837, |
1239 | PREFIX_VEX_0F3837, |
1133 | PREFIX_VEX_0F3838, |
1240 | PREFIX_VEX_0F3838, |
1134 | PREFIX_VEX_0F3839, |
1241 | PREFIX_VEX_0F3839, |
1135 | PREFIX_VEX_0F383A, |
1242 | PREFIX_VEX_0F383A, |
1136 | PREFIX_VEX_0F383B, |
1243 | PREFIX_VEX_0F383B, |
1137 | PREFIX_VEX_0F383C, |
1244 | PREFIX_VEX_0F383C, |
1138 | PREFIX_VEX_0F383D, |
1245 | PREFIX_VEX_0F383D, |
1139 | PREFIX_VEX_0F383E, |
1246 | PREFIX_VEX_0F383E, |
1140 | PREFIX_VEX_0F383F, |
1247 | PREFIX_VEX_0F383F, |
1141 | PREFIX_VEX_0F3840, |
1248 | PREFIX_VEX_0F3840, |
1142 | PREFIX_VEX_0F3841, |
1249 | PREFIX_VEX_0F3841, |
1143 | PREFIX_VEX_0F3845, |
1250 | PREFIX_VEX_0F3845, |
1144 | PREFIX_VEX_0F3846, |
1251 | PREFIX_VEX_0F3846, |
1145 | PREFIX_VEX_0F3847, |
1252 | PREFIX_VEX_0F3847, |
1146 | PREFIX_VEX_0F3858, |
1253 | PREFIX_VEX_0F3858, |
1147 | PREFIX_VEX_0F3859, |
1254 | PREFIX_VEX_0F3859, |
1148 | PREFIX_VEX_0F385A, |
1255 | PREFIX_VEX_0F385A, |
1149 | PREFIX_VEX_0F3878, |
1256 | PREFIX_VEX_0F3878, |
1150 | PREFIX_VEX_0F3879, |
1257 | PREFIX_VEX_0F3879, |
1151 | PREFIX_VEX_0F388C, |
1258 | PREFIX_VEX_0F388C, |
1152 | PREFIX_VEX_0F388E, |
1259 | PREFIX_VEX_0F388E, |
1153 | PREFIX_VEX_0F3890, |
1260 | PREFIX_VEX_0F3890, |
1154 | PREFIX_VEX_0F3891, |
1261 | PREFIX_VEX_0F3891, |
1155 | PREFIX_VEX_0F3892, |
1262 | PREFIX_VEX_0F3892, |
1156 | PREFIX_VEX_0F3893, |
1263 | PREFIX_VEX_0F3893, |
1157 | PREFIX_VEX_0F3896, |
1264 | PREFIX_VEX_0F3896, |
1158 | PREFIX_VEX_0F3897, |
1265 | PREFIX_VEX_0F3897, |
1159 | PREFIX_VEX_0F3898, |
1266 | PREFIX_VEX_0F3898, |
1160 | PREFIX_VEX_0F3899, |
1267 | PREFIX_VEX_0F3899, |
1161 | PREFIX_VEX_0F389A, |
1268 | PREFIX_VEX_0F389A, |
1162 | PREFIX_VEX_0F389B, |
1269 | PREFIX_VEX_0F389B, |
1163 | PREFIX_VEX_0F389C, |
1270 | PREFIX_VEX_0F389C, |
1164 | PREFIX_VEX_0F389D, |
1271 | PREFIX_VEX_0F389D, |
1165 | PREFIX_VEX_0F389E, |
1272 | PREFIX_VEX_0F389E, |
1166 | PREFIX_VEX_0F389F, |
1273 | PREFIX_VEX_0F389F, |
1167 | PREFIX_VEX_0F38A6, |
1274 | PREFIX_VEX_0F38A6, |
1168 | PREFIX_VEX_0F38A7, |
1275 | PREFIX_VEX_0F38A7, |
1169 | PREFIX_VEX_0F38A8, |
1276 | PREFIX_VEX_0F38A8, |
1170 | PREFIX_VEX_0F38A9, |
1277 | PREFIX_VEX_0F38A9, |
1171 | PREFIX_VEX_0F38AA, |
1278 | PREFIX_VEX_0F38AA, |
1172 | PREFIX_VEX_0F38AB, |
1279 | PREFIX_VEX_0F38AB, |
1173 | PREFIX_VEX_0F38AC, |
1280 | PREFIX_VEX_0F38AC, |
1174 | PREFIX_VEX_0F38AD, |
1281 | PREFIX_VEX_0F38AD, |
1175 | PREFIX_VEX_0F38AE, |
1282 | PREFIX_VEX_0F38AE, |
1176 | PREFIX_VEX_0F38AF, |
1283 | PREFIX_VEX_0F38AF, |
1177 | PREFIX_VEX_0F38B6, |
1284 | PREFIX_VEX_0F38B6, |
1178 | PREFIX_VEX_0F38B7, |
1285 | PREFIX_VEX_0F38B7, |
1179 | PREFIX_VEX_0F38B8, |
1286 | PREFIX_VEX_0F38B8, |
1180 | PREFIX_VEX_0F38B9, |
1287 | PREFIX_VEX_0F38B9, |
1181 | PREFIX_VEX_0F38BA, |
1288 | PREFIX_VEX_0F38BA, |
1182 | PREFIX_VEX_0F38BB, |
1289 | PREFIX_VEX_0F38BB, |
1183 | PREFIX_VEX_0F38BC, |
1290 | PREFIX_VEX_0F38BC, |
1184 | PREFIX_VEX_0F38BD, |
1291 | PREFIX_VEX_0F38BD, |
1185 | PREFIX_VEX_0F38BE, |
1292 | PREFIX_VEX_0F38BE, |
1186 | PREFIX_VEX_0F38BF, |
1293 | PREFIX_VEX_0F38BF, |
1187 | PREFIX_VEX_0F38DB, |
1294 | PREFIX_VEX_0F38DB, |
1188 | PREFIX_VEX_0F38DC, |
1295 | PREFIX_VEX_0F38DC, |
1189 | PREFIX_VEX_0F38DD, |
1296 | PREFIX_VEX_0F38DD, |
1190 | PREFIX_VEX_0F38DE, |
1297 | PREFIX_VEX_0F38DE, |
1191 | PREFIX_VEX_0F38DF, |
1298 | PREFIX_VEX_0F38DF, |
1192 | PREFIX_VEX_0F38F2, |
1299 | PREFIX_VEX_0F38F2, |
1193 | PREFIX_VEX_0F38F3_REG_1, |
1300 | PREFIX_VEX_0F38F3_REG_1, |
1194 | PREFIX_VEX_0F38F3_REG_2, |
1301 | PREFIX_VEX_0F38F3_REG_2, |
1195 | PREFIX_VEX_0F38F3_REG_3, |
1302 | PREFIX_VEX_0F38F3_REG_3, |
1196 | PREFIX_VEX_0F38F5, |
1303 | PREFIX_VEX_0F38F5, |
1197 | PREFIX_VEX_0F38F6, |
1304 | PREFIX_VEX_0F38F6, |
1198 | PREFIX_VEX_0F38F7, |
1305 | PREFIX_VEX_0F38F7, |
1199 | PREFIX_VEX_0F3A00, |
1306 | PREFIX_VEX_0F3A00, |
1200 | PREFIX_VEX_0F3A01, |
1307 | PREFIX_VEX_0F3A01, |
1201 | PREFIX_VEX_0F3A02, |
1308 | PREFIX_VEX_0F3A02, |
1202 | PREFIX_VEX_0F3A04, |
1309 | PREFIX_VEX_0F3A04, |
1203 | PREFIX_VEX_0F3A05, |
1310 | PREFIX_VEX_0F3A05, |
1204 | PREFIX_VEX_0F3A06, |
1311 | PREFIX_VEX_0F3A06, |
1205 | PREFIX_VEX_0F3A08, |
1312 | PREFIX_VEX_0F3A08, |
1206 | PREFIX_VEX_0F3A09, |
1313 | PREFIX_VEX_0F3A09, |
1207 | PREFIX_VEX_0F3A0A, |
1314 | PREFIX_VEX_0F3A0A, |
1208 | PREFIX_VEX_0F3A0B, |
1315 | PREFIX_VEX_0F3A0B, |
1209 | PREFIX_VEX_0F3A0C, |
1316 | PREFIX_VEX_0F3A0C, |
1210 | PREFIX_VEX_0F3A0D, |
1317 | PREFIX_VEX_0F3A0D, |
1211 | PREFIX_VEX_0F3A0E, |
1318 | PREFIX_VEX_0F3A0E, |
1212 | PREFIX_VEX_0F3A0F, |
1319 | PREFIX_VEX_0F3A0F, |
1213 | PREFIX_VEX_0F3A14, |
1320 | PREFIX_VEX_0F3A14, |
1214 | PREFIX_VEX_0F3A15, |
1321 | PREFIX_VEX_0F3A15, |
1215 | PREFIX_VEX_0F3A16, |
1322 | PREFIX_VEX_0F3A16, |
1216 | PREFIX_VEX_0F3A17, |
1323 | PREFIX_VEX_0F3A17, |
1217 | PREFIX_VEX_0F3A18, |
1324 | PREFIX_VEX_0F3A18, |
1218 | PREFIX_VEX_0F3A19, |
1325 | PREFIX_VEX_0F3A19, |
1219 | PREFIX_VEX_0F3A1D, |
1326 | PREFIX_VEX_0F3A1D, |
1220 | PREFIX_VEX_0F3A20, |
1327 | PREFIX_VEX_0F3A20, |
1221 | PREFIX_VEX_0F3A21, |
1328 | PREFIX_VEX_0F3A21, |
1222 | PREFIX_VEX_0F3A22, |
1329 | PREFIX_VEX_0F3A22, |
1223 | PREFIX_VEX_0F3A30, |
1330 | PREFIX_VEX_0F3A30, |
- | 1331 | PREFIX_VEX_0F3A31, |
|
1224 | PREFIX_VEX_0F3A32, |
1332 | PREFIX_VEX_0F3A32, |
- | 1333 | PREFIX_VEX_0F3A33, |
|
1225 | PREFIX_VEX_0F3A38, |
1334 | PREFIX_VEX_0F3A38, |
1226 | PREFIX_VEX_0F3A39, |
1335 | PREFIX_VEX_0F3A39, |
1227 | PREFIX_VEX_0F3A40, |
1336 | PREFIX_VEX_0F3A40, |
1228 | PREFIX_VEX_0F3A41, |
1337 | PREFIX_VEX_0F3A41, |
1229 | PREFIX_VEX_0F3A42, |
1338 | PREFIX_VEX_0F3A42, |
1230 | PREFIX_VEX_0F3A44, |
1339 | PREFIX_VEX_0F3A44, |
1231 | PREFIX_VEX_0F3A46, |
1340 | PREFIX_VEX_0F3A46, |
1232 | PREFIX_VEX_0F3A48, |
1341 | PREFIX_VEX_0F3A48, |
1233 | PREFIX_VEX_0F3A49, |
1342 | PREFIX_VEX_0F3A49, |
1234 | PREFIX_VEX_0F3A4A, |
1343 | PREFIX_VEX_0F3A4A, |
1235 | PREFIX_VEX_0F3A4B, |
1344 | PREFIX_VEX_0F3A4B, |
1236 | PREFIX_VEX_0F3A4C, |
1345 | PREFIX_VEX_0F3A4C, |
1237 | PREFIX_VEX_0F3A5C, |
1346 | PREFIX_VEX_0F3A5C, |
1238 | PREFIX_VEX_0F3A5D, |
1347 | PREFIX_VEX_0F3A5D, |
1239 | PREFIX_VEX_0F3A5E, |
1348 | PREFIX_VEX_0F3A5E, |
1240 | PREFIX_VEX_0F3A5F, |
1349 | PREFIX_VEX_0F3A5F, |
1241 | PREFIX_VEX_0F3A60, |
1350 | PREFIX_VEX_0F3A60, |
1242 | PREFIX_VEX_0F3A61, |
1351 | PREFIX_VEX_0F3A61, |
1243 | PREFIX_VEX_0F3A62, |
1352 | PREFIX_VEX_0F3A62, |
1244 | PREFIX_VEX_0F3A63, |
1353 | PREFIX_VEX_0F3A63, |
1245 | PREFIX_VEX_0F3A68, |
1354 | PREFIX_VEX_0F3A68, |
1246 | PREFIX_VEX_0F3A69, |
1355 | PREFIX_VEX_0F3A69, |
1247 | PREFIX_VEX_0F3A6A, |
1356 | PREFIX_VEX_0F3A6A, |
1248 | PREFIX_VEX_0F3A6B, |
1357 | PREFIX_VEX_0F3A6B, |
1249 | PREFIX_VEX_0F3A6C, |
1358 | PREFIX_VEX_0F3A6C, |
1250 | PREFIX_VEX_0F3A6D, |
1359 | PREFIX_VEX_0F3A6D, |
1251 | PREFIX_VEX_0F3A6E, |
1360 | PREFIX_VEX_0F3A6E, |
1252 | PREFIX_VEX_0F3A6F, |
1361 | PREFIX_VEX_0F3A6F, |
1253 | PREFIX_VEX_0F3A78, |
1362 | PREFIX_VEX_0F3A78, |
1254 | PREFIX_VEX_0F3A79, |
1363 | PREFIX_VEX_0F3A79, |
1255 | PREFIX_VEX_0F3A7A, |
1364 | PREFIX_VEX_0F3A7A, |
1256 | PREFIX_VEX_0F3A7B, |
1365 | PREFIX_VEX_0F3A7B, |
1257 | PREFIX_VEX_0F3A7C, |
1366 | PREFIX_VEX_0F3A7C, |
1258 | PREFIX_VEX_0F3A7D, |
1367 | PREFIX_VEX_0F3A7D, |
1259 | PREFIX_VEX_0F3A7E, |
1368 | PREFIX_VEX_0F3A7E, |
1260 | PREFIX_VEX_0F3A7F, |
1369 | PREFIX_VEX_0F3A7F, |
1261 | PREFIX_VEX_0F3ADF, |
1370 | PREFIX_VEX_0F3ADF, |
1262 | PREFIX_VEX_0F3AF0, |
1371 | PREFIX_VEX_0F3AF0, |
1263 | 1372 | ||
1264 | PREFIX_EVEX_0F10, |
1373 | PREFIX_EVEX_0F10, |
1265 | PREFIX_EVEX_0F11, |
1374 | PREFIX_EVEX_0F11, |
1266 | PREFIX_EVEX_0F12, |
1375 | PREFIX_EVEX_0F12, |
1267 | PREFIX_EVEX_0F13, |
1376 | PREFIX_EVEX_0F13, |
1268 | PREFIX_EVEX_0F14, |
1377 | PREFIX_EVEX_0F14, |
1269 | PREFIX_EVEX_0F15, |
1378 | PREFIX_EVEX_0F15, |
1270 | PREFIX_EVEX_0F16, |
1379 | PREFIX_EVEX_0F16, |
1271 | PREFIX_EVEX_0F17, |
1380 | PREFIX_EVEX_0F17, |
1272 | PREFIX_EVEX_0F28, |
1381 | PREFIX_EVEX_0F28, |
1273 | PREFIX_EVEX_0F29, |
1382 | PREFIX_EVEX_0F29, |
1274 | PREFIX_EVEX_0F2A, |
1383 | PREFIX_EVEX_0F2A, |
1275 | PREFIX_EVEX_0F2B, |
1384 | PREFIX_EVEX_0F2B, |
1276 | PREFIX_EVEX_0F2C, |
1385 | PREFIX_EVEX_0F2C, |
1277 | PREFIX_EVEX_0F2D, |
1386 | PREFIX_EVEX_0F2D, |
1278 | PREFIX_EVEX_0F2E, |
1387 | PREFIX_EVEX_0F2E, |
1279 | PREFIX_EVEX_0F2F, |
1388 | PREFIX_EVEX_0F2F, |
1280 | PREFIX_EVEX_0F51, |
1389 | PREFIX_EVEX_0F51, |
- | 1390 | PREFIX_EVEX_0F54, |
|
- | 1391 | PREFIX_EVEX_0F55, |
|
- | 1392 | PREFIX_EVEX_0F56, |
|
- | 1393 | PREFIX_EVEX_0F57, |
|
1281 | PREFIX_EVEX_0F58, |
1394 | PREFIX_EVEX_0F58, |
1282 | PREFIX_EVEX_0F59, |
1395 | PREFIX_EVEX_0F59, |
1283 | PREFIX_EVEX_0F5A, |
1396 | PREFIX_EVEX_0F5A, |
1284 | PREFIX_EVEX_0F5B, |
1397 | PREFIX_EVEX_0F5B, |
1285 | PREFIX_EVEX_0F5C, |
1398 | PREFIX_EVEX_0F5C, |
1286 | PREFIX_EVEX_0F5D, |
1399 | PREFIX_EVEX_0F5D, |
1287 | PREFIX_EVEX_0F5E, |
1400 | PREFIX_EVEX_0F5E, |
1288 | PREFIX_EVEX_0F5F, |
1401 | PREFIX_EVEX_0F5F, |
- | 1402 | PREFIX_EVEX_0F60, |
|
- | 1403 | PREFIX_EVEX_0F61, |
|
1289 | PREFIX_EVEX_0F62, |
1404 | PREFIX_EVEX_0F62, |
- | 1405 | PREFIX_EVEX_0F63, |
|
- | 1406 | PREFIX_EVEX_0F64, |
|
- | 1407 | PREFIX_EVEX_0F65, |
|
1290 | PREFIX_EVEX_0F66, |
1408 | PREFIX_EVEX_0F66, |
- | 1409 | PREFIX_EVEX_0F67, |
|
- | 1410 | PREFIX_EVEX_0F68, |
|
- | 1411 | PREFIX_EVEX_0F69, |
|
1291 | PREFIX_EVEX_0F6A, |
1412 | PREFIX_EVEX_0F6A, |
- | 1413 | PREFIX_EVEX_0F6B, |
|
1292 | PREFIX_EVEX_0F6C, |
1414 | PREFIX_EVEX_0F6C, |
1293 | PREFIX_EVEX_0F6D, |
1415 | PREFIX_EVEX_0F6D, |
1294 | PREFIX_EVEX_0F6E, |
1416 | PREFIX_EVEX_0F6E, |
1295 | PREFIX_EVEX_0F6F, |
1417 | PREFIX_EVEX_0F6F, |
1296 | PREFIX_EVEX_0F70, |
1418 | PREFIX_EVEX_0F70, |
- | 1419 | PREFIX_EVEX_0F71_REG_2, |
|
- | 1420 | PREFIX_EVEX_0F71_REG_4, |
|
- | 1421 | PREFIX_EVEX_0F71_REG_6, |
|
1297 | PREFIX_EVEX_0F72_REG_0, |
1422 | PREFIX_EVEX_0F72_REG_0, |
1298 | PREFIX_EVEX_0F72_REG_1, |
1423 | PREFIX_EVEX_0F72_REG_1, |
1299 | PREFIX_EVEX_0F72_REG_2, |
1424 | PREFIX_EVEX_0F72_REG_2, |
1300 | PREFIX_EVEX_0F72_REG_4, |
1425 | PREFIX_EVEX_0F72_REG_4, |
1301 | PREFIX_EVEX_0F72_REG_6, |
1426 | PREFIX_EVEX_0F72_REG_6, |
1302 | PREFIX_EVEX_0F73_REG_2, |
1427 | PREFIX_EVEX_0F73_REG_2, |
- | 1428 | PREFIX_EVEX_0F73_REG_3, |
|
1303 | PREFIX_EVEX_0F73_REG_6, |
1429 | PREFIX_EVEX_0F73_REG_6, |
- | 1430 | PREFIX_EVEX_0F73_REG_7, |
|
- | 1431 | PREFIX_EVEX_0F74, |
|
- | 1432 | PREFIX_EVEX_0F75, |
|
1304 | PREFIX_EVEX_0F76, |
1433 | PREFIX_EVEX_0F76, |
1305 | PREFIX_EVEX_0F78, |
1434 | PREFIX_EVEX_0F78, |
1306 | PREFIX_EVEX_0F79, |
1435 | PREFIX_EVEX_0F79, |
1307 | PREFIX_EVEX_0F7A, |
1436 | PREFIX_EVEX_0F7A, |
1308 | PREFIX_EVEX_0F7B, |
1437 | PREFIX_EVEX_0F7B, |
1309 | PREFIX_EVEX_0F7E, |
1438 | PREFIX_EVEX_0F7E, |
1310 | PREFIX_EVEX_0F7F, |
1439 | PREFIX_EVEX_0F7F, |
1311 | PREFIX_EVEX_0FC2, |
1440 | PREFIX_EVEX_0FC2, |
- | 1441 | PREFIX_EVEX_0FC4, |
|
- | 1442 | PREFIX_EVEX_0FC5, |
|
1312 | PREFIX_EVEX_0FC6, |
1443 | PREFIX_EVEX_0FC6, |
- | 1444 | PREFIX_EVEX_0FD1, |
|
1313 | PREFIX_EVEX_0FD2, |
1445 | PREFIX_EVEX_0FD2, |
1314 | PREFIX_EVEX_0FD3, |
1446 | PREFIX_EVEX_0FD3, |
1315 | PREFIX_EVEX_0FD4, |
1447 | PREFIX_EVEX_0FD4, |
- | 1448 | PREFIX_EVEX_0FD5, |
|
1316 | PREFIX_EVEX_0FD6, |
1449 | PREFIX_EVEX_0FD6, |
- | 1450 | PREFIX_EVEX_0FD8, |
|
- | 1451 | PREFIX_EVEX_0FD9, |
|
- | 1452 | PREFIX_EVEX_0FDA, |
|
1317 | PREFIX_EVEX_0FDB, |
1453 | PREFIX_EVEX_0FDB, |
- | 1454 | PREFIX_EVEX_0FDC, |
|
- | 1455 | PREFIX_EVEX_0FDD, |
|
- | 1456 | PREFIX_EVEX_0FDE, |
|
1318 | PREFIX_EVEX_0FDF, |
1457 | PREFIX_EVEX_0FDF, |
- | 1458 | PREFIX_EVEX_0FE0, |
|
- | 1459 | PREFIX_EVEX_0FE1, |
|
1319 | PREFIX_EVEX_0FE2, |
1460 | PREFIX_EVEX_0FE2, |
- | 1461 | PREFIX_EVEX_0FE3, |
|
- | 1462 | PREFIX_EVEX_0FE4, |
|
- | 1463 | PREFIX_EVEX_0FE5, |
|
1320 | PREFIX_EVEX_0FE6, |
1464 | PREFIX_EVEX_0FE6, |
1321 | PREFIX_EVEX_0FE7, |
1465 | PREFIX_EVEX_0FE7, |
- | 1466 | PREFIX_EVEX_0FE8, |
|
- | 1467 | PREFIX_EVEX_0FE9, |
|
- | 1468 | PREFIX_EVEX_0FEA, |
|
1322 | PREFIX_EVEX_0FEB, |
1469 | PREFIX_EVEX_0FEB, |
- | 1470 | PREFIX_EVEX_0FEC, |
|
- | 1471 | PREFIX_EVEX_0FED, |
|
- | 1472 | PREFIX_EVEX_0FEE, |
|
1323 | PREFIX_EVEX_0FEF, |
1473 | PREFIX_EVEX_0FEF, |
- | 1474 | PREFIX_EVEX_0FF1, |
|
1324 | PREFIX_EVEX_0FF2, |
1475 | PREFIX_EVEX_0FF2, |
1325 | PREFIX_EVEX_0FF3, |
1476 | PREFIX_EVEX_0FF3, |
1326 | PREFIX_EVEX_0FF4, |
1477 | PREFIX_EVEX_0FF4, |
- | 1478 | PREFIX_EVEX_0FF5, |
|
- | 1479 | PREFIX_EVEX_0FF6, |
|
- | 1480 | PREFIX_EVEX_0FF8, |
|
- | 1481 | PREFIX_EVEX_0FF9, |
|
1327 | PREFIX_EVEX_0FFA, |
1482 | PREFIX_EVEX_0FFA, |
1328 | PREFIX_EVEX_0FFB, |
1483 | PREFIX_EVEX_0FFB, |
- | 1484 | PREFIX_EVEX_0FFC, |
|
- | 1485 | PREFIX_EVEX_0FFD, |
|
1329 | PREFIX_EVEX_0FFE, |
1486 | PREFIX_EVEX_0FFE, |
- | 1487 | PREFIX_EVEX_0F3800, |
|
- | 1488 | PREFIX_EVEX_0F3804, |
|
- | 1489 | PREFIX_EVEX_0F380B, |
|
1330 | PREFIX_EVEX_0F380C, |
1490 | PREFIX_EVEX_0F380C, |
1331 | PREFIX_EVEX_0F380D, |
1491 | PREFIX_EVEX_0F380D, |
- | 1492 | PREFIX_EVEX_0F3810, |
|
1332 | PREFIX_EVEX_0F3811, |
1493 | PREFIX_EVEX_0F3811, |
1333 | PREFIX_EVEX_0F3812, |
1494 | PREFIX_EVEX_0F3812, |
1334 | PREFIX_EVEX_0F3813, |
1495 | PREFIX_EVEX_0F3813, |
1335 | PREFIX_EVEX_0F3814, |
1496 | PREFIX_EVEX_0F3814, |
1336 | PREFIX_EVEX_0F3815, |
1497 | PREFIX_EVEX_0F3815, |
1337 | PREFIX_EVEX_0F3816, |
1498 | PREFIX_EVEX_0F3816, |
1338 | PREFIX_EVEX_0F3818, |
1499 | PREFIX_EVEX_0F3818, |
1339 | PREFIX_EVEX_0F3819, |
1500 | PREFIX_EVEX_0F3819, |
1340 | PREFIX_EVEX_0F381A, |
1501 | PREFIX_EVEX_0F381A, |
1341 | PREFIX_EVEX_0F381B, |
1502 | PREFIX_EVEX_0F381B, |
- | 1503 | PREFIX_EVEX_0F381C, |
|
- | 1504 | PREFIX_EVEX_0F381D, |
|
1342 | PREFIX_EVEX_0F381E, |
1505 | PREFIX_EVEX_0F381E, |
1343 | PREFIX_EVEX_0F381F, |
1506 | PREFIX_EVEX_0F381F, |
- | 1507 | PREFIX_EVEX_0F3820, |
|
1344 | PREFIX_EVEX_0F3821, |
1508 | PREFIX_EVEX_0F3821, |
1345 | PREFIX_EVEX_0F3822, |
1509 | PREFIX_EVEX_0F3822, |
1346 | PREFIX_EVEX_0F3823, |
1510 | PREFIX_EVEX_0F3823, |
1347 | PREFIX_EVEX_0F3824, |
1511 | PREFIX_EVEX_0F3824, |
1348 | PREFIX_EVEX_0F3825, |
1512 | PREFIX_EVEX_0F3825, |
- | 1513 | PREFIX_EVEX_0F3826, |
|
1349 | PREFIX_EVEX_0F3827, |
1514 | PREFIX_EVEX_0F3827, |
1350 | PREFIX_EVEX_0F3828, |
1515 | PREFIX_EVEX_0F3828, |
1351 | PREFIX_EVEX_0F3829, |
1516 | PREFIX_EVEX_0F3829, |
1352 | PREFIX_EVEX_0F382A, |
1517 | PREFIX_EVEX_0F382A, |
- | 1518 | PREFIX_EVEX_0F382B, |
|
1353 | PREFIX_EVEX_0F382C, |
1519 | PREFIX_EVEX_0F382C, |
1354 | PREFIX_EVEX_0F382D, |
1520 | PREFIX_EVEX_0F382D, |
- | 1521 | PREFIX_EVEX_0F3830, |
|
1355 | PREFIX_EVEX_0F3831, |
1522 | PREFIX_EVEX_0F3831, |
1356 | PREFIX_EVEX_0F3832, |
1523 | PREFIX_EVEX_0F3832, |
1357 | PREFIX_EVEX_0F3833, |
1524 | PREFIX_EVEX_0F3833, |
1358 | PREFIX_EVEX_0F3834, |
1525 | PREFIX_EVEX_0F3834, |
1359 | PREFIX_EVEX_0F3835, |
1526 | PREFIX_EVEX_0F3835, |
1360 | PREFIX_EVEX_0F3836, |
1527 | PREFIX_EVEX_0F3836, |
1361 | PREFIX_EVEX_0F3837, |
1528 | PREFIX_EVEX_0F3837, |
- | 1529 | PREFIX_EVEX_0F3838, |
|
1362 | PREFIX_EVEX_0F3839, |
1530 | PREFIX_EVEX_0F3839, |
1363 | PREFIX_EVEX_0F383A, |
1531 | PREFIX_EVEX_0F383A, |
1364 | PREFIX_EVEX_0F383B, |
1532 | PREFIX_EVEX_0F383B, |
- | 1533 | PREFIX_EVEX_0F383C, |
|
1365 | PREFIX_EVEX_0F383D, |
1534 | PREFIX_EVEX_0F383D, |
- | 1535 | PREFIX_EVEX_0F383E, |
|
1366 | PREFIX_EVEX_0F383F, |
1536 | PREFIX_EVEX_0F383F, |
1367 | PREFIX_EVEX_0F3840, |
1537 | PREFIX_EVEX_0F3840, |
1368 | PREFIX_EVEX_0F3842, |
1538 | PREFIX_EVEX_0F3842, |
1369 | PREFIX_EVEX_0F3843, |
1539 | PREFIX_EVEX_0F3843, |
1370 | PREFIX_EVEX_0F3844, |
1540 | PREFIX_EVEX_0F3844, |
1371 | PREFIX_EVEX_0F3845, |
1541 | PREFIX_EVEX_0F3845, |
1372 | PREFIX_EVEX_0F3846, |
1542 | PREFIX_EVEX_0F3846, |
1373 | PREFIX_EVEX_0F3847, |
1543 | PREFIX_EVEX_0F3847, |
1374 | PREFIX_EVEX_0F384C, |
1544 | PREFIX_EVEX_0F384C, |
1375 | PREFIX_EVEX_0F384D, |
1545 | PREFIX_EVEX_0F384D, |
1376 | PREFIX_EVEX_0F384E, |
1546 | PREFIX_EVEX_0F384E, |
1377 | PREFIX_EVEX_0F384F, |
1547 | PREFIX_EVEX_0F384F, |
1378 | PREFIX_EVEX_0F3858, |
1548 | PREFIX_EVEX_0F3858, |
1379 | PREFIX_EVEX_0F3859, |
1549 | PREFIX_EVEX_0F3859, |
1380 | PREFIX_EVEX_0F385A, |
1550 | PREFIX_EVEX_0F385A, |
1381 | PREFIX_EVEX_0F385B, |
1551 | PREFIX_EVEX_0F385B, |
1382 | PREFIX_EVEX_0F3864, |
1552 | PREFIX_EVEX_0F3864, |
1383 | PREFIX_EVEX_0F3865, |
1553 | PREFIX_EVEX_0F3865, |
- | 1554 | PREFIX_EVEX_0F3866, |
|
- | 1555 | PREFIX_EVEX_0F3875, |
|
1384 | PREFIX_EVEX_0F3876, |
1556 | PREFIX_EVEX_0F3876, |
1385 | PREFIX_EVEX_0F3877, |
1557 | PREFIX_EVEX_0F3877, |
- | 1558 | PREFIX_EVEX_0F3878, |
|
- | 1559 | PREFIX_EVEX_0F3879, |
|
- | 1560 | PREFIX_EVEX_0F387A, |
|
- | 1561 | PREFIX_EVEX_0F387B, |
|
1386 | PREFIX_EVEX_0F387C, |
1562 | PREFIX_EVEX_0F387C, |
- | 1563 | PREFIX_EVEX_0F387D, |
|
1387 | PREFIX_EVEX_0F387E, |
1564 | PREFIX_EVEX_0F387E, |
1388 | PREFIX_EVEX_0F387F, |
1565 | PREFIX_EVEX_0F387F, |
- | 1566 | PREFIX_EVEX_0F3883, |
|
1389 | PREFIX_EVEX_0F3888, |
1567 | PREFIX_EVEX_0F3888, |
1390 | PREFIX_EVEX_0F3889, |
1568 | PREFIX_EVEX_0F3889, |
1391 | PREFIX_EVEX_0F388A, |
1569 | PREFIX_EVEX_0F388A, |
1392 | PREFIX_EVEX_0F388B, |
1570 | PREFIX_EVEX_0F388B, |
- | 1571 | PREFIX_EVEX_0F388D, |
|
1393 | PREFIX_EVEX_0F3890, |
1572 | PREFIX_EVEX_0F3890, |
1394 | PREFIX_EVEX_0F3891, |
1573 | PREFIX_EVEX_0F3891, |
1395 | PREFIX_EVEX_0F3892, |
1574 | PREFIX_EVEX_0F3892, |
1396 | PREFIX_EVEX_0F3893, |
1575 | PREFIX_EVEX_0F3893, |
1397 | PREFIX_EVEX_0F3896, |
1576 | PREFIX_EVEX_0F3896, |
1398 | PREFIX_EVEX_0F3897, |
1577 | PREFIX_EVEX_0F3897, |
1399 | PREFIX_EVEX_0F3898, |
1578 | PREFIX_EVEX_0F3898, |
1400 | PREFIX_EVEX_0F3899, |
1579 | PREFIX_EVEX_0F3899, |
1401 | PREFIX_EVEX_0F389A, |
1580 | PREFIX_EVEX_0F389A, |
1402 | PREFIX_EVEX_0F389B, |
1581 | PREFIX_EVEX_0F389B, |
1403 | PREFIX_EVEX_0F389C, |
1582 | PREFIX_EVEX_0F389C, |
1404 | PREFIX_EVEX_0F389D, |
1583 | PREFIX_EVEX_0F389D, |
1405 | PREFIX_EVEX_0F389E, |
1584 | PREFIX_EVEX_0F389E, |
1406 | PREFIX_EVEX_0F389F, |
1585 | PREFIX_EVEX_0F389F, |
1407 | PREFIX_EVEX_0F38A0, |
1586 | PREFIX_EVEX_0F38A0, |
1408 | PREFIX_EVEX_0F38A1, |
1587 | PREFIX_EVEX_0F38A1, |
1409 | PREFIX_EVEX_0F38A2, |
1588 | PREFIX_EVEX_0F38A2, |
1410 | PREFIX_EVEX_0F38A3, |
1589 | PREFIX_EVEX_0F38A3, |
1411 | PREFIX_EVEX_0F38A6, |
1590 | PREFIX_EVEX_0F38A6, |
1412 | PREFIX_EVEX_0F38A7, |
1591 | PREFIX_EVEX_0F38A7, |
1413 | PREFIX_EVEX_0F38A8, |
1592 | PREFIX_EVEX_0F38A8, |
1414 | PREFIX_EVEX_0F38A9, |
1593 | PREFIX_EVEX_0F38A9, |
1415 | PREFIX_EVEX_0F38AA, |
1594 | PREFIX_EVEX_0F38AA, |
1416 | PREFIX_EVEX_0F38AB, |
1595 | PREFIX_EVEX_0F38AB, |
1417 | PREFIX_EVEX_0F38AC, |
1596 | PREFIX_EVEX_0F38AC, |
1418 | PREFIX_EVEX_0F38AD, |
1597 | PREFIX_EVEX_0F38AD, |
1419 | PREFIX_EVEX_0F38AE, |
1598 | PREFIX_EVEX_0F38AE, |
1420 | PREFIX_EVEX_0F38AF, |
1599 | PREFIX_EVEX_0F38AF, |
- | 1600 | PREFIX_EVEX_0F38B4, |
|
- | 1601 | PREFIX_EVEX_0F38B5, |
|
1421 | PREFIX_EVEX_0F38B6, |
1602 | PREFIX_EVEX_0F38B6, |
1422 | PREFIX_EVEX_0F38B7, |
1603 | PREFIX_EVEX_0F38B7, |
1423 | PREFIX_EVEX_0F38B8, |
1604 | PREFIX_EVEX_0F38B8, |
1424 | PREFIX_EVEX_0F38B9, |
1605 | PREFIX_EVEX_0F38B9, |
1425 | PREFIX_EVEX_0F38BA, |
1606 | PREFIX_EVEX_0F38BA, |
1426 | PREFIX_EVEX_0F38BB, |
1607 | PREFIX_EVEX_0F38BB, |
1427 | PREFIX_EVEX_0F38BC, |
1608 | PREFIX_EVEX_0F38BC, |
1428 | PREFIX_EVEX_0F38BD, |
1609 | PREFIX_EVEX_0F38BD, |
1429 | PREFIX_EVEX_0F38BE, |
1610 | PREFIX_EVEX_0F38BE, |
1430 | PREFIX_EVEX_0F38BF, |
1611 | PREFIX_EVEX_0F38BF, |
1431 | PREFIX_EVEX_0F38C4, |
1612 | PREFIX_EVEX_0F38C4, |
1432 | PREFIX_EVEX_0F38C6_REG_1, |
1613 | PREFIX_EVEX_0F38C6_REG_1, |
1433 | PREFIX_EVEX_0F38C6_REG_2, |
1614 | PREFIX_EVEX_0F38C6_REG_2, |
1434 | PREFIX_EVEX_0F38C6_REG_5, |
1615 | PREFIX_EVEX_0F38C6_REG_5, |
1435 | PREFIX_EVEX_0F38C6_REG_6, |
1616 | PREFIX_EVEX_0F38C6_REG_6, |
1436 | PREFIX_EVEX_0F38C7_REG_1, |
1617 | PREFIX_EVEX_0F38C7_REG_1, |
1437 | PREFIX_EVEX_0F38C7_REG_2, |
1618 | PREFIX_EVEX_0F38C7_REG_2, |
1438 | PREFIX_EVEX_0F38C7_REG_5, |
1619 | PREFIX_EVEX_0F38C7_REG_5, |
1439 | PREFIX_EVEX_0F38C7_REG_6, |
1620 | PREFIX_EVEX_0F38C7_REG_6, |
1440 | PREFIX_EVEX_0F38C8, |
1621 | PREFIX_EVEX_0F38C8, |
1441 | PREFIX_EVEX_0F38CA, |
1622 | PREFIX_EVEX_0F38CA, |
1442 | PREFIX_EVEX_0F38CB, |
1623 | PREFIX_EVEX_0F38CB, |
1443 | PREFIX_EVEX_0F38CC, |
1624 | PREFIX_EVEX_0F38CC, |
1444 | PREFIX_EVEX_0F38CD, |
1625 | PREFIX_EVEX_0F38CD, |
1445 | 1626 | ||
1446 | PREFIX_EVEX_0F3A00, |
1627 | PREFIX_EVEX_0F3A00, |
1447 | PREFIX_EVEX_0F3A01, |
1628 | PREFIX_EVEX_0F3A01, |
1448 | PREFIX_EVEX_0F3A03, |
1629 | PREFIX_EVEX_0F3A03, |
1449 | PREFIX_EVEX_0F3A04, |
1630 | PREFIX_EVEX_0F3A04, |
1450 | PREFIX_EVEX_0F3A05, |
1631 | PREFIX_EVEX_0F3A05, |
1451 | PREFIX_EVEX_0F3A08, |
1632 | PREFIX_EVEX_0F3A08, |
1452 | PREFIX_EVEX_0F3A09, |
1633 | PREFIX_EVEX_0F3A09, |
1453 | PREFIX_EVEX_0F3A0A, |
1634 | PREFIX_EVEX_0F3A0A, |
1454 | PREFIX_EVEX_0F3A0B, |
1635 | PREFIX_EVEX_0F3A0B, |
- | 1636 | PREFIX_EVEX_0F3A0F, |
|
- | 1637 | PREFIX_EVEX_0F3A14, |
|
- | 1638 | PREFIX_EVEX_0F3A15, |
|
- | 1639 | PREFIX_EVEX_0F3A16, |
|
1455 | PREFIX_EVEX_0F3A17, |
1640 | PREFIX_EVEX_0F3A17, |
1456 | PREFIX_EVEX_0F3A18, |
1641 | PREFIX_EVEX_0F3A18, |
1457 | PREFIX_EVEX_0F3A19, |
1642 | PREFIX_EVEX_0F3A19, |
1458 | PREFIX_EVEX_0F3A1A, |
1643 | PREFIX_EVEX_0F3A1A, |
1459 | PREFIX_EVEX_0F3A1B, |
1644 | PREFIX_EVEX_0F3A1B, |
1460 | PREFIX_EVEX_0F3A1D, |
1645 | PREFIX_EVEX_0F3A1D, |
1461 | PREFIX_EVEX_0F3A1E, |
1646 | PREFIX_EVEX_0F3A1E, |
1462 | PREFIX_EVEX_0F3A1F, |
1647 | PREFIX_EVEX_0F3A1F, |
- | 1648 | PREFIX_EVEX_0F3A20, |
|
1463 | PREFIX_EVEX_0F3A21, |
1649 | PREFIX_EVEX_0F3A21, |
- | 1650 | PREFIX_EVEX_0F3A22, |
|
1464 | PREFIX_EVEX_0F3A23, |
1651 | PREFIX_EVEX_0F3A23, |
1465 | PREFIX_EVEX_0F3A25, |
1652 | PREFIX_EVEX_0F3A25, |
1466 | PREFIX_EVEX_0F3A26, |
1653 | PREFIX_EVEX_0F3A26, |
1467 | PREFIX_EVEX_0F3A27, |
1654 | PREFIX_EVEX_0F3A27, |
1468 | PREFIX_EVEX_0F3A38, |
1655 | PREFIX_EVEX_0F3A38, |
1469 | PREFIX_EVEX_0F3A39, |
1656 | PREFIX_EVEX_0F3A39, |
1470 | PREFIX_EVEX_0F3A3A, |
1657 | PREFIX_EVEX_0F3A3A, |
1471 | PREFIX_EVEX_0F3A3B, |
1658 | PREFIX_EVEX_0F3A3B, |
- | 1659 | PREFIX_EVEX_0F3A3E, |
|
- | 1660 | PREFIX_EVEX_0F3A3F, |
|
- | 1661 | PREFIX_EVEX_0F3A42, |
|
1472 | PREFIX_EVEX_0F3A43, |
1662 | PREFIX_EVEX_0F3A43, |
- | 1663 | PREFIX_EVEX_0F3A50, |
|
- | 1664 | PREFIX_EVEX_0F3A51, |
|
1473 | PREFIX_EVEX_0F3A54, |
1665 | PREFIX_EVEX_0F3A54, |
1474 | PREFIX_EVEX_0F3A55, |
1666 | PREFIX_EVEX_0F3A55, |
- | 1667 | PREFIX_EVEX_0F3A56, |
|
- | 1668 | PREFIX_EVEX_0F3A57, |
|
- | 1669 | PREFIX_EVEX_0F3A66, |
|
- | 1670 | PREFIX_EVEX_0F3A67 |
|
1475 | }; |
1671 | }; |
1476 | 1672 | ||
1477 | enum |
1673 | enum |
1478 | { |
1674 | { |
1479 | X86_64_06 = 0, |
1675 | X86_64_06 = 0, |
1480 | X86_64_07, |
1676 | X86_64_07, |
1481 | X86_64_0D, |
1677 | X86_64_0D, |
1482 | X86_64_16, |
1678 | X86_64_16, |
1483 | X86_64_17, |
1679 | X86_64_17, |
1484 | X86_64_1E, |
1680 | X86_64_1E, |
1485 | X86_64_1F, |
1681 | X86_64_1F, |
1486 | X86_64_27, |
1682 | X86_64_27, |
1487 | X86_64_2F, |
1683 | X86_64_2F, |
1488 | X86_64_37, |
1684 | X86_64_37, |
1489 | X86_64_3F, |
1685 | X86_64_3F, |
1490 | X86_64_60, |
1686 | X86_64_60, |
1491 | X86_64_61, |
1687 | X86_64_61, |
1492 | X86_64_62, |
1688 | X86_64_62, |
1493 | X86_64_63, |
1689 | X86_64_63, |
1494 | X86_64_6D, |
1690 | X86_64_6D, |
1495 | X86_64_6F, |
1691 | X86_64_6F, |
1496 | X86_64_9A, |
1692 | X86_64_9A, |
1497 | X86_64_C4, |
1693 | X86_64_C4, |
1498 | X86_64_C5, |
1694 | X86_64_C5, |
1499 | X86_64_CE, |
1695 | X86_64_CE, |
1500 | X86_64_D4, |
1696 | X86_64_D4, |
1501 | X86_64_D5, |
1697 | X86_64_D5, |
- | 1698 | X86_64_E8, |
|
- | 1699 | X86_64_E9, |
|
1502 | X86_64_EA, |
1700 | X86_64_EA, |
1503 | X86_64_0F01_REG_0, |
1701 | X86_64_0F01_REG_0, |
1504 | X86_64_0F01_REG_1, |
1702 | X86_64_0F01_REG_1, |
1505 | X86_64_0F01_REG_2, |
1703 | X86_64_0F01_REG_2, |
1506 | X86_64_0F01_REG_3 |
1704 | X86_64_0F01_REG_3 |
1507 | }; |
1705 | }; |
1508 | 1706 | ||
1509 | enum |
1707 | enum |
1510 | { |
1708 | { |
1511 | THREE_BYTE_0F38 = 0, |
1709 | THREE_BYTE_0F38 = 0, |
1512 | THREE_BYTE_0F3A, |
1710 | THREE_BYTE_0F3A, |
1513 | THREE_BYTE_0F7A |
1711 | THREE_BYTE_0F7A |
1514 | }; |
1712 | }; |
1515 | 1713 | ||
1516 | enum |
1714 | enum |
1517 | { |
1715 | { |
1518 | XOP_08 = 0, |
1716 | XOP_08 = 0, |
1519 | XOP_09, |
1717 | XOP_09, |
1520 | XOP_0A |
1718 | XOP_0A |
1521 | }; |
1719 | }; |
1522 | 1720 | ||
1523 | enum |
1721 | enum |
1524 | { |
1722 | { |
1525 | VEX_0F = 0, |
1723 | VEX_0F = 0, |
1526 | VEX_0F38, |
1724 | VEX_0F38, |
1527 | VEX_0F3A |
1725 | VEX_0F3A |
1528 | }; |
1726 | }; |
1529 | 1727 | ||
1530 | enum |
1728 | enum |
1531 | { |
1729 | { |
1532 | EVEX_0F = 0, |
1730 | EVEX_0F = 0, |
1533 | EVEX_0F38, |
1731 | EVEX_0F38, |
1534 | EVEX_0F3A |
1732 | EVEX_0F3A |
1535 | }; |
1733 | }; |
1536 | 1734 | ||
1537 | enum |
1735 | enum |
1538 | { |
1736 | { |
1539 | VEX_LEN_0F10_P_1 = 0, |
1737 | VEX_LEN_0F10_P_1 = 0, |
1540 | VEX_LEN_0F10_P_3, |
1738 | VEX_LEN_0F10_P_3, |
1541 | VEX_LEN_0F11_P_1, |
1739 | VEX_LEN_0F11_P_1, |
1542 | VEX_LEN_0F11_P_3, |
1740 | VEX_LEN_0F11_P_3, |
1543 | VEX_LEN_0F12_P_0_M_0, |
1741 | VEX_LEN_0F12_P_0_M_0, |
1544 | VEX_LEN_0F12_P_0_M_1, |
1742 | VEX_LEN_0F12_P_0_M_1, |
1545 | VEX_LEN_0F12_P_2, |
1743 | VEX_LEN_0F12_P_2, |
1546 | VEX_LEN_0F13_M_0, |
1744 | VEX_LEN_0F13_M_0, |
1547 | VEX_LEN_0F16_P_0_M_0, |
1745 | VEX_LEN_0F16_P_0_M_0, |
1548 | VEX_LEN_0F16_P_0_M_1, |
1746 | VEX_LEN_0F16_P_0_M_1, |
1549 | VEX_LEN_0F16_P_2, |
1747 | VEX_LEN_0F16_P_2, |
1550 | VEX_LEN_0F17_M_0, |
1748 | VEX_LEN_0F17_M_0, |
1551 | VEX_LEN_0F2A_P_1, |
1749 | VEX_LEN_0F2A_P_1, |
1552 | VEX_LEN_0F2A_P_3, |
1750 | VEX_LEN_0F2A_P_3, |
1553 | VEX_LEN_0F2C_P_1, |
1751 | VEX_LEN_0F2C_P_1, |
1554 | VEX_LEN_0F2C_P_3, |
1752 | VEX_LEN_0F2C_P_3, |
1555 | VEX_LEN_0F2D_P_1, |
1753 | VEX_LEN_0F2D_P_1, |
1556 | VEX_LEN_0F2D_P_3, |
1754 | VEX_LEN_0F2D_P_3, |
1557 | VEX_LEN_0F2E_P_0, |
1755 | VEX_LEN_0F2E_P_0, |
1558 | VEX_LEN_0F2E_P_2, |
1756 | VEX_LEN_0F2E_P_2, |
1559 | VEX_LEN_0F2F_P_0, |
1757 | VEX_LEN_0F2F_P_0, |
1560 | VEX_LEN_0F2F_P_2, |
1758 | VEX_LEN_0F2F_P_2, |
1561 | VEX_LEN_0F41_P_0, |
1759 | VEX_LEN_0F41_P_0, |
- | 1760 | VEX_LEN_0F41_P_2, |
|
1562 | VEX_LEN_0F42_P_0, |
1761 | VEX_LEN_0F42_P_0, |
- | 1762 | VEX_LEN_0F42_P_2, |
|
1563 | VEX_LEN_0F44_P_0, |
1763 | VEX_LEN_0F44_P_0, |
- | 1764 | VEX_LEN_0F44_P_2, |
|
1564 | VEX_LEN_0F45_P_0, |
1765 | VEX_LEN_0F45_P_0, |
- | 1766 | VEX_LEN_0F45_P_2, |
|
1565 | VEX_LEN_0F46_P_0, |
1767 | VEX_LEN_0F46_P_0, |
- | 1768 | VEX_LEN_0F46_P_2, |
|
1566 | VEX_LEN_0F47_P_0, |
1769 | VEX_LEN_0F47_P_0, |
- | 1770 | VEX_LEN_0F47_P_2, |
|
- | 1771 | VEX_LEN_0F4A_P_0, |
|
- | 1772 | VEX_LEN_0F4A_P_2, |
|
- | 1773 | VEX_LEN_0F4B_P_0, |
|
1567 | VEX_LEN_0F4B_P_2, |
1774 | VEX_LEN_0F4B_P_2, |
1568 | VEX_LEN_0F51_P_1, |
1775 | VEX_LEN_0F51_P_1, |
1569 | VEX_LEN_0F51_P_3, |
1776 | VEX_LEN_0F51_P_3, |
1570 | VEX_LEN_0F52_P_1, |
1777 | VEX_LEN_0F52_P_1, |
1571 | VEX_LEN_0F53_P_1, |
1778 | VEX_LEN_0F53_P_1, |
1572 | VEX_LEN_0F58_P_1, |
1779 | VEX_LEN_0F58_P_1, |
1573 | VEX_LEN_0F58_P_3, |
1780 | VEX_LEN_0F58_P_3, |
1574 | VEX_LEN_0F59_P_1, |
1781 | VEX_LEN_0F59_P_1, |
1575 | VEX_LEN_0F59_P_3, |
1782 | VEX_LEN_0F59_P_3, |
1576 | VEX_LEN_0F5A_P_1, |
1783 | VEX_LEN_0F5A_P_1, |
1577 | VEX_LEN_0F5A_P_3, |
1784 | VEX_LEN_0F5A_P_3, |
1578 | VEX_LEN_0F5C_P_1, |
1785 | VEX_LEN_0F5C_P_1, |
1579 | VEX_LEN_0F5C_P_3, |
1786 | VEX_LEN_0F5C_P_3, |
1580 | VEX_LEN_0F5D_P_1, |
1787 | VEX_LEN_0F5D_P_1, |
1581 | VEX_LEN_0F5D_P_3, |
1788 | VEX_LEN_0F5D_P_3, |
1582 | VEX_LEN_0F5E_P_1, |
1789 | VEX_LEN_0F5E_P_1, |
1583 | VEX_LEN_0F5E_P_3, |
1790 | VEX_LEN_0F5E_P_3, |
1584 | VEX_LEN_0F5F_P_1, |
1791 | VEX_LEN_0F5F_P_1, |
1585 | VEX_LEN_0F5F_P_3, |
1792 | VEX_LEN_0F5F_P_3, |
1586 | VEX_LEN_0F6E_P_2, |
1793 | VEX_LEN_0F6E_P_2, |
1587 | VEX_LEN_0F7E_P_1, |
1794 | VEX_LEN_0F7E_P_1, |
1588 | VEX_LEN_0F7E_P_2, |
1795 | VEX_LEN_0F7E_P_2, |
1589 | VEX_LEN_0F90_P_0, |
1796 | VEX_LEN_0F90_P_0, |
- | 1797 | VEX_LEN_0F90_P_2, |
|
1590 | VEX_LEN_0F91_P_0, |
1798 | VEX_LEN_0F91_P_0, |
- | 1799 | VEX_LEN_0F91_P_2, |
|
1591 | VEX_LEN_0F92_P_0, |
1800 | VEX_LEN_0F92_P_0, |
- | 1801 | VEX_LEN_0F92_P_2, |
|
- | 1802 | VEX_LEN_0F92_P_3, |
|
1592 | VEX_LEN_0F93_P_0, |
1803 | VEX_LEN_0F93_P_0, |
- | 1804 | VEX_LEN_0F93_P_2, |
|
- | 1805 | VEX_LEN_0F93_P_3, |
|
1593 | VEX_LEN_0F98_P_0, |
1806 | VEX_LEN_0F98_P_0, |
- | 1807 | VEX_LEN_0F98_P_2, |
|
- | 1808 | VEX_LEN_0F99_P_0, |
|
- | 1809 | VEX_LEN_0F99_P_2, |
|
1594 | VEX_LEN_0FAE_R_2_M_0, |
1810 | VEX_LEN_0FAE_R_2_M_0, |
1595 | VEX_LEN_0FAE_R_3_M_0, |
1811 | VEX_LEN_0FAE_R_3_M_0, |
1596 | VEX_LEN_0FC2_P_1, |
1812 | VEX_LEN_0FC2_P_1, |
1597 | VEX_LEN_0FC2_P_3, |
1813 | VEX_LEN_0FC2_P_3, |
1598 | VEX_LEN_0FC4_P_2, |
1814 | VEX_LEN_0FC4_P_2, |
1599 | VEX_LEN_0FC5_P_2, |
1815 | VEX_LEN_0FC5_P_2, |
1600 | VEX_LEN_0FD6_P_2, |
1816 | VEX_LEN_0FD6_P_2, |
1601 | VEX_LEN_0FF7_P_2, |
1817 | VEX_LEN_0FF7_P_2, |
1602 | VEX_LEN_0F3816_P_2, |
1818 | VEX_LEN_0F3816_P_2, |
1603 | VEX_LEN_0F3819_P_2, |
1819 | VEX_LEN_0F3819_P_2, |
1604 | VEX_LEN_0F381A_P_2_M_0, |
1820 | VEX_LEN_0F381A_P_2_M_0, |
1605 | VEX_LEN_0F3836_P_2, |
1821 | VEX_LEN_0F3836_P_2, |
1606 | VEX_LEN_0F3841_P_2, |
1822 | VEX_LEN_0F3841_P_2, |
1607 | VEX_LEN_0F385A_P_2_M_0, |
1823 | VEX_LEN_0F385A_P_2_M_0, |
1608 | VEX_LEN_0F38DB_P_2, |
1824 | VEX_LEN_0F38DB_P_2, |
1609 | VEX_LEN_0F38DC_P_2, |
1825 | VEX_LEN_0F38DC_P_2, |
1610 | VEX_LEN_0F38DD_P_2, |
1826 | VEX_LEN_0F38DD_P_2, |
1611 | VEX_LEN_0F38DE_P_2, |
1827 | VEX_LEN_0F38DE_P_2, |
1612 | VEX_LEN_0F38DF_P_2, |
1828 | VEX_LEN_0F38DF_P_2, |
1613 | VEX_LEN_0F38F2_P_0, |
1829 | VEX_LEN_0F38F2_P_0, |
1614 | VEX_LEN_0F38F3_R_1_P_0, |
1830 | VEX_LEN_0F38F3_R_1_P_0, |
1615 | VEX_LEN_0F38F3_R_2_P_0, |
1831 | VEX_LEN_0F38F3_R_2_P_0, |
1616 | VEX_LEN_0F38F3_R_3_P_0, |
1832 | VEX_LEN_0F38F3_R_3_P_0, |
1617 | VEX_LEN_0F38F5_P_0, |
1833 | VEX_LEN_0F38F5_P_0, |
1618 | VEX_LEN_0F38F5_P_1, |
1834 | VEX_LEN_0F38F5_P_1, |
1619 | VEX_LEN_0F38F5_P_3, |
1835 | VEX_LEN_0F38F5_P_3, |
1620 | VEX_LEN_0F38F6_P_3, |
1836 | VEX_LEN_0F38F6_P_3, |
1621 | VEX_LEN_0F38F7_P_0, |
1837 | VEX_LEN_0F38F7_P_0, |
1622 | VEX_LEN_0F38F7_P_1, |
1838 | VEX_LEN_0F38F7_P_1, |
1623 | VEX_LEN_0F38F7_P_2, |
1839 | VEX_LEN_0F38F7_P_2, |
1624 | VEX_LEN_0F38F7_P_3, |
1840 | VEX_LEN_0F38F7_P_3, |
1625 | VEX_LEN_0F3A00_P_2, |
1841 | VEX_LEN_0F3A00_P_2, |
1626 | VEX_LEN_0F3A01_P_2, |
1842 | VEX_LEN_0F3A01_P_2, |
1627 | VEX_LEN_0F3A06_P_2, |
1843 | VEX_LEN_0F3A06_P_2, |
1628 | VEX_LEN_0F3A0A_P_2, |
1844 | VEX_LEN_0F3A0A_P_2, |
1629 | VEX_LEN_0F3A0B_P_2, |
1845 | VEX_LEN_0F3A0B_P_2, |
1630 | VEX_LEN_0F3A14_P_2, |
1846 | VEX_LEN_0F3A14_P_2, |
1631 | VEX_LEN_0F3A15_P_2, |
1847 | VEX_LEN_0F3A15_P_2, |
1632 | VEX_LEN_0F3A16_P_2, |
1848 | VEX_LEN_0F3A16_P_2, |
1633 | VEX_LEN_0F3A17_P_2, |
1849 | VEX_LEN_0F3A17_P_2, |
1634 | VEX_LEN_0F3A18_P_2, |
1850 | VEX_LEN_0F3A18_P_2, |
1635 | VEX_LEN_0F3A19_P_2, |
1851 | VEX_LEN_0F3A19_P_2, |
1636 | VEX_LEN_0F3A20_P_2, |
1852 | VEX_LEN_0F3A20_P_2, |
1637 | VEX_LEN_0F3A21_P_2, |
1853 | VEX_LEN_0F3A21_P_2, |
1638 | VEX_LEN_0F3A22_P_2, |
1854 | VEX_LEN_0F3A22_P_2, |
1639 | VEX_LEN_0F3A30_P_2, |
1855 | VEX_LEN_0F3A30_P_2, |
- | 1856 | VEX_LEN_0F3A31_P_2, |
|
1640 | VEX_LEN_0F3A32_P_2, |
1857 | VEX_LEN_0F3A32_P_2, |
- | 1858 | VEX_LEN_0F3A33_P_2, |
|
1641 | VEX_LEN_0F3A38_P_2, |
1859 | VEX_LEN_0F3A38_P_2, |
1642 | VEX_LEN_0F3A39_P_2, |
1860 | VEX_LEN_0F3A39_P_2, |
1643 | VEX_LEN_0F3A41_P_2, |
1861 | VEX_LEN_0F3A41_P_2, |
1644 | VEX_LEN_0F3A44_P_2, |
1862 | VEX_LEN_0F3A44_P_2, |
1645 | VEX_LEN_0F3A46_P_2, |
1863 | VEX_LEN_0F3A46_P_2, |
1646 | VEX_LEN_0F3A60_P_2, |
1864 | VEX_LEN_0F3A60_P_2, |
1647 | VEX_LEN_0F3A61_P_2, |
1865 | VEX_LEN_0F3A61_P_2, |
1648 | VEX_LEN_0F3A62_P_2, |
1866 | VEX_LEN_0F3A62_P_2, |
1649 | VEX_LEN_0F3A63_P_2, |
1867 | VEX_LEN_0F3A63_P_2, |
1650 | VEX_LEN_0F3A6A_P_2, |
1868 | VEX_LEN_0F3A6A_P_2, |
1651 | VEX_LEN_0F3A6B_P_2, |
1869 | VEX_LEN_0F3A6B_P_2, |
1652 | VEX_LEN_0F3A6E_P_2, |
1870 | VEX_LEN_0F3A6E_P_2, |
1653 | VEX_LEN_0F3A6F_P_2, |
1871 | VEX_LEN_0F3A6F_P_2, |
1654 | VEX_LEN_0F3A7A_P_2, |
1872 | VEX_LEN_0F3A7A_P_2, |
1655 | VEX_LEN_0F3A7B_P_2, |
1873 | VEX_LEN_0F3A7B_P_2, |
1656 | VEX_LEN_0F3A7E_P_2, |
1874 | VEX_LEN_0F3A7E_P_2, |
1657 | VEX_LEN_0F3A7F_P_2, |
1875 | VEX_LEN_0F3A7F_P_2, |
1658 | VEX_LEN_0F3ADF_P_2, |
1876 | VEX_LEN_0F3ADF_P_2, |
1659 | VEX_LEN_0F3AF0_P_3, |
1877 | VEX_LEN_0F3AF0_P_3, |
1660 | VEX_LEN_0FXOP_08_CC, |
1878 | VEX_LEN_0FXOP_08_CC, |
1661 | VEX_LEN_0FXOP_08_CD, |
1879 | VEX_LEN_0FXOP_08_CD, |
1662 | VEX_LEN_0FXOP_08_CE, |
1880 | VEX_LEN_0FXOP_08_CE, |
1663 | VEX_LEN_0FXOP_08_CF, |
1881 | VEX_LEN_0FXOP_08_CF, |
1664 | VEX_LEN_0FXOP_08_EC, |
1882 | VEX_LEN_0FXOP_08_EC, |
1665 | VEX_LEN_0FXOP_08_ED, |
1883 | VEX_LEN_0FXOP_08_ED, |
1666 | VEX_LEN_0FXOP_08_EE, |
1884 | VEX_LEN_0FXOP_08_EE, |
1667 | VEX_LEN_0FXOP_08_EF, |
1885 | VEX_LEN_0FXOP_08_EF, |
1668 | VEX_LEN_0FXOP_09_80, |
1886 | VEX_LEN_0FXOP_09_80, |
1669 | VEX_LEN_0FXOP_09_81 |
1887 | VEX_LEN_0FXOP_09_81 |
1670 | }; |
1888 | }; |
1671 | 1889 | ||
1672 | enum |
1890 | enum |
1673 | { |
1891 | { |
1674 | VEX_W_0F10_P_0 = 0, |
1892 | VEX_W_0F10_P_0 = 0, |
1675 | VEX_W_0F10_P_1, |
1893 | VEX_W_0F10_P_1, |
1676 | VEX_W_0F10_P_2, |
1894 | VEX_W_0F10_P_2, |
1677 | VEX_W_0F10_P_3, |
1895 | VEX_W_0F10_P_3, |
1678 | VEX_W_0F11_P_0, |
1896 | VEX_W_0F11_P_0, |
1679 | VEX_W_0F11_P_1, |
1897 | VEX_W_0F11_P_1, |
1680 | VEX_W_0F11_P_2, |
1898 | VEX_W_0F11_P_2, |
1681 | VEX_W_0F11_P_3, |
1899 | VEX_W_0F11_P_3, |
1682 | VEX_W_0F12_P_0_M_0, |
1900 | VEX_W_0F12_P_0_M_0, |
1683 | VEX_W_0F12_P_0_M_1, |
1901 | VEX_W_0F12_P_0_M_1, |
1684 | VEX_W_0F12_P_1, |
1902 | VEX_W_0F12_P_1, |
1685 | VEX_W_0F12_P_2, |
1903 | VEX_W_0F12_P_2, |
1686 | VEX_W_0F12_P_3, |
1904 | VEX_W_0F12_P_3, |
1687 | VEX_W_0F13_M_0, |
1905 | VEX_W_0F13_M_0, |
1688 | VEX_W_0F14, |
1906 | VEX_W_0F14, |
1689 | VEX_W_0F15, |
1907 | VEX_W_0F15, |
1690 | VEX_W_0F16_P_0_M_0, |
1908 | VEX_W_0F16_P_0_M_0, |
1691 | VEX_W_0F16_P_0_M_1, |
1909 | VEX_W_0F16_P_0_M_1, |
1692 | VEX_W_0F16_P_1, |
1910 | VEX_W_0F16_P_1, |
1693 | VEX_W_0F16_P_2, |
1911 | VEX_W_0F16_P_2, |
1694 | VEX_W_0F17_M_0, |
1912 | VEX_W_0F17_M_0, |
1695 | VEX_W_0F28, |
1913 | VEX_W_0F28, |
1696 | VEX_W_0F29, |
1914 | VEX_W_0F29, |
1697 | VEX_W_0F2B_M_0, |
1915 | VEX_W_0F2B_M_0, |
1698 | VEX_W_0F2E_P_0, |
1916 | VEX_W_0F2E_P_0, |
1699 | VEX_W_0F2E_P_2, |
1917 | VEX_W_0F2E_P_2, |
1700 | VEX_W_0F2F_P_0, |
1918 | VEX_W_0F2F_P_0, |
1701 | VEX_W_0F2F_P_2, |
1919 | VEX_W_0F2F_P_2, |
1702 | VEX_W_0F41_P_0_LEN_1, |
1920 | VEX_W_0F41_P_0_LEN_1, |
- | 1921 | VEX_W_0F41_P_2_LEN_1, |
|
1703 | VEX_W_0F42_P_0_LEN_1, |
1922 | VEX_W_0F42_P_0_LEN_1, |
- | 1923 | VEX_W_0F42_P_2_LEN_1, |
|
1704 | VEX_W_0F44_P_0_LEN_0, |
1924 | VEX_W_0F44_P_0_LEN_0, |
- | 1925 | VEX_W_0F44_P_2_LEN_0, |
|
1705 | VEX_W_0F45_P_0_LEN_1, |
1926 | VEX_W_0F45_P_0_LEN_1, |
- | 1927 | VEX_W_0F45_P_2_LEN_1, |
|
1706 | VEX_W_0F46_P_0_LEN_1, |
1928 | VEX_W_0F46_P_0_LEN_1, |
- | 1929 | VEX_W_0F46_P_2_LEN_1, |
|
1707 | VEX_W_0F47_P_0_LEN_1, |
1930 | VEX_W_0F47_P_0_LEN_1, |
- | 1931 | VEX_W_0F47_P_2_LEN_1, |
|
- | 1932 | VEX_W_0F4A_P_0_LEN_1, |
|
- | 1933 | VEX_W_0F4A_P_2_LEN_1, |
|
- | 1934 | VEX_W_0F4B_P_0_LEN_1, |
|
1708 | VEX_W_0F4B_P_2_LEN_1, |
1935 | VEX_W_0F4B_P_2_LEN_1, |
1709 | VEX_W_0F50_M_0, |
1936 | VEX_W_0F50_M_0, |
1710 | VEX_W_0F51_P_0, |
1937 | VEX_W_0F51_P_0, |
1711 | VEX_W_0F51_P_1, |
1938 | VEX_W_0F51_P_1, |
1712 | VEX_W_0F51_P_2, |
1939 | VEX_W_0F51_P_2, |
1713 | VEX_W_0F51_P_3, |
1940 | VEX_W_0F51_P_3, |
1714 | VEX_W_0F52_P_0, |
1941 | VEX_W_0F52_P_0, |
1715 | VEX_W_0F52_P_1, |
1942 | VEX_W_0F52_P_1, |
1716 | VEX_W_0F53_P_0, |
1943 | VEX_W_0F53_P_0, |
1717 | VEX_W_0F53_P_1, |
1944 | VEX_W_0F53_P_1, |
1718 | VEX_W_0F58_P_0, |
1945 | VEX_W_0F58_P_0, |
1719 | VEX_W_0F58_P_1, |
1946 | VEX_W_0F58_P_1, |
1720 | VEX_W_0F58_P_2, |
1947 | VEX_W_0F58_P_2, |
1721 | VEX_W_0F58_P_3, |
1948 | VEX_W_0F58_P_3, |
1722 | VEX_W_0F59_P_0, |
1949 | VEX_W_0F59_P_0, |
1723 | VEX_W_0F59_P_1, |
1950 | VEX_W_0F59_P_1, |
1724 | VEX_W_0F59_P_2, |
1951 | VEX_W_0F59_P_2, |
1725 | VEX_W_0F59_P_3, |
1952 | VEX_W_0F59_P_3, |
1726 | VEX_W_0F5A_P_0, |
1953 | VEX_W_0F5A_P_0, |
1727 | VEX_W_0F5A_P_1, |
1954 | VEX_W_0F5A_P_1, |
1728 | VEX_W_0F5A_P_3, |
1955 | VEX_W_0F5A_P_3, |
1729 | VEX_W_0F5B_P_0, |
1956 | VEX_W_0F5B_P_0, |
1730 | VEX_W_0F5B_P_1, |
1957 | VEX_W_0F5B_P_1, |
1731 | VEX_W_0F5B_P_2, |
1958 | VEX_W_0F5B_P_2, |
1732 | VEX_W_0F5C_P_0, |
1959 | VEX_W_0F5C_P_0, |
1733 | VEX_W_0F5C_P_1, |
1960 | VEX_W_0F5C_P_1, |
1734 | VEX_W_0F5C_P_2, |
1961 | VEX_W_0F5C_P_2, |
1735 | VEX_W_0F5C_P_3, |
1962 | VEX_W_0F5C_P_3, |
1736 | VEX_W_0F5D_P_0, |
1963 | VEX_W_0F5D_P_0, |
1737 | VEX_W_0F5D_P_1, |
1964 | VEX_W_0F5D_P_1, |
1738 | VEX_W_0F5D_P_2, |
1965 | VEX_W_0F5D_P_2, |
1739 | VEX_W_0F5D_P_3, |
1966 | VEX_W_0F5D_P_3, |
1740 | VEX_W_0F5E_P_0, |
1967 | VEX_W_0F5E_P_0, |
1741 | VEX_W_0F5E_P_1, |
1968 | VEX_W_0F5E_P_1, |
1742 | VEX_W_0F5E_P_2, |
1969 | VEX_W_0F5E_P_2, |
1743 | VEX_W_0F5E_P_3, |
1970 | VEX_W_0F5E_P_3, |
1744 | VEX_W_0F5F_P_0, |
1971 | VEX_W_0F5F_P_0, |
1745 | VEX_W_0F5F_P_1, |
1972 | VEX_W_0F5F_P_1, |
1746 | VEX_W_0F5F_P_2, |
1973 | VEX_W_0F5F_P_2, |
1747 | VEX_W_0F5F_P_3, |
1974 | VEX_W_0F5F_P_3, |
1748 | VEX_W_0F60_P_2, |
1975 | VEX_W_0F60_P_2, |
1749 | VEX_W_0F61_P_2, |
1976 | VEX_W_0F61_P_2, |
1750 | VEX_W_0F62_P_2, |
1977 | VEX_W_0F62_P_2, |
1751 | VEX_W_0F63_P_2, |
1978 | VEX_W_0F63_P_2, |
1752 | VEX_W_0F64_P_2, |
1979 | VEX_W_0F64_P_2, |
1753 | VEX_W_0F65_P_2, |
1980 | VEX_W_0F65_P_2, |
1754 | VEX_W_0F66_P_2, |
1981 | VEX_W_0F66_P_2, |
1755 | VEX_W_0F67_P_2, |
1982 | VEX_W_0F67_P_2, |
1756 | VEX_W_0F68_P_2, |
1983 | VEX_W_0F68_P_2, |
1757 | VEX_W_0F69_P_2, |
1984 | VEX_W_0F69_P_2, |
1758 | VEX_W_0F6A_P_2, |
1985 | VEX_W_0F6A_P_2, |
1759 | VEX_W_0F6B_P_2, |
1986 | VEX_W_0F6B_P_2, |
1760 | VEX_W_0F6C_P_2, |
1987 | VEX_W_0F6C_P_2, |
1761 | VEX_W_0F6D_P_2, |
1988 | VEX_W_0F6D_P_2, |
1762 | VEX_W_0F6F_P_1, |
1989 | VEX_W_0F6F_P_1, |
1763 | VEX_W_0F6F_P_2, |
1990 | VEX_W_0F6F_P_2, |
1764 | VEX_W_0F70_P_1, |
1991 | VEX_W_0F70_P_1, |
1765 | VEX_W_0F70_P_2, |
1992 | VEX_W_0F70_P_2, |
1766 | VEX_W_0F70_P_3, |
1993 | VEX_W_0F70_P_3, |
1767 | VEX_W_0F71_R_2_P_2, |
1994 | VEX_W_0F71_R_2_P_2, |
1768 | VEX_W_0F71_R_4_P_2, |
1995 | VEX_W_0F71_R_4_P_2, |
1769 | VEX_W_0F71_R_6_P_2, |
1996 | VEX_W_0F71_R_6_P_2, |
1770 | VEX_W_0F72_R_2_P_2, |
1997 | VEX_W_0F72_R_2_P_2, |
1771 | VEX_W_0F72_R_4_P_2, |
1998 | VEX_W_0F72_R_4_P_2, |
1772 | VEX_W_0F72_R_6_P_2, |
1999 | VEX_W_0F72_R_6_P_2, |
1773 | VEX_W_0F73_R_2_P_2, |
2000 | VEX_W_0F73_R_2_P_2, |
1774 | VEX_W_0F73_R_3_P_2, |
2001 | VEX_W_0F73_R_3_P_2, |
1775 | VEX_W_0F73_R_6_P_2, |
2002 | VEX_W_0F73_R_6_P_2, |
1776 | VEX_W_0F73_R_7_P_2, |
2003 | VEX_W_0F73_R_7_P_2, |
1777 | VEX_W_0F74_P_2, |
2004 | VEX_W_0F74_P_2, |
1778 | VEX_W_0F75_P_2, |
2005 | VEX_W_0F75_P_2, |
1779 | VEX_W_0F76_P_2, |
2006 | VEX_W_0F76_P_2, |
1780 | VEX_W_0F77_P_0, |
2007 | VEX_W_0F77_P_0, |
1781 | VEX_W_0F7C_P_2, |
2008 | VEX_W_0F7C_P_2, |
1782 | VEX_W_0F7C_P_3, |
2009 | VEX_W_0F7C_P_3, |
1783 | VEX_W_0F7D_P_2, |
2010 | VEX_W_0F7D_P_2, |
1784 | VEX_W_0F7D_P_3, |
2011 | VEX_W_0F7D_P_3, |
1785 | VEX_W_0F7E_P_1, |
2012 | VEX_W_0F7E_P_1, |
1786 | VEX_W_0F7F_P_1, |
2013 | VEX_W_0F7F_P_1, |
1787 | VEX_W_0F7F_P_2, |
2014 | VEX_W_0F7F_P_2, |
1788 | VEX_W_0F90_P_0_LEN_0, |
2015 | VEX_W_0F90_P_0_LEN_0, |
- | 2016 | VEX_W_0F90_P_2_LEN_0, |
|
1789 | VEX_W_0F91_P_0_LEN_0, |
2017 | VEX_W_0F91_P_0_LEN_0, |
- | 2018 | VEX_W_0F91_P_2_LEN_0, |
|
1790 | VEX_W_0F92_P_0_LEN_0, |
2019 | VEX_W_0F92_P_0_LEN_0, |
- | 2020 | VEX_W_0F92_P_2_LEN_0, |
|
- | 2021 | VEX_W_0F92_P_3_LEN_0, |
|
1791 | VEX_W_0F93_P_0_LEN_0, |
2022 | VEX_W_0F93_P_0_LEN_0, |
- | 2023 | VEX_W_0F93_P_2_LEN_0, |
|
- | 2024 | VEX_W_0F93_P_3_LEN_0, |
|
1792 | VEX_W_0F98_P_0_LEN_0, |
2025 | VEX_W_0F98_P_0_LEN_0, |
- | 2026 | VEX_W_0F98_P_2_LEN_0, |
|
- | 2027 | VEX_W_0F99_P_0_LEN_0, |
|
- | 2028 | VEX_W_0F99_P_2_LEN_0, |
|
1793 | VEX_W_0FAE_R_2_M_0, |
2029 | VEX_W_0FAE_R_2_M_0, |
1794 | VEX_W_0FAE_R_3_M_0, |
2030 | VEX_W_0FAE_R_3_M_0, |
1795 | VEX_W_0FC2_P_0, |
2031 | VEX_W_0FC2_P_0, |
1796 | VEX_W_0FC2_P_1, |
2032 | VEX_W_0FC2_P_1, |
1797 | VEX_W_0FC2_P_2, |
2033 | VEX_W_0FC2_P_2, |
1798 | VEX_W_0FC2_P_3, |
2034 | VEX_W_0FC2_P_3, |
1799 | VEX_W_0FC4_P_2, |
2035 | VEX_W_0FC4_P_2, |
1800 | VEX_W_0FC5_P_2, |
2036 | VEX_W_0FC5_P_2, |
1801 | VEX_W_0FD0_P_2, |
2037 | VEX_W_0FD0_P_2, |
1802 | VEX_W_0FD0_P_3, |
2038 | VEX_W_0FD0_P_3, |
1803 | VEX_W_0FD1_P_2, |
2039 | VEX_W_0FD1_P_2, |
1804 | VEX_W_0FD2_P_2, |
2040 | VEX_W_0FD2_P_2, |
1805 | VEX_W_0FD3_P_2, |
2041 | VEX_W_0FD3_P_2, |
1806 | VEX_W_0FD4_P_2, |
2042 | VEX_W_0FD4_P_2, |
1807 | VEX_W_0FD5_P_2, |
2043 | VEX_W_0FD5_P_2, |
1808 | VEX_W_0FD6_P_2, |
2044 | VEX_W_0FD6_P_2, |
1809 | VEX_W_0FD7_P_2_M_1, |
2045 | VEX_W_0FD7_P_2_M_1, |
1810 | VEX_W_0FD8_P_2, |
2046 | VEX_W_0FD8_P_2, |
1811 | VEX_W_0FD9_P_2, |
2047 | VEX_W_0FD9_P_2, |
1812 | VEX_W_0FDA_P_2, |
2048 | VEX_W_0FDA_P_2, |
1813 | VEX_W_0FDB_P_2, |
2049 | VEX_W_0FDB_P_2, |
1814 | VEX_W_0FDC_P_2, |
2050 | VEX_W_0FDC_P_2, |
1815 | VEX_W_0FDD_P_2, |
2051 | VEX_W_0FDD_P_2, |
1816 | VEX_W_0FDE_P_2, |
2052 | VEX_W_0FDE_P_2, |
1817 | VEX_W_0FDF_P_2, |
2053 | VEX_W_0FDF_P_2, |
1818 | VEX_W_0FE0_P_2, |
2054 | VEX_W_0FE0_P_2, |
1819 | VEX_W_0FE1_P_2, |
2055 | VEX_W_0FE1_P_2, |
1820 | VEX_W_0FE2_P_2, |
2056 | VEX_W_0FE2_P_2, |
1821 | VEX_W_0FE3_P_2, |
2057 | VEX_W_0FE3_P_2, |
1822 | VEX_W_0FE4_P_2, |
2058 | VEX_W_0FE4_P_2, |
1823 | VEX_W_0FE5_P_2, |
2059 | VEX_W_0FE5_P_2, |
1824 | VEX_W_0FE6_P_1, |
2060 | VEX_W_0FE6_P_1, |
1825 | VEX_W_0FE6_P_2, |
2061 | VEX_W_0FE6_P_2, |
1826 | VEX_W_0FE6_P_3, |
2062 | VEX_W_0FE6_P_3, |
1827 | VEX_W_0FE7_P_2_M_0, |
2063 | VEX_W_0FE7_P_2_M_0, |
1828 | VEX_W_0FE8_P_2, |
2064 | VEX_W_0FE8_P_2, |
1829 | VEX_W_0FE9_P_2, |
2065 | VEX_W_0FE9_P_2, |
1830 | VEX_W_0FEA_P_2, |
2066 | VEX_W_0FEA_P_2, |
1831 | VEX_W_0FEB_P_2, |
2067 | VEX_W_0FEB_P_2, |
1832 | VEX_W_0FEC_P_2, |
2068 | VEX_W_0FEC_P_2, |
1833 | VEX_W_0FED_P_2, |
2069 | VEX_W_0FED_P_2, |
1834 | VEX_W_0FEE_P_2, |
2070 | VEX_W_0FEE_P_2, |
1835 | VEX_W_0FEF_P_2, |
2071 | VEX_W_0FEF_P_2, |
1836 | VEX_W_0FF0_P_3_M_0, |
2072 | VEX_W_0FF0_P_3_M_0, |
1837 | VEX_W_0FF1_P_2, |
2073 | VEX_W_0FF1_P_2, |
1838 | VEX_W_0FF2_P_2, |
2074 | VEX_W_0FF2_P_2, |
1839 | VEX_W_0FF3_P_2, |
2075 | VEX_W_0FF3_P_2, |
1840 | VEX_W_0FF4_P_2, |
2076 | VEX_W_0FF4_P_2, |
1841 | VEX_W_0FF5_P_2, |
2077 | VEX_W_0FF5_P_2, |
1842 | VEX_W_0FF6_P_2, |
2078 | VEX_W_0FF6_P_2, |
1843 | VEX_W_0FF7_P_2, |
2079 | VEX_W_0FF7_P_2, |
1844 | VEX_W_0FF8_P_2, |
2080 | VEX_W_0FF8_P_2, |
1845 | VEX_W_0FF9_P_2, |
2081 | VEX_W_0FF9_P_2, |
1846 | VEX_W_0FFA_P_2, |
2082 | VEX_W_0FFA_P_2, |
1847 | VEX_W_0FFB_P_2, |
2083 | VEX_W_0FFB_P_2, |
1848 | VEX_W_0FFC_P_2, |
2084 | VEX_W_0FFC_P_2, |
1849 | VEX_W_0FFD_P_2, |
2085 | VEX_W_0FFD_P_2, |
1850 | VEX_W_0FFE_P_2, |
2086 | VEX_W_0FFE_P_2, |
1851 | VEX_W_0F3800_P_2, |
2087 | VEX_W_0F3800_P_2, |
1852 | VEX_W_0F3801_P_2, |
2088 | VEX_W_0F3801_P_2, |
1853 | VEX_W_0F3802_P_2, |
2089 | VEX_W_0F3802_P_2, |
1854 | VEX_W_0F3803_P_2, |
2090 | VEX_W_0F3803_P_2, |
1855 | VEX_W_0F3804_P_2, |
2091 | VEX_W_0F3804_P_2, |
1856 | VEX_W_0F3805_P_2, |
2092 | VEX_W_0F3805_P_2, |
1857 | VEX_W_0F3806_P_2, |
2093 | VEX_W_0F3806_P_2, |
1858 | VEX_W_0F3807_P_2, |
2094 | VEX_W_0F3807_P_2, |
1859 | VEX_W_0F3808_P_2, |
2095 | VEX_W_0F3808_P_2, |
1860 | VEX_W_0F3809_P_2, |
2096 | VEX_W_0F3809_P_2, |
1861 | VEX_W_0F380A_P_2, |
2097 | VEX_W_0F380A_P_2, |
1862 | VEX_W_0F380B_P_2, |
2098 | VEX_W_0F380B_P_2, |
1863 | VEX_W_0F380C_P_2, |
2099 | VEX_W_0F380C_P_2, |
1864 | VEX_W_0F380D_P_2, |
2100 | VEX_W_0F380D_P_2, |
1865 | VEX_W_0F380E_P_2, |
2101 | VEX_W_0F380E_P_2, |
1866 | VEX_W_0F380F_P_2, |
2102 | VEX_W_0F380F_P_2, |
1867 | VEX_W_0F3816_P_2, |
2103 | VEX_W_0F3816_P_2, |
1868 | VEX_W_0F3817_P_2, |
2104 | VEX_W_0F3817_P_2, |
1869 | VEX_W_0F3818_P_2, |
2105 | VEX_W_0F3818_P_2, |
1870 | VEX_W_0F3819_P_2, |
2106 | VEX_W_0F3819_P_2, |
1871 | VEX_W_0F381A_P_2_M_0, |
2107 | VEX_W_0F381A_P_2_M_0, |
1872 | VEX_W_0F381C_P_2, |
2108 | VEX_W_0F381C_P_2, |
1873 | VEX_W_0F381D_P_2, |
2109 | VEX_W_0F381D_P_2, |
1874 | VEX_W_0F381E_P_2, |
2110 | VEX_W_0F381E_P_2, |
1875 | VEX_W_0F3820_P_2, |
2111 | VEX_W_0F3820_P_2, |
1876 | VEX_W_0F3821_P_2, |
2112 | VEX_W_0F3821_P_2, |
1877 | VEX_W_0F3822_P_2, |
2113 | VEX_W_0F3822_P_2, |
1878 | VEX_W_0F3823_P_2, |
2114 | VEX_W_0F3823_P_2, |
1879 | VEX_W_0F3824_P_2, |
2115 | VEX_W_0F3824_P_2, |
1880 | VEX_W_0F3825_P_2, |
2116 | VEX_W_0F3825_P_2, |
1881 | VEX_W_0F3828_P_2, |
2117 | VEX_W_0F3828_P_2, |
1882 | VEX_W_0F3829_P_2, |
2118 | VEX_W_0F3829_P_2, |
1883 | VEX_W_0F382A_P_2_M_0, |
2119 | VEX_W_0F382A_P_2_M_0, |
1884 | VEX_W_0F382B_P_2, |
2120 | VEX_W_0F382B_P_2, |
1885 | VEX_W_0F382C_P_2_M_0, |
2121 | VEX_W_0F382C_P_2_M_0, |
1886 | VEX_W_0F382D_P_2_M_0, |
2122 | VEX_W_0F382D_P_2_M_0, |
1887 | VEX_W_0F382E_P_2_M_0, |
2123 | VEX_W_0F382E_P_2_M_0, |
1888 | VEX_W_0F382F_P_2_M_0, |
2124 | VEX_W_0F382F_P_2_M_0, |
1889 | VEX_W_0F3830_P_2, |
2125 | VEX_W_0F3830_P_2, |
1890 | VEX_W_0F3831_P_2, |
2126 | VEX_W_0F3831_P_2, |
1891 | VEX_W_0F3832_P_2, |
2127 | VEX_W_0F3832_P_2, |
1892 | VEX_W_0F3833_P_2, |
2128 | VEX_W_0F3833_P_2, |
1893 | VEX_W_0F3834_P_2, |
2129 | VEX_W_0F3834_P_2, |
1894 | VEX_W_0F3835_P_2, |
2130 | VEX_W_0F3835_P_2, |
1895 | VEX_W_0F3836_P_2, |
2131 | VEX_W_0F3836_P_2, |
1896 | VEX_W_0F3837_P_2, |
2132 | VEX_W_0F3837_P_2, |
1897 | VEX_W_0F3838_P_2, |
2133 | VEX_W_0F3838_P_2, |
1898 | VEX_W_0F3839_P_2, |
2134 | VEX_W_0F3839_P_2, |
1899 | VEX_W_0F383A_P_2, |
2135 | VEX_W_0F383A_P_2, |
1900 | VEX_W_0F383B_P_2, |
2136 | VEX_W_0F383B_P_2, |
1901 | VEX_W_0F383C_P_2, |
2137 | VEX_W_0F383C_P_2, |
1902 | VEX_W_0F383D_P_2, |
2138 | VEX_W_0F383D_P_2, |
1903 | VEX_W_0F383E_P_2, |
2139 | VEX_W_0F383E_P_2, |
1904 | VEX_W_0F383F_P_2, |
2140 | VEX_W_0F383F_P_2, |
1905 | VEX_W_0F3840_P_2, |
2141 | VEX_W_0F3840_P_2, |
1906 | VEX_W_0F3841_P_2, |
2142 | VEX_W_0F3841_P_2, |
1907 | VEX_W_0F3846_P_2, |
2143 | VEX_W_0F3846_P_2, |
1908 | VEX_W_0F3858_P_2, |
2144 | VEX_W_0F3858_P_2, |
1909 | VEX_W_0F3859_P_2, |
2145 | VEX_W_0F3859_P_2, |
1910 | VEX_W_0F385A_P_2_M_0, |
2146 | VEX_W_0F385A_P_2_M_0, |
1911 | VEX_W_0F3878_P_2, |
2147 | VEX_W_0F3878_P_2, |
1912 | VEX_W_0F3879_P_2, |
2148 | VEX_W_0F3879_P_2, |
1913 | VEX_W_0F38DB_P_2, |
2149 | VEX_W_0F38DB_P_2, |
1914 | VEX_W_0F38DC_P_2, |
2150 | VEX_W_0F38DC_P_2, |
1915 | VEX_W_0F38DD_P_2, |
2151 | VEX_W_0F38DD_P_2, |
1916 | VEX_W_0F38DE_P_2, |
2152 | VEX_W_0F38DE_P_2, |
1917 | VEX_W_0F38DF_P_2, |
2153 | VEX_W_0F38DF_P_2, |
1918 | VEX_W_0F3A00_P_2, |
2154 | VEX_W_0F3A00_P_2, |
1919 | VEX_W_0F3A01_P_2, |
2155 | VEX_W_0F3A01_P_2, |
1920 | VEX_W_0F3A02_P_2, |
2156 | VEX_W_0F3A02_P_2, |
1921 | VEX_W_0F3A04_P_2, |
2157 | VEX_W_0F3A04_P_2, |
1922 | VEX_W_0F3A05_P_2, |
2158 | VEX_W_0F3A05_P_2, |
1923 | VEX_W_0F3A06_P_2, |
2159 | VEX_W_0F3A06_P_2, |
1924 | VEX_W_0F3A08_P_2, |
2160 | VEX_W_0F3A08_P_2, |
1925 | VEX_W_0F3A09_P_2, |
2161 | VEX_W_0F3A09_P_2, |
1926 | VEX_W_0F3A0A_P_2, |
2162 | VEX_W_0F3A0A_P_2, |
1927 | VEX_W_0F3A0B_P_2, |
2163 | VEX_W_0F3A0B_P_2, |
1928 | VEX_W_0F3A0C_P_2, |
2164 | VEX_W_0F3A0C_P_2, |
1929 | VEX_W_0F3A0D_P_2, |
2165 | VEX_W_0F3A0D_P_2, |
1930 | VEX_W_0F3A0E_P_2, |
2166 | VEX_W_0F3A0E_P_2, |
1931 | VEX_W_0F3A0F_P_2, |
2167 | VEX_W_0F3A0F_P_2, |
1932 | VEX_W_0F3A14_P_2, |
2168 | VEX_W_0F3A14_P_2, |
1933 | VEX_W_0F3A15_P_2, |
2169 | VEX_W_0F3A15_P_2, |
1934 | VEX_W_0F3A18_P_2, |
2170 | VEX_W_0F3A18_P_2, |
1935 | VEX_W_0F3A19_P_2, |
2171 | VEX_W_0F3A19_P_2, |
1936 | VEX_W_0F3A20_P_2, |
2172 | VEX_W_0F3A20_P_2, |
1937 | VEX_W_0F3A21_P_2, |
2173 | VEX_W_0F3A21_P_2, |
1938 | VEX_W_0F3A30_P_2_LEN_0, |
2174 | VEX_W_0F3A30_P_2_LEN_0, |
- | 2175 | VEX_W_0F3A31_P_2_LEN_0, |
|
1939 | VEX_W_0F3A32_P_2_LEN_0, |
2176 | VEX_W_0F3A32_P_2_LEN_0, |
- | 2177 | VEX_W_0F3A33_P_2_LEN_0, |
|
1940 | VEX_W_0F3A38_P_2, |
2178 | VEX_W_0F3A38_P_2, |
1941 | VEX_W_0F3A39_P_2, |
2179 | VEX_W_0F3A39_P_2, |
1942 | VEX_W_0F3A40_P_2, |
2180 | VEX_W_0F3A40_P_2, |
1943 | VEX_W_0F3A41_P_2, |
2181 | VEX_W_0F3A41_P_2, |
1944 | VEX_W_0F3A42_P_2, |
2182 | VEX_W_0F3A42_P_2, |
1945 | VEX_W_0F3A44_P_2, |
2183 | VEX_W_0F3A44_P_2, |
1946 | VEX_W_0F3A46_P_2, |
2184 | VEX_W_0F3A46_P_2, |
1947 | VEX_W_0F3A48_P_2, |
2185 | VEX_W_0F3A48_P_2, |
1948 | VEX_W_0F3A49_P_2, |
2186 | VEX_W_0F3A49_P_2, |
1949 | VEX_W_0F3A4A_P_2, |
2187 | VEX_W_0F3A4A_P_2, |
1950 | VEX_W_0F3A4B_P_2, |
2188 | VEX_W_0F3A4B_P_2, |
1951 | VEX_W_0F3A4C_P_2, |
2189 | VEX_W_0F3A4C_P_2, |
1952 | VEX_W_0F3A60_P_2, |
2190 | VEX_W_0F3A60_P_2, |
1953 | VEX_W_0F3A61_P_2, |
2191 | VEX_W_0F3A61_P_2, |
1954 | VEX_W_0F3A62_P_2, |
2192 | VEX_W_0F3A62_P_2, |
1955 | VEX_W_0F3A63_P_2, |
2193 | VEX_W_0F3A63_P_2, |
1956 | VEX_W_0F3ADF_P_2, |
2194 | VEX_W_0F3ADF_P_2, |
1957 | 2195 | ||
1958 | EVEX_W_0F10_P_0, |
2196 | EVEX_W_0F10_P_0, |
1959 | EVEX_W_0F10_P_1_M_0, |
2197 | EVEX_W_0F10_P_1_M_0, |
1960 | EVEX_W_0F10_P_1_M_1, |
2198 | EVEX_W_0F10_P_1_M_1, |
1961 | EVEX_W_0F10_P_2, |
2199 | EVEX_W_0F10_P_2, |
1962 | EVEX_W_0F10_P_3_M_0, |
2200 | EVEX_W_0F10_P_3_M_0, |
1963 | EVEX_W_0F10_P_3_M_1, |
2201 | EVEX_W_0F10_P_3_M_1, |
1964 | EVEX_W_0F11_P_0, |
2202 | EVEX_W_0F11_P_0, |
1965 | EVEX_W_0F11_P_1_M_0, |
2203 | EVEX_W_0F11_P_1_M_0, |
1966 | EVEX_W_0F11_P_1_M_1, |
2204 | EVEX_W_0F11_P_1_M_1, |
1967 | EVEX_W_0F11_P_2, |
2205 | EVEX_W_0F11_P_2, |
1968 | EVEX_W_0F11_P_3_M_0, |
2206 | EVEX_W_0F11_P_3_M_0, |
1969 | EVEX_W_0F11_P_3_M_1, |
2207 | EVEX_W_0F11_P_3_M_1, |
1970 | EVEX_W_0F12_P_0_M_0, |
2208 | EVEX_W_0F12_P_0_M_0, |
1971 | EVEX_W_0F12_P_0_M_1, |
2209 | EVEX_W_0F12_P_0_M_1, |
1972 | EVEX_W_0F12_P_1, |
2210 | EVEX_W_0F12_P_1, |
1973 | EVEX_W_0F12_P_2, |
2211 | EVEX_W_0F12_P_2, |
1974 | EVEX_W_0F12_P_3, |
2212 | EVEX_W_0F12_P_3, |
1975 | EVEX_W_0F13_P_0, |
2213 | EVEX_W_0F13_P_0, |
1976 | EVEX_W_0F13_P_2, |
2214 | EVEX_W_0F13_P_2, |
1977 | EVEX_W_0F14_P_0, |
2215 | EVEX_W_0F14_P_0, |
1978 | EVEX_W_0F14_P_2, |
2216 | EVEX_W_0F14_P_2, |
1979 | EVEX_W_0F15_P_0, |
2217 | EVEX_W_0F15_P_0, |
1980 | EVEX_W_0F15_P_2, |
2218 | EVEX_W_0F15_P_2, |
1981 | EVEX_W_0F16_P_0_M_0, |
2219 | EVEX_W_0F16_P_0_M_0, |
1982 | EVEX_W_0F16_P_0_M_1, |
2220 | EVEX_W_0F16_P_0_M_1, |
1983 | EVEX_W_0F16_P_1, |
2221 | EVEX_W_0F16_P_1, |
1984 | EVEX_W_0F16_P_2, |
2222 | EVEX_W_0F16_P_2, |
1985 | EVEX_W_0F17_P_0, |
2223 | EVEX_W_0F17_P_0, |
1986 | EVEX_W_0F17_P_2, |
2224 | EVEX_W_0F17_P_2, |
1987 | EVEX_W_0F28_P_0, |
2225 | EVEX_W_0F28_P_0, |
1988 | EVEX_W_0F28_P_2, |
2226 | EVEX_W_0F28_P_2, |
1989 | EVEX_W_0F29_P_0, |
2227 | EVEX_W_0F29_P_0, |
1990 | EVEX_W_0F29_P_2, |
2228 | EVEX_W_0F29_P_2, |
1991 | EVEX_W_0F2A_P_1, |
2229 | EVEX_W_0F2A_P_1, |
1992 | EVEX_W_0F2A_P_3, |
2230 | EVEX_W_0F2A_P_3, |
1993 | EVEX_W_0F2B_P_0, |
2231 | EVEX_W_0F2B_P_0, |
1994 | EVEX_W_0F2B_P_2, |
2232 | EVEX_W_0F2B_P_2, |
1995 | EVEX_W_0F2E_P_0, |
2233 | EVEX_W_0F2E_P_0, |
1996 | EVEX_W_0F2E_P_2, |
2234 | EVEX_W_0F2E_P_2, |
1997 | EVEX_W_0F2F_P_0, |
2235 | EVEX_W_0F2F_P_0, |
1998 | EVEX_W_0F2F_P_2, |
2236 | EVEX_W_0F2F_P_2, |
1999 | EVEX_W_0F51_P_0, |
2237 | EVEX_W_0F51_P_0, |
2000 | EVEX_W_0F51_P_1, |
2238 | EVEX_W_0F51_P_1, |
2001 | EVEX_W_0F51_P_2, |
2239 | EVEX_W_0F51_P_2, |
2002 | EVEX_W_0F51_P_3, |
2240 | EVEX_W_0F51_P_3, |
- | 2241 | EVEX_W_0F54_P_0, |
|
- | 2242 | EVEX_W_0F54_P_2, |
|
- | 2243 | EVEX_W_0F55_P_0, |
|
- | 2244 | EVEX_W_0F55_P_2, |
|
- | 2245 | EVEX_W_0F56_P_0, |
|
- | 2246 | EVEX_W_0F56_P_2, |
|
- | 2247 | EVEX_W_0F57_P_0, |
|
- | 2248 | EVEX_W_0F57_P_2, |
|
2003 | EVEX_W_0F58_P_0, |
2249 | EVEX_W_0F58_P_0, |
2004 | EVEX_W_0F58_P_1, |
2250 | EVEX_W_0F58_P_1, |
2005 | EVEX_W_0F58_P_2, |
2251 | EVEX_W_0F58_P_2, |
2006 | EVEX_W_0F58_P_3, |
2252 | EVEX_W_0F58_P_3, |
2007 | EVEX_W_0F59_P_0, |
2253 | EVEX_W_0F59_P_0, |
2008 | EVEX_W_0F59_P_1, |
2254 | EVEX_W_0F59_P_1, |
2009 | EVEX_W_0F59_P_2, |
2255 | EVEX_W_0F59_P_2, |
2010 | EVEX_W_0F59_P_3, |
2256 | EVEX_W_0F59_P_3, |
2011 | EVEX_W_0F5A_P_0, |
2257 | EVEX_W_0F5A_P_0, |
2012 | EVEX_W_0F5A_P_1, |
2258 | EVEX_W_0F5A_P_1, |
2013 | EVEX_W_0F5A_P_2, |
2259 | EVEX_W_0F5A_P_2, |
2014 | EVEX_W_0F5A_P_3, |
2260 | EVEX_W_0F5A_P_3, |
2015 | EVEX_W_0F5B_P_0, |
2261 | EVEX_W_0F5B_P_0, |
2016 | EVEX_W_0F5B_P_1, |
2262 | EVEX_W_0F5B_P_1, |
2017 | EVEX_W_0F5B_P_2, |
2263 | EVEX_W_0F5B_P_2, |
2018 | EVEX_W_0F5C_P_0, |
2264 | EVEX_W_0F5C_P_0, |
2019 | EVEX_W_0F5C_P_1, |
2265 | EVEX_W_0F5C_P_1, |
2020 | EVEX_W_0F5C_P_2, |
2266 | EVEX_W_0F5C_P_2, |
2021 | EVEX_W_0F5C_P_3, |
2267 | EVEX_W_0F5C_P_3, |
2022 | EVEX_W_0F5D_P_0, |
2268 | EVEX_W_0F5D_P_0, |
2023 | EVEX_W_0F5D_P_1, |
2269 | EVEX_W_0F5D_P_1, |
2024 | EVEX_W_0F5D_P_2, |
2270 | EVEX_W_0F5D_P_2, |
2025 | EVEX_W_0F5D_P_3, |
2271 | EVEX_W_0F5D_P_3, |
2026 | EVEX_W_0F5E_P_0, |
2272 | EVEX_W_0F5E_P_0, |
2027 | EVEX_W_0F5E_P_1, |
2273 | EVEX_W_0F5E_P_1, |
2028 | EVEX_W_0F5E_P_2, |
2274 | EVEX_W_0F5E_P_2, |
2029 | EVEX_W_0F5E_P_3, |
2275 | EVEX_W_0F5E_P_3, |
2030 | EVEX_W_0F5F_P_0, |
2276 | EVEX_W_0F5F_P_0, |
2031 | EVEX_W_0F5F_P_1, |
2277 | EVEX_W_0F5F_P_1, |
2032 | EVEX_W_0F5F_P_2, |
2278 | EVEX_W_0F5F_P_2, |
2033 | EVEX_W_0F5F_P_3, |
2279 | EVEX_W_0F5F_P_3, |
2034 | EVEX_W_0F62_P_2, |
2280 | EVEX_W_0F62_P_2, |
2035 | EVEX_W_0F66_P_2, |
2281 | EVEX_W_0F66_P_2, |
2036 | EVEX_W_0F6A_P_2, |
2282 | EVEX_W_0F6A_P_2, |
- | 2283 | EVEX_W_0F6B_P_2, |
|
2037 | EVEX_W_0F6C_P_2, |
2284 | EVEX_W_0F6C_P_2, |
2038 | EVEX_W_0F6D_P_2, |
2285 | EVEX_W_0F6D_P_2, |
2039 | EVEX_W_0F6E_P_2, |
2286 | EVEX_W_0F6E_P_2, |
2040 | EVEX_W_0F6F_P_1, |
2287 | EVEX_W_0F6F_P_1, |
2041 | EVEX_W_0F6F_P_2, |
2288 | EVEX_W_0F6F_P_2, |
- | 2289 | EVEX_W_0F6F_P_3, |
|
2042 | EVEX_W_0F70_P_2, |
2290 | EVEX_W_0F70_P_2, |
2043 | EVEX_W_0F72_R_2_P_2, |
2291 | EVEX_W_0F72_R_2_P_2, |
2044 | EVEX_W_0F72_R_6_P_2, |
2292 | EVEX_W_0F72_R_6_P_2, |
2045 | EVEX_W_0F73_R_2_P_2, |
2293 | EVEX_W_0F73_R_2_P_2, |
2046 | EVEX_W_0F73_R_6_P_2, |
2294 | EVEX_W_0F73_R_6_P_2, |
2047 | EVEX_W_0F76_P_2, |
2295 | EVEX_W_0F76_P_2, |
2048 | EVEX_W_0F78_P_0, |
2296 | EVEX_W_0F78_P_0, |
- | 2297 | EVEX_W_0F78_P_2, |
|
2049 | EVEX_W_0F79_P_0, |
2298 | EVEX_W_0F79_P_0, |
- | 2299 | EVEX_W_0F79_P_2, |
|
2050 | EVEX_W_0F7A_P_1, |
2300 | EVEX_W_0F7A_P_1, |
- | 2301 | EVEX_W_0F7A_P_2, |
|
2051 | EVEX_W_0F7A_P_3, |
2302 | EVEX_W_0F7A_P_3, |
2052 | EVEX_W_0F7B_P_1, |
2303 | EVEX_W_0F7B_P_1, |
- | 2304 | EVEX_W_0F7B_P_2, |
|
2053 | EVEX_W_0F7B_P_3, |
2305 | EVEX_W_0F7B_P_3, |
2054 | EVEX_W_0F7E_P_1, |
2306 | EVEX_W_0F7E_P_1, |
2055 | EVEX_W_0F7E_P_2, |
2307 | EVEX_W_0F7E_P_2, |
2056 | EVEX_W_0F7F_P_1, |
2308 | EVEX_W_0F7F_P_1, |
2057 | EVEX_W_0F7F_P_2, |
2309 | EVEX_W_0F7F_P_2, |
- | 2310 | EVEX_W_0F7F_P_3, |
|
2058 | EVEX_W_0FC2_P_0, |
2311 | EVEX_W_0FC2_P_0, |
2059 | EVEX_W_0FC2_P_1, |
2312 | EVEX_W_0FC2_P_1, |
2060 | EVEX_W_0FC2_P_2, |
2313 | EVEX_W_0FC2_P_2, |
2061 | EVEX_W_0FC2_P_3, |
2314 | EVEX_W_0FC2_P_3, |
2062 | EVEX_W_0FC6_P_0, |
2315 | EVEX_W_0FC6_P_0, |
2063 | EVEX_W_0FC6_P_2, |
2316 | EVEX_W_0FC6_P_2, |
2064 | EVEX_W_0FD2_P_2, |
2317 | EVEX_W_0FD2_P_2, |
2065 | EVEX_W_0FD3_P_2, |
2318 | EVEX_W_0FD3_P_2, |
2066 | EVEX_W_0FD4_P_2, |
2319 | EVEX_W_0FD4_P_2, |
2067 | EVEX_W_0FD6_P_2, |
2320 | EVEX_W_0FD6_P_2, |
2068 | EVEX_W_0FE6_P_1, |
2321 | EVEX_W_0FE6_P_1, |
2069 | EVEX_W_0FE6_P_2, |
2322 | EVEX_W_0FE6_P_2, |
2070 | EVEX_W_0FE6_P_3, |
2323 | EVEX_W_0FE6_P_3, |
2071 | EVEX_W_0FE7_P_2, |
2324 | EVEX_W_0FE7_P_2, |
2072 | EVEX_W_0FF2_P_2, |
2325 | EVEX_W_0FF2_P_2, |
2073 | EVEX_W_0FF3_P_2, |
2326 | EVEX_W_0FF3_P_2, |
2074 | EVEX_W_0FF4_P_2, |
2327 | EVEX_W_0FF4_P_2, |
2075 | EVEX_W_0FFA_P_2, |
2328 | EVEX_W_0FFA_P_2, |
2076 | EVEX_W_0FFB_P_2, |
2329 | EVEX_W_0FFB_P_2, |
2077 | EVEX_W_0FFE_P_2, |
2330 | EVEX_W_0FFE_P_2, |
2078 | EVEX_W_0F380C_P_2, |
2331 | EVEX_W_0F380C_P_2, |
2079 | EVEX_W_0F380D_P_2, |
2332 | EVEX_W_0F380D_P_2, |
- | 2333 | EVEX_W_0F3810_P_1, |
|
- | 2334 | EVEX_W_0F3810_P_2, |
|
2080 | EVEX_W_0F3811_P_1, |
2335 | EVEX_W_0F3811_P_1, |
- | 2336 | EVEX_W_0F3811_P_2, |
|
2081 | EVEX_W_0F3812_P_1, |
2337 | EVEX_W_0F3812_P_1, |
- | 2338 | EVEX_W_0F3812_P_2, |
|
2082 | EVEX_W_0F3813_P_1, |
2339 | EVEX_W_0F3813_P_1, |
2083 | EVEX_W_0F3813_P_2, |
2340 | EVEX_W_0F3813_P_2, |
2084 | EVEX_W_0F3814_P_1, |
2341 | EVEX_W_0F3814_P_1, |
2085 | EVEX_W_0F3815_P_1, |
2342 | EVEX_W_0F3815_P_1, |
2086 | EVEX_W_0F3818_P_2, |
2343 | EVEX_W_0F3818_P_2, |
2087 | EVEX_W_0F3819_P_2, |
2344 | EVEX_W_0F3819_P_2, |
2088 | EVEX_W_0F381A_P_2, |
2345 | EVEX_W_0F381A_P_2, |
2089 | EVEX_W_0F381B_P_2, |
2346 | EVEX_W_0F381B_P_2, |
2090 | EVEX_W_0F381E_P_2, |
2347 | EVEX_W_0F381E_P_2, |
2091 | EVEX_W_0F381F_P_2, |
2348 | EVEX_W_0F381F_P_2, |
- | 2349 | EVEX_W_0F3820_P_1, |
|
2092 | EVEX_W_0F3821_P_1, |
2350 | EVEX_W_0F3821_P_1, |
2093 | EVEX_W_0F3822_P_1, |
2351 | EVEX_W_0F3822_P_1, |
2094 | EVEX_W_0F3823_P_1, |
2352 | EVEX_W_0F3823_P_1, |
2095 | EVEX_W_0F3824_P_1, |
2353 | EVEX_W_0F3824_P_1, |
2096 | EVEX_W_0F3825_P_1, |
2354 | EVEX_W_0F3825_P_1, |
2097 | EVEX_W_0F3825_P_2, |
2355 | EVEX_W_0F3825_P_2, |
- | 2356 | EVEX_W_0F3826_P_1, |
|
- | 2357 | EVEX_W_0F3826_P_2, |
|
- | 2358 | EVEX_W_0F3828_P_1, |
|
2098 | EVEX_W_0F3828_P_2, |
2359 | EVEX_W_0F3828_P_2, |
- | 2360 | EVEX_W_0F3829_P_1, |
|
2099 | EVEX_W_0F3829_P_2, |
2361 | EVEX_W_0F3829_P_2, |
2100 | EVEX_W_0F382A_P_1, |
2362 | EVEX_W_0F382A_P_1, |
2101 | EVEX_W_0F382A_P_2, |
2363 | EVEX_W_0F382A_P_2, |
- | 2364 | EVEX_W_0F382B_P_2, |
|
- | 2365 | EVEX_W_0F3830_P_1, |
|
2102 | EVEX_W_0F3831_P_1, |
2366 | EVEX_W_0F3831_P_1, |
2103 | EVEX_W_0F3832_P_1, |
2367 | EVEX_W_0F3832_P_1, |
2104 | EVEX_W_0F3833_P_1, |
2368 | EVEX_W_0F3833_P_1, |
2105 | EVEX_W_0F3834_P_1, |
2369 | EVEX_W_0F3834_P_1, |
2106 | EVEX_W_0F3835_P_1, |
2370 | EVEX_W_0F3835_P_1, |
2107 | EVEX_W_0F3835_P_2, |
2371 | EVEX_W_0F3835_P_2, |
2108 | EVEX_W_0F3837_P_2, |
2372 | EVEX_W_0F3837_P_2, |
- | 2373 | EVEX_W_0F3838_P_1, |
|
- | 2374 | EVEX_W_0F3839_P_1, |
|
2109 | EVEX_W_0F383A_P_1, |
2375 | EVEX_W_0F383A_P_1, |
2110 | EVEX_W_0F3840_P_2, |
2376 | EVEX_W_0F3840_P_2, |
2111 | EVEX_W_0F3858_P_2, |
2377 | EVEX_W_0F3858_P_2, |
2112 | EVEX_W_0F3859_P_2, |
2378 | EVEX_W_0F3859_P_2, |
2113 | EVEX_W_0F385A_P_2, |
2379 | EVEX_W_0F385A_P_2, |
2114 | EVEX_W_0F385B_P_2, |
2380 | EVEX_W_0F385B_P_2, |
- | 2381 | EVEX_W_0F3866_P_2, |
|
- | 2382 | EVEX_W_0F3875_P_2, |
|
- | 2383 | EVEX_W_0F3878_P_2, |
|
- | 2384 | EVEX_W_0F3879_P_2, |
|
- | 2385 | EVEX_W_0F387A_P_2, |
|
- | 2386 | EVEX_W_0F387B_P_2, |
|
- | 2387 | EVEX_W_0F387D_P_2, |
|
- | 2388 | EVEX_W_0F3883_P_2, |
|
- | 2389 | EVEX_W_0F388D_P_2, |
|
2115 | EVEX_W_0F3891_P_2, |
2390 | EVEX_W_0F3891_P_2, |
2116 | EVEX_W_0F3893_P_2, |
2391 | EVEX_W_0F3893_P_2, |
2117 | EVEX_W_0F38A1_P_2, |
2392 | EVEX_W_0F38A1_P_2, |
2118 | EVEX_W_0F38A3_P_2, |
2393 | EVEX_W_0F38A3_P_2, |
2119 | EVEX_W_0F38C7_R_1_P_2, |
2394 | EVEX_W_0F38C7_R_1_P_2, |
2120 | EVEX_W_0F38C7_R_2_P_2, |
2395 | EVEX_W_0F38C7_R_2_P_2, |
2121 | EVEX_W_0F38C7_R_5_P_2, |
2396 | EVEX_W_0F38C7_R_5_P_2, |
2122 | EVEX_W_0F38C7_R_6_P_2, |
2397 | EVEX_W_0F38C7_R_6_P_2, |
2123 | 2398 | ||
2124 | EVEX_W_0F3A00_P_2, |
2399 | EVEX_W_0F3A00_P_2, |
2125 | EVEX_W_0F3A01_P_2, |
2400 | EVEX_W_0F3A01_P_2, |
2126 | EVEX_W_0F3A04_P_2, |
2401 | EVEX_W_0F3A04_P_2, |
2127 | EVEX_W_0F3A05_P_2, |
2402 | EVEX_W_0F3A05_P_2, |
2128 | EVEX_W_0F3A08_P_2, |
2403 | EVEX_W_0F3A08_P_2, |
2129 | EVEX_W_0F3A09_P_2, |
2404 | EVEX_W_0F3A09_P_2, |
2130 | EVEX_W_0F3A0A_P_2, |
2405 | EVEX_W_0F3A0A_P_2, |
2131 | EVEX_W_0F3A0B_P_2, |
2406 | EVEX_W_0F3A0B_P_2, |
- | 2407 | EVEX_W_0F3A16_P_2, |
|
2132 | EVEX_W_0F3A18_P_2, |
2408 | EVEX_W_0F3A18_P_2, |
2133 | EVEX_W_0F3A19_P_2, |
2409 | EVEX_W_0F3A19_P_2, |
2134 | EVEX_W_0F3A1A_P_2, |
2410 | EVEX_W_0F3A1A_P_2, |
2135 | EVEX_W_0F3A1B_P_2, |
2411 | EVEX_W_0F3A1B_P_2, |
2136 | EVEX_W_0F3A1D_P_2, |
2412 | EVEX_W_0F3A1D_P_2, |
2137 | EVEX_W_0F3A21_P_2, |
2413 | EVEX_W_0F3A21_P_2, |
- | 2414 | EVEX_W_0F3A22_P_2, |
|
2138 | EVEX_W_0F3A23_P_2, |
2415 | EVEX_W_0F3A23_P_2, |
2139 | EVEX_W_0F3A38_P_2, |
2416 | EVEX_W_0F3A38_P_2, |
2140 | EVEX_W_0F3A39_P_2, |
2417 | EVEX_W_0F3A39_P_2, |
2141 | EVEX_W_0F3A3A_P_2, |
2418 | EVEX_W_0F3A3A_P_2, |
2142 | EVEX_W_0F3A3B_P_2, |
2419 | EVEX_W_0F3A3B_P_2, |
- | 2420 | EVEX_W_0F3A3E_P_2, |
|
- | 2421 | EVEX_W_0F3A3F_P_2, |
|
- | 2422 | EVEX_W_0F3A42_P_2, |
|
2143 | EVEX_W_0F3A43_P_2, |
2423 | EVEX_W_0F3A43_P_2, |
- | 2424 | EVEX_W_0F3A50_P_2, |
|
- | 2425 | EVEX_W_0F3A51_P_2, |
|
- | 2426 | EVEX_W_0F3A56_P_2, |
|
- | 2427 | EVEX_W_0F3A57_P_2, |
|
- | 2428 | EVEX_W_0F3A66_P_2, |
|
- | 2429 | EVEX_W_0F3A67_P_2 |
|
2144 | }; |
2430 | }; |
2145 | 2431 | ||
2146 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
2432 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
2147 | 2433 | ||
2148 | struct dis386 { |
2434 | struct dis386 { |
2149 | const char *name; |
2435 | const char *name; |
2150 | struct |
2436 | struct |
2151 | { |
2437 | { |
2152 | op_rtn rtn; |
2438 | op_rtn rtn; |
2153 | int bytemode; |
2439 | int bytemode; |
2154 | } op[MAX_OPERANDS]; |
2440 | } op[MAX_OPERANDS]; |
- | 2441 | unsigned int prefix_requirement; |
|
2155 | }; |
2442 | }; |
2156 | 2443 | ||
2157 | /* Upper case letters in the instruction names here are macros. |
2444 | /* Upper case letters in the instruction names here are macros. |
2158 | 'A' => print 'b' if no register operands or suffix_always is true |
2445 | 'A' => print 'b' if no register operands or suffix_always is true |
2159 | 'B' => print 'b' if suffix_always is true |
2446 | 'B' => print 'b' if suffix_always is true |
2160 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
2447 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
2161 | size prefix |
2448 | size prefix |
2162 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
2449 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
2163 | suffix_always is true |
2450 | suffix_always is true |
2164 | 'E' => print 'e' if 32-bit form of jcxz |
2451 | 'E' => print 'e' if 32-bit form of jcxz |
2165 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
2452 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
2166 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
2453 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
2167 | 'H' => print ",pt" or ",pn" branch hint |
2454 | 'H' => print ",pt" or ",pn" branch hint |
2168 | 'I' => honor following macro letter even in Intel mode (implemented only |
2455 | 'I' => honor following macro letter even in Intel mode (implemented only |
2169 | for some of the macro letters) |
2456 | for some of the macro letters) |
2170 | 'J' => print 'l' |
2457 | 'J' => print 'l' |
2171 | 'K' => print 'd' or 'q' if rex prefix is present. |
2458 | 'K' => print 'd' or 'q' if rex prefix is present. |
2172 | 'L' => print 'l' if suffix_always is true |
2459 | 'L' => print 'l' if suffix_always is true |
2173 | 'M' => print 'r' if intel_mnemonic is false. |
2460 | 'M' => print 'r' if intel_mnemonic is false. |
2174 | 'N' => print 'n' if instruction has no wait "prefix" |
2461 | 'N' => print 'n' if instruction has no wait "prefix" |
2175 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
2462 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
2176 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
2463 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
2177 | or suffix_always is true. print 'q' if rex prefix is present. |
2464 | or suffix_always is true. print 'q' if rex prefix is present. |
2178 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always |
2465 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always |
2179 | is true |
2466 | is true |
2180 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
2467 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
2181 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
2468 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
2182 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
2469 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
- | 2470 | prefix and behave as 'P' otherwise |
|
2183 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise |
2471 | 'U' => print 'q' in 64bit mode if instruction has no operand size |
- | 2472 | prefix and behave as 'Q' otherwise |
|
2184 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
2473 | 'V' => print 'q' in 64bit mode if instruction has no operand size |
- | 2474 | prefix and behave as 'S' otherwise |
|
2185 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
2475 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
2186 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
2476 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
2187 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2477 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2188 | suffix_always is true. |
2478 | suffix_always is true. |
2189 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
2479 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
2190 | '!' => change condition from true to false or from false to true. |
2480 | '!' => change condition from true to false or from false to true. |
2191 | '%' => add 1 upper case letter to the macro. |
2481 | '%' => add 1 upper case letter to the macro. |
- | 2482 | '^' => print 'w' or 'l' depending on operand size prefix or |
|
- | 2483 | suffix_always is true (lcall/ljmp). |
|
- | 2484 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
|
- | 2485 | on operand size prefix. |
|
2192 | 2486 | ||
2193 | 2 upper case letter macros: |
2487 | 2 upper case letter macros: |
2194 | "XY" => print 'x' or 'y' if no register operands or suffix_always |
2488 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
- | 2489 | operands and no broadcast. |
|
- | 2490 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no |
|
2195 | is true. |
2491 | register operands and no broadcast. |
2196 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2492 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2197 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand |
2493 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand |
2198 | or suffix_always is true |
2494 | or suffix_always is true |
2199 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2495 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2200 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise |
2496 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise |
2201 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise |
2497 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise |
2202 | "LW" => print 'd', 'q' depending on the VEX.W bit |
2498 | "LW" => print 'd', 'q' depending on the VEX.W bit |
- | 2499 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
|
- | 2500 | an operand size prefix, or suffix_always is true. print |
|
- | 2501 | 'q' if rex prefix is present. |
|
2203 | 2502 | ||
2204 | Many of the above letters print nothing in Intel mode. See "putop" |
2503 | Many of the above letters print nothing in Intel mode. See "putop" |
2205 | for the details. |
2504 | for the details. |
2206 | 2505 | ||
2207 | Braces '{' and '}', and vertical bars '|', indicate alternative |
2506 | Braces '{' and '}', and vertical bars '|', indicate alternative |
2208 | mnemonic strings for AT&T and Intel. */ |
2507 | mnemonic strings for AT&T and Intel. */ |
2209 | 2508 | ||
2210 | static const struct dis386 dis386[] = { |
2509 | static const struct dis386 dis386[] = { |
2211 | /* 00 */ |
2510 | /* 00 */ |
2212 | { "addB", { Ebh1, Gb } }, |
2511 | { "addB", { Ebh1, Gb }, 0 }, |
2213 | { "addS", { Evh1, Gv } }, |
2512 | { "addS", { Evh1, Gv }, 0 }, |
2214 | { "addB", { Gb, EbS } }, |
2513 | { "addB", { Gb, EbS }, 0 }, |
2215 | { "addS", { Gv, EvS } }, |
2514 | { "addS", { Gv, EvS }, 0 }, |
2216 | { "addB", { AL, Ib } }, |
2515 | { "addB", { AL, Ib }, 0 }, |
2217 | { "addS", { eAX, Iv } }, |
2516 | { "addS", { eAX, Iv }, 0 }, |
2218 | { X86_64_TABLE (X86_64_06) }, |
2517 | { X86_64_TABLE (X86_64_06) }, |
2219 | { X86_64_TABLE (X86_64_07) }, |
2518 | { X86_64_TABLE (X86_64_07) }, |
2220 | /* 08 */ |
2519 | /* 08 */ |
2221 | { "orB", { Ebh1, Gb } }, |
2520 | { "orB", { Ebh1, Gb }, 0 }, |
2222 | { "orS", { Evh1, Gv } }, |
2521 | { "orS", { Evh1, Gv }, 0 }, |
2223 | { "orB", { Gb, EbS } }, |
2522 | { "orB", { Gb, EbS }, 0 }, |
2224 | { "orS", { Gv, EvS } }, |
2523 | { "orS", { Gv, EvS }, 0 }, |
2225 | { "orB", { AL, Ib } }, |
2524 | { "orB", { AL, Ib }, 0 }, |
2226 | { "orS", { eAX, Iv } }, |
2525 | { "orS", { eAX, Iv }, 0 }, |
2227 | { X86_64_TABLE (X86_64_0D) }, |
2526 | { X86_64_TABLE (X86_64_0D) }, |
2228 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
2527 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
2229 | /* 10 */ |
2528 | /* 10 */ |
2230 | { "adcB", { Ebh1, Gb } }, |
2529 | { "adcB", { Ebh1, Gb }, 0 }, |
2231 | { "adcS", { Evh1, Gv } }, |
2530 | { "adcS", { Evh1, Gv }, 0 }, |
2232 | { "adcB", { Gb, EbS } }, |
2531 | { "adcB", { Gb, EbS }, 0 }, |
2233 | { "adcS", { Gv, EvS } }, |
2532 | { "adcS", { Gv, EvS }, 0 }, |
2234 | { "adcB", { AL, Ib } }, |
2533 | { "adcB", { AL, Ib }, 0 }, |
2235 | { "adcS", { eAX, Iv } }, |
2534 | { "adcS", { eAX, Iv }, 0 }, |
2236 | { X86_64_TABLE (X86_64_16) }, |
2535 | { X86_64_TABLE (X86_64_16) }, |
2237 | { X86_64_TABLE (X86_64_17) }, |
2536 | { X86_64_TABLE (X86_64_17) }, |
2238 | /* 18 */ |
2537 | /* 18 */ |
2239 | { "sbbB", { Ebh1, Gb } }, |
2538 | { "sbbB", { Ebh1, Gb }, 0 }, |
2240 | { "sbbS", { Evh1, Gv } }, |
2539 | { "sbbS", { Evh1, Gv }, 0 }, |
2241 | { "sbbB", { Gb, EbS } }, |
2540 | { "sbbB", { Gb, EbS }, 0 }, |
2242 | { "sbbS", { Gv, EvS } }, |
2541 | { "sbbS", { Gv, EvS }, 0 }, |
2243 | { "sbbB", { AL, Ib } }, |
2542 | { "sbbB", { AL, Ib }, 0 }, |
2244 | { "sbbS", { eAX, Iv } }, |
2543 | { "sbbS", { eAX, Iv }, 0 }, |
2245 | { X86_64_TABLE (X86_64_1E) }, |
2544 | { X86_64_TABLE (X86_64_1E) }, |
2246 | { X86_64_TABLE (X86_64_1F) }, |
2545 | { X86_64_TABLE (X86_64_1F) }, |
2247 | /* 20 */ |
2546 | /* 20 */ |
2248 | { "andB", { Ebh1, Gb } }, |
2547 | { "andB", { Ebh1, Gb }, 0 }, |
2249 | { "andS", { Evh1, Gv } }, |
2548 | { "andS", { Evh1, Gv }, 0 }, |
2250 | { "andB", { Gb, EbS } }, |
2549 | { "andB", { Gb, EbS }, 0 }, |
2251 | { "andS", { Gv, EvS } }, |
2550 | { "andS", { Gv, EvS }, 0 }, |
2252 | { "andB", { AL, Ib } }, |
2551 | { "andB", { AL, Ib }, 0 }, |
2253 | { "andS", { eAX, Iv } }, |
2552 | { "andS", { eAX, Iv }, 0 }, |
2254 | { Bad_Opcode }, /* SEG ES prefix */ |
2553 | { Bad_Opcode }, /* SEG ES prefix */ |
2255 | { X86_64_TABLE (X86_64_27) }, |
2554 | { X86_64_TABLE (X86_64_27) }, |
2256 | /* 28 */ |
2555 | /* 28 */ |
2257 | { "subB", { Ebh1, Gb } }, |
2556 | { "subB", { Ebh1, Gb }, 0 }, |
2258 | { "subS", { Evh1, Gv } }, |
2557 | { "subS", { Evh1, Gv }, 0 }, |
2259 | { "subB", { Gb, EbS } }, |
2558 | { "subB", { Gb, EbS }, 0 }, |
2260 | { "subS", { Gv, EvS } }, |
2559 | { "subS", { Gv, EvS }, 0 }, |
2261 | { "subB", { AL, Ib } }, |
2560 | { "subB", { AL, Ib }, 0 }, |
2262 | { "subS", { eAX, Iv } }, |
2561 | { "subS", { eAX, Iv }, 0 }, |
2263 | { Bad_Opcode }, /* SEG CS prefix */ |
2562 | { Bad_Opcode }, /* SEG CS prefix */ |
2264 | { X86_64_TABLE (X86_64_2F) }, |
2563 | { X86_64_TABLE (X86_64_2F) }, |
2265 | /* 30 */ |
2564 | /* 30 */ |
2266 | { "xorB", { Ebh1, Gb } }, |
2565 | { "xorB", { Ebh1, Gb }, 0 }, |
2267 | { "xorS", { Evh1, Gv } }, |
2566 | { "xorS", { Evh1, Gv }, 0 }, |
2268 | { "xorB", { Gb, EbS } }, |
2567 | { "xorB", { Gb, EbS }, 0 }, |
2269 | { "xorS", { Gv, EvS } }, |
2568 | { "xorS", { Gv, EvS }, 0 }, |
2270 | { "xorB", { AL, Ib } }, |
2569 | { "xorB", { AL, Ib }, 0 }, |
2271 | { "xorS", { eAX, Iv } }, |
2570 | { "xorS", { eAX, Iv }, 0 }, |
2272 | { Bad_Opcode }, /* SEG SS prefix */ |
2571 | { Bad_Opcode }, /* SEG SS prefix */ |
2273 | { X86_64_TABLE (X86_64_37) }, |
2572 | { X86_64_TABLE (X86_64_37) }, |
2274 | /* 38 */ |
2573 | /* 38 */ |
2275 | { "cmpB", { Eb, Gb } }, |
2574 | { "cmpB", { Eb, Gb }, 0 }, |
2276 | { "cmpS", { Ev, Gv } }, |
2575 | { "cmpS", { Ev, Gv }, 0 }, |
2277 | { "cmpB", { Gb, EbS } }, |
2576 | { "cmpB", { Gb, EbS }, 0 }, |
2278 | { "cmpS", { Gv, EvS } }, |
2577 | { "cmpS", { Gv, EvS }, 0 }, |
2279 | { "cmpB", { AL, Ib } }, |
2578 | { "cmpB", { AL, Ib }, 0 }, |
2280 | { "cmpS", { eAX, Iv } }, |
2579 | { "cmpS", { eAX, Iv }, 0 }, |
2281 | { Bad_Opcode }, /* SEG DS prefix */ |
2580 | { Bad_Opcode }, /* SEG DS prefix */ |
2282 | { X86_64_TABLE (X86_64_3F) }, |
2581 | { X86_64_TABLE (X86_64_3F) }, |
2283 | /* 40 */ |
2582 | /* 40 */ |
2284 | { "inc{S|}", { RMeAX } }, |
2583 | { "inc{S|}", { RMeAX }, 0 }, |
2285 | { "inc{S|}", { RMeCX } }, |
2584 | { "inc{S|}", { RMeCX }, 0 }, |
2286 | { "inc{S|}", { RMeDX } }, |
2585 | { "inc{S|}", { RMeDX }, 0 }, |
2287 | { "inc{S|}", { RMeBX } }, |
2586 | { "inc{S|}", { RMeBX }, 0 }, |
2288 | { "inc{S|}", { RMeSP } }, |
2587 | { "inc{S|}", { RMeSP }, 0 }, |
2289 | { "inc{S|}", { RMeBP } }, |
2588 | { "inc{S|}", { RMeBP }, 0 }, |
2290 | { "inc{S|}", { RMeSI } }, |
2589 | { "inc{S|}", { RMeSI }, 0 }, |
2291 | { "inc{S|}", { RMeDI } }, |
2590 | { "inc{S|}", { RMeDI }, 0 }, |
2292 | /* 48 */ |
2591 | /* 48 */ |
2293 | { "dec{S|}", { RMeAX } }, |
2592 | { "dec{S|}", { RMeAX }, 0 }, |
2294 | { "dec{S|}", { RMeCX } }, |
2593 | { "dec{S|}", { RMeCX }, 0 }, |
2295 | { "dec{S|}", { RMeDX } }, |
2594 | { "dec{S|}", { RMeDX }, 0 }, |
2296 | { "dec{S|}", { RMeBX } }, |
2595 | { "dec{S|}", { RMeBX }, 0 }, |
2297 | { "dec{S|}", { RMeSP } }, |
2596 | { "dec{S|}", { RMeSP }, 0 }, |
2298 | { "dec{S|}", { RMeBP } }, |
2597 | { "dec{S|}", { RMeBP }, 0 }, |
2299 | { "dec{S|}", { RMeSI } }, |
2598 | { "dec{S|}", { RMeSI }, 0 }, |
2300 | { "dec{S|}", { RMeDI } }, |
2599 | { "dec{S|}", { RMeDI }, 0 }, |
2301 | /* 50 */ |
2600 | /* 50 */ |
2302 | { "pushV", { RMrAX } }, |
2601 | { "pushV", { RMrAX }, 0 }, |
2303 | { "pushV", { RMrCX } }, |
2602 | { "pushV", { RMrCX }, 0 }, |
2304 | { "pushV", { RMrDX } }, |
2603 | { "pushV", { RMrDX }, 0 }, |
2305 | { "pushV", { RMrBX } }, |
2604 | { "pushV", { RMrBX }, 0 }, |
2306 | { "pushV", { RMrSP } }, |
2605 | { "pushV", { RMrSP }, 0 }, |
2307 | { "pushV", { RMrBP } }, |
2606 | { "pushV", { RMrBP }, 0 }, |
2308 | { "pushV", { RMrSI } }, |
2607 | { "pushV", { RMrSI }, 0 }, |
2309 | { "pushV", { RMrDI } }, |
2608 | { "pushV", { RMrDI }, 0 }, |
2310 | /* 58 */ |
2609 | /* 58 */ |
2311 | { "popV", { RMrAX } }, |
2610 | { "popV", { RMrAX }, 0 }, |
2312 | { "popV", { RMrCX } }, |
2611 | { "popV", { RMrCX }, 0 }, |
2313 | { "popV", { RMrDX } }, |
2612 | { "popV", { RMrDX }, 0 }, |
2314 | { "popV", { RMrBX } }, |
2613 | { "popV", { RMrBX }, 0 }, |
2315 | { "popV", { RMrSP } }, |
2614 | { "popV", { RMrSP }, 0 }, |
2316 | { "popV", { RMrBP } }, |
2615 | { "popV", { RMrBP }, 0 }, |
2317 | { "popV", { RMrSI } }, |
2616 | { "popV", { RMrSI }, 0 }, |
2318 | { "popV", { RMrDI } }, |
2617 | { "popV", { RMrDI }, 0 }, |
2319 | /* 60 */ |
2618 | /* 60 */ |
2320 | { X86_64_TABLE (X86_64_60) }, |
2619 | { X86_64_TABLE (X86_64_60) }, |
2321 | { X86_64_TABLE (X86_64_61) }, |
2620 | { X86_64_TABLE (X86_64_61) }, |
2322 | { X86_64_TABLE (X86_64_62) }, |
2621 | { X86_64_TABLE (X86_64_62) }, |
2323 | { X86_64_TABLE (X86_64_63) }, |
2622 | { X86_64_TABLE (X86_64_63) }, |
2324 | { Bad_Opcode }, /* seg fs */ |
2623 | { Bad_Opcode }, /* seg fs */ |
2325 | { Bad_Opcode }, /* seg gs */ |
2624 | { Bad_Opcode }, /* seg gs */ |
2326 | { Bad_Opcode }, /* op size prefix */ |
2625 | { Bad_Opcode }, /* op size prefix */ |
2327 | { Bad_Opcode }, /* adr size prefix */ |
2626 | { Bad_Opcode }, /* adr size prefix */ |
2328 | /* 68 */ |
2627 | /* 68 */ |
2329 | { "pushT", { sIv } }, |
2628 | { "pushT", { sIv }, 0 }, |
2330 | { "imulS", { Gv, Ev, Iv } }, |
2629 | { "imulS", { Gv, Ev, Iv }, 0 }, |
2331 | { "pushT", { sIbT } }, |
2630 | { "pushT", { sIbT }, 0 }, |
2332 | { "imulS", { Gv, Ev, sIb } }, |
2631 | { "imulS", { Gv, Ev, sIb }, 0 }, |
2333 | { "ins{b|}", { Ybr, indirDX } }, |
2632 | { "ins{b|}", { Ybr, indirDX }, 0 }, |
2334 | { X86_64_TABLE (X86_64_6D) }, |
2633 | { X86_64_TABLE (X86_64_6D) }, |
2335 | { "outs{b|}", { indirDXr, Xb } }, |
2634 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
2336 | { X86_64_TABLE (X86_64_6F) }, |
2635 | { X86_64_TABLE (X86_64_6F) }, |
2337 | /* 70 */ |
2636 | /* 70 */ |
2338 | { "joH", { Jb, BND, cond_jump_flag } }, |
2637 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2339 | { "jnoH", { Jb, BND, cond_jump_flag } }, |
2638 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, |
2340 | { "jbH", { Jb, BND, cond_jump_flag } }, |
2639 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, |
2341 | { "jaeH", { Jb, BND, cond_jump_flag } }, |
2640 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, |
2342 | { "jeH", { Jb, BND, cond_jump_flag } }, |
2641 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, |
2343 | { "jneH", { Jb, BND, cond_jump_flag } }, |
2642 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, |
2344 | { "jbeH", { Jb, BND, cond_jump_flag } }, |
2643 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, |
2345 | { "jaH", { Jb, BND, cond_jump_flag } }, |
2644 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, |
2346 | /* 78 */ |
2645 | /* 78 */ |
2347 | { "jsH", { Jb, BND, cond_jump_flag } }, |
2646 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2348 | { "jnsH", { Jb, BND, cond_jump_flag } }, |
2647 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, |
2349 | { "jpH", { Jb, BND, cond_jump_flag } }, |
2648 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, |
2350 | { "jnpH", { Jb, BND, cond_jump_flag } }, |
2649 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, |
2351 | { "jlH", { Jb, BND, cond_jump_flag } }, |
2650 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, |
2352 | { "jgeH", { Jb, BND, cond_jump_flag } }, |
2651 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, |
2353 | { "jleH", { Jb, BND, cond_jump_flag } }, |
2652 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, |
2354 | { "jgH", { Jb, BND, cond_jump_flag } }, |
2653 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, |
2355 | /* 80 */ |
2654 | /* 80 */ |
2356 | { REG_TABLE (REG_80) }, |
2655 | { REG_TABLE (REG_80) }, |
2357 | { REG_TABLE (REG_81) }, |
2656 | { REG_TABLE (REG_81) }, |
2358 | { Bad_Opcode }, |
2657 | { Bad_Opcode }, |
2359 | { REG_TABLE (REG_82) }, |
2658 | { REG_TABLE (REG_82) }, |
2360 | { "testB", { Eb, Gb } }, |
2659 | { "testB", { Eb, Gb }, 0 }, |
2361 | { "testS", { Ev, Gv } }, |
2660 | { "testS", { Ev, Gv }, 0 }, |
2362 | { "xchgB", { Ebh2, Gb } }, |
2661 | { "xchgB", { Ebh2, Gb }, 0 }, |
2363 | { "xchgS", { Evh2, Gv } }, |
2662 | { "xchgS", { Evh2, Gv }, 0 }, |
2364 | /* 88 */ |
2663 | /* 88 */ |
2365 | { "movB", { Ebh3, Gb } }, |
2664 | { "movB", { Ebh3, Gb }, 0 }, |
2366 | { "movS", { Evh3, Gv } }, |
2665 | { "movS", { Evh3, Gv }, 0 }, |
2367 | { "movB", { Gb, EbS } }, |
2666 | { "movB", { Gb, EbS }, 0 }, |
2368 | { "movS", { Gv, EvS } }, |
2667 | { "movS", { Gv, EvS }, 0 }, |
2369 | { "movD", { Sv, Sw } }, |
2668 | { "movD", { Sv, Sw }, 0 }, |
2370 | { MOD_TABLE (MOD_8D) }, |
2669 | { MOD_TABLE (MOD_8D) }, |
2371 | { "movD", { Sw, Sv } }, |
2670 | { "movD", { Sw, Sv }, 0 }, |
2372 | { REG_TABLE (REG_8F) }, |
2671 | { REG_TABLE (REG_8F) }, |
2373 | /* 90 */ |
2672 | /* 90 */ |
2374 | { PREFIX_TABLE (PREFIX_90) }, |
2673 | { PREFIX_TABLE (PREFIX_90) }, |
2375 | { "xchgS", { RMeCX, eAX } }, |
2674 | { "xchgS", { RMeCX, eAX }, 0 }, |
2376 | { "xchgS", { RMeDX, eAX } }, |
2675 | { "xchgS", { RMeDX, eAX }, 0 }, |
2377 | { "xchgS", { RMeBX, eAX } }, |
2676 | { "xchgS", { RMeBX, eAX }, 0 }, |
2378 | { "xchgS", { RMeSP, eAX } }, |
2677 | { "xchgS", { RMeSP, eAX }, 0 }, |
2379 | { "xchgS", { RMeBP, eAX } }, |
2678 | { "xchgS", { RMeBP, eAX }, 0 }, |
2380 | { "xchgS", { RMeSI, eAX } }, |
2679 | { "xchgS", { RMeSI, eAX }, 0 }, |
2381 | { "xchgS", { RMeDI, eAX } }, |
2680 | { "xchgS", { RMeDI, eAX }, 0 }, |
2382 | /* 98 */ |
2681 | /* 98 */ |
2383 | { "cW{t|}R", { XX } }, |
2682 | { "cW{t|}R", { XX }, 0 }, |
2384 | { "cR{t|}O", { XX } }, |
2683 | { "cR{t|}O", { XX }, 0 }, |
2385 | { X86_64_TABLE (X86_64_9A) }, |
2684 | { X86_64_TABLE (X86_64_9A) }, |
2386 | { Bad_Opcode }, /* fwait */ |
2685 | { Bad_Opcode }, /* fwait */ |
2387 | { "pushfT", { XX } }, |
2686 | { "pushfT", { XX }, 0 }, |
2388 | { "popfT", { XX } }, |
2687 | { "popfT", { XX }, 0 }, |
2389 | { "sahf", { XX } }, |
2688 | { "sahf", { XX }, 0 }, |
2390 | { "lahf", { XX } }, |
2689 | { "lahf", { XX }, 0 }, |
2391 | /* a0 */ |
2690 | /* a0 */ |
2392 | { "mov%LB", { AL, Ob } }, |
2691 | { "mov%LB", { AL, Ob }, 0 }, |
2393 | { "mov%LS", { eAX, Ov } }, |
2692 | { "mov%LS", { eAX, Ov }, 0 }, |
2394 | { "mov%LB", { Ob, AL } }, |
2693 | { "mov%LB", { Ob, AL }, 0 }, |
2395 | { "mov%LS", { Ov, eAX } }, |
2694 | { "mov%LS", { Ov, eAX }, 0 }, |
2396 | { "movs{b|}", { Ybr, Xb } }, |
2695 | { "movs{b|}", { Ybr, Xb }, 0 }, |
2397 | { "movs{R|}", { Yvr, Xv } }, |
2696 | { "movs{R|}", { Yvr, Xv }, 0 }, |
2398 | { "cmps{b|}", { Xb, Yb } }, |
2697 | { "cmps{b|}", { Xb, Yb }, 0 }, |
2399 | { "cmps{R|}", { Xv, Yv } }, |
2698 | { "cmps{R|}", { Xv, Yv }, 0 }, |
2400 | /* a8 */ |
2699 | /* a8 */ |
2401 | { "testB", { AL, Ib } }, |
2700 | { "testB", { AL, Ib }, 0 }, |
2402 | { "testS", { eAX, Iv } }, |
2701 | { "testS", { eAX, Iv }, 0 }, |
2403 | { "stosB", { Ybr, AL } }, |
2702 | { "stosB", { Ybr, AL }, 0 }, |
2404 | { "stosS", { Yvr, eAX } }, |
2703 | { "stosS", { Yvr, eAX }, 0 }, |
2405 | { "lodsB", { ALr, Xb } }, |
2704 | { "lodsB", { ALr, Xb }, 0 }, |
2406 | { "lodsS", { eAXr, Xv } }, |
2705 | { "lodsS", { eAXr, Xv }, 0 }, |
2407 | { "scasB", { AL, Yb } }, |
2706 | { "scasB", { AL, Yb }, 0 }, |
2408 | { "scasS", { eAX, Yv } }, |
2707 | { "scasS", { eAX, Yv }, 0 }, |
2409 | /* b0 */ |
2708 | /* b0 */ |
2410 | { "movB", { RMAL, Ib } }, |
2709 | { "movB", { RMAL, Ib }, 0 }, |
2411 | { "movB", { RMCL, Ib } }, |
2710 | { "movB", { RMCL, Ib }, 0 }, |
2412 | { "movB", { RMDL, Ib } }, |
2711 | { "movB", { RMDL, Ib }, 0 }, |
2413 | { "movB", { RMBL, Ib } }, |
2712 | { "movB", { RMBL, Ib }, 0 }, |
2414 | { "movB", { RMAH, Ib } }, |
2713 | { "movB", { RMAH, Ib }, 0 }, |
2415 | { "movB", { RMCH, Ib } }, |
2714 | { "movB", { RMCH, Ib }, 0 }, |
2416 | { "movB", { RMDH, Ib } }, |
2715 | { "movB", { RMDH, Ib }, 0 }, |
2417 | { "movB", { RMBH, Ib } }, |
2716 | { "movB", { RMBH, Ib }, 0 }, |
2418 | /* b8 */ |
2717 | /* b8 */ |
2419 | { "mov%LV", { RMeAX, Iv64 } }, |
2718 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2420 | { "mov%LV", { RMeCX, Iv64 } }, |
2719 | { "mov%LV", { RMeCX, Iv64 }, 0 }, |
2421 | { "mov%LV", { RMeDX, Iv64 } }, |
2720 | { "mov%LV", { RMeDX, Iv64 }, 0 }, |
2422 | { "mov%LV", { RMeBX, Iv64 } }, |
2721 | { "mov%LV", { RMeBX, Iv64 }, 0 }, |
2423 | { "mov%LV", { RMeSP, Iv64 } }, |
2722 | { "mov%LV", { RMeSP, Iv64 }, 0 }, |
2424 | { "mov%LV", { RMeBP, Iv64 } }, |
2723 | { "mov%LV", { RMeBP, Iv64 }, 0 }, |
2425 | { "mov%LV", { RMeSI, Iv64 } }, |
2724 | { "mov%LV", { RMeSI, Iv64 }, 0 }, |
2426 | { "mov%LV", { RMeDI, Iv64 } }, |
2725 | { "mov%LV", { RMeDI, Iv64 }, 0 }, |
2427 | /* c0 */ |
2726 | /* c0 */ |
2428 | { REG_TABLE (REG_C0) }, |
2727 | { REG_TABLE (REG_C0) }, |
2429 | { REG_TABLE (REG_C1) }, |
2728 | { REG_TABLE (REG_C1) }, |
2430 | { "retT", { Iw, BND } }, |
2729 | { "retT", { Iw, BND }, 0 }, |
2431 | { "retT", { BND } }, |
2730 | { "retT", { BND }, 0 }, |
2432 | { X86_64_TABLE (X86_64_C4) }, |
2731 | { X86_64_TABLE (X86_64_C4) }, |
2433 | { X86_64_TABLE (X86_64_C5) }, |
2732 | { X86_64_TABLE (X86_64_C5) }, |
2434 | { REG_TABLE (REG_C6) }, |
2733 | { REG_TABLE (REG_C6) }, |
2435 | { REG_TABLE (REG_C7) }, |
2734 | { REG_TABLE (REG_C7) }, |
2436 | /* c8 */ |
2735 | /* c8 */ |
2437 | { "enterT", { Iw, Ib } }, |
2736 | { "enterT", { Iw, Ib }, 0 }, |
2438 | { "leaveT", { XX } }, |
2737 | { "leaveT", { XX }, 0 }, |
2439 | { "Jret{|f}P", { Iw } }, |
2738 | { "Jret{|f}P", { Iw }, 0 }, |
2440 | { "Jret{|f}P", { XX } }, |
2739 | { "Jret{|f}P", { XX }, 0 }, |
2441 | { "int3", { XX } }, |
2740 | { "int3", { XX }, 0 }, |
2442 | { "int", { Ib } }, |
2741 | { "int", { Ib }, 0 }, |
2443 | { X86_64_TABLE (X86_64_CE) }, |
2742 | { X86_64_TABLE (X86_64_CE) }, |
2444 | { "iretP", { XX } }, |
2743 | { "iret%LP", { XX }, 0 }, |
2445 | /* d0 */ |
2744 | /* d0 */ |
2446 | { REG_TABLE (REG_D0) }, |
2745 | { REG_TABLE (REG_D0) }, |
2447 | { REG_TABLE (REG_D1) }, |
2746 | { REG_TABLE (REG_D1) }, |
2448 | { REG_TABLE (REG_D2) }, |
2747 | { REG_TABLE (REG_D2) }, |
2449 | { REG_TABLE (REG_D3) }, |
2748 | { REG_TABLE (REG_D3) }, |
2450 | { X86_64_TABLE (X86_64_D4) }, |
2749 | { X86_64_TABLE (X86_64_D4) }, |
2451 | { X86_64_TABLE (X86_64_D5) }, |
2750 | { X86_64_TABLE (X86_64_D5) }, |
2452 | { Bad_Opcode }, |
2751 | { Bad_Opcode }, |
2453 | { "xlat", { DSBX } }, |
2752 | { "xlat", { DSBX }, 0 }, |
2454 | /* d8 */ |
2753 | /* d8 */ |
2455 | { FLOAT }, |
2754 | { FLOAT }, |
2456 | { FLOAT }, |
2755 | { FLOAT }, |
2457 | { FLOAT }, |
2756 | { FLOAT }, |
2458 | { FLOAT }, |
2757 | { FLOAT }, |
2459 | { FLOAT }, |
2758 | { FLOAT }, |
2460 | { FLOAT }, |
2759 | { FLOAT }, |
2461 | { FLOAT }, |
2760 | { FLOAT }, |
2462 | { FLOAT }, |
2761 | { FLOAT }, |
2463 | /* e0 */ |
2762 | /* e0 */ |
2464 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
2763 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2465 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, |
2764 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2466 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, |
2765 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2467 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, |
2766 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2468 | { "inB", { AL, Ib } }, |
2767 | { "inB", { AL, Ib }, 0 }, |
2469 | { "inG", { zAX, Ib } }, |
2768 | { "inG", { zAX, Ib }, 0 }, |
2470 | { "outB", { Ib, AL } }, |
2769 | { "outB", { Ib, AL }, 0 }, |
2471 | { "outG", { Ib, zAX } }, |
2770 | { "outG", { Ib, zAX }, 0 }, |
2472 | /* e8 */ |
2771 | /* e8 */ |
2473 | { "callT", { Jv, BND } }, |
2772 | { X86_64_TABLE (X86_64_E8) }, |
2474 | { "jmpT", { Jv, BND } }, |
2773 | { X86_64_TABLE (X86_64_E9) }, |
2475 | { X86_64_TABLE (X86_64_EA) }, |
2774 | { X86_64_TABLE (X86_64_EA) }, |
2476 | { "jmp", { Jb, BND } }, |
2775 | { "jmp", { Jb, BND }, 0 }, |
2477 | { "inB", { AL, indirDX } }, |
2776 | { "inB", { AL, indirDX }, 0 }, |
2478 | { "inG", { zAX, indirDX } }, |
2777 | { "inG", { zAX, indirDX }, 0 }, |
2479 | { "outB", { indirDX, AL } }, |
2778 | { "outB", { indirDX, AL }, 0 }, |
2480 | { "outG", { indirDX, zAX } }, |
2779 | { "outG", { indirDX, zAX }, 0 }, |
2481 | /* f0 */ |
2780 | /* f0 */ |
2482 | { Bad_Opcode }, /* lock prefix */ |
2781 | { Bad_Opcode }, /* lock prefix */ |
2483 | { "icebp", { XX } }, |
2782 | { "icebp", { XX }, 0 }, |
2484 | { Bad_Opcode }, /* repne */ |
2783 | { Bad_Opcode }, /* repne */ |
2485 | { Bad_Opcode }, /* repz */ |
2784 | { Bad_Opcode }, /* repz */ |
2486 | { "hlt", { XX } }, |
2785 | { "hlt", { XX }, 0 }, |
2487 | { "cmc", { XX } }, |
2786 | { "cmc", { XX }, 0 }, |
2488 | { REG_TABLE (REG_F6) }, |
2787 | { REG_TABLE (REG_F6) }, |
2489 | { REG_TABLE (REG_F7) }, |
2788 | { REG_TABLE (REG_F7) }, |
2490 | /* f8 */ |
2789 | /* f8 */ |
2491 | { "clc", { XX } }, |
2790 | { "clc", { XX }, 0 }, |
2492 | { "stc", { XX } }, |
2791 | { "stc", { XX }, 0 }, |
2493 | { "cli", { XX } }, |
2792 | { "cli", { XX }, 0 }, |
2494 | { "sti", { XX } }, |
2793 | { "sti", { XX }, 0 }, |
2495 | { "cld", { XX } }, |
2794 | { "cld", { XX }, 0 }, |
2496 | { "std", { XX } }, |
2795 | { "std", { XX }, 0 }, |
2497 | { REG_TABLE (REG_FE) }, |
2796 | { REG_TABLE (REG_FE) }, |
2498 | { REG_TABLE (REG_FF) }, |
2797 | { REG_TABLE (REG_FF) }, |
2499 | }; |
2798 | }; |
2500 | 2799 | ||
2501 | static const struct dis386 dis386_twobyte[] = { |
2800 | static const struct dis386 dis386_twobyte[] = { |
2502 | /* 00 */ |
2801 | /* 00 */ |
2503 | { REG_TABLE (REG_0F00 ) }, |
2802 | { REG_TABLE (REG_0F00 ) }, |
2504 | { REG_TABLE (REG_0F01 ) }, |
2803 | { REG_TABLE (REG_0F01 ) }, |
2505 | { "larS", { Gv, Ew } }, |
2804 | { "larS", { Gv, Ew }, 0 }, |
2506 | { "lslS", { Gv, Ew } }, |
2805 | { "lslS", { Gv, Ew }, 0 }, |
2507 | { Bad_Opcode }, |
2806 | { Bad_Opcode }, |
2508 | { "syscall", { XX } }, |
2807 | { "syscall", { XX }, 0 }, |
2509 | { "clts", { XX } }, |
2808 | { "clts", { XX }, 0 }, |
2510 | { "sysretP", { XX } }, |
2809 | { "sysret%LP", { XX }, 0 }, |
2511 | /* 08 */ |
2810 | /* 08 */ |
2512 | { "invd", { XX } }, |
2811 | { "invd", { XX }, 0 }, |
2513 | { "wbinvd", { XX } }, |
2812 | { "wbinvd", { XX }, 0 }, |
2514 | { Bad_Opcode }, |
2813 | { Bad_Opcode }, |
2515 | { "ud2", { XX } }, |
2814 | { "ud2", { XX }, 0 }, |
2516 | { Bad_Opcode }, |
2815 | { Bad_Opcode }, |
2517 | { REG_TABLE (REG_0F0D) }, |
2816 | { REG_TABLE (REG_0F0D) }, |
2518 | { "femms", { XX } }, |
2817 | { "femms", { XX }, 0 }, |
2519 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ |
2818 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ |
2520 | /* 10 */ |
2819 | /* 10 */ |
2521 | { PREFIX_TABLE (PREFIX_0F10) }, |
2820 | { PREFIX_TABLE (PREFIX_0F10) }, |
2522 | { PREFIX_TABLE (PREFIX_0F11) }, |
2821 | { PREFIX_TABLE (PREFIX_0F11) }, |
2523 | { PREFIX_TABLE (PREFIX_0F12) }, |
2822 | { PREFIX_TABLE (PREFIX_0F12) }, |
2524 | { MOD_TABLE (MOD_0F13) }, |
2823 | { MOD_TABLE (MOD_0F13) }, |
2525 | { "unpcklpX", { XM, EXx } }, |
2824 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2526 | { "unpckhpX", { XM, EXx } }, |
2825 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, |
2527 | { PREFIX_TABLE (PREFIX_0F16) }, |
2826 | { PREFIX_TABLE (PREFIX_0F16) }, |
2528 | { MOD_TABLE (MOD_0F17) }, |
2827 | { MOD_TABLE (MOD_0F17) }, |
2529 | /* 18 */ |
2828 | /* 18 */ |
2530 | { REG_TABLE (REG_0F18) }, |
2829 | { REG_TABLE (REG_0F18) }, |
2531 | { "nopQ", { Ev } }, |
2830 | { "nopQ", { Ev }, 0 }, |
2532 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2831 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2533 | { PREFIX_TABLE (PREFIX_0F1B) }, |
2832 | { PREFIX_TABLE (PREFIX_0F1B) }, |
2534 | { "nopQ", { Ev } }, |
2833 | { "nopQ", { Ev }, 0 }, |
2535 | { "nopQ", { Ev } }, |
2834 | { "nopQ", { Ev }, 0 }, |
2536 | { "nopQ", { Ev } }, |
2835 | { "nopQ", { Ev }, 0 }, |
2537 | { "nopQ", { Ev } }, |
2836 | { "nopQ", { Ev }, 0 }, |
2538 | /* 20 */ |
2837 | /* 20 */ |
2539 | { MOD_TABLE (MOD_0F20) }, |
2838 | { "movZ", { Rm, Cm }, 0 }, |
2540 | { MOD_TABLE (MOD_0F21) }, |
2839 | { "movZ", { Rm, Dm }, 0 }, |
2541 | { MOD_TABLE (MOD_0F22) }, |
2840 | { "movZ", { Cm, Rm }, 0 }, |
2542 | { MOD_TABLE (MOD_0F23) }, |
2841 | { "movZ", { Dm, Rm }, 0 }, |
2543 | { MOD_TABLE (MOD_0F24) }, |
2842 | { MOD_TABLE (MOD_0F24) }, |
2544 | { Bad_Opcode }, |
2843 | { Bad_Opcode }, |
2545 | { MOD_TABLE (MOD_0F26) }, |
2844 | { MOD_TABLE (MOD_0F26) }, |
2546 | { Bad_Opcode }, |
2845 | { Bad_Opcode }, |
2547 | /* 28 */ |
2846 | /* 28 */ |
2548 | { "movapX", { XM, EXx } }, |
2847 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2549 | { "movapX", { EXxS, XM } }, |
2848 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, |
2550 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2849 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2551 | { PREFIX_TABLE (PREFIX_0F2B) }, |
2850 | { PREFIX_TABLE (PREFIX_0F2B) }, |
2552 | { PREFIX_TABLE (PREFIX_0F2C) }, |
2851 | { PREFIX_TABLE (PREFIX_0F2C) }, |
2553 | { PREFIX_TABLE (PREFIX_0F2D) }, |
2852 | { PREFIX_TABLE (PREFIX_0F2D) }, |
2554 | { PREFIX_TABLE (PREFIX_0F2E) }, |
2853 | { PREFIX_TABLE (PREFIX_0F2E) }, |
2555 | { PREFIX_TABLE (PREFIX_0F2F) }, |
2854 | { PREFIX_TABLE (PREFIX_0F2F) }, |
2556 | /* 30 */ |
2855 | /* 30 */ |
2557 | { "wrmsr", { XX } }, |
2856 | { "wrmsr", { XX }, 0 }, |
2558 | { "rdtsc", { XX } }, |
2857 | { "rdtsc", { XX }, 0 }, |
2559 | { "rdmsr", { XX } }, |
2858 | { "rdmsr", { XX }, 0 }, |
2560 | { "rdpmc", { XX } }, |
2859 | { "rdpmc", { XX }, 0 }, |
2561 | { "sysenter", { XX } }, |
2860 | { "sysenter", { XX }, 0 }, |
2562 | { "sysexit", { XX } }, |
2861 | { "sysexit", { XX }, 0 }, |
2563 | { Bad_Opcode }, |
2862 | { Bad_Opcode }, |
2564 | { "getsec", { XX } }, |
2863 | { "getsec", { XX }, 0 }, |
2565 | /* 38 */ |
2864 | /* 38 */ |
2566 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
2865 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
2567 | { Bad_Opcode }, |
2866 | { Bad_Opcode }, |
2568 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
2867 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
2569 | { Bad_Opcode }, |
2868 | { Bad_Opcode }, |
2570 | { Bad_Opcode }, |
2869 | { Bad_Opcode }, |
2571 | { Bad_Opcode }, |
2870 | { Bad_Opcode }, |
2572 | { Bad_Opcode }, |
2871 | { Bad_Opcode }, |
2573 | { Bad_Opcode }, |
2872 | { Bad_Opcode }, |
2574 | /* 40 */ |
2873 | /* 40 */ |
2575 | { "cmovoS", { Gv, Ev } }, |
2874 | { "cmovoS", { Gv, Ev }, 0 }, |
2576 | { "cmovnoS", { Gv, Ev } }, |
2875 | { "cmovnoS", { Gv, Ev }, 0 }, |
2577 | { "cmovbS", { Gv, Ev } }, |
2876 | { "cmovbS", { Gv, Ev }, 0 }, |
2578 | { "cmovaeS", { Gv, Ev } }, |
2877 | { "cmovaeS", { Gv, Ev }, 0 }, |
2579 | { "cmoveS", { Gv, Ev } }, |
2878 | { "cmoveS", { Gv, Ev }, 0 }, |
2580 | { "cmovneS", { Gv, Ev } }, |
2879 | { "cmovneS", { Gv, Ev }, 0 }, |
2581 | { "cmovbeS", { Gv, Ev } }, |
2880 | { "cmovbeS", { Gv, Ev }, 0 }, |
2582 | { "cmovaS", { Gv, Ev } }, |
2881 | { "cmovaS", { Gv, Ev }, 0 }, |
2583 | /* 48 */ |
2882 | /* 48 */ |
2584 | { "cmovsS", { Gv, Ev } }, |
2883 | { "cmovsS", { Gv, Ev }, 0 }, |
2585 | { "cmovnsS", { Gv, Ev } }, |
2884 | { "cmovnsS", { Gv, Ev }, 0 }, |
2586 | { "cmovpS", { Gv, Ev } }, |
2885 | { "cmovpS", { Gv, Ev }, 0 }, |
2587 | { "cmovnpS", { Gv, Ev } }, |
2886 | { "cmovnpS", { Gv, Ev }, 0 }, |
2588 | { "cmovlS", { Gv, Ev } }, |
2887 | { "cmovlS", { Gv, Ev }, 0 }, |
2589 | { "cmovgeS", { Gv, Ev } }, |
2888 | { "cmovgeS", { Gv, Ev }, 0 }, |
2590 | { "cmovleS", { Gv, Ev } }, |
2889 | { "cmovleS", { Gv, Ev }, 0 }, |
2591 | { "cmovgS", { Gv, Ev } }, |
2890 | { "cmovgS", { Gv, Ev }, 0 }, |
2592 | /* 50 */ |
2891 | /* 50 */ |
2593 | { MOD_TABLE (MOD_0F51) }, |
2892 | { MOD_TABLE (MOD_0F51) }, |
2594 | { PREFIX_TABLE (PREFIX_0F51) }, |
2893 | { PREFIX_TABLE (PREFIX_0F51) }, |
2595 | { PREFIX_TABLE (PREFIX_0F52) }, |
2894 | { PREFIX_TABLE (PREFIX_0F52) }, |
2596 | { PREFIX_TABLE (PREFIX_0F53) }, |
2895 | { PREFIX_TABLE (PREFIX_0F53) }, |
2597 | { "andpX", { XM, EXx } }, |
2896 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2598 | { "andnpX", { XM, EXx } }, |
2897 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, |
2599 | { "orpX", { XM, EXx } }, |
2898 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, |
2600 | { "xorpX", { XM, EXx } }, |
2899 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, |
2601 | /* 58 */ |
2900 | /* 58 */ |
2602 | { PREFIX_TABLE (PREFIX_0F58) }, |
2901 | { PREFIX_TABLE (PREFIX_0F58) }, |
2603 | { PREFIX_TABLE (PREFIX_0F59) }, |
2902 | { PREFIX_TABLE (PREFIX_0F59) }, |
2604 | { PREFIX_TABLE (PREFIX_0F5A) }, |
2903 | { PREFIX_TABLE (PREFIX_0F5A) }, |
2605 | { PREFIX_TABLE (PREFIX_0F5B) }, |
2904 | { PREFIX_TABLE (PREFIX_0F5B) }, |
2606 | { PREFIX_TABLE (PREFIX_0F5C) }, |
2905 | { PREFIX_TABLE (PREFIX_0F5C) }, |
2607 | { PREFIX_TABLE (PREFIX_0F5D) }, |
2906 | { PREFIX_TABLE (PREFIX_0F5D) }, |
2608 | { PREFIX_TABLE (PREFIX_0F5E) }, |
2907 | { PREFIX_TABLE (PREFIX_0F5E) }, |
2609 | { PREFIX_TABLE (PREFIX_0F5F) }, |
2908 | { PREFIX_TABLE (PREFIX_0F5F) }, |
2610 | /* 60 */ |
2909 | /* 60 */ |
2611 | { PREFIX_TABLE (PREFIX_0F60) }, |
2910 | { PREFIX_TABLE (PREFIX_0F60) }, |
2612 | { PREFIX_TABLE (PREFIX_0F61) }, |
2911 | { PREFIX_TABLE (PREFIX_0F61) }, |
2613 | { PREFIX_TABLE (PREFIX_0F62) }, |
2912 | { PREFIX_TABLE (PREFIX_0F62) }, |
2614 | { "packsswb", { MX, EM } }, |
2913 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2615 | { "pcmpgtb", { MX, EM } }, |
2914 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, |
2616 | { "pcmpgtw", { MX, EM } }, |
2915 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, |
2617 | { "pcmpgtd", { MX, EM } }, |
2916 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, |
2618 | { "packuswb", { MX, EM } }, |
2917 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, |
2619 | /* 68 */ |
2918 | /* 68 */ |
2620 | { "punpckhbw", { MX, EM } }, |
2919 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2621 | { "punpckhwd", { MX, EM } }, |
2920 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, |
2622 | { "punpckhdq", { MX, EM } }, |
2921 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, |
2623 | { "packssdw", { MX, EM } }, |
2922 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, |
2624 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2923 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2625 | { PREFIX_TABLE (PREFIX_0F6D) }, |
2924 | { PREFIX_TABLE (PREFIX_0F6D) }, |
2626 | { "movK", { MX, Edq } }, |
2925 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
2627 | { PREFIX_TABLE (PREFIX_0F6F) }, |
2926 | { PREFIX_TABLE (PREFIX_0F6F) }, |
2628 | /* 70 */ |
2927 | /* 70 */ |
2629 | { PREFIX_TABLE (PREFIX_0F70) }, |
2928 | { PREFIX_TABLE (PREFIX_0F70) }, |
2630 | { REG_TABLE (REG_0F71) }, |
2929 | { REG_TABLE (REG_0F71) }, |
2631 | { REG_TABLE (REG_0F72) }, |
2930 | { REG_TABLE (REG_0F72) }, |
2632 | { REG_TABLE (REG_0F73) }, |
2931 | { REG_TABLE (REG_0F73) }, |
2633 | { "pcmpeqb", { MX, EM } }, |
2932 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2634 | { "pcmpeqw", { MX, EM } }, |
2933 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, |
2635 | { "pcmpeqd", { MX, EM } }, |
2934 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, |
2636 | { "emms", { XX } }, |
2935 | { "emms", { XX }, PREFIX_OPCODE }, |
2637 | /* 78 */ |
2936 | /* 78 */ |
2638 | { PREFIX_TABLE (PREFIX_0F78) }, |
2937 | { PREFIX_TABLE (PREFIX_0F78) }, |
2639 | { PREFIX_TABLE (PREFIX_0F79) }, |
2938 | { PREFIX_TABLE (PREFIX_0F79) }, |
2640 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
2939 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
2641 | { Bad_Opcode }, |
2940 | { Bad_Opcode }, |
2642 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2941 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2643 | { PREFIX_TABLE (PREFIX_0F7D) }, |
2942 | { PREFIX_TABLE (PREFIX_0F7D) }, |
2644 | { PREFIX_TABLE (PREFIX_0F7E) }, |
2943 | { PREFIX_TABLE (PREFIX_0F7E) }, |
2645 | { PREFIX_TABLE (PREFIX_0F7F) }, |
2944 | { PREFIX_TABLE (PREFIX_0F7F) }, |
2646 | /* 80 */ |
2945 | /* 80 */ |
2647 | { "joH", { Jv, BND, cond_jump_flag } }, |
2946 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2648 | { "jnoH", { Jv, BND, cond_jump_flag } }, |
2947 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, |
2649 | { "jbH", { Jv, BND, cond_jump_flag } }, |
2948 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, |
2650 | { "jaeH", { Jv, BND, cond_jump_flag } }, |
2949 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, |
2651 | { "jeH", { Jv, BND, cond_jump_flag } }, |
2950 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, |
2652 | { "jneH", { Jv, BND, cond_jump_flag } }, |
2951 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, |
2653 | { "jbeH", { Jv, BND, cond_jump_flag } }, |
2952 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, |
2654 | { "jaH", { Jv, BND, cond_jump_flag } }, |
2953 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, |
2655 | /* 88 */ |
2954 | /* 88 */ |
2656 | { "jsH", { Jv, BND, cond_jump_flag } }, |
2955 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2657 | { "jnsH", { Jv, BND, cond_jump_flag } }, |
2956 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, |
2658 | { "jpH", { Jv, BND, cond_jump_flag } }, |
2957 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, |
2659 | { "jnpH", { Jv, BND, cond_jump_flag } }, |
2958 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, |
2660 | { "jlH", { Jv, BND, cond_jump_flag } }, |
2959 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, |
2661 | { "jgeH", { Jv, BND, cond_jump_flag } }, |
2960 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, |
2662 | { "jleH", { Jv, BND, cond_jump_flag } }, |
2961 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, |
2663 | { "jgH", { Jv, BND, cond_jump_flag } }, |
2962 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, |
2664 | /* 90 */ |
2963 | /* 90 */ |
2665 | { "seto", { Eb } }, |
2964 | { "seto", { Eb }, 0 }, |
2666 | { "setno", { Eb } }, |
2965 | { "setno", { Eb }, 0 }, |
2667 | { "setb", { Eb } }, |
2966 | { "setb", { Eb }, 0 }, |
2668 | { "setae", { Eb } }, |
2967 | { "setae", { Eb }, 0 }, |
2669 | { "sete", { Eb } }, |
2968 | { "sete", { Eb }, 0 }, |
2670 | { "setne", { Eb } }, |
2969 | { "setne", { Eb }, 0 }, |
2671 | { "setbe", { Eb } }, |
2970 | { "setbe", { Eb }, 0 }, |
2672 | { "seta", { Eb } }, |
2971 | { "seta", { Eb }, 0 }, |
2673 | /* 98 */ |
2972 | /* 98 */ |
2674 | { "sets", { Eb } }, |
2973 | { "sets", { Eb }, 0 }, |
2675 | { "setns", { Eb } }, |
2974 | { "setns", { Eb }, 0 }, |
2676 | { "setp", { Eb } }, |
2975 | { "setp", { Eb }, 0 }, |
2677 | { "setnp", { Eb } }, |
2976 | { "setnp", { Eb }, 0 }, |
2678 | { "setl", { Eb } }, |
2977 | { "setl", { Eb }, 0 }, |
2679 | { "setge", { Eb } }, |
2978 | { "setge", { Eb }, 0 }, |
2680 | { "setle", { Eb } }, |
2979 | { "setle", { Eb }, 0 }, |
2681 | { "setg", { Eb } }, |
2980 | { "setg", { Eb }, 0 }, |
2682 | /* a0 */ |
2981 | /* a0 */ |
2683 | { "pushT", { fs } }, |
2982 | { "pushT", { fs }, 0 }, |
2684 | { "popT", { fs } }, |
2983 | { "popT", { fs }, 0 }, |
2685 | { "cpuid", { XX } }, |
2984 | { "cpuid", { XX }, 0 }, |
2686 | { "btS", { Ev, Gv } }, |
2985 | { "btS", { Ev, Gv }, 0 }, |
2687 | { "shldS", { Ev, Gv, Ib } }, |
2986 | { "shldS", { Ev, Gv, Ib }, 0 }, |
2688 | { "shldS", { Ev, Gv, CL } }, |
2987 | { "shldS", { Ev, Gv, CL }, 0 }, |
2689 | { REG_TABLE (REG_0FA6) }, |
2988 | { REG_TABLE (REG_0FA6) }, |
2690 | { REG_TABLE (REG_0FA7) }, |
2989 | { REG_TABLE (REG_0FA7) }, |
2691 | /* a8 */ |
2990 | /* a8 */ |
2692 | { "pushT", { gs } }, |
2991 | { "pushT", { gs }, 0 }, |
2693 | { "popT", { gs } }, |
2992 | { "popT", { gs }, 0 }, |
2694 | { "rsm", { XX } }, |
2993 | { "rsm", { XX }, 0 }, |
2695 | { "btsS", { Evh1, Gv } }, |
2994 | { "btsS", { Evh1, Gv }, 0 }, |
2696 | { "shrdS", { Ev, Gv, Ib } }, |
2995 | { "shrdS", { Ev, Gv, Ib }, 0 }, |
2697 | { "shrdS", { Ev, Gv, CL } }, |
2996 | { "shrdS", { Ev, Gv, CL }, 0 }, |
2698 | { REG_TABLE (REG_0FAE) }, |
2997 | { REG_TABLE (REG_0FAE) }, |
2699 | { "imulS", { Gv, Ev } }, |
2998 | { "imulS", { Gv, Ev }, 0 }, |
2700 | /* b0 */ |
2999 | /* b0 */ |
2701 | { "cmpxchgB", { Ebh1, Gb } }, |
3000 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2702 | { "cmpxchgS", { Evh1, Gv } }, |
3001 | { "cmpxchgS", { Evh1, Gv }, 0 }, |
2703 | { MOD_TABLE (MOD_0FB2) }, |
3002 | { MOD_TABLE (MOD_0FB2) }, |
2704 | { "btrS", { Evh1, Gv } }, |
3003 | { "btrS", { Evh1, Gv }, 0 }, |
2705 | { MOD_TABLE (MOD_0FB4) }, |
3004 | { MOD_TABLE (MOD_0FB4) }, |
2706 | { MOD_TABLE (MOD_0FB5) }, |
3005 | { MOD_TABLE (MOD_0FB5) }, |
2707 | { "movz{bR|x}", { Gv, Eb } }, |
3006 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2708 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ |
3007 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ |
2709 | /* b8 */ |
3008 | /* b8 */ |
2710 | { PREFIX_TABLE (PREFIX_0FB8) }, |
3009 | { PREFIX_TABLE (PREFIX_0FB8) }, |
2711 | { "ud1", { XX } }, |
3010 | { "ud1", { XX }, 0 }, |
2712 | { REG_TABLE (REG_0FBA) }, |
3011 | { REG_TABLE (REG_0FBA) }, |
2713 | { "btcS", { Evh1, Gv } }, |
3012 | { "btcS", { Evh1, Gv }, 0 }, |
2714 | { PREFIX_TABLE (PREFIX_0FBC) }, |
3013 | { PREFIX_TABLE (PREFIX_0FBC) }, |
2715 | { PREFIX_TABLE (PREFIX_0FBD) }, |
3014 | { PREFIX_TABLE (PREFIX_0FBD) }, |
2716 | { "movs{bR|x}", { Gv, Eb } }, |
3015 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2717 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ |
3016 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ |
2718 | /* c0 */ |
3017 | /* c0 */ |
2719 | { "xaddB", { Ebh1, Gb } }, |
3018 | { "xaddB", { Ebh1, Gb }, 0 }, |
2720 | { "xaddS", { Evh1, Gv } }, |
3019 | { "xaddS", { Evh1, Gv }, 0 }, |
2721 | { PREFIX_TABLE (PREFIX_0FC2) }, |
3020 | { PREFIX_TABLE (PREFIX_0FC2) }, |
2722 | { PREFIX_TABLE (PREFIX_0FC3) }, |
3021 | { MOD_TABLE (MOD_0FC3) }, |
2723 | { "pinsrw", { MX, Edqw, Ib } }, |
3022 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2724 | { "pextrw", { Gdq, MS, Ib } }, |
3023 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, |
2725 | { "shufpX", { XM, EXx, Ib } }, |
3024 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, |
2726 | { REG_TABLE (REG_0FC7) }, |
3025 | { REG_TABLE (REG_0FC7) }, |
2727 | /* c8 */ |
3026 | /* c8 */ |
2728 | { "bswap", { RMeAX } }, |
3027 | { "bswap", { RMeAX }, 0 }, |
2729 | { "bswap", { RMeCX } }, |
3028 | { "bswap", { RMeCX }, 0 }, |
2730 | { "bswap", { RMeDX } }, |
3029 | { "bswap", { RMeDX }, 0 }, |
2731 | { "bswap", { RMeBX } }, |
3030 | { "bswap", { RMeBX }, 0 }, |
2732 | { "bswap", { RMeSP } }, |
3031 | { "bswap", { RMeSP }, 0 }, |
2733 | { "bswap", { RMeBP } }, |
3032 | { "bswap", { RMeBP }, 0 }, |
2734 | { "bswap", { RMeSI } }, |
3033 | { "bswap", { RMeSI }, 0 }, |
2735 | { "bswap", { RMeDI } }, |
3034 | { "bswap", { RMeDI }, 0 }, |
2736 | /* d0 */ |
3035 | /* d0 */ |
2737 | { PREFIX_TABLE (PREFIX_0FD0) }, |
3036 | { PREFIX_TABLE (PREFIX_0FD0) }, |
2738 | { "psrlw", { MX, EM } }, |
3037 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2739 | { "psrld", { MX, EM } }, |
3038 | { "psrld", { MX, EM }, PREFIX_OPCODE }, |
2740 | { "psrlq", { MX, EM } }, |
3039 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, |
2741 | { "paddq", { MX, EM } }, |
3040 | { "paddq", { MX, EM }, PREFIX_OPCODE }, |
2742 | { "pmullw", { MX, EM } }, |
3041 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, |
2743 | { PREFIX_TABLE (PREFIX_0FD6) }, |
3042 | { PREFIX_TABLE (PREFIX_0FD6) }, |
2744 | { MOD_TABLE (MOD_0FD7) }, |
3043 | { MOD_TABLE (MOD_0FD7) }, |
2745 | /* d8 */ |
3044 | /* d8 */ |
2746 | { "psubusb", { MX, EM } }, |
3045 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2747 | { "psubusw", { MX, EM } }, |
3046 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, |
2748 | { "pminub", { MX, EM } }, |
3047 | { "pminub", { MX, EM }, PREFIX_OPCODE }, |
2749 | { "pand", { MX, EM } }, |
3048 | { "pand", { MX, EM }, PREFIX_OPCODE }, |
2750 | { "paddusb", { MX, EM } }, |
3049 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, |
2751 | { "paddusw", { MX, EM } }, |
3050 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, |
2752 | { "pmaxub", { MX, EM } }, |
3051 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, |
2753 | { "pandn", { MX, EM } }, |
3052 | { "pandn", { MX, EM }, PREFIX_OPCODE }, |
2754 | /* e0 */ |
3053 | /* e0 */ |
2755 | { "pavgb", { MX, EM } }, |
3054 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2756 | { "psraw", { MX, EM } }, |
3055 | { "psraw", { MX, EM }, PREFIX_OPCODE }, |
2757 | { "psrad", { MX, EM } }, |
3056 | { "psrad", { MX, EM }, PREFIX_OPCODE }, |
2758 | { "pavgw", { MX, EM } }, |
3057 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, |
2759 | { "pmulhuw", { MX, EM } }, |
3058 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, |
2760 | { "pmulhw", { MX, EM } }, |
3059 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, |
2761 | { PREFIX_TABLE (PREFIX_0FE6) }, |
3060 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2762 | { PREFIX_TABLE (PREFIX_0FE7) }, |
3061 | { PREFIX_TABLE (PREFIX_0FE7) }, |
2763 | /* e8 */ |
3062 | /* e8 */ |
2764 | { "psubsb", { MX, EM } }, |
3063 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2765 | { "psubsw", { MX, EM } }, |
3064 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, |
2766 | { "pminsw", { MX, EM } }, |
3065 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, |
2767 | { "por", { MX, EM } }, |
3066 | { "por", { MX, EM }, PREFIX_OPCODE }, |
2768 | { "paddsb", { MX, EM } }, |
3067 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, |
2769 | { "paddsw", { MX, EM } }, |
3068 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, |
2770 | { "pmaxsw", { MX, EM } }, |
3069 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, |
2771 | { "pxor", { MX, EM } }, |
3070 | { "pxor", { MX, EM }, PREFIX_OPCODE }, |
2772 | /* f0 */ |
3071 | /* f0 */ |
2773 | { PREFIX_TABLE (PREFIX_0FF0) }, |
3072 | { PREFIX_TABLE (PREFIX_0FF0) }, |
2774 | { "psllw", { MX, EM } }, |
3073 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2775 | { "pslld", { MX, EM } }, |
3074 | { "pslld", { MX, EM }, PREFIX_OPCODE }, |
2776 | { "psllq", { MX, EM } }, |
3075 | { "psllq", { MX, EM }, PREFIX_OPCODE }, |
2777 | { "pmuludq", { MX, EM } }, |
3076 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, |
2778 | { "pmaddwd", { MX, EM } }, |
3077 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, |
2779 | { "psadbw", { MX, EM } }, |
3078 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, |
2780 | { PREFIX_TABLE (PREFIX_0FF7) }, |
3079 | { PREFIX_TABLE (PREFIX_0FF7) }, |
2781 | /* f8 */ |
3080 | /* f8 */ |
2782 | { "psubb", { MX, EM } }, |
3081 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2783 | { "psubw", { MX, EM } }, |
3082 | { "psubw", { MX, EM }, PREFIX_OPCODE }, |
2784 | { "psubd", { MX, EM } }, |
3083 | { "psubd", { MX, EM }, PREFIX_OPCODE }, |
2785 | { "psubq", { MX, EM } }, |
3084 | { "psubq", { MX, EM }, PREFIX_OPCODE }, |
2786 | { "paddb", { MX, EM } }, |
3085 | { "paddb", { MX, EM }, PREFIX_OPCODE }, |
2787 | { "paddw", { MX, EM } }, |
3086 | { "paddw", { MX, EM }, PREFIX_OPCODE }, |
2788 | { "paddd", { MX, EM } }, |
3087 | { "paddd", { MX, EM }, PREFIX_OPCODE }, |
2789 | { Bad_Opcode }, |
3088 | { Bad_Opcode }, |
2790 | }; |
3089 | }; |
2791 | 3090 | ||
2792 | static const unsigned char onebyte_has_modrm[256] = { |
3091 | static const unsigned char onebyte_has_modrm[256] = { |
2793 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3092 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2794 | /* ------------------------------- */ |
3093 | /* ------------------------------- */ |
2795 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ |
3094 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ |
2796 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ |
3095 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ |
2797 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ |
3096 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ |
2798 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ |
3097 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ |
2799 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ |
3098 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ |
2800 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ |
3099 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ |
2801 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ |
3100 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ |
2802 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ |
3101 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ |
2803 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ |
3102 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ |
2804 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ |
3103 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ |
2805 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ |
3104 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ |
2806 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ |
3105 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ |
2807 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ |
3106 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ |
2808 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ |
3107 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ |
2809 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ |
3108 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ |
2810 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ |
3109 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ |
2811 | /* ------------------------------- */ |
3110 | /* ------------------------------- */ |
2812 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3111 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2813 | }; |
3112 | }; |
2814 | 3113 | ||
2815 | static const unsigned char twobyte_has_modrm[256] = { |
3114 | static const unsigned char twobyte_has_modrm[256] = { |
2816 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3115 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2817 | /* ------------------------------- */ |
3116 | /* ------------------------------- */ |
2818 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
3117 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
2819 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
3118 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
2820 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
3119 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
2821 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
3120 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
2822 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
3121 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
2823 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
3122 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2824 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ |
3123 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ |
2825 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
3124 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
2826 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
3125 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2827 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ |
3126 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ |
2828 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
3127 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
2829 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
3128 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
2830 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
3129 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
2831 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
3130 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
2832 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
3131 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
2833 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
3132 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
2834 | /* ------------------------------- */ |
3133 | /* ------------------------------- */ |
2835 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3134 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2836 | }; |
3135 | }; |
2837 | 3136 | ||
2838 | static char obuf[100]; |
3137 | static char obuf[100]; |
2839 | static char *obufp; |
3138 | static char *obufp; |
2840 | static char *mnemonicendp; |
3139 | static char *mnemonicendp; |
2841 | static char scratchbuf[100]; |
3140 | static char scratchbuf[100]; |
2842 | static unsigned char *start_codep; |
3141 | static unsigned char *start_codep; |
2843 | static unsigned char *insn_codep; |
3142 | static unsigned char *insn_codep; |
2844 | static unsigned char *codep; |
3143 | static unsigned char *codep; |
- | 3144 | static unsigned char *end_codep; |
|
2845 | static int last_lock_prefix; |
3145 | static int last_lock_prefix; |
2846 | static int last_repz_prefix; |
3146 | static int last_repz_prefix; |
2847 | static int last_repnz_prefix; |
3147 | static int last_repnz_prefix; |
2848 | static int last_data_prefix; |
3148 | static int last_data_prefix; |
2849 | static int last_addr_prefix; |
3149 | static int last_addr_prefix; |
2850 | static int last_rex_prefix; |
3150 | static int last_rex_prefix; |
2851 | static int last_seg_prefix; |
3151 | static int last_seg_prefix; |
- | 3152 | static int fwait_prefix; |
|
- | 3153 | /* The active segment register prefix. */ |
|
- | 3154 | static int active_seg_prefix; |
|
2852 | #define MAX_CODE_LENGTH 15 |
3155 | #define MAX_CODE_LENGTH 15 |
2853 | /* We can up to 14 prefixes since the maximum instruction length is |
3156 | /* We can up to 14 prefixes since the maximum instruction length is |
2854 | 15bytes. */ |
3157 | 15bytes. */ |
2855 | static int all_prefixes[MAX_CODE_LENGTH - 1]; |
3158 | static int all_prefixes[MAX_CODE_LENGTH - 1]; |
2856 | static disassemble_info *the_info; |
3159 | static disassemble_info *the_info; |
2857 | static struct |
3160 | static struct |
2858 | { |
3161 | { |
2859 | int mod; |
3162 | int mod; |
2860 | int reg; |
3163 | int reg; |
2861 | int rm; |
3164 | int rm; |
2862 | } |
3165 | } |
2863 | modrm; |
3166 | modrm; |
2864 | static unsigned char need_modrm; |
3167 | static unsigned char need_modrm; |
2865 | static struct |
3168 | static struct |
2866 | { |
3169 | { |
2867 | int scale; |
3170 | int scale; |
2868 | int index; |
3171 | int index; |
2869 | int base; |
3172 | int base; |
2870 | } |
3173 | } |
2871 | sib; |
3174 | sib; |
2872 | static struct |
3175 | static struct |
2873 | { |
3176 | { |
2874 | int register_specifier; |
3177 | int register_specifier; |
2875 | int length; |
3178 | int length; |
2876 | int prefix; |
3179 | int prefix; |
2877 | int w; |
3180 | int w; |
2878 | int evex; |
3181 | int evex; |
2879 | int r; |
3182 | int r; |
2880 | int v; |
3183 | int v; |
2881 | int mask_register_specifier; |
3184 | int mask_register_specifier; |
2882 | int zeroing; |
3185 | int zeroing; |
2883 | int ll; |
3186 | int ll; |
2884 | int b; |
3187 | int b; |
2885 | } |
3188 | } |
2886 | vex; |
3189 | vex; |
2887 | static unsigned char need_vex; |
3190 | static unsigned char need_vex; |
2888 | static unsigned char need_vex_reg; |
3191 | static unsigned char need_vex_reg; |
2889 | static unsigned char vex_w_done; |
3192 | static unsigned char vex_w_done; |
2890 | 3193 | ||
2891 | struct op |
3194 | struct op |
2892 | { |
3195 | { |
2893 | const char *name; |
3196 | const char *name; |
2894 | unsigned int len; |
3197 | unsigned int len; |
2895 | }; |
3198 | }; |
2896 | 3199 | ||
2897 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3200 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2898 | values are stale. Hitting this abort likely indicates that you |
3201 | values are stale. Hitting this abort likely indicates that you |
2899 | need to update onebyte_has_modrm or twobyte_has_modrm. */ |
3202 | need to update onebyte_has_modrm or twobyte_has_modrm. */ |
2900 | #define MODRM_CHECK if (!need_modrm) abort () |
3203 | #define MODRM_CHECK if (!need_modrm) abort () |
2901 | 3204 | ||
2902 | static const char **names64; |
3205 | static const char **names64; |
2903 | static const char **names32; |
3206 | static const char **names32; |
2904 | static const char **names16; |
3207 | static const char **names16; |
2905 | static const char **names8; |
3208 | static const char **names8; |
2906 | static const char **names8rex; |
3209 | static const char **names8rex; |
2907 | static const char **names_seg; |
3210 | static const char **names_seg; |
2908 | static const char *index64; |
3211 | static const char *index64; |
2909 | static const char *index32; |
3212 | static const char *index32; |
2910 | static const char **index16; |
3213 | static const char **index16; |
2911 | static const char **names_bnd; |
3214 | static const char **names_bnd; |
2912 | 3215 | ||
2913 | static const char *intel_names64[] = { |
3216 | static const char *intel_names64[] = { |
2914 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", |
3217 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", |
2915 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
3218 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
2916 | }; |
3219 | }; |
2917 | static const char *intel_names32[] = { |
3220 | static const char *intel_names32[] = { |
2918 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", |
3221 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", |
2919 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" |
3222 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" |
2920 | }; |
3223 | }; |
2921 | static const char *intel_names16[] = { |
3224 | static const char *intel_names16[] = { |
2922 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", |
3225 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", |
2923 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" |
3226 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" |
2924 | }; |
3227 | }; |
2925 | static const char *intel_names8[] = { |
3228 | static const char *intel_names8[] = { |
2926 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", |
3229 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", |
2927 | }; |
3230 | }; |
2928 | static const char *intel_names8rex[] = { |
3231 | static const char *intel_names8rex[] = { |
2929 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", |
3232 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", |
2930 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" |
3233 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" |
2931 | }; |
3234 | }; |
2932 | static const char *intel_names_seg[] = { |
3235 | static const char *intel_names_seg[] = { |
2933 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", |
3236 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", |
2934 | }; |
3237 | }; |
2935 | static const char *intel_index64 = "riz"; |
3238 | static const char *intel_index64 = "riz"; |
2936 | static const char *intel_index32 = "eiz"; |
3239 | static const char *intel_index32 = "eiz"; |
2937 | static const char *intel_index16[] = { |
3240 | static const char *intel_index16[] = { |
2938 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" |
3241 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" |
2939 | }; |
3242 | }; |
2940 | 3243 | ||
2941 | static const char *att_names64[] = { |
3244 | static const char *att_names64[] = { |
2942 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", |
3245 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", |
2943 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3246 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2944 | }; |
3247 | }; |
2945 | static const char *att_names32[] = { |
3248 | static const char *att_names32[] = { |
2946 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", |
3249 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", |
2947 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
3250 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
2948 | }; |
3251 | }; |
2949 | static const char *att_names16[] = { |
3252 | static const char *att_names16[] = { |
2950 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", |
3253 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", |
2951 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
3254 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
2952 | }; |
3255 | }; |
2953 | static const char *att_names8[] = { |
3256 | static const char *att_names8[] = { |
2954 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", |
3257 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", |
2955 | }; |
3258 | }; |
2956 | static const char *att_names8rex[] = { |
3259 | static const char *att_names8rex[] = { |
2957 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", |
3260 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", |
2958 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3261 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2959 | }; |
3262 | }; |
2960 | static const char *att_names_seg[] = { |
3263 | static const char *att_names_seg[] = { |
2961 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", |
3264 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", |
2962 | }; |
3265 | }; |
2963 | static const char *att_index64 = "%riz"; |
3266 | static const char *att_index64 = "%riz"; |
2964 | static const char *att_index32 = "%eiz"; |
3267 | static const char *att_index32 = "%eiz"; |
2965 | static const char *att_index16[] = { |
3268 | static const char *att_index16[] = { |
2966 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" |
3269 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" |
2967 | }; |
3270 | }; |
2968 | 3271 | ||
2969 | static const char **names_mm; |
3272 | static const char **names_mm; |
2970 | static const char *intel_names_mm[] = { |
3273 | static const char *intel_names_mm[] = { |
2971 | "mm0", "mm1", "mm2", "mm3", |
3274 | "mm0", "mm1", "mm2", "mm3", |
2972 | "mm4", "mm5", "mm6", "mm7" |
3275 | "mm4", "mm5", "mm6", "mm7" |
2973 | }; |
3276 | }; |
2974 | static const char *att_names_mm[] = { |
3277 | static const char *att_names_mm[] = { |
2975 | "%mm0", "%mm1", "%mm2", "%mm3", |
3278 | "%mm0", "%mm1", "%mm2", "%mm3", |
2976 | "%mm4", "%mm5", "%mm6", "%mm7" |
3279 | "%mm4", "%mm5", "%mm6", "%mm7" |
2977 | }; |
3280 | }; |
2978 | 3281 | ||
2979 | static const char *intel_names_bnd[] = { |
3282 | static const char *intel_names_bnd[] = { |
2980 | "bnd0", "bnd1", "bnd2", "bnd3" |
3283 | "bnd0", "bnd1", "bnd2", "bnd3" |
2981 | }; |
3284 | }; |
2982 | 3285 | ||
2983 | static const char *att_names_bnd[] = { |
3286 | static const char *att_names_bnd[] = { |
2984 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" |
3287 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" |
2985 | }; |
3288 | }; |
2986 | 3289 | ||
2987 | static const char **names_xmm; |
3290 | static const char **names_xmm; |
2988 | static const char *intel_names_xmm[] = { |
3291 | static const char *intel_names_xmm[] = { |
2989 | "xmm0", "xmm1", "xmm2", "xmm3", |
3292 | "xmm0", "xmm1", "xmm2", "xmm3", |
2990 | "xmm4", "xmm5", "xmm6", "xmm7", |
3293 | "xmm4", "xmm5", "xmm6", "xmm7", |
2991 | "xmm8", "xmm9", "xmm10", "xmm11", |
3294 | "xmm8", "xmm9", "xmm10", "xmm11", |
2992 | "xmm12", "xmm13", "xmm14", "xmm15", |
3295 | "xmm12", "xmm13", "xmm14", "xmm15", |
2993 | "xmm16", "xmm17", "xmm18", "xmm19", |
3296 | "xmm16", "xmm17", "xmm18", "xmm19", |
2994 | "xmm20", "xmm21", "xmm22", "xmm23", |
3297 | "xmm20", "xmm21", "xmm22", "xmm23", |
2995 | "xmm24", "xmm25", "xmm26", "xmm27", |
3298 | "xmm24", "xmm25", "xmm26", "xmm27", |
2996 | "xmm28", "xmm29", "xmm30", "xmm31" |
3299 | "xmm28", "xmm29", "xmm30", "xmm31" |
2997 | }; |
3300 | }; |
2998 | static const char *att_names_xmm[] = { |
3301 | static const char *att_names_xmm[] = { |
2999 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", |
3302 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", |
3000 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", |
3303 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", |
3001 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", |
3304 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", |
3002 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3305 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3003 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", |
3306 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", |
3004 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", |
3307 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", |
3005 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", |
3308 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", |
3006 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" |
3309 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" |
3007 | }; |
3310 | }; |
3008 | 3311 | ||
3009 | static const char **names_ymm; |
3312 | static const char **names_ymm; |
3010 | static const char *intel_names_ymm[] = { |
3313 | static const char *intel_names_ymm[] = { |
3011 | "ymm0", "ymm1", "ymm2", "ymm3", |
3314 | "ymm0", "ymm1", "ymm2", "ymm3", |
3012 | "ymm4", "ymm5", "ymm6", "ymm7", |
3315 | "ymm4", "ymm5", "ymm6", "ymm7", |
3013 | "ymm8", "ymm9", "ymm10", "ymm11", |
3316 | "ymm8", "ymm9", "ymm10", "ymm11", |
3014 | "ymm12", "ymm13", "ymm14", "ymm15", |
3317 | "ymm12", "ymm13", "ymm14", "ymm15", |
3015 | "ymm16", "ymm17", "ymm18", "ymm19", |
3318 | "ymm16", "ymm17", "ymm18", "ymm19", |
3016 | "ymm20", "ymm21", "ymm22", "ymm23", |
3319 | "ymm20", "ymm21", "ymm22", "ymm23", |
3017 | "ymm24", "ymm25", "ymm26", "ymm27", |
3320 | "ymm24", "ymm25", "ymm26", "ymm27", |
3018 | "ymm28", "ymm29", "ymm30", "ymm31" |
3321 | "ymm28", "ymm29", "ymm30", "ymm31" |
3019 | }; |
3322 | }; |
3020 | static const char *att_names_ymm[] = { |
3323 | static const char *att_names_ymm[] = { |
3021 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", |
3324 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", |
3022 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", |
3325 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", |
3023 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", |
3326 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", |
3024 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3327 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3025 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", |
3328 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", |
3026 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", |
3329 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", |
3027 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", |
3330 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", |
3028 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" |
3331 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" |
3029 | }; |
3332 | }; |
3030 | 3333 | ||
3031 | static const char **names_zmm; |
3334 | static const char **names_zmm; |
3032 | static const char *intel_names_zmm[] = { |
3335 | static const char *intel_names_zmm[] = { |
3033 | "zmm0", "zmm1", "zmm2", "zmm3", |
3336 | "zmm0", "zmm1", "zmm2", "zmm3", |
3034 | "zmm4", "zmm5", "zmm6", "zmm7", |
3337 | "zmm4", "zmm5", "zmm6", "zmm7", |
3035 | "zmm8", "zmm9", "zmm10", "zmm11", |
3338 | "zmm8", "zmm9", "zmm10", "zmm11", |
3036 | "zmm12", "zmm13", "zmm14", "zmm15", |
3339 | "zmm12", "zmm13", "zmm14", "zmm15", |
3037 | "zmm16", "zmm17", "zmm18", "zmm19", |
3340 | "zmm16", "zmm17", "zmm18", "zmm19", |
3038 | "zmm20", "zmm21", "zmm22", "zmm23", |
3341 | "zmm20", "zmm21", "zmm22", "zmm23", |
3039 | "zmm24", "zmm25", "zmm26", "zmm27", |
3342 | "zmm24", "zmm25", "zmm26", "zmm27", |
3040 | "zmm28", "zmm29", "zmm30", "zmm31" |
3343 | "zmm28", "zmm29", "zmm30", "zmm31" |
3041 | }; |
3344 | }; |
3042 | static const char *att_names_zmm[] = { |
3345 | static const char *att_names_zmm[] = { |
3043 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", |
3346 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", |
3044 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", |
3347 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", |
3045 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", |
3348 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", |
3046 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", |
3349 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", |
3047 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", |
3350 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", |
3048 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", |
3351 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", |
3049 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", |
3352 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", |
3050 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" |
3353 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" |
3051 | }; |
3354 | }; |
3052 | 3355 | ||
3053 | static const char **names_mask; |
3356 | static const char **names_mask; |
3054 | static const char *intel_names_mask[] = { |
3357 | static const char *intel_names_mask[] = { |
3055 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" |
3358 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" |
3056 | }; |
3359 | }; |
3057 | static const char *att_names_mask[] = { |
3360 | static const char *att_names_mask[] = { |
3058 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" |
3361 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" |
3059 | }; |
3362 | }; |
3060 | 3363 | ||
3061 | static const char *names_rounding[] = |
3364 | static const char *names_rounding[] = |
3062 | { |
3365 | { |
3063 | "{rn-sae}", |
3366 | "{rn-sae}", |
3064 | "{rd-sae}", |
3367 | "{rd-sae}", |
3065 | "{ru-sae}", |
3368 | "{ru-sae}", |
3066 | "{rz-sae}" |
3369 | "{rz-sae}" |
3067 | }; |
3370 | }; |
3068 | 3371 | ||
3069 | static const struct dis386 reg_table[][8] = { |
3372 | static const struct dis386 reg_table[][8] = { |
3070 | /* REG_80 */ |
3373 | /* REG_80 */ |
3071 | { |
3374 | { |
3072 | { "addA", { Ebh1, Ib } }, |
3375 | { "addA", { Ebh1, Ib }, 0 }, |
3073 | { "orA", { Ebh1, Ib } }, |
3376 | { "orA", { Ebh1, Ib }, 0 }, |
3074 | { "adcA", { Ebh1, Ib } }, |
3377 | { "adcA", { Ebh1, Ib }, 0 }, |
3075 | { "sbbA", { Ebh1, Ib } }, |
3378 | { "sbbA", { Ebh1, Ib }, 0 }, |
3076 | { "andA", { Ebh1, Ib } }, |
3379 | { "andA", { Ebh1, Ib }, 0 }, |
3077 | { "subA", { Ebh1, Ib } }, |
3380 | { "subA", { Ebh1, Ib }, 0 }, |
3078 | { "xorA", { Ebh1, Ib } }, |
3381 | { "xorA", { Ebh1, Ib }, 0 }, |
3079 | { "cmpA", { Eb, Ib } }, |
3382 | { "cmpA", { Eb, Ib }, 0 }, |
3080 | }, |
3383 | }, |
3081 | /* REG_81 */ |
3384 | /* REG_81 */ |
3082 | { |
3385 | { |
3083 | { "addQ", { Evh1, Iv } }, |
3386 | { "addQ", { Evh1, Iv }, 0 }, |
3084 | { "orQ", { Evh1, Iv } }, |
3387 | { "orQ", { Evh1, Iv }, 0 }, |
3085 | { "adcQ", { Evh1, Iv } }, |
3388 | { "adcQ", { Evh1, Iv }, 0 }, |
3086 | { "sbbQ", { Evh1, Iv } }, |
3389 | { "sbbQ", { Evh1, Iv }, 0 }, |
3087 | { "andQ", { Evh1, Iv } }, |
3390 | { "andQ", { Evh1, Iv }, 0 }, |
3088 | { "subQ", { Evh1, Iv } }, |
3391 | { "subQ", { Evh1, Iv }, 0 }, |
3089 | { "xorQ", { Evh1, Iv } }, |
3392 | { "xorQ", { Evh1, Iv }, 0 }, |
3090 | { "cmpQ", { Ev, Iv } }, |
3393 | { "cmpQ", { Ev, Iv }, 0 }, |
3091 | }, |
3394 | }, |
3092 | /* REG_82 */ |
3395 | /* REG_82 */ |
3093 | { |
3396 | { |
3094 | { "addQ", { Evh1, sIb } }, |
3397 | { "addQ", { Evh1, sIb }, 0 }, |
3095 | { "orQ", { Evh1, sIb } }, |
3398 | { "orQ", { Evh1, sIb }, 0 }, |
3096 | { "adcQ", { Evh1, sIb } }, |
3399 | { "adcQ", { Evh1, sIb }, 0 }, |
3097 | { "sbbQ", { Evh1, sIb } }, |
3400 | { "sbbQ", { Evh1, sIb }, 0 }, |
3098 | { "andQ", { Evh1, sIb } }, |
3401 | { "andQ", { Evh1, sIb }, 0 }, |
3099 | { "subQ", { Evh1, sIb } }, |
3402 | { "subQ", { Evh1, sIb }, 0 }, |
3100 | { "xorQ", { Evh1, sIb } }, |
3403 | { "xorQ", { Evh1, sIb }, 0 }, |
3101 | { "cmpQ", { Ev, sIb } }, |
3404 | { "cmpQ", { Ev, sIb }, 0 }, |
3102 | }, |
3405 | }, |
3103 | /* REG_8F */ |
3406 | /* REG_8F */ |
3104 | { |
3407 | { |
3105 | { "popU", { stackEv } }, |
3408 | { "popU", { stackEv }, 0 }, |
3106 | { XOP_8F_TABLE (XOP_09) }, |
3409 | { XOP_8F_TABLE (XOP_09) }, |
3107 | { Bad_Opcode }, |
3410 | { Bad_Opcode }, |
3108 | { Bad_Opcode }, |
3411 | { Bad_Opcode }, |
3109 | { Bad_Opcode }, |
3412 | { Bad_Opcode }, |
3110 | { XOP_8F_TABLE (XOP_09) }, |
3413 | { XOP_8F_TABLE (XOP_09) }, |
3111 | }, |
3414 | }, |
3112 | /* REG_C0 */ |
3415 | /* REG_C0 */ |
3113 | { |
3416 | { |
3114 | { "rolA", { Eb, Ib } }, |
3417 | { "rolA", { Eb, Ib }, 0 }, |
3115 | { "rorA", { Eb, Ib } }, |
3418 | { "rorA", { Eb, Ib }, 0 }, |
3116 | { "rclA", { Eb, Ib } }, |
3419 | { "rclA", { Eb, Ib }, 0 }, |
3117 | { "rcrA", { Eb, Ib } }, |
3420 | { "rcrA", { Eb, Ib }, 0 }, |
3118 | { "shlA", { Eb, Ib } }, |
3421 | { "shlA", { Eb, Ib }, 0 }, |
3119 | { "shrA", { Eb, Ib } }, |
3422 | { "shrA", { Eb, Ib }, 0 }, |
3120 | { Bad_Opcode }, |
3423 | { Bad_Opcode }, |
3121 | { "sarA", { Eb, Ib } }, |
3424 | { "sarA", { Eb, Ib }, 0 }, |
3122 | }, |
3425 | }, |
3123 | /* REG_C1 */ |
3426 | /* REG_C1 */ |
3124 | { |
3427 | { |
3125 | { "rolQ", { Ev, Ib } }, |
3428 | { "rolQ", { Ev, Ib }, 0 }, |
3126 | { "rorQ", { Ev, Ib } }, |
3429 | { "rorQ", { Ev, Ib }, 0 }, |
3127 | { "rclQ", { Ev, Ib } }, |
3430 | { "rclQ", { Ev, Ib }, 0 }, |
3128 | { "rcrQ", { Ev, Ib } }, |
3431 | { "rcrQ", { Ev, Ib }, 0 }, |
3129 | { "shlQ", { Ev, Ib } }, |
3432 | { "shlQ", { Ev, Ib }, 0 }, |
3130 | { "shrQ", { Ev, Ib } }, |
3433 | { "shrQ", { Ev, Ib }, 0 }, |
3131 | { Bad_Opcode }, |
3434 | { Bad_Opcode }, |
3132 | { "sarQ", { Ev, Ib } }, |
3435 | { "sarQ", { Ev, Ib }, 0 }, |
3133 | }, |
3436 | }, |
3134 | /* REG_C6 */ |
3437 | /* REG_C6 */ |
3135 | { |
3438 | { |
3136 | { "movA", { Ebh3, Ib } }, |
3439 | { "movA", { Ebh3, Ib }, 0 }, |
3137 | { Bad_Opcode }, |
3440 | { Bad_Opcode }, |
3138 | { Bad_Opcode }, |
3441 | { Bad_Opcode }, |
3139 | { Bad_Opcode }, |
3442 | { Bad_Opcode }, |
3140 | { Bad_Opcode }, |
3443 | { Bad_Opcode }, |
3141 | { Bad_Opcode }, |
3444 | { Bad_Opcode }, |
3142 | { Bad_Opcode }, |
3445 | { Bad_Opcode }, |
3143 | { MOD_TABLE (MOD_C6_REG_7) }, |
3446 | { MOD_TABLE (MOD_C6_REG_7) }, |
3144 | }, |
3447 | }, |
3145 | /* REG_C7 */ |
3448 | /* REG_C7 */ |
3146 | { |
3449 | { |
3147 | { "movQ", { Evh3, Iv } }, |
3450 | { "movQ", { Evh3, Iv }, 0 }, |
3148 | { Bad_Opcode }, |
3451 | { Bad_Opcode }, |
3149 | { Bad_Opcode }, |
3452 | { Bad_Opcode }, |
3150 | { Bad_Opcode }, |
3453 | { Bad_Opcode }, |
3151 | { Bad_Opcode }, |
3454 | { Bad_Opcode }, |
3152 | { Bad_Opcode }, |
3455 | { Bad_Opcode }, |
3153 | { Bad_Opcode }, |
3456 | { Bad_Opcode }, |
3154 | { MOD_TABLE (MOD_C7_REG_7) }, |
3457 | { MOD_TABLE (MOD_C7_REG_7) }, |
3155 | }, |
3458 | }, |
3156 | /* REG_D0 */ |
3459 | /* REG_D0 */ |
3157 | { |
3460 | { |
3158 | { "rolA", { Eb, I1 } }, |
3461 | { "rolA", { Eb, I1 }, 0 }, |
3159 | { "rorA", { Eb, I1 } }, |
3462 | { "rorA", { Eb, I1 }, 0 }, |
3160 | { "rclA", { Eb, I1 } }, |
3463 | { "rclA", { Eb, I1 }, 0 }, |
3161 | { "rcrA", { Eb, I1 } }, |
3464 | { "rcrA", { Eb, I1 }, 0 }, |
3162 | { "shlA", { Eb, I1 } }, |
3465 | { "shlA", { Eb, I1 }, 0 }, |
3163 | { "shrA", { Eb, I1 } }, |
3466 | { "shrA", { Eb, I1 }, 0 }, |
3164 | { Bad_Opcode }, |
3467 | { Bad_Opcode }, |
3165 | { "sarA", { Eb, I1 } }, |
3468 | { "sarA", { Eb, I1 }, 0 }, |
3166 | }, |
3469 | }, |
3167 | /* REG_D1 */ |
3470 | /* REG_D1 */ |
3168 | { |
3471 | { |
3169 | { "rolQ", { Ev, I1 } }, |
3472 | { "rolQ", { Ev, I1 }, 0 }, |
3170 | { "rorQ", { Ev, I1 } }, |
3473 | { "rorQ", { Ev, I1 }, 0 }, |
3171 | { "rclQ", { Ev, I1 } }, |
3474 | { "rclQ", { Ev, I1 }, 0 }, |
3172 | { "rcrQ", { Ev, I1 } }, |
3475 | { "rcrQ", { Ev, I1 }, 0 }, |
3173 | { "shlQ", { Ev, I1 } }, |
3476 | { "shlQ", { Ev, I1 }, 0 }, |
3174 | { "shrQ", { Ev, I1 } }, |
3477 | { "shrQ", { Ev, I1 }, 0 }, |
3175 | { Bad_Opcode }, |
3478 | { Bad_Opcode }, |
3176 | { "sarQ", { Ev, I1 } }, |
3479 | { "sarQ", { Ev, I1 }, 0 }, |
3177 | }, |
3480 | }, |
3178 | /* REG_D2 */ |
3481 | /* REG_D2 */ |
3179 | { |
3482 | { |
3180 | { "rolA", { Eb, CL } }, |
3483 | { "rolA", { Eb, CL }, 0 }, |
3181 | { "rorA", { Eb, CL } }, |
3484 | { "rorA", { Eb, CL }, 0 }, |
3182 | { "rclA", { Eb, CL } }, |
3485 | { "rclA", { Eb, CL }, 0 }, |
3183 | { "rcrA", { Eb, CL } }, |
3486 | { "rcrA", { Eb, CL }, 0 }, |
3184 | { "shlA", { Eb, CL } }, |
3487 | { "shlA", { Eb, CL }, 0 }, |
3185 | { "shrA", { Eb, CL } }, |
3488 | { "shrA", { Eb, CL }, 0 }, |
3186 | { Bad_Opcode }, |
3489 | { Bad_Opcode }, |
3187 | { "sarA", { Eb, CL } }, |
3490 | { "sarA", { Eb, CL }, 0 }, |
3188 | }, |
3491 | }, |
3189 | /* REG_D3 */ |
3492 | /* REG_D3 */ |
3190 | { |
3493 | { |
3191 | { "rolQ", { Ev, CL } }, |
3494 | { "rolQ", { Ev, CL }, 0 }, |
3192 | { "rorQ", { Ev, CL } }, |
3495 | { "rorQ", { Ev, CL }, 0 }, |
3193 | { "rclQ", { Ev, CL } }, |
3496 | { "rclQ", { Ev, CL }, 0 }, |
3194 | { "rcrQ", { Ev, CL } }, |
3497 | { "rcrQ", { Ev, CL }, 0 }, |
3195 | { "shlQ", { Ev, CL } }, |
3498 | { "shlQ", { Ev, CL }, 0 }, |
3196 | { "shrQ", { Ev, CL } }, |
3499 | { "shrQ", { Ev, CL }, 0 }, |
3197 | { Bad_Opcode }, |
3500 | { Bad_Opcode }, |
3198 | { "sarQ", { Ev, CL } }, |
3501 | { "sarQ", { Ev, CL }, 0 }, |
3199 | }, |
3502 | }, |
3200 | /* REG_F6 */ |
3503 | /* REG_F6 */ |
3201 | { |
3504 | { |
3202 | { "testA", { Eb, Ib } }, |
3505 | { "testA", { Eb, Ib }, 0 }, |
3203 | { Bad_Opcode }, |
3506 | { Bad_Opcode }, |
3204 | { "notA", { Ebh1 } }, |
3507 | { "notA", { Ebh1 }, 0 }, |
3205 | { "negA", { Ebh1 } }, |
3508 | { "negA", { Ebh1 }, 0 }, |
3206 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ |
3509 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ |
3207 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ |
3510 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ |
3208 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ |
3511 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ |
3209 | { "idivA", { Eb } }, /* and idiv for consistency. */ |
3512 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ |
3210 | }, |
3513 | }, |
3211 | /* REG_F7 */ |
3514 | /* REG_F7 */ |
3212 | { |
3515 | { |
3213 | { "testQ", { Ev, Iv } }, |
3516 | { "testQ", { Ev, Iv }, 0 }, |
3214 | { Bad_Opcode }, |
3517 | { Bad_Opcode }, |
3215 | { "notQ", { Evh1 } }, |
3518 | { "notQ", { Evh1 }, 0 }, |
3216 | { "negQ", { Evh1 } }, |
3519 | { "negQ", { Evh1 }, 0 }, |
3217 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ |
3520 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ |
3218 | { "imulQ", { Ev } }, |
3521 | { "imulQ", { Ev }, 0 }, |
3219 | { "divQ", { Ev } }, |
3522 | { "divQ", { Ev }, 0 }, |
3220 | { "idivQ", { Ev } }, |
3523 | { "idivQ", { Ev }, 0 }, |
3221 | }, |
3524 | }, |
3222 | /* REG_FE */ |
3525 | /* REG_FE */ |
3223 | { |
3526 | { |
3224 | { "incA", { Ebh1 } }, |
3527 | { "incA", { Ebh1 }, 0 }, |
3225 | { "decA", { Ebh1 } }, |
3528 | { "decA", { Ebh1 }, 0 }, |
3226 | }, |
3529 | }, |
3227 | /* REG_FF */ |
3530 | /* REG_FF */ |
3228 | { |
3531 | { |
3229 | { "incQ", { Evh1 } }, |
3532 | { "incQ", { Evh1 }, 0 }, |
3230 | { "decQ", { Evh1 } }, |
3533 | { "decQ", { Evh1 }, 0 }, |
3231 | { "call{T|}", { indirEv, BND } }, |
3534 | { "call{T|}", { indirEv, BND }, 0 }, |
3232 | { "Jcall{T|}", { indirEp } }, |
3535 | { MOD_TABLE (MOD_FF_REG_3) }, |
3233 | { "jmp{T|}", { indirEv, BND } }, |
3536 | { "jmp{T|}", { indirEv, BND }, 0 }, |
3234 | { "Jjmp{T|}", { indirEp } }, |
3537 | { MOD_TABLE (MOD_FF_REG_5) }, |
3235 | { "pushU", { stackEv } }, |
3538 | { "pushU", { stackEv }, 0 }, |
3236 | { Bad_Opcode }, |
3539 | { Bad_Opcode }, |
3237 | }, |
3540 | }, |
3238 | /* REG_0F00 */ |
3541 | /* REG_0F00 */ |
3239 | { |
3542 | { |
3240 | { "sldtD", { Sv } }, |
3543 | { "sldtD", { Sv }, 0 }, |
3241 | { "strD", { Sv } }, |
3544 | { "strD", { Sv }, 0 }, |
3242 | { "lldt", { Ew } }, |
3545 | { "lldt", { Ew }, 0 }, |
3243 | { "ltr", { Ew } }, |
3546 | { "ltr", { Ew }, 0 }, |
3244 | { "verr", { Ew } }, |
3547 | { "verr", { Ew }, 0 }, |
3245 | { "verw", { Ew } }, |
3548 | { "verw", { Ew }, 0 }, |
3246 | { Bad_Opcode }, |
3549 | { Bad_Opcode }, |
3247 | { Bad_Opcode }, |
3550 | { Bad_Opcode }, |
3248 | }, |
3551 | }, |
3249 | /* REG_0F01 */ |
3552 | /* REG_0F01 */ |
3250 | { |
3553 | { |
3251 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3554 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3252 | { MOD_TABLE (MOD_0F01_REG_1) }, |
3555 | { MOD_TABLE (MOD_0F01_REG_1) }, |
3253 | { MOD_TABLE (MOD_0F01_REG_2) }, |
3556 | { MOD_TABLE (MOD_0F01_REG_2) }, |
3254 | { MOD_TABLE (MOD_0F01_REG_3) }, |
3557 | { MOD_TABLE (MOD_0F01_REG_3) }, |
3255 | { "smswD", { Sv } }, |
3558 | { "smswD", { Sv }, 0 }, |
3256 | { Bad_Opcode }, |
3559 | { MOD_TABLE (MOD_0F01_REG_5) }, |
3257 | { "lmsw", { Ew } }, |
3560 | { "lmsw", { Ew }, 0 }, |
3258 | { MOD_TABLE (MOD_0F01_REG_7) }, |
3561 | { MOD_TABLE (MOD_0F01_REG_7) }, |
3259 | }, |
3562 | }, |
3260 | /* REG_0F0D */ |
3563 | /* REG_0F0D */ |
3261 | { |
3564 | { |
3262 | { "prefetch", { Mb } }, |
3565 | { "prefetch", { Mb }, 0 }, |
3263 | { "prefetchw", { Mb } }, |
3566 | { "prefetchw", { Mb }, 0 }, |
3264 | { "prefetchwt1", { Mb } }, |
3567 | { "prefetchwt1", { Mb }, 0 }, |
3265 | { "prefetch", { Mb } }, |
3568 | { "prefetch", { Mb }, 0 }, |
3266 | { "prefetch", { Mb } }, |
3569 | { "prefetch", { Mb }, 0 }, |
3267 | { "prefetch", { Mb } }, |
3570 | { "prefetch", { Mb }, 0 }, |
3268 | { "prefetch", { Mb } }, |
3571 | { "prefetch", { Mb }, 0 }, |
3269 | { "prefetch", { Mb } }, |
3572 | { "prefetch", { Mb }, 0 }, |
3270 | }, |
3573 | }, |
3271 | /* REG_0F18 */ |
3574 | /* REG_0F18 */ |
3272 | { |
3575 | { |
3273 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3576 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3274 | { MOD_TABLE (MOD_0F18_REG_1) }, |
3577 | { MOD_TABLE (MOD_0F18_REG_1) }, |
3275 | { MOD_TABLE (MOD_0F18_REG_2) }, |
3578 | { MOD_TABLE (MOD_0F18_REG_2) }, |
3276 | { MOD_TABLE (MOD_0F18_REG_3) }, |
3579 | { MOD_TABLE (MOD_0F18_REG_3) }, |
3277 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3580 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3278 | { MOD_TABLE (MOD_0F18_REG_5) }, |
3581 | { MOD_TABLE (MOD_0F18_REG_5) }, |
3279 | { MOD_TABLE (MOD_0F18_REG_6) }, |
3582 | { MOD_TABLE (MOD_0F18_REG_6) }, |
3280 | { MOD_TABLE (MOD_0F18_REG_7) }, |
3583 | { MOD_TABLE (MOD_0F18_REG_7) }, |
3281 | }, |
3584 | }, |
3282 | /* REG_0F71 */ |
3585 | /* REG_0F71 */ |
3283 | { |
3586 | { |
3284 | { Bad_Opcode }, |
3587 | { Bad_Opcode }, |
3285 | { Bad_Opcode }, |
3588 | { Bad_Opcode }, |
3286 | { MOD_TABLE (MOD_0F71_REG_2) }, |
3589 | { MOD_TABLE (MOD_0F71_REG_2) }, |
3287 | { Bad_Opcode }, |
3590 | { Bad_Opcode }, |
3288 | { MOD_TABLE (MOD_0F71_REG_4) }, |
3591 | { MOD_TABLE (MOD_0F71_REG_4) }, |
3289 | { Bad_Opcode }, |
3592 | { Bad_Opcode }, |
3290 | { MOD_TABLE (MOD_0F71_REG_6) }, |
3593 | { MOD_TABLE (MOD_0F71_REG_6) }, |
3291 | }, |
3594 | }, |
3292 | /* REG_0F72 */ |
3595 | /* REG_0F72 */ |
3293 | { |
3596 | { |
3294 | { Bad_Opcode }, |
3597 | { Bad_Opcode }, |
3295 | { Bad_Opcode }, |
3598 | { Bad_Opcode }, |
3296 | { MOD_TABLE (MOD_0F72_REG_2) }, |
3599 | { MOD_TABLE (MOD_0F72_REG_2) }, |
3297 | { Bad_Opcode }, |
3600 | { Bad_Opcode }, |
3298 | { MOD_TABLE (MOD_0F72_REG_4) }, |
3601 | { MOD_TABLE (MOD_0F72_REG_4) }, |
3299 | { Bad_Opcode }, |
3602 | { Bad_Opcode }, |
3300 | { MOD_TABLE (MOD_0F72_REG_6) }, |
3603 | { MOD_TABLE (MOD_0F72_REG_6) }, |
3301 | }, |
3604 | }, |
3302 | /* REG_0F73 */ |
3605 | /* REG_0F73 */ |
3303 | { |
3606 | { |
3304 | { Bad_Opcode }, |
3607 | { Bad_Opcode }, |
3305 | { Bad_Opcode }, |
3608 | { Bad_Opcode }, |
3306 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3609 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3307 | { MOD_TABLE (MOD_0F73_REG_3) }, |
3610 | { MOD_TABLE (MOD_0F73_REG_3) }, |
3308 | { Bad_Opcode }, |
3611 | { Bad_Opcode }, |
3309 | { Bad_Opcode }, |
3612 | { Bad_Opcode }, |
3310 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3613 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3311 | { MOD_TABLE (MOD_0F73_REG_7) }, |
3614 | { MOD_TABLE (MOD_0F73_REG_7) }, |
3312 | }, |
3615 | }, |
3313 | /* REG_0FA6 */ |
3616 | /* REG_0FA6 */ |
3314 | { |
3617 | { |
3315 | { "montmul", { { OP_0f07, 0 } } }, |
3618 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3316 | { "xsha1", { { OP_0f07, 0 } } }, |
3619 | { "xsha1", { { OP_0f07, 0 } }, 0 }, |
3317 | { "xsha256", { { OP_0f07, 0 } } }, |
3620 | { "xsha256", { { OP_0f07, 0 } }, 0 }, |
3318 | }, |
3621 | }, |
3319 | /* REG_0FA7 */ |
3622 | /* REG_0FA7 */ |
3320 | { |
3623 | { |
3321 | { "xstore-rng", { { OP_0f07, 0 } } }, |
3624 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3322 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, |
3625 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, |
3323 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, |
3626 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, |
3324 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, |
3627 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, |
3325 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, |
3628 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, |
3326 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, |
3629 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, |
3327 | }, |
3630 | }, |
3328 | /* REG_0FAE */ |
3631 | /* REG_0FAE */ |
3329 | { |
3632 | { |
3330 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3633 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3331 | { MOD_TABLE (MOD_0FAE_REG_1) }, |
3634 | { MOD_TABLE (MOD_0FAE_REG_1) }, |
3332 | { MOD_TABLE (MOD_0FAE_REG_2) }, |
3635 | { MOD_TABLE (MOD_0FAE_REG_2) }, |
3333 | { MOD_TABLE (MOD_0FAE_REG_3) }, |
3636 | { MOD_TABLE (MOD_0FAE_REG_3) }, |
3334 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
3637 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
3335 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3638 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3336 | { MOD_TABLE (MOD_0FAE_REG_6) }, |
3639 | { MOD_TABLE (MOD_0FAE_REG_6) }, |
3337 | { MOD_TABLE (MOD_0FAE_REG_7) }, |
3640 | { MOD_TABLE (MOD_0FAE_REG_7) }, |
3338 | }, |
3641 | }, |
3339 | /* REG_0FBA */ |
3642 | /* REG_0FBA */ |
3340 | { |
3643 | { |
3341 | { Bad_Opcode }, |
3644 | { Bad_Opcode }, |
3342 | { Bad_Opcode }, |
3645 | { Bad_Opcode }, |
3343 | { Bad_Opcode }, |
3646 | { Bad_Opcode }, |
3344 | { Bad_Opcode }, |
3647 | { Bad_Opcode }, |
3345 | { "btQ", { Ev, Ib } }, |
3648 | { "btQ", { Ev, Ib }, 0 }, |
3346 | { "btsQ", { Evh1, Ib } }, |
3649 | { "btsQ", { Evh1, Ib }, 0 }, |
3347 | { "btrQ", { Evh1, Ib } }, |
3650 | { "btrQ", { Evh1, Ib }, 0 }, |
3348 | { "btcQ", { Evh1, Ib } }, |
3651 | { "btcQ", { Evh1, Ib }, 0 }, |
3349 | }, |
3652 | }, |
3350 | /* REG_0FC7 */ |
3653 | /* REG_0FC7 */ |
3351 | { |
3654 | { |
3352 | { Bad_Opcode }, |
3655 | { Bad_Opcode }, |
3353 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
3656 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
3354 | { Bad_Opcode }, |
- | |
3355 | { Bad_Opcode }, |
- | |
3356 | { Bad_Opcode }, |
- | |
3357 | { Bad_Opcode }, |
3657 | { Bad_Opcode }, |
- | 3658 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
|
- | 3659 | { MOD_TABLE (MOD_0FC7_REG_4) }, |
|
- | 3660 | { MOD_TABLE (MOD_0FC7_REG_5) }, |
|
3358 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3661 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3359 | { MOD_TABLE (MOD_0FC7_REG_7) }, |
3662 | { MOD_TABLE (MOD_0FC7_REG_7) }, |
3360 | }, |
3663 | }, |
3361 | /* REG_VEX_0F71 */ |
3664 | /* REG_VEX_0F71 */ |
3362 | { |
3665 | { |
3363 | { Bad_Opcode }, |
3666 | { Bad_Opcode }, |
3364 | { Bad_Opcode }, |
3667 | { Bad_Opcode }, |
3365 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
3668 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
3366 | { Bad_Opcode }, |
3669 | { Bad_Opcode }, |
3367 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
3670 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
3368 | { Bad_Opcode }, |
3671 | { Bad_Opcode }, |
3369 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
3672 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
3370 | }, |
3673 | }, |
3371 | /* REG_VEX_0F72 */ |
3674 | /* REG_VEX_0F72 */ |
3372 | { |
3675 | { |
3373 | { Bad_Opcode }, |
3676 | { Bad_Opcode }, |
3374 | { Bad_Opcode }, |
3677 | { Bad_Opcode }, |
3375 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
3678 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
3376 | { Bad_Opcode }, |
3679 | { Bad_Opcode }, |
3377 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
3680 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
3378 | { Bad_Opcode }, |
3681 | { Bad_Opcode }, |
3379 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
3682 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
3380 | }, |
3683 | }, |
3381 | /* REG_VEX_0F73 */ |
3684 | /* REG_VEX_0F73 */ |
3382 | { |
3685 | { |
3383 | { Bad_Opcode }, |
3686 | { Bad_Opcode }, |
3384 | { Bad_Opcode }, |
3687 | { Bad_Opcode }, |
3385 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3688 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3386 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, |
3689 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, |
3387 | { Bad_Opcode }, |
3690 | { Bad_Opcode }, |
3388 | { Bad_Opcode }, |
3691 | { Bad_Opcode }, |
3389 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3692 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3390 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, |
3693 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, |
3391 | }, |
3694 | }, |
3392 | /* REG_VEX_0FAE */ |
3695 | /* REG_VEX_0FAE */ |
3393 | { |
3696 | { |
3394 | { Bad_Opcode }, |
3697 | { Bad_Opcode }, |
3395 | { Bad_Opcode }, |
3698 | { Bad_Opcode }, |
3396 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3699 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3397 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, |
3700 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, |
3398 | }, |
3701 | }, |
3399 | /* REG_VEX_0F38F3 */ |
3702 | /* REG_VEX_0F38F3 */ |
3400 | { |
3703 | { |
3401 | { Bad_Opcode }, |
3704 | { Bad_Opcode }, |
3402 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, |
3705 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, |
3403 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, |
3706 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, |
3404 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, |
3707 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, |
3405 | }, |
3708 | }, |
3406 | /* REG_XOP_LWPCB */ |
3709 | /* REG_XOP_LWPCB */ |
3407 | { |
3710 | { |
3408 | { "llwpcb", { { OP_LWPCB_E, 0 } } }, |
3711 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3409 | { "slwpcb", { { OP_LWPCB_E, 0 } } }, |
3712 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3410 | }, |
3713 | }, |
3411 | /* REG_XOP_LWP */ |
3714 | /* REG_XOP_LWP */ |
3412 | { |
3715 | { |
3413 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, |
3716 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3414 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, |
3717 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3415 | }, |
3718 | }, |
3416 | /* REG_XOP_TBM_01 */ |
3719 | /* REG_XOP_TBM_01 */ |
3417 | { |
3720 | { |
3418 | { Bad_Opcode }, |
3721 | { Bad_Opcode }, |
3419 | { "blcfill", { { OP_LWP_E, 0 }, Ev } }, |
3722 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3420 | { "blsfill", { { OP_LWP_E, 0 }, Ev } }, |
3723 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3421 | { "blcs", { { OP_LWP_E, 0 }, Ev } }, |
3724 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3422 | { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, |
3725 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3423 | { "blcic", { { OP_LWP_E, 0 }, Ev } }, |
3726 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3424 | { "blsic", { { OP_LWP_E, 0 }, Ev } }, |
3727 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3425 | { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, |
3728 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3426 | }, |
3729 | }, |
3427 | /* REG_XOP_TBM_02 */ |
3730 | /* REG_XOP_TBM_02 */ |
3428 | { |
3731 | { |
3429 | { Bad_Opcode }, |
3732 | { Bad_Opcode }, |
3430 | { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, |
3733 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3431 | { Bad_Opcode }, |
3734 | { Bad_Opcode }, |
3432 | { Bad_Opcode }, |
3735 | { Bad_Opcode }, |
3433 | { Bad_Opcode }, |
3736 | { Bad_Opcode }, |
3434 | { Bad_Opcode }, |
3737 | { Bad_Opcode }, |
3435 | { "blci", { { OP_LWP_E, 0 }, Ev } }, |
3738 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3436 | }, |
3739 | }, |
3437 | #define NEED_REG_TABLE |
3740 | #define NEED_REG_TABLE |
3438 | #include "i386-dis-evex.h" |
3741 | #include "i386-dis-evex.h" |
3439 | #undef NEED_REG_TABLE |
3742 | #undef NEED_REG_TABLE |
3440 | }; |
3743 | }; |
3441 | 3744 | ||
3442 | static const struct dis386 prefix_table[][4] = { |
3745 | static const struct dis386 prefix_table[][4] = { |
3443 | /* PREFIX_90 */ |
3746 | /* PREFIX_90 */ |
3444 | { |
3747 | { |
3445 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
3748 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3446 | { "pause", { XX } }, |
3749 | { "pause", { XX }, 0 }, |
3447 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
3750 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
- | 3751 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
|
3448 | }, |
3752 | }, |
3449 | 3753 | ||
3450 | /* PREFIX_0F10 */ |
3754 | /* PREFIX_0F10 */ |
3451 | { |
3755 | { |
3452 | { "movups", { XM, EXx } }, |
3756 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3453 | { "movss", { XM, EXd } }, |
3757 | { "movss", { XM, EXd }, PREFIX_OPCODE }, |
3454 | { "movupd", { XM, EXx } }, |
3758 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, |
3455 | { "movsd", { XM, EXq } }, |
3759 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, |
3456 | }, |
3760 | }, |
3457 | 3761 | ||
3458 | /* PREFIX_0F11 */ |
3762 | /* PREFIX_0F11 */ |
3459 | { |
3763 | { |
3460 | { "movups", { EXxS, XM } }, |
3764 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3461 | { "movss", { EXdS, XM } }, |
3765 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, |
3462 | { "movupd", { EXxS, XM } }, |
3766 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, |
3463 | { "movsd", { EXqS, XM } }, |
3767 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, |
3464 | }, |
3768 | }, |
3465 | 3769 | ||
3466 | /* PREFIX_0F12 */ |
3770 | /* PREFIX_0F12 */ |
3467 | { |
3771 | { |
3468 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
3772 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
3469 | { "movsldup", { XM, EXx } }, |
3773 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3470 | { "movlpd", { XM, EXq } }, |
3774 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, |
3471 | { "movddup", { XM, EXq } }, |
3775 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
3472 | }, |
3776 | }, |
3473 | 3777 | ||
3474 | /* PREFIX_0F16 */ |
3778 | /* PREFIX_0F16 */ |
3475 | { |
3779 | { |
3476 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
3780 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
3477 | { "movshdup", { XM, EXx } }, |
3781 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3478 | { "movhpd", { XM, EXq } }, |
3782 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, |
3479 | }, |
3783 | }, |
3480 | 3784 | ||
3481 | /* PREFIX_0F1A */ |
3785 | /* PREFIX_0F1A */ |
3482 | { |
3786 | { |
3483 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, |
3787 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, |
3484 | { "bndcl", { Gbnd, Ev_bnd } }, |
3788 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3485 | { "bndmov", { Gbnd, Ebnd } }, |
3789 | { "bndmov", { Gbnd, Ebnd }, 0 }, |
3486 | { "bndcu", { Gbnd, Ev_bnd } }, |
3790 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, |
3487 | }, |
3791 | }, |
3488 | 3792 | ||
3489 | /* PREFIX_0F1B */ |
3793 | /* PREFIX_0F1B */ |
3490 | { |
3794 | { |
3491 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, |
3795 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, |
3492 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, |
3796 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, |
3493 | { "bndmov", { Ebnd, Gbnd } }, |
3797 | { "bndmov", { Ebnd, Gbnd }, 0 }, |
3494 | { "bndcn", { Gbnd, Ev_bnd } }, |
3798 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
3495 | }, |
3799 | }, |
3496 | 3800 | ||
3497 | /* PREFIX_0F2A */ |
3801 | /* PREFIX_0F2A */ |
3498 | { |
3802 | { |
3499 | { "cvtpi2ps", { XM, EMCq } }, |
3803 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3500 | { "cvtsi2ss%LQ", { XM, Ev } }, |
3804 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, |
3501 | { "cvtpi2pd", { XM, EMCq } }, |
3805 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
3502 | { "cvtsi2sd%LQ", { XM, Ev } }, |
3806 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
3503 | }, |
3807 | }, |
3504 | 3808 | ||
3505 | /* PREFIX_0F2B */ |
3809 | /* PREFIX_0F2B */ |
3506 | { |
3810 | { |
3507 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3811 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3508 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, |
3812 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, |
3509 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, |
3813 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, |
3510 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, |
3814 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, |
3511 | }, |
3815 | }, |
3512 | 3816 | ||
3513 | /* PREFIX_0F2C */ |
3817 | /* PREFIX_0F2C */ |
3514 | { |
3818 | { |
3515 | { "cvttps2pi", { MXC, EXq } }, |
3819 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3516 | { "cvttss2siY", { Gv, EXd } }, |
3820 | { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, |
3517 | { "cvttpd2pi", { MXC, EXx } }, |
3821 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
3518 | { "cvttsd2siY", { Gv, EXq } }, |
3822 | { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, |
3519 | }, |
3823 | }, |
3520 | 3824 | ||
3521 | /* PREFIX_0F2D */ |
3825 | /* PREFIX_0F2D */ |
3522 | { |
3826 | { |
3523 | { "cvtps2pi", { MXC, EXq } }, |
3827 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3524 | { "cvtss2siY", { Gv, EXd } }, |
3828 | { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, |
3525 | { "cvtpd2pi", { MXC, EXx } }, |
3829 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
3526 | { "cvtsd2siY", { Gv, EXq } }, |
3830 | { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, |
3527 | }, |
3831 | }, |
3528 | 3832 | ||
3529 | /* PREFIX_0F2E */ |
3833 | /* PREFIX_0F2E */ |
3530 | { |
3834 | { |
3531 | { "ucomiss",{ XM, EXd } }, |
3835 | { "ucomiss",{ XM, EXd }, 0 }, |
3532 | { Bad_Opcode }, |
3836 | { Bad_Opcode }, |
3533 | { "ucomisd",{ XM, EXq } }, |
3837 | { "ucomisd",{ XM, EXq }, 0 }, |
3534 | }, |
3838 | }, |
3535 | 3839 | ||
3536 | /* PREFIX_0F2F */ |
3840 | /* PREFIX_0F2F */ |
3537 | { |
3841 | { |
3538 | { "comiss", { XM, EXd } }, |
3842 | { "comiss", { XM, EXd }, 0 }, |
3539 | { Bad_Opcode }, |
3843 | { Bad_Opcode }, |
3540 | { "comisd", { XM, EXq } }, |
3844 | { "comisd", { XM, EXq }, 0 }, |
3541 | }, |
3845 | }, |
3542 | 3846 | ||
3543 | /* PREFIX_0F51 */ |
3847 | /* PREFIX_0F51 */ |
3544 | { |
3848 | { |
3545 | { "sqrtps", { XM, EXx } }, |
3849 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3546 | { "sqrtss", { XM, EXd } }, |
3850 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, |
3547 | { "sqrtpd", { XM, EXx } }, |
3851 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, |
3548 | { "sqrtsd", { XM, EXq } }, |
3852 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, |
3549 | }, |
3853 | }, |
3550 | 3854 | ||
3551 | /* PREFIX_0F52 */ |
3855 | /* PREFIX_0F52 */ |
3552 | { |
3856 | { |
3553 | { "rsqrtps",{ XM, EXx } }, |
3857 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3554 | { "rsqrtss",{ XM, EXd } }, |
3858 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, |
3555 | }, |
3859 | }, |
3556 | 3860 | ||
3557 | /* PREFIX_0F53 */ |
3861 | /* PREFIX_0F53 */ |
3558 | { |
3862 | { |
3559 | { "rcpps", { XM, EXx } }, |
3863 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3560 | { "rcpss", { XM, EXd } }, |
3864 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, |
3561 | }, |
3865 | }, |
3562 | 3866 | ||
3563 | /* PREFIX_0F58 */ |
3867 | /* PREFIX_0F58 */ |
3564 | { |
3868 | { |
3565 | { "addps", { XM, EXx } }, |
3869 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3566 | { "addss", { XM, EXd } }, |
3870 | { "addss", { XM, EXd }, PREFIX_OPCODE }, |
3567 | { "addpd", { XM, EXx } }, |
3871 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, |
3568 | { "addsd", { XM, EXq } }, |
3872 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, |
3569 | }, |
3873 | }, |
3570 | 3874 | ||
3571 | /* PREFIX_0F59 */ |
3875 | /* PREFIX_0F59 */ |
3572 | { |
3876 | { |
3573 | { "mulps", { XM, EXx } }, |
3877 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3574 | { "mulss", { XM, EXd } }, |
3878 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, |
3575 | { "mulpd", { XM, EXx } }, |
3879 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, |
3576 | { "mulsd", { XM, EXq } }, |
3880 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, |
3577 | }, |
3881 | }, |
3578 | 3882 | ||
3579 | /* PREFIX_0F5A */ |
3883 | /* PREFIX_0F5A */ |
3580 | { |
3884 | { |
3581 | { "cvtps2pd", { XM, EXq } }, |
3885 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3582 | { "cvtss2sd", { XM, EXd } }, |
3886 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, |
3583 | { "cvtpd2ps", { XM, EXx } }, |
3887 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, |
3584 | { "cvtsd2ss", { XM, EXq } }, |
3888 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, |
3585 | }, |
3889 | }, |
3586 | 3890 | ||
3587 | /* PREFIX_0F5B */ |
3891 | /* PREFIX_0F5B */ |
3588 | { |
3892 | { |
3589 | { "cvtdq2ps", { XM, EXx } }, |
3893 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3590 | { "cvttps2dq", { XM, EXx } }, |
3894 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, |
3591 | { "cvtps2dq", { XM, EXx } }, |
3895 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, |
3592 | }, |
3896 | }, |
3593 | 3897 | ||
3594 | /* PREFIX_0F5C */ |
3898 | /* PREFIX_0F5C */ |
3595 | { |
3899 | { |
3596 | { "subps", { XM, EXx } }, |
3900 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3597 | { "subss", { XM, EXd } }, |
3901 | { "subss", { XM, EXd }, PREFIX_OPCODE }, |
3598 | { "subpd", { XM, EXx } }, |
3902 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, |
3599 | { "subsd", { XM, EXq } }, |
3903 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, |
3600 | }, |
3904 | }, |
3601 | 3905 | ||
3602 | /* PREFIX_0F5D */ |
3906 | /* PREFIX_0F5D */ |
3603 | { |
3907 | { |
3604 | { "minps", { XM, EXx } }, |
3908 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3605 | { "minss", { XM, EXd } }, |
3909 | { "minss", { XM, EXd }, PREFIX_OPCODE }, |
3606 | { "minpd", { XM, EXx } }, |
3910 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, |
3607 | { "minsd", { XM, EXq } }, |
3911 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, |
3608 | }, |
3912 | }, |
3609 | 3913 | ||
3610 | /* PREFIX_0F5E */ |
3914 | /* PREFIX_0F5E */ |
3611 | { |
3915 | { |
3612 | { "divps", { XM, EXx } }, |
3916 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3613 | { "divss", { XM, EXd } }, |
3917 | { "divss", { XM, EXd }, PREFIX_OPCODE }, |
3614 | { "divpd", { XM, EXx } }, |
3918 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, |
3615 | { "divsd", { XM, EXq } }, |
3919 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, |
3616 | }, |
3920 | }, |
3617 | 3921 | ||
3618 | /* PREFIX_0F5F */ |
3922 | /* PREFIX_0F5F */ |
3619 | { |
3923 | { |
3620 | { "maxps", { XM, EXx } }, |
3924 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3621 | { "maxss", { XM, EXd } }, |
3925 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, |
3622 | { "maxpd", { XM, EXx } }, |
3926 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, |
3623 | { "maxsd", { XM, EXq } }, |
3927 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, |
3624 | }, |
3928 | }, |
3625 | 3929 | ||
3626 | /* PREFIX_0F60 */ |
3930 | /* PREFIX_0F60 */ |
3627 | { |
3931 | { |
3628 | { "punpcklbw",{ MX, EMd } }, |
3932 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
3629 | { Bad_Opcode }, |
3933 | { Bad_Opcode }, |
3630 | { "punpcklbw",{ MX, EMx } }, |
3934 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
3631 | }, |
3935 | }, |
3632 | 3936 | ||
3633 | /* PREFIX_0F61 */ |
3937 | /* PREFIX_0F61 */ |
3634 | { |
3938 | { |
3635 | { "punpcklwd",{ MX, EMd } }, |
3939 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
3636 | { Bad_Opcode }, |
3940 | { Bad_Opcode }, |
3637 | { "punpcklwd",{ MX, EMx } }, |
3941 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
3638 | }, |
3942 | }, |
3639 | 3943 | ||
3640 | /* PREFIX_0F62 */ |
3944 | /* PREFIX_0F62 */ |
3641 | { |
3945 | { |
3642 | { "punpckldq",{ MX, EMd } }, |
3946 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
3643 | { Bad_Opcode }, |
3947 | { Bad_Opcode }, |
3644 | { "punpckldq",{ MX, EMx } }, |
3948 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
3645 | }, |
3949 | }, |
3646 | 3950 | ||
3647 | /* PREFIX_0F6C */ |
3951 | /* PREFIX_0F6C */ |
3648 | { |
3952 | { |
3649 | { Bad_Opcode }, |
3953 | { Bad_Opcode }, |
3650 | { Bad_Opcode }, |
3954 | { Bad_Opcode }, |
3651 | { "punpcklqdq", { XM, EXx } }, |
3955 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
3652 | }, |
3956 | }, |
3653 | 3957 | ||
3654 | /* PREFIX_0F6D */ |
3958 | /* PREFIX_0F6D */ |
3655 | { |
3959 | { |
3656 | { Bad_Opcode }, |
3960 | { Bad_Opcode }, |
3657 | { Bad_Opcode }, |
3961 | { Bad_Opcode }, |
3658 | { "punpckhqdq", { XM, EXx } }, |
3962 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
3659 | }, |
3963 | }, |
3660 | 3964 | ||
3661 | /* PREFIX_0F6F */ |
3965 | /* PREFIX_0F6F */ |
3662 | { |
3966 | { |
3663 | { "movq", { MX, EM } }, |
3967 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3664 | { "movdqu", { XM, EXx } }, |
3968 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, |
3665 | { "movdqa", { XM, EXx } }, |
3969 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, |
3666 | }, |
3970 | }, |
3667 | 3971 | ||
3668 | /* PREFIX_0F70 */ |
3972 | /* PREFIX_0F70 */ |
3669 | { |
3973 | { |
3670 | { "pshufw", { MX, EM, Ib } }, |
3974 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3671 | { "pshufhw",{ XM, EXx, Ib } }, |
3975 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, |
3672 | { "pshufd", { XM, EXx, Ib } }, |
3976 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
3673 | { "pshuflw",{ XM, EXx, Ib } }, |
3977 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, |
3674 | }, |
3978 | }, |
3675 | 3979 | ||
3676 | /* PREFIX_0F73_REG_3 */ |
3980 | /* PREFIX_0F73_REG_3 */ |
3677 | { |
3981 | { |
3678 | { Bad_Opcode }, |
3982 | { Bad_Opcode }, |
3679 | { Bad_Opcode }, |
3983 | { Bad_Opcode }, |
3680 | { "psrldq", { XS, Ib } }, |
3984 | { "psrldq", { XS, Ib }, 0 }, |
3681 | }, |
3985 | }, |
3682 | 3986 | ||
3683 | /* PREFIX_0F73_REG_7 */ |
3987 | /* PREFIX_0F73_REG_7 */ |
3684 | { |
3988 | { |
3685 | { Bad_Opcode }, |
3989 | { Bad_Opcode }, |
3686 | { Bad_Opcode }, |
3990 | { Bad_Opcode }, |
3687 | { "pslldq", { XS, Ib } }, |
3991 | { "pslldq", { XS, Ib }, 0 }, |
3688 | }, |
3992 | }, |
3689 | 3993 | ||
3690 | /* PREFIX_0F78 */ |
3994 | /* PREFIX_0F78 */ |
3691 | { |
3995 | { |
3692 | {"vmread", { Em, Gm } }, |
3996 | {"vmread", { Em, Gm }, 0 }, |
3693 | { Bad_Opcode }, |
3997 | { Bad_Opcode }, |
3694 | {"extrq", { XS, Ib, Ib } }, |
3998 | {"extrq", { XS, Ib, Ib }, 0 }, |
3695 | {"insertq", { XM, XS, Ib, Ib } }, |
3999 | {"insertq", { XM, XS, Ib, Ib }, 0 }, |
3696 | }, |
4000 | }, |
3697 | 4001 | ||
3698 | /* PREFIX_0F79 */ |
4002 | /* PREFIX_0F79 */ |
3699 | { |
4003 | { |
3700 | {"vmwrite", { Gm, Em } }, |
4004 | {"vmwrite", { Gm, Em }, 0 }, |
3701 | { Bad_Opcode }, |
4005 | { Bad_Opcode }, |
3702 | {"extrq", { XM, XS } }, |
4006 | {"extrq", { XM, XS }, 0 }, |
3703 | {"insertq", { XM, XS } }, |
4007 | {"insertq", { XM, XS }, 0 }, |
3704 | }, |
4008 | }, |
3705 | 4009 | ||
3706 | /* PREFIX_0F7C */ |
4010 | /* PREFIX_0F7C */ |
3707 | { |
4011 | { |
3708 | { Bad_Opcode }, |
4012 | { Bad_Opcode }, |
3709 | { Bad_Opcode }, |
4013 | { Bad_Opcode }, |
3710 | { "haddpd", { XM, EXx } }, |
4014 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3711 | { "haddps", { XM, EXx } }, |
4015 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, |
3712 | }, |
4016 | }, |
3713 | 4017 | ||
3714 | /* PREFIX_0F7D */ |
4018 | /* PREFIX_0F7D */ |
3715 | { |
4019 | { |
3716 | { Bad_Opcode }, |
4020 | { Bad_Opcode }, |
3717 | { Bad_Opcode }, |
4021 | { Bad_Opcode }, |
3718 | { "hsubpd", { XM, EXx } }, |
4022 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3719 | { "hsubps", { XM, EXx } }, |
4023 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, |
3720 | }, |
4024 | }, |
3721 | 4025 | ||
3722 | /* PREFIX_0F7E */ |
4026 | /* PREFIX_0F7E */ |
3723 | { |
4027 | { |
3724 | { "movK", { Edq, MX } }, |
4028 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3725 | { "movq", { XM, EXq } }, |
4029 | { "movq", { XM, EXq }, PREFIX_OPCODE }, |
3726 | { "movK", { Edq, XM } }, |
4030 | { "movK", { Edq, XM }, PREFIX_OPCODE }, |
3727 | }, |
4031 | }, |
3728 | 4032 | ||
3729 | /* PREFIX_0F7F */ |
4033 | /* PREFIX_0F7F */ |
3730 | { |
4034 | { |
3731 | { "movq", { EMS, MX } }, |
4035 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3732 | { "movdqu", { EXxS, XM } }, |
4036 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, |
3733 | { "movdqa", { EXxS, XM } }, |
4037 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, |
3734 | }, |
4038 | }, |
3735 | 4039 | ||
3736 | /* PREFIX_0FAE_REG_0 */ |
4040 | /* PREFIX_0FAE_REG_0 */ |
3737 | { |
4041 | { |
3738 | { Bad_Opcode }, |
4042 | { Bad_Opcode }, |
3739 | { "rdfsbase", { Ev } }, |
4043 | { "rdfsbase", { Ev }, 0 }, |
3740 | }, |
4044 | }, |
3741 | 4045 | ||
3742 | /* PREFIX_0FAE_REG_1 */ |
4046 | /* PREFIX_0FAE_REG_1 */ |
3743 | { |
4047 | { |
3744 | { Bad_Opcode }, |
4048 | { Bad_Opcode }, |
3745 | { "rdgsbase", { Ev } }, |
4049 | { "rdgsbase", { Ev }, 0 }, |
3746 | }, |
4050 | }, |
3747 | 4051 | ||
3748 | /* PREFIX_0FAE_REG_2 */ |
4052 | /* PREFIX_0FAE_REG_2 */ |
3749 | { |
4053 | { |
3750 | { Bad_Opcode }, |
4054 | { Bad_Opcode }, |
3751 | { "wrfsbase", { Ev } }, |
4055 | { "wrfsbase", { Ev }, 0 }, |
3752 | }, |
4056 | }, |
3753 | 4057 | ||
3754 | /* PREFIX_0FAE_REG_3 */ |
4058 | /* PREFIX_0FAE_REG_3 */ |
3755 | { |
4059 | { |
3756 | { Bad_Opcode }, |
4060 | { Bad_Opcode }, |
3757 | { "wrgsbase", { Ev } }, |
4061 | { "wrgsbase", { Ev }, 0 }, |
- | 4062 | }, |
|
- | 4063 | ||
- | 4064 | /* PREFIX_0FAE_REG_6 */ |
|
- | 4065 | { |
|
- | 4066 | { "xsaveopt", { FXSAVE }, 0 }, |
|
- | 4067 | { Bad_Opcode }, |
|
- | 4068 | { "clwb", { Mb }, 0 }, |
|
- | 4069 | }, |
|
- | 4070 | ||
- | 4071 | /* PREFIX_0FAE_REG_7 */ |
|
- | 4072 | { |
|
- | 4073 | { "clflush", { Mb }, 0 }, |
|
- | 4074 | { Bad_Opcode }, |
|
- | 4075 | { "clflushopt", { Mb }, 0 }, |
|
- | 4076 | }, |
|
- | 4077 | ||
- | 4078 | /* PREFIX_RM_0_0FAE_REG_7 */ |
|
- | 4079 | { |
|
- | 4080 | { "sfence", { Skip_MODRM }, 0 }, |
|
- | 4081 | { Bad_Opcode }, |
|
- | 4082 | { "pcommit", { Skip_MODRM }, 0 }, |
|
3758 | }, |
4083 | }, |
3759 | 4084 | ||
3760 | /* PREFIX_0FB8 */ |
4085 | /* PREFIX_0FB8 */ |
3761 | { |
4086 | { |
3762 | { Bad_Opcode }, |
4087 | { Bad_Opcode }, |
3763 | { "popcntS", { Gv, Ev } }, |
4088 | { "popcntS", { Gv, Ev }, 0 }, |
3764 | }, |
4089 | }, |
3765 | 4090 | ||
3766 | /* PREFIX_0FBC */ |
4091 | /* PREFIX_0FBC */ |
3767 | { |
4092 | { |
3768 | { "bsfS", { Gv, Ev } }, |
4093 | { "bsfS", { Gv, Ev }, 0 }, |
3769 | { "tzcntS", { Gv, Ev } }, |
4094 | { "tzcntS", { Gv, Ev }, 0 }, |
3770 | { "bsfS", { Gv, Ev } }, |
4095 | { "bsfS", { Gv, Ev }, 0 }, |
3771 | }, |
4096 | }, |
3772 | 4097 | ||
3773 | /* PREFIX_0FBD */ |
4098 | /* PREFIX_0FBD */ |
3774 | { |
4099 | { |
3775 | { "bsrS", { Gv, Ev } }, |
4100 | { "bsrS", { Gv, Ev }, 0 }, |
3776 | { "lzcntS", { Gv, Ev } }, |
4101 | { "lzcntS", { Gv, Ev }, 0 }, |
3777 | { "bsrS", { Gv, Ev } }, |
4102 | { "bsrS", { Gv, Ev }, 0 }, |
3778 | }, |
4103 | }, |
3779 | 4104 | ||
3780 | /* PREFIX_0FC2 */ |
4105 | /* PREFIX_0FC2 */ |
3781 | { |
4106 | { |
3782 | { "cmpps", { XM, EXx, CMP } }, |
4107 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
3783 | { "cmpss", { XM, EXd, CMP } }, |
4108 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, |
3784 | { "cmppd", { XM, EXx, CMP } }, |
4109 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, |
3785 | { "cmpsd", { XM, EXq, CMP } }, |
4110 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, |
3786 | }, |
4111 | }, |
3787 | 4112 | ||
3788 | /* PREFIX_0FC3 */ |
4113 | /* PREFIX_MOD_0_0FC3 */ |
3789 | { |
4114 | { |
3790 | { "movntiS", { Ma, Gv } }, |
4115 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
3791 | }, |
4116 | }, |
3792 | 4117 | ||
3793 | /* PREFIX_0FC7_REG_6 */ |
4118 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
3794 | { |
4119 | { |
3795 | { "vmptrld",{ Mq } }, |
4120 | { "vmptrld",{ Mq }, 0 }, |
- | 4121 | { "vmxon", { Mq }, 0 }, |
|
- | 4122 | { "vmclear",{ Mq }, 0 }, |
|
- | 4123 | }, |
|
- | 4124 | ||
- | 4125 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
|
- | 4126 | { |
|
- | 4127 | { "rdrand", { Ev }, 0 }, |
|
- | 4128 | { Bad_Opcode }, |
|
- | 4129 | { "rdrand", { Ev }, 0 } |
|
- | 4130 | }, |
|
- | 4131 | ||
- | 4132 | /* PREFIX_MOD_3_0FC7_REG_7 */ |
|
- | 4133 | { |
|
- | 4134 | { "rdseed", { Ev }, 0 }, |
|
3796 | { "vmxon", { Mq } }, |
4135 | { Bad_Opcode }, |
3797 | { "vmclear",{ Mq } }, |
4136 | { "rdseed", { Ev }, 0 }, |
3798 | }, |
4137 | }, |
3799 | 4138 | ||
3800 | /* PREFIX_0FD0 */ |
4139 | /* PREFIX_0FD0 */ |
3801 | { |
4140 | { |
3802 | { Bad_Opcode }, |
4141 | { Bad_Opcode }, |
3803 | { Bad_Opcode }, |
4142 | { Bad_Opcode }, |
3804 | { "addsubpd", { XM, EXx } }, |
4143 | { "addsubpd", { XM, EXx }, 0 }, |
3805 | { "addsubps", { XM, EXx } }, |
4144 | { "addsubps", { XM, EXx }, 0 }, |
3806 | }, |
4145 | }, |
3807 | 4146 | ||
3808 | /* PREFIX_0FD6 */ |
4147 | /* PREFIX_0FD6 */ |
3809 | { |
4148 | { |
3810 | { Bad_Opcode }, |
4149 | { Bad_Opcode }, |
3811 | { "movq2dq",{ XM, MS } }, |
4150 | { "movq2dq",{ XM, MS }, 0 }, |
3812 | { "movq", { EXqS, XM } }, |
4151 | { "movq", { EXqS, XM }, 0 }, |
3813 | { "movdq2q",{ MX, XS } }, |
4152 | { "movdq2q",{ MX, XS }, 0 }, |
3814 | }, |
4153 | }, |
3815 | 4154 | ||
3816 | /* PREFIX_0FE6 */ |
4155 | /* PREFIX_0FE6 */ |
3817 | { |
4156 | { |
3818 | { Bad_Opcode }, |
4157 | { Bad_Opcode }, |
3819 | { "cvtdq2pd", { XM, EXq } }, |
4158 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
3820 | { "cvttpd2dq", { XM, EXx } }, |
4159 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, |
3821 | { "cvtpd2dq", { XM, EXx } }, |
4160 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, |
3822 | }, |
4161 | }, |
3823 | 4162 | ||
3824 | /* PREFIX_0FE7 */ |
4163 | /* PREFIX_0FE7 */ |
3825 | { |
4164 | { |
3826 | { "movntq", { Mq, MX } }, |
4165 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
3827 | { Bad_Opcode }, |
4166 | { Bad_Opcode }, |
3828 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4167 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
3829 | }, |
4168 | }, |
3830 | 4169 | ||
3831 | /* PREFIX_0FF0 */ |
4170 | /* PREFIX_0FF0 */ |
3832 | { |
4171 | { |
3833 | { Bad_Opcode }, |
4172 | { Bad_Opcode }, |
3834 | { Bad_Opcode }, |
4173 | { Bad_Opcode }, |
3835 | { Bad_Opcode }, |
4174 | { Bad_Opcode }, |
3836 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4175 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
3837 | }, |
4176 | }, |
3838 | 4177 | ||
3839 | /* PREFIX_0FF7 */ |
4178 | /* PREFIX_0FF7 */ |
3840 | { |
4179 | { |
3841 | { "maskmovq", { MX, MS } }, |
4180 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
3842 | { Bad_Opcode }, |
4181 | { Bad_Opcode }, |
3843 | { "maskmovdqu", { XM, XS } }, |
4182 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
3844 | }, |
4183 | }, |
3845 | 4184 | ||
3846 | /* PREFIX_0F3810 */ |
4185 | /* PREFIX_0F3810 */ |
3847 | { |
4186 | { |
3848 | { Bad_Opcode }, |
4187 | { Bad_Opcode }, |
3849 | { Bad_Opcode }, |
4188 | { Bad_Opcode }, |
3850 | { "pblendvb", { XM, EXx, XMM0 } }, |
4189 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
3851 | }, |
4190 | }, |
3852 | 4191 | ||
3853 | /* PREFIX_0F3814 */ |
4192 | /* PREFIX_0F3814 */ |
3854 | { |
4193 | { |
3855 | { Bad_Opcode }, |
4194 | { Bad_Opcode }, |
3856 | { Bad_Opcode }, |
4195 | { Bad_Opcode }, |
3857 | { "blendvps", { XM, EXx, XMM0 } }, |
4196 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
3858 | }, |
4197 | }, |
3859 | 4198 | ||
3860 | /* PREFIX_0F3815 */ |
4199 | /* PREFIX_0F3815 */ |
3861 | { |
4200 | { |
3862 | { Bad_Opcode }, |
4201 | { Bad_Opcode }, |
3863 | { Bad_Opcode }, |
4202 | { Bad_Opcode }, |
3864 | { "blendvpd", { XM, EXx, XMM0 } }, |
4203 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
3865 | }, |
4204 | }, |
3866 | 4205 | ||
3867 | /* PREFIX_0F3817 */ |
4206 | /* PREFIX_0F3817 */ |
3868 | { |
4207 | { |
3869 | { Bad_Opcode }, |
4208 | { Bad_Opcode }, |
3870 | { Bad_Opcode }, |
4209 | { Bad_Opcode }, |
3871 | { "ptest", { XM, EXx } }, |
4210 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
3872 | }, |
4211 | }, |
3873 | 4212 | ||
3874 | /* PREFIX_0F3820 */ |
4213 | /* PREFIX_0F3820 */ |
3875 | { |
4214 | { |
3876 | { Bad_Opcode }, |
4215 | { Bad_Opcode }, |
3877 | { Bad_Opcode }, |
4216 | { Bad_Opcode }, |
3878 | { "pmovsxbw", { XM, EXq } }, |
4217 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
3879 | }, |
4218 | }, |
3880 | 4219 | ||
3881 | /* PREFIX_0F3821 */ |
4220 | /* PREFIX_0F3821 */ |
3882 | { |
4221 | { |
3883 | { Bad_Opcode }, |
4222 | { Bad_Opcode }, |
3884 | { Bad_Opcode }, |
4223 | { Bad_Opcode }, |
3885 | { "pmovsxbd", { XM, EXd } }, |
4224 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
3886 | }, |
4225 | }, |
3887 | 4226 | ||
3888 | /* PREFIX_0F3822 */ |
4227 | /* PREFIX_0F3822 */ |
3889 | { |
4228 | { |
3890 | { Bad_Opcode }, |
4229 | { Bad_Opcode }, |
3891 | { Bad_Opcode }, |
4230 | { Bad_Opcode }, |
3892 | { "pmovsxbq", { XM, EXw } }, |
4231 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
3893 | }, |
4232 | }, |
3894 | 4233 | ||
3895 | /* PREFIX_0F3823 */ |
4234 | /* PREFIX_0F3823 */ |
3896 | { |
4235 | { |
3897 | { Bad_Opcode }, |
4236 | { Bad_Opcode }, |
3898 | { Bad_Opcode }, |
4237 | { Bad_Opcode }, |
3899 | { "pmovsxwd", { XM, EXq } }, |
4238 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
3900 | }, |
4239 | }, |
3901 | 4240 | ||
3902 | /* PREFIX_0F3824 */ |
4241 | /* PREFIX_0F3824 */ |
3903 | { |
4242 | { |
3904 | { Bad_Opcode }, |
4243 | { Bad_Opcode }, |
3905 | { Bad_Opcode }, |
4244 | { Bad_Opcode }, |
3906 | { "pmovsxwq", { XM, EXd } }, |
4245 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
3907 | }, |
4246 | }, |
3908 | 4247 | ||
3909 | /* PREFIX_0F3825 */ |
4248 | /* PREFIX_0F3825 */ |
3910 | { |
4249 | { |
3911 | { Bad_Opcode }, |
4250 | { Bad_Opcode }, |
3912 | { Bad_Opcode }, |
4251 | { Bad_Opcode }, |
3913 | { "pmovsxdq", { XM, EXq } }, |
4252 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
3914 | }, |
4253 | }, |
3915 | 4254 | ||
3916 | /* PREFIX_0F3828 */ |
4255 | /* PREFIX_0F3828 */ |
3917 | { |
4256 | { |
3918 | { Bad_Opcode }, |
4257 | { Bad_Opcode }, |
3919 | { Bad_Opcode }, |
4258 | { Bad_Opcode }, |
3920 | { "pmuldq", { XM, EXx } }, |
4259 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
3921 | }, |
4260 | }, |
3922 | 4261 | ||
3923 | /* PREFIX_0F3829 */ |
4262 | /* PREFIX_0F3829 */ |
3924 | { |
4263 | { |
3925 | { Bad_Opcode }, |
4264 | { Bad_Opcode }, |
3926 | { Bad_Opcode }, |
4265 | { Bad_Opcode }, |
3927 | { "pcmpeqq", { XM, EXx } }, |
4266 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
3928 | }, |
4267 | }, |
3929 | 4268 | ||
3930 | /* PREFIX_0F382A */ |
4269 | /* PREFIX_0F382A */ |
3931 | { |
4270 | { |
3932 | { Bad_Opcode }, |
4271 | { Bad_Opcode }, |
3933 | { Bad_Opcode }, |
4272 | { Bad_Opcode }, |
3934 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
4273 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
3935 | }, |
4274 | }, |
3936 | 4275 | ||
3937 | /* PREFIX_0F382B */ |
4276 | /* PREFIX_0F382B */ |
3938 | { |
4277 | { |
3939 | { Bad_Opcode }, |
4278 | { Bad_Opcode }, |
3940 | { Bad_Opcode }, |
4279 | { Bad_Opcode }, |
3941 | { "packusdw", { XM, EXx } }, |
4280 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
3942 | }, |
4281 | }, |
3943 | 4282 | ||
3944 | /* PREFIX_0F3830 */ |
4283 | /* PREFIX_0F3830 */ |
3945 | { |
4284 | { |
3946 | { Bad_Opcode }, |
4285 | { Bad_Opcode }, |
3947 | { Bad_Opcode }, |
4286 | { Bad_Opcode }, |
3948 | { "pmovzxbw", { XM, EXq } }, |
4287 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
3949 | }, |
4288 | }, |
3950 | 4289 | ||
3951 | /* PREFIX_0F3831 */ |
4290 | /* PREFIX_0F3831 */ |
3952 | { |
4291 | { |
3953 | { Bad_Opcode }, |
4292 | { Bad_Opcode }, |
3954 | { Bad_Opcode }, |
4293 | { Bad_Opcode }, |
3955 | { "pmovzxbd", { XM, EXd } }, |
4294 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
3956 | }, |
4295 | }, |
3957 | 4296 | ||
3958 | /* PREFIX_0F3832 */ |
4297 | /* PREFIX_0F3832 */ |
3959 | { |
4298 | { |
3960 | { Bad_Opcode }, |
4299 | { Bad_Opcode }, |
3961 | { Bad_Opcode }, |
4300 | { Bad_Opcode }, |
3962 | { "pmovzxbq", { XM, EXw } }, |
4301 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
3963 | }, |
4302 | }, |
3964 | 4303 | ||
3965 | /* PREFIX_0F3833 */ |
4304 | /* PREFIX_0F3833 */ |
3966 | { |
4305 | { |
3967 | { Bad_Opcode }, |
4306 | { Bad_Opcode }, |
3968 | { Bad_Opcode }, |
4307 | { Bad_Opcode }, |
3969 | { "pmovzxwd", { XM, EXq } }, |
4308 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
3970 | }, |
4309 | }, |
3971 | 4310 | ||
3972 | /* PREFIX_0F3834 */ |
4311 | /* PREFIX_0F3834 */ |
3973 | { |
4312 | { |
3974 | { Bad_Opcode }, |
4313 | { Bad_Opcode }, |
3975 | { Bad_Opcode }, |
4314 | { Bad_Opcode }, |
3976 | { "pmovzxwq", { XM, EXd } }, |
4315 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
3977 | }, |
4316 | }, |
3978 | 4317 | ||
3979 | /* PREFIX_0F3835 */ |
4318 | /* PREFIX_0F3835 */ |
3980 | { |
4319 | { |
3981 | { Bad_Opcode }, |
4320 | { Bad_Opcode }, |
3982 | { Bad_Opcode }, |
4321 | { Bad_Opcode }, |
3983 | { "pmovzxdq", { XM, EXq } }, |
4322 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
3984 | }, |
4323 | }, |
3985 | 4324 | ||
3986 | /* PREFIX_0F3837 */ |
4325 | /* PREFIX_0F3837 */ |
3987 | { |
4326 | { |
3988 | { Bad_Opcode }, |
4327 | { Bad_Opcode }, |
3989 | { Bad_Opcode }, |
4328 | { Bad_Opcode }, |
3990 | { "pcmpgtq", { XM, EXx } }, |
4329 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
3991 | }, |
4330 | }, |
3992 | 4331 | ||
3993 | /* PREFIX_0F3838 */ |
4332 | /* PREFIX_0F3838 */ |
3994 | { |
4333 | { |
3995 | { Bad_Opcode }, |
4334 | { Bad_Opcode }, |
3996 | { Bad_Opcode }, |
4335 | { Bad_Opcode }, |
3997 | { "pminsb", { XM, EXx } }, |
4336 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
3998 | }, |
4337 | }, |
3999 | 4338 | ||
4000 | /* PREFIX_0F3839 */ |
4339 | /* PREFIX_0F3839 */ |
4001 | { |
4340 | { |
4002 | { Bad_Opcode }, |
4341 | { Bad_Opcode }, |
4003 | { Bad_Opcode }, |
4342 | { Bad_Opcode }, |
4004 | { "pminsd", { XM, EXx } }, |
4343 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
4005 | }, |
4344 | }, |
4006 | 4345 | ||
4007 | /* PREFIX_0F383A */ |
4346 | /* PREFIX_0F383A */ |
4008 | { |
4347 | { |
4009 | { Bad_Opcode }, |
4348 | { Bad_Opcode }, |
4010 | { Bad_Opcode }, |
4349 | { Bad_Opcode }, |
4011 | { "pminuw", { XM, EXx } }, |
4350 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
4012 | }, |
4351 | }, |
4013 | 4352 | ||
4014 | /* PREFIX_0F383B */ |
4353 | /* PREFIX_0F383B */ |
4015 | { |
4354 | { |
4016 | { Bad_Opcode }, |
4355 | { Bad_Opcode }, |
4017 | { Bad_Opcode }, |
4356 | { Bad_Opcode }, |
4018 | { "pminud", { XM, EXx } }, |
4357 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
4019 | }, |
4358 | }, |
4020 | 4359 | ||
4021 | /* PREFIX_0F383C */ |
4360 | /* PREFIX_0F383C */ |
4022 | { |
4361 | { |
4023 | { Bad_Opcode }, |
4362 | { Bad_Opcode }, |
4024 | { Bad_Opcode }, |
4363 | { Bad_Opcode }, |
4025 | { "pmaxsb", { XM, EXx } }, |
4364 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
4026 | }, |
4365 | }, |
4027 | 4366 | ||
4028 | /* PREFIX_0F383D */ |
4367 | /* PREFIX_0F383D */ |
4029 | { |
4368 | { |
4030 | { Bad_Opcode }, |
4369 | { Bad_Opcode }, |
4031 | { Bad_Opcode }, |
4370 | { Bad_Opcode }, |
4032 | { "pmaxsd", { XM, EXx } }, |
4371 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
4033 | }, |
4372 | }, |
4034 | 4373 | ||
4035 | /* PREFIX_0F383E */ |
4374 | /* PREFIX_0F383E */ |
4036 | { |
4375 | { |
4037 | { Bad_Opcode }, |
4376 | { Bad_Opcode }, |
4038 | { Bad_Opcode }, |
4377 | { Bad_Opcode }, |
4039 | { "pmaxuw", { XM, EXx } }, |
4378 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
4040 | }, |
4379 | }, |
4041 | 4380 | ||
4042 | /* PREFIX_0F383F */ |
4381 | /* PREFIX_0F383F */ |
4043 | { |
4382 | { |
4044 | { Bad_Opcode }, |
4383 | { Bad_Opcode }, |
4045 | { Bad_Opcode }, |
4384 | { Bad_Opcode }, |
4046 | { "pmaxud", { XM, EXx } }, |
4385 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
4047 | }, |
4386 | }, |
4048 | 4387 | ||
4049 | /* PREFIX_0F3840 */ |
4388 | /* PREFIX_0F3840 */ |
4050 | { |
4389 | { |
4051 | { Bad_Opcode }, |
4390 | { Bad_Opcode }, |
4052 | { Bad_Opcode }, |
4391 | { Bad_Opcode }, |
4053 | { "pmulld", { XM, EXx } }, |
4392 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
4054 | }, |
4393 | }, |
4055 | 4394 | ||
4056 | /* PREFIX_0F3841 */ |
4395 | /* PREFIX_0F3841 */ |
4057 | { |
4396 | { |
4058 | { Bad_Opcode }, |
4397 | { Bad_Opcode }, |
4059 | { Bad_Opcode }, |
4398 | { Bad_Opcode }, |
4060 | { "phminposuw", { XM, EXx } }, |
4399 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
4061 | }, |
4400 | }, |
4062 | 4401 | ||
4063 | /* PREFIX_0F3880 */ |
4402 | /* PREFIX_0F3880 */ |
4064 | { |
4403 | { |
4065 | { Bad_Opcode }, |
4404 | { Bad_Opcode }, |
4066 | { Bad_Opcode }, |
4405 | { Bad_Opcode }, |
4067 | { "invept", { Gm, Mo } }, |
4406 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
4068 | }, |
4407 | }, |
4069 | 4408 | ||
4070 | /* PREFIX_0F3881 */ |
4409 | /* PREFIX_0F3881 */ |
4071 | { |
4410 | { |
4072 | { Bad_Opcode }, |
4411 | { Bad_Opcode }, |
4073 | { Bad_Opcode }, |
4412 | { Bad_Opcode }, |
4074 | { "invvpid", { Gm, Mo } }, |
4413 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
4075 | }, |
4414 | }, |
4076 | 4415 | ||
4077 | /* PREFIX_0F3882 */ |
4416 | /* PREFIX_0F3882 */ |
4078 | { |
4417 | { |
4079 | { Bad_Opcode }, |
4418 | { Bad_Opcode }, |
4080 | { Bad_Opcode }, |
4419 | { Bad_Opcode }, |
4081 | { "invpcid", { Gm, M } }, |
4420 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
4082 | }, |
4421 | }, |
4083 | 4422 | ||
4084 | /* PREFIX_0F38C8 */ |
4423 | /* PREFIX_0F38C8 */ |
4085 | { |
4424 | { |
4086 | { "sha1nexte", { XM, EXxmm } }, |
4425 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
4087 | }, |
4426 | }, |
4088 | 4427 | ||
4089 | /* PREFIX_0F38C9 */ |
4428 | /* PREFIX_0F38C9 */ |
4090 | { |
4429 | { |
4091 | { "sha1msg1", { XM, EXxmm } }, |
4430 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
4092 | }, |
4431 | }, |
4093 | 4432 | ||
4094 | /* PREFIX_0F38CA */ |
4433 | /* PREFIX_0F38CA */ |
4095 | { |
4434 | { |
4096 | { "sha1msg2", { XM, EXxmm } }, |
4435 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
4097 | }, |
4436 | }, |
4098 | 4437 | ||
4099 | /* PREFIX_0F38CB */ |
4438 | /* PREFIX_0F38CB */ |
4100 | { |
4439 | { |
4101 | { "sha256rnds2", { XM, EXxmm, XMM0 } }, |
4440 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
4102 | }, |
4441 | }, |
4103 | 4442 | ||
4104 | /* PREFIX_0F38CC */ |
4443 | /* PREFIX_0F38CC */ |
4105 | { |
4444 | { |
4106 | { "sha256msg1", { XM, EXxmm } }, |
4445 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
4107 | }, |
4446 | }, |
4108 | 4447 | ||
4109 | /* PREFIX_0F38CD */ |
4448 | /* PREFIX_0F38CD */ |
4110 | { |
4449 | { |
4111 | { "sha256msg2", { XM, EXxmm } }, |
4450 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
4112 | }, |
4451 | }, |
4113 | 4452 | ||
4114 | /* PREFIX_0F38DB */ |
4453 | /* PREFIX_0F38DB */ |
4115 | { |
4454 | { |
4116 | { Bad_Opcode }, |
4455 | { Bad_Opcode }, |
4117 | { Bad_Opcode }, |
4456 | { Bad_Opcode }, |
4118 | { "aesimc", { XM, EXx } }, |
4457 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
4119 | }, |
4458 | }, |
4120 | 4459 | ||
4121 | /* PREFIX_0F38DC */ |
4460 | /* PREFIX_0F38DC */ |
4122 | { |
4461 | { |
4123 | { Bad_Opcode }, |
4462 | { Bad_Opcode }, |
4124 | { Bad_Opcode }, |
4463 | { Bad_Opcode }, |
4125 | { "aesenc", { XM, EXx } }, |
4464 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
4126 | }, |
4465 | }, |
4127 | 4466 | ||
4128 | /* PREFIX_0F38DD */ |
4467 | /* PREFIX_0F38DD */ |
4129 | { |
4468 | { |
4130 | { Bad_Opcode }, |
4469 | { Bad_Opcode }, |
4131 | { Bad_Opcode }, |
4470 | { Bad_Opcode }, |
4132 | { "aesenclast", { XM, EXx } }, |
4471 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
4133 | }, |
4472 | }, |
4134 | 4473 | ||
4135 | /* PREFIX_0F38DE */ |
4474 | /* PREFIX_0F38DE */ |
4136 | { |
4475 | { |
4137 | { Bad_Opcode }, |
4476 | { Bad_Opcode }, |
4138 | { Bad_Opcode }, |
4477 | { Bad_Opcode }, |
4139 | { "aesdec", { XM, EXx } }, |
4478 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
4140 | }, |
4479 | }, |
4141 | 4480 | ||
4142 | /* PREFIX_0F38DF */ |
4481 | /* PREFIX_0F38DF */ |
4143 | { |
4482 | { |
4144 | { Bad_Opcode }, |
4483 | { Bad_Opcode }, |
4145 | { Bad_Opcode }, |
4484 | { Bad_Opcode }, |
4146 | { "aesdeclast", { XM, EXx } }, |
4485 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
4147 | }, |
4486 | }, |
4148 | 4487 | ||
4149 | /* PREFIX_0F38F0 */ |
4488 | /* PREFIX_0F38F0 */ |
4150 | { |
4489 | { |
4151 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
4490 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4152 | { Bad_Opcode }, |
4491 | { Bad_Opcode }, |
4153 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
4492 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4154 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, |
4493 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, |
4155 | }, |
4494 | }, |
4156 | 4495 | ||
4157 | /* PREFIX_0F38F1 */ |
4496 | /* PREFIX_0F38F1 */ |
4158 | { |
4497 | { |
4159 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
4498 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4160 | { Bad_Opcode }, |
4499 | { Bad_Opcode }, |
4161 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
4500 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4162 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, |
4501 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, |
4163 | }, |
4502 | }, |
4164 | 4503 | ||
4165 | /* PREFIX_0F38F6 */ |
4504 | /* PREFIX_0F38F6 */ |
4166 | { |
4505 | { |
4167 | { Bad_Opcode }, |
4506 | { Bad_Opcode }, |
4168 | { "adoxS", { Gdq, Edq} }, |
4507 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4169 | { "adcxS", { Gdq, Edq} }, |
4508 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4170 | { Bad_Opcode }, |
4509 | { Bad_Opcode }, |
4171 | }, |
4510 | }, |
4172 | 4511 | ||
4173 | /* PREFIX_0F3A08 */ |
4512 | /* PREFIX_0F3A08 */ |
4174 | { |
4513 | { |
4175 | { Bad_Opcode }, |
4514 | { Bad_Opcode }, |
4176 | { Bad_Opcode }, |
4515 | { Bad_Opcode }, |
4177 | { "roundps", { XM, EXx, Ib } }, |
4516 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4178 | }, |
4517 | }, |
4179 | 4518 | ||
4180 | /* PREFIX_0F3A09 */ |
4519 | /* PREFIX_0F3A09 */ |
4181 | { |
4520 | { |
4182 | { Bad_Opcode }, |
4521 | { Bad_Opcode }, |
4183 | { Bad_Opcode }, |
4522 | { Bad_Opcode }, |
4184 | { "roundpd", { XM, EXx, Ib } }, |
4523 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4185 | }, |
4524 | }, |
4186 | 4525 | ||
4187 | /* PREFIX_0F3A0A */ |
4526 | /* PREFIX_0F3A0A */ |
4188 | { |
4527 | { |
4189 | { Bad_Opcode }, |
4528 | { Bad_Opcode }, |
4190 | { Bad_Opcode }, |
4529 | { Bad_Opcode }, |
4191 | { "roundss", { XM, EXd, Ib } }, |
4530 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
4192 | }, |
4531 | }, |
4193 | 4532 | ||
4194 | /* PREFIX_0F3A0B */ |
4533 | /* PREFIX_0F3A0B */ |
4195 | { |
4534 | { |
4196 | { Bad_Opcode }, |
4535 | { Bad_Opcode }, |
4197 | { Bad_Opcode }, |
4536 | { Bad_Opcode }, |
4198 | { "roundsd", { XM, EXq, Ib } }, |
4537 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
4199 | }, |
4538 | }, |
4200 | 4539 | ||
4201 | /* PREFIX_0F3A0C */ |
4540 | /* PREFIX_0F3A0C */ |
4202 | { |
4541 | { |
4203 | { Bad_Opcode }, |
4542 | { Bad_Opcode }, |
4204 | { Bad_Opcode }, |
4543 | { Bad_Opcode }, |
4205 | { "blendps", { XM, EXx, Ib } }, |
4544 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4206 | }, |
4545 | }, |
4207 | 4546 | ||
4208 | /* PREFIX_0F3A0D */ |
4547 | /* PREFIX_0F3A0D */ |
4209 | { |
4548 | { |
4210 | { Bad_Opcode }, |
4549 | { Bad_Opcode }, |
4211 | { Bad_Opcode }, |
4550 | { Bad_Opcode }, |
4212 | { "blendpd", { XM, EXx, Ib } }, |
4551 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4213 | }, |
4552 | }, |
4214 | 4553 | ||
4215 | /* PREFIX_0F3A0E */ |
4554 | /* PREFIX_0F3A0E */ |
4216 | { |
4555 | { |
4217 | { Bad_Opcode }, |
4556 | { Bad_Opcode }, |
4218 | { Bad_Opcode }, |
4557 | { Bad_Opcode }, |
4219 | { "pblendw", { XM, EXx, Ib } }, |
4558 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4220 | }, |
4559 | }, |
4221 | 4560 | ||
4222 | /* PREFIX_0F3A14 */ |
4561 | /* PREFIX_0F3A14 */ |
4223 | { |
4562 | { |
4224 | { Bad_Opcode }, |
4563 | { Bad_Opcode }, |
4225 | { Bad_Opcode }, |
4564 | { Bad_Opcode }, |
4226 | { "pextrb", { Edqb, XM, Ib } }, |
4565 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
4227 | }, |
4566 | }, |
4228 | 4567 | ||
4229 | /* PREFIX_0F3A15 */ |
4568 | /* PREFIX_0F3A15 */ |
4230 | { |
4569 | { |
4231 | { Bad_Opcode }, |
4570 | { Bad_Opcode }, |
4232 | { Bad_Opcode }, |
4571 | { Bad_Opcode }, |
4233 | { "pextrw", { Edqw, XM, Ib } }, |
4572 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
4234 | }, |
4573 | }, |
4235 | 4574 | ||
4236 | /* PREFIX_0F3A16 */ |
4575 | /* PREFIX_0F3A16 */ |
4237 | { |
4576 | { |
4238 | { Bad_Opcode }, |
4577 | { Bad_Opcode }, |
4239 | { Bad_Opcode }, |
4578 | { Bad_Opcode }, |
4240 | { "pextrK", { Edq, XM, Ib } }, |
4579 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
4241 | }, |
4580 | }, |
4242 | 4581 | ||
4243 | /* PREFIX_0F3A17 */ |
4582 | /* PREFIX_0F3A17 */ |
4244 | { |
4583 | { |
4245 | { Bad_Opcode }, |
4584 | { Bad_Opcode }, |
4246 | { Bad_Opcode }, |
4585 | { Bad_Opcode }, |
4247 | { "extractps", { Edqd, XM, Ib } }, |
4586 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
4248 | }, |
4587 | }, |
4249 | 4588 | ||
4250 | /* PREFIX_0F3A20 */ |
4589 | /* PREFIX_0F3A20 */ |
4251 | { |
4590 | { |
4252 | { Bad_Opcode }, |
4591 | { Bad_Opcode }, |
4253 | { Bad_Opcode }, |
4592 | { Bad_Opcode }, |
4254 | { "pinsrb", { XM, Edqb, Ib } }, |
4593 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
4255 | }, |
4594 | }, |
4256 | 4595 | ||
4257 | /* PREFIX_0F3A21 */ |
4596 | /* PREFIX_0F3A21 */ |
4258 | { |
4597 | { |
4259 | { Bad_Opcode }, |
4598 | { Bad_Opcode }, |
4260 | { Bad_Opcode }, |
4599 | { Bad_Opcode }, |
4261 | { "insertps", { XM, EXd, Ib } }, |
4600 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
4262 | }, |
4601 | }, |
4263 | 4602 | ||
4264 | /* PREFIX_0F3A22 */ |
4603 | /* PREFIX_0F3A22 */ |
4265 | { |
4604 | { |
4266 | { Bad_Opcode }, |
4605 | { Bad_Opcode }, |
4267 | { Bad_Opcode }, |
4606 | { Bad_Opcode }, |
4268 | { "pinsrK", { XM, Edq, Ib } }, |
4607 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
4269 | }, |
4608 | }, |
4270 | 4609 | ||
4271 | /* PREFIX_0F3A40 */ |
4610 | /* PREFIX_0F3A40 */ |
4272 | { |
4611 | { |
4273 | { Bad_Opcode }, |
4612 | { Bad_Opcode }, |
4274 | { Bad_Opcode }, |
4613 | { Bad_Opcode }, |
4275 | { "dpps", { XM, EXx, Ib } }, |
4614 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4276 | }, |
4615 | }, |
4277 | 4616 | ||
4278 | /* PREFIX_0F3A41 */ |
4617 | /* PREFIX_0F3A41 */ |
4279 | { |
4618 | { |
4280 | { Bad_Opcode }, |
4619 | { Bad_Opcode }, |
4281 | { Bad_Opcode }, |
4620 | { Bad_Opcode }, |
4282 | { "dppd", { XM, EXx, Ib } }, |
4621 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4283 | }, |
4622 | }, |
4284 | 4623 | ||
4285 | /* PREFIX_0F3A42 */ |
4624 | /* PREFIX_0F3A42 */ |
4286 | { |
4625 | { |
4287 | { Bad_Opcode }, |
4626 | { Bad_Opcode }, |
4288 | { Bad_Opcode }, |
4627 | { Bad_Opcode }, |
4289 | { "mpsadbw", { XM, EXx, Ib } }, |
4628 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4290 | }, |
4629 | }, |
4291 | 4630 | ||
4292 | /* PREFIX_0F3A44 */ |
4631 | /* PREFIX_0F3A44 */ |
4293 | { |
4632 | { |
4294 | { Bad_Opcode }, |
4633 | { Bad_Opcode }, |
4295 | { Bad_Opcode }, |
4634 | { Bad_Opcode }, |
4296 | { "pclmulqdq", { XM, EXx, PCLMUL } }, |
4635 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
4297 | }, |
4636 | }, |
4298 | 4637 | ||
4299 | /* PREFIX_0F3A60 */ |
4638 | /* PREFIX_0F3A60 */ |
4300 | { |
4639 | { |
4301 | { Bad_Opcode }, |
4640 | { Bad_Opcode }, |
4302 | { Bad_Opcode }, |
4641 | { Bad_Opcode }, |
4303 | { "pcmpestrm", { XM, EXx, Ib } }, |
4642 | { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4304 | }, |
4643 | }, |
4305 | 4644 | ||
4306 | /* PREFIX_0F3A61 */ |
4645 | /* PREFIX_0F3A61 */ |
4307 | { |
4646 | { |
4308 | { Bad_Opcode }, |
4647 | { Bad_Opcode }, |
4309 | { Bad_Opcode }, |
4648 | { Bad_Opcode }, |
4310 | { "pcmpestri", { XM, EXx, Ib } }, |
4649 | { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4311 | }, |
4650 | }, |
4312 | 4651 | ||
4313 | /* PREFIX_0F3A62 */ |
4652 | /* PREFIX_0F3A62 */ |
4314 | { |
4653 | { |
4315 | { Bad_Opcode }, |
4654 | { Bad_Opcode }, |
4316 | { Bad_Opcode }, |
4655 | { Bad_Opcode }, |
4317 | { "pcmpistrm", { XM, EXx, Ib } }, |
4656 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4318 | }, |
4657 | }, |
4319 | 4658 | ||
4320 | /* PREFIX_0F3A63 */ |
4659 | /* PREFIX_0F3A63 */ |
4321 | { |
4660 | { |
4322 | { Bad_Opcode }, |
4661 | { Bad_Opcode }, |
4323 | { Bad_Opcode }, |
4662 | { Bad_Opcode }, |
4324 | { "pcmpistri", { XM, EXx, Ib } }, |
4663 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4325 | }, |
4664 | }, |
4326 | 4665 | ||
4327 | /* PREFIX_0F3ACC */ |
4666 | /* PREFIX_0F3ACC */ |
4328 | { |
4667 | { |
4329 | { "sha1rnds4", { XM, EXxmm, Ib } }, |
4668 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
4330 | }, |
4669 | }, |
4331 | 4670 | ||
4332 | /* PREFIX_0F3ADF */ |
4671 | /* PREFIX_0F3ADF */ |
4333 | { |
4672 | { |
4334 | { Bad_Opcode }, |
4673 | { Bad_Opcode }, |
4335 | { Bad_Opcode }, |
4674 | { Bad_Opcode }, |
4336 | { "aeskeygenassist", { XM, EXx, Ib } }, |
4675 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4337 | }, |
4676 | }, |
4338 | 4677 | ||
4339 | /* PREFIX_VEX_0F10 */ |
4678 | /* PREFIX_VEX_0F10 */ |
4340 | { |
4679 | { |
4341 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4680 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4342 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, |
4681 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, |
4343 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, |
4682 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, |
4344 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, |
4683 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, |
4345 | }, |
4684 | }, |
4346 | 4685 | ||
4347 | /* PREFIX_VEX_0F11 */ |
4686 | /* PREFIX_VEX_0F11 */ |
4348 | { |
4687 | { |
4349 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4688 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4350 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, |
4689 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, |
4351 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, |
4690 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, |
4352 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, |
4691 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, |
4353 | }, |
4692 | }, |
4354 | 4693 | ||
4355 | /* PREFIX_VEX_0F12 */ |
4694 | /* PREFIX_VEX_0F12 */ |
4356 | { |
4695 | { |
4357 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4696 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4358 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, |
4697 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, |
4359 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, |
4698 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, |
4360 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, |
4699 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, |
4361 | }, |
4700 | }, |
4362 | 4701 | ||
4363 | /* PREFIX_VEX_0F16 */ |
4702 | /* PREFIX_VEX_0F16 */ |
4364 | { |
4703 | { |
4365 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4704 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4366 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, |
4705 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, |
4367 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, |
4706 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, |
4368 | }, |
4707 | }, |
4369 | 4708 | ||
4370 | /* PREFIX_VEX_0F2A */ |
4709 | /* PREFIX_VEX_0F2A */ |
4371 | { |
4710 | { |
4372 | { Bad_Opcode }, |
4711 | { Bad_Opcode }, |
4373 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
4712 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
4374 | { Bad_Opcode }, |
4713 | { Bad_Opcode }, |
4375 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
4714 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
4376 | }, |
4715 | }, |
4377 | 4716 | ||
4378 | /* PREFIX_VEX_0F2C */ |
4717 | /* PREFIX_VEX_0F2C */ |
4379 | { |
4718 | { |
4380 | { Bad_Opcode }, |
4719 | { Bad_Opcode }, |
4381 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
4720 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
4382 | { Bad_Opcode }, |
4721 | { Bad_Opcode }, |
4383 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
4722 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
4384 | }, |
4723 | }, |
4385 | 4724 | ||
4386 | /* PREFIX_VEX_0F2D */ |
4725 | /* PREFIX_VEX_0F2D */ |
4387 | { |
4726 | { |
4388 | { Bad_Opcode }, |
4727 | { Bad_Opcode }, |
4389 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
4728 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
4390 | { Bad_Opcode }, |
4729 | { Bad_Opcode }, |
4391 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
4730 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
4392 | }, |
4731 | }, |
4393 | 4732 | ||
4394 | /* PREFIX_VEX_0F2E */ |
4733 | /* PREFIX_VEX_0F2E */ |
4395 | { |
4734 | { |
4396 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
4735 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
4397 | { Bad_Opcode }, |
4736 | { Bad_Opcode }, |
4398 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
4737 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
4399 | }, |
4738 | }, |
4400 | 4739 | ||
4401 | /* PREFIX_VEX_0F2F */ |
4740 | /* PREFIX_VEX_0F2F */ |
4402 | { |
4741 | { |
4403 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
4742 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
4404 | { Bad_Opcode }, |
4743 | { Bad_Opcode }, |
4405 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
4744 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
4406 | }, |
4745 | }, |
4407 | 4746 | ||
4408 | /* PREFIX_VEX_0F41 */ |
4747 | /* PREFIX_VEX_0F41 */ |
4409 | { |
4748 | { |
4410 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, |
4749 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, |
- | 4750 | { Bad_Opcode }, |
|
- | 4751 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, |
|
4411 | }, |
4752 | }, |
4412 | 4753 | ||
4413 | /* PREFIX_VEX_0F42 */ |
4754 | /* PREFIX_VEX_0F42 */ |
4414 | { |
4755 | { |
4415 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, |
4756 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, |
- | 4757 | { Bad_Opcode }, |
|
- | 4758 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, |
|
4416 | }, |
4759 | }, |
4417 | 4760 | ||
4418 | /* PREFIX_VEX_0F44 */ |
4761 | /* PREFIX_VEX_0F44 */ |
4419 | { |
4762 | { |
4420 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, |
4763 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, |
- | 4764 | { Bad_Opcode }, |
|
- | 4765 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, |
|
4421 | }, |
4766 | }, |
4422 | 4767 | ||
4423 | /* PREFIX_VEX_0F45 */ |
4768 | /* PREFIX_VEX_0F45 */ |
4424 | { |
4769 | { |
4425 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, |
4770 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, |
- | 4771 | { Bad_Opcode }, |
|
- | 4772 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, |
|
4426 | }, |
4773 | }, |
4427 | 4774 | ||
4428 | /* PREFIX_VEX_0F46 */ |
4775 | /* PREFIX_VEX_0F46 */ |
4429 | { |
4776 | { |
4430 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, |
4777 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, |
- | 4778 | { Bad_Opcode }, |
|
- | 4779 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, |
|
4431 | }, |
4780 | }, |
4432 | 4781 | ||
4433 | /* PREFIX_VEX_0F47 */ |
4782 | /* PREFIX_VEX_0F47 */ |
4434 | { |
4783 | { |
4435 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, |
4784 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, |
- | 4785 | { Bad_Opcode }, |
|
- | 4786 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, |
|
4436 | }, |
4787 | }, |
4437 | 4788 | ||
4438 | /* PREFIX_VEX_0F4B */ |
4789 | /* PREFIX_VEX_0F4A */ |
- | 4790 | { |
|
4439 | { |
4791 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
- | 4792 | { Bad_Opcode }, |
|
- | 4793 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
|
- | 4794 | }, |
|
- | 4795 | ||
- | 4796 | /* PREFIX_VEX_0F4B */ |
|
- | 4797 | { |
|
4440 | { Bad_Opcode }, |
4798 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, |
4441 | { Bad_Opcode }, |
4799 | { Bad_Opcode }, |
4442 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, |
4800 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, |
4443 | }, |
4801 | }, |
4444 | 4802 | ||
4445 | /* PREFIX_VEX_0F51 */ |
4803 | /* PREFIX_VEX_0F51 */ |
4446 | { |
4804 | { |
4447 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4805 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4448 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, |
4806 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, |
4449 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, |
4807 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, |
4450 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, |
4808 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, |
4451 | }, |
4809 | }, |
4452 | 4810 | ||
4453 | /* PREFIX_VEX_0F52 */ |
4811 | /* PREFIX_VEX_0F52 */ |
4454 | { |
4812 | { |
4455 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4813 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4456 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, |
4814 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, |
4457 | }, |
4815 | }, |
4458 | 4816 | ||
4459 | /* PREFIX_VEX_0F53 */ |
4817 | /* PREFIX_VEX_0F53 */ |
4460 | { |
4818 | { |
4461 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4819 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4462 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, |
4820 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, |
4463 | }, |
4821 | }, |
4464 | 4822 | ||
4465 | /* PREFIX_VEX_0F58 */ |
4823 | /* PREFIX_VEX_0F58 */ |
4466 | { |
4824 | { |
4467 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4825 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4468 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, |
4826 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, |
4469 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, |
4827 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, |
4470 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, |
4828 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, |
4471 | }, |
4829 | }, |
4472 | 4830 | ||
4473 | /* PREFIX_VEX_0F59 */ |
4831 | /* PREFIX_VEX_0F59 */ |
4474 | { |
4832 | { |
4475 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4833 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4476 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, |
4834 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, |
4477 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, |
4835 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, |
4478 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, |
4836 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, |
4479 | }, |
4837 | }, |
4480 | 4838 | ||
4481 | /* PREFIX_VEX_0F5A */ |
4839 | /* PREFIX_VEX_0F5A */ |
4482 | { |
4840 | { |
4483 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4841 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4484 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, |
4842 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, |
4485 | { "vcvtpd2ps%XY", { XMM, EXx } }, |
4843 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
4486 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
4844 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
4487 | }, |
4845 | }, |
4488 | 4846 | ||
4489 | /* PREFIX_VEX_0F5B */ |
4847 | /* PREFIX_VEX_0F5B */ |
4490 | { |
4848 | { |
4491 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
4849 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
4492 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, |
4850 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, |
4493 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, |
4851 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, |
4494 | }, |
4852 | }, |
4495 | 4853 | ||
4496 | /* PREFIX_VEX_0F5C */ |
4854 | /* PREFIX_VEX_0F5C */ |
4497 | { |
4855 | { |
4498 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
4856 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
4499 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, |
4857 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, |
4500 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, |
4858 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, |
4501 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, |
4859 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, |
4502 | }, |
4860 | }, |
4503 | 4861 | ||
4504 | /* PREFIX_VEX_0F5D */ |
4862 | /* PREFIX_VEX_0F5D */ |
4505 | { |
4863 | { |
4506 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
4864 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
4507 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, |
4865 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, |
4508 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, |
4866 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, |
4509 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, |
4867 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, |
4510 | }, |
4868 | }, |
4511 | 4869 | ||
4512 | /* PREFIX_VEX_0F5E */ |
4870 | /* PREFIX_VEX_0F5E */ |
4513 | { |
4871 | { |
4514 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
4872 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
4515 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, |
4873 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, |
4516 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, |
4874 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, |
4517 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, |
4875 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, |
4518 | }, |
4876 | }, |
4519 | 4877 | ||
4520 | /* PREFIX_VEX_0F5F */ |
4878 | /* PREFIX_VEX_0F5F */ |
4521 | { |
4879 | { |
4522 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
4880 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
4523 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, |
4881 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, |
4524 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, |
4882 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, |
4525 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, |
4883 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, |
4526 | }, |
4884 | }, |
4527 | 4885 | ||
4528 | /* PREFIX_VEX_0F60 */ |
4886 | /* PREFIX_VEX_0F60 */ |
4529 | { |
4887 | { |
4530 | { Bad_Opcode }, |
4888 | { Bad_Opcode }, |
4531 | { Bad_Opcode }, |
4889 | { Bad_Opcode }, |
4532 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
4890 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
4533 | }, |
4891 | }, |
4534 | 4892 | ||
4535 | /* PREFIX_VEX_0F61 */ |
4893 | /* PREFIX_VEX_0F61 */ |
4536 | { |
4894 | { |
4537 | { Bad_Opcode }, |
4895 | { Bad_Opcode }, |
4538 | { Bad_Opcode }, |
4896 | { Bad_Opcode }, |
4539 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
4897 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
4540 | }, |
4898 | }, |
4541 | 4899 | ||
4542 | /* PREFIX_VEX_0F62 */ |
4900 | /* PREFIX_VEX_0F62 */ |
4543 | { |
4901 | { |
4544 | { Bad_Opcode }, |
4902 | { Bad_Opcode }, |
4545 | { Bad_Opcode }, |
4903 | { Bad_Opcode }, |
4546 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
4904 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
4547 | }, |
4905 | }, |
4548 | 4906 | ||
4549 | /* PREFIX_VEX_0F63 */ |
4907 | /* PREFIX_VEX_0F63 */ |
4550 | { |
4908 | { |
4551 | { Bad_Opcode }, |
4909 | { Bad_Opcode }, |
4552 | { Bad_Opcode }, |
4910 | { Bad_Opcode }, |
4553 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
4911 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
4554 | }, |
4912 | }, |
4555 | 4913 | ||
4556 | /* PREFIX_VEX_0F64 */ |
4914 | /* PREFIX_VEX_0F64 */ |
4557 | { |
4915 | { |
4558 | { Bad_Opcode }, |
4916 | { Bad_Opcode }, |
4559 | { Bad_Opcode }, |
4917 | { Bad_Opcode }, |
4560 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
4918 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
4561 | }, |
4919 | }, |
4562 | 4920 | ||
4563 | /* PREFIX_VEX_0F65 */ |
4921 | /* PREFIX_VEX_0F65 */ |
4564 | { |
4922 | { |
4565 | { Bad_Opcode }, |
4923 | { Bad_Opcode }, |
4566 | { Bad_Opcode }, |
4924 | { Bad_Opcode }, |
4567 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
4925 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
4568 | }, |
4926 | }, |
4569 | 4927 | ||
4570 | /* PREFIX_VEX_0F66 */ |
4928 | /* PREFIX_VEX_0F66 */ |
4571 | { |
4929 | { |
4572 | { Bad_Opcode }, |
4930 | { Bad_Opcode }, |
4573 | { Bad_Opcode }, |
4931 | { Bad_Opcode }, |
4574 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
4932 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
4575 | }, |
4933 | }, |
4576 | 4934 | ||
4577 | /* PREFIX_VEX_0F67 */ |
4935 | /* PREFIX_VEX_0F67 */ |
4578 | { |
4936 | { |
4579 | { Bad_Opcode }, |
4937 | { Bad_Opcode }, |
4580 | { Bad_Opcode }, |
4938 | { Bad_Opcode }, |
4581 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
4939 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
4582 | }, |
4940 | }, |
4583 | 4941 | ||
4584 | /* PREFIX_VEX_0F68 */ |
4942 | /* PREFIX_VEX_0F68 */ |
4585 | { |
4943 | { |
4586 | { Bad_Opcode }, |
4944 | { Bad_Opcode }, |
4587 | { Bad_Opcode }, |
4945 | { Bad_Opcode }, |
4588 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
4946 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
4589 | }, |
4947 | }, |
4590 | 4948 | ||
4591 | /* PREFIX_VEX_0F69 */ |
4949 | /* PREFIX_VEX_0F69 */ |
4592 | { |
4950 | { |
4593 | { Bad_Opcode }, |
4951 | { Bad_Opcode }, |
4594 | { Bad_Opcode }, |
4952 | { Bad_Opcode }, |
4595 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
4953 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
4596 | }, |
4954 | }, |
4597 | 4955 | ||
4598 | /* PREFIX_VEX_0F6A */ |
4956 | /* PREFIX_VEX_0F6A */ |
4599 | { |
4957 | { |
4600 | { Bad_Opcode }, |
4958 | { Bad_Opcode }, |
4601 | { Bad_Opcode }, |
4959 | { Bad_Opcode }, |
4602 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
4960 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
4603 | }, |
4961 | }, |
4604 | 4962 | ||
4605 | /* PREFIX_VEX_0F6B */ |
4963 | /* PREFIX_VEX_0F6B */ |
4606 | { |
4964 | { |
4607 | { Bad_Opcode }, |
4965 | { Bad_Opcode }, |
4608 | { Bad_Opcode }, |
4966 | { Bad_Opcode }, |
4609 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
4967 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
4610 | }, |
4968 | }, |
4611 | 4969 | ||
4612 | /* PREFIX_VEX_0F6C */ |
4970 | /* PREFIX_VEX_0F6C */ |
4613 | { |
4971 | { |
4614 | { Bad_Opcode }, |
4972 | { Bad_Opcode }, |
4615 | { Bad_Opcode }, |
4973 | { Bad_Opcode }, |
4616 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
4974 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
4617 | }, |
4975 | }, |
4618 | 4976 | ||
4619 | /* PREFIX_VEX_0F6D */ |
4977 | /* PREFIX_VEX_0F6D */ |
4620 | { |
4978 | { |
4621 | { Bad_Opcode }, |
4979 | { Bad_Opcode }, |
4622 | { Bad_Opcode }, |
4980 | { Bad_Opcode }, |
4623 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
4981 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
4624 | }, |
4982 | }, |
4625 | 4983 | ||
4626 | /* PREFIX_VEX_0F6E */ |
4984 | /* PREFIX_VEX_0F6E */ |
4627 | { |
4985 | { |
4628 | { Bad_Opcode }, |
4986 | { Bad_Opcode }, |
4629 | { Bad_Opcode }, |
4987 | { Bad_Opcode }, |
4630 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
4988 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
4631 | }, |
4989 | }, |
4632 | 4990 | ||
4633 | /* PREFIX_VEX_0F6F */ |
4991 | /* PREFIX_VEX_0F6F */ |
4634 | { |
4992 | { |
4635 | { Bad_Opcode }, |
4993 | { Bad_Opcode }, |
4636 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
4994 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
4637 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, |
4995 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, |
4638 | }, |
4996 | }, |
4639 | 4997 | ||
4640 | /* PREFIX_VEX_0F70 */ |
4998 | /* PREFIX_VEX_0F70 */ |
4641 | { |
4999 | { |
4642 | { Bad_Opcode }, |
5000 | { Bad_Opcode }, |
4643 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
5001 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
4644 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, |
5002 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, |
4645 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, |
5003 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, |
4646 | }, |
5004 | }, |
4647 | 5005 | ||
4648 | /* PREFIX_VEX_0F71_REG_2 */ |
5006 | /* PREFIX_VEX_0F71_REG_2 */ |
4649 | { |
5007 | { |
4650 | { Bad_Opcode }, |
5008 | { Bad_Opcode }, |
4651 | { Bad_Opcode }, |
5009 | { Bad_Opcode }, |
4652 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
5010 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
4653 | }, |
5011 | }, |
4654 | 5012 | ||
4655 | /* PREFIX_VEX_0F71_REG_4 */ |
5013 | /* PREFIX_VEX_0F71_REG_4 */ |
4656 | { |
5014 | { |
4657 | { Bad_Opcode }, |
5015 | { Bad_Opcode }, |
4658 | { Bad_Opcode }, |
5016 | { Bad_Opcode }, |
4659 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
5017 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
4660 | }, |
5018 | }, |
4661 | 5019 | ||
4662 | /* PREFIX_VEX_0F71_REG_6 */ |
5020 | /* PREFIX_VEX_0F71_REG_6 */ |
4663 | { |
5021 | { |
4664 | { Bad_Opcode }, |
5022 | { Bad_Opcode }, |
4665 | { Bad_Opcode }, |
5023 | { Bad_Opcode }, |
4666 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
5024 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
4667 | }, |
5025 | }, |
4668 | 5026 | ||
4669 | /* PREFIX_VEX_0F72_REG_2 */ |
5027 | /* PREFIX_VEX_0F72_REG_2 */ |
4670 | { |
5028 | { |
4671 | { Bad_Opcode }, |
5029 | { Bad_Opcode }, |
4672 | { Bad_Opcode }, |
5030 | { Bad_Opcode }, |
4673 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
5031 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
4674 | }, |
5032 | }, |
4675 | 5033 | ||
4676 | /* PREFIX_VEX_0F72_REG_4 */ |
5034 | /* PREFIX_VEX_0F72_REG_4 */ |
4677 | { |
5035 | { |
4678 | { Bad_Opcode }, |
5036 | { Bad_Opcode }, |
4679 | { Bad_Opcode }, |
5037 | { Bad_Opcode }, |
4680 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
5038 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
4681 | }, |
5039 | }, |
4682 | 5040 | ||
4683 | /* PREFIX_VEX_0F72_REG_6 */ |
5041 | /* PREFIX_VEX_0F72_REG_6 */ |
4684 | { |
5042 | { |
4685 | { Bad_Opcode }, |
5043 | { Bad_Opcode }, |
4686 | { Bad_Opcode }, |
5044 | { Bad_Opcode }, |
4687 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
5045 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
4688 | }, |
5046 | }, |
4689 | 5047 | ||
4690 | /* PREFIX_VEX_0F73_REG_2 */ |
5048 | /* PREFIX_VEX_0F73_REG_2 */ |
4691 | { |
5049 | { |
4692 | { Bad_Opcode }, |
5050 | { Bad_Opcode }, |
4693 | { Bad_Opcode }, |
5051 | { Bad_Opcode }, |
4694 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
5052 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
4695 | }, |
5053 | }, |
4696 | 5054 | ||
4697 | /* PREFIX_VEX_0F73_REG_3 */ |
5055 | /* PREFIX_VEX_0F73_REG_3 */ |
4698 | { |
5056 | { |
4699 | { Bad_Opcode }, |
5057 | { Bad_Opcode }, |
4700 | { Bad_Opcode }, |
5058 | { Bad_Opcode }, |
4701 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
5059 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
4702 | }, |
5060 | }, |
4703 | 5061 | ||
4704 | /* PREFIX_VEX_0F73_REG_6 */ |
5062 | /* PREFIX_VEX_0F73_REG_6 */ |
4705 | { |
5063 | { |
4706 | { Bad_Opcode }, |
5064 | { Bad_Opcode }, |
4707 | { Bad_Opcode }, |
5065 | { Bad_Opcode }, |
4708 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
5066 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
4709 | }, |
5067 | }, |
4710 | 5068 | ||
4711 | /* PREFIX_VEX_0F73_REG_7 */ |
5069 | /* PREFIX_VEX_0F73_REG_7 */ |
4712 | { |
5070 | { |
4713 | { Bad_Opcode }, |
5071 | { Bad_Opcode }, |
4714 | { Bad_Opcode }, |
5072 | { Bad_Opcode }, |
4715 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
5073 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
4716 | }, |
5074 | }, |
4717 | 5075 | ||
4718 | /* PREFIX_VEX_0F74 */ |
5076 | /* PREFIX_VEX_0F74 */ |
4719 | { |
5077 | { |
4720 | { Bad_Opcode }, |
5078 | { Bad_Opcode }, |
4721 | { Bad_Opcode }, |
5079 | { Bad_Opcode }, |
4722 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
5080 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
4723 | }, |
5081 | }, |
4724 | 5082 | ||
4725 | /* PREFIX_VEX_0F75 */ |
5083 | /* PREFIX_VEX_0F75 */ |
4726 | { |
5084 | { |
4727 | { Bad_Opcode }, |
5085 | { Bad_Opcode }, |
4728 | { Bad_Opcode }, |
5086 | { Bad_Opcode }, |
4729 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
5087 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
4730 | }, |
5088 | }, |
4731 | 5089 | ||
4732 | /* PREFIX_VEX_0F76 */ |
5090 | /* PREFIX_VEX_0F76 */ |
4733 | { |
5091 | { |
4734 | { Bad_Opcode }, |
5092 | { Bad_Opcode }, |
4735 | { Bad_Opcode }, |
5093 | { Bad_Opcode }, |
4736 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
5094 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
4737 | }, |
5095 | }, |
4738 | 5096 | ||
4739 | /* PREFIX_VEX_0F77 */ |
5097 | /* PREFIX_VEX_0F77 */ |
4740 | { |
5098 | { |
4741 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
5099 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
4742 | }, |
5100 | }, |
4743 | 5101 | ||
4744 | /* PREFIX_VEX_0F7C */ |
5102 | /* PREFIX_VEX_0F7C */ |
4745 | { |
5103 | { |
4746 | { Bad_Opcode }, |
5104 | { Bad_Opcode }, |
4747 | { Bad_Opcode }, |
5105 | { Bad_Opcode }, |
4748 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
5106 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
4749 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, |
5107 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, |
4750 | }, |
5108 | }, |
4751 | 5109 | ||
4752 | /* PREFIX_VEX_0F7D */ |
5110 | /* PREFIX_VEX_0F7D */ |
4753 | { |
5111 | { |
4754 | { Bad_Opcode }, |
5112 | { Bad_Opcode }, |
4755 | { Bad_Opcode }, |
5113 | { Bad_Opcode }, |
4756 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
5114 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
4757 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, |
5115 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, |
4758 | }, |
5116 | }, |
4759 | 5117 | ||
4760 | /* PREFIX_VEX_0F7E */ |
5118 | /* PREFIX_VEX_0F7E */ |
4761 | { |
5119 | { |
4762 | { Bad_Opcode }, |
5120 | { Bad_Opcode }, |
4763 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5121 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
4764 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, |
5122 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, |
4765 | }, |
5123 | }, |
4766 | 5124 | ||
4767 | /* PREFIX_VEX_0F7F */ |
5125 | /* PREFIX_VEX_0F7F */ |
4768 | { |
5126 | { |
4769 | { Bad_Opcode }, |
5127 | { Bad_Opcode }, |
4770 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
5128 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
4771 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, |
5129 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, |
4772 | }, |
5130 | }, |
4773 | 5131 | ||
4774 | /* PREFIX_VEX_0F90 */ |
5132 | /* PREFIX_VEX_0F90 */ |
4775 | { |
5133 | { |
4776 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, |
5134 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, |
- | 5135 | { Bad_Opcode }, |
|
- | 5136 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, |
|
4777 | }, |
5137 | }, |
4778 | 5138 | ||
4779 | /* PREFIX_VEX_0F91 */ |
5139 | /* PREFIX_VEX_0F91 */ |
4780 | { |
5140 | { |
4781 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, |
5141 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, |
- | 5142 | { Bad_Opcode }, |
|
- | 5143 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, |
|
4782 | }, |
5144 | }, |
4783 | 5145 | ||
4784 | /* PREFIX_VEX_0F92 */ |
5146 | /* PREFIX_VEX_0F92 */ |
4785 | { |
5147 | { |
4786 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, |
5148 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, |
- | 5149 | { Bad_Opcode }, |
|
- | 5150 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
|
- | 5151 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
|
4787 | }, |
5152 | }, |
4788 | 5153 | ||
4789 | /* PREFIX_VEX_0F93 */ |
5154 | /* PREFIX_VEX_0F93 */ |
4790 | { |
5155 | { |
4791 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, |
5156 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, |
- | 5157 | { Bad_Opcode }, |
|
- | 5158 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
|
- | 5159 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
|
4792 | }, |
5160 | }, |
4793 | 5161 | ||
4794 | /* PREFIX_VEX_0F98 */ |
5162 | /* PREFIX_VEX_0F98 */ |
4795 | { |
5163 | { |
4796 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, |
5164 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, |
- | 5165 | { Bad_Opcode }, |
|
- | 5166 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, |
|
- | 5167 | }, |
|
- | 5168 | ||
- | 5169 | /* PREFIX_VEX_0F99 */ |
|
- | 5170 | { |
|
- | 5171 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, |
|
- | 5172 | { Bad_Opcode }, |
|
- | 5173 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, |
|
4797 | }, |
5174 | }, |
4798 | 5175 | ||
4799 | /* PREFIX_VEX_0FC2 */ |
5176 | /* PREFIX_VEX_0FC2 */ |
4800 | { |
5177 | { |
4801 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
5178 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
4802 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, |
5179 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, |
4803 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, |
5180 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, |
4804 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, |
5181 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, |
4805 | }, |
5182 | }, |
4806 | 5183 | ||
4807 | /* PREFIX_VEX_0FC4 */ |
5184 | /* PREFIX_VEX_0FC4 */ |
4808 | { |
5185 | { |
4809 | { Bad_Opcode }, |
5186 | { Bad_Opcode }, |
4810 | { Bad_Opcode }, |
5187 | { Bad_Opcode }, |
4811 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
5188 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
4812 | }, |
5189 | }, |
4813 | 5190 | ||
4814 | /* PREFIX_VEX_0FC5 */ |
5191 | /* PREFIX_VEX_0FC5 */ |
4815 | { |
5192 | { |
4816 | { Bad_Opcode }, |
5193 | { Bad_Opcode }, |
4817 | { Bad_Opcode }, |
5194 | { Bad_Opcode }, |
4818 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
5195 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
4819 | }, |
5196 | }, |
4820 | 5197 | ||
4821 | /* PREFIX_VEX_0FD0 */ |
5198 | /* PREFIX_VEX_0FD0 */ |
4822 | { |
5199 | { |
4823 | { Bad_Opcode }, |
5200 | { Bad_Opcode }, |
4824 | { Bad_Opcode }, |
5201 | { Bad_Opcode }, |
4825 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
5202 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
4826 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, |
5203 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, |
4827 | }, |
5204 | }, |
4828 | 5205 | ||
4829 | /* PREFIX_VEX_0FD1 */ |
5206 | /* PREFIX_VEX_0FD1 */ |
4830 | { |
5207 | { |
4831 | { Bad_Opcode }, |
5208 | { Bad_Opcode }, |
4832 | { Bad_Opcode }, |
5209 | { Bad_Opcode }, |
4833 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
5210 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
4834 | }, |
5211 | }, |
4835 | 5212 | ||
4836 | /* PREFIX_VEX_0FD2 */ |
5213 | /* PREFIX_VEX_0FD2 */ |
4837 | { |
5214 | { |
4838 | { Bad_Opcode }, |
5215 | { Bad_Opcode }, |
4839 | { Bad_Opcode }, |
5216 | { Bad_Opcode }, |
4840 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
5217 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
4841 | }, |
5218 | }, |
4842 | 5219 | ||
4843 | /* PREFIX_VEX_0FD3 */ |
5220 | /* PREFIX_VEX_0FD3 */ |
4844 | { |
5221 | { |
4845 | { Bad_Opcode }, |
5222 | { Bad_Opcode }, |
4846 | { Bad_Opcode }, |
5223 | { Bad_Opcode }, |
4847 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
5224 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
4848 | }, |
5225 | }, |
4849 | 5226 | ||
4850 | /* PREFIX_VEX_0FD4 */ |
5227 | /* PREFIX_VEX_0FD4 */ |
4851 | { |
5228 | { |
4852 | { Bad_Opcode }, |
5229 | { Bad_Opcode }, |
4853 | { Bad_Opcode }, |
5230 | { Bad_Opcode }, |
4854 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
5231 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
4855 | }, |
5232 | }, |
4856 | 5233 | ||
4857 | /* PREFIX_VEX_0FD5 */ |
5234 | /* PREFIX_VEX_0FD5 */ |
4858 | { |
5235 | { |
4859 | { Bad_Opcode }, |
5236 | { Bad_Opcode }, |
4860 | { Bad_Opcode }, |
5237 | { Bad_Opcode }, |
4861 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
5238 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
4862 | }, |
5239 | }, |
4863 | 5240 | ||
4864 | /* PREFIX_VEX_0FD6 */ |
5241 | /* PREFIX_VEX_0FD6 */ |
4865 | { |
5242 | { |
4866 | { Bad_Opcode }, |
5243 | { Bad_Opcode }, |
4867 | { Bad_Opcode }, |
5244 | { Bad_Opcode }, |
4868 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
5245 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
4869 | }, |
5246 | }, |
4870 | 5247 | ||
4871 | /* PREFIX_VEX_0FD7 */ |
5248 | /* PREFIX_VEX_0FD7 */ |
4872 | { |
5249 | { |
4873 | { Bad_Opcode }, |
5250 | { Bad_Opcode }, |
4874 | { Bad_Opcode }, |
5251 | { Bad_Opcode }, |
4875 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
5252 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
4876 | }, |
5253 | }, |
4877 | 5254 | ||
4878 | /* PREFIX_VEX_0FD8 */ |
5255 | /* PREFIX_VEX_0FD8 */ |
4879 | { |
5256 | { |
4880 | { Bad_Opcode }, |
5257 | { Bad_Opcode }, |
4881 | { Bad_Opcode }, |
5258 | { Bad_Opcode }, |
4882 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
5259 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
4883 | }, |
5260 | }, |
4884 | 5261 | ||
4885 | /* PREFIX_VEX_0FD9 */ |
5262 | /* PREFIX_VEX_0FD9 */ |
4886 | { |
5263 | { |
4887 | { Bad_Opcode }, |
5264 | { Bad_Opcode }, |
4888 | { Bad_Opcode }, |
5265 | { Bad_Opcode }, |
4889 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
5266 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
4890 | }, |
5267 | }, |
4891 | 5268 | ||
4892 | /* PREFIX_VEX_0FDA */ |
5269 | /* PREFIX_VEX_0FDA */ |
4893 | { |
5270 | { |
4894 | { Bad_Opcode }, |
5271 | { Bad_Opcode }, |
4895 | { Bad_Opcode }, |
5272 | { Bad_Opcode }, |
4896 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
5273 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
4897 | }, |
5274 | }, |
4898 | 5275 | ||
4899 | /* PREFIX_VEX_0FDB */ |
5276 | /* PREFIX_VEX_0FDB */ |
4900 | { |
5277 | { |
4901 | { Bad_Opcode }, |
5278 | { Bad_Opcode }, |
4902 | { Bad_Opcode }, |
5279 | { Bad_Opcode }, |
4903 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
5280 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
4904 | }, |
5281 | }, |
4905 | 5282 | ||
4906 | /* PREFIX_VEX_0FDC */ |
5283 | /* PREFIX_VEX_0FDC */ |
4907 | { |
5284 | { |
4908 | { Bad_Opcode }, |
5285 | { Bad_Opcode }, |
4909 | { Bad_Opcode }, |
5286 | { Bad_Opcode }, |
4910 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
5287 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
4911 | }, |
5288 | }, |
4912 | 5289 | ||
4913 | /* PREFIX_VEX_0FDD */ |
5290 | /* PREFIX_VEX_0FDD */ |
4914 | { |
5291 | { |
4915 | { Bad_Opcode }, |
5292 | { Bad_Opcode }, |
4916 | { Bad_Opcode }, |
5293 | { Bad_Opcode }, |
4917 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
5294 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
4918 | }, |
5295 | }, |
4919 | 5296 | ||
4920 | /* PREFIX_VEX_0FDE */ |
5297 | /* PREFIX_VEX_0FDE */ |
4921 | { |
5298 | { |
4922 | { Bad_Opcode }, |
5299 | { Bad_Opcode }, |
4923 | { Bad_Opcode }, |
5300 | { Bad_Opcode }, |
4924 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
5301 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
4925 | }, |
5302 | }, |
4926 | 5303 | ||
4927 | /* PREFIX_VEX_0FDF */ |
5304 | /* PREFIX_VEX_0FDF */ |
4928 | { |
5305 | { |
4929 | { Bad_Opcode }, |
5306 | { Bad_Opcode }, |
4930 | { Bad_Opcode }, |
5307 | { Bad_Opcode }, |
4931 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
5308 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
4932 | }, |
5309 | }, |
4933 | 5310 | ||
4934 | /* PREFIX_VEX_0FE0 */ |
5311 | /* PREFIX_VEX_0FE0 */ |
4935 | { |
5312 | { |
4936 | { Bad_Opcode }, |
5313 | { Bad_Opcode }, |
4937 | { Bad_Opcode }, |
5314 | { Bad_Opcode }, |
4938 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
5315 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
4939 | }, |
5316 | }, |
4940 | 5317 | ||
4941 | /* PREFIX_VEX_0FE1 */ |
5318 | /* PREFIX_VEX_0FE1 */ |
4942 | { |
5319 | { |
4943 | { Bad_Opcode }, |
5320 | { Bad_Opcode }, |
4944 | { Bad_Opcode }, |
5321 | { Bad_Opcode }, |
4945 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
5322 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
4946 | }, |
5323 | }, |
4947 | 5324 | ||
4948 | /* PREFIX_VEX_0FE2 */ |
5325 | /* PREFIX_VEX_0FE2 */ |
4949 | { |
5326 | { |
4950 | { Bad_Opcode }, |
5327 | { Bad_Opcode }, |
4951 | { Bad_Opcode }, |
5328 | { Bad_Opcode }, |
4952 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
5329 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
4953 | }, |
5330 | }, |
4954 | 5331 | ||
4955 | /* PREFIX_VEX_0FE3 */ |
5332 | /* PREFIX_VEX_0FE3 */ |
4956 | { |
5333 | { |
4957 | { Bad_Opcode }, |
5334 | { Bad_Opcode }, |
4958 | { Bad_Opcode }, |
5335 | { Bad_Opcode }, |
4959 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
5336 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
4960 | }, |
5337 | }, |
4961 | 5338 | ||
4962 | /* PREFIX_VEX_0FE4 */ |
5339 | /* PREFIX_VEX_0FE4 */ |
4963 | { |
5340 | { |
4964 | { Bad_Opcode }, |
5341 | { Bad_Opcode }, |
4965 | { Bad_Opcode }, |
5342 | { Bad_Opcode }, |
4966 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
5343 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
4967 | }, |
5344 | }, |
4968 | 5345 | ||
4969 | /* PREFIX_VEX_0FE5 */ |
5346 | /* PREFIX_VEX_0FE5 */ |
4970 | { |
5347 | { |
4971 | { Bad_Opcode }, |
5348 | { Bad_Opcode }, |
4972 | { Bad_Opcode }, |
5349 | { Bad_Opcode }, |
4973 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
5350 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
4974 | }, |
5351 | }, |
4975 | 5352 | ||
4976 | /* PREFIX_VEX_0FE6 */ |
5353 | /* PREFIX_VEX_0FE6 */ |
4977 | { |
5354 | { |
4978 | { Bad_Opcode }, |
5355 | { Bad_Opcode }, |
4979 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
5356 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
4980 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, |
5357 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, |
4981 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, |
5358 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, |
4982 | }, |
5359 | }, |
4983 | 5360 | ||
4984 | /* PREFIX_VEX_0FE7 */ |
5361 | /* PREFIX_VEX_0FE7 */ |
4985 | { |
5362 | { |
4986 | { Bad_Opcode }, |
5363 | { Bad_Opcode }, |
4987 | { Bad_Opcode }, |
5364 | { Bad_Opcode }, |
4988 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
5365 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
4989 | }, |
5366 | }, |
4990 | 5367 | ||
4991 | /* PREFIX_VEX_0FE8 */ |
5368 | /* PREFIX_VEX_0FE8 */ |
4992 | { |
5369 | { |
4993 | { Bad_Opcode }, |
5370 | { Bad_Opcode }, |
4994 | { Bad_Opcode }, |
5371 | { Bad_Opcode }, |
4995 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
5372 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
4996 | }, |
5373 | }, |
4997 | 5374 | ||
4998 | /* PREFIX_VEX_0FE9 */ |
5375 | /* PREFIX_VEX_0FE9 */ |
4999 | { |
5376 | { |
5000 | { Bad_Opcode }, |
5377 | { Bad_Opcode }, |
5001 | { Bad_Opcode }, |
5378 | { Bad_Opcode }, |
5002 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
5379 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
5003 | }, |
5380 | }, |
5004 | 5381 | ||
5005 | /* PREFIX_VEX_0FEA */ |
5382 | /* PREFIX_VEX_0FEA */ |
5006 | { |
5383 | { |
5007 | { Bad_Opcode }, |
5384 | { Bad_Opcode }, |
5008 | { Bad_Opcode }, |
5385 | { Bad_Opcode }, |
5009 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
5386 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
5010 | }, |
5387 | }, |
5011 | 5388 | ||
5012 | /* PREFIX_VEX_0FEB */ |
5389 | /* PREFIX_VEX_0FEB */ |
5013 | { |
5390 | { |
5014 | { Bad_Opcode }, |
5391 | { Bad_Opcode }, |
5015 | { Bad_Opcode }, |
5392 | { Bad_Opcode }, |
5016 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
5393 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
5017 | }, |
5394 | }, |
5018 | 5395 | ||
5019 | /* PREFIX_VEX_0FEC */ |
5396 | /* PREFIX_VEX_0FEC */ |
5020 | { |
5397 | { |
5021 | { Bad_Opcode }, |
5398 | { Bad_Opcode }, |
5022 | { Bad_Opcode }, |
5399 | { Bad_Opcode }, |
5023 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
5400 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
5024 | }, |
5401 | }, |
5025 | 5402 | ||
5026 | /* PREFIX_VEX_0FED */ |
5403 | /* PREFIX_VEX_0FED */ |
5027 | { |
5404 | { |
5028 | { Bad_Opcode }, |
5405 | { Bad_Opcode }, |
5029 | { Bad_Opcode }, |
5406 | { Bad_Opcode }, |
5030 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
5407 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
5031 | }, |
5408 | }, |
5032 | 5409 | ||
5033 | /* PREFIX_VEX_0FEE */ |
5410 | /* PREFIX_VEX_0FEE */ |
5034 | { |
5411 | { |
5035 | { Bad_Opcode }, |
5412 | { Bad_Opcode }, |
5036 | { Bad_Opcode }, |
5413 | { Bad_Opcode }, |
5037 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
5414 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
5038 | }, |
5415 | }, |
5039 | 5416 | ||
5040 | /* PREFIX_VEX_0FEF */ |
5417 | /* PREFIX_VEX_0FEF */ |
5041 | { |
5418 | { |
5042 | { Bad_Opcode }, |
5419 | { Bad_Opcode }, |
5043 | { Bad_Opcode }, |
5420 | { Bad_Opcode }, |
5044 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
5421 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
5045 | }, |
5422 | }, |
5046 | 5423 | ||
5047 | /* PREFIX_VEX_0FF0 */ |
5424 | /* PREFIX_VEX_0FF0 */ |
5048 | { |
5425 | { |
5049 | { Bad_Opcode }, |
5426 | { Bad_Opcode }, |
5050 | { Bad_Opcode }, |
5427 | { Bad_Opcode }, |
5051 | { Bad_Opcode }, |
5428 | { Bad_Opcode }, |
5052 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
5429 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
5053 | }, |
5430 | }, |
5054 | 5431 | ||
5055 | /* PREFIX_VEX_0FF1 */ |
5432 | /* PREFIX_VEX_0FF1 */ |
5056 | { |
5433 | { |
5057 | { Bad_Opcode }, |
5434 | { Bad_Opcode }, |
5058 | { Bad_Opcode }, |
5435 | { Bad_Opcode }, |
5059 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
5436 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
5060 | }, |
5437 | }, |
5061 | 5438 | ||
5062 | /* PREFIX_VEX_0FF2 */ |
5439 | /* PREFIX_VEX_0FF2 */ |
5063 | { |
5440 | { |
5064 | { Bad_Opcode }, |
5441 | { Bad_Opcode }, |
5065 | { Bad_Opcode }, |
5442 | { Bad_Opcode }, |
5066 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
5443 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
5067 | }, |
5444 | }, |
5068 | 5445 | ||
5069 | /* PREFIX_VEX_0FF3 */ |
5446 | /* PREFIX_VEX_0FF3 */ |
5070 | { |
5447 | { |
5071 | { Bad_Opcode }, |
5448 | { Bad_Opcode }, |
5072 | { Bad_Opcode }, |
5449 | { Bad_Opcode }, |
5073 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
5450 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
5074 | }, |
5451 | }, |
5075 | 5452 | ||
5076 | /* PREFIX_VEX_0FF4 */ |
5453 | /* PREFIX_VEX_0FF4 */ |
5077 | { |
5454 | { |
5078 | { Bad_Opcode }, |
5455 | { Bad_Opcode }, |
5079 | { Bad_Opcode }, |
5456 | { Bad_Opcode }, |
5080 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
5457 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
5081 | }, |
5458 | }, |
5082 | 5459 | ||
5083 | /* PREFIX_VEX_0FF5 */ |
5460 | /* PREFIX_VEX_0FF5 */ |
5084 | { |
5461 | { |
5085 | { Bad_Opcode }, |
5462 | { Bad_Opcode }, |
5086 | { Bad_Opcode }, |
5463 | { Bad_Opcode }, |
5087 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
5464 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
5088 | }, |
5465 | }, |
5089 | 5466 | ||
5090 | /* PREFIX_VEX_0FF6 */ |
5467 | /* PREFIX_VEX_0FF6 */ |
5091 | { |
5468 | { |
5092 | { Bad_Opcode }, |
5469 | { Bad_Opcode }, |
5093 | { Bad_Opcode }, |
5470 | { Bad_Opcode }, |
5094 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
5471 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
5095 | }, |
5472 | }, |
5096 | 5473 | ||
5097 | /* PREFIX_VEX_0FF7 */ |
5474 | /* PREFIX_VEX_0FF7 */ |
5098 | { |
5475 | { |
5099 | { Bad_Opcode }, |
5476 | { Bad_Opcode }, |
5100 | { Bad_Opcode }, |
5477 | { Bad_Opcode }, |
5101 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
5478 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
5102 | }, |
5479 | }, |
5103 | 5480 | ||
5104 | /* PREFIX_VEX_0FF8 */ |
5481 | /* PREFIX_VEX_0FF8 */ |
5105 | { |
5482 | { |
5106 | { Bad_Opcode }, |
5483 | { Bad_Opcode }, |
5107 | { Bad_Opcode }, |
5484 | { Bad_Opcode }, |
5108 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
5485 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
5109 | }, |
5486 | }, |
5110 | 5487 | ||
5111 | /* PREFIX_VEX_0FF9 */ |
5488 | /* PREFIX_VEX_0FF9 */ |
5112 | { |
5489 | { |
5113 | { Bad_Opcode }, |
5490 | { Bad_Opcode }, |
5114 | { Bad_Opcode }, |
5491 | { Bad_Opcode }, |
5115 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
5492 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
5116 | }, |
5493 | }, |
5117 | 5494 | ||
5118 | /* PREFIX_VEX_0FFA */ |
5495 | /* PREFIX_VEX_0FFA */ |
5119 | { |
5496 | { |
5120 | { Bad_Opcode }, |
5497 | { Bad_Opcode }, |
5121 | { Bad_Opcode }, |
5498 | { Bad_Opcode }, |
5122 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
5499 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
5123 | }, |
5500 | }, |
5124 | 5501 | ||
5125 | /* PREFIX_VEX_0FFB */ |
5502 | /* PREFIX_VEX_0FFB */ |
5126 | { |
5503 | { |
5127 | { Bad_Opcode }, |
5504 | { Bad_Opcode }, |
5128 | { Bad_Opcode }, |
5505 | { Bad_Opcode }, |
5129 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
5506 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
5130 | }, |
5507 | }, |
5131 | 5508 | ||
5132 | /* PREFIX_VEX_0FFC */ |
5509 | /* PREFIX_VEX_0FFC */ |
5133 | { |
5510 | { |
5134 | { Bad_Opcode }, |
5511 | { Bad_Opcode }, |
5135 | { Bad_Opcode }, |
5512 | { Bad_Opcode }, |
5136 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
5513 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
5137 | }, |
5514 | }, |
5138 | 5515 | ||
5139 | /* PREFIX_VEX_0FFD */ |
5516 | /* PREFIX_VEX_0FFD */ |
5140 | { |
5517 | { |
5141 | { Bad_Opcode }, |
5518 | { Bad_Opcode }, |
5142 | { Bad_Opcode }, |
5519 | { Bad_Opcode }, |
5143 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
5520 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
5144 | }, |
5521 | }, |
5145 | 5522 | ||
5146 | /* PREFIX_VEX_0FFE */ |
5523 | /* PREFIX_VEX_0FFE */ |
5147 | { |
5524 | { |
5148 | { Bad_Opcode }, |
5525 | { Bad_Opcode }, |
5149 | { Bad_Opcode }, |
5526 | { Bad_Opcode }, |
5150 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
5527 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
5151 | }, |
5528 | }, |
5152 | 5529 | ||
5153 | /* PREFIX_VEX_0F3800 */ |
5530 | /* PREFIX_VEX_0F3800 */ |
5154 | { |
5531 | { |
5155 | { Bad_Opcode }, |
5532 | { Bad_Opcode }, |
5156 | { Bad_Opcode }, |
5533 | { Bad_Opcode }, |
5157 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
5534 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
5158 | }, |
5535 | }, |
5159 | 5536 | ||
5160 | /* PREFIX_VEX_0F3801 */ |
5537 | /* PREFIX_VEX_0F3801 */ |
5161 | { |
5538 | { |
5162 | { Bad_Opcode }, |
5539 | { Bad_Opcode }, |
5163 | { Bad_Opcode }, |
5540 | { Bad_Opcode }, |
5164 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
5541 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
5165 | }, |
5542 | }, |
5166 | 5543 | ||
5167 | /* PREFIX_VEX_0F3802 */ |
5544 | /* PREFIX_VEX_0F3802 */ |
5168 | { |
5545 | { |
5169 | { Bad_Opcode }, |
5546 | { Bad_Opcode }, |
5170 | { Bad_Opcode }, |
5547 | { Bad_Opcode }, |
5171 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
5548 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
5172 | }, |
5549 | }, |
5173 | 5550 | ||
5174 | /* PREFIX_VEX_0F3803 */ |
5551 | /* PREFIX_VEX_0F3803 */ |
5175 | { |
5552 | { |
5176 | { Bad_Opcode }, |
5553 | { Bad_Opcode }, |
5177 | { Bad_Opcode }, |
5554 | { Bad_Opcode }, |
5178 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
5555 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
5179 | }, |
5556 | }, |
5180 | 5557 | ||
5181 | /* PREFIX_VEX_0F3804 */ |
5558 | /* PREFIX_VEX_0F3804 */ |
5182 | { |
5559 | { |
5183 | { Bad_Opcode }, |
5560 | { Bad_Opcode }, |
5184 | { Bad_Opcode }, |
5561 | { Bad_Opcode }, |
5185 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
5562 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
5186 | }, |
5563 | }, |
5187 | 5564 | ||
5188 | /* PREFIX_VEX_0F3805 */ |
5565 | /* PREFIX_VEX_0F3805 */ |
5189 | { |
5566 | { |
5190 | { Bad_Opcode }, |
5567 | { Bad_Opcode }, |
5191 | { Bad_Opcode }, |
5568 | { Bad_Opcode }, |
5192 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
5569 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
5193 | }, |
5570 | }, |
5194 | 5571 | ||
5195 | /* PREFIX_VEX_0F3806 */ |
5572 | /* PREFIX_VEX_0F3806 */ |
5196 | { |
5573 | { |
5197 | { Bad_Opcode }, |
5574 | { Bad_Opcode }, |
5198 | { Bad_Opcode }, |
5575 | { Bad_Opcode }, |
5199 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
5576 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
5200 | }, |
5577 | }, |
5201 | 5578 | ||
5202 | /* PREFIX_VEX_0F3807 */ |
5579 | /* PREFIX_VEX_0F3807 */ |
5203 | { |
5580 | { |
5204 | { Bad_Opcode }, |
5581 | { Bad_Opcode }, |
5205 | { Bad_Opcode }, |
5582 | { Bad_Opcode }, |
5206 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
5583 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
5207 | }, |
5584 | }, |
5208 | 5585 | ||
5209 | /* PREFIX_VEX_0F3808 */ |
5586 | /* PREFIX_VEX_0F3808 */ |
5210 | { |
5587 | { |
5211 | { Bad_Opcode }, |
5588 | { Bad_Opcode }, |
5212 | { Bad_Opcode }, |
5589 | { Bad_Opcode }, |
5213 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
5590 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
5214 | }, |
5591 | }, |
5215 | 5592 | ||
5216 | /* PREFIX_VEX_0F3809 */ |
5593 | /* PREFIX_VEX_0F3809 */ |
5217 | { |
5594 | { |
5218 | { Bad_Opcode }, |
5595 | { Bad_Opcode }, |
5219 | { Bad_Opcode }, |
5596 | { Bad_Opcode }, |
5220 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
5597 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
5221 | }, |
5598 | }, |
5222 | 5599 | ||
5223 | /* PREFIX_VEX_0F380A */ |
5600 | /* PREFIX_VEX_0F380A */ |
5224 | { |
5601 | { |
5225 | { Bad_Opcode }, |
5602 | { Bad_Opcode }, |
5226 | { Bad_Opcode }, |
5603 | { Bad_Opcode }, |
5227 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
5604 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
5228 | }, |
5605 | }, |
5229 | 5606 | ||
5230 | /* PREFIX_VEX_0F380B */ |
5607 | /* PREFIX_VEX_0F380B */ |
5231 | { |
5608 | { |
5232 | { Bad_Opcode }, |
5609 | { Bad_Opcode }, |
5233 | { Bad_Opcode }, |
5610 | { Bad_Opcode }, |
5234 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
5611 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
5235 | }, |
5612 | }, |
5236 | 5613 | ||
5237 | /* PREFIX_VEX_0F380C */ |
5614 | /* PREFIX_VEX_0F380C */ |
5238 | { |
5615 | { |
5239 | { Bad_Opcode }, |
5616 | { Bad_Opcode }, |
5240 | { Bad_Opcode }, |
5617 | { Bad_Opcode }, |
5241 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
5618 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
5242 | }, |
5619 | }, |
5243 | 5620 | ||
5244 | /* PREFIX_VEX_0F380D */ |
5621 | /* PREFIX_VEX_0F380D */ |
5245 | { |
5622 | { |
5246 | { Bad_Opcode }, |
5623 | { Bad_Opcode }, |
5247 | { Bad_Opcode }, |
5624 | { Bad_Opcode }, |
5248 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
5625 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
5249 | }, |
5626 | }, |
5250 | 5627 | ||
5251 | /* PREFIX_VEX_0F380E */ |
5628 | /* PREFIX_VEX_0F380E */ |
5252 | { |
5629 | { |
5253 | { Bad_Opcode }, |
5630 | { Bad_Opcode }, |
5254 | { Bad_Opcode }, |
5631 | { Bad_Opcode }, |
5255 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
5632 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
5256 | }, |
5633 | }, |
5257 | 5634 | ||
5258 | /* PREFIX_VEX_0F380F */ |
5635 | /* PREFIX_VEX_0F380F */ |
5259 | { |
5636 | { |
5260 | { Bad_Opcode }, |
5637 | { Bad_Opcode }, |
5261 | { Bad_Opcode }, |
5638 | { Bad_Opcode }, |
5262 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
5639 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
5263 | }, |
5640 | }, |
5264 | 5641 | ||
5265 | /* PREFIX_VEX_0F3813 */ |
5642 | /* PREFIX_VEX_0F3813 */ |
5266 | { |
5643 | { |
5267 | { Bad_Opcode }, |
5644 | { Bad_Opcode }, |
5268 | { Bad_Opcode }, |
5645 | { Bad_Opcode }, |
5269 | { "vcvtph2ps", { XM, EXxmmq } }, |
5646 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
5270 | }, |
5647 | }, |
5271 | 5648 | ||
5272 | /* PREFIX_VEX_0F3816 */ |
5649 | /* PREFIX_VEX_0F3816 */ |
5273 | { |
5650 | { |
5274 | { Bad_Opcode }, |
5651 | { Bad_Opcode }, |
5275 | { Bad_Opcode }, |
5652 | { Bad_Opcode }, |
5276 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, |
5653 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, |
5277 | }, |
5654 | }, |
5278 | 5655 | ||
5279 | /* PREFIX_VEX_0F3817 */ |
5656 | /* PREFIX_VEX_0F3817 */ |
5280 | { |
5657 | { |
5281 | { Bad_Opcode }, |
5658 | { Bad_Opcode }, |
5282 | { Bad_Opcode }, |
5659 | { Bad_Opcode }, |
5283 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
5660 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
5284 | }, |
5661 | }, |
5285 | 5662 | ||
5286 | /* PREFIX_VEX_0F3818 */ |
5663 | /* PREFIX_VEX_0F3818 */ |
5287 | { |
5664 | { |
5288 | { Bad_Opcode }, |
5665 | { Bad_Opcode }, |
5289 | { Bad_Opcode }, |
5666 | { Bad_Opcode }, |
5290 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
5667 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
5291 | }, |
5668 | }, |
5292 | 5669 | ||
5293 | /* PREFIX_VEX_0F3819 */ |
5670 | /* PREFIX_VEX_0F3819 */ |
5294 | { |
5671 | { |
5295 | { Bad_Opcode }, |
5672 | { Bad_Opcode }, |
5296 | { Bad_Opcode }, |
5673 | { Bad_Opcode }, |
5297 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
5674 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
5298 | }, |
5675 | }, |
5299 | 5676 | ||
5300 | /* PREFIX_VEX_0F381A */ |
5677 | /* PREFIX_VEX_0F381A */ |
5301 | { |
5678 | { |
5302 | { Bad_Opcode }, |
5679 | { Bad_Opcode }, |
5303 | { Bad_Opcode }, |
5680 | { Bad_Opcode }, |
5304 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
5681 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
5305 | }, |
5682 | }, |
5306 | 5683 | ||
5307 | /* PREFIX_VEX_0F381C */ |
5684 | /* PREFIX_VEX_0F381C */ |
5308 | { |
5685 | { |
5309 | { Bad_Opcode }, |
5686 | { Bad_Opcode }, |
5310 | { Bad_Opcode }, |
5687 | { Bad_Opcode }, |
5311 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
5688 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
5312 | }, |
5689 | }, |
5313 | 5690 | ||
5314 | /* PREFIX_VEX_0F381D */ |
5691 | /* PREFIX_VEX_0F381D */ |
5315 | { |
5692 | { |
5316 | { Bad_Opcode }, |
5693 | { Bad_Opcode }, |
5317 | { Bad_Opcode }, |
5694 | { Bad_Opcode }, |
5318 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
5695 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
5319 | }, |
5696 | }, |
5320 | 5697 | ||
5321 | /* PREFIX_VEX_0F381E */ |
5698 | /* PREFIX_VEX_0F381E */ |
5322 | { |
5699 | { |
5323 | { Bad_Opcode }, |
5700 | { Bad_Opcode }, |
5324 | { Bad_Opcode }, |
5701 | { Bad_Opcode }, |
5325 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
5702 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
5326 | }, |
5703 | }, |
5327 | 5704 | ||
5328 | /* PREFIX_VEX_0F3820 */ |
5705 | /* PREFIX_VEX_0F3820 */ |
5329 | { |
5706 | { |
5330 | { Bad_Opcode }, |
5707 | { Bad_Opcode }, |
5331 | { Bad_Opcode }, |
5708 | { Bad_Opcode }, |
5332 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
5709 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
5333 | }, |
5710 | }, |
5334 | 5711 | ||
5335 | /* PREFIX_VEX_0F3821 */ |
5712 | /* PREFIX_VEX_0F3821 */ |
5336 | { |
5713 | { |
5337 | { Bad_Opcode }, |
5714 | { Bad_Opcode }, |
5338 | { Bad_Opcode }, |
5715 | { Bad_Opcode }, |
5339 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
5716 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
5340 | }, |
5717 | }, |
5341 | 5718 | ||
5342 | /* PREFIX_VEX_0F3822 */ |
5719 | /* PREFIX_VEX_0F3822 */ |
5343 | { |
5720 | { |
5344 | { Bad_Opcode }, |
5721 | { Bad_Opcode }, |
5345 | { Bad_Opcode }, |
5722 | { Bad_Opcode }, |
5346 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
5723 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
5347 | }, |
5724 | }, |
5348 | 5725 | ||
5349 | /* PREFIX_VEX_0F3823 */ |
5726 | /* PREFIX_VEX_0F3823 */ |
5350 | { |
5727 | { |
5351 | { Bad_Opcode }, |
5728 | { Bad_Opcode }, |
5352 | { Bad_Opcode }, |
5729 | { Bad_Opcode }, |
5353 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
5730 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
5354 | }, |
5731 | }, |
5355 | 5732 | ||
5356 | /* PREFIX_VEX_0F3824 */ |
5733 | /* PREFIX_VEX_0F3824 */ |
5357 | { |
5734 | { |
5358 | { Bad_Opcode }, |
5735 | { Bad_Opcode }, |
5359 | { Bad_Opcode }, |
5736 | { Bad_Opcode }, |
5360 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
5737 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
5361 | }, |
5738 | }, |
5362 | 5739 | ||
5363 | /* PREFIX_VEX_0F3825 */ |
5740 | /* PREFIX_VEX_0F3825 */ |
5364 | { |
5741 | { |
5365 | { Bad_Opcode }, |
5742 | { Bad_Opcode }, |
5366 | { Bad_Opcode }, |
5743 | { Bad_Opcode }, |
5367 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
5744 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
5368 | }, |
5745 | }, |
5369 | 5746 | ||
5370 | /* PREFIX_VEX_0F3828 */ |
5747 | /* PREFIX_VEX_0F3828 */ |
5371 | { |
5748 | { |
5372 | { Bad_Opcode }, |
5749 | { Bad_Opcode }, |
5373 | { Bad_Opcode }, |
5750 | { Bad_Opcode }, |
5374 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
5751 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
5375 | }, |
5752 | }, |
5376 | 5753 | ||
5377 | /* PREFIX_VEX_0F3829 */ |
5754 | /* PREFIX_VEX_0F3829 */ |
5378 | { |
5755 | { |
5379 | { Bad_Opcode }, |
5756 | { Bad_Opcode }, |
5380 | { Bad_Opcode }, |
5757 | { Bad_Opcode }, |
5381 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
5758 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
5382 | }, |
5759 | }, |
5383 | 5760 | ||
5384 | /* PREFIX_VEX_0F382A */ |
5761 | /* PREFIX_VEX_0F382A */ |
5385 | { |
5762 | { |
5386 | { Bad_Opcode }, |
5763 | { Bad_Opcode }, |
5387 | { Bad_Opcode }, |
5764 | { Bad_Opcode }, |
5388 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
5765 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
5389 | }, |
5766 | }, |
5390 | 5767 | ||
5391 | /* PREFIX_VEX_0F382B */ |
5768 | /* PREFIX_VEX_0F382B */ |
5392 | { |
5769 | { |
5393 | { Bad_Opcode }, |
5770 | { Bad_Opcode }, |
5394 | { Bad_Opcode }, |
5771 | { Bad_Opcode }, |
5395 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
5772 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
5396 | }, |
5773 | }, |
5397 | 5774 | ||
5398 | /* PREFIX_VEX_0F382C */ |
5775 | /* PREFIX_VEX_0F382C */ |
5399 | { |
5776 | { |
5400 | { Bad_Opcode }, |
5777 | { Bad_Opcode }, |
5401 | { Bad_Opcode }, |
5778 | { Bad_Opcode }, |
5402 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
5779 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
5403 | }, |
5780 | }, |
5404 | 5781 | ||
5405 | /* PREFIX_VEX_0F382D */ |
5782 | /* PREFIX_VEX_0F382D */ |
5406 | { |
5783 | { |
5407 | { Bad_Opcode }, |
5784 | { Bad_Opcode }, |
5408 | { Bad_Opcode }, |
5785 | { Bad_Opcode }, |
5409 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
5786 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
5410 | }, |
5787 | }, |
5411 | 5788 | ||
5412 | /* PREFIX_VEX_0F382E */ |
5789 | /* PREFIX_VEX_0F382E */ |
5413 | { |
5790 | { |
5414 | { Bad_Opcode }, |
5791 | { Bad_Opcode }, |
5415 | { Bad_Opcode }, |
5792 | { Bad_Opcode }, |
5416 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
5793 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
5417 | }, |
5794 | }, |
5418 | 5795 | ||
5419 | /* PREFIX_VEX_0F382F */ |
5796 | /* PREFIX_VEX_0F382F */ |
5420 | { |
5797 | { |
5421 | { Bad_Opcode }, |
5798 | { Bad_Opcode }, |
5422 | { Bad_Opcode }, |
5799 | { Bad_Opcode }, |
5423 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
5800 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
5424 | }, |
5801 | }, |
5425 | 5802 | ||
5426 | /* PREFIX_VEX_0F3830 */ |
5803 | /* PREFIX_VEX_0F3830 */ |
5427 | { |
5804 | { |
5428 | { Bad_Opcode }, |
5805 | { Bad_Opcode }, |
5429 | { Bad_Opcode }, |
5806 | { Bad_Opcode }, |
5430 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
5807 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
5431 | }, |
5808 | }, |
5432 | 5809 | ||
5433 | /* PREFIX_VEX_0F3831 */ |
5810 | /* PREFIX_VEX_0F3831 */ |
5434 | { |
5811 | { |
5435 | { Bad_Opcode }, |
5812 | { Bad_Opcode }, |
5436 | { Bad_Opcode }, |
5813 | { Bad_Opcode }, |
5437 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
5814 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
5438 | }, |
5815 | }, |
5439 | 5816 | ||
5440 | /* PREFIX_VEX_0F3832 */ |
5817 | /* PREFIX_VEX_0F3832 */ |
5441 | { |
5818 | { |
5442 | { Bad_Opcode }, |
5819 | { Bad_Opcode }, |
5443 | { Bad_Opcode }, |
5820 | { Bad_Opcode }, |
5444 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
5821 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
5445 | }, |
5822 | }, |
5446 | 5823 | ||
5447 | /* PREFIX_VEX_0F3833 */ |
5824 | /* PREFIX_VEX_0F3833 */ |
5448 | { |
5825 | { |
5449 | { Bad_Opcode }, |
5826 | { Bad_Opcode }, |
5450 | { Bad_Opcode }, |
5827 | { Bad_Opcode }, |
5451 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
5828 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
5452 | }, |
5829 | }, |
5453 | 5830 | ||
5454 | /* PREFIX_VEX_0F3834 */ |
5831 | /* PREFIX_VEX_0F3834 */ |
5455 | { |
5832 | { |
5456 | { Bad_Opcode }, |
5833 | { Bad_Opcode }, |
5457 | { Bad_Opcode }, |
5834 | { Bad_Opcode }, |
5458 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
5835 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
5459 | }, |
5836 | }, |
5460 | 5837 | ||
5461 | /* PREFIX_VEX_0F3835 */ |
5838 | /* PREFIX_VEX_0F3835 */ |
5462 | { |
5839 | { |
5463 | { Bad_Opcode }, |
5840 | { Bad_Opcode }, |
5464 | { Bad_Opcode }, |
5841 | { Bad_Opcode }, |
5465 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
5842 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
5466 | }, |
5843 | }, |
5467 | 5844 | ||
5468 | /* PREFIX_VEX_0F3836 */ |
5845 | /* PREFIX_VEX_0F3836 */ |
5469 | { |
5846 | { |
5470 | { Bad_Opcode }, |
5847 | { Bad_Opcode }, |
5471 | { Bad_Opcode }, |
5848 | { Bad_Opcode }, |
5472 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, |
5849 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, |
5473 | }, |
5850 | }, |
5474 | 5851 | ||
5475 | /* PREFIX_VEX_0F3837 */ |
5852 | /* PREFIX_VEX_0F3837 */ |
5476 | { |
5853 | { |
5477 | { Bad_Opcode }, |
5854 | { Bad_Opcode }, |
5478 | { Bad_Opcode }, |
5855 | { Bad_Opcode }, |
5479 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
5856 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
5480 | }, |
5857 | }, |
5481 | 5858 | ||
5482 | /* PREFIX_VEX_0F3838 */ |
5859 | /* PREFIX_VEX_0F3838 */ |
5483 | { |
5860 | { |
5484 | { Bad_Opcode }, |
5861 | { Bad_Opcode }, |
5485 | { Bad_Opcode }, |
5862 | { Bad_Opcode }, |
5486 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
5863 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
5487 | }, |
5864 | }, |
5488 | 5865 | ||
5489 | /* PREFIX_VEX_0F3839 */ |
5866 | /* PREFIX_VEX_0F3839 */ |
5490 | { |
5867 | { |
5491 | { Bad_Opcode }, |
5868 | { Bad_Opcode }, |
5492 | { Bad_Opcode }, |
5869 | { Bad_Opcode }, |
5493 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
5870 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
5494 | }, |
5871 | }, |
5495 | 5872 | ||
5496 | /* PREFIX_VEX_0F383A */ |
5873 | /* PREFIX_VEX_0F383A */ |
5497 | { |
5874 | { |
5498 | { Bad_Opcode }, |
5875 | { Bad_Opcode }, |
5499 | { Bad_Opcode }, |
5876 | { Bad_Opcode }, |
5500 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
5877 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
5501 | }, |
5878 | }, |
5502 | 5879 | ||
5503 | /* PREFIX_VEX_0F383B */ |
5880 | /* PREFIX_VEX_0F383B */ |
5504 | { |
5881 | { |
5505 | { Bad_Opcode }, |
5882 | { Bad_Opcode }, |
5506 | { Bad_Opcode }, |
5883 | { Bad_Opcode }, |
5507 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
5884 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
5508 | }, |
5885 | }, |
5509 | 5886 | ||
5510 | /* PREFIX_VEX_0F383C */ |
5887 | /* PREFIX_VEX_0F383C */ |
5511 | { |
5888 | { |
5512 | { Bad_Opcode }, |
5889 | { Bad_Opcode }, |
5513 | { Bad_Opcode }, |
5890 | { Bad_Opcode }, |
5514 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
5891 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
5515 | }, |
5892 | }, |
5516 | 5893 | ||
5517 | /* PREFIX_VEX_0F383D */ |
5894 | /* PREFIX_VEX_0F383D */ |
5518 | { |
5895 | { |
5519 | { Bad_Opcode }, |
5896 | { Bad_Opcode }, |
5520 | { Bad_Opcode }, |
5897 | { Bad_Opcode }, |
5521 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
5898 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
5522 | }, |
5899 | }, |
5523 | 5900 | ||
5524 | /* PREFIX_VEX_0F383E */ |
5901 | /* PREFIX_VEX_0F383E */ |
5525 | { |
5902 | { |
5526 | { Bad_Opcode }, |
5903 | { Bad_Opcode }, |
5527 | { Bad_Opcode }, |
5904 | { Bad_Opcode }, |
5528 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
5905 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
5529 | }, |
5906 | }, |
5530 | 5907 | ||
5531 | /* PREFIX_VEX_0F383F */ |
5908 | /* PREFIX_VEX_0F383F */ |
5532 | { |
5909 | { |
5533 | { Bad_Opcode }, |
5910 | { Bad_Opcode }, |
5534 | { Bad_Opcode }, |
5911 | { Bad_Opcode }, |
5535 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
5912 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
5536 | }, |
5913 | }, |
5537 | 5914 | ||
5538 | /* PREFIX_VEX_0F3840 */ |
5915 | /* PREFIX_VEX_0F3840 */ |
5539 | { |
5916 | { |
5540 | { Bad_Opcode }, |
5917 | { Bad_Opcode }, |
5541 | { Bad_Opcode }, |
5918 | { Bad_Opcode }, |
5542 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
5919 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
5543 | }, |
5920 | }, |
5544 | 5921 | ||
5545 | /* PREFIX_VEX_0F3841 */ |
5922 | /* PREFIX_VEX_0F3841 */ |
5546 | { |
5923 | { |
5547 | { Bad_Opcode }, |
5924 | { Bad_Opcode }, |
5548 | { Bad_Opcode }, |
5925 | { Bad_Opcode }, |
5549 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
5926 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
5550 | }, |
5927 | }, |
5551 | 5928 | ||
5552 | /* PREFIX_VEX_0F3845 */ |
5929 | /* PREFIX_VEX_0F3845 */ |
5553 | { |
5930 | { |
5554 | { Bad_Opcode }, |
5931 | { Bad_Opcode }, |
5555 | { Bad_Opcode }, |
5932 | { Bad_Opcode }, |
5556 | { "vpsrlv%LW", { XM, Vex, EXx } }, |
5933 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
5557 | }, |
5934 | }, |
5558 | 5935 | ||
5559 | /* PREFIX_VEX_0F3846 */ |
5936 | /* PREFIX_VEX_0F3846 */ |
5560 | { |
5937 | { |
5561 | { Bad_Opcode }, |
5938 | { Bad_Opcode }, |
5562 | { Bad_Opcode }, |
5939 | { Bad_Opcode }, |
5563 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, |
5940 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, |
5564 | }, |
5941 | }, |
5565 | 5942 | ||
5566 | /* PREFIX_VEX_0F3847 */ |
5943 | /* PREFIX_VEX_0F3847 */ |
5567 | { |
5944 | { |
5568 | { Bad_Opcode }, |
5945 | { Bad_Opcode }, |
5569 | { Bad_Opcode }, |
5946 | { Bad_Opcode }, |
5570 | { "vpsllv%LW", { XM, Vex, EXx } }, |
5947 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
5571 | }, |
5948 | }, |
5572 | 5949 | ||
5573 | /* PREFIX_VEX_0F3858 */ |
5950 | /* PREFIX_VEX_0F3858 */ |
5574 | { |
5951 | { |
5575 | { Bad_Opcode }, |
5952 | { Bad_Opcode }, |
5576 | { Bad_Opcode }, |
5953 | { Bad_Opcode }, |
5577 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, |
5954 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, |
5578 | }, |
5955 | }, |
5579 | 5956 | ||
5580 | /* PREFIX_VEX_0F3859 */ |
5957 | /* PREFIX_VEX_0F3859 */ |
5581 | { |
5958 | { |
5582 | { Bad_Opcode }, |
5959 | { Bad_Opcode }, |
5583 | { Bad_Opcode }, |
5960 | { Bad_Opcode }, |
5584 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, |
5961 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, |
5585 | }, |
5962 | }, |
5586 | 5963 | ||
5587 | /* PREFIX_VEX_0F385A */ |
5964 | /* PREFIX_VEX_0F385A */ |
5588 | { |
5965 | { |
5589 | { Bad_Opcode }, |
5966 | { Bad_Opcode }, |
5590 | { Bad_Opcode }, |
5967 | { Bad_Opcode }, |
5591 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, |
5968 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, |
5592 | }, |
5969 | }, |
5593 | 5970 | ||
5594 | /* PREFIX_VEX_0F3878 */ |
5971 | /* PREFIX_VEX_0F3878 */ |
5595 | { |
5972 | { |
5596 | { Bad_Opcode }, |
5973 | { Bad_Opcode }, |
5597 | { Bad_Opcode }, |
5974 | { Bad_Opcode }, |
5598 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, |
5975 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, |
5599 | }, |
5976 | }, |
5600 | 5977 | ||
5601 | /* PREFIX_VEX_0F3879 */ |
5978 | /* PREFIX_VEX_0F3879 */ |
5602 | { |
5979 | { |
5603 | { Bad_Opcode }, |
5980 | { Bad_Opcode }, |
5604 | { Bad_Opcode }, |
5981 | { Bad_Opcode }, |
5605 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, |
5982 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, |
5606 | }, |
5983 | }, |
5607 | 5984 | ||
5608 | /* PREFIX_VEX_0F388C */ |
5985 | /* PREFIX_VEX_0F388C */ |
5609 | { |
5986 | { |
5610 | { Bad_Opcode }, |
5987 | { Bad_Opcode }, |
5611 | { Bad_Opcode }, |
5988 | { Bad_Opcode }, |
5612 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
5989 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
5613 | }, |
5990 | }, |
5614 | 5991 | ||
5615 | /* PREFIX_VEX_0F388E */ |
5992 | /* PREFIX_VEX_0F388E */ |
5616 | { |
5993 | { |
5617 | { Bad_Opcode }, |
5994 | { Bad_Opcode }, |
5618 | { Bad_Opcode }, |
5995 | { Bad_Opcode }, |
5619 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
5996 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
5620 | }, |
5997 | }, |
5621 | 5998 | ||
5622 | /* PREFIX_VEX_0F3890 */ |
5999 | /* PREFIX_VEX_0F3890 */ |
5623 | { |
6000 | { |
5624 | { Bad_Opcode }, |
6001 | { Bad_Opcode }, |
5625 | { Bad_Opcode }, |
6002 | { Bad_Opcode }, |
5626 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } }, |
6003 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
5627 | }, |
6004 | }, |
5628 | 6005 | ||
5629 | /* PREFIX_VEX_0F3891 */ |
6006 | /* PREFIX_VEX_0F3891 */ |
5630 | { |
6007 | { |
5631 | { Bad_Opcode }, |
6008 | { Bad_Opcode }, |
5632 | { Bad_Opcode }, |
6009 | { Bad_Opcode }, |
5633 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, |
6010 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
5634 | }, |
6011 | }, |
5635 | 6012 | ||
5636 | /* PREFIX_VEX_0F3892 */ |
6013 | /* PREFIX_VEX_0F3892 */ |
5637 | { |
6014 | { |
5638 | { Bad_Opcode }, |
6015 | { Bad_Opcode }, |
5639 | { Bad_Opcode }, |
6016 | { Bad_Opcode }, |
5640 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } }, |
6017 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
5641 | }, |
6018 | }, |
5642 | 6019 | ||
5643 | /* PREFIX_VEX_0F3893 */ |
6020 | /* PREFIX_VEX_0F3893 */ |
5644 | { |
6021 | { |
5645 | { Bad_Opcode }, |
6022 | { Bad_Opcode }, |
5646 | { Bad_Opcode }, |
6023 | { Bad_Opcode }, |
5647 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, |
6024 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
5648 | }, |
6025 | }, |
5649 | 6026 | ||
5650 | /* PREFIX_VEX_0F3896 */ |
6027 | /* PREFIX_VEX_0F3896 */ |
5651 | { |
6028 | { |
5652 | { Bad_Opcode }, |
6029 | { Bad_Opcode }, |
5653 | { Bad_Opcode }, |
6030 | { Bad_Opcode }, |
5654 | { "vfmaddsub132p%XW", { XM, Vex, EXx } }, |
6031 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
5655 | }, |
6032 | }, |
5656 | 6033 | ||
5657 | /* PREFIX_VEX_0F3897 */ |
6034 | /* PREFIX_VEX_0F3897 */ |
5658 | { |
6035 | { |
5659 | { Bad_Opcode }, |
6036 | { Bad_Opcode }, |
5660 | { Bad_Opcode }, |
6037 | { Bad_Opcode }, |
5661 | { "vfmsubadd132p%XW", { XM, Vex, EXx } }, |
6038 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
5662 | }, |
6039 | }, |
5663 | 6040 | ||
5664 | /* PREFIX_VEX_0F3898 */ |
6041 | /* PREFIX_VEX_0F3898 */ |
5665 | { |
6042 | { |
5666 | { Bad_Opcode }, |
6043 | { Bad_Opcode }, |
5667 | { Bad_Opcode }, |
6044 | { Bad_Opcode }, |
5668 | { "vfmadd132p%XW", { XM, Vex, EXx } }, |
6045 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
5669 | }, |
6046 | }, |
5670 | 6047 | ||
5671 | /* PREFIX_VEX_0F3899 */ |
6048 | /* PREFIX_VEX_0F3899 */ |
5672 | { |
6049 | { |
5673 | { Bad_Opcode }, |
6050 | { Bad_Opcode }, |
5674 | { Bad_Opcode }, |
6051 | { Bad_Opcode }, |
5675 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6052 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5676 | }, |
6053 | }, |
5677 | 6054 | ||
5678 | /* PREFIX_VEX_0F389A */ |
6055 | /* PREFIX_VEX_0F389A */ |
5679 | { |
6056 | { |
5680 | { Bad_Opcode }, |
6057 | { Bad_Opcode }, |
5681 | { Bad_Opcode }, |
6058 | { Bad_Opcode }, |
5682 | { "vfmsub132p%XW", { XM, Vex, EXx } }, |
6059 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
5683 | }, |
6060 | }, |
5684 | 6061 | ||
5685 | /* PREFIX_VEX_0F389B */ |
6062 | /* PREFIX_VEX_0F389B */ |
5686 | { |
6063 | { |
5687 | { Bad_Opcode }, |
6064 | { Bad_Opcode }, |
5688 | { Bad_Opcode }, |
6065 | { Bad_Opcode }, |
5689 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6066 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5690 | }, |
6067 | }, |
5691 | 6068 | ||
5692 | /* PREFIX_VEX_0F389C */ |
6069 | /* PREFIX_VEX_0F389C */ |
5693 | { |
6070 | { |
5694 | { Bad_Opcode }, |
6071 | { Bad_Opcode }, |
5695 | { Bad_Opcode }, |
6072 | { Bad_Opcode }, |
5696 | { "vfnmadd132p%XW", { XM, Vex, EXx } }, |
6073 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
5697 | }, |
6074 | }, |
5698 | 6075 | ||
5699 | /* PREFIX_VEX_0F389D */ |
6076 | /* PREFIX_VEX_0F389D */ |
5700 | { |
6077 | { |
5701 | { Bad_Opcode }, |
6078 | { Bad_Opcode }, |
5702 | { Bad_Opcode }, |
6079 | { Bad_Opcode }, |
5703 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6080 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5704 | }, |
6081 | }, |
5705 | 6082 | ||
5706 | /* PREFIX_VEX_0F389E */ |
6083 | /* PREFIX_VEX_0F389E */ |
5707 | { |
6084 | { |
5708 | { Bad_Opcode }, |
6085 | { Bad_Opcode }, |
5709 | { Bad_Opcode }, |
6086 | { Bad_Opcode }, |
5710 | { "vfnmsub132p%XW", { XM, Vex, EXx } }, |
6087 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
5711 | }, |
6088 | }, |
5712 | 6089 | ||
5713 | /* PREFIX_VEX_0F389F */ |
6090 | /* PREFIX_VEX_0F389F */ |
5714 | { |
6091 | { |
5715 | { Bad_Opcode }, |
6092 | { Bad_Opcode }, |
5716 | { Bad_Opcode }, |
6093 | { Bad_Opcode }, |
5717 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6094 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5718 | }, |
6095 | }, |
5719 | 6096 | ||
5720 | /* PREFIX_VEX_0F38A6 */ |
6097 | /* PREFIX_VEX_0F38A6 */ |
5721 | { |
6098 | { |
5722 | { Bad_Opcode }, |
6099 | { Bad_Opcode }, |
5723 | { Bad_Opcode }, |
6100 | { Bad_Opcode }, |
5724 | { "vfmaddsub213p%XW", { XM, Vex, EXx } }, |
6101 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
5725 | { Bad_Opcode }, |
6102 | { Bad_Opcode }, |
5726 | }, |
6103 | }, |
5727 | 6104 | ||
5728 | /* PREFIX_VEX_0F38A7 */ |
6105 | /* PREFIX_VEX_0F38A7 */ |
5729 | { |
6106 | { |
5730 | { Bad_Opcode }, |
6107 | { Bad_Opcode }, |
5731 | { Bad_Opcode }, |
6108 | { Bad_Opcode }, |
5732 | { "vfmsubadd213p%XW", { XM, Vex, EXx } }, |
6109 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
5733 | }, |
6110 | }, |
5734 | 6111 | ||
5735 | /* PREFIX_VEX_0F38A8 */ |
6112 | /* PREFIX_VEX_0F38A8 */ |
5736 | { |
6113 | { |
5737 | { Bad_Opcode }, |
6114 | { Bad_Opcode }, |
5738 | { Bad_Opcode }, |
6115 | { Bad_Opcode }, |
5739 | { "vfmadd213p%XW", { XM, Vex, EXx } }, |
6116 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
5740 | }, |
6117 | }, |
5741 | 6118 | ||
5742 | /* PREFIX_VEX_0F38A9 */ |
6119 | /* PREFIX_VEX_0F38A9 */ |
5743 | { |
6120 | { |
5744 | { Bad_Opcode }, |
6121 | { Bad_Opcode }, |
5745 | { Bad_Opcode }, |
6122 | { Bad_Opcode }, |
5746 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6123 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5747 | }, |
6124 | }, |
5748 | 6125 | ||
5749 | /* PREFIX_VEX_0F38AA */ |
6126 | /* PREFIX_VEX_0F38AA */ |
5750 | { |
6127 | { |
5751 | { Bad_Opcode }, |
6128 | { Bad_Opcode }, |
5752 | { Bad_Opcode }, |
6129 | { Bad_Opcode }, |
5753 | { "vfmsub213p%XW", { XM, Vex, EXx } }, |
6130 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
5754 | }, |
6131 | }, |
5755 | 6132 | ||
5756 | /* PREFIX_VEX_0F38AB */ |
6133 | /* PREFIX_VEX_0F38AB */ |
5757 | { |
6134 | { |
5758 | { Bad_Opcode }, |
6135 | { Bad_Opcode }, |
5759 | { Bad_Opcode }, |
6136 | { Bad_Opcode }, |
5760 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6137 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5761 | }, |
6138 | }, |
5762 | 6139 | ||
5763 | /* PREFIX_VEX_0F38AC */ |
6140 | /* PREFIX_VEX_0F38AC */ |
5764 | { |
6141 | { |
5765 | { Bad_Opcode }, |
6142 | { Bad_Opcode }, |
5766 | { Bad_Opcode }, |
6143 | { Bad_Opcode }, |
5767 | { "vfnmadd213p%XW", { XM, Vex, EXx } }, |
6144 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
5768 | }, |
6145 | }, |
5769 | 6146 | ||
5770 | /* PREFIX_VEX_0F38AD */ |
6147 | /* PREFIX_VEX_0F38AD */ |
5771 | { |
6148 | { |
5772 | { Bad_Opcode }, |
6149 | { Bad_Opcode }, |
5773 | { Bad_Opcode }, |
6150 | { Bad_Opcode }, |
5774 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6151 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5775 | }, |
6152 | }, |
5776 | 6153 | ||
5777 | /* PREFIX_VEX_0F38AE */ |
6154 | /* PREFIX_VEX_0F38AE */ |
5778 | { |
6155 | { |
5779 | { Bad_Opcode }, |
6156 | { Bad_Opcode }, |
5780 | { Bad_Opcode }, |
6157 | { Bad_Opcode }, |
5781 | { "vfnmsub213p%XW", { XM, Vex, EXx } }, |
6158 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
5782 | }, |
6159 | }, |
5783 | 6160 | ||
5784 | /* PREFIX_VEX_0F38AF */ |
6161 | /* PREFIX_VEX_0F38AF */ |
5785 | { |
6162 | { |
5786 | { Bad_Opcode }, |
6163 | { Bad_Opcode }, |
5787 | { Bad_Opcode }, |
6164 | { Bad_Opcode }, |
5788 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6165 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5789 | }, |
6166 | }, |
5790 | 6167 | ||
5791 | /* PREFIX_VEX_0F38B6 */ |
6168 | /* PREFIX_VEX_0F38B6 */ |
5792 | { |
6169 | { |
5793 | { Bad_Opcode }, |
6170 | { Bad_Opcode }, |
5794 | { Bad_Opcode }, |
6171 | { Bad_Opcode }, |
5795 | { "vfmaddsub231p%XW", { XM, Vex, EXx } }, |
6172 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
5796 | }, |
6173 | }, |
5797 | 6174 | ||
5798 | /* PREFIX_VEX_0F38B7 */ |
6175 | /* PREFIX_VEX_0F38B7 */ |
5799 | { |
6176 | { |
5800 | { Bad_Opcode }, |
6177 | { Bad_Opcode }, |
5801 | { Bad_Opcode }, |
6178 | { Bad_Opcode }, |
5802 | { "vfmsubadd231p%XW", { XM, Vex, EXx } }, |
6179 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
5803 | }, |
6180 | }, |
5804 | 6181 | ||
5805 | /* PREFIX_VEX_0F38B8 */ |
6182 | /* PREFIX_VEX_0F38B8 */ |
5806 | { |
6183 | { |
5807 | { Bad_Opcode }, |
6184 | { Bad_Opcode }, |
5808 | { Bad_Opcode }, |
6185 | { Bad_Opcode }, |
5809 | { "vfmadd231p%XW", { XM, Vex, EXx } }, |
6186 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
5810 | }, |
6187 | }, |
5811 | 6188 | ||
5812 | /* PREFIX_VEX_0F38B9 */ |
6189 | /* PREFIX_VEX_0F38B9 */ |
5813 | { |
6190 | { |
5814 | { Bad_Opcode }, |
6191 | { Bad_Opcode }, |
5815 | { Bad_Opcode }, |
6192 | { Bad_Opcode }, |
5816 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6193 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5817 | }, |
6194 | }, |
5818 | 6195 | ||
5819 | /* PREFIX_VEX_0F38BA */ |
6196 | /* PREFIX_VEX_0F38BA */ |
5820 | { |
6197 | { |
5821 | { Bad_Opcode }, |
6198 | { Bad_Opcode }, |
5822 | { Bad_Opcode }, |
6199 | { Bad_Opcode }, |
5823 | { "vfmsub231p%XW", { XM, Vex, EXx } }, |
6200 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
5824 | }, |
6201 | }, |
5825 | 6202 | ||
5826 | /* PREFIX_VEX_0F38BB */ |
6203 | /* PREFIX_VEX_0F38BB */ |
5827 | { |
6204 | { |
5828 | { Bad_Opcode }, |
6205 | { Bad_Opcode }, |
5829 | { Bad_Opcode }, |
6206 | { Bad_Opcode }, |
5830 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6207 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5831 | }, |
6208 | }, |
5832 | 6209 | ||
5833 | /* PREFIX_VEX_0F38BC */ |
6210 | /* PREFIX_VEX_0F38BC */ |
5834 | { |
6211 | { |
5835 | { Bad_Opcode }, |
6212 | { Bad_Opcode }, |
5836 | { Bad_Opcode }, |
6213 | { Bad_Opcode }, |
5837 | { "vfnmadd231p%XW", { XM, Vex, EXx } }, |
6214 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
5838 | }, |
6215 | }, |
5839 | 6216 | ||
5840 | /* PREFIX_VEX_0F38BD */ |
6217 | /* PREFIX_VEX_0F38BD */ |
5841 | { |
6218 | { |
5842 | { Bad_Opcode }, |
6219 | { Bad_Opcode }, |
5843 | { Bad_Opcode }, |
6220 | { Bad_Opcode }, |
5844 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6221 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5845 | }, |
6222 | }, |
5846 | 6223 | ||
5847 | /* PREFIX_VEX_0F38BE */ |
6224 | /* PREFIX_VEX_0F38BE */ |
5848 | { |
6225 | { |
5849 | { Bad_Opcode }, |
6226 | { Bad_Opcode }, |
5850 | { Bad_Opcode }, |
6227 | { Bad_Opcode }, |
5851 | { "vfnmsub231p%XW", { XM, Vex, EXx } }, |
6228 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
5852 | }, |
6229 | }, |
5853 | 6230 | ||
5854 | /* PREFIX_VEX_0F38BF */ |
6231 | /* PREFIX_VEX_0F38BF */ |
5855 | { |
6232 | { |
5856 | { Bad_Opcode }, |
6233 | { Bad_Opcode }, |
5857 | { Bad_Opcode }, |
6234 | { Bad_Opcode }, |
5858 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6235 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5859 | }, |
6236 | }, |
5860 | 6237 | ||
5861 | /* PREFIX_VEX_0F38DB */ |
6238 | /* PREFIX_VEX_0F38DB */ |
5862 | { |
6239 | { |
5863 | { Bad_Opcode }, |
6240 | { Bad_Opcode }, |
5864 | { Bad_Opcode }, |
6241 | { Bad_Opcode }, |
5865 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
6242 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
5866 | }, |
6243 | }, |
5867 | 6244 | ||
5868 | /* PREFIX_VEX_0F38DC */ |
6245 | /* PREFIX_VEX_0F38DC */ |
5869 | { |
6246 | { |
5870 | { Bad_Opcode }, |
6247 | { Bad_Opcode }, |
5871 | { Bad_Opcode }, |
6248 | { Bad_Opcode }, |
5872 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
6249 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
5873 | }, |
6250 | }, |
5874 | 6251 | ||
5875 | /* PREFIX_VEX_0F38DD */ |
6252 | /* PREFIX_VEX_0F38DD */ |
5876 | { |
6253 | { |
5877 | { Bad_Opcode }, |
6254 | { Bad_Opcode }, |
5878 | { Bad_Opcode }, |
6255 | { Bad_Opcode }, |
5879 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
6256 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
5880 | }, |
6257 | }, |
5881 | 6258 | ||
5882 | /* PREFIX_VEX_0F38DE */ |
6259 | /* PREFIX_VEX_0F38DE */ |
5883 | { |
6260 | { |
5884 | { Bad_Opcode }, |
6261 | { Bad_Opcode }, |
5885 | { Bad_Opcode }, |
6262 | { Bad_Opcode }, |
5886 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
6263 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
5887 | }, |
6264 | }, |
5888 | 6265 | ||
5889 | /* PREFIX_VEX_0F38DF */ |
6266 | /* PREFIX_VEX_0F38DF */ |
5890 | { |
6267 | { |
5891 | { Bad_Opcode }, |
6268 | { Bad_Opcode }, |
5892 | { Bad_Opcode }, |
6269 | { Bad_Opcode }, |
5893 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
6270 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
5894 | }, |
6271 | }, |
5895 | 6272 | ||
5896 | /* PREFIX_VEX_0F38F2 */ |
6273 | /* PREFIX_VEX_0F38F2 */ |
5897 | { |
6274 | { |
5898 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, |
6275 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, |
5899 | }, |
6276 | }, |
5900 | 6277 | ||
5901 | /* PREFIX_VEX_0F38F3_REG_1 */ |
6278 | /* PREFIX_VEX_0F38F3_REG_1 */ |
5902 | { |
6279 | { |
5903 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, |
6280 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, |
5904 | }, |
6281 | }, |
5905 | 6282 | ||
5906 | /* PREFIX_VEX_0F38F3_REG_2 */ |
6283 | /* PREFIX_VEX_0F38F3_REG_2 */ |
5907 | { |
6284 | { |
5908 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, |
6285 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, |
5909 | }, |
6286 | }, |
5910 | 6287 | ||
5911 | /* PREFIX_VEX_0F38F3_REG_3 */ |
6288 | /* PREFIX_VEX_0F38F3_REG_3 */ |
5912 | { |
6289 | { |
5913 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, |
6290 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, |
5914 | }, |
6291 | }, |
5915 | 6292 | ||
5916 | /* PREFIX_VEX_0F38F5 */ |
6293 | /* PREFIX_VEX_0F38F5 */ |
5917 | { |
6294 | { |
5918 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, |
6295 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, |
5919 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, |
6296 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, |
5920 | { Bad_Opcode }, |
6297 | { Bad_Opcode }, |
5921 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, |
6298 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, |
5922 | }, |
6299 | }, |
5923 | 6300 | ||
5924 | /* PREFIX_VEX_0F38F6 */ |
6301 | /* PREFIX_VEX_0F38F6 */ |
5925 | { |
6302 | { |
5926 | { Bad_Opcode }, |
6303 | { Bad_Opcode }, |
5927 | { Bad_Opcode }, |
6304 | { Bad_Opcode }, |
5928 | { Bad_Opcode }, |
6305 | { Bad_Opcode }, |
5929 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, |
6306 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, |
5930 | }, |
6307 | }, |
5931 | 6308 | ||
5932 | /* PREFIX_VEX_0F38F7 */ |
6309 | /* PREFIX_VEX_0F38F7 */ |
5933 | { |
6310 | { |
5934 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, |
6311 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, |
5935 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6312 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
5936 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, |
6313 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, |
5937 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, |
6314 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, |
5938 | }, |
6315 | }, |
5939 | 6316 | ||
5940 | /* PREFIX_VEX_0F3A00 */ |
6317 | /* PREFIX_VEX_0F3A00 */ |
5941 | { |
6318 | { |
5942 | { Bad_Opcode }, |
6319 | { Bad_Opcode }, |
5943 | { Bad_Opcode }, |
6320 | { Bad_Opcode }, |
5944 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, |
6321 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, |
5945 | }, |
6322 | }, |
5946 | 6323 | ||
5947 | /* PREFIX_VEX_0F3A01 */ |
6324 | /* PREFIX_VEX_0F3A01 */ |
5948 | { |
6325 | { |
5949 | { Bad_Opcode }, |
6326 | { Bad_Opcode }, |
5950 | { Bad_Opcode }, |
6327 | { Bad_Opcode }, |
5951 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, |
6328 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, |
5952 | }, |
6329 | }, |
5953 | 6330 | ||
5954 | /* PREFIX_VEX_0F3A02 */ |
6331 | /* PREFIX_VEX_0F3A02 */ |
5955 | { |
6332 | { |
5956 | { Bad_Opcode }, |
6333 | { Bad_Opcode }, |
5957 | { Bad_Opcode }, |
6334 | { Bad_Opcode }, |
5958 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, |
6335 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, |
5959 | }, |
6336 | }, |
5960 | 6337 | ||
5961 | /* PREFIX_VEX_0F3A04 */ |
6338 | /* PREFIX_VEX_0F3A04 */ |
5962 | { |
6339 | { |
5963 | { Bad_Opcode }, |
6340 | { Bad_Opcode }, |
5964 | { Bad_Opcode }, |
6341 | { Bad_Opcode }, |
5965 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
6342 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
5966 | }, |
6343 | }, |
5967 | 6344 | ||
5968 | /* PREFIX_VEX_0F3A05 */ |
6345 | /* PREFIX_VEX_0F3A05 */ |
5969 | { |
6346 | { |
5970 | { Bad_Opcode }, |
6347 | { Bad_Opcode }, |
5971 | { Bad_Opcode }, |
6348 | { Bad_Opcode }, |
5972 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
6349 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
5973 | }, |
6350 | }, |
5974 | 6351 | ||
5975 | /* PREFIX_VEX_0F3A06 */ |
6352 | /* PREFIX_VEX_0F3A06 */ |
5976 | { |
6353 | { |
5977 | { Bad_Opcode }, |
6354 | { Bad_Opcode }, |
5978 | { Bad_Opcode }, |
6355 | { Bad_Opcode }, |
5979 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
6356 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
5980 | }, |
6357 | }, |
5981 | 6358 | ||
5982 | /* PREFIX_VEX_0F3A08 */ |
6359 | /* PREFIX_VEX_0F3A08 */ |
5983 | { |
6360 | { |
5984 | { Bad_Opcode }, |
6361 | { Bad_Opcode }, |
5985 | { Bad_Opcode }, |
6362 | { Bad_Opcode }, |
5986 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
6363 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
5987 | }, |
6364 | }, |
5988 | 6365 | ||
5989 | /* PREFIX_VEX_0F3A09 */ |
6366 | /* PREFIX_VEX_0F3A09 */ |
5990 | { |
6367 | { |
5991 | { Bad_Opcode }, |
6368 | { Bad_Opcode }, |
5992 | { Bad_Opcode }, |
6369 | { Bad_Opcode }, |
5993 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
6370 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
5994 | }, |
6371 | }, |
5995 | 6372 | ||
5996 | /* PREFIX_VEX_0F3A0A */ |
6373 | /* PREFIX_VEX_0F3A0A */ |
5997 | { |
6374 | { |
5998 | { Bad_Opcode }, |
6375 | { Bad_Opcode }, |
5999 | { Bad_Opcode }, |
6376 | { Bad_Opcode }, |
6000 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
6377 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
6001 | }, |
6378 | }, |
6002 | 6379 | ||
6003 | /* PREFIX_VEX_0F3A0B */ |
6380 | /* PREFIX_VEX_0F3A0B */ |
6004 | { |
6381 | { |
6005 | { Bad_Opcode }, |
6382 | { Bad_Opcode }, |
6006 | { Bad_Opcode }, |
6383 | { Bad_Opcode }, |
6007 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
6384 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
6008 | }, |
6385 | }, |
6009 | 6386 | ||
6010 | /* PREFIX_VEX_0F3A0C */ |
6387 | /* PREFIX_VEX_0F3A0C */ |
6011 | { |
6388 | { |
6012 | { Bad_Opcode }, |
6389 | { Bad_Opcode }, |
6013 | { Bad_Opcode }, |
6390 | { Bad_Opcode }, |
6014 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
6391 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
6015 | }, |
6392 | }, |
6016 | 6393 | ||
6017 | /* PREFIX_VEX_0F3A0D */ |
6394 | /* PREFIX_VEX_0F3A0D */ |
6018 | { |
6395 | { |
6019 | { Bad_Opcode }, |
6396 | { Bad_Opcode }, |
6020 | { Bad_Opcode }, |
6397 | { Bad_Opcode }, |
6021 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
6398 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
6022 | }, |
6399 | }, |
6023 | 6400 | ||
6024 | /* PREFIX_VEX_0F3A0E */ |
6401 | /* PREFIX_VEX_0F3A0E */ |
6025 | { |
6402 | { |
6026 | { Bad_Opcode }, |
6403 | { Bad_Opcode }, |
6027 | { Bad_Opcode }, |
6404 | { Bad_Opcode }, |
6028 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
6405 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
6029 | }, |
6406 | }, |
6030 | 6407 | ||
6031 | /* PREFIX_VEX_0F3A0F */ |
6408 | /* PREFIX_VEX_0F3A0F */ |
6032 | { |
6409 | { |
6033 | { Bad_Opcode }, |
6410 | { Bad_Opcode }, |
6034 | { Bad_Opcode }, |
6411 | { Bad_Opcode }, |
6035 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
6412 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
6036 | }, |
6413 | }, |
6037 | 6414 | ||
6038 | /* PREFIX_VEX_0F3A14 */ |
6415 | /* PREFIX_VEX_0F3A14 */ |
6039 | { |
6416 | { |
6040 | { Bad_Opcode }, |
6417 | { Bad_Opcode }, |
6041 | { Bad_Opcode }, |
6418 | { Bad_Opcode }, |
6042 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
6419 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
6043 | }, |
6420 | }, |
6044 | 6421 | ||
6045 | /* PREFIX_VEX_0F3A15 */ |
6422 | /* PREFIX_VEX_0F3A15 */ |
6046 | { |
6423 | { |
6047 | { Bad_Opcode }, |
6424 | { Bad_Opcode }, |
6048 | { Bad_Opcode }, |
6425 | { Bad_Opcode }, |
6049 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
6426 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
6050 | }, |
6427 | }, |
6051 | 6428 | ||
6052 | /* PREFIX_VEX_0F3A16 */ |
6429 | /* PREFIX_VEX_0F3A16 */ |
6053 | { |
6430 | { |
6054 | { Bad_Opcode }, |
6431 | { Bad_Opcode }, |
6055 | { Bad_Opcode }, |
6432 | { Bad_Opcode }, |
6056 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
6433 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
6057 | }, |
6434 | }, |
6058 | 6435 | ||
6059 | /* PREFIX_VEX_0F3A17 */ |
6436 | /* PREFIX_VEX_0F3A17 */ |
6060 | { |
6437 | { |
6061 | { Bad_Opcode }, |
6438 | { Bad_Opcode }, |
6062 | { Bad_Opcode }, |
6439 | { Bad_Opcode }, |
6063 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
6440 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
6064 | }, |
6441 | }, |
6065 | 6442 | ||
6066 | /* PREFIX_VEX_0F3A18 */ |
6443 | /* PREFIX_VEX_0F3A18 */ |
6067 | { |
6444 | { |
6068 | { Bad_Opcode }, |
6445 | { Bad_Opcode }, |
6069 | { Bad_Opcode }, |
6446 | { Bad_Opcode }, |
6070 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
6447 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
6071 | }, |
6448 | }, |
6072 | 6449 | ||
6073 | /* PREFIX_VEX_0F3A19 */ |
6450 | /* PREFIX_VEX_0F3A19 */ |
6074 | { |
6451 | { |
6075 | { Bad_Opcode }, |
6452 | { Bad_Opcode }, |
6076 | { Bad_Opcode }, |
6453 | { Bad_Opcode }, |
6077 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
6454 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
6078 | }, |
6455 | }, |
6079 | 6456 | ||
6080 | /* PREFIX_VEX_0F3A1D */ |
6457 | /* PREFIX_VEX_0F3A1D */ |
6081 | { |
6458 | { |
6082 | { Bad_Opcode }, |
6459 | { Bad_Opcode }, |
6083 | { Bad_Opcode }, |
6460 | { Bad_Opcode }, |
6084 | { "vcvtps2ph", { EXxmmq, XM, Ib } }, |
6461 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
6085 | }, |
6462 | }, |
6086 | 6463 | ||
6087 | /* PREFIX_VEX_0F3A20 */ |
6464 | /* PREFIX_VEX_0F3A20 */ |
6088 | { |
6465 | { |
6089 | { Bad_Opcode }, |
6466 | { Bad_Opcode }, |
6090 | { Bad_Opcode }, |
6467 | { Bad_Opcode }, |
6091 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
6468 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
6092 | }, |
6469 | }, |
6093 | 6470 | ||
6094 | /* PREFIX_VEX_0F3A21 */ |
6471 | /* PREFIX_VEX_0F3A21 */ |
6095 | { |
6472 | { |
6096 | { Bad_Opcode }, |
6473 | { Bad_Opcode }, |
6097 | { Bad_Opcode }, |
6474 | { Bad_Opcode }, |
6098 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
6475 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
6099 | }, |
6476 | }, |
6100 | 6477 | ||
6101 | /* PREFIX_VEX_0F3A22 */ |
6478 | /* PREFIX_VEX_0F3A22 */ |
6102 | { |
6479 | { |
6103 | { Bad_Opcode }, |
6480 | { Bad_Opcode }, |
6104 | { Bad_Opcode }, |
6481 | { Bad_Opcode }, |
6105 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
6482 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
6106 | }, |
6483 | }, |
6107 | 6484 | ||
6108 | /* PREFIX_VEX_0F3A30 */ |
6485 | /* PREFIX_VEX_0F3A30 */ |
6109 | { |
6486 | { |
6110 | { Bad_Opcode }, |
6487 | { Bad_Opcode }, |
6111 | { Bad_Opcode }, |
6488 | { Bad_Opcode }, |
6112 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, |
6489 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, |
6113 | }, |
6490 | }, |
- | 6491 | ||
- | 6492 | /* PREFIX_VEX_0F3A31 */ |
|
- | 6493 | { |
|
- | 6494 | { Bad_Opcode }, |
|
- | 6495 | { Bad_Opcode }, |
|
- | 6496 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, |
|
- | 6497 | }, |
|
6114 | 6498 | ||
6115 | /* PREFIX_VEX_0F3A32 */ |
6499 | /* PREFIX_VEX_0F3A32 */ |
6116 | { |
6500 | { |
6117 | { Bad_Opcode }, |
6501 | { Bad_Opcode }, |
6118 | { Bad_Opcode }, |
6502 | { Bad_Opcode }, |
6119 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, |
6503 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, |
6120 | }, |
6504 | }, |
- | 6505 | ||
- | 6506 | /* PREFIX_VEX_0F3A33 */ |
|
- | 6507 | { |
|
- | 6508 | { Bad_Opcode }, |
|
- | 6509 | { Bad_Opcode }, |
|
- | 6510 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, |
|
- | 6511 | }, |
|
6121 | 6512 | ||
6122 | /* PREFIX_VEX_0F3A38 */ |
6513 | /* PREFIX_VEX_0F3A38 */ |
6123 | { |
6514 | { |
6124 | { Bad_Opcode }, |
6515 | { Bad_Opcode }, |
6125 | { Bad_Opcode }, |
6516 | { Bad_Opcode }, |
6126 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, |
6517 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, |
6127 | }, |
6518 | }, |
6128 | 6519 | ||
6129 | /* PREFIX_VEX_0F3A39 */ |
6520 | /* PREFIX_VEX_0F3A39 */ |
6130 | { |
6521 | { |
6131 | { Bad_Opcode }, |
6522 | { Bad_Opcode }, |
6132 | { Bad_Opcode }, |
6523 | { Bad_Opcode }, |
6133 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, |
6524 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, |
6134 | }, |
6525 | }, |
6135 | 6526 | ||
6136 | /* PREFIX_VEX_0F3A40 */ |
6527 | /* PREFIX_VEX_0F3A40 */ |
6137 | { |
6528 | { |
6138 | { Bad_Opcode }, |
6529 | { Bad_Opcode }, |
6139 | { Bad_Opcode }, |
6530 | { Bad_Opcode }, |
6140 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
6531 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
6141 | }, |
6532 | }, |
6142 | 6533 | ||
6143 | /* PREFIX_VEX_0F3A41 */ |
6534 | /* PREFIX_VEX_0F3A41 */ |
6144 | { |
6535 | { |
6145 | { Bad_Opcode }, |
6536 | { Bad_Opcode }, |
6146 | { Bad_Opcode }, |
6537 | { Bad_Opcode }, |
6147 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
6538 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
6148 | }, |
6539 | }, |
6149 | 6540 | ||
6150 | /* PREFIX_VEX_0F3A42 */ |
6541 | /* PREFIX_VEX_0F3A42 */ |
6151 | { |
6542 | { |
6152 | { Bad_Opcode }, |
6543 | { Bad_Opcode }, |
6153 | { Bad_Opcode }, |
6544 | { Bad_Opcode }, |
6154 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
6545 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
6155 | }, |
6546 | }, |
6156 | 6547 | ||
6157 | /* PREFIX_VEX_0F3A44 */ |
6548 | /* PREFIX_VEX_0F3A44 */ |
6158 | { |
6549 | { |
6159 | { Bad_Opcode }, |
6550 | { Bad_Opcode }, |
6160 | { Bad_Opcode }, |
6551 | { Bad_Opcode }, |
6161 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
6552 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
6162 | }, |
6553 | }, |
6163 | 6554 | ||
6164 | /* PREFIX_VEX_0F3A46 */ |
6555 | /* PREFIX_VEX_0F3A46 */ |
6165 | { |
6556 | { |
6166 | { Bad_Opcode }, |
6557 | { Bad_Opcode }, |
6167 | { Bad_Opcode }, |
6558 | { Bad_Opcode }, |
6168 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, |
6559 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, |
6169 | }, |
6560 | }, |
6170 | 6561 | ||
6171 | /* PREFIX_VEX_0F3A48 */ |
6562 | /* PREFIX_VEX_0F3A48 */ |
6172 | { |
6563 | { |
6173 | { Bad_Opcode }, |
6564 | { Bad_Opcode }, |
6174 | { Bad_Opcode }, |
6565 | { Bad_Opcode }, |
6175 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
6566 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
6176 | }, |
6567 | }, |
6177 | 6568 | ||
6178 | /* PREFIX_VEX_0F3A49 */ |
6569 | /* PREFIX_VEX_0F3A49 */ |
6179 | { |
6570 | { |
6180 | { Bad_Opcode }, |
6571 | { Bad_Opcode }, |
6181 | { Bad_Opcode }, |
6572 | { Bad_Opcode }, |
6182 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
6573 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
6183 | }, |
6574 | }, |
6184 | 6575 | ||
6185 | /* PREFIX_VEX_0F3A4A */ |
6576 | /* PREFIX_VEX_0F3A4A */ |
6186 | { |
6577 | { |
6187 | { Bad_Opcode }, |
6578 | { Bad_Opcode }, |
6188 | { Bad_Opcode }, |
6579 | { Bad_Opcode }, |
6189 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
6580 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
6190 | }, |
6581 | }, |
6191 | 6582 | ||
6192 | /* PREFIX_VEX_0F3A4B */ |
6583 | /* PREFIX_VEX_0F3A4B */ |
6193 | { |
6584 | { |
6194 | { Bad_Opcode }, |
6585 | { Bad_Opcode }, |
6195 | { Bad_Opcode }, |
6586 | { Bad_Opcode }, |
6196 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
6587 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
6197 | }, |
6588 | }, |
6198 | 6589 | ||
6199 | /* PREFIX_VEX_0F3A4C */ |
6590 | /* PREFIX_VEX_0F3A4C */ |
6200 | { |
6591 | { |
6201 | { Bad_Opcode }, |
6592 | { Bad_Opcode }, |
6202 | { Bad_Opcode }, |
6593 | { Bad_Opcode }, |
6203 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
6594 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
6204 | }, |
6595 | }, |
6205 | 6596 | ||
6206 | /* PREFIX_VEX_0F3A5C */ |
6597 | /* PREFIX_VEX_0F3A5C */ |
6207 | { |
6598 | { |
6208 | { Bad_Opcode }, |
6599 | { Bad_Opcode }, |
6209 | { Bad_Opcode }, |
6600 | { Bad_Opcode }, |
6210 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6601 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6211 | }, |
6602 | }, |
6212 | 6603 | ||
6213 | /* PREFIX_VEX_0F3A5D */ |
6604 | /* PREFIX_VEX_0F3A5D */ |
6214 | { |
6605 | { |
6215 | { Bad_Opcode }, |
6606 | { Bad_Opcode }, |
6216 | { Bad_Opcode }, |
6607 | { Bad_Opcode }, |
6217 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6608 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6218 | }, |
6609 | }, |
6219 | 6610 | ||
6220 | /* PREFIX_VEX_0F3A5E */ |
6611 | /* PREFIX_VEX_0F3A5E */ |
6221 | { |
6612 | { |
6222 | { Bad_Opcode }, |
6613 | { Bad_Opcode }, |
6223 | { Bad_Opcode }, |
6614 | { Bad_Opcode }, |
6224 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6615 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6225 | }, |
6616 | }, |
6226 | 6617 | ||
6227 | /* PREFIX_VEX_0F3A5F */ |
6618 | /* PREFIX_VEX_0F3A5F */ |
6228 | { |
6619 | { |
6229 | { Bad_Opcode }, |
6620 | { Bad_Opcode }, |
6230 | { Bad_Opcode }, |
6621 | { Bad_Opcode }, |
6231 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6622 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6232 | }, |
6623 | }, |
6233 | 6624 | ||
6234 | /* PREFIX_VEX_0F3A60 */ |
6625 | /* PREFIX_VEX_0F3A60 */ |
6235 | { |
6626 | { |
6236 | { Bad_Opcode }, |
6627 | { Bad_Opcode }, |
6237 | { Bad_Opcode }, |
6628 | { Bad_Opcode }, |
6238 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
6629 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
6239 | { Bad_Opcode }, |
6630 | { Bad_Opcode }, |
6240 | }, |
6631 | }, |
6241 | 6632 | ||
6242 | /* PREFIX_VEX_0F3A61 */ |
6633 | /* PREFIX_VEX_0F3A61 */ |
6243 | { |
6634 | { |
6244 | { Bad_Opcode }, |
6635 | { Bad_Opcode }, |
6245 | { Bad_Opcode }, |
6636 | { Bad_Opcode }, |
6246 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
6637 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
6247 | }, |
6638 | }, |
6248 | 6639 | ||
6249 | /* PREFIX_VEX_0F3A62 */ |
6640 | /* PREFIX_VEX_0F3A62 */ |
6250 | { |
6641 | { |
6251 | { Bad_Opcode }, |
6642 | { Bad_Opcode }, |
6252 | { Bad_Opcode }, |
6643 | { Bad_Opcode }, |
6253 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
6644 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
6254 | }, |
6645 | }, |
6255 | 6646 | ||
6256 | /* PREFIX_VEX_0F3A63 */ |
6647 | /* PREFIX_VEX_0F3A63 */ |
6257 | { |
6648 | { |
6258 | { Bad_Opcode }, |
6649 | { Bad_Opcode }, |
6259 | { Bad_Opcode }, |
6650 | { Bad_Opcode }, |
6260 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
6651 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
6261 | }, |
6652 | }, |
6262 | 6653 | ||
6263 | /* PREFIX_VEX_0F3A68 */ |
6654 | /* PREFIX_VEX_0F3A68 */ |
6264 | { |
6655 | { |
6265 | { Bad_Opcode }, |
6656 | { Bad_Opcode }, |
6266 | { Bad_Opcode }, |
6657 | { Bad_Opcode }, |
6267 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6658 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6268 | }, |
6659 | }, |
6269 | 6660 | ||
6270 | /* PREFIX_VEX_0F3A69 */ |
6661 | /* PREFIX_VEX_0F3A69 */ |
6271 | { |
6662 | { |
6272 | { Bad_Opcode }, |
6663 | { Bad_Opcode }, |
6273 | { Bad_Opcode }, |
6664 | { Bad_Opcode }, |
6274 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6665 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6275 | }, |
6666 | }, |
6276 | 6667 | ||
6277 | /* PREFIX_VEX_0F3A6A */ |
6668 | /* PREFIX_VEX_0F3A6A */ |
6278 | { |
6669 | { |
6279 | { Bad_Opcode }, |
6670 | { Bad_Opcode }, |
6280 | { Bad_Opcode }, |
6671 | { Bad_Opcode }, |
6281 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
6672 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
6282 | }, |
6673 | }, |
6283 | 6674 | ||
6284 | /* PREFIX_VEX_0F3A6B */ |
6675 | /* PREFIX_VEX_0F3A6B */ |
6285 | { |
6676 | { |
6286 | { Bad_Opcode }, |
6677 | { Bad_Opcode }, |
6287 | { Bad_Opcode }, |
6678 | { Bad_Opcode }, |
6288 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
6679 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
6289 | }, |
6680 | }, |
6290 | 6681 | ||
6291 | /* PREFIX_VEX_0F3A6C */ |
6682 | /* PREFIX_VEX_0F3A6C */ |
6292 | { |
6683 | { |
6293 | { Bad_Opcode }, |
6684 | { Bad_Opcode }, |
6294 | { Bad_Opcode }, |
6685 | { Bad_Opcode }, |
6295 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6686 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6296 | }, |
6687 | }, |
6297 | 6688 | ||
6298 | /* PREFIX_VEX_0F3A6D */ |
6689 | /* PREFIX_VEX_0F3A6D */ |
6299 | { |
6690 | { |
6300 | { Bad_Opcode }, |
6691 | { Bad_Opcode }, |
6301 | { Bad_Opcode }, |
6692 | { Bad_Opcode }, |
6302 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6693 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6303 | }, |
6694 | }, |
6304 | 6695 | ||
6305 | /* PREFIX_VEX_0F3A6E */ |
6696 | /* PREFIX_VEX_0F3A6E */ |
6306 | { |
6697 | { |
6307 | { Bad_Opcode }, |
6698 | { Bad_Opcode }, |
6308 | { Bad_Opcode }, |
6699 | { Bad_Opcode }, |
6309 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
6700 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
6310 | }, |
6701 | }, |
6311 | 6702 | ||
6312 | /* PREFIX_VEX_0F3A6F */ |
6703 | /* PREFIX_VEX_0F3A6F */ |
6313 | { |
6704 | { |
6314 | { Bad_Opcode }, |
6705 | { Bad_Opcode }, |
6315 | { Bad_Opcode }, |
6706 | { Bad_Opcode }, |
6316 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
6707 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
6317 | }, |
6708 | }, |
6318 | 6709 | ||
6319 | /* PREFIX_VEX_0F3A78 */ |
6710 | /* PREFIX_VEX_0F3A78 */ |
6320 | { |
6711 | { |
6321 | { Bad_Opcode }, |
6712 | { Bad_Opcode }, |
6322 | { Bad_Opcode }, |
6713 | { Bad_Opcode }, |
6323 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6714 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6324 | }, |
6715 | }, |
6325 | 6716 | ||
6326 | /* PREFIX_VEX_0F3A79 */ |
6717 | /* PREFIX_VEX_0F3A79 */ |
6327 | { |
6718 | { |
6328 | { Bad_Opcode }, |
6719 | { Bad_Opcode }, |
6329 | { Bad_Opcode }, |
6720 | { Bad_Opcode }, |
6330 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6721 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6331 | }, |
6722 | }, |
6332 | 6723 | ||
6333 | /* PREFIX_VEX_0F3A7A */ |
6724 | /* PREFIX_VEX_0F3A7A */ |
6334 | { |
6725 | { |
6335 | { Bad_Opcode }, |
6726 | { Bad_Opcode }, |
6336 | { Bad_Opcode }, |
6727 | { Bad_Opcode }, |
6337 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
6728 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
6338 | }, |
6729 | }, |
6339 | 6730 | ||
6340 | /* PREFIX_VEX_0F3A7B */ |
6731 | /* PREFIX_VEX_0F3A7B */ |
6341 | { |
6732 | { |
6342 | { Bad_Opcode }, |
6733 | { Bad_Opcode }, |
6343 | { Bad_Opcode }, |
6734 | { Bad_Opcode }, |
6344 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
6735 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
6345 | }, |
6736 | }, |
6346 | 6737 | ||
6347 | /* PREFIX_VEX_0F3A7C */ |
6738 | /* PREFIX_VEX_0F3A7C */ |
6348 | { |
6739 | { |
6349 | { Bad_Opcode }, |
6740 | { Bad_Opcode }, |
6350 | { Bad_Opcode }, |
6741 | { Bad_Opcode }, |
6351 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6742 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6352 | { Bad_Opcode }, |
6743 | { Bad_Opcode }, |
6353 | }, |
6744 | }, |
6354 | 6745 | ||
6355 | /* PREFIX_VEX_0F3A7D */ |
6746 | /* PREFIX_VEX_0F3A7D */ |
6356 | { |
6747 | { |
6357 | { Bad_Opcode }, |
6748 | { Bad_Opcode }, |
6358 | { Bad_Opcode }, |
6749 | { Bad_Opcode }, |
6359 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6750 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6360 | }, |
6751 | }, |
6361 | 6752 | ||
6362 | /* PREFIX_VEX_0F3A7E */ |
6753 | /* PREFIX_VEX_0F3A7E */ |
6363 | { |
6754 | { |
6364 | { Bad_Opcode }, |
6755 | { Bad_Opcode }, |
6365 | { Bad_Opcode }, |
6756 | { Bad_Opcode }, |
6366 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
6757 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
6367 | }, |
6758 | }, |
6368 | 6759 | ||
6369 | /* PREFIX_VEX_0F3A7F */ |
6760 | /* PREFIX_VEX_0F3A7F */ |
6370 | { |
6761 | { |
6371 | { Bad_Opcode }, |
6762 | { Bad_Opcode }, |
6372 | { Bad_Opcode }, |
6763 | { Bad_Opcode }, |
6373 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
6764 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
6374 | }, |
6765 | }, |
6375 | 6766 | ||
6376 | /* PREFIX_VEX_0F3ADF */ |
6767 | /* PREFIX_VEX_0F3ADF */ |
6377 | { |
6768 | { |
6378 | { Bad_Opcode }, |
6769 | { Bad_Opcode }, |
6379 | { Bad_Opcode }, |
6770 | { Bad_Opcode }, |
6380 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
6771 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
6381 | }, |
6772 | }, |
6382 | 6773 | ||
6383 | /* PREFIX_VEX_0F3AF0 */ |
6774 | /* PREFIX_VEX_0F3AF0 */ |
6384 | { |
6775 | { |
6385 | { Bad_Opcode }, |
6776 | { Bad_Opcode }, |
6386 | { Bad_Opcode }, |
6777 | { Bad_Opcode }, |
6387 | { Bad_Opcode }, |
6778 | { Bad_Opcode }, |
6388 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, |
6779 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, |
6389 | }, |
6780 | }, |
6390 | 6781 | ||
6391 | #define NEED_PREFIX_TABLE |
6782 | #define NEED_PREFIX_TABLE |
6392 | #include "i386-dis-evex.h" |
6783 | #include "i386-dis-evex.h" |
6393 | #undef NEED_PREFIX_TABLE |
6784 | #undef NEED_PREFIX_TABLE |
6394 | }; |
6785 | }; |
6395 | 6786 | ||
6396 | static const struct dis386 x86_64_table[][2] = { |
6787 | static const struct dis386 x86_64_table[][2] = { |
6397 | /* X86_64_06 */ |
6788 | /* X86_64_06 */ |
6398 | { |
6789 | { |
6399 | { "pushP", { es } }, |
6790 | { "pushP", { es }, 0 }, |
6400 | }, |
6791 | }, |
6401 | 6792 | ||
6402 | /* X86_64_07 */ |
6793 | /* X86_64_07 */ |
6403 | { |
6794 | { |
6404 | { "popP", { es } }, |
6795 | { "popP", { es }, 0 }, |
6405 | }, |
6796 | }, |
6406 | 6797 | ||
6407 | /* X86_64_0D */ |
6798 | /* X86_64_0D */ |
6408 | { |
6799 | { |
6409 | { "pushP", { cs } }, |
6800 | { "pushP", { cs }, 0 }, |
6410 | }, |
6801 | }, |
6411 | 6802 | ||
6412 | /* X86_64_16 */ |
6803 | /* X86_64_16 */ |
6413 | { |
6804 | { |
6414 | { "pushP", { ss } }, |
6805 | { "pushP", { ss }, 0 }, |
6415 | }, |
6806 | }, |
6416 | 6807 | ||
6417 | /* X86_64_17 */ |
6808 | /* X86_64_17 */ |
6418 | { |
6809 | { |
6419 | { "popP", { ss } }, |
6810 | { "popP", { ss }, 0 }, |
6420 | }, |
6811 | }, |
6421 | 6812 | ||
6422 | /* X86_64_1E */ |
6813 | /* X86_64_1E */ |
6423 | { |
6814 | { |
6424 | { "pushP", { ds } }, |
6815 | { "pushP", { ds }, 0 }, |
6425 | }, |
6816 | }, |
6426 | 6817 | ||
6427 | /* X86_64_1F */ |
6818 | /* X86_64_1F */ |
6428 | { |
6819 | { |
6429 | { "popP", { ds } }, |
6820 | { "popP", { ds }, 0 }, |
6430 | }, |
6821 | }, |
6431 | 6822 | ||
6432 | /* X86_64_27 */ |
6823 | /* X86_64_27 */ |
6433 | { |
6824 | { |
6434 | { "daa", { XX } }, |
6825 | { "daa", { XX }, 0 }, |
6435 | }, |
6826 | }, |
6436 | 6827 | ||
6437 | /* X86_64_2F */ |
6828 | /* X86_64_2F */ |
6438 | { |
6829 | { |
6439 | { "das", { XX } }, |
6830 | { "das", { XX }, 0 }, |
6440 | }, |
6831 | }, |
6441 | 6832 | ||
6442 | /* X86_64_37 */ |
6833 | /* X86_64_37 */ |
6443 | { |
6834 | { |
6444 | { "aaa", { XX } }, |
6835 | { "aaa", { XX }, 0 }, |
6445 | }, |
6836 | }, |
6446 | 6837 | ||
6447 | /* X86_64_3F */ |
6838 | /* X86_64_3F */ |
6448 | { |
6839 | { |
6449 | { "aas", { XX } }, |
6840 | { "aas", { XX }, 0 }, |
6450 | }, |
6841 | }, |
6451 | 6842 | ||
6452 | /* X86_64_60 */ |
6843 | /* X86_64_60 */ |
6453 | { |
6844 | { |
6454 | { "pushaP", { XX } }, |
6845 | { "pushaP", { XX }, 0 }, |
6455 | }, |
6846 | }, |
6456 | 6847 | ||
6457 | /* X86_64_61 */ |
6848 | /* X86_64_61 */ |
6458 | { |
6849 | { |
6459 | { "popaP", { XX } }, |
6850 | { "popaP", { XX }, 0 }, |
6460 | }, |
6851 | }, |
6461 | 6852 | ||
6462 | /* X86_64_62 */ |
6853 | /* X86_64_62 */ |
6463 | { |
6854 | { |
6464 | { MOD_TABLE (MOD_62_32BIT) }, |
6855 | { MOD_TABLE (MOD_62_32BIT) }, |
6465 | { EVEX_TABLE (EVEX_0F) }, |
6856 | { EVEX_TABLE (EVEX_0F) }, |
6466 | }, |
6857 | }, |
6467 | 6858 | ||
6468 | /* X86_64_63 */ |
6859 | /* X86_64_63 */ |
6469 | { |
6860 | { |
6470 | { "arpl", { Ew, Gw } }, |
6861 | { "arpl", { Ew, Gw }, 0 }, |
6471 | { "movs{lq|xd}", { Gv, Ed } }, |
6862 | { "movs{lq|xd}", { Gv, Ed }, 0 }, |
6472 | }, |
6863 | }, |
6473 | 6864 | ||
6474 | /* X86_64_6D */ |
6865 | /* X86_64_6D */ |
6475 | { |
6866 | { |
6476 | { "ins{R|}", { Yzr, indirDX } }, |
6867 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6477 | { "ins{G|}", { Yzr, indirDX } }, |
6868 | { "ins{G|}", { Yzr, indirDX }, 0 }, |
6478 | }, |
6869 | }, |
6479 | 6870 | ||
6480 | /* X86_64_6F */ |
6871 | /* X86_64_6F */ |
6481 | { |
6872 | { |
6482 | { "outs{R|}", { indirDXr, Xz } }, |
6873 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6483 | { "outs{G|}", { indirDXr, Xz } }, |
6874 | { "outs{G|}", { indirDXr, Xz }, 0 }, |
6484 | }, |
6875 | }, |
6485 | 6876 | ||
6486 | /* X86_64_9A */ |
6877 | /* X86_64_9A */ |
6487 | { |
6878 | { |
6488 | { "Jcall{T|}", { Ap } }, |
6879 | { "Jcall{T|}", { Ap }, 0 }, |
6489 | }, |
6880 | }, |
6490 | 6881 | ||
6491 | /* X86_64_C4 */ |
6882 | /* X86_64_C4 */ |
6492 | { |
6883 | { |
6493 | { MOD_TABLE (MOD_C4_32BIT) }, |
6884 | { MOD_TABLE (MOD_C4_32BIT) }, |
6494 | { VEX_C4_TABLE (VEX_0F) }, |
6885 | { VEX_C4_TABLE (VEX_0F) }, |
6495 | }, |
6886 | }, |
6496 | 6887 | ||
6497 | /* X86_64_C5 */ |
6888 | /* X86_64_C5 */ |
6498 | { |
6889 | { |
6499 | { MOD_TABLE (MOD_C5_32BIT) }, |
6890 | { MOD_TABLE (MOD_C5_32BIT) }, |
6500 | { VEX_C5_TABLE (VEX_0F) }, |
6891 | { VEX_C5_TABLE (VEX_0F) }, |
6501 | }, |
6892 | }, |
6502 | 6893 | ||
6503 | /* X86_64_CE */ |
6894 | /* X86_64_CE */ |
6504 | { |
6895 | { |
6505 | { "into", { XX } }, |
6896 | { "into", { XX }, 0 }, |
6506 | }, |
6897 | }, |
6507 | 6898 | ||
6508 | /* X86_64_D4 */ |
6899 | /* X86_64_D4 */ |
6509 | { |
6900 | { |
6510 | { "aam", { Ib } }, |
6901 | { "aam", { Ib }, 0 }, |
6511 | }, |
6902 | }, |
6512 | 6903 | ||
6513 | /* X86_64_D5 */ |
6904 | /* X86_64_D5 */ |
6514 | { |
6905 | { |
6515 | { "aad", { Ib } }, |
6906 | { "aad", { Ib }, 0 }, |
- | 6907 | }, |
|
- | 6908 | ||
- | 6909 | /* X86_64_E8 */ |
|
- | 6910 | { |
|
- | 6911 | { "callP", { Jv, BND }, 0 }, |
|
- | 6912 | { "call@", { Jv, BND }, 0 } |
|
- | 6913 | }, |
|
- | 6914 | ||
- | 6915 | /* X86_64_E9 */ |
|
- | 6916 | { |
|
- | 6917 | { "jmpP", { Jv, BND }, 0 }, |
|
- | 6918 | { "jmp@", { Jv, BND }, 0 } |
|
6516 | }, |
6919 | }, |
6517 | 6920 | ||
6518 | /* X86_64_EA */ |
6921 | /* X86_64_EA */ |
6519 | { |
6922 | { |
6520 | { "Jjmp{T|}", { Ap } }, |
6923 | { "Jjmp{T|}", { Ap }, 0 }, |
6521 | }, |
6924 | }, |
6522 | 6925 | ||
6523 | /* X86_64_0F01_REG_0 */ |
6926 | /* X86_64_0F01_REG_0 */ |
6524 | { |
6927 | { |
6525 | { "sgdt{Q|IQ}", { M } }, |
6928 | { "sgdt{Q|IQ}", { M }, 0 }, |
6526 | { "sgdt", { M } }, |
6929 | { "sgdt", { M }, 0 }, |
6527 | }, |
6930 | }, |
6528 | 6931 | ||
6529 | /* X86_64_0F01_REG_1 */ |
6932 | /* X86_64_0F01_REG_1 */ |
6530 | { |
6933 | { |
6531 | { "sidt{Q|IQ}", { M } }, |
6934 | { "sidt{Q|IQ}", { M }, 0 }, |
6532 | { "sidt", { M } }, |
6935 | { "sidt", { M }, 0 }, |
6533 | }, |
6936 | }, |
6534 | 6937 | ||
6535 | /* X86_64_0F01_REG_2 */ |
6938 | /* X86_64_0F01_REG_2 */ |
6536 | { |
6939 | { |
6537 | { "lgdt{Q|Q}", { M } }, |
6940 | { "lgdt{Q|Q}", { M }, 0 }, |
6538 | { "lgdt", { M } }, |
6941 | { "lgdt", { M }, 0 }, |
6539 | }, |
6942 | }, |
6540 | 6943 | ||
6541 | /* X86_64_0F01_REG_3 */ |
6944 | /* X86_64_0F01_REG_3 */ |
6542 | { |
6945 | { |
6543 | { "lidt{Q|Q}", { M } }, |
6946 | { "lidt{Q|Q}", { M }, 0 }, |
6544 | { "lidt", { M } }, |
6947 | { "lidt", { M }, 0 }, |
6545 | }, |
6948 | }, |
6546 | }; |
6949 | }; |
6547 | 6950 | ||
6548 | static const struct dis386 three_byte_table[][256] = { |
6951 | static const struct dis386 three_byte_table[][256] = { |
6549 | 6952 | ||
6550 | /* THREE_BYTE_0F38 */ |
6953 | /* THREE_BYTE_0F38 */ |
6551 | { |
6954 | { |
6552 | /* 00 */ |
6955 | /* 00 */ |
6553 | { "pshufb", { MX, EM } }, |
6956 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6554 | { "phaddw", { MX, EM } }, |
6957 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, |
6555 | { "phaddd", { MX, EM } }, |
6958 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, |
6556 | { "phaddsw", { MX, EM } }, |
6959 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, |
6557 | { "pmaddubsw", { MX, EM } }, |
6960 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, |
6558 | { "phsubw", { MX, EM } }, |
6961 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, |
6559 | { "phsubd", { MX, EM } }, |
6962 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, |
6560 | { "phsubsw", { MX, EM } }, |
6963 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, |
6561 | /* 08 */ |
6964 | /* 08 */ |
6562 | { "psignb", { MX, EM } }, |
6965 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6563 | { "psignw", { MX, EM } }, |
6966 | { "psignw", { MX, EM }, PREFIX_OPCODE }, |
6564 | { "psignd", { MX, EM } }, |
6967 | { "psignd", { MX, EM }, PREFIX_OPCODE }, |
6565 | { "pmulhrsw", { MX, EM } }, |
6968 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, |
6566 | { Bad_Opcode }, |
6969 | { Bad_Opcode }, |
6567 | { Bad_Opcode }, |
6970 | { Bad_Opcode }, |
6568 | { Bad_Opcode }, |
6971 | { Bad_Opcode }, |
6569 | { Bad_Opcode }, |
6972 | { Bad_Opcode }, |
6570 | /* 10 */ |
6973 | /* 10 */ |
6571 | { PREFIX_TABLE (PREFIX_0F3810) }, |
6974 | { PREFIX_TABLE (PREFIX_0F3810) }, |
6572 | { Bad_Opcode }, |
6975 | { Bad_Opcode }, |
6573 | { Bad_Opcode }, |
6976 | { Bad_Opcode }, |
6574 | { Bad_Opcode }, |
6977 | { Bad_Opcode }, |
6575 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6978 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6576 | { PREFIX_TABLE (PREFIX_0F3815) }, |
6979 | { PREFIX_TABLE (PREFIX_0F3815) }, |
6577 | { Bad_Opcode }, |
6980 | { Bad_Opcode }, |
6578 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6981 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6579 | /* 18 */ |
6982 | /* 18 */ |
6580 | { Bad_Opcode }, |
6983 | { Bad_Opcode }, |
6581 | { Bad_Opcode }, |
6984 | { Bad_Opcode }, |
6582 | { Bad_Opcode }, |
6985 | { Bad_Opcode }, |
6583 | { Bad_Opcode }, |
6986 | { Bad_Opcode }, |
6584 | { "pabsb", { MX, EM } }, |
6987 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6585 | { "pabsw", { MX, EM } }, |
6988 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, |
6586 | { "pabsd", { MX, EM } }, |
6989 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, |
6587 | { Bad_Opcode }, |
6990 | { Bad_Opcode }, |
6588 | /* 20 */ |
6991 | /* 20 */ |
6589 | { PREFIX_TABLE (PREFIX_0F3820) }, |
6992 | { PREFIX_TABLE (PREFIX_0F3820) }, |
6590 | { PREFIX_TABLE (PREFIX_0F3821) }, |
6993 | { PREFIX_TABLE (PREFIX_0F3821) }, |
6591 | { PREFIX_TABLE (PREFIX_0F3822) }, |
6994 | { PREFIX_TABLE (PREFIX_0F3822) }, |
6592 | { PREFIX_TABLE (PREFIX_0F3823) }, |
6995 | { PREFIX_TABLE (PREFIX_0F3823) }, |
6593 | { PREFIX_TABLE (PREFIX_0F3824) }, |
6996 | { PREFIX_TABLE (PREFIX_0F3824) }, |
6594 | { PREFIX_TABLE (PREFIX_0F3825) }, |
6997 | { PREFIX_TABLE (PREFIX_0F3825) }, |
6595 | { Bad_Opcode }, |
6998 | { Bad_Opcode }, |
6596 | { Bad_Opcode }, |
6999 | { Bad_Opcode }, |
6597 | /* 28 */ |
7000 | /* 28 */ |
6598 | { PREFIX_TABLE (PREFIX_0F3828) }, |
7001 | { PREFIX_TABLE (PREFIX_0F3828) }, |
6599 | { PREFIX_TABLE (PREFIX_0F3829) }, |
7002 | { PREFIX_TABLE (PREFIX_0F3829) }, |
6600 | { PREFIX_TABLE (PREFIX_0F382A) }, |
7003 | { PREFIX_TABLE (PREFIX_0F382A) }, |
6601 | { PREFIX_TABLE (PREFIX_0F382B) }, |
7004 | { PREFIX_TABLE (PREFIX_0F382B) }, |
6602 | { Bad_Opcode }, |
7005 | { Bad_Opcode }, |
6603 | { Bad_Opcode }, |
7006 | { Bad_Opcode }, |
6604 | { Bad_Opcode }, |
7007 | { Bad_Opcode }, |
6605 | { Bad_Opcode }, |
7008 | { Bad_Opcode }, |
6606 | /* 30 */ |
7009 | /* 30 */ |
6607 | { PREFIX_TABLE (PREFIX_0F3830) }, |
7010 | { PREFIX_TABLE (PREFIX_0F3830) }, |
6608 | { PREFIX_TABLE (PREFIX_0F3831) }, |
7011 | { PREFIX_TABLE (PREFIX_0F3831) }, |
6609 | { PREFIX_TABLE (PREFIX_0F3832) }, |
7012 | { PREFIX_TABLE (PREFIX_0F3832) }, |
6610 | { PREFIX_TABLE (PREFIX_0F3833) }, |
7013 | { PREFIX_TABLE (PREFIX_0F3833) }, |
6611 | { PREFIX_TABLE (PREFIX_0F3834) }, |
7014 | { PREFIX_TABLE (PREFIX_0F3834) }, |
6612 | { PREFIX_TABLE (PREFIX_0F3835) }, |
7015 | { PREFIX_TABLE (PREFIX_0F3835) }, |
6613 | { Bad_Opcode }, |
7016 | { Bad_Opcode }, |
6614 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7017 | { PREFIX_TABLE (PREFIX_0F3837) }, |
6615 | /* 38 */ |
7018 | /* 38 */ |
6616 | { PREFIX_TABLE (PREFIX_0F3838) }, |
7019 | { PREFIX_TABLE (PREFIX_0F3838) }, |
6617 | { PREFIX_TABLE (PREFIX_0F3839) }, |
7020 | { PREFIX_TABLE (PREFIX_0F3839) }, |
6618 | { PREFIX_TABLE (PREFIX_0F383A) }, |
7021 | { PREFIX_TABLE (PREFIX_0F383A) }, |
6619 | { PREFIX_TABLE (PREFIX_0F383B) }, |
7022 | { PREFIX_TABLE (PREFIX_0F383B) }, |
6620 | { PREFIX_TABLE (PREFIX_0F383C) }, |
7023 | { PREFIX_TABLE (PREFIX_0F383C) }, |
6621 | { PREFIX_TABLE (PREFIX_0F383D) }, |
7024 | { PREFIX_TABLE (PREFIX_0F383D) }, |
6622 | { PREFIX_TABLE (PREFIX_0F383E) }, |
7025 | { PREFIX_TABLE (PREFIX_0F383E) }, |
6623 | { PREFIX_TABLE (PREFIX_0F383F) }, |
7026 | { PREFIX_TABLE (PREFIX_0F383F) }, |
6624 | /* 40 */ |
7027 | /* 40 */ |
6625 | { PREFIX_TABLE (PREFIX_0F3840) }, |
7028 | { PREFIX_TABLE (PREFIX_0F3840) }, |
6626 | { PREFIX_TABLE (PREFIX_0F3841) }, |
7029 | { PREFIX_TABLE (PREFIX_0F3841) }, |
6627 | { Bad_Opcode }, |
7030 | { Bad_Opcode }, |
6628 | { Bad_Opcode }, |
7031 | { Bad_Opcode }, |
6629 | { Bad_Opcode }, |
7032 | { Bad_Opcode }, |
6630 | { Bad_Opcode }, |
7033 | { Bad_Opcode }, |
6631 | { Bad_Opcode }, |
7034 | { Bad_Opcode }, |
6632 | { Bad_Opcode }, |
7035 | { Bad_Opcode }, |
6633 | /* 48 */ |
7036 | /* 48 */ |
6634 | { Bad_Opcode }, |
7037 | { Bad_Opcode }, |
6635 | { Bad_Opcode }, |
7038 | { Bad_Opcode }, |
6636 | { Bad_Opcode }, |
7039 | { Bad_Opcode }, |
6637 | { Bad_Opcode }, |
7040 | { Bad_Opcode }, |
6638 | { Bad_Opcode }, |
7041 | { Bad_Opcode }, |
6639 | { Bad_Opcode }, |
7042 | { Bad_Opcode }, |
6640 | { Bad_Opcode }, |
7043 | { Bad_Opcode }, |
6641 | { Bad_Opcode }, |
7044 | { Bad_Opcode }, |
6642 | /* 50 */ |
7045 | /* 50 */ |
6643 | { Bad_Opcode }, |
7046 | { Bad_Opcode }, |
6644 | { Bad_Opcode }, |
7047 | { Bad_Opcode }, |
6645 | { Bad_Opcode }, |
7048 | { Bad_Opcode }, |
6646 | { Bad_Opcode }, |
7049 | { Bad_Opcode }, |
6647 | { Bad_Opcode }, |
7050 | { Bad_Opcode }, |
6648 | { Bad_Opcode }, |
7051 | { Bad_Opcode }, |
6649 | { Bad_Opcode }, |
7052 | { Bad_Opcode }, |
6650 | { Bad_Opcode }, |
7053 | { Bad_Opcode }, |
6651 | /* 58 */ |
7054 | /* 58 */ |
6652 | { Bad_Opcode }, |
7055 | { Bad_Opcode }, |
6653 | { Bad_Opcode }, |
7056 | { Bad_Opcode }, |
6654 | { Bad_Opcode }, |
7057 | { Bad_Opcode }, |
6655 | { Bad_Opcode }, |
7058 | { Bad_Opcode }, |
6656 | { Bad_Opcode }, |
7059 | { Bad_Opcode }, |
6657 | { Bad_Opcode }, |
7060 | { Bad_Opcode }, |
6658 | { Bad_Opcode }, |
7061 | { Bad_Opcode }, |
6659 | { Bad_Opcode }, |
7062 | { Bad_Opcode }, |
6660 | /* 60 */ |
7063 | /* 60 */ |
6661 | { Bad_Opcode }, |
7064 | { Bad_Opcode }, |
6662 | { Bad_Opcode }, |
7065 | { Bad_Opcode }, |
6663 | { Bad_Opcode }, |
7066 | { Bad_Opcode }, |
6664 | { Bad_Opcode }, |
7067 | { Bad_Opcode }, |
6665 | { Bad_Opcode }, |
7068 | { Bad_Opcode }, |
6666 | { Bad_Opcode }, |
7069 | { Bad_Opcode }, |
6667 | { Bad_Opcode }, |
7070 | { Bad_Opcode }, |
6668 | { Bad_Opcode }, |
7071 | { Bad_Opcode }, |
6669 | /* 68 */ |
7072 | /* 68 */ |
6670 | { Bad_Opcode }, |
7073 | { Bad_Opcode }, |
6671 | { Bad_Opcode }, |
7074 | { Bad_Opcode }, |
6672 | { Bad_Opcode }, |
7075 | { Bad_Opcode }, |
6673 | { Bad_Opcode }, |
7076 | { Bad_Opcode }, |
6674 | { Bad_Opcode }, |
7077 | { Bad_Opcode }, |
6675 | { Bad_Opcode }, |
7078 | { Bad_Opcode }, |
6676 | { Bad_Opcode }, |
7079 | { Bad_Opcode }, |
6677 | { Bad_Opcode }, |
7080 | { Bad_Opcode }, |
6678 | /* 70 */ |
7081 | /* 70 */ |
6679 | { Bad_Opcode }, |
7082 | { Bad_Opcode }, |
6680 | { Bad_Opcode }, |
7083 | { Bad_Opcode }, |
6681 | { Bad_Opcode }, |
7084 | { Bad_Opcode }, |
6682 | { Bad_Opcode }, |
7085 | { Bad_Opcode }, |
6683 | { Bad_Opcode }, |
7086 | { Bad_Opcode }, |
6684 | { Bad_Opcode }, |
7087 | { Bad_Opcode }, |
6685 | { Bad_Opcode }, |
7088 | { Bad_Opcode }, |
6686 | { Bad_Opcode }, |
7089 | { Bad_Opcode }, |
6687 | /* 78 */ |
7090 | /* 78 */ |
6688 | { Bad_Opcode }, |
7091 | { Bad_Opcode }, |
6689 | { Bad_Opcode }, |
7092 | { Bad_Opcode }, |
6690 | { Bad_Opcode }, |
7093 | { Bad_Opcode }, |
6691 | { Bad_Opcode }, |
7094 | { Bad_Opcode }, |
6692 | { Bad_Opcode }, |
7095 | { Bad_Opcode }, |
6693 | { Bad_Opcode }, |
7096 | { Bad_Opcode }, |
6694 | { Bad_Opcode }, |
7097 | { Bad_Opcode }, |
6695 | { Bad_Opcode }, |
7098 | { Bad_Opcode }, |
6696 | /* 80 */ |
7099 | /* 80 */ |
6697 | { PREFIX_TABLE (PREFIX_0F3880) }, |
7100 | { PREFIX_TABLE (PREFIX_0F3880) }, |
6698 | { PREFIX_TABLE (PREFIX_0F3881) }, |
7101 | { PREFIX_TABLE (PREFIX_0F3881) }, |
6699 | { PREFIX_TABLE (PREFIX_0F3882) }, |
7102 | { PREFIX_TABLE (PREFIX_0F3882) }, |
6700 | { Bad_Opcode }, |
7103 | { Bad_Opcode }, |
6701 | { Bad_Opcode }, |
7104 | { Bad_Opcode }, |
6702 | { Bad_Opcode }, |
7105 | { Bad_Opcode }, |
6703 | { Bad_Opcode }, |
7106 | { Bad_Opcode }, |
6704 | { Bad_Opcode }, |
7107 | { Bad_Opcode }, |
6705 | /* 88 */ |
7108 | /* 88 */ |
6706 | { Bad_Opcode }, |
7109 | { Bad_Opcode }, |
6707 | { Bad_Opcode }, |
7110 | { Bad_Opcode }, |
6708 | { Bad_Opcode }, |
7111 | { Bad_Opcode }, |
6709 | { Bad_Opcode }, |
7112 | { Bad_Opcode }, |
6710 | { Bad_Opcode }, |
7113 | { Bad_Opcode }, |
6711 | { Bad_Opcode }, |
7114 | { Bad_Opcode }, |
6712 | { Bad_Opcode }, |
7115 | { Bad_Opcode }, |
6713 | { Bad_Opcode }, |
7116 | { Bad_Opcode }, |
6714 | /* 90 */ |
7117 | /* 90 */ |
6715 | { Bad_Opcode }, |
7118 | { Bad_Opcode }, |
6716 | { Bad_Opcode }, |
7119 | { Bad_Opcode }, |
6717 | { Bad_Opcode }, |
7120 | { Bad_Opcode }, |
6718 | { Bad_Opcode }, |
7121 | { Bad_Opcode }, |
6719 | { Bad_Opcode }, |
7122 | { Bad_Opcode }, |
6720 | { Bad_Opcode }, |
7123 | { Bad_Opcode }, |
6721 | { Bad_Opcode }, |
7124 | { Bad_Opcode }, |
6722 | { Bad_Opcode }, |
7125 | { Bad_Opcode }, |
6723 | /* 98 */ |
7126 | /* 98 */ |
6724 | { Bad_Opcode }, |
7127 | { Bad_Opcode }, |
6725 | { Bad_Opcode }, |
7128 | { Bad_Opcode }, |
6726 | { Bad_Opcode }, |
7129 | { Bad_Opcode }, |
6727 | { Bad_Opcode }, |
7130 | { Bad_Opcode }, |
6728 | { Bad_Opcode }, |
7131 | { Bad_Opcode }, |
6729 | { Bad_Opcode }, |
7132 | { Bad_Opcode }, |
6730 | { Bad_Opcode }, |
7133 | { Bad_Opcode }, |
6731 | { Bad_Opcode }, |
7134 | { Bad_Opcode }, |
6732 | /* a0 */ |
7135 | /* a0 */ |
6733 | { Bad_Opcode }, |
7136 | { Bad_Opcode }, |
6734 | { Bad_Opcode }, |
7137 | { Bad_Opcode }, |
6735 | { Bad_Opcode }, |
7138 | { Bad_Opcode }, |
6736 | { Bad_Opcode }, |
7139 | { Bad_Opcode }, |
6737 | { Bad_Opcode }, |
7140 | { Bad_Opcode }, |
6738 | { Bad_Opcode }, |
7141 | { Bad_Opcode }, |
6739 | { Bad_Opcode }, |
7142 | { Bad_Opcode }, |
6740 | { Bad_Opcode }, |
7143 | { Bad_Opcode }, |
6741 | /* a8 */ |
7144 | /* a8 */ |
6742 | { Bad_Opcode }, |
7145 | { Bad_Opcode }, |
6743 | { Bad_Opcode }, |
7146 | { Bad_Opcode }, |
6744 | { Bad_Opcode }, |
7147 | { Bad_Opcode }, |
6745 | { Bad_Opcode }, |
7148 | { Bad_Opcode }, |
6746 | { Bad_Opcode }, |
7149 | { Bad_Opcode }, |
6747 | { Bad_Opcode }, |
7150 | { Bad_Opcode }, |
6748 | { Bad_Opcode }, |
7151 | { Bad_Opcode }, |
6749 | { Bad_Opcode }, |
7152 | { Bad_Opcode }, |
6750 | /* b0 */ |
7153 | /* b0 */ |
6751 | { Bad_Opcode }, |
7154 | { Bad_Opcode }, |
6752 | { Bad_Opcode }, |
7155 | { Bad_Opcode }, |
6753 | { Bad_Opcode }, |
7156 | { Bad_Opcode }, |
6754 | { Bad_Opcode }, |
7157 | { Bad_Opcode }, |
6755 | { Bad_Opcode }, |
7158 | { Bad_Opcode }, |
6756 | { Bad_Opcode }, |
7159 | { Bad_Opcode }, |
6757 | { Bad_Opcode }, |
7160 | { Bad_Opcode }, |
6758 | { Bad_Opcode }, |
7161 | { Bad_Opcode }, |
6759 | /* b8 */ |
7162 | /* b8 */ |
6760 | { Bad_Opcode }, |
7163 | { Bad_Opcode }, |
6761 | { Bad_Opcode }, |
7164 | { Bad_Opcode }, |
6762 | { Bad_Opcode }, |
7165 | { Bad_Opcode }, |
6763 | { Bad_Opcode }, |
7166 | { Bad_Opcode }, |
6764 | { Bad_Opcode }, |
7167 | { Bad_Opcode }, |
6765 | { Bad_Opcode }, |
7168 | { Bad_Opcode }, |
6766 | { Bad_Opcode }, |
7169 | { Bad_Opcode }, |
6767 | { Bad_Opcode }, |
7170 | { Bad_Opcode }, |
6768 | /* c0 */ |
7171 | /* c0 */ |
6769 | { Bad_Opcode }, |
7172 | { Bad_Opcode }, |
6770 | { Bad_Opcode }, |
7173 | { Bad_Opcode }, |
6771 | { Bad_Opcode }, |
7174 | { Bad_Opcode }, |
6772 | { Bad_Opcode }, |
7175 | { Bad_Opcode }, |
6773 | { Bad_Opcode }, |
7176 | { Bad_Opcode }, |
6774 | { Bad_Opcode }, |
7177 | { Bad_Opcode }, |
6775 | { Bad_Opcode }, |
7178 | { Bad_Opcode }, |
6776 | { Bad_Opcode }, |
7179 | { Bad_Opcode }, |
6777 | /* c8 */ |
7180 | /* c8 */ |
6778 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7181 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
6779 | { PREFIX_TABLE (PREFIX_0F38C9) }, |
7182 | { PREFIX_TABLE (PREFIX_0F38C9) }, |
6780 | { PREFIX_TABLE (PREFIX_0F38CA) }, |
7183 | { PREFIX_TABLE (PREFIX_0F38CA) }, |
6781 | { PREFIX_TABLE (PREFIX_0F38CB) }, |
7184 | { PREFIX_TABLE (PREFIX_0F38CB) }, |
6782 | { PREFIX_TABLE (PREFIX_0F38CC) }, |
7185 | { PREFIX_TABLE (PREFIX_0F38CC) }, |
6783 | { PREFIX_TABLE (PREFIX_0F38CD) }, |
7186 | { PREFIX_TABLE (PREFIX_0F38CD) }, |
6784 | { Bad_Opcode }, |
7187 | { Bad_Opcode }, |
6785 | { Bad_Opcode }, |
7188 | { Bad_Opcode }, |
6786 | /* d0 */ |
7189 | /* d0 */ |
6787 | { Bad_Opcode }, |
7190 | { Bad_Opcode }, |
6788 | { Bad_Opcode }, |
7191 | { Bad_Opcode }, |
6789 | { Bad_Opcode }, |
7192 | { Bad_Opcode }, |
6790 | { Bad_Opcode }, |
7193 | { Bad_Opcode }, |
6791 | { Bad_Opcode }, |
7194 | { Bad_Opcode }, |
6792 | { Bad_Opcode }, |
7195 | { Bad_Opcode }, |
6793 | { Bad_Opcode }, |
7196 | { Bad_Opcode }, |
6794 | { Bad_Opcode }, |
7197 | { Bad_Opcode }, |
6795 | /* d8 */ |
7198 | /* d8 */ |
6796 | { Bad_Opcode }, |
7199 | { Bad_Opcode }, |
6797 | { Bad_Opcode }, |
7200 | { Bad_Opcode }, |
6798 | { Bad_Opcode }, |
7201 | { Bad_Opcode }, |
6799 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7202 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
6800 | { PREFIX_TABLE (PREFIX_0F38DC) }, |
7203 | { PREFIX_TABLE (PREFIX_0F38DC) }, |
6801 | { PREFIX_TABLE (PREFIX_0F38DD) }, |
7204 | { PREFIX_TABLE (PREFIX_0F38DD) }, |
6802 | { PREFIX_TABLE (PREFIX_0F38DE) }, |
7205 | { PREFIX_TABLE (PREFIX_0F38DE) }, |
6803 | { PREFIX_TABLE (PREFIX_0F38DF) }, |
7206 | { PREFIX_TABLE (PREFIX_0F38DF) }, |
6804 | /* e0 */ |
7207 | /* e0 */ |
6805 | { Bad_Opcode }, |
7208 | { Bad_Opcode }, |
6806 | { Bad_Opcode }, |
7209 | { Bad_Opcode }, |
6807 | { Bad_Opcode }, |
7210 | { Bad_Opcode }, |
6808 | { Bad_Opcode }, |
7211 | { Bad_Opcode }, |
6809 | { Bad_Opcode }, |
7212 | { Bad_Opcode }, |
6810 | { Bad_Opcode }, |
7213 | { Bad_Opcode }, |
6811 | { Bad_Opcode }, |
7214 | { Bad_Opcode }, |
6812 | { Bad_Opcode }, |
7215 | { Bad_Opcode }, |
6813 | /* e8 */ |
7216 | /* e8 */ |
6814 | { Bad_Opcode }, |
7217 | { Bad_Opcode }, |
6815 | { Bad_Opcode }, |
7218 | { Bad_Opcode }, |
6816 | { Bad_Opcode }, |
7219 | { Bad_Opcode }, |
6817 | { Bad_Opcode }, |
7220 | { Bad_Opcode }, |
6818 | { Bad_Opcode }, |
7221 | { Bad_Opcode }, |
6819 | { Bad_Opcode }, |
7222 | { Bad_Opcode }, |
6820 | { Bad_Opcode }, |
7223 | { Bad_Opcode }, |
6821 | { Bad_Opcode }, |
7224 | { Bad_Opcode }, |
6822 | /* f0 */ |
7225 | /* f0 */ |
6823 | { PREFIX_TABLE (PREFIX_0F38F0) }, |
7226 | { PREFIX_TABLE (PREFIX_0F38F0) }, |
6824 | { PREFIX_TABLE (PREFIX_0F38F1) }, |
7227 | { PREFIX_TABLE (PREFIX_0F38F1) }, |
6825 | { Bad_Opcode }, |
7228 | { Bad_Opcode }, |
6826 | { Bad_Opcode }, |
7229 | { Bad_Opcode }, |
6827 | { Bad_Opcode }, |
7230 | { Bad_Opcode }, |
6828 | { Bad_Opcode }, |
7231 | { Bad_Opcode }, |
6829 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
7232 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
6830 | { Bad_Opcode }, |
7233 | { Bad_Opcode }, |
6831 | /* f8 */ |
7234 | /* f8 */ |
6832 | { Bad_Opcode }, |
7235 | { Bad_Opcode }, |
6833 | { Bad_Opcode }, |
7236 | { Bad_Opcode }, |
6834 | { Bad_Opcode }, |
7237 | { Bad_Opcode }, |
6835 | { Bad_Opcode }, |
7238 | { Bad_Opcode }, |
6836 | { Bad_Opcode }, |
7239 | { Bad_Opcode }, |
6837 | { Bad_Opcode }, |
7240 | { Bad_Opcode }, |
6838 | { Bad_Opcode }, |
7241 | { Bad_Opcode }, |
6839 | { Bad_Opcode }, |
7242 | { Bad_Opcode }, |
6840 | }, |
7243 | }, |
6841 | /* THREE_BYTE_0F3A */ |
7244 | /* THREE_BYTE_0F3A */ |
6842 | { |
7245 | { |
6843 | /* 00 */ |
7246 | /* 00 */ |
6844 | { Bad_Opcode }, |
7247 | { Bad_Opcode }, |
6845 | { Bad_Opcode }, |
7248 | { Bad_Opcode }, |
6846 | { Bad_Opcode }, |
7249 | { Bad_Opcode }, |
6847 | { Bad_Opcode }, |
7250 | { Bad_Opcode }, |
6848 | { Bad_Opcode }, |
7251 | { Bad_Opcode }, |
6849 | { Bad_Opcode }, |
7252 | { Bad_Opcode }, |
6850 | { Bad_Opcode }, |
7253 | { Bad_Opcode }, |
6851 | { Bad_Opcode }, |
7254 | { Bad_Opcode }, |
6852 | /* 08 */ |
7255 | /* 08 */ |
6853 | { PREFIX_TABLE (PREFIX_0F3A08) }, |
7256 | { PREFIX_TABLE (PREFIX_0F3A08) }, |
6854 | { PREFIX_TABLE (PREFIX_0F3A09) }, |
7257 | { PREFIX_TABLE (PREFIX_0F3A09) }, |
6855 | { PREFIX_TABLE (PREFIX_0F3A0A) }, |
7258 | { PREFIX_TABLE (PREFIX_0F3A0A) }, |
6856 | { PREFIX_TABLE (PREFIX_0F3A0B) }, |
7259 | { PREFIX_TABLE (PREFIX_0F3A0B) }, |
6857 | { PREFIX_TABLE (PREFIX_0F3A0C) }, |
7260 | { PREFIX_TABLE (PREFIX_0F3A0C) }, |
6858 | { PREFIX_TABLE (PREFIX_0F3A0D) }, |
7261 | { PREFIX_TABLE (PREFIX_0F3A0D) }, |
6859 | { PREFIX_TABLE (PREFIX_0F3A0E) }, |
7262 | { PREFIX_TABLE (PREFIX_0F3A0E) }, |
6860 | { "palignr", { MX, EM, Ib } }, |
7263 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
6861 | /* 10 */ |
7264 | /* 10 */ |
6862 | { Bad_Opcode }, |
7265 | { Bad_Opcode }, |
6863 | { Bad_Opcode }, |
7266 | { Bad_Opcode }, |
6864 | { Bad_Opcode }, |
7267 | { Bad_Opcode }, |
6865 | { Bad_Opcode }, |
7268 | { Bad_Opcode }, |
6866 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7269 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
6867 | { PREFIX_TABLE (PREFIX_0F3A15) }, |
7270 | { PREFIX_TABLE (PREFIX_0F3A15) }, |
6868 | { PREFIX_TABLE (PREFIX_0F3A16) }, |
7271 | { PREFIX_TABLE (PREFIX_0F3A16) }, |
6869 | { PREFIX_TABLE (PREFIX_0F3A17) }, |
7272 | { PREFIX_TABLE (PREFIX_0F3A17) }, |
6870 | /* 18 */ |
7273 | /* 18 */ |
6871 | { Bad_Opcode }, |
7274 | { Bad_Opcode }, |
6872 | { Bad_Opcode }, |
7275 | { Bad_Opcode }, |
6873 | { Bad_Opcode }, |
7276 | { Bad_Opcode }, |
6874 | { Bad_Opcode }, |
7277 | { Bad_Opcode }, |
6875 | { Bad_Opcode }, |
7278 | { Bad_Opcode }, |
6876 | { Bad_Opcode }, |
7279 | { Bad_Opcode }, |
6877 | { Bad_Opcode }, |
7280 | { Bad_Opcode }, |
6878 | { Bad_Opcode }, |
7281 | { Bad_Opcode }, |
6879 | /* 20 */ |
7282 | /* 20 */ |
6880 | { PREFIX_TABLE (PREFIX_0F3A20) }, |
7283 | { PREFIX_TABLE (PREFIX_0F3A20) }, |
6881 | { PREFIX_TABLE (PREFIX_0F3A21) }, |
7284 | { PREFIX_TABLE (PREFIX_0F3A21) }, |
6882 | { PREFIX_TABLE (PREFIX_0F3A22) }, |
7285 | { PREFIX_TABLE (PREFIX_0F3A22) }, |
6883 | { Bad_Opcode }, |
7286 | { Bad_Opcode }, |
6884 | { Bad_Opcode }, |
7287 | { Bad_Opcode }, |
6885 | { Bad_Opcode }, |
7288 | { Bad_Opcode }, |
6886 | { Bad_Opcode }, |
7289 | { Bad_Opcode }, |
6887 | { Bad_Opcode }, |
7290 | { Bad_Opcode }, |
6888 | /* 28 */ |
7291 | /* 28 */ |
6889 | { Bad_Opcode }, |
7292 | { Bad_Opcode }, |
6890 | { Bad_Opcode }, |
7293 | { Bad_Opcode }, |
6891 | { Bad_Opcode }, |
7294 | { Bad_Opcode }, |
6892 | { Bad_Opcode }, |
7295 | { Bad_Opcode }, |
6893 | { Bad_Opcode }, |
7296 | { Bad_Opcode }, |
6894 | { Bad_Opcode }, |
7297 | { Bad_Opcode }, |
6895 | { Bad_Opcode }, |
7298 | { Bad_Opcode }, |
6896 | { Bad_Opcode }, |
7299 | { Bad_Opcode }, |
6897 | /* 30 */ |
7300 | /* 30 */ |
6898 | { Bad_Opcode }, |
7301 | { Bad_Opcode }, |
6899 | { Bad_Opcode }, |
7302 | { Bad_Opcode }, |
6900 | { Bad_Opcode }, |
7303 | { Bad_Opcode }, |
6901 | { Bad_Opcode }, |
7304 | { Bad_Opcode }, |
6902 | { Bad_Opcode }, |
7305 | { Bad_Opcode }, |
6903 | { Bad_Opcode }, |
7306 | { Bad_Opcode }, |
6904 | { Bad_Opcode }, |
7307 | { Bad_Opcode }, |
6905 | { Bad_Opcode }, |
7308 | { Bad_Opcode }, |
6906 | /* 38 */ |
7309 | /* 38 */ |
6907 | { Bad_Opcode }, |
7310 | { Bad_Opcode }, |
6908 | { Bad_Opcode }, |
7311 | { Bad_Opcode }, |
6909 | { Bad_Opcode }, |
7312 | { Bad_Opcode }, |
6910 | { Bad_Opcode }, |
7313 | { Bad_Opcode }, |
6911 | { Bad_Opcode }, |
7314 | { Bad_Opcode }, |
6912 | { Bad_Opcode }, |
7315 | { Bad_Opcode }, |
6913 | { Bad_Opcode }, |
7316 | { Bad_Opcode }, |
6914 | { Bad_Opcode }, |
7317 | { Bad_Opcode }, |
6915 | /* 40 */ |
7318 | /* 40 */ |
6916 | { PREFIX_TABLE (PREFIX_0F3A40) }, |
7319 | { PREFIX_TABLE (PREFIX_0F3A40) }, |
6917 | { PREFIX_TABLE (PREFIX_0F3A41) }, |
7320 | { PREFIX_TABLE (PREFIX_0F3A41) }, |
6918 | { PREFIX_TABLE (PREFIX_0F3A42) }, |
7321 | { PREFIX_TABLE (PREFIX_0F3A42) }, |
6919 | { Bad_Opcode }, |
7322 | { Bad_Opcode }, |
6920 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
7323 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
6921 | { Bad_Opcode }, |
7324 | { Bad_Opcode }, |
6922 | { Bad_Opcode }, |
7325 | { Bad_Opcode }, |
6923 | { Bad_Opcode }, |
7326 | { Bad_Opcode }, |
6924 | /* 48 */ |
7327 | /* 48 */ |
6925 | { Bad_Opcode }, |
7328 | { Bad_Opcode }, |
6926 | { Bad_Opcode }, |
7329 | { Bad_Opcode }, |
6927 | { Bad_Opcode }, |
7330 | { Bad_Opcode }, |
6928 | { Bad_Opcode }, |
7331 | { Bad_Opcode }, |
6929 | { Bad_Opcode }, |
7332 | { Bad_Opcode }, |
6930 | { Bad_Opcode }, |
7333 | { Bad_Opcode }, |
6931 | { Bad_Opcode }, |
7334 | { Bad_Opcode }, |
6932 | { Bad_Opcode }, |
7335 | { Bad_Opcode }, |
6933 | /* 50 */ |
7336 | /* 50 */ |
6934 | { Bad_Opcode }, |
7337 | { Bad_Opcode }, |
6935 | { Bad_Opcode }, |
7338 | { Bad_Opcode }, |
6936 | { Bad_Opcode }, |
7339 | { Bad_Opcode }, |
6937 | { Bad_Opcode }, |
7340 | { Bad_Opcode }, |
6938 | { Bad_Opcode }, |
7341 | { Bad_Opcode }, |
6939 | { Bad_Opcode }, |
7342 | { Bad_Opcode }, |
6940 | { Bad_Opcode }, |
7343 | { Bad_Opcode }, |
6941 | { Bad_Opcode }, |
7344 | { Bad_Opcode }, |
6942 | /* 58 */ |
7345 | /* 58 */ |
6943 | { Bad_Opcode }, |
7346 | { Bad_Opcode }, |
6944 | { Bad_Opcode }, |
7347 | { Bad_Opcode }, |
6945 | { Bad_Opcode }, |
7348 | { Bad_Opcode }, |
6946 | { Bad_Opcode }, |
7349 | { Bad_Opcode }, |
6947 | { Bad_Opcode }, |
7350 | { Bad_Opcode }, |
6948 | { Bad_Opcode }, |
7351 | { Bad_Opcode }, |
6949 | { Bad_Opcode }, |
7352 | { Bad_Opcode }, |
6950 | { Bad_Opcode }, |
7353 | { Bad_Opcode }, |
6951 | /* 60 */ |
7354 | /* 60 */ |
6952 | { PREFIX_TABLE (PREFIX_0F3A60) }, |
7355 | { PREFIX_TABLE (PREFIX_0F3A60) }, |
6953 | { PREFIX_TABLE (PREFIX_0F3A61) }, |
7356 | { PREFIX_TABLE (PREFIX_0F3A61) }, |
6954 | { PREFIX_TABLE (PREFIX_0F3A62) }, |
7357 | { PREFIX_TABLE (PREFIX_0F3A62) }, |
6955 | { PREFIX_TABLE (PREFIX_0F3A63) }, |
7358 | { PREFIX_TABLE (PREFIX_0F3A63) }, |
6956 | { Bad_Opcode }, |
7359 | { Bad_Opcode }, |
6957 | { Bad_Opcode }, |
7360 | { Bad_Opcode }, |
6958 | { Bad_Opcode }, |
7361 | { Bad_Opcode }, |
6959 | { Bad_Opcode }, |
7362 | { Bad_Opcode }, |
6960 | /* 68 */ |
7363 | /* 68 */ |
6961 | { Bad_Opcode }, |
7364 | { Bad_Opcode }, |
6962 | { Bad_Opcode }, |
7365 | { Bad_Opcode }, |
6963 | { Bad_Opcode }, |
7366 | { Bad_Opcode }, |
6964 | { Bad_Opcode }, |
7367 | { Bad_Opcode }, |
6965 | { Bad_Opcode }, |
7368 | { Bad_Opcode }, |
6966 | { Bad_Opcode }, |
7369 | { Bad_Opcode }, |
6967 | { Bad_Opcode }, |
7370 | { Bad_Opcode }, |
6968 | { Bad_Opcode }, |
7371 | { Bad_Opcode }, |
6969 | /* 70 */ |
7372 | /* 70 */ |
6970 | { Bad_Opcode }, |
7373 | { Bad_Opcode }, |
6971 | { Bad_Opcode }, |
7374 | { Bad_Opcode }, |
6972 | { Bad_Opcode }, |
7375 | { Bad_Opcode }, |
6973 | { Bad_Opcode }, |
7376 | { Bad_Opcode }, |
6974 | { Bad_Opcode }, |
7377 | { Bad_Opcode }, |
6975 | { Bad_Opcode }, |
7378 | { Bad_Opcode }, |
6976 | { Bad_Opcode }, |
7379 | { Bad_Opcode }, |
6977 | { Bad_Opcode }, |
7380 | { Bad_Opcode }, |
6978 | /* 78 */ |
7381 | /* 78 */ |
6979 | { Bad_Opcode }, |
7382 | { Bad_Opcode }, |
6980 | { Bad_Opcode }, |
7383 | { Bad_Opcode }, |
6981 | { Bad_Opcode }, |
7384 | { Bad_Opcode }, |
6982 | { Bad_Opcode }, |
7385 | { Bad_Opcode }, |
6983 | { Bad_Opcode }, |
7386 | { Bad_Opcode }, |
6984 | { Bad_Opcode }, |
7387 | { Bad_Opcode }, |
6985 | { Bad_Opcode }, |
7388 | { Bad_Opcode }, |
6986 | { Bad_Opcode }, |
7389 | { Bad_Opcode }, |
6987 | /* 80 */ |
7390 | /* 80 */ |
6988 | { Bad_Opcode }, |
7391 | { Bad_Opcode }, |
6989 | { Bad_Opcode }, |
7392 | { Bad_Opcode }, |
6990 | { Bad_Opcode }, |
7393 | { Bad_Opcode }, |
6991 | { Bad_Opcode }, |
7394 | { Bad_Opcode }, |
6992 | { Bad_Opcode }, |
7395 | { Bad_Opcode }, |
6993 | { Bad_Opcode }, |
7396 | { Bad_Opcode }, |
6994 | { Bad_Opcode }, |
7397 | { Bad_Opcode }, |
6995 | { Bad_Opcode }, |
7398 | { Bad_Opcode }, |
6996 | /* 88 */ |
7399 | /* 88 */ |
6997 | { Bad_Opcode }, |
7400 | { Bad_Opcode }, |
6998 | { Bad_Opcode }, |
7401 | { Bad_Opcode }, |
6999 | { Bad_Opcode }, |
7402 | { Bad_Opcode }, |
7000 | { Bad_Opcode }, |
7403 | { Bad_Opcode }, |
7001 | { Bad_Opcode }, |
7404 | { Bad_Opcode }, |
7002 | { Bad_Opcode }, |
7405 | { Bad_Opcode }, |
7003 | { Bad_Opcode }, |
7406 | { Bad_Opcode }, |
7004 | { Bad_Opcode }, |
7407 | { Bad_Opcode }, |
7005 | /* 90 */ |
7408 | /* 90 */ |
7006 | { Bad_Opcode }, |
7409 | { Bad_Opcode }, |
7007 | { Bad_Opcode }, |
7410 | { Bad_Opcode }, |
7008 | { Bad_Opcode }, |
7411 | { Bad_Opcode }, |
7009 | { Bad_Opcode }, |
7412 | { Bad_Opcode }, |
7010 | { Bad_Opcode }, |
7413 | { Bad_Opcode }, |
7011 | { Bad_Opcode }, |
7414 | { Bad_Opcode }, |
7012 | { Bad_Opcode }, |
7415 | { Bad_Opcode }, |
7013 | { Bad_Opcode }, |
7416 | { Bad_Opcode }, |
7014 | /* 98 */ |
7417 | /* 98 */ |
7015 | { Bad_Opcode }, |
7418 | { Bad_Opcode }, |
7016 | { Bad_Opcode }, |
7419 | { Bad_Opcode }, |
7017 | { Bad_Opcode }, |
7420 | { Bad_Opcode }, |
7018 | { Bad_Opcode }, |
7421 | { Bad_Opcode }, |
7019 | { Bad_Opcode }, |
7422 | { Bad_Opcode }, |
7020 | { Bad_Opcode }, |
7423 | { Bad_Opcode }, |
7021 | { Bad_Opcode }, |
7424 | { Bad_Opcode }, |
7022 | { Bad_Opcode }, |
7425 | { Bad_Opcode }, |
7023 | /* a0 */ |
7426 | /* a0 */ |
7024 | { Bad_Opcode }, |
7427 | { Bad_Opcode }, |
7025 | { Bad_Opcode }, |
7428 | { Bad_Opcode }, |
7026 | { Bad_Opcode }, |
7429 | { Bad_Opcode }, |
7027 | { Bad_Opcode }, |
7430 | { Bad_Opcode }, |
7028 | { Bad_Opcode }, |
7431 | { Bad_Opcode }, |
7029 | { Bad_Opcode }, |
7432 | { Bad_Opcode }, |
7030 | { Bad_Opcode }, |
7433 | { Bad_Opcode }, |
7031 | { Bad_Opcode }, |
7434 | { Bad_Opcode }, |
7032 | /* a8 */ |
7435 | /* a8 */ |
7033 | { Bad_Opcode }, |
7436 | { Bad_Opcode }, |
7034 | { Bad_Opcode }, |
7437 | { Bad_Opcode }, |
7035 | { Bad_Opcode }, |
7438 | { Bad_Opcode }, |
7036 | { Bad_Opcode }, |
7439 | { Bad_Opcode }, |
7037 | { Bad_Opcode }, |
7440 | { Bad_Opcode }, |
7038 | { Bad_Opcode }, |
7441 | { Bad_Opcode }, |
7039 | { Bad_Opcode }, |
7442 | { Bad_Opcode }, |
7040 | { Bad_Opcode }, |
7443 | { Bad_Opcode }, |
7041 | /* b0 */ |
7444 | /* b0 */ |
7042 | { Bad_Opcode }, |
7445 | { Bad_Opcode }, |
7043 | { Bad_Opcode }, |
7446 | { Bad_Opcode }, |
7044 | { Bad_Opcode }, |
7447 | { Bad_Opcode }, |
7045 | { Bad_Opcode }, |
7448 | { Bad_Opcode }, |
7046 | { Bad_Opcode }, |
7449 | { Bad_Opcode }, |
7047 | { Bad_Opcode }, |
7450 | { Bad_Opcode }, |
7048 | { Bad_Opcode }, |
7451 | { Bad_Opcode }, |
7049 | { Bad_Opcode }, |
7452 | { Bad_Opcode }, |
7050 | /* b8 */ |
7453 | /* b8 */ |
7051 | { Bad_Opcode }, |
7454 | { Bad_Opcode }, |
7052 | { Bad_Opcode }, |
7455 | { Bad_Opcode }, |
7053 | { Bad_Opcode }, |
7456 | { Bad_Opcode }, |
7054 | { Bad_Opcode }, |
7457 | { Bad_Opcode }, |
7055 | { Bad_Opcode }, |
7458 | { Bad_Opcode }, |
7056 | { Bad_Opcode }, |
7459 | { Bad_Opcode }, |
7057 | { Bad_Opcode }, |
7460 | { Bad_Opcode }, |
7058 | { Bad_Opcode }, |
7461 | { Bad_Opcode }, |
7059 | /* c0 */ |
7462 | /* c0 */ |
7060 | { Bad_Opcode }, |
7463 | { Bad_Opcode }, |
7061 | { Bad_Opcode }, |
7464 | { Bad_Opcode }, |
7062 | { Bad_Opcode }, |
7465 | { Bad_Opcode }, |
7063 | { Bad_Opcode }, |
7466 | { Bad_Opcode }, |
7064 | { Bad_Opcode }, |
7467 | { Bad_Opcode }, |
7065 | { Bad_Opcode }, |
7468 | { Bad_Opcode }, |
7066 | { Bad_Opcode }, |
7469 | { Bad_Opcode }, |
7067 | { Bad_Opcode }, |
7470 | { Bad_Opcode }, |
7068 | /* c8 */ |
7471 | /* c8 */ |
7069 | { Bad_Opcode }, |
7472 | { Bad_Opcode }, |
7070 | { Bad_Opcode }, |
7473 | { Bad_Opcode }, |
7071 | { Bad_Opcode }, |
7474 | { Bad_Opcode }, |
7072 | { Bad_Opcode }, |
7475 | { Bad_Opcode }, |
7073 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
7476 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
7074 | { Bad_Opcode }, |
7477 | { Bad_Opcode }, |
7075 | { Bad_Opcode }, |
7478 | { Bad_Opcode }, |
7076 | { Bad_Opcode }, |
7479 | { Bad_Opcode }, |
7077 | /* d0 */ |
7480 | /* d0 */ |
7078 | { Bad_Opcode }, |
7481 | { Bad_Opcode }, |
7079 | { Bad_Opcode }, |
7482 | { Bad_Opcode }, |
7080 | { Bad_Opcode }, |
7483 | { Bad_Opcode }, |
7081 | { Bad_Opcode }, |
7484 | { Bad_Opcode }, |
7082 | { Bad_Opcode }, |
7485 | { Bad_Opcode }, |
7083 | { Bad_Opcode }, |
7486 | { Bad_Opcode }, |
7084 | { Bad_Opcode }, |
7487 | { Bad_Opcode }, |
7085 | { Bad_Opcode }, |
7488 | { Bad_Opcode }, |
7086 | /* d8 */ |
7489 | /* d8 */ |
7087 | { Bad_Opcode }, |
7490 | { Bad_Opcode }, |
7088 | { Bad_Opcode }, |
7491 | { Bad_Opcode }, |
7089 | { Bad_Opcode }, |
7492 | { Bad_Opcode }, |
7090 | { Bad_Opcode }, |
7493 | { Bad_Opcode }, |
7091 | { Bad_Opcode }, |
7494 | { Bad_Opcode }, |
7092 | { Bad_Opcode }, |
7495 | { Bad_Opcode }, |
7093 | { Bad_Opcode }, |
7496 | { Bad_Opcode }, |
7094 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7497 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7095 | /* e0 */ |
7498 | /* e0 */ |
7096 | { Bad_Opcode }, |
7499 | { Bad_Opcode }, |
7097 | { Bad_Opcode }, |
7500 | { Bad_Opcode }, |
7098 | { Bad_Opcode }, |
7501 | { Bad_Opcode }, |
7099 | { Bad_Opcode }, |
7502 | { Bad_Opcode }, |
7100 | { Bad_Opcode }, |
7503 | { Bad_Opcode }, |
7101 | { Bad_Opcode }, |
7504 | { Bad_Opcode }, |
7102 | { Bad_Opcode }, |
7505 | { Bad_Opcode }, |
7103 | { Bad_Opcode }, |
7506 | { Bad_Opcode }, |
7104 | /* e8 */ |
7507 | /* e8 */ |
7105 | { Bad_Opcode }, |
7508 | { Bad_Opcode }, |
7106 | { Bad_Opcode }, |
7509 | { Bad_Opcode }, |
7107 | { Bad_Opcode }, |
7510 | { Bad_Opcode }, |
7108 | { Bad_Opcode }, |
7511 | { Bad_Opcode }, |
7109 | { Bad_Opcode }, |
7512 | { Bad_Opcode }, |
7110 | { Bad_Opcode }, |
7513 | { Bad_Opcode }, |
7111 | { Bad_Opcode }, |
7514 | { Bad_Opcode }, |
7112 | { Bad_Opcode }, |
7515 | { Bad_Opcode }, |
7113 | /* f0 */ |
7516 | /* f0 */ |
7114 | { Bad_Opcode }, |
7517 | { Bad_Opcode }, |
7115 | { Bad_Opcode }, |
7518 | { Bad_Opcode }, |
7116 | { Bad_Opcode }, |
7519 | { Bad_Opcode }, |
7117 | { Bad_Opcode }, |
7520 | { Bad_Opcode }, |
7118 | { Bad_Opcode }, |
7521 | { Bad_Opcode }, |
7119 | { Bad_Opcode }, |
7522 | { Bad_Opcode }, |
7120 | { Bad_Opcode }, |
7523 | { Bad_Opcode }, |
7121 | { Bad_Opcode }, |
7524 | { Bad_Opcode }, |
7122 | /* f8 */ |
7525 | /* f8 */ |
7123 | { Bad_Opcode }, |
7526 | { Bad_Opcode }, |
7124 | { Bad_Opcode }, |
7527 | { Bad_Opcode }, |
7125 | { Bad_Opcode }, |
7528 | { Bad_Opcode }, |
7126 | { Bad_Opcode }, |
7529 | { Bad_Opcode }, |
7127 | { Bad_Opcode }, |
7530 | { Bad_Opcode }, |
7128 | { Bad_Opcode }, |
7531 | { Bad_Opcode }, |
7129 | { Bad_Opcode }, |
7532 | { Bad_Opcode }, |
7130 | { Bad_Opcode }, |
7533 | { Bad_Opcode }, |
7131 | }, |
7534 | }, |
7132 | 7535 | ||
7133 | /* THREE_BYTE_0F7A */ |
7536 | /* THREE_BYTE_0F7A */ |
7134 | { |
7537 | { |
7135 | /* 00 */ |
7538 | /* 00 */ |
7136 | { Bad_Opcode }, |
7539 | { Bad_Opcode }, |
7137 | { Bad_Opcode }, |
7540 | { Bad_Opcode }, |
7138 | { Bad_Opcode }, |
7541 | { Bad_Opcode }, |
7139 | { Bad_Opcode }, |
7542 | { Bad_Opcode }, |
7140 | { Bad_Opcode }, |
7543 | { Bad_Opcode }, |
7141 | { Bad_Opcode }, |
7544 | { Bad_Opcode }, |
7142 | { Bad_Opcode }, |
7545 | { Bad_Opcode }, |
7143 | { Bad_Opcode }, |
7546 | { Bad_Opcode }, |
7144 | /* 08 */ |
7547 | /* 08 */ |
7145 | { Bad_Opcode }, |
7548 | { Bad_Opcode }, |
7146 | { Bad_Opcode }, |
7549 | { Bad_Opcode }, |
7147 | { Bad_Opcode }, |
7550 | { Bad_Opcode }, |
7148 | { Bad_Opcode }, |
7551 | { Bad_Opcode }, |
7149 | { Bad_Opcode }, |
7552 | { Bad_Opcode }, |
7150 | { Bad_Opcode }, |
7553 | { Bad_Opcode }, |
7151 | { Bad_Opcode }, |
7554 | { Bad_Opcode }, |
7152 | { Bad_Opcode }, |
7555 | { Bad_Opcode }, |
7153 | /* 10 */ |
7556 | /* 10 */ |
7154 | { Bad_Opcode }, |
7557 | { Bad_Opcode }, |
7155 | { Bad_Opcode }, |
7558 | { Bad_Opcode }, |
7156 | { Bad_Opcode }, |
7559 | { Bad_Opcode }, |
7157 | { Bad_Opcode }, |
7560 | { Bad_Opcode }, |
7158 | { Bad_Opcode }, |
7561 | { Bad_Opcode }, |
7159 | { Bad_Opcode }, |
7562 | { Bad_Opcode }, |
7160 | { Bad_Opcode }, |
7563 | { Bad_Opcode }, |
7161 | { Bad_Opcode }, |
7564 | { Bad_Opcode }, |
7162 | /* 18 */ |
7565 | /* 18 */ |
7163 | { Bad_Opcode }, |
7566 | { Bad_Opcode }, |
7164 | { Bad_Opcode }, |
7567 | { Bad_Opcode }, |
7165 | { Bad_Opcode }, |
7568 | { Bad_Opcode }, |
7166 | { Bad_Opcode }, |
7569 | { Bad_Opcode }, |
7167 | { Bad_Opcode }, |
7570 | { Bad_Opcode }, |
7168 | { Bad_Opcode }, |
7571 | { Bad_Opcode }, |
7169 | { Bad_Opcode }, |
7572 | { Bad_Opcode }, |
7170 | { Bad_Opcode }, |
7573 | { Bad_Opcode }, |
7171 | /* 20 */ |
7574 | /* 20 */ |
7172 | { "ptest", { XX } }, |
7575 | { "ptest", { XX }, PREFIX_OPCODE }, |
7173 | { Bad_Opcode }, |
7576 | { Bad_Opcode }, |
7174 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, |
7175 | { Bad_Opcode }, |
7578 | { Bad_Opcode }, |
7176 | { Bad_Opcode }, |
7579 | { Bad_Opcode }, |
7177 | { Bad_Opcode }, |
7580 | { Bad_Opcode }, |
7178 | { Bad_Opcode }, |
7581 | { Bad_Opcode }, |
7179 | { Bad_Opcode }, |
7582 | { Bad_Opcode }, |
7180 | /* 28 */ |
7583 | /* 28 */ |
7181 | { Bad_Opcode }, |
7584 | { Bad_Opcode }, |
7182 | { Bad_Opcode }, |
7585 | { Bad_Opcode }, |
7183 | { Bad_Opcode }, |
7586 | { Bad_Opcode }, |
7184 | { Bad_Opcode }, |
7587 | { Bad_Opcode }, |
7185 | { Bad_Opcode }, |
7588 | { Bad_Opcode }, |
7186 | { Bad_Opcode }, |
7589 | { Bad_Opcode }, |
7187 | { Bad_Opcode }, |
7590 | { Bad_Opcode }, |
7188 | { Bad_Opcode }, |
7591 | { Bad_Opcode }, |
7189 | /* 30 */ |
7592 | /* 30 */ |
7190 | { Bad_Opcode }, |
7593 | { Bad_Opcode }, |
7191 | { Bad_Opcode }, |
7594 | { Bad_Opcode }, |
7192 | { Bad_Opcode }, |
7595 | { Bad_Opcode }, |
7193 | { Bad_Opcode }, |
7596 | { Bad_Opcode }, |
7194 | { Bad_Opcode }, |
7597 | { Bad_Opcode }, |
7195 | { Bad_Opcode }, |
7598 | { Bad_Opcode }, |
7196 | { Bad_Opcode }, |
7599 | { Bad_Opcode }, |
7197 | { Bad_Opcode }, |
7600 | { Bad_Opcode }, |
7198 | /* 38 */ |
7601 | /* 38 */ |
7199 | { Bad_Opcode }, |
7602 | { Bad_Opcode }, |
7200 | { Bad_Opcode }, |
7603 | { Bad_Opcode }, |
7201 | { Bad_Opcode }, |
7604 | { Bad_Opcode }, |
7202 | { Bad_Opcode }, |
7605 | { Bad_Opcode }, |
7203 | { Bad_Opcode }, |
7606 | { Bad_Opcode }, |
7204 | { Bad_Opcode }, |
7607 | { Bad_Opcode }, |
7205 | { Bad_Opcode }, |
7608 | { Bad_Opcode }, |
7206 | { Bad_Opcode }, |
7609 | { Bad_Opcode }, |
7207 | /* 40 */ |
7610 | /* 40 */ |
7208 | { Bad_Opcode }, |
7611 | { Bad_Opcode }, |
7209 | { "phaddbw", { XM, EXq } }, |
7612 | { "phaddbw", { XM, EXq }, PREFIX_OPCODE }, |
7210 | { "phaddbd", { XM, EXq } }, |
7613 | { "phaddbd", { XM, EXq }, PREFIX_OPCODE }, |
7211 | { "phaddbq", { XM, EXq } }, |
7614 | { "phaddbq", { XM, EXq }, PREFIX_OPCODE }, |
7212 | { Bad_Opcode }, |
7615 | { Bad_Opcode }, |
7213 | { Bad_Opcode }, |
7616 | { Bad_Opcode }, |
7214 | { "phaddwd", { XM, EXq } }, |
7617 | { "phaddwd", { XM, EXq }, PREFIX_OPCODE }, |
7215 | { "phaddwq", { XM, EXq } }, |
7618 | { "phaddwq", { XM, EXq }, PREFIX_OPCODE }, |
7216 | /* 48 */ |
7619 | /* 48 */ |
7217 | { Bad_Opcode }, |
7620 | { Bad_Opcode }, |
7218 | { Bad_Opcode }, |
7621 | { Bad_Opcode }, |
7219 | { Bad_Opcode }, |
7622 | { Bad_Opcode }, |
7220 | { "phadddq", { XM, EXq } }, |
7623 | { "phadddq", { XM, EXq }, PREFIX_OPCODE }, |
7221 | { Bad_Opcode }, |
7624 | { Bad_Opcode }, |
7222 | { Bad_Opcode }, |
7625 | { Bad_Opcode }, |
7223 | { Bad_Opcode }, |
7626 | { Bad_Opcode }, |
7224 | { Bad_Opcode }, |
7627 | { Bad_Opcode }, |
7225 | /* 50 */ |
7628 | /* 50 */ |
7226 | { Bad_Opcode }, |
7629 | { Bad_Opcode }, |
7227 | { "phaddubw", { XM, EXq } }, |
7630 | { "phaddubw", { XM, EXq }, PREFIX_OPCODE }, |
7228 | { "phaddubd", { XM, EXq } }, |
7631 | { "phaddubd", { XM, EXq }, PREFIX_OPCODE }, |
7229 | { "phaddubq", { XM, EXq } }, |
7632 | { "phaddubq", { XM, EXq }, PREFIX_OPCODE }, |
7230 | { Bad_Opcode }, |
7633 | { Bad_Opcode }, |
7231 | { Bad_Opcode }, |
7634 | { Bad_Opcode }, |
7232 | { "phadduwd", { XM, EXq } }, |
7635 | { "phadduwd", { XM, EXq }, PREFIX_OPCODE }, |
7233 | { "phadduwq", { XM, EXq } }, |
7636 | { "phadduwq", { XM, EXq }, PREFIX_OPCODE }, |
7234 | /* 58 */ |
7637 | /* 58 */ |
7235 | { Bad_Opcode }, |
7638 | { Bad_Opcode }, |
7236 | { Bad_Opcode }, |
7639 | { Bad_Opcode }, |
7237 | { Bad_Opcode }, |
7640 | { Bad_Opcode }, |
7238 | { "phaddudq", { XM, EXq } }, |
7641 | { "phaddudq", { XM, EXq }, PREFIX_OPCODE }, |
7239 | { Bad_Opcode }, |
7642 | { Bad_Opcode }, |
7240 | { Bad_Opcode }, |
7643 | { Bad_Opcode }, |
7241 | { Bad_Opcode }, |
7644 | { Bad_Opcode }, |
7242 | { Bad_Opcode }, |
7645 | { Bad_Opcode }, |
7243 | /* 60 */ |
7646 | /* 60 */ |
7244 | { Bad_Opcode }, |
7647 | { Bad_Opcode }, |
7245 | { "phsubbw", { XM, EXq } }, |
7648 | { "phsubbw", { XM, EXq }, PREFIX_OPCODE }, |
7246 | { "phsubbd", { XM, EXq } }, |
7649 | { "phsubbd", { XM, EXq }, PREFIX_OPCODE }, |
7247 | { "phsubbq", { XM, EXq } }, |
7650 | { "phsubbq", { XM, EXq }, PREFIX_OPCODE }, |
7248 | { Bad_Opcode }, |
7651 | { Bad_Opcode }, |
7249 | { Bad_Opcode }, |
7652 | { Bad_Opcode }, |
7250 | { Bad_Opcode }, |
7653 | { Bad_Opcode }, |
7251 | { Bad_Opcode }, |
7654 | { Bad_Opcode }, |
7252 | /* 68 */ |
7655 | /* 68 */ |
7253 | { Bad_Opcode }, |
7656 | { Bad_Opcode }, |
7254 | { Bad_Opcode }, |
7657 | { Bad_Opcode }, |
7255 | { Bad_Opcode }, |
7658 | { Bad_Opcode }, |
7256 | { Bad_Opcode }, |
7659 | { Bad_Opcode }, |
7257 | { Bad_Opcode }, |
7660 | { Bad_Opcode }, |
7258 | { Bad_Opcode }, |
7661 | { Bad_Opcode }, |
7259 | { Bad_Opcode }, |
7662 | { Bad_Opcode }, |
7260 | { Bad_Opcode }, |
7663 | { Bad_Opcode }, |
7261 | /* 70 */ |
7664 | /* 70 */ |
7262 | { Bad_Opcode }, |
7665 | { Bad_Opcode }, |
7263 | { Bad_Opcode }, |
7666 | { Bad_Opcode }, |
7264 | { Bad_Opcode }, |
7667 | { Bad_Opcode }, |
7265 | { Bad_Opcode }, |
7668 | { Bad_Opcode }, |
7266 | { Bad_Opcode }, |
7669 | { Bad_Opcode }, |
7267 | { Bad_Opcode }, |
7670 | { Bad_Opcode }, |
7268 | { Bad_Opcode }, |
7671 | { Bad_Opcode }, |
7269 | { Bad_Opcode }, |
7672 | { Bad_Opcode }, |
7270 | /* 78 */ |
7673 | /* 78 */ |
7271 | { Bad_Opcode }, |
7674 | { Bad_Opcode }, |
7272 | { Bad_Opcode }, |
7675 | { Bad_Opcode }, |
7273 | { Bad_Opcode }, |
7676 | { Bad_Opcode }, |
7274 | { Bad_Opcode }, |
7677 | { Bad_Opcode }, |
7275 | { Bad_Opcode }, |
7678 | { Bad_Opcode }, |
7276 | { Bad_Opcode }, |
7679 | { Bad_Opcode }, |
7277 | { Bad_Opcode }, |
7680 | { Bad_Opcode }, |
7278 | { Bad_Opcode }, |
7681 | { Bad_Opcode }, |
7279 | /* 80 */ |
7682 | /* 80 */ |
7280 | { Bad_Opcode }, |
7683 | { Bad_Opcode }, |
7281 | { Bad_Opcode }, |
7684 | { Bad_Opcode }, |
7282 | { Bad_Opcode }, |
7685 | { Bad_Opcode }, |
7283 | { Bad_Opcode }, |
7686 | { Bad_Opcode }, |
7284 | { Bad_Opcode }, |
7687 | { Bad_Opcode }, |
7285 | { Bad_Opcode }, |
7688 | { Bad_Opcode }, |
7286 | { Bad_Opcode }, |
7689 | { Bad_Opcode }, |
7287 | { Bad_Opcode }, |
7690 | { Bad_Opcode }, |
7288 | /* 88 */ |
7691 | /* 88 */ |
7289 | { Bad_Opcode }, |
7692 | { Bad_Opcode }, |
7290 | { Bad_Opcode }, |
7693 | { Bad_Opcode }, |
7291 | { Bad_Opcode }, |
7694 | { Bad_Opcode }, |
7292 | { Bad_Opcode }, |
7695 | { Bad_Opcode }, |
7293 | { Bad_Opcode }, |
7696 | { Bad_Opcode }, |
7294 | { Bad_Opcode }, |
7697 | { Bad_Opcode }, |
7295 | { Bad_Opcode }, |
7698 | { Bad_Opcode }, |
7296 | { Bad_Opcode }, |
7699 | { Bad_Opcode }, |
7297 | /* 90 */ |
7700 | /* 90 */ |
7298 | { Bad_Opcode }, |
7701 | { Bad_Opcode }, |
7299 | { Bad_Opcode }, |
7702 | { Bad_Opcode }, |
7300 | { Bad_Opcode }, |
7703 | { Bad_Opcode }, |
7301 | { Bad_Opcode }, |
7704 | { Bad_Opcode }, |
7302 | { Bad_Opcode }, |
7705 | { Bad_Opcode }, |
7303 | { Bad_Opcode }, |
7706 | { Bad_Opcode }, |
7304 | { Bad_Opcode }, |
7707 | { Bad_Opcode }, |
7305 | { Bad_Opcode }, |
7708 | { Bad_Opcode }, |
7306 | /* 98 */ |
7709 | /* 98 */ |
7307 | { Bad_Opcode }, |
7710 | { Bad_Opcode }, |
7308 | { Bad_Opcode }, |
7711 | { Bad_Opcode }, |
7309 | { Bad_Opcode }, |
7712 | { Bad_Opcode }, |
7310 | { Bad_Opcode }, |
7713 | { Bad_Opcode }, |
7311 | { Bad_Opcode }, |
7714 | { Bad_Opcode }, |
7312 | { Bad_Opcode }, |
7715 | { Bad_Opcode }, |
7313 | { Bad_Opcode }, |
7716 | { Bad_Opcode }, |
7314 | { Bad_Opcode }, |
7717 | { Bad_Opcode }, |
7315 | /* a0 */ |
7718 | /* a0 */ |
7316 | { Bad_Opcode }, |
7719 | { Bad_Opcode }, |
7317 | { Bad_Opcode }, |
7720 | { Bad_Opcode }, |
7318 | { Bad_Opcode }, |
7721 | { Bad_Opcode }, |
7319 | { Bad_Opcode }, |
7722 | { Bad_Opcode }, |
7320 | { Bad_Opcode }, |
7723 | { Bad_Opcode }, |
7321 | { Bad_Opcode }, |
7724 | { Bad_Opcode }, |
7322 | { Bad_Opcode }, |
7725 | { Bad_Opcode }, |
7323 | { Bad_Opcode }, |
7726 | { Bad_Opcode }, |
7324 | /* a8 */ |
7727 | /* a8 */ |
7325 | { Bad_Opcode }, |
7728 | { Bad_Opcode }, |
7326 | { Bad_Opcode }, |
7729 | { Bad_Opcode }, |
7327 | { Bad_Opcode }, |
7730 | { Bad_Opcode }, |
7328 | { Bad_Opcode }, |
7731 | { Bad_Opcode }, |
7329 | { Bad_Opcode }, |
7732 | { Bad_Opcode }, |
7330 | { Bad_Opcode }, |
7733 | { Bad_Opcode }, |
7331 | { Bad_Opcode }, |
7734 | { Bad_Opcode }, |
7332 | { Bad_Opcode }, |
7735 | { Bad_Opcode }, |
7333 | /* b0 */ |
7736 | /* b0 */ |
7334 | { Bad_Opcode }, |
7737 | { Bad_Opcode }, |
7335 | { Bad_Opcode }, |
7738 | { Bad_Opcode }, |
7336 | { Bad_Opcode }, |
7739 | { Bad_Opcode }, |
7337 | { Bad_Opcode }, |
7740 | { Bad_Opcode }, |
7338 | { Bad_Opcode }, |
7741 | { Bad_Opcode }, |
7339 | { Bad_Opcode }, |
7742 | { Bad_Opcode }, |
7340 | { Bad_Opcode }, |
7743 | { Bad_Opcode }, |
7341 | { Bad_Opcode }, |
7744 | { Bad_Opcode }, |
7342 | /* b8 */ |
7745 | /* b8 */ |
7343 | { Bad_Opcode }, |
7746 | { Bad_Opcode }, |
7344 | { Bad_Opcode }, |
7747 | { Bad_Opcode }, |
7345 | { Bad_Opcode }, |
7748 | { Bad_Opcode }, |
7346 | { Bad_Opcode }, |
7749 | { Bad_Opcode }, |
7347 | { Bad_Opcode }, |
7750 | { Bad_Opcode }, |
7348 | { Bad_Opcode }, |
7751 | { Bad_Opcode }, |
7349 | { Bad_Opcode }, |
7752 | { Bad_Opcode }, |
7350 | { Bad_Opcode }, |
7753 | { Bad_Opcode }, |
7351 | /* c0 */ |
7754 | /* c0 */ |
7352 | { Bad_Opcode }, |
7755 | { Bad_Opcode }, |
7353 | { Bad_Opcode }, |
7756 | { Bad_Opcode }, |
7354 | { Bad_Opcode }, |
7757 | { Bad_Opcode }, |
7355 | { Bad_Opcode }, |
7758 | { Bad_Opcode }, |
7356 | { Bad_Opcode }, |
7759 | { Bad_Opcode }, |
7357 | { Bad_Opcode }, |
7760 | { Bad_Opcode }, |
7358 | { Bad_Opcode }, |
7761 | { Bad_Opcode }, |
7359 | { Bad_Opcode }, |
7762 | { Bad_Opcode }, |
7360 | /* c8 */ |
7763 | /* c8 */ |
7361 | { Bad_Opcode }, |
7764 | { Bad_Opcode }, |
7362 | { Bad_Opcode }, |
7765 | { Bad_Opcode }, |
7363 | { Bad_Opcode }, |
7766 | { Bad_Opcode }, |
7364 | { Bad_Opcode }, |
7767 | { Bad_Opcode }, |
7365 | { Bad_Opcode }, |
7768 | { Bad_Opcode }, |
7366 | { Bad_Opcode }, |
7769 | { Bad_Opcode }, |
7367 | { Bad_Opcode }, |
7770 | { Bad_Opcode }, |
7368 | { Bad_Opcode }, |
7771 | { Bad_Opcode }, |
7369 | /* d0 */ |
7772 | /* d0 */ |
7370 | { Bad_Opcode }, |
7773 | { Bad_Opcode }, |
7371 | { Bad_Opcode }, |
7774 | { Bad_Opcode }, |
7372 | { Bad_Opcode }, |
7775 | { Bad_Opcode }, |
7373 | { Bad_Opcode }, |
7776 | { Bad_Opcode }, |
7374 | { Bad_Opcode }, |
7777 | { Bad_Opcode }, |
7375 | { Bad_Opcode }, |
7778 | { Bad_Opcode }, |
7376 | { Bad_Opcode }, |
7779 | { Bad_Opcode }, |
7377 | { Bad_Opcode }, |
7780 | { Bad_Opcode }, |
7378 | /* d8 */ |
7781 | /* d8 */ |
7379 | { Bad_Opcode }, |
7782 | { Bad_Opcode }, |
7380 | { Bad_Opcode }, |
7783 | { Bad_Opcode }, |
7381 | { Bad_Opcode }, |
7784 | { Bad_Opcode }, |
7382 | { Bad_Opcode }, |
7785 | { Bad_Opcode }, |
7383 | { Bad_Opcode }, |
7786 | { Bad_Opcode }, |
7384 | { Bad_Opcode }, |
7787 | { Bad_Opcode }, |
7385 | { Bad_Opcode }, |
7788 | { Bad_Opcode }, |
7386 | { Bad_Opcode }, |
7789 | { Bad_Opcode }, |
7387 | /* e0 */ |
7790 | /* e0 */ |
7388 | { Bad_Opcode }, |
7791 | { Bad_Opcode }, |
7389 | { Bad_Opcode }, |
7792 | { Bad_Opcode }, |
7390 | { Bad_Opcode }, |
7793 | { Bad_Opcode }, |
7391 | { Bad_Opcode }, |
7794 | { Bad_Opcode }, |
7392 | { Bad_Opcode }, |
7795 | { Bad_Opcode }, |
7393 | { Bad_Opcode }, |
7796 | { Bad_Opcode }, |
7394 | { Bad_Opcode }, |
7797 | { Bad_Opcode }, |
7395 | { Bad_Opcode }, |
7798 | { Bad_Opcode }, |
7396 | /* e8 */ |
7799 | /* e8 */ |
7397 | { Bad_Opcode }, |
7800 | { Bad_Opcode }, |
7398 | { Bad_Opcode }, |
7801 | { Bad_Opcode }, |
7399 | { Bad_Opcode }, |
7802 | { Bad_Opcode }, |
7400 | { Bad_Opcode }, |
7803 | { Bad_Opcode }, |
7401 | { Bad_Opcode }, |
7804 | { Bad_Opcode }, |
7402 | { Bad_Opcode }, |
7805 | { Bad_Opcode }, |
7403 | { Bad_Opcode }, |
7806 | { Bad_Opcode }, |
7404 | { Bad_Opcode }, |
7807 | { Bad_Opcode }, |
7405 | /* f0 */ |
7808 | /* f0 */ |
7406 | { Bad_Opcode }, |
7809 | { Bad_Opcode }, |
7407 | { Bad_Opcode }, |
7810 | { Bad_Opcode }, |
7408 | { Bad_Opcode }, |
7811 | { Bad_Opcode }, |
7409 | { Bad_Opcode }, |
7812 | { Bad_Opcode }, |
7410 | { Bad_Opcode }, |
7813 | { Bad_Opcode }, |
7411 | { Bad_Opcode }, |
7814 | { Bad_Opcode }, |
7412 | { Bad_Opcode }, |
7815 | { Bad_Opcode }, |
7413 | { Bad_Opcode }, |
7816 | { Bad_Opcode }, |
7414 | /* f8 */ |
7817 | /* f8 */ |
7415 | { Bad_Opcode }, |
7818 | { Bad_Opcode }, |
7416 | { Bad_Opcode }, |
7819 | { Bad_Opcode }, |
7417 | { Bad_Opcode }, |
7820 | { Bad_Opcode }, |
7418 | { Bad_Opcode }, |
7821 | { Bad_Opcode }, |
7419 | { Bad_Opcode }, |
7822 | { Bad_Opcode }, |
7420 | { Bad_Opcode }, |
7823 | { Bad_Opcode }, |
7421 | { Bad_Opcode }, |
7824 | { Bad_Opcode }, |
7422 | { Bad_Opcode }, |
7825 | { Bad_Opcode }, |
7423 | }, |
7826 | }, |
7424 | }; |
7827 | }; |
7425 | 7828 | ||
7426 | static const struct dis386 xop_table[][256] = { |
7829 | static const struct dis386 xop_table[][256] = { |
7427 | /* XOP_08 */ |
7830 | /* XOP_08 */ |
7428 | { |
7831 | { |
7429 | /* 00 */ |
7832 | /* 00 */ |
7430 | { Bad_Opcode }, |
7833 | { Bad_Opcode }, |
7431 | { Bad_Opcode }, |
7834 | { Bad_Opcode }, |
7432 | { Bad_Opcode }, |
7835 | { Bad_Opcode }, |
7433 | { Bad_Opcode }, |
7836 | { Bad_Opcode }, |
7434 | { Bad_Opcode }, |
7837 | { Bad_Opcode }, |
7435 | { Bad_Opcode }, |
7838 | { Bad_Opcode }, |
7436 | { Bad_Opcode }, |
7839 | { Bad_Opcode }, |
7437 | { Bad_Opcode }, |
7840 | { Bad_Opcode }, |
7438 | /* 08 */ |
7841 | /* 08 */ |
7439 | { Bad_Opcode }, |
7842 | { Bad_Opcode }, |
7440 | { Bad_Opcode }, |
7843 | { Bad_Opcode }, |
7441 | { Bad_Opcode }, |
7844 | { Bad_Opcode }, |
7442 | { Bad_Opcode }, |
7845 | { Bad_Opcode }, |
7443 | { Bad_Opcode }, |
7846 | { Bad_Opcode }, |
7444 | { Bad_Opcode }, |
7847 | { Bad_Opcode }, |
7445 | { Bad_Opcode }, |
7848 | { Bad_Opcode }, |
7446 | { Bad_Opcode }, |
7849 | { Bad_Opcode }, |
7447 | /* 10 */ |
7850 | /* 10 */ |
7448 | { Bad_Opcode }, |
7851 | { Bad_Opcode }, |
7449 | { Bad_Opcode }, |
7852 | { Bad_Opcode }, |
7450 | { Bad_Opcode }, |
7853 | { Bad_Opcode }, |
7451 | { Bad_Opcode }, |
7854 | { Bad_Opcode }, |
7452 | { Bad_Opcode }, |
7855 | { Bad_Opcode }, |
7453 | { Bad_Opcode }, |
7856 | { Bad_Opcode }, |
7454 | { Bad_Opcode }, |
7857 | { Bad_Opcode }, |
7455 | { Bad_Opcode }, |
7858 | { Bad_Opcode }, |
7456 | /* 18 */ |
7859 | /* 18 */ |
7457 | { Bad_Opcode }, |
7860 | { Bad_Opcode }, |
7458 | { Bad_Opcode }, |
7861 | { Bad_Opcode }, |
7459 | { Bad_Opcode }, |
7862 | { Bad_Opcode }, |
7460 | { Bad_Opcode }, |
7863 | { Bad_Opcode }, |
7461 | { Bad_Opcode }, |
7864 | { Bad_Opcode }, |
7462 | { Bad_Opcode }, |
7865 | { Bad_Opcode }, |
7463 | { Bad_Opcode }, |
7866 | { Bad_Opcode }, |
7464 | { Bad_Opcode }, |
7867 | { Bad_Opcode }, |
7465 | /* 20 */ |
7868 | /* 20 */ |
7466 | { Bad_Opcode }, |
7869 | { Bad_Opcode }, |
7467 | { Bad_Opcode }, |
7870 | { Bad_Opcode }, |
7468 | { Bad_Opcode }, |
7871 | { Bad_Opcode }, |
7469 | { Bad_Opcode }, |
7872 | { Bad_Opcode }, |
7470 | { Bad_Opcode }, |
7873 | { Bad_Opcode }, |
7471 | { Bad_Opcode }, |
7874 | { Bad_Opcode }, |
7472 | { Bad_Opcode }, |
7875 | { Bad_Opcode }, |
7473 | { Bad_Opcode }, |
7876 | { Bad_Opcode }, |
7474 | /* 28 */ |
7877 | /* 28 */ |
7475 | { Bad_Opcode }, |
7878 | { Bad_Opcode }, |
7476 | { Bad_Opcode }, |
7879 | { Bad_Opcode }, |
7477 | { Bad_Opcode }, |
7880 | { Bad_Opcode }, |
7478 | { Bad_Opcode }, |
7881 | { Bad_Opcode }, |
7479 | { Bad_Opcode }, |
7882 | { Bad_Opcode }, |
7480 | { Bad_Opcode }, |
7883 | { Bad_Opcode }, |
7481 | { Bad_Opcode }, |
7884 | { Bad_Opcode }, |
7482 | { Bad_Opcode }, |
7885 | { Bad_Opcode }, |
7483 | /* 30 */ |
7886 | /* 30 */ |
7484 | { Bad_Opcode }, |
7887 | { Bad_Opcode }, |
7485 | { Bad_Opcode }, |
7888 | { Bad_Opcode }, |
7486 | { Bad_Opcode }, |
7889 | { Bad_Opcode }, |
7487 | { Bad_Opcode }, |
7890 | { Bad_Opcode }, |
7488 | { Bad_Opcode }, |
7891 | { Bad_Opcode }, |
7489 | { Bad_Opcode }, |
7892 | { Bad_Opcode }, |
7490 | { Bad_Opcode }, |
7893 | { Bad_Opcode }, |
7491 | { Bad_Opcode }, |
7894 | { Bad_Opcode }, |
7492 | /* 38 */ |
7895 | /* 38 */ |
7493 | { Bad_Opcode }, |
7896 | { Bad_Opcode }, |
7494 | { Bad_Opcode }, |
7897 | { Bad_Opcode }, |
7495 | { Bad_Opcode }, |
7898 | { Bad_Opcode }, |
7496 | { Bad_Opcode }, |
7899 | { Bad_Opcode }, |
7497 | { Bad_Opcode }, |
7900 | { Bad_Opcode }, |
7498 | { Bad_Opcode }, |
7901 | { Bad_Opcode }, |
7499 | { Bad_Opcode }, |
7902 | { Bad_Opcode }, |
7500 | { Bad_Opcode }, |
7903 | { Bad_Opcode }, |
7501 | /* 40 */ |
7904 | /* 40 */ |
7502 | { Bad_Opcode }, |
7905 | { Bad_Opcode }, |
7503 | { Bad_Opcode }, |
7906 | { Bad_Opcode }, |
7504 | { Bad_Opcode }, |
7907 | { Bad_Opcode }, |
7505 | { Bad_Opcode }, |
7908 | { Bad_Opcode }, |
7506 | { Bad_Opcode }, |
7909 | { Bad_Opcode }, |
7507 | { Bad_Opcode }, |
7910 | { Bad_Opcode }, |
7508 | { Bad_Opcode }, |
7911 | { Bad_Opcode }, |
7509 | { Bad_Opcode }, |
7912 | { Bad_Opcode }, |
7510 | /* 48 */ |
7913 | /* 48 */ |
7511 | { Bad_Opcode }, |
7914 | { Bad_Opcode }, |
7512 | { Bad_Opcode }, |
7915 | { Bad_Opcode }, |
7513 | { Bad_Opcode }, |
7916 | { Bad_Opcode }, |
7514 | { Bad_Opcode }, |
7917 | { Bad_Opcode }, |
7515 | { Bad_Opcode }, |
7918 | { Bad_Opcode }, |
7516 | { Bad_Opcode }, |
7919 | { Bad_Opcode }, |
7517 | { Bad_Opcode }, |
7920 | { Bad_Opcode }, |
7518 | { Bad_Opcode }, |
7921 | { Bad_Opcode }, |
7519 | /* 50 */ |
7922 | /* 50 */ |
7520 | { Bad_Opcode }, |
7923 | { Bad_Opcode }, |
7521 | { Bad_Opcode }, |
7924 | { Bad_Opcode }, |
7522 | { Bad_Opcode }, |
7925 | { Bad_Opcode }, |
7523 | { Bad_Opcode }, |
7926 | { Bad_Opcode }, |
7524 | { Bad_Opcode }, |
7927 | { Bad_Opcode }, |
7525 | { Bad_Opcode }, |
7928 | { Bad_Opcode }, |
7526 | { Bad_Opcode }, |
7929 | { Bad_Opcode }, |
7527 | { Bad_Opcode }, |
7930 | { Bad_Opcode }, |
7528 | /* 58 */ |
7931 | /* 58 */ |
7529 | { Bad_Opcode }, |
7932 | { Bad_Opcode }, |
7530 | { Bad_Opcode }, |
7933 | { Bad_Opcode }, |
7531 | { Bad_Opcode }, |
7934 | { Bad_Opcode }, |
7532 | { Bad_Opcode }, |
7935 | { Bad_Opcode }, |
7533 | { Bad_Opcode }, |
7936 | { Bad_Opcode }, |
7534 | { Bad_Opcode }, |
7937 | { Bad_Opcode }, |
7535 | { Bad_Opcode }, |
7938 | { Bad_Opcode }, |
7536 | { Bad_Opcode }, |
7939 | { Bad_Opcode }, |
7537 | /* 60 */ |
7940 | /* 60 */ |
7538 | { Bad_Opcode }, |
7941 | { Bad_Opcode }, |
7539 | { Bad_Opcode }, |
7942 | { Bad_Opcode }, |
7540 | { Bad_Opcode }, |
7943 | { Bad_Opcode }, |
7541 | { Bad_Opcode }, |
7944 | { Bad_Opcode }, |
7542 | { Bad_Opcode }, |
7945 | { Bad_Opcode }, |
7543 | { Bad_Opcode }, |
7946 | { Bad_Opcode }, |
7544 | { Bad_Opcode }, |
7947 | { Bad_Opcode }, |
7545 | { Bad_Opcode }, |
7948 | { Bad_Opcode }, |
7546 | /* 68 */ |
7949 | /* 68 */ |
7547 | { Bad_Opcode }, |
7950 | { Bad_Opcode }, |
7548 | { Bad_Opcode }, |
7951 | { Bad_Opcode }, |
7549 | { Bad_Opcode }, |
7952 | { Bad_Opcode }, |
7550 | { Bad_Opcode }, |
7953 | { Bad_Opcode }, |
7551 | { Bad_Opcode }, |
7954 | { Bad_Opcode }, |
7552 | { Bad_Opcode }, |
7955 | { Bad_Opcode }, |
7553 | { Bad_Opcode }, |
7956 | { Bad_Opcode }, |
7554 | { Bad_Opcode }, |
7957 | { Bad_Opcode }, |
7555 | /* 70 */ |
7958 | /* 70 */ |
7556 | { Bad_Opcode }, |
7959 | { Bad_Opcode }, |
7557 | { Bad_Opcode }, |
7960 | { Bad_Opcode }, |
7558 | { Bad_Opcode }, |
7961 | { Bad_Opcode }, |
7559 | { Bad_Opcode }, |
7962 | { Bad_Opcode }, |
7560 | { Bad_Opcode }, |
7963 | { Bad_Opcode }, |
7561 | { Bad_Opcode }, |
7964 | { Bad_Opcode }, |
7562 | { Bad_Opcode }, |
7965 | { Bad_Opcode }, |
7563 | { Bad_Opcode }, |
7966 | { Bad_Opcode }, |
7564 | /* 78 */ |
7967 | /* 78 */ |
7565 | { Bad_Opcode }, |
7968 | { Bad_Opcode }, |
7566 | { Bad_Opcode }, |
7969 | { Bad_Opcode }, |
7567 | { Bad_Opcode }, |
7970 | { Bad_Opcode }, |
7568 | { Bad_Opcode }, |
7971 | { Bad_Opcode }, |
7569 | { Bad_Opcode }, |
7972 | { Bad_Opcode }, |
7570 | { Bad_Opcode }, |
7973 | { Bad_Opcode }, |
7571 | { Bad_Opcode }, |
7974 | { Bad_Opcode }, |
7572 | { Bad_Opcode }, |
7975 | { Bad_Opcode }, |
7573 | /* 80 */ |
7976 | /* 80 */ |
7574 | { Bad_Opcode }, |
7977 | { Bad_Opcode }, |
7575 | { Bad_Opcode }, |
7978 | { Bad_Opcode }, |
7576 | { Bad_Opcode }, |
7979 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, |
7980 | { Bad_Opcode }, |
7578 | { Bad_Opcode }, |
7981 | { Bad_Opcode }, |
7579 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7982 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7580 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7983 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7581 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7984 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7582 | /* 88 */ |
7985 | /* 88 */ |
7583 | { Bad_Opcode }, |
7986 | { Bad_Opcode }, |
7584 | { Bad_Opcode }, |
7987 | { Bad_Opcode }, |
7585 | { Bad_Opcode }, |
7988 | { Bad_Opcode }, |
7586 | { Bad_Opcode }, |
7989 | { Bad_Opcode }, |
7587 | { Bad_Opcode }, |
7990 | { Bad_Opcode }, |
7588 | { Bad_Opcode }, |
7991 | { Bad_Opcode }, |
7589 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7992 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7590 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7993 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7591 | /* 90 */ |
7994 | /* 90 */ |
7592 | { Bad_Opcode }, |
7995 | { Bad_Opcode }, |
7593 | { Bad_Opcode }, |
7996 | { Bad_Opcode }, |
7594 | { Bad_Opcode }, |
7997 | { Bad_Opcode }, |
7595 | { Bad_Opcode }, |
7998 | { Bad_Opcode }, |
7596 | { Bad_Opcode }, |
7999 | { Bad_Opcode }, |
7597 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8000 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7598 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8001 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7599 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8002 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7600 | /* 98 */ |
8003 | /* 98 */ |
7601 | { Bad_Opcode }, |
8004 | { Bad_Opcode }, |
7602 | { Bad_Opcode }, |
8005 | { Bad_Opcode }, |
7603 | { Bad_Opcode }, |
8006 | { Bad_Opcode }, |
7604 | { Bad_Opcode }, |
8007 | { Bad_Opcode }, |
7605 | { Bad_Opcode }, |
8008 | { Bad_Opcode }, |
7606 | { Bad_Opcode }, |
8009 | { Bad_Opcode }, |
7607 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8010 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7608 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8011 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7609 | /* a0 */ |
8012 | /* a0 */ |
7610 | { Bad_Opcode }, |
8013 | { Bad_Opcode }, |
7611 | { Bad_Opcode }, |
8014 | { Bad_Opcode }, |
7612 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8015 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7613 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8016 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7614 | { Bad_Opcode }, |
8017 | { Bad_Opcode }, |
7615 | { Bad_Opcode }, |
8018 | { Bad_Opcode }, |
7616 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8019 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7617 | { Bad_Opcode }, |
8020 | { Bad_Opcode }, |
7618 | /* a8 */ |
8021 | /* a8 */ |
7619 | { Bad_Opcode }, |
8022 | { Bad_Opcode }, |
7620 | { Bad_Opcode }, |
8023 | { Bad_Opcode }, |
7621 | { Bad_Opcode }, |
8024 | { Bad_Opcode }, |
7622 | { Bad_Opcode }, |
8025 | { Bad_Opcode }, |
7623 | { Bad_Opcode }, |
8026 | { Bad_Opcode }, |
7624 | { Bad_Opcode }, |
8027 | { Bad_Opcode }, |
7625 | { Bad_Opcode }, |
8028 | { Bad_Opcode }, |
7626 | { Bad_Opcode }, |
8029 | { Bad_Opcode }, |
7627 | /* b0 */ |
8030 | /* b0 */ |
7628 | { Bad_Opcode }, |
8031 | { Bad_Opcode }, |
7629 | { Bad_Opcode }, |
8032 | { Bad_Opcode }, |
7630 | { Bad_Opcode }, |
8033 | { Bad_Opcode }, |
7631 | { Bad_Opcode }, |
8034 | { Bad_Opcode }, |
7632 | { Bad_Opcode }, |
8035 | { Bad_Opcode }, |
7633 | { Bad_Opcode }, |
8036 | { Bad_Opcode }, |
7634 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8037 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7635 | { Bad_Opcode }, |
8038 | { Bad_Opcode }, |
7636 | /* b8 */ |
8039 | /* b8 */ |
7637 | { Bad_Opcode }, |
8040 | { Bad_Opcode }, |
7638 | { Bad_Opcode }, |
8041 | { Bad_Opcode }, |
7639 | { Bad_Opcode }, |
8042 | { Bad_Opcode }, |
7640 | { Bad_Opcode }, |
8043 | { Bad_Opcode }, |
7641 | { Bad_Opcode }, |
8044 | { Bad_Opcode }, |
7642 | { Bad_Opcode }, |
8045 | { Bad_Opcode }, |
7643 | { Bad_Opcode }, |
8046 | { Bad_Opcode }, |
7644 | { Bad_Opcode }, |
8047 | { Bad_Opcode }, |
7645 | /* c0 */ |
8048 | /* c0 */ |
7646 | { "vprotb", { XM, Vex_2src_1, Ib } }, |
8049 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7647 | { "vprotw", { XM, Vex_2src_1, Ib } }, |
8050 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, |
7648 | { "vprotd", { XM, Vex_2src_1, Ib } }, |
8051 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, |
7649 | { "vprotq", { XM, Vex_2src_1, Ib } }, |
8052 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, |
7650 | { Bad_Opcode }, |
8053 | { Bad_Opcode }, |
7651 | { Bad_Opcode }, |
8054 | { Bad_Opcode }, |
7652 | { Bad_Opcode }, |
8055 | { Bad_Opcode }, |
7653 | { Bad_Opcode }, |
8056 | { Bad_Opcode }, |
7654 | /* c8 */ |
8057 | /* c8 */ |
7655 | { Bad_Opcode }, |
8058 | { Bad_Opcode }, |
7656 | { Bad_Opcode }, |
8059 | { Bad_Opcode }, |
7657 | { Bad_Opcode }, |
8060 | { Bad_Opcode }, |
7658 | { Bad_Opcode }, |
8061 | { Bad_Opcode }, |
7659 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
8062 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7660 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, |
8063 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, |
7661 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, |
8064 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, |
7662 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, |
8065 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, |
7663 | /* d0 */ |
8066 | /* d0 */ |
7664 | { Bad_Opcode }, |
8067 | { Bad_Opcode }, |
7665 | { Bad_Opcode }, |
8068 | { Bad_Opcode }, |
7666 | { Bad_Opcode }, |
8069 | { Bad_Opcode }, |
7667 | { Bad_Opcode }, |
8070 | { Bad_Opcode }, |
7668 | { Bad_Opcode }, |
8071 | { Bad_Opcode }, |
7669 | { Bad_Opcode }, |
8072 | { Bad_Opcode }, |
7670 | { Bad_Opcode }, |
8073 | { Bad_Opcode }, |
7671 | { Bad_Opcode }, |
8074 | { Bad_Opcode }, |
7672 | /* d8 */ |
8075 | /* d8 */ |
7673 | { Bad_Opcode }, |
8076 | { Bad_Opcode }, |
7674 | { Bad_Opcode }, |
8077 | { Bad_Opcode }, |
7675 | { Bad_Opcode }, |
8078 | { Bad_Opcode }, |
7676 | { Bad_Opcode }, |
8079 | { Bad_Opcode }, |
7677 | { Bad_Opcode }, |
8080 | { Bad_Opcode }, |
7678 | { Bad_Opcode }, |
8081 | { Bad_Opcode }, |
7679 | { Bad_Opcode }, |
8082 | { Bad_Opcode }, |
7680 | { Bad_Opcode }, |
8083 | { Bad_Opcode }, |
7681 | /* e0 */ |
8084 | /* e0 */ |
7682 | { Bad_Opcode }, |
8085 | { Bad_Opcode }, |
7683 | { Bad_Opcode }, |
8086 | { Bad_Opcode }, |
7684 | { Bad_Opcode }, |
8087 | { Bad_Opcode }, |
7685 | { Bad_Opcode }, |
8088 | { Bad_Opcode }, |
7686 | { Bad_Opcode }, |
8089 | { Bad_Opcode }, |
7687 | { Bad_Opcode }, |
8090 | { Bad_Opcode }, |
7688 | { Bad_Opcode }, |
8091 | { Bad_Opcode }, |
7689 | { Bad_Opcode }, |
8092 | { Bad_Opcode }, |
7690 | /* e8 */ |
8093 | /* e8 */ |
7691 | { Bad_Opcode }, |
8094 | { Bad_Opcode }, |
7692 | { Bad_Opcode }, |
8095 | { Bad_Opcode }, |
7693 | { Bad_Opcode }, |
8096 | { Bad_Opcode }, |
7694 | { Bad_Opcode }, |
8097 | { Bad_Opcode }, |
7695 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
8098 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7696 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, |
8099 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, |
7697 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, |
8100 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, |
7698 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, |
8101 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, |
7699 | /* f0 */ |
8102 | /* f0 */ |
7700 | { Bad_Opcode }, |
8103 | { Bad_Opcode }, |
7701 | { Bad_Opcode }, |
8104 | { Bad_Opcode }, |
7702 | { Bad_Opcode }, |
8105 | { Bad_Opcode }, |
7703 | { Bad_Opcode }, |
8106 | { Bad_Opcode }, |
7704 | { Bad_Opcode }, |
8107 | { Bad_Opcode }, |
7705 | { Bad_Opcode }, |
8108 | { Bad_Opcode }, |
7706 | { Bad_Opcode }, |
8109 | { Bad_Opcode }, |
7707 | { Bad_Opcode }, |
8110 | { Bad_Opcode }, |
7708 | /* f8 */ |
8111 | /* f8 */ |
7709 | { Bad_Opcode }, |
8112 | { Bad_Opcode }, |
7710 | { Bad_Opcode }, |
8113 | { Bad_Opcode }, |
7711 | { Bad_Opcode }, |
8114 | { Bad_Opcode }, |
7712 | { Bad_Opcode }, |
8115 | { Bad_Opcode }, |
7713 | { Bad_Opcode }, |
8116 | { Bad_Opcode }, |
7714 | { Bad_Opcode }, |
8117 | { Bad_Opcode }, |
7715 | { Bad_Opcode }, |
8118 | { Bad_Opcode }, |
7716 | { Bad_Opcode }, |
8119 | { Bad_Opcode }, |
7717 | }, |
8120 | }, |
7718 | /* XOP_09 */ |
8121 | /* XOP_09 */ |
7719 | { |
8122 | { |
7720 | /* 00 */ |
8123 | /* 00 */ |
7721 | { Bad_Opcode }, |
8124 | { Bad_Opcode }, |
7722 | { REG_TABLE (REG_XOP_TBM_01) }, |
8125 | { REG_TABLE (REG_XOP_TBM_01) }, |
7723 | { REG_TABLE (REG_XOP_TBM_02) }, |
8126 | { REG_TABLE (REG_XOP_TBM_02) }, |
7724 | { Bad_Opcode }, |
8127 | { Bad_Opcode }, |
7725 | { Bad_Opcode }, |
8128 | { Bad_Opcode }, |
7726 | { Bad_Opcode }, |
8129 | { Bad_Opcode }, |
7727 | { Bad_Opcode }, |
8130 | { Bad_Opcode }, |
7728 | { Bad_Opcode }, |
8131 | { Bad_Opcode }, |
7729 | /* 08 */ |
8132 | /* 08 */ |
7730 | { Bad_Opcode }, |
8133 | { Bad_Opcode }, |
7731 | { Bad_Opcode }, |
8134 | { Bad_Opcode }, |
7732 | { Bad_Opcode }, |
8135 | { Bad_Opcode }, |
7733 | { Bad_Opcode }, |
8136 | { Bad_Opcode }, |
7734 | { Bad_Opcode }, |
8137 | { Bad_Opcode }, |
7735 | { Bad_Opcode }, |
8138 | { Bad_Opcode }, |
7736 | { Bad_Opcode }, |
8139 | { Bad_Opcode }, |
7737 | { Bad_Opcode }, |
8140 | { Bad_Opcode }, |
7738 | /* 10 */ |
8141 | /* 10 */ |
7739 | { Bad_Opcode }, |
8142 | { Bad_Opcode }, |
7740 | { Bad_Opcode }, |
8143 | { Bad_Opcode }, |
7741 | { REG_TABLE (REG_XOP_LWPCB) }, |
8144 | { REG_TABLE (REG_XOP_LWPCB) }, |
7742 | { Bad_Opcode }, |
8145 | { Bad_Opcode }, |
7743 | { Bad_Opcode }, |
8146 | { Bad_Opcode }, |
7744 | { Bad_Opcode }, |
8147 | { Bad_Opcode }, |
7745 | { Bad_Opcode }, |
8148 | { Bad_Opcode }, |
7746 | { Bad_Opcode }, |
8149 | { Bad_Opcode }, |
7747 | /* 18 */ |
8150 | /* 18 */ |
7748 | { Bad_Opcode }, |
8151 | { Bad_Opcode }, |
7749 | { Bad_Opcode }, |
8152 | { Bad_Opcode }, |
7750 | { Bad_Opcode }, |
8153 | { Bad_Opcode }, |
7751 | { Bad_Opcode }, |
8154 | { Bad_Opcode }, |
7752 | { Bad_Opcode }, |
8155 | { Bad_Opcode }, |
7753 | { Bad_Opcode }, |
8156 | { Bad_Opcode }, |
7754 | { Bad_Opcode }, |
8157 | { Bad_Opcode }, |
7755 | { Bad_Opcode }, |
8158 | { Bad_Opcode }, |
7756 | /* 20 */ |
8159 | /* 20 */ |
7757 | { Bad_Opcode }, |
8160 | { Bad_Opcode }, |
7758 | { Bad_Opcode }, |
8161 | { Bad_Opcode }, |
7759 | { Bad_Opcode }, |
8162 | { Bad_Opcode }, |
7760 | { Bad_Opcode }, |
8163 | { Bad_Opcode }, |
7761 | { Bad_Opcode }, |
8164 | { Bad_Opcode }, |
7762 | { Bad_Opcode }, |
8165 | { Bad_Opcode }, |
7763 | { Bad_Opcode }, |
8166 | { Bad_Opcode }, |
7764 | { Bad_Opcode }, |
8167 | { Bad_Opcode }, |
7765 | /* 28 */ |
8168 | /* 28 */ |
7766 | { Bad_Opcode }, |
8169 | { Bad_Opcode }, |
7767 | { Bad_Opcode }, |
8170 | { Bad_Opcode }, |
7768 | { Bad_Opcode }, |
8171 | { Bad_Opcode }, |
7769 | { Bad_Opcode }, |
8172 | { Bad_Opcode }, |
7770 | { Bad_Opcode }, |
8173 | { Bad_Opcode }, |
7771 | { Bad_Opcode }, |
8174 | { Bad_Opcode }, |
7772 | { Bad_Opcode }, |
8175 | { Bad_Opcode }, |
7773 | { Bad_Opcode }, |
8176 | { Bad_Opcode }, |
7774 | /* 30 */ |
8177 | /* 30 */ |
7775 | { Bad_Opcode }, |
8178 | { Bad_Opcode }, |
7776 | { Bad_Opcode }, |
8179 | { Bad_Opcode }, |
7777 | { Bad_Opcode }, |
8180 | { Bad_Opcode }, |
7778 | { Bad_Opcode }, |
8181 | { Bad_Opcode }, |
7779 | { Bad_Opcode }, |
8182 | { Bad_Opcode }, |
7780 | { Bad_Opcode }, |
8183 | { Bad_Opcode }, |
7781 | { Bad_Opcode }, |
8184 | { Bad_Opcode }, |
7782 | { Bad_Opcode }, |
8185 | { Bad_Opcode }, |
7783 | /* 38 */ |
8186 | /* 38 */ |
7784 | { Bad_Opcode }, |
8187 | { Bad_Opcode }, |
7785 | { Bad_Opcode }, |
8188 | { Bad_Opcode }, |
7786 | { Bad_Opcode }, |
8189 | { Bad_Opcode }, |
7787 | { Bad_Opcode }, |
8190 | { Bad_Opcode }, |
7788 | { Bad_Opcode }, |
8191 | { Bad_Opcode }, |
7789 | { Bad_Opcode }, |
8192 | { Bad_Opcode }, |
7790 | { Bad_Opcode }, |
8193 | { Bad_Opcode }, |
7791 | { Bad_Opcode }, |
8194 | { Bad_Opcode }, |
7792 | /* 40 */ |
8195 | /* 40 */ |
7793 | { Bad_Opcode }, |
8196 | { Bad_Opcode }, |
7794 | { Bad_Opcode }, |
8197 | { Bad_Opcode }, |
7795 | { Bad_Opcode }, |
8198 | { Bad_Opcode }, |
7796 | { Bad_Opcode }, |
8199 | { Bad_Opcode }, |
7797 | { Bad_Opcode }, |
8200 | { Bad_Opcode }, |
7798 | { Bad_Opcode }, |
8201 | { Bad_Opcode }, |
7799 | { Bad_Opcode }, |
8202 | { Bad_Opcode }, |
7800 | { Bad_Opcode }, |
8203 | { Bad_Opcode }, |
7801 | /* 48 */ |
8204 | /* 48 */ |
7802 | { Bad_Opcode }, |
8205 | { Bad_Opcode }, |
7803 | { Bad_Opcode }, |
8206 | { Bad_Opcode }, |
7804 | { Bad_Opcode }, |
8207 | { Bad_Opcode }, |
7805 | { Bad_Opcode }, |
8208 | { Bad_Opcode }, |
7806 | { Bad_Opcode }, |
8209 | { Bad_Opcode }, |
7807 | { Bad_Opcode }, |
8210 | { Bad_Opcode }, |
7808 | { Bad_Opcode }, |
8211 | { Bad_Opcode }, |
7809 | { Bad_Opcode }, |
8212 | { Bad_Opcode }, |
7810 | /* 50 */ |
8213 | /* 50 */ |
7811 | { Bad_Opcode }, |
8214 | { Bad_Opcode }, |
7812 | { Bad_Opcode }, |
8215 | { Bad_Opcode }, |
7813 | { Bad_Opcode }, |
8216 | { Bad_Opcode }, |
7814 | { Bad_Opcode }, |
8217 | { Bad_Opcode }, |
7815 | { Bad_Opcode }, |
8218 | { Bad_Opcode }, |
7816 | { Bad_Opcode }, |
8219 | { Bad_Opcode }, |
7817 | { Bad_Opcode }, |
8220 | { Bad_Opcode }, |
7818 | { Bad_Opcode }, |
8221 | { Bad_Opcode }, |
7819 | /* 58 */ |
8222 | /* 58 */ |
7820 | { Bad_Opcode }, |
8223 | { Bad_Opcode }, |
7821 | { Bad_Opcode }, |
8224 | { Bad_Opcode }, |
7822 | { Bad_Opcode }, |
8225 | { Bad_Opcode }, |
7823 | { Bad_Opcode }, |
8226 | { Bad_Opcode }, |
7824 | { Bad_Opcode }, |
8227 | { Bad_Opcode }, |
7825 | { Bad_Opcode }, |
8228 | { Bad_Opcode }, |
7826 | { Bad_Opcode }, |
8229 | { Bad_Opcode }, |
7827 | { Bad_Opcode }, |
8230 | { Bad_Opcode }, |
7828 | /* 60 */ |
8231 | /* 60 */ |
7829 | { Bad_Opcode }, |
8232 | { Bad_Opcode }, |
7830 | { Bad_Opcode }, |
8233 | { Bad_Opcode }, |
7831 | { Bad_Opcode }, |
8234 | { Bad_Opcode }, |
7832 | { Bad_Opcode }, |
8235 | { Bad_Opcode }, |
7833 | { Bad_Opcode }, |
8236 | { Bad_Opcode }, |
7834 | { Bad_Opcode }, |
8237 | { Bad_Opcode }, |
7835 | { Bad_Opcode }, |
8238 | { Bad_Opcode }, |
7836 | { Bad_Opcode }, |
8239 | { Bad_Opcode }, |
7837 | /* 68 */ |
8240 | /* 68 */ |
7838 | { Bad_Opcode }, |
8241 | { Bad_Opcode }, |
7839 | { Bad_Opcode }, |
8242 | { Bad_Opcode }, |
7840 | { Bad_Opcode }, |
8243 | { Bad_Opcode }, |
7841 | { Bad_Opcode }, |
8244 | { Bad_Opcode }, |
7842 | { Bad_Opcode }, |
8245 | { Bad_Opcode }, |
7843 | { Bad_Opcode }, |
8246 | { Bad_Opcode }, |
7844 | { Bad_Opcode }, |
8247 | { Bad_Opcode }, |
7845 | { Bad_Opcode }, |
8248 | { Bad_Opcode }, |
7846 | /* 70 */ |
8249 | /* 70 */ |
7847 | { Bad_Opcode }, |
8250 | { Bad_Opcode }, |
7848 | { Bad_Opcode }, |
8251 | { Bad_Opcode }, |
7849 | { Bad_Opcode }, |
8252 | { Bad_Opcode }, |
7850 | { Bad_Opcode }, |
8253 | { Bad_Opcode }, |
7851 | { Bad_Opcode }, |
8254 | { Bad_Opcode }, |
7852 | { Bad_Opcode }, |
8255 | { Bad_Opcode }, |
7853 | { Bad_Opcode }, |
8256 | { Bad_Opcode }, |
7854 | { Bad_Opcode }, |
8257 | { Bad_Opcode }, |
7855 | /* 78 */ |
8258 | /* 78 */ |
7856 | { Bad_Opcode }, |
8259 | { Bad_Opcode }, |
7857 | { Bad_Opcode }, |
8260 | { Bad_Opcode }, |
7858 | { Bad_Opcode }, |
8261 | { Bad_Opcode }, |
7859 | { Bad_Opcode }, |
8262 | { Bad_Opcode }, |
7860 | { Bad_Opcode }, |
8263 | { Bad_Opcode }, |
7861 | { Bad_Opcode }, |
8264 | { Bad_Opcode }, |
7862 | { Bad_Opcode }, |
8265 | { Bad_Opcode }, |
7863 | { Bad_Opcode }, |
8266 | { Bad_Opcode }, |
7864 | /* 80 */ |
8267 | /* 80 */ |
7865 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
8268 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7866 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, |
8269 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, |
7867 | { "vfrczss", { XM, EXd } }, |
8270 | { "vfrczss", { XM, EXd }, 0 }, |
7868 | { "vfrczsd", { XM, EXq } }, |
8271 | { "vfrczsd", { XM, EXq }, 0 }, |
7869 | { Bad_Opcode }, |
8272 | { Bad_Opcode }, |
7870 | { Bad_Opcode }, |
8273 | { Bad_Opcode }, |
7871 | { Bad_Opcode }, |
8274 | { Bad_Opcode }, |
7872 | { Bad_Opcode }, |
8275 | { Bad_Opcode }, |
7873 | /* 88 */ |
8276 | /* 88 */ |
7874 | { Bad_Opcode }, |
8277 | { Bad_Opcode }, |
7875 | { Bad_Opcode }, |
8278 | { Bad_Opcode }, |
7876 | { Bad_Opcode }, |
8279 | { Bad_Opcode }, |
7877 | { Bad_Opcode }, |
8280 | { Bad_Opcode }, |
7878 | { Bad_Opcode }, |
8281 | { Bad_Opcode }, |
7879 | { Bad_Opcode }, |
8282 | { Bad_Opcode }, |
7880 | { Bad_Opcode }, |
8283 | { Bad_Opcode }, |
7881 | { Bad_Opcode }, |
8284 | { Bad_Opcode }, |
7882 | /* 90 */ |
8285 | /* 90 */ |
7883 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, |
8286 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7884 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, |
8287 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7885 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, |
8288 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7886 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, |
8289 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7887 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, |
8290 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7888 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, |
8291 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7889 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, |
8292 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7890 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, |
8293 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7891 | /* 98 */ |
8294 | /* 98 */ |
7892 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, |
8295 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7893 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, |
8296 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7894 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, |
8297 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7895 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, |
8298 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7896 | { Bad_Opcode }, |
8299 | { Bad_Opcode }, |
7897 | { Bad_Opcode }, |
8300 | { Bad_Opcode }, |
7898 | { Bad_Opcode }, |
8301 | { Bad_Opcode }, |
7899 | { Bad_Opcode }, |
8302 | { Bad_Opcode }, |
7900 | /* a0 */ |
8303 | /* a0 */ |
7901 | { Bad_Opcode }, |
8304 | { Bad_Opcode }, |
7902 | { Bad_Opcode }, |
8305 | { Bad_Opcode }, |
7903 | { Bad_Opcode }, |
8306 | { Bad_Opcode }, |
7904 | { Bad_Opcode }, |
8307 | { Bad_Opcode }, |
7905 | { Bad_Opcode }, |
8308 | { Bad_Opcode }, |
7906 | { Bad_Opcode }, |
8309 | { Bad_Opcode }, |
7907 | { Bad_Opcode }, |
8310 | { Bad_Opcode }, |
7908 | { Bad_Opcode }, |
8311 | { Bad_Opcode }, |
7909 | /* a8 */ |
8312 | /* a8 */ |
7910 | { Bad_Opcode }, |
8313 | { Bad_Opcode }, |
7911 | { Bad_Opcode }, |
8314 | { Bad_Opcode }, |
7912 | { Bad_Opcode }, |
8315 | { Bad_Opcode }, |
7913 | { Bad_Opcode }, |
8316 | { Bad_Opcode }, |
7914 | { Bad_Opcode }, |
8317 | { Bad_Opcode }, |
7915 | { Bad_Opcode }, |
8318 | { Bad_Opcode }, |
7916 | { Bad_Opcode }, |
8319 | { Bad_Opcode }, |
7917 | { Bad_Opcode }, |
8320 | { Bad_Opcode }, |
7918 | /* b0 */ |
8321 | /* b0 */ |
7919 | { Bad_Opcode }, |
8322 | { Bad_Opcode }, |
7920 | { Bad_Opcode }, |
8323 | { Bad_Opcode }, |
7921 | { Bad_Opcode }, |
8324 | { Bad_Opcode }, |
7922 | { Bad_Opcode }, |
8325 | { Bad_Opcode }, |
7923 | { Bad_Opcode }, |
8326 | { Bad_Opcode }, |
7924 | { Bad_Opcode }, |
8327 | { Bad_Opcode }, |
7925 | { Bad_Opcode }, |
8328 | { Bad_Opcode }, |
7926 | { Bad_Opcode }, |
8329 | { Bad_Opcode }, |
7927 | /* b8 */ |
8330 | /* b8 */ |
7928 | { Bad_Opcode }, |
8331 | { Bad_Opcode }, |
7929 | { Bad_Opcode }, |
8332 | { Bad_Opcode }, |
7930 | { Bad_Opcode }, |
8333 | { Bad_Opcode }, |
7931 | { Bad_Opcode }, |
8334 | { Bad_Opcode }, |
7932 | { Bad_Opcode }, |
8335 | { Bad_Opcode }, |
7933 | { Bad_Opcode }, |
8336 | { Bad_Opcode }, |
7934 | { Bad_Opcode }, |
8337 | { Bad_Opcode }, |
7935 | { Bad_Opcode }, |
8338 | { Bad_Opcode }, |
7936 | /* c0 */ |
8339 | /* c0 */ |
7937 | { Bad_Opcode }, |
8340 | { Bad_Opcode }, |
7938 | { "vphaddbw", { XM, EXxmm } }, |
8341 | { "vphaddbw", { XM, EXxmm }, 0 }, |
7939 | { "vphaddbd", { XM, EXxmm } }, |
8342 | { "vphaddbd", { XM, EXxmm }, 0 }, |
7940 | { "vphaddbq", { XM, EXxmm } }, |
8343 | { "vphaddbq", { XM, EXxmm }, 0 }, |
7941 | { Bad_Opcode }, |
8344 | { Bad_Opcode }, |
7942 | { Bad_Opcode }, |
8345 | { Bad_Opcode }, |
7943 | { "vphaddwd", { XM, EXxmm } }, |
8346 | { "vphaddwd", { XM, EXxmm }, 0 }, |
7944 | { "vphaddwq", { XM, EXxmm } }, |
8347 | { "vphaddwq", { XM, EXxmm }, 0 }, |
7945 | /* c8 */ |
8348 | /* c8 */ |
7946 | { Bad_Opcode }, |
8349 | { Bad_Opcode }, |
7947 | { Bad_Opcode }, |
8350 | { Bad_Opcode }, |
7948 | { Bad_Opcode }, |
8351 | { Bad_Opcode }, |
7949 | { "vphadddq", { XM, EXxmm } }, |
8352 | { "vphadddq", { XM, EXxmm }, 0 }, |
7950 | { Bad_Opcode }, |
8353 | { Bad_Opcode }, |
7951 | { Bad_Opcode }, |
8354 | { Bad_Opcode }, |
7952 | { Bad_Opcode }, |
8355 | { Bad_Opcode }, |
7953 | { Bad_Opcode }, |
8356 | { Bad_Opcode }, |
7954 | /* d0 */ |
8357 | /* d0 */ |
7955 | { Bad_Opcode }, |
8358 | { Bad_Opcode }, |
7956 | { "vphaddubw", { XM, EXxmm } }, |
8359 | { "vphaddubw", { XM, EXxmm }, 0 }, |
7957 | { "vphaddubd", { XM, EXxmm } }, |
8360 | { "vphaddubd", { XM, EXxmm }, 0 }, |
7958 | { "vphaddubq", { XM, EXxmm } }, |
8361 | { "vphaddubq", { XM, EXxmm }, 0 }, |
7959 | { Bad_Opcode }, |
8362 | { Bad_Opcode }, |
7960 | { Bad_Opcode }, |
8363 | { Bad_Opcode }, |
7961 | { "vphadduwd", { XM, EXxmm } }, |
8364 | { "vphadduwd", { XM, EXxmm }, 0 }, |
7962 | { "vphadduwq", { XM, EXxmm } }, |
8365 | { "vphadduwq", { XM, EXxmm }, 0 }, |
7963 | /* d8 */ |
8366 | /* d8 */ |
7964 | { Bad_Opcode }, |
8367 | { Bad_Opcode }, |
7965 | { Bad_Opcode }, |
8368 | { Bad_Opcode }, |
7966 | { Bad_Opcode }, |
8369 | { Bad_Opcode }, |
7967 | { "vphaddudq", { XM, EXxmm } }, |
8370 | { "vphaddudq", { XM, EXxmm }, 0 }, |
7968 | { Bad_Opcode }, |
8371 | { Bad_Opcode }, |
7969 | { Bad_Opcode }, |
8372 | { Bad_Opcode }, |
7970 | { Bad_Opcode }, |
8373 | { Bad_Opcode }, |
7971 | { Bad_Opcode }, |
8374 | { Bad_Opcode }, |
7972 | /* e0 */ |
8375 | /* e0 */ |
7973 | { Bad_Opcode }, |
8376 | { Bad_Opcode }, |
7974 | { "vphsubbw", { XM, EXxmm } }, |
8377 | { "vphsubbw", { XM, EXxmm }, 0 }, |
7975 | { "vphsubwd", { XM, EXxmm } }, |
8378 | { "vphsubwd", { XM, EXxmm }, 0 }, |
7976 | { "vphsubdq", { XM, EXxmm } }, |
8379 | { "vphsubdq", { XM, EXxmm }, 0 }, |
7977 | { Bad_Opcode }, |
8380 | { Bad_Opcode }, |
7978 | { Bad_Opcode }, |
8381 | { Bad_Opcode }, |
7979 | { Bad_Opcode }, |
8382 | { Bad_Opcode }, |
7980 | { Bad_Opcode }, |
8383 | { Bad_Opcode }, |
7981 | /* e8 */ |
8384 | /* e8 */ |
7982 | { Bad_Opcode }, |
8385 | { Bad_Opcode }, |
7983 | { Bad_Opcode }, |
8386 | { Bad_Opcode }, |
7984 | { Bad_Opcode }, |
8387 | { Bad_Opcode }, |
7985 | { Bad_Opcode }, |
8388 | { Bad_Opcode }, |
7986 | { Bad_Opcode }, |
8389 | { Bad_Opcode }, |
7987 | { Bad_Opcode }, |
8390 | { Bad_Opcode }, |
7988 | { Bad_Opcode }, |
8391 | { Bad_Opcode }, |
7989 | { Bad_Opcode }, |
8392 | { Bad_Opcode }, |
7990 | /* f0 */ |
8393 | /* f0 */ |
7991 | { Bad_Opcode }, |
8394 | { Bad_Opcode }, |
7992 | { Bad_Opcode }, |
8395 | { Bad_Opcode }, |
7993 | { Bad_Opcode }, |
8396 | { Bad_Opcode }, |
7994 | { Bad_Opcode }, |
8397 | { Bad_Opcode }, |
7995 | { Bad_Opcode }, |
8398 | { Bad_Opcode }, |
7996 | { Bad_Opcode }, |
8399 | { Bad_Opcode }, |
7997 | { Bad_Opcode }, |
8400 | { Bad_Opcode }, |
7998 | { Bad_Opcode }, |
8401 | { Bad_Opcode }, |
7999 | /* f8 */ |
8402 | /* f8 */ |
8000 | { Bad_Opcode }, |
8403 | { Bad_Opcode }, |
8001 | { Bad_Opcode }, |
8404 | { Bad_Opcode }, |
8002 | { Bad_Opcode }, |
8405 | { Bad_Opcode }, |
8003 | { Bad_Opcode }, |
8406 | { Bad_Opcode }, |
8004 | { Bad_Opcode }, |
8407 | { Bad_Opcode }, |
8005 | { Bad_Opcode }, |
8408 | { Bad_Opcode }, |
8006 | { Bad_Opcode }, |
8409 | { Bad_Opcode }, |
8007 | { Bad_Opcode }, |
8410 | { Bad_Opcode }, |
8008 | }, |
8411 | }, |
8009 | /* XOP_0A */ |
8412 | /* XOP_0A */ |
8010 | { |
8413 | { |
8011 | /* 00 */ |
8414 | /* 00 */ |
8012 | { Bad_Opcode }, |
8415 | { Bad_Opcode }, |
8013 | { Bad_Opcode }, |
8416 | { Bad_Opcode }, |
8014 | { Bad_Opcode }, |
8417 | { Bad_Opcode }, |
8015 | { Bad_Opcode }, |
8418 | { Bad_Opcode }, |
8016 | { Bad_Opcode }, |
8419 | { Bad_Opcode }, |
8017 | { Bad_Opcode }, |
8420 | { Bad_Opcode }, |
8018 | { Bad_Opcode }, |
8421 | { Bad_Opcode }, |
8019 | { Bad_Opcode }, |
8422 | { Bad_Opcode }, |
8020 | /* 08 */ |
8423 | /* 08 */ |
8021 | { Bad_Opcode }, |
8424 | { Bad_Opcode }, |
8022 | { Bad_Opcode }, |
8425 | { Bad_Opcode }, |
8023 | { Bad_Opcode }, |
8426 | { Bad_Opcode }, |
8024 | { Bad_Opcode }, |
8427 | { Bad_Opcode }, |
8025 | { Bad_Opcode }, |
8428 | { Bad_Opcode }, |
8026 | { Bad_Opcode }, |
8429 | { Bad_Opcode }, |
8027 | { Bad_Opcode }, |
8430 | { Bad_Opcode }, |
8028 | { Bad_Opcode }, |
8431 | { Bad_Opcode }, |
8029 | /* 10 */ |
8432 | /* 10 */ |
8030 | { "bextr", { Gv, Ev, Iq } }, |
8433 | { "bextr", { Gv, Ev, Iq }, 0 }, |
8031 | { Bad_Opcode }, |
8434 | { Bad_Opcode }, |
8032 | { REG_TABLE (REG_XOP_LWP) }, |
8435 | { REG_TABLE (REG_XOP_LWP) }, |
8033 | { Bad_Opcode }, |
8436 | { Bad_Opcode }, |
8034 | { Bad_Opcode }, |
8437 | { Bad_Opcode }, |
8035 | { Bad_Opcode }, |
8438 | { Bad_Opcode }, |
8036 | { Bad_Opcode }, |
8439 | { Bad_Opcode }, |
8037 | { Bad_Opcode }, |
8440 | { Bad_Opcode }, |
8038 | /* 18 */ |
8441 | /* 18 */ |
8039 | { Bad_Opcode }, |
8442 | { Bad_Opcode }, |
8040 | { Bad_Opcode }, |
8443 | { Bad_Opcode }, |
8041 | { Bad_Opcode }, |
8444 | { Bad_Opcode }, |
8042 | { Bad_Opcode }, |
8445 | { Bad_Opcode }, |
8043 | { Bad_Opcode }, |
8446 | { Bad_Opcode }, |
8044 | { Bad_Opcode }, |
8447 | { Bad_Opcode }, |
8045 | { Bad_Opcode }, |
8448 | { Bad_Opcode }, |
8046 | { Bad_Opcode }, |
8449 | { Bad_Opcode }, |
8047 | /* 20 */ |
8450 | /* 20 */ |
8048 | { Bad_Opcode }, |
8451 | { Bad_Opcode }, |
8049 | { Bad_Opcode }, |
8452 | { Bad_Opcode }, |
8050 | { Bad_Opcode }, |
8453 | { Bad_Opcode }, |
8051 | { Bad_Opcode }, |
8454 | { Bad_Opcode }, |
8052 | { Bad_Opcode }, |
8455 | { Bad_Opcode }, |
8053 | { Bad_Opcode }, |
8456 | { Bad_Opcode }, |
8054 | { Bad_Opcode }, |
8457 | { Bad_Opcode }, |
8055 | { Bad_Opcode }, |
8458 | { Bad_Opcode }, |
8056 | /* 28 */ |
8459 | /* 28 */ |
8057 | { Bad_Opcode }, |
8460 | { Bad_Opcode }, |
8058 | { Bad_Opcode }, |
8461 | { Bad_Opcode }, |
8059 | { Bad_Opcode }, |
8462 | { Bad_Opcode }, |
8060 | { Bad_Opcode }, |
8463 | { Bad_Opcode }, |
8061 | { Bad_Opcode }, |
8464 | { Bad_Opcode }, |
8062 | { Bad_Opcode }, |
8465 | { Bad_Opcode }, |
8063 | { Bad_Opcode }, |
8466 | { Bad_Opcode }, |
8064 | { Bad_Opcode }, |
8467 | { Bad_Opcode }, |
8065 | /* 30 */ |
8468 | /* 30 */ |
8066 | { Bad_Opcode }, |
8469 | { Bad_Opcode }, |
8067 | { Bad_Opcode }, |
8470 | { Bad_Opcode }, |
8068 | { Bad_Opcode }, |
8471 | { Bad_Opcode }, |
8069 | { Bad_Opcode }, |
8472 | { Bad_Opcode }, |
8070 | { Bad_Opcode }, |
8473 | { Bad_Opcode }, |
8071 | { Bad_Opcode }, |
8474 | { Bad_Opcode }, |
8072 | { Bad_Opcode }, |
8475 | { Bad_Opcode }, |
8073 | { Bad_Opcode }, |
8476 | { Bad_Opcode }, |
8074 | /* 38 */ |
8477 | /* 38 */ |
8075 | { Bad_Opcode }, |
8478 | { Bad_Opcode }, |
8076 | { Bad_Opcode }, |
8479 | { Bad_Opcode }, |
8077 | { Bad_Opcode }, |
8480 | { Bad_Opcode }, |
8078 | { Bad_Opcode }, |
8481 | { Bad_Opcode }, |
8079 | { Bad_Opcode }, |
8482 | { Bad_Opcode }, |
8080 | { Bad_Opcode }, |
8483 | { Bad_Opcode }, |
8081 | { Bad_Opcode }, |
8484 | { Bad_Opcode }, |
8082 | { Bad_Opcode }, |
8485 | { Bad_Opcode }, |
8083 | /* 40 */ |
8486 | /* 40 */ |
8084 | { Bad_Opcode }, |
8487 | { Bad_Opcode }, |
8085 | { Bad_Opcode }, |
8488 | { Bad_Opcode }, |
8086 | { Bad_Opcode }, |
8489 | { Bad_Opcode }, |
8087 | { Bad_Opcode }, |
8490 | { Bad_Opcode }, |
8088 | { Bad_Opcode }, |
8491 | { Bad_Opcode }, |
8089 | { Bad_Opcode }, |
8492 | { Bad_Opcode }, |
8090 | { Bad_Opcode }, |
8493 | { Bad_Opcode }, |
8091 | { Bad_Opcode }, |
8494 | { Bad_Opcode }, |
8092 | /* 48 */ |
8495 | /* 48 */ |
8093 | { Bad_Opcode }, |
8496 | { Bad_Opcode }, |
8094 | { Bad_Opcode }, |
8497 | { Bad_Opcode }, |
8095 | { Bad_Opcode }, |
8498 | { Bad_Opcode }, |
8096 | { Bad_Opcode }, |
8499 | { Bad_Opcode }, |
8097 | { Bad_Opcode }, |
8500 | { Bad_Opcode }, |
8098 | { Bad_Opcode }, |
8501 | { Bad_Opcode }, |
8099 | { Bad_Opcode }, |
8502 | { Bad_Opcode }, |
8100 | { Bad_Opcode }, |
8503 | { Bad_Opcode }, |
8101 | /* 50 */ |
8504 | /* 50 */ |
8102 | { Bad_Opcode }, |
8505 | { Bad_Opcode }, |
8103 | { Bad_Opcode }, |
8506 | { Bad_Opcode }, |
8104 | { Bad_Opcode }, |
8507 | { Bad_Opcode }, |
8105 | { Bad_Opcode }, |
8508 | { Bad_Opcode }, |
8106 | { Bad_Opcode }, |
8509 | { Bad_Opcode }, |
8107 | { Bad_Opcode }, |
8510 | { Bad_Opcode }, |
8108 | { Bad_Opcode }, |
8511 | { Bad_Opcode }, |
8109 | { Bad_Opcode }, |
8512 | { Bad_Opcode }, |
8110 | /* 58 */ |
8513 | /* 58 */ |
8111 | { Bad_Opcode }, |
8514 | { Bad_Opcode }, |
8112 | { Bad_Opcode }, |
8515 | { Bad_Opcode }, |
8113 | { Bad_Opcode }, |
8516 | { Bad_Opcode }, |
8114 | { Bad_Opcode }, |
8517 | { Bad_Opcode }, |
8115 | { Bad_Opcode }, |
8518 | { Bad_Opcode }, |
8116 | { Bad_Opcode }, |
8519 | { Bad_Opcode }, |
8117 | { Bad_Opcode }, |
8520 | { Bad_Opcode }, |
8118 | { Bad_Opcode }, |
8521 | { Bad_Opcode }, |
8119 | /* 60 */ |
8522 | /* 60 */ |
8120 | { Bad_Opcode }, |
8523 | { Bad_Opcode }, |
8121 | { Bad_Opcode }, |
8524 | { Bad_Opcode }, |
8122 | { Bad_Opcode }, |
8525 | { Bad_Opcode }, |
8123 | { Bad_Opcode }, |
8526 | { Bad_Opcode }, |
8124 | { Bad_Opcode }, |
8527 | { Bad_Opcode }, |
8125 | { Bad_Opcode }, |
8528 | { Bad_Opcode }, |
8126 | { Bad_Opcode }, |
8529 | { Bad_Opcode }, |
8127 | { Bad_Opcode }, |
8530 | { Bad_Opcode }, |
8128 | /* 68 */ |
8531 | /* 68 */ |
8129 | { Bad_Opcode }, |
8532 | { Bad_Opcode }, |
8130 | { Bad_Opcode }, |
8533 | { Bad_Opcode }, |
8131 | { Bad_Opcode }, |
8534 | { Bad_Opcode }, |
8132 | { Bad_Opcode }, |
8535 | { Bad_Opcode }, |
8133 | { Bad_Opcode }, |
8536 | { Bad_Opcode }, |
8134 | { Bad_Opcode }, |
8537 | { Bad_Opcode }, |
8135 | { Bad_Opcode }, |
8538 | { Bad_Opcode }, |
8136 | { Bad_Opcode }, |
8539 | { Bad_Opcode }, |
8137 | /* 70 */ |
8540 | /* 70 */ |
8138 | { Bad_Opcode }, |
8541 | { Bad_Opcode }, |
8139 | { Bad_Opcode }, |
8542 | { Bad_Opcode }, |
8140 | { Bad_Opcode }, |
8543 | { Bad_Opcode }, |
8141 | { Bad_Opcode }, |
8544 | { Bad_Opcode }, |
8142 | { Bad_Opcode }, |
8545 | { Bad_Opcode }, |
8143 | { Bad_Opcode }, |
8546 | { Bad_Opcode }, |
8144 | { Bad_Opcode }, |
8547 | { Bad_Opcode }, |
8145 | { Bad_Opcode }, |
8548 | { Bad_Opcode }, |
8146 | /* 78 */ |
8549 | /* 78 */ |
8147 | { Bad_Opcode }, |
8550 | { Bad_Opcode }, |
8148 | { Bad_Opcode }, |
8551 | { Bad_Opcode }, |
8149 | { Bad_Opcode }, |
8552 | { Bad_Opcode }, |
8150 | { Bad_Opcode }, |
8553 | { Bad_Opcode }, |
8151 | { Bad_Opcode }, |
8554 | { Bad_Opcode }, |
8152 | { Bad_Opcode }, |
8555 | { Bad_Opcode }, |
8153 | { Bad_Opcode }, |
8556 | { Bad_Opcode }, |
8154 | { Bad_Opcode }, |
8557 | { Bad_Opcode }, |
8155 | /* 80 */ |
8558 | /* 80 */ |
8156 | { Bad_Opcode }, |
8559 | { Bad_Opcode }, |
8157 | { Bad_Opcode }, |
8560 | { Bad_Opcode }, |
8158 | { Bad_Opcode }, |
8561 | { Bad_Opcode }, |
8159 | { Bad_Opcode }, |
8562 | { Bad_Opcode }, |
8160 | { Bad_Opcode }, |
8563 | { Bad_Opcode }, |
8161 | { Bad_Opcode }, |
8564 | { Bad_Opcode }, |
8162 | { Bad_Opcode }, |
8565 | { Bad_Opcode }, |
8163 | { Bad_Opcode }, |
8566 | { Bad_Opcode }, |
8164 | /* 88 */ |
8567 | /* 88 */ |
8165 | { Bad_Opcode }, |
8568 | { Bad_Opcode }, |
8166 | { Bad_Opcode }, |
8569 | { Bad_Opcode }, |
8167 | { Bad_Opcode }, |
8570 | { Bad_Opcode }, |
8168 | { Bad_Opcode }, |
8571 | { Bad_Opcode }, |
8169 | { Bad_Opcode }, |
8572 | { Bad_Opcode }, |
8170 | { Bad_Opcode }, |
8573 | { Bad_Opcode }, |
8171 | { Bad_Opcode }, |
8574 | { Bad_Opcode }, |
8172 | { Bad_Opcode }, |
8575 | { Bad_Opcode }, |
8173 | /* 90 */ |
8576 | /* 90 */ |
8174 | { Bad_Opcode }, |
8577 | { Bad_Opcode }, |
8175 | { Bad_Opcode }, |
8578 | { Bad_Opcode }, |
8176 | { Bad_Opcode }, |
8579 | { Bad_Opcode }, |
8177 | { Bad_Opcode }, |
8580 | { Bad_Opcode }, |
8178 | { Bad_Opcode }, |
8581 | { Bad_Opcode }, |
8179 | { Bad_Opcode }, |
8582 | { Bad_Opcode }, |
8180 | { Bad_Opcode }, |
8583 | { Bad_Opcode }, |
8181 | { Bad_Opcode }, |
8584 | { Bad_Opcode }, |
8182 | /* 98 */ |
8585 | /* 98 */ |
8183 | { Bad_Opcode }, |
8586 | { Bad_Opcode }, |
8184 | { Bad_Opcode }, |
8587 | { Bad_Opcode }, |
8185 | { Bad_Opcode }, |
8588 | { Bad_Opcode }, |
8186 | { Bad_Opcode }, |
8589 | { Bad_Opcode }, |
8187 | { Bad_Opcode }, |
8590 | { Bad_Opcode }, |
8188 | { Bad_Opcode }, |
8591 | { Bad_Opcode }, |
8189 | { Bad_Opcode }, |
8592 | { Bad_Opcode }, |
8190 | { Bad_Opcode }, |
8593 | { Bad_Opcode }, |
8191 | /* a0 */ |
8594 | /* a0 */ |
8192 | { Bad_Opcode }, |
8595 | { Bad_Opcode }, |
8193 | { Bad_Opcode }, |
8596 | { Bad_Opcode }, |
8194 | { Bad_Opcode }, |
8597 | { Bad_Opcode }, |
8195 | { Bad_Opcode }, |
8598 | { Bad_Opcode }, |
8196 | { Bad_Opcode }, |
8599 | { Bad_Opcode }, |
8197 | { Bad_Opcode }, |
8600 | { Bad_Opcode }, |
8198 | { Bad_Opcode }, |
8601 | { Bad_Opcode }, |
8199 | { Bad_Opcode }, |
8602 | { Bad_Opcode }, |
8200 | /* a8 */ |
8603 | /* a8 */ |
8201 | { Bad_Opcode }, |
8604 | { Bad_Opcode }, |
8202 | { Bad_Opcode }, |
8605 | { Bad_Opcode }, |
8203 | { Bad_Opcode }, |
8606 | { Bad_Opcode }, |
8204 | { Bad_Opcode }, |
8607 | { Bad_Opcode }, |
8205 | { Bad_Opcode }, |
8608 | { Bad_Opcode }, |
8206 | { Bad_Opcode }, |
8609 | { Bad_Opcode }, |
8207 | { Bad_Opcode }, |
8610 | { Bad_Opcode }, |
8208 | { Bad_Opcode }, |
8611 | { Bad_Opcode }, |
8209 | /* b0 */ |
8612 | /* b0 */ |
8210 | { Bad_Opcode }, |
8613 | { Bad_Opcode }, |
8211 | { Bad_Opcode }, |
8614 | { Bad_Opcode }, |
8212 | { Bad_Opcode }, |
8615 | { Bad_Opcode }, |
8213 | { Bad_Opcode }, |
8616 | { Bad_Opcode }, |
8214 | { Bad_Opcode }, |
8617 | { Bad_Opcode }, |
8215 | { Bad_Opcode }, |
8618 | { Bad_Opcode }, |
8216 | { Bad_Opcode }, |
8619 | { Bad_Opcode }, |
8217 | { Bad_Opcode }, |
8620 | { Bad_Opcode }, |
8218 | /* b8 */ |
8621 | /* b8 */ |
8219 | { Bad_Opcode }, |
8622 | { Bad_Opcode }, |
8220 | { Bad_Opcode }, |
8623 | { Bad_Opcode }, |
8221 | { Bad_Opcode }, |
8624 | { Bad_Opcode }, |
8222 | { Bad_Opcode }, |
8625 | { Bad_Opcode }, |
8223 | { Bad_Opcode }, |
8626 | { Bad_Opcode }, |
8224 | { Bad_Opcode }, |
8627 | { Bad_Opcode }, |
8225 | { Bad_Opcode }, |
8628 | { Bad_Opcode }, |
8226 | { Bad_Opcode }, |
8629 | { Bad_Opcode }, |
8227 | /* c0 */ |
8630 | /* c0 */ |
8228 | { Bad_Opcode }, |
8631 | { Bad_Opcode }, |
8229 | { Bad_Opcode }, |
8632 | { Bad_Opcode }, |
8230 | { Bad_Opcode }, |
8633 | { Bad_Opcode }, |
8231 | { Bad_Opcode }, |
8634 | { Bad_Opcode }, |
8232 | { Bad_Opcode }, |
8635 | { Bad_Opcode }, |
8233 | { Bad_Opcode }, |
8636 | { Bad_Opcode }, |
8234 | { Bad_Opcode }, |
8637 | { Bad_Opcode }, |
8235 | { Bad_Opcode }, |
8638 | { Bad_Opcode }, |
8236 | /* c8 */ |
8639 | /* c8 */ |
8237 | { Bad_Opcode }, |
8640 | { Bad_Opcode }, |
8238 | { Bad_Opcode }, |
8641 | { Bad_Opcode }, |
8239 | { Bad_Opcode }, |
8642 | { Bad_Opcode }, |
8240 | { Bad_Opcode }, |
8643 | { Bad_Opcode }, |
8241 | { Bad_Opcode }, |
8644 | { Bad_Opcode }, |
8242 | { Bad_Opcode }, |
8645 | { Bad_Opcode }, |
8243 | { Bad_Opcode }, |
8646 | { Bad_Opcode }, |
8244 | { Bad_Opcode }, |
8647 | { Bad_Opcode }, |
8245 | /* d0 */ |
8648 | /* d0 */ |
8246 | { Bad_Opcode }, |
8649 | { Bad_Opcode }, |
8247 | { Bad_Opcode }, |
8650 | { Bad_Opcode }, |
8248 | { Bad_Opcode }, |
8651 | { Bad_Opcode }, |
8249 | { Bad_Opcode }, |
8652 | { Bad_Opcode }, |
8250 | { Bad_Opcode }, |
8653 | { Bad_Opcode }, |
8251 | { Bad_Opcode }, |
8654 | { Bad_Opcode }, |
8252 | { Bad_Opcode }, |
8655 | { Bad_Opcode }, |
8253 | { Bad_Opcode }, |
8656 | { Bad_Opcode }, |
8254 | /* d8 */ |
8657 | /* d8 */ |
8255 | { Bad_Opcode }, |
8658 | { Bad_Opcode }, |
8256 | { Bad_Opcode }, |
8659 | { Bad_Opcode }, |
8257 | { Bad_Opcode }, |
8660 | { Bad_Opcode }, |
8258 | { Bad_Opcode }, |
8661 | { Bad_Opcode }, |
8259 | { Bad_Opcode }, |
8662 | { Bad_Opcode }, |
8260 | { Bad_Opcode }, |
8663 | { Bad_Opcode }, |
8261 | { Bad_Opcode }, |
8664 | { Bad_Opcode }, |
8262 | { Bad_Opcode }, |
8665 | { Bad_Opcode }, |
8263 | /* e0 */ |
8666 | /* e0 */ |
8264 | { Bad_Opcode }, |
8667 | { Bad_Opcode }, |
8265 | { Bad_Opcode }, |
8668 | { Bad_Opcode }, |
8266 | { Bad_Opcode }, |
8669 | { Bad_Opcode }, |
8267 | { Bad_Opcode }, |
8670 | { Bad_Opcode }, |
8268 | { Bad_Opcode }, |
8671 | { Bad_Opcode }, |
8269 | { Bad_Opcode }, |
8672 | { Bad_Opcode }, |
8270 | { Bad_Opcode }, |
8673 | { Bad_Opcode }, |
8271 | { Bad_Opcode }, |
8674 | { Bad_Opcode }, |
8272 | /* e8 */ |
8675 | /* e8 */ |
8273 | { Bad_Opcode }, |
8676 | { Bad_Opcode }, |
8274 | { Bad_Opcode }, |
8677 | { Bad_Opcode }, |
8275 | { Bad_Opcode }, |
8678 | { Bad_Opcode }, |
8276 | { Bad_Opcode }, |
8679 | { Bad_Opcode }, |
8277 | { Bad_Opcode }, |
8680 | { Bad_Opcode }, |
8278 | { Bad_Opcode }, |
8681 | { Bad_Opcode }, |
8279 | { Bad_Opcode }, |
8682 | { Bad_Opcode }, |
8280 | { Bad_Opcode }, |
8683 | { Bad_Opcode }, |
8281 | /* f0 */ |
8684 | /* f0 */ |
8282 | { Bad_Opcode }, |
8685 | { Bad_Opcode }, |
8283 | { Bad_Opcode }, |
8686 | { Bad_Opcode }, |
8284 | { Bad_Opcode }, |
8687 | { Bad_Opcode }, |
8285 | { Bad_Opcode }, |
8688 | { Bad_Opcode }, |
8286 | { Bad_Opcode }, |
8689 | { Bad_Opcode }, |
8287 | { Bad_Opcode }, |
8690 | { Bad_Opcode }, |
8288 | { Bad_Opcode }, |
8691 | { Bad_Opcode }, |
8289 | { Bad_Opcode }, |
8692 | { Bad_Opcode }, |
8290 | /* f8 */ |
8693 | /* f8 */ |
8291 | { Bad_Opcode }, |
8694 | { Bad_Opcode }, |
8292 | { Bad_Opcode }, |
8695 | { Bad_Opcode }, |
8293 | { Bad_Opcode }, |
8696 | { Bad_Opcode }, |
8294 | { Bad_Opcode }, |
8697 | { Bad_Opcode }, |
8295 | { Bad_Opcode }, |
8698 | { Bad_Opcode }, |
8296 | { Bad_Opcode }, |
8699 | { Bad_Opcode }, |
8297 | { Bad_Opcode }, |
8700 | { Bad_Opcode }, |
8298 | { Bad_Opcode }, |
8701 | { Bad_Opcode }, |
8299 | }, |
8702 | }, |
8300 | }; |
8703 | }; |
8301 | 8704 | ||
8302 | static const struct dis386 vex_table[][256] = { |
8705 | static const struct dis386 vex_table[][256] = { |
8303 | /* VEX_0F */ |
8706 | /* VEX_0F */ |
8304 | { |
8707 | { |
8305 | /* 00 */ |
8708 | /* 00 */ |
8306 | { Bad_Opcode }, |
8709 | { Bad_Opcode }, |
8307 | { Bad_Opcode }, |
8710 | { Bad_Opcode }, |
8308 | { Bad_Opcode }, |
8711 | { Bad_Opcode }, |
8309 | { Bad_Opcode }, |
8712 | { Bad_Opcode }, |
8310 | { Bad_Opcode }, |
8713 | { Bad_Opcode }, |
8311 | { Bad_Opcode }, |
8714 | { Bad_Opcode }, |
8312 | { Bad_Opcode }, |
8715 | { Bad_Opcode }, |
8313 | { Bad_Opcode }, |
8716 | { Bad_Opcode }, |
8314 | /* 08 */ |
8717 | /* 08 */ |
8315 | { Bad_Opcode }, |
8718 | { Bad_Opcode }, |
8316 | { Bad_Opcode }, |
8719 | { Bad_Opcode }, |
8317 | { Bad_Opcode }, |
8720 | { Bad_Opcode }, |
8318 | { Bad_Opcode }, |
8721 | { Bad_Opcode }, |
8319 | { Bad_Opcode }, |
8722 | { Bad_Opcode }, |
8320 | { Bad_Opcode }, |
8723 | { Bad_Opcode }, |
8321 | { Bad_Opcode }, |
8724 | { Bad_Opcode }, |
8322 | { Bad_Opcode }, |
8725 | { Bad_Opcode }, |
8323 | /* 10 */ |
8726 | /* 10 */ |
8324 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8727 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8325 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, |
8728 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, |
8326 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, |
8729 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, |
8327 | { MOD_TABLE (MOD_VEX_0F13) }, |
8730 | { MOD_TABLE (MOD_VEX_0F13) }, |
8328 | { VEX_W_TABLE (VEX_W_0F14) }, |
8731 | { VEX_W_TABLE (VEX_W_0F14) }, |
8329 | { VEX_W_TABLE (VEX_W_0F15) }, |
8732 | { VEX_W_TABLE (VEX_W_0F15) }, |
8330 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8733 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8331 | { MOD_TABLE (MOD_VEX_0F17) }, |
8734 | { MOD_TABLE (MOD_VEX_0F17) }, |
8332 | /* 18 */ |
8735 | /* 18 */ |
8333 | { Bad_Opcode }, |
8736 | { Bad_Opcode }, |
8334 | { Bad_Opcode }, |
8737 | { Bad_Opcode }, |
8335 | { Bad_Opcode }, |
8738 | { Bad_Opcode }, |
8336 | { Bad_Opcode }, |
8739 | { Bad_Opcode }, |
8337 | { Bad_Opcode }, |
8740 | { Bad_Opcode }, |
8338 | { Bad_Opcode }, |
8741 | { Bad_Opcode }, |
8339 | { Bad_Opcode }, |
8742 | { Bad_Opcode }, |
8340 | { Bad_Opcode }, |
8743 | { Bad_Opcode }, |
8341 | /* 20 */ |
8744 | /* 20 */ |
8342 | { Bad_Opcode }, |
8745 | { Bad_Opcode }, |
8343 | { Bad_Opcode }, |
8746 | { Bad_Opcode }, |
8344 | { Bad_Opcode }, |
8747 | { Bad_Opcode }, |
8345 | { Bad_Opcode }, |
8748 | { Bad_Opcode }, |
8346 | { Bad_Opcode }, |
8749 | { Bad_Opcode }, |
8347 | { Bad_Opcode }, |
8750 | { Bad_Opcode }, |
8348 | { Bad_Opcode }, |
8751 | { Bad_Opcode }, |
8349 | { Bad_Opcode }, |
8752 | { Bad_Opcode }, |
8350 | /* 28 */ |
8753 | /* 28 */ |
8351 | { VEX_W_TABLE (VEX_W_0F28) }, |
8754 | { VEX_W_TABLE (VEX_W_0F28) }, |
8352 | { VEX_W_TABLE (VEX_W_0F29) }, |
8755 | { VEX_W_TABLE (VEX_W_0F29) }, |
8353 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8354 | { MOD_TABLE (MOD_VEX_0F2B) }, |
8757 | { MOD_TABLE (MOD_VEX_0F2B) }, |
8355 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, |
8758 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, |
8356 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, |
8357 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, |
8760 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, |
8358 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, |
8359 | /* 30 */ |
8762 | /* 30 */ |
8360 | { Bad_Opcode }, |
8763 | { Bad_Opcode }, |
8361 | { Bad_Opcode }, |
8764 | { Bad_Opcode }, |
8362 | { Bad_Opcode }, |
8765 | { Bad_Opcode }, |
8363 | { Bad_Opcode }, |
8766 | { Bad_Opcode }, |
8364 | { Bad_Opcode }, |
8767 | { Bad_Opcode }, |
8365 | { Bad_Opcode }, |
8768 | { Bad_Opcode }, |
8366 | { Bad_Opcode }, |
8769 | { Bad_Opcode }, |
8367 | { Bad_Opcode }, |
8770 | { Bad_Opcode }, |
8368 | /* 38 */ |
8771 | /* 38 */ |
8369 | { Bad_Opcode }, |
8772 | { Bad_Opcode }, |
8370 | { Bad_Opcode }, |
8773 | { Bad_Opcode }, |
8371 | { Bad_Opcode }, |
8774 | { Bad_Opcode }, |
8372 | { Bad_Opcode }, |
8775 | { Bad_Opcode }, |
8373 | { Bad_Opcode }, |
8776 | { Bad_Opcode }, |
8374 | { Bad_Opcode }, |
8777 | { Bad_Opcode }, |
8375 | { Bad_Opcode }, |
8778 | { Bad_Opcode }, |
8376 | { Bad_Opcode }, |
8779 | { Bad_Opcode }, |
8377 | /* 40 */ |
8780 | /* 40 */ |
8378 | { Bad_Opcode }, |
8781 | { Bad_Opcode }, |
8379 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8782 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8380 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, |
8783 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, |
8381 | { Bad_Opcode }, |
8784 | { Bad_Opcode }, |
8382 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8785 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8383 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, |
8384 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, |
8385 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, |
8386 | /* 48 */ |
8789 | /* 48 */ |
8387 | { Bad_Opcode }, |
8790 | { Bad_Opcode }, |
8388 | { Bad_Opcode }, |
8791 | { Bad_Opcode }, |
8389 | { Bad_Opcode }, |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
8390 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
8391 | { Bad_Opcode }, |
8794 | { Bad_Opcode }, |
8392 | { Bad_Opcode }, |
8795 | { Bad_Opcode }, |
8393 | { Bad_Opcode }, |
8796 | { Bad_Opcode }, |
8394 | { Bad_Opcode }, |
8797 | { Bad_Opcode }, |
8395 | /* 50 */ |
8798 | /* 50 */ |
8396 | { MOD_TABLE (MOD_VEX_0F50) }, |
8799 | { MOD_TABLE (MOD_VEX_0F50) }, |
8397 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, |
8800 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, |
8398 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, |
8399 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, |
8802 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, |
8400 | { "vandpX", { XM, Vex, EXx } }, |
8803 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8401 | { "vandnpX", { XM, Vex, EXx } }, |
8804 | { "vandnpX", { XM, Vex, EXx }, 0 }, |
8402 | { "vorpX", { XM, Vex, EXx } }, |
8805 | { "vorpX", { XM, Vex, EXx }, 0 }, |
8403 | { "vxorpX", { XM, Vex, EXx } }, |
8806 | { "vxorpX", { XM, Vex, EXx }, 0 }, |
8404 | /* 58 */ |
8807 | /* 58 */ |
8405 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8406 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, |
8407 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, |
8810 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, |
8408 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, |
8811 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, |
8409 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, |
8812 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, |
8410 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, |
8813 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, |
8411 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, |
8814 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, |
8412 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, |
8815 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, |
8413 | /* 60 */ |
8816 | /* 60 */ |
8414 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8817 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8415 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, |
8818 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, |
8416 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, |
8819 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, |
8417 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, |
8820 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, |
8418 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, |
8821 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, |
8419 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, |
8822 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, |
8420 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, |
8823 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, |
8421 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, |
8824 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, |
8422 | /* 68 */ |
8825 | /* 68 */ |
8423 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8826 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8424 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, |
8827 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, |
8425 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, |
8828 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, |
8426 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, |
8829 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, |
8427 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, |
8830 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, |
8428 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, |
8831 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, |
8429 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, |
8832 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, |
8430 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, |
8833 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, |
8431 | /* 70 */ |
8834 | /* 70 */ |
8432 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8835 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8433 | { REG_TABLE (REG_VEX_0F71) }, |
8836 | { REG_TABLE (REG_VEX_0F71) }, |
8434 | { REG_TABLE (REG_VEX_0F72) }, |
8837 | { REG_TABLE (REG_VEX_0F72) }, |
8435 | { REG_TABLE (REG_VEX_0F73) }, |
8838 | { REG_TABLE (REG_VEX_0F73) }, |
8436 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, |
8839 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, |
8437 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, |
8840 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, |
8438 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, |
8841 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, |
8439 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, |
8842 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, |
8440 | /* 78 */ |
8843 | /* 78 */ |
8441 | { Bad_Opcode }, |
8844 | { Bad_Opcode }, |
8442 | { Bad_Opcode }, |
8845 | { Bad_Opcode }, |
8443 | { Bad_Opcode }, |
8846 | { Bad_Opcode }, |
8444 | { Bad_Opcode }, |
8847 | { Bad_Opcode }, |
8445 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8848 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8446 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, |
8849 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, |
8447 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, |
8850 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, |
8448 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, |
8851 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, |
8449 | /* 80 */ |
8852 | /* 80 */ |
8450 | { Bad_Opcode }, |
8853 | { Bad_Opcode }, |
8451 | { Bad_Opcode }, |
8854 | { Bad_Opcode }, |
8452 | { Bad_Opcode }, |
8855 | { Bad_Opcode }, |
8453 | { Bad_Opcode }, |
8856 | { Bad_Opcode }, |
8454 | { Bad_Opcode }, |
8857 | { Bad_Opcode }, |
8455 | { Bad_Opcode }, |
8858 | { Bad_Opcode }, |
8456 | { Bad_Opcode }, |
8859 | { Bad_Opcode }, |
8457 | { Bad_Opcode }, |
8860 | { Bad_Opcode }, |
8458 | /* 88 */ |
8861 | /* 88 */ |
8459 | { Bad_Opcode }, |
8862 | { Bad_Opcode }, |
8460 | { Bad_Opcode }, |
8863 | { Bad_Opcode }, |
8461 | { Bad_Opcode }, |
8864 | { Bad_Opcode }, |
8462 | { Bad_Opcode }, |
8865 | { Bad_Opcode }, |
8463 | { Bad_Opcode }, |
8866 | { Bad_Opcode }, |
8464 | { Bad_Opcode }, |
8867 | { Bad_Opcode }, |
8465 | { Bad_Opcode }, |
8868 | { Bad_Opcode }, |
8466 | { Bad_Opcode }, |
8869 | { Bad_Opcode }, |
8467 | /* 90 */ |
8870 | /* 90 */ |
8468 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8871 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8469 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, |
8872 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, |
8470 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, |
8873 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, |
8471 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, |
8874 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, |
8472 | { Bad_Opcode }, |
8875 | { Bad_Opcode }, |
8473 | { Bad_Opcode }, |
8876 | { Bad_Opcode }, |
8474 | { Bad_Opcode }, |
8877 | { Bad_Opcode }, |
8475 | { Bad_Opcode }, |
8878 | { Bad_Opcode }, |
8476 | /* 98 */ |
8879 | /* 98 */ |
8477 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
8880 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
8478 | { Bad_Opcode }, |
8881 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
8479 | { Bad_Opcode }, |
8882 | { Bad_Opcode }, |
8480 | { Bad_Opcode }, |
8883 | { Bad_Opcode }, |
8481 | { Bad_Opcode }, |
8884 | { Bad_Opcode }, |
8482 | { Bad_Opcode }, |
8885 | { Bad_Opcode }, |
8483 | { Bad_Opcode }, |
8886 | { Bad_Opcode }, |
8484 | { Bad_Opcode }, |
8887 | { Bad_Opcode }, |
8485 | /* a0 */ |
8888 | /* a0 */ |
8486 | { Bad_Opcode }, |
8889 | { Bad_Opcode }, |
8487 | { Bad_Opcode }, |
8890 | { Bad_Opcode }, |
8488 | { Bad_Opcode }, |
8891 | { Bad_Opcode }, |
8489 | { Bad_Opcode }, |
8892 | { Bad_Opcode }, |
8490 | { Bad_Opcode }, |
8893 | { Bad_Opcode }, |
8491 | { Bad_Opcode }, |
8894 | { Bad_Opcode }, |
8492 | { Bad_Opcode }, |
8895 | { Bad_Opcode }, |
8493 | { Bad_Opcode }, |
8896 | { Bad_Opcode }, |
8494 | /* a8 */ |
8897 | /* a8 */ |
8495 | { Bad_Opcode }, |
8898 | { Bad_Opcode }, |
8496 | { Bad_Opcode }, |
8899 | { Bad_Opcode }, |
8497 | { Bad_Opcode }, |
8900 | { Bad_Opcode }, |
8498 | { Bad_Opcode }, |
8901 | { Bad_Opcode }, |
8499 | { Bad_Opcode }, |
8902 | { Bad_Opcode }, |
8500 | { Bad_Opcode }, |
8903 | { Bad_Opcode }, |
8501 | { REG_TABLE (REG_VEX_0FAE) }, |
8904 | { REG_TABLE (REG_VEX_0FAE) }, |
8502 | { Bad_Opcode }, |
8905 | { Bad_Opcode }, |
8503 | /* b0 */ |
8906 | /* b0 */ |
8504 | { Bad_Opcode }, |
8907 | { Bad_Opcode }, |
8505 | { Bad_Opcode }, |
8908 | { Bad_Opcode }, |
8506 | { Bad_Opcode }, |
8909 | { Bad_Opcode }, |
8507 | { Bad_Opcode }, |
8910 | { Bad_Opcode }, |
8508 | { Bad_Opcode }, |
8911 | { Bad_Opcode }, |
8509 | { Bad_Opcode }, |
8912 | { Bad_Opcode }, |
8510 | { Bad_Opcode }, |
8913 | { Bad_Opcode }, |
8511 | { Bad_Opcode }, |
8914 | { Bad_Opcode }, |
8512 | /* b8 */ |
8915 | /* b8 */ |
8513 | { Bad_Opcode }, |
8916 | { Bad_Opcode }, |
8514 | { Bad_Opcode }, |
8917 | { Bad_Opcode }, |
8515 | { Bad_Opcode }, |
8918 | { Bad_Opcode }, |
8516 | { Bad_Opcode }, |
8919 | { Bad_Opcode }, |
8517 | { Bad_Opcode }, |
8920 | { Bad_Opcode }, |
8518 | { Bad_Opcode }, |
8921 | { Bad_Opcode }, |
8519 | { Bad_Opcode }, |
8922 | { Bad_Opcode }, |
8520 | { Bad_Opcode }, |
8923 | { Bad_Opcode }, |
8521 | /* c0 */ |
8924 | /* c0 */ |
8522 | { Bad_Opcode }, |
8925 | { Bad_Opcode }, |
8523 | { Bad_Opcode }, |
8926 | { Bad_Opcode }, |
8524 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
8927 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
8525 | { Bad_Opcode }, |
8928 | { Bad_Opcode }, |
8526 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8929 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8527 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, |
8930 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, |
8528 | { "vshufpX", { XM, Vex, EXx, Ib } }, |
8931 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
8529 | { Bad_Opcode }, |
8932 | { Bad_Opcode }, |
8530 | /* c8 */ |
8933 | /* c8 */ |
8531 | { Bad_Opcode }, |
8934 | { Bad_Opcode }, |
8532 | { Bad_Opcode }, |
8935 | { Bad_Opcode }, |
8533 | { Bad_Opcode }, |
8936 | { Bad_Opcode }, |
8534 | { Bad_Opcode }, |
8937 | { Bad_Opcode }, |
8535 | { Bad_Opcode }, |
8938 | { Bad_Opcode }, |
8536 | { Bad_Opcode }, |
8939 | { Bad_Opcode }, |
8537 | { Bad_Opcode }, |
8940 | { Bad_Opcode }, |
8538 | { Bad_Opcode }, |
8941 | { Bad_Opcode }, |
8539 | /* d0 */ |
8942 | /* d0 */ |
8540 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8943 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8541 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, |
8944 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, |
8542 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, |
8945 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, |
8543 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, |
8946 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, |
8544 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, |
8947 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, |
8545 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, |
8948 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, |
8546 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, |
8949 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, |
8547 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, |
8950 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, |
8548 | /* d8 */ |
8951 | /* d8 */ |
8549 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8952 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8550 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, |
8953 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, |
8551 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, |
8954 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, |
8552 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, |
8955 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, |
8553 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, |
8956 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, |
8554 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, |
8957 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, |
8555 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, |
8958 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, |
8556 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, |
8959 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, |
8557 | /* e0 */ |
8960 | /* e0 */ |
8558 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8961 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8559 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, |
8962 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, |
8560 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, |
8963 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, |
8561 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, |
8964 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, |
8562 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, |
8965 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, |
8563 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, |
8966 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, |
8564 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, |
8967 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, |
8565 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, |
8968 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, |
8566 | /* e8 */ |
8969 | /* e8 */ |
8567 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8970 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8568 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, |
8971 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, |
8569 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, |
8972 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, |
8570 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, |
8973 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, |
8571 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, |
8974 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, |
8572 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, |
8975 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, |
8573 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, |
8976 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, |
8574 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, |
8977 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, |
8575 | /* f0 */ |
8978 | /* f0 */ |
8576 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8979 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8577 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, |
8980 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, |
8578 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, |
8981 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, |
8579 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, |
8982 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, |
8580 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, |
8983 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, |
8581 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, |
8984 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, |
8582 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, |
8985 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, |
8583 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, |
8986 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, |
8584 | /* f8 */ |
8987 | /* f8 */ |
8585 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8988 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8586 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, |
8989 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, |
8587 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, |
8990 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, |
8588 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, |
8991 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, |
8589 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, |
8992 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, |
8590 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, |
8993 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, |
8591 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, |
8994 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, |
8592 | { Bad_Opcode }, |
8995 | { Bad_Opcode }, |
8593 | }, |
8996 | }, |
8594 | /* VEX_0F38 */ |
8997 | /* VEX_0F38 */ |
8595 | { |
8998 | { |
8596 | /* 00 */ |
8999 | /* 00 */ |
8597 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
9000 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8598 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, |
8599 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, |
8600 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, |
8601 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, |
9004 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, |
8602 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, |
8603 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, |
9006 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, |
8604 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, |
9007 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, |
8605 | /* 08 */ |
9008 | /* 08 */ |
8606 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
9009 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8607 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, |
9010 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, |
8608 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, |
8609 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, |
8610 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, |
9013 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, |
8611 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, |
8612 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, |
8613 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, |
8614 | /* 10 */ |
9017 | /* 10 */ |
8615 | { Bad_Opcode }, |
9018 | { Bad_Opcode }, |
8616 | { Bad_Opcode }, |
9019 | { Bad_Opcode }, |
8617 | { Bad_Opcode }, |
9020 | { Bad_Opcode }, |
8618 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
9021 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
8619 | { Bad_Opcode }, |
9022 | { Bad_Opcode }, |
8620 | { Bad_Opcode }, |
9023 | { Bad_Opcode }, |
8621 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
9024 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
8622 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
8623 | /* 18 */ |
9026 | /* 18 */ |
8624 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8625 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, |
9028 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, |
8626 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, |
9029 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, |
8627 | { Bad_Opcode }, |
9030 | { Bad_Opcode }, |
8628 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
9031 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8629 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, |
9032 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, |
8630 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, |
9033 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, |
8631 | { Bad_Opcode }, |
9034 | { Bad_Opcode }, |
8632 | /* 20 */ |
9035 | /* 20 */ |
8633 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
9036 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8634 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, |
9037 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, |
8635 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, |
9038 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, |
8636 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, |
9039 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, |
8637 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, |
9040 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, |
8638 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, |
9041 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, |
8639 | { Bad_Opcode }, |
9042 | { Bad_Opcode }, |
8640 | { Bad_Opcode }, |
9043 | { Bad_Opcode }, |
8641 | /* 28 */ |
9044 | /* 28 */ |
8642 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
9045 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8643 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, |
9046 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, |
8644 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, |
9047 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, |
8645 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, |
9048 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, |
8646 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, |
9049 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, |
8647 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, |
9050 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, |
8648 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, |
9051 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, |
8649 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, |
9052 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, |
8650 | /* 30 */ |
9053 | /* 30 */ |
8651 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
9054 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8652 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, |
9055 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, |
8653 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, |
9056 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, |
8654 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, |
9057 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, |
8655 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, |
9058 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, |
8656 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, |
9059 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, |
8657 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
9060 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
8658 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
9061 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
8659 | /* 38 */ |
9062 | /* 38 */ |
8660 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
9063 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8661 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, |
9064 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, |
8662 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, |
9065 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, |
8663 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, |
9066 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, |
8664 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, |
9067 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, |
8665 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, |
9068 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, |
8666 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, |
9069 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, |
8667 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, |
9070 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, |
8668 | /* 40 */ |
9071 | /* 40 */ |
8669 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
9072 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8670 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, |
9073 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, |
8671 | { Bad_Opcode }, |
9074 | { Bad_Opcode }, |
8672 | { Bad_Opcode }, |
9075 | { Bad_Opcode }, |
8673 | { Bad_Opcode }, |
9076 | { Bad_Opcode }, |
8674 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
9077 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8675 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, |
9078 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, |
8676 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, |
9079 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, |
8677 | /* 48 */ |
9080 | /* 48 */ |
8678 | { Bad_Opcode }, |
9081 | { Bad_Opcode }, |
8679 | { Bad_Opcode }, |
9082 | { Bad_Opcode }, |
8680 | { Bad_Opcode }, |
9083 | { Bad_Opcode }, |
8681 | { Bad_Opcode }, |
9084 | { Bad_Opcode }, |
8682 | { Bad_Opcode }, |
9085 | { Bad_Opcode }, |
8683 | { Bad_Opcode }, |
9086 | { Bad_Opcode }, |
8684 | { Bad_Opcode }, |
9087 | { Bad_Opcode }, |
8685 | { Bad_Opcode }, |
9088 | { Bad_Opcode }, |
8686 | /* 50 */ |
9089 | /* 50 */ |
8687 | { Bad_Opcode }, |
9090 | { Bad_Opcode }, |
8688 | { Bad_Opcode }, |
9091 | { Bad_Opcode }, |
8689 | { Bad_Opcode }, |
9092 | { Bad_Opcode }, |
8690 | { Bad_Opcode }, |
9093 | { Bad_Opcode }, |
8691 | { Bad_Opcode }, |
9094 | { Bad_Opcode }, |
8692 | { Bad_Opcode }, |
9095 | { Bad_Opcode }, |
8693 | { Bad_Opcode }, |
9096 | { Bad_Opcode }, |
8694 | { Bad_Opcode }, |
9097 | { Bad_Opcode }, |
8695 | /* 58 */ |
9098 | /* 58 */ |
8696 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
9099 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8697 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, |
9100 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, |
8698 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, |
9101 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, |
8699 | { Bad_Opcode }, |
9102 | { Bad_Opcode }, |
8700 | { Bad_Opcode }, |
9103 | { Bad_Opcode }, |
8701 | { Bad_Opcode }, |
9104 | { Bad_Opcode }, |
8702 | { Bad_Opcode }, |
9105 | { Bad_Opcode }, |
8703 | { Bad_Opcode }, |
9106 | { Bad_Opcode }, |
8704 | /* 60 */ |
9107 | /* 60 */ |
8705 | { Bad_Opcode }, |
9108 | { Bad_Opcode }, |
8706 | { Bad_Opcode }, |
9109 | { Bad_Opcode }, |
8707 | { Bad_Opcode }, |
9110 | { Bad_Opcode }, |
8708 | { Bad_Opcode }, |
9111 | { Bad_Opcode }, |
8709 | { Bad_Opcode }, |
9112 | { Bad_Opcode }, |
8710 | { Bad_Opcode }, |
9113 | { Bad_Opcode }, |
8711 | { Bad_Opcode }, |
9114 | { Bad_Opcode }, |
8712 | { Bad_Opcode }, |
9115 | { Bad_Opcode }, |
8713 | /* 68 */ |
9116 | /* 68 */ |
8714 | { Bad_Opcode }, |
9117 | { Bad_Opcode }, |
8715 | { Bad_Opcode }, |
9118 | { Bad_Opcode }, |
8716 | { Bad_Opcode }, |
9119 | { Bad_Opcode }, |
8717 | { Bad_Opcode }, |
9120 | { Bad_Opcode }, |
8718 | { Bad_Opcode }, |
9121 | { Bad_Opcode }, |
8719 | { Bad_Opcode }, |
9122 | { Bad_Opcode }, |
8720 | { Bad_Opcode }, |
9123 | { Bad_Opcode }, |
8721 | { Bad_Opcode }, |
9124 | { Bad_Opcode }, |
8722 | /* 70 */ |
9125 | /* 70 */ |
8723 | { Bad_Opcode }, |
9126 | { Bad_Opcode }, |
8724 | { Bad_Opcode }, |
9127 | { Bad_Opcode }, |
8725 | { Bad_Opcode }, |
9128 | { Bad_Opcode }, |
8726 | { Bad_Opcode }, |
9129 | { Bad_Opcode }, |
8727 | { Bad_Opcode }, |
9130 | { Bad_Opcode }, |
8728 | { Bad_Opcode }, |
9131 | { Bad_Opcode }, |
8729 | { Bad_Opcode }, |
9132 | { Bad_Opcode }, |
8730 | { Bad_Opcode }, |
9133 | { Bad_Opcode }, |
8731 | /* 78 */ |
9134 | /* 78 */ |
8732 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
9135 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8733 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, |
9136 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, |
8734 | { Bad_Opcode }, |
9137 | { Bad_Opcode }, |
8735 | { Bad_Opcode }, |
9138 | { Bad_Opcode }, |
8736 | { Bad_Opcode }, |
9139 | { Bad_Opcode }, |
8737 | { Bad_Opcode }, |
9140 | { Bad_Opcode }, |
8738 | { Bad_Opcode }, |
9141 | { Bad_Opcode }, |
8739 | { Bad_Opcode }, |
9142 | { Bad_Opcode }, |
8740 | /* 80 */ |
9143 | /* 80 */ |
8741 | { Bad_Opcode }, |
9144 | { Bad_Opcode }, |
8742 | { Bad_Opcode }, |
9145 | { Bad_Opcode }, |
8743 | { Bad_Opcode }, |
9146 | { Bad_Opcode }, |
8744 | { Bad_Opcode }, |
9147 | { Bad_Opcode }, |
8745 | { Bad_Opcode }, |
9148 | { Bad_Opcode }, |
8746 | { Bad_Opcode }, |
9149 | { Bad_Opcode }, |
8747 | { Bad_Opcode }, |
9150 | { Bad_Opcode }, |
8748 | { Bad_Opcode }, |
9151 | { Bad_Opcode }, |
8749 | /* 88 */ |
9152 | /* 88 */ |
8750 | { Bad_Opcode }, |
9153 | { Bad_Opcode }, |
8751 | { Bad_Opcode }, |
9154 | { Bad_Opcode }, |
8752 | { Bad_Opcode }, |
9155 | { Bad_Opcode }, |
8753 | { Bad_Opcode }, |
9156 | { Bad_Opcode }, |
8754 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
9157 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
8755 | { Bad_Opcode }, |
9158 | { Bad_Opcode }, |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
9159 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
8757 | { Bad_Opcode }, |
9160 | { Bad_Opcode }, |
8758 | /* 90 */ |
9161 | /* 90 */ |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
9162 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8760 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, |
9163 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, |
9164 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, |
8762 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, |
9165 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, |
8763 | { Bad_Opcode }, |
9166 | { Bad_Opcode }, |
8764 | { Bad_Opcode }, |
9167 | { Bad_Opcode }, |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
9168 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, |
9169 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, |
8767 | /* 98 */ |
9170 | /* 98 */ |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
9171 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8769 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, |
9172 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, |
9173 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, |
8771 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, |
9174 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, |
8772 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, |
9175 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, |
8773 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, |
9176 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, |
8774 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, |
9177 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, |
9178 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, |
8776 | /* a0 */ |
9179 | /* a0 */ |
8777 | { Bad_Opcode }, |
9180 | { Bad_Opcode }, |
8778 | { Bad_Opcode }, |
9181 | { Bad_Opcode }, |
8779 | { Bad_Opcode }, |
9182 | { Bad_Opcode }, |
8780 | { Bad_Opcode }, |
9183 | { Bad_Opcode }, |
8781 | { Bad_Opcode }, |
9184 | { Bad_Opcode }, |
8782 | { Bad_Opcode }, |
9185 | { Bad_Opcode }, |
8783 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
9186 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8784 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, |
9187 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, |
8785 | /* a8 */ |
9188 | /* a8 */ |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
9189 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, |
9190 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, |
9191 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, |
8789 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, |
9192 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, |
8790 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, |
9193 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, |
8791 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, |
9194 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, |
9195 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, |
9196 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, |
8794 | /* b0 */ |
9197 | /* b0 */ |
8795 | { Bad_Opcode }, |
9198 | { Bad_Opcode }, |
8796 | { Bad_Opcode }, |
9199 | { Bad_Opcode }, |
8797 | { Bad_Opcode }, |
9200 | { Bad_Opcode }, |
8798 | { Bad_Opcode }, |
9201 | { Bad_Opcode }, |
8799 | { Bad_Opcode }, |
9202 | { Bad_Opcode }, |
8800 | { Bad_Opcode }, |
9203 | { Bad_Opcode }, |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
9204 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8802 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, |
9205 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, |
8803 | /* b8 */ |
9206 | /* b8 */ |
8804 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
9207 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8805 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, |
9208 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, |
8806 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, |
9209 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, |
9210 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, |
9211 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, |
9212 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, |
8810 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, |
9213 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, |
8811 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, |
9214 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, |
8812 | /* c0 */ |
9215 | /* c0 */ |
8813 | { Bad_Opcode }, |
9216 | { Bad_Opcode }, |
8814 | { Bad_Opcode }, |
9217 | { Bad_Opcode }, |
8815 | { Bad_Opcode }, |
9218 | { Bad_Opcode }, |
8816 | { Bad_Opcode }, |
9219 | { Bad_Opcode }, |
8817 | { Bad_Opcode }, |
9220 | { Bad_Opcode }, |
8818 | { Bad_Opcode }, |
9221 | { Bad_Opcode }, |
8819 | { Bad_Opcode }, |
9222 | { Bad_Opcode }, |
8820 | { Bad_Opcode }, |
9223 | { Bad_Opcode }, |
8821 | /* c8 */ |
9224 | /* c8 */ |
8822 | { Bad_Opcode }, |
9225 | { Bad_Opcode }, |
8823 | { Bad_Opcode }, |
9226 | { Bad_Opcode }, |
8824 | { Bad_Opcode }, |
9227 | { Bad_Opcode }, |
8825 | { Bad_Opcode }, |
9228 | { Bad_Opcode }, |
8826 | { Bad_Opcode }, |
9229 | { Bad_Opcode }, |
8827 | { Bad_Opcode }, |
9230 | { Bad_Opcode }, |
8828 | { Bad_Opcode }, |
9231 | { Bad_Opcode }, |
8829 | { Bad_Opcode }, |
9232 | { Bad_Opcode }, |
8830 | /* d0 */ |
9233 | /* d0 */ |
8831 | { Bad_Opcode }, |
9234 | { Bad_Opcode }, |
8832 | { Bad_Opcode }, |
9235 | { Bad_Opcode }, |
8833 | { Bad_Opcode }, |
9236 | { Bad_Opcode }, |
8834 | { Bad_Opcode }, |
9237 | { Bad_Opcode }, |
8835 | { Bad_Opcode }, |
9238 | { Bad_Opcode }, |
8836 | { Bad_Opcode }, |
9239 | { Bad_Opcode }, |
8837 | { Bad_Opcode }, |
9240 | { Bad_Opcode }, |
8838 | { Bad_Opcode }, |
9241 | { Bad_Opcode }, |
8839 | /* d8 */ |
9242 | /* d8 */ |
8840 | { Bad_Opcode }, |
9243 | { Bad_Opcode }, |
8841 | { Bad_Opcode }, |
9244 | { Bad_Opcode }, |
8842 | { Bad_Opcode }, |
9245 | { Bad_Opcode }, |
8843 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9246 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8844 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, |
9247 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, |
8845 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, |
9248 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, |
8846 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, |
9249 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, |
8847 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, |
9250 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, |
8848 | /* e0 */ |
9251 | /* e0 */ |
8849 | { Bad_Opcode }, |
9252 | { Bad_Opcode }, |
8850 | { Bad_Opcode }, |
9253 | { Bad_Opcode }, |
8851 | { Bad_Opcode }, |
9254 | { Bad_Opcode }, |
8852 | { Bad_Opcode }, |
9255 | { Bad_Opcode }, |
8853 | { Bad_Opcode }, |
9256 | { Bad_Opcode }, |
8854 | { Bad_Opcode }, |
9257 | { Bad_Opcode }, |
8855 | { Bad_Opcode }, |
9258 | { Bad_Opcode }, |
8856 | { Bad_Opcode }, |
9259 | { Bad_Opcode }, |
8857 | /* e8 */ |
9260 | /* e8 */ |
8858 | { Bad_Opcode }, |
9261 | { Bad_Opcode }, |
8859 | { Bad_Opcode }, |
9262 | { Bad_Opcode }, |
8860 | { Bad_Opcode }, |
9263 | { Bad_Opcode }, |
8861 | { Bad_Opcode }, |
9264 | { Bad_Opcode }, |
8862 | { Bad_Opcode }, |
9265 | { Bad_Opcode }, |
8863 | { Bad_Opcode }, |
9266 | { Bad_Opcode }, |
8864 | { Bad_Opcode }, |
9267 | { Bad_Opcode }, |
8865 | { Bad_Opcode }, |
9268 | { Bad_Opcode }, |
8866 | /* f0 */ |
9269 | /* f0 */ |
8867 | { Bad_Opcode }, |
9270 | { Bad_Opcode }, |
8868 | { Bad_Opcode }, |
9271 | { Bad_Opcode }, |
8869 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9272 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8870 | { REG_TABLE (REG_VEX_0F38F3) }, |
9273 | { REG_TABLE (REG_VEX_0F38F3) }, |
8871 | { Bad_Opcode }, |
9274 | { Bad_Opcode }, |
8872 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9275 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8873 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, |
9276 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, |
8874 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
9277 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
8875 | /* f8 */ |
9278 | /* f8 */ |
8876 | { Bad_Opcode }, |
9279 | { Bad_Opcode }, |
8877 | { Bad_Opcode }, |
9280 | { Bad_Opcode }, |
8878 | { Bad_Opcode }, |
9281 | { Bad_Opcode }, |
8879 | { Bad_Opcode }, |
9282 | { Bad_Opcode }, |
8880 | { Bad_Opcode }, |
9283 | { Bad_Opcode }, |
8881 | { Bad_Opcode }, |
9284 | { Bad_Opcode }, |
8882 | { Bad_Opcode }, |
9285 | { Bad_Opcode }, |
8883 | { Bad_Opcode }, |
9286 | { Bad_Opcode }, |
8884 | }, |
9287 | }, |
8885 | /* VEX_0F3A */ |
9288 | /* VEX_0F3A */ |
8886 | { |
9289 | { |
8887 | /* 00 */ |
9290 | /* 00 */ |
8888 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9291 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8889 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, |
9292 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, |
9293 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, |
8891 | { Bad_Opcode }, |
9294 | { Bad_Opcode }, |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9295 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8893 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, |
9296 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, |
8894 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, |
9297 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, |
8895 | { Bad_Opcode }, |
9298 | { Bad_Opcode }, |
8896 | /* 08 */ |
9299 | /* 08 */ |
8897 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9300 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8898 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, |
9301 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, |
8899 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, |
9302 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, |
8900 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, |
9303 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, |
9304 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, |
8902 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, |
9305 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, |
9306 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, |
8904 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, |
9307 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, |
8905 | /* 10 */ |
9308 | /* 10 */ |
8906 | { Bad_Opcode }, |
9309 | { Bad_Opcode }, |
8907 | { Bad_Opcode }, |
9310 | { Bad_Opcode }, |
8908 | { Bad_Opcode }, |
9311 | { Bad_Opcode }, |
8909 | { Bad_Opcode }, |
9312 | { Bad_Opcode }, |
8910 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9313 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
8911 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, |
9314 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, |
8912 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, |
9315 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, |
8913 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, |
9316 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, |
8914 | /* 18 */ |
9317 | /* 18 */ |
8915 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9318 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
8916 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, |
9319 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, |
8917 | { Bad_Opcode }, |
9320 | { Bad_Opcode }, |
8918 | { Bad_Opcode }, |
9321 | { Bad_Opcode }, |
8919 | { Bad_Opcode }, |
9322 | { Bad_Opcode }, |
8920 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
9323 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
8921 | { Bad_Opcode }, |
9324 | { Bad_Opcode }, |
8922 | { Bad_Opcode }, |
9325 | { Bad_Opcode }, |
8923 | /* 20 */ |
9326 | /* 20 */ |
8924 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9327 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
8925 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, |
9328 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, |
8926 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, |
9329 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, |
8927 | { Bad_Opcode }, |
9330 | { Bad_Opcode }, |
8928 | { Bad_Opcode }, |
9331 | { Bad_Opcode }, |
8929 | { Bad_Opcode }, |
9332 | { Bad_Opcode }, |
8930 | { Bad_Opcode }, |
9333 | { Bad_Opcode }, |
8931 | { Bad_Opcode }, |
9334 | { Bad_Opcode }, |
8932 | /* 28 */ |
9335 | /* 28 */ |
8933 | { Bad_Opcode }, |
9336 | { Bad_Opcode }, |
8934 | { Bad_Opcode }, |
9337 | { Bad_Opcode }, |
8935 | { Bad_Opcode }, |
9338 | { Bad_Opcode }, |
8936 | { Bad_Opcode }, |
9339 | { Bad_Opcode }, |
8937 | { Bad_Opcode }, |
9340 | { Bad_Opcode }, |
8938 | { Bad_Opcode }, |
9341 | { Bad_Opcode }, |
8939 | { Bad_Opcode }, |
9342 | { Bad_Opcode }, |
8940 | { Bad_Opcode }, |
9343 | { Bad_Opcode }, |
8941 | /* 30 */ |
9344 | /* 30 */ |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
9345 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
8943 | { Bad_Opcode }, |
9346 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
9347 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
8945 | { Bad_Opcode }, |
9348 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
8946 | { Bad_Opcode }, |
9349 | { Bad_Opcode }, |
8947 | { Bad_Opcode }, |
9350 | { Bad_Opcode }, |
8948 | { Bad_Opcode }, |
9351 | { Bad_Opcode }, |
8949 | { Bad_Opcode }, |
9352 | { Bad_Opcode }, |
8950 | /* 38 */ |
9353 | /* 38 */ |
8951 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9354 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
8952 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, |
9355 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, |
8953 | { Bad_Opcode }, |
9356 | { Bad_Opcode }, |
8954 | { Bad_Opcode }, |
9357 | { Bad_Opcode }, |
8955 | { Bad_Opcode }, |
9358 | { Bad_Opcode }, |
8956 | { Bad_Opcode }, |
9359 | { Bad_Opcode }, |
8957 | { Bad_Opcode }, |
9360 | { Bad_Opcode }, |
8958 | { Bad_Opcode }, |
9361 | { Bad_Opcode }, |
8959 | /* 40 */ |
9362 | /* 40 */ |
8960 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9363 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
8961 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, |
9364 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, |
8962 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, |
9365 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, |
8963 | { Bad_Opcode }, |
9366 | { Bad_Opcode }, |
8964 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
9367 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
8965 | { Bad_Opcode }, |
9368 | { Bad_Opcode }, |
8966 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
9369 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
8967 | { Bad_Opcode }, |
9370 | { Bad_Opcode }, |
8968 | /* 48 */ |
9371 | /* 48 */ |
8969 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9372 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
8970 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, |
9373 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, |
8971 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, |
9374 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, |
8972 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, |
9375 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, |
8973 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, |
9376 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, |
8974 | { Bad_Opcode }, |
9377 | { Bad_Opcode }, |
8975 | { Bad_Opcode }, |
9378 | { Bad_Opcode }, |
8976 | { Bad_Opcode }, |
9379 | { Bad_Opcode }, |
8977 | /* 50 */ |
9380 | /* 50 */ |
8978 | { Bad_Opcode }, |
9381 | { Bad_Opcode }, |
8979 | { Bad_Opcode }, |
9382 | { Bad_Opcode }, |
8980 | { Bad_Opcode }, |
9383 | { Bad_Opcode }, |
8981 | { Bad_Opcode }, |
9384 | { Bad_Opcode }, |
8982 | { Bad_Opcode }, |
9385 | { Bad_Opcode }, |
8983 | { Bad_Opcode }, |
9386 | { Bad_Opcode }, |
8984 | { Bad_Opcode }, |
9387 | { Bad_Opcode }, |
8985 | { Bad_Opcode }, |
9388 | { Bad_Opcode }, |
8986 | /* 58 */ |
9389 | /* 58 */ |
8987 | { Bad_Opcode }, |
9390 | { Bad_Opcode }, |
8988 | { Bad_Opcode }, |
9391 | { Bad_Opcode }, |
8989 | { Bad_Opcode }, |
9392 | { Bad_Opcode }, |
8990 | { Bad_Opcode }, |
9393 | { Bad_Opcode }, |
8991 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9394 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
8992 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, |
9395 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, |
8993 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, |
9396 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, |
8994 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, |
9397 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, |
8995 | /* 60 */ |
9398 | /* 60 */ |
8996 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9399 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
8997 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, |
9400 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, |
9401 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, |
8999 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, |
9402 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, |
9000 | { Bad_Opcode }, |
9403 | { Bad_Opcode }, |
9001 | { Bad_Opcode }, |
9404 | { Bad_Opcode }, |
9002 | { Bad_Opcode }, |
9405 | { Bad_Opcode }, |
9003 | { Bad_Opcode }, |
9406 | { Bad_Opcode }, |
9004 | /* 68 */ |
9407 | /* 68 */ |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9408 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9006 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, |
9409 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, |
9007 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, |
9410 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, |
9008 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, |
9411 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, |
9009 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, |
9412 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, |
9010 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, |
9413 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, |
9414 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, |
9415 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, |
9013 | /* 70 */ |
9416 | /* 70 */ |
9014 | { Bad_Opcode }, |
9417 | { Bad_Opcode }, |
9015 | { Bad_Opcode }, |
9418 | { Bad_Opcode }, |
9016 | { Bad_Opcode }, |
9419 | { Bad_Opcode }, |
9017 | { Bad_Opcode }, |
9420 | { Bad_Opcode }, |
9018 | { Bad_Opcode }, |
9421 | { Bad_Opcode }, |
9019 | { Bad_Opcode }, |
9422 | { Bad_Opcode }, |
9020 | { Bad_Opcode }, |
9423 | { Bad_Opcode }, |
9021 | { Bad_Opcode }, |
9424 | { Bad_Opcode }, |
9022 | /* 78 */ |
9425 | /* 78 */ |
9023 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9426 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9024 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, |
9427 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, |
9428 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, |
9026 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, |
9429 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, |
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, |
9430 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, |
9028 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, |
9431 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, |
9029 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, |
9432 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, |
9030 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, |
9433 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, |
9031 | /* 80 */ |
9434 | /* 80 */ |
9032 | { Bad_Opcode }, |
9435 | { Bad_Opcode }, |
9033 | { Bad_Opcode }, |
9436 | { Bad_Opcode }, |
9034 | { Bad_Opcode }, |
9437 | { Bad_Opcode }, |
9035 | { Bad_Opcode }, |
9438 | { Bad_Opcode }, |
9036 | { Bad_Opcode }, |
9439 | { Bad_Opcode }, |
9037 | { Bad_Opcode }, |
9440 | { Bad_Opcode }, |
9038 | { Bad_Opcode }, |
9441 | { Bad_Opcode }, |
9039 | { Bad_Opcode }, |
9442 | { Bad_Opcode }, |
9040 | /* 88 */ |
9443 | /* 88 */ |
9041 | { Bad_Opcode }, |
9444 | { Bad_Opcode }, |
9042 | { Bad_Opcode }, |
9445 | { Bad_Opcode }, |
9043 | { Bad_Opcode }, |
9446 | { Bad_Opcode }, |
9044 | { Bad_Opcode }, |
9447 | { Bad_Opcode }, |
9045 | { Bad_Opcode }, |
9448 | { Bad_Opcode }, |
9046 | { Bad_Opcode }, |
9449 | { Bad_Opcode }, |
9047 | { Bad_Opcode }, |
9450 | { Bad_Opcode }, |
9048 | { Bad_Opcode }, |
9451 | { Bad_Opcode }, |
9049 | /* 90 */ |
9452 | /* 90 */ |
9050 | { Bad_Opcode }, |
9453 | { Bad_Opcode }, |
9051 | { Bad_Opcode }, |
9454 | { Bad_Opcode }, |
9052 | { Bad_Opcode }, |
9455 | { Bad_Opcode }, |
9053 | { Bad_Opcode }, |
9456 | { Bad_Opcode }, |
9054 | { Bad_Opcode }, |
9457 | { Bad_Opcode }, |
9055 | { Bad_Opcode }, |
9458 | { Bad_Opcode }, |
9056 | { Bad_Opcode }, |
9459 | { Bad_Opcode }, |
9057 | { Bad_Opcode }, |
9460 | { Bad_Opcode }, |
9058 | /* 98 */ |
9461 | /* 98 */ |
9059 | { Bad_Opcode }, |
9462 | { Bad_Opcode }, |
9060 | { Bad_Opcode }, |
9463 | { Bad_Opcode }, |
9061 | { Bad_Opcode }, |
9464 | { Bad_Opcode }, |
9062 | { Bad_Opcode }, |
9465 | { Bad_Opcode }, |
9063 | { Bad_Opcode }, |
9466 | { Bad_Opcode }, |
9064 | { Bad_Opcode }, |
9467 | { Bad_Opcode }, |
9065 | { Bad_Opcode }, |
9468 | { Bad_Opcode }, |
9066 | { Bad_Opcode }, |
9469 | { Bad_Opcode }, |
9067 | /* a0 */ |
9470 | /* a0 */ |
9068 | { Bad_Opcode }, |
9471 | { Bad_Opcode }, |
9069 | { Bad_Opcode }, |
9472 | { Bad_Opcode }, |
9070 | { Bad_Opcode }, |
9473 | { Bad_Opcode }, |
9071 | { Bad_Opcode }, |
9474 | { Bad_Opcode }, |
9072 | { Bad_Opcode }, |
9475 | { Bad_Opcode }, |
9073 | { Bad_Opcode }, |
9476 | { Bad_Opcode }, |
9074 | { Bad_Opcode }, |
9477 | { Bad_Opcode }, |
9075 | { Bad_Opcode }, |
9478 | { Bad_Opcode }, |
9076 | /* a8 */ |
9479 | /* a8 */ |
9077 | { Bad_Opcode }, |
9480 | { Bad_Opcode }, |
9078 | { Bad_Opcode }, |
9481 | { Bad_Opcode }, |
9079 | { Bad_Opcode }, |
9482 | { Bad_Opcode }, |
9080 | { Bad_Opcode }, |
9483 | { Bad_Opcode }, |
9081 | { Bad_Opcode }, |
9484 | { Bad_Opcode }, |
9082 | { Bad_Opcode }, |
9485 | { Bad_Opcode }, |
9083 | { Bad_Opcode }, |
9486 | { Bad_Opcode }, |
9084 | { Bad_Opcode }, |
9487 | { Bad_Opcode }, |
9085 | /* b0 */ |
9488 | /* b0 */ |
9086 | { Bad_Opcode }, |
9489 | { Bad_Opcode }, |
9087 | { Bad_Opcode }, |
9490 | { Bad_Opcode }, |
9088 | { Bad_Opcode }, |
9491 | { Bad_Opcode }, |
9089 | { Bad_Opcode }, |
9492 | { Bad_Opcode }, |
9090 | { Bad_Opcode }, |
9493 | { Bad_Opcode }, |
9091 | { Bad_Opcode }, |
9494 | { Bad_Opcode }, |
9092 | { Bad_Opcode }, |
9495 | { Bad_Opcode }, |
9093 | { Bad_Opcode }, |
9496 | { Bad_Opcode }, |
9094 | /* b8 */ |
9497 | /* b8 */ |
9095 | { Bad_Opcode }, |
9498 | { Bad_Opcode }, |
9096 | { Bad_Opcode }, |
9499 | { Bad_Opcode }, |
9097 | { Bad_Opcode }, |
9500 | { Bad_Opcode }, |
9098 | { Bad_Opcode }, |
9501 | { Bad_Opcode }, |
9099 | { Bad_Opcode }, |
9502 | { Bad_Opcode }, |
9100 | { Bad_Opcode }, |
9503 | { Bad_Opcode }, |
9101 | { Bad_Opcode }, |
9504 | { Bad_Opcode }, |
9102 | { Bad_Opcode }, |
9505 | { Bad_Opcode }, |
9103 | /* c0 */ |
9506 | /* c0 */ |
9104 | { Bad_Opcode }, |
9507 | { Bad_Opcode }, |
9105 | { Bad_Opcode }, |
9508 | { Bad_Opcode }, |
9106 | { Bad_Opcode }, |
9509 | { Bad_Opcode }, |
9107 | { Bad_Opcode }, |
9510 | { Bad_Opcode }, |
9108 | { Bad_Opcode }, |
9511 | { Bad_Opcode }, |
9109 | { Bad_Opcode }, |
9512 | { Bad_Opcode }, |
9110 | { Bad_Opcode }, |
9513 | { Bad_Opcode }, |
9111 | { Bad_Opcode }, |
9514 | { Bad_Opcode }, |
9112 | /* c8 */ |
9515 | /* c8 */ |
9113 | { Bad_Opcode }, |
9516 | { Bad_Opcode }, |
9114 | { Bad_Opcode }, |
9517 | { Bad_Opcode }, |
9115 | { Bad_Opcode }, |
9518 | { Bad_Opcode }, |
9116 | { Bad_Opcode }, |
9519 | { Bad_Opcode }, |
9117 | { Bad_Opcode }, |
9520 | { Bad_Opcode }, |
9118 | { Bad_Opcode }, |
9521 | { Bad_Opcode }, |
9119 | { Bad_Opcode }, |
9522 | { Bad_Opcode }, |
9120 | { Bad_Opcode }, |
9523 | { Bad_Opcode }, |
9121 | /* d0 */ |
9524 | /* d0 */ |
9122 | { Bad_Opcode }, |
9525 | { Bad_Opcode }, |
9123 | { Bad_Opcode }, |
9526 | { Bad_Opcode }, |
9124 | { Bad_Opcode }, |
9527 | { Bad_Opcode }, |
9125 | { Bad_Opcode }, |
9528 | { Bad_Opcode }, |
9126 | { Bad_Opcode }, |
9529 | { Bad_Opcode }, |
9127 | { Bad_Opcode }, |
9530 | { Bad_Opcode }, |
9128 | { Bad_Opcode }, |
9531 | { Bad_Opcode }, |
9129 | { Bad_Opcode }, |
9532 | { Bad_Opcode }, |
9130 | /* d8 */ |
9533 | /* d8 */ |
9131 | { Bad_Opcode }, |
9534 | { Bad_Opcode }, |
9132 | { Bad_Opcode }, |
9535 | { Bad_Opcode }, |
9133 | { Bad_Opcode }, |
9536 | { Bad_Opcode }, |
9134 | { Bad_Opcode }, |
9537 | { Bad_Opcode }, |
9135 | { Bad_Opcode }, |
9538 | { Bad_Opcode }, |
9136 | { Bad_Opcode }, |
9539 | { Bad_Opcode }, |
9137 | { Bad_Opcode }, |
9540 | { Bad_Opcode }, |
9138 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
9541 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
9139 | /* e0 */ |
9542 | /* e0 */ |
9140 | { Bad_Opcode }, |
9543 | { Bad_Opcode }, |
9141 | { Bad_Opcode }, |
9544 | { Bad_Opcode }, |
9142 | { Bad_Opcode }, |
9545 | { Bad_Opcode }, |
9143 | { Bad_Opcode }, |
9546 | { Bad_Opcode }, |
9144 | { Bad_Opcode }, |
9547 | { Bad_Opcode }, |
9145 | { Bad_Opcode }, |
9548 | { Bad_Opcode }, |
9146 | { Bad_Opcode }, |
9549 | { Bad_Opcode }, |
9147 | { Bad_Opcode }, |
9550 | { Bad_Opcode }, |
9148 | /* e8 */ |
9551 | /* e8 */ |
9149 | { Bad_Opcode }, |
9552 | { Bad_Opcode }, |
9150 | { Bad_Opcode }, |
9553 | { Bad_Opcode }, |
9151 | { Bad_Opcode }, |
9554 | { Bad_Opcode }, |
9152 | { Bad_Opcode }, |
9555 | { Bad_Opcode }, |
9153 | { Bad_Opcode }, |
9556 | { Bad_Opcode }, |
9154 | { Bad_Opcode }, |
9557 | { Bad_Opcode }, |
9155 | { Bad_Opcode }, |
9558 | { Bad_Opcode }, |
9156 | { Bad_Opcode }, |
9559 | { Bad_Opcode }, |
9157 | /* f0 */ |
9560 | /* f0 */ |
9158 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
9561 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
9159 | { Bad_Opcode }, |
9562 | { Bad_Opcode }, |
9160 | { Bad_Opcode }, |
9563 | { Bad_Opcode }, |
9161 | { Bad_Opcode }, |
9564 | { Bad_Opcode }, |
9162 | { Bad_Opcode }, |
9565 | { Bad_Opcode }, |
9163 | { Bad_Opcode }, |
9566 | { Bad_Opcode }, |
9164 | { Bad_Opcode }, |
9567 | { Bad_Opcode }, |
9165 | { Bad_Opcode }, |
9568 | { Bad_Opcode }, |
9166 | /* f8 */ |
9569 | /* f8 */ |
9167 | { Bad_Opcode }, |
9570 | { Bad_Opcode }, |
9168 | { Bad_Opcode }, |
9571 | { Bad_Opcode }, |
9169 | { Bad_Opcode }, |
9572 | { Bad_Opcode }, |
9170 | { Bad_Opcode }, |
9573 | { Bad_Opcode }, |
9171 | { Bad_Opcode }, |
9574 | { Bad_Opcode }, |
9172 | { Bad_Opcode }, |
9575 | { Bad_Opcode }, |
9173 | { Bad_Opcode }, |
9576 | { Bad_Opcode }, |
9174 | { Bad_Opcode }, |
9577 | { Bad_Opcode }, |
9175 | }, |
9578 | }, |
9176 | }; |
9579 | }; |
9177 | 9580 | ||
9178 | #define NEED_OPCODE_TABLE |
9581 | #define NEED_OPCODE_TABLE |
9179 | #include "i386-dis-evex.h" |
9582 | #include "i386-dis-evex.h" |
9180 | #undef NEED_OPCODE_TABLE |
9583 | #undef NEED_OPCODE_TABLE |
9181 | static const struct dis386 vex_len_table[][2] = { |
9584 | static const struct dis386 vex_len_table[][2] = { |
9182 | /* VEX_LEN_0F10_P_1 */ |
9585 | /* VEX_LEN_0F10_P_1 */ |
9183 | { |
9586 | { |
9184 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9587 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9185 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9588 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9186 | }, |
9589 | }, |
9187 | 9590 | ||
9188 | /* VEX_LEN_0F10_P_3 */ |
9591 | /* VEX_LEN_0F10_P_3 */ |
9189 | { |
9592 | { |
9190 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9593 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9191 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9594 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9192 | }, |
9595 | }, |
9193 | 9596 | ||
9194 | /* VEX_LEN_0F11_P_1 */ |
9597 | /* VEX_LEN_0F11_P_1 */ |
9195 | { |
9598 | { |
9196 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9599 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9197 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9600 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9198 | }, |
9601 | }, |
9199 | 9602 | ||
9200 | /* VEX_LEN_0F11_P_3 */ |
9603 | /* VEX_LEN_0F11_P_3 */ |
9201 | { |
9604 | { |
9202 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9605 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9203 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9606 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9204 | }, |
9607 | }, |
9205 | 9608 | ||
9206 | /* VEX_LEN_0F12_P_0_M_0 */ |
9609 | /* VEX_LEN_0F12_P_0_M_0 */ |
9207 | { |
9610 | { |
9208 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
9611 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
9209 | }, |
9612 | }, |
9210 | 9613 | ||
9211 | /* VEX_LEN_0F12_P_0_M_1 */ |
9614 | /* VEX_LEN_0F12_P_0_M_1 */ |
9212 | { |
9615 | { |
9213 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
9616 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
9214 | }, |
9617 | }, |
9215 | 9618 | ||
9216 | /* VEX_LEN_0F12_P_2 */ |
9619 | /* VEX_LEN_0F12_P_2 */ |
9217 | { |
9620 | { |
9218 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
9621 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
9219 | }, |
9622 | }, |
9220 | 9623 | ||
9221 | /* VEX_LEN_0F13_M_0 */ |
9624 | /* VEX_LEN_0F13_M_0 */ |
9222 | { |
9625 | { |
9223 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
9626 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
9224 | }, |
9627 | }, |
9225 | 9628 | ||
9226 | /* VEX_LEN_0F16_P_0_M_0 */ |
9629 | /* VEX_LEN_0F16_P_0_M_0 */ |
9227 | { |
9630 | { |
9228 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
9631 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
9229 | }, |
9632 | }, |
9230 | 9633 | ||
9231 | /* VEX_LEN_0F16_P_0_M_1 */ |
9634 | /* VEX_LEN_0F16_P_0_M_1 */ |
9232 | { |
9635 | { |
9233 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
9636 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
9234 | }, |
9637 | }, |
9235 | 9638 | ||
9236 | /* VEX_LEN_0F16_P_2 */ |
9639 | /* VEX_LEN_0F16_P_2 */ |
9237 | { |
9640 | { |
9238 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
9641 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
9239 | }, |
9642 | }, |
9240 | 9643 | ||
9241 | /* VEX_LEN_0F17_M_0 */ |
9644 | /* VEX_LEN_0F17_M_0 */ |
9242 | { |
9645 | { |
9243 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
9646 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
9244 | }, |
9647 | }, |
9245 | 9648 | ||
9246 | /* VEX_LEN_0F2A_P_1 */ |
9649 | /* VEX_LEN_0F2A_P_1 */ |
9247 | { |
9650 | { |
9248 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, |
9651 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9249 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, |
9652 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9250 | }, |
9653 | }, |
9251 | 9654 | ||
9252 | /* VEX_LEN_0F2A_P_3 */ |
9655 | /* VEX_LEN_0F2A_P_3 */ |
9253 | { |
9656 | { |
9254 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, |
9657 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9255 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, |
9658 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9256 | }, |
9659 | }, |
9257 | 9660 | ||
9258 | /* VEX_LEN_0F2C_P_1 */ |
9661 | /* VEX_LEN_0F2C_P_1 */ |
9259 | { |
9662 | { |
9260 | { "vcvttss2siY", { Gv, EXdScalar } }, |
9663 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
9261 | { "vcvttss2siY", { Gv, EXdScalar } }, |
9664 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
9262 | }, |
9665 | }, |
9263 | 9666 | ||
9264 | /* VEX_LEN_0F2C_P_3 */ |
9667 | /* VEX_LEN_0F2C_P_3 */ |
9265 | { |
9668 | { |
9266 | { "vcvttsd2siY", { Gv, EXqScalar } }, |
9669 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
9267 | { "vcvttsd2siY", { Gv, EXqScalar } }, |
9670 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
9268 | }, |
9671 | }, |
9269 | 9672 | ||
9270 | /* VEX_LEN_0F2D_P_1 */ |
9673 | /* VEX_LEN_0F2D_P_1 */ |
9271 | { |
9674 | { |
9272 | { "vcvtss2siY", { Gv, EXdScalar } }, |
9675 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
9273 | { "vcvtss2siY", { Gv, EXdScalar } }, |
9676 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
9274 | }, |
9677 | }, |
9275 | 9678 | ||
9276 | /* VEX_LEN_0F2D_P_3 */ |
9679 | /* VEX_LEN_0F2D_P_3 */ |
9277 | { |
9680 | { |
9278 | { "vcvtsd2siY", { Gv, EXqScalar } }, |
9681 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, |
9279 | { "vcvtsd2siY", { Gv, EXqScalar } }, |
9682 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, |
9280 | }, |
9683 | }, |
9281 | 9684 | ||
9282 | /* VEX_LEN_0F2E_P_0 */ |
9685 | /* VEX_LEN_0F2E_P_0 */ |
9283 | { |
9686 | { |
9284 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9687 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9285 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9688 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9286 | }, |
9689 | }, |
9287 | 9690 | ||
9288 | /* VEX_LEN_0F2E_P_2 */ |
9691 | /* VEX_LEN_0F2E_P_2 */ |
9289 | { |
9692 | { |
9290 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9693 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9291 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9694 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9292 | }, |
9695 | }, |
9293 | 9696 | ||
9294 | /* VEX_LEN_0F2F_P_0 */ |
9697 | /* VEX_LEN_0F2F_P_0 */ |
9295 | { |
9698 | { |
9296 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9699 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9297 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9700 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9298 | }, |
9701 | }, |
9299 | 9702 | ||
9300 | /* VEX_LEN_0F2F_P_2 */ |
9703 | /* VEX_LEN_0F2F_P_2 */ |
9301 | { |
9704 | { |
9302 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9705 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9303 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9706 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9304 | }, |
9707 | }, |
9305 | 9708 | ||
9306 | /* VEX_LEN_0F41_P_0 */ |
9709 | /* VEX_LEN_0F41_P_0 */ |
9307 | { |
9710 | { |
9308 | { Bad_Opcode }, |
9711 | { Bad_Opcode }, |
9309 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, |
9712 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, |
9310 | }, |
9713 | }, |
- | 9714 | /* VEX_LEN_0F41_P_2 */ |
|
- | 9715 | { |
|
- | 9716 | { Bad_Opcode }, |
|
- | 9717 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, |
|
- | 9718 | }, |
|
9311 | /* VEX_LEN_0F42_P_0 */ |
9719 | /* VEX_LEN_0F42_P_0 */ |
9312 | { |
9720 | { |
9313 | { Bad_Opcode }, |
9721 | { Bad_Opcode }, |
9314 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, |
9722 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, |
9315 | }, |
9723 | }, |
- | 9724 | /* VEX_LEN_0F42_P_2 */ |
|
- | 9725 | { |
|
- | 9726 | { Bad_Opcode }, |
|
- | 9727 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, |
|
- | 9728 | }, |
|
9316 | /* VEX_LEN_0F44_P_0 */ |
9729 | /* VEX_LEN_0F44_P_0 */ |
9317 | { |
9730 | { |
9318 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, |
9731 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, |
9319 | }, |
9732 | }, |
- | 9733 | /* VEX_LEN_0F44_P_2 */ |
|
- | 9734 | { |
|
- | 9735 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, |
|
- | 9736 | }, |
|
9320 | /* VEX_LEN_0F45_P_0 */ |
9737 | /* VEX_LEN_0F45_P_0 */ |
9321 | { |
9738 | { |
9322 | { Bad_Opcode }, |
9739 | { Bad_Opcode }, |
9323 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, |
9740 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, |
9324 | }, |
9741 | }, |
- | 9742 | /* VEX_LEN_0F45_P_2 */ |
|
- | 9743 | { |
|
- | 9744 | { Bad_Opcode }, |
|
- | 9745 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, |
|
- | 9746 | }, |
|
9325 | /* VEX_LEN_0F46_P_0 */ |
9747 | /* VEX_LEN_0F46_P_0 */ |
9326 | { |
9748 | { |
9327 | { Bad_Opcode }, |
9749 | { Bad_Opcode }, |
9328 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, |
9750 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, |
9329 | }, |
9751 | }, |
- | 9752 | /* VEX_LEN_0F46_P_2 */ |
|
- | 9753 | { |
|
- | 9754 | { Bad_Opcode }, |
|
- | 9755 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, |
|
- | 9756 | }, |
|
9330 | /* VEX_LEN_0F47_P_0 */ |
9757 | /* VEX_LEN_0F47_P_0 */ |
9331 | { |
9758 | { |
9332 | { Bad_Opcode }, |
9759 | { Bad_Opcode }, |
9333 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, |
9760 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, |
9334 | }, |
9761 | }, |
- | 9762 | /* VEX_LEN_0F47_P_2 */ |
|
- | 9763 | { |
|
- | 9764 | { Bad_Opcode }, |
|
- | 9765 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, |
|
- | 9766 | }, |
|
- | 9767 | /* VEX_LEN_0F4A_P_0 */ |
|
- | 9768 | { |
|
- | 9769 | { Bad_Opcode }, |
|
- | 9770 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, |
|
- | 9771 | }, |
|
- | 9772 | /* VEX_LEN_0F4A_P_2 */ |
|
- | 9773 | { |
|
- | 9774 | { Bad_Opcode }, |
|
- | 9775 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, |
|
- | 9776 | }, |
|
- | 9777 | /* VEX_LEN_0F4B_P_0 */ |
|
- | 9778 | { |
|
- | 9779 | { Bad_Opcode }, |
|
- | 9780 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, |
|
- | 9781 | }, |
|
9335 | /* VEX_LEN_0F4B_P_2 */ |
9782 | /* VEX_LEN_0F4B_P_2 */ |
9336 | { |
9783 | { |
9337 | { Bad_Opcode }, |
9784 | { Bad_Opcode }, |
9338 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, |
9785 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, |
9339 | }, |
9786 | }, |
9340 | 9787 | ||
9341 | /* VEX_LEN_0F51_P_1 */ |
9788 | /* VEX_LEN_0F51_P_1 */ |
9342 | { |
9789 | { |
9343 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9790 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9344 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9791 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9345 | }, |
9792 | }, |
9346 | 9793 | ||
9347 | /* VEX_LEN_0F51_P_3 */ |
9794 | /* VEX_LEN_0F51_P_3 */ |
9348 | { |
9795 | { |
9349 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9796 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9350 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9797 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9351 | }, |
9798 | }, |
9352 | 9799 | ||
9353 | /* VEX_LEN_0F52_P_1 */ |
9800 | /* VEX_LEN_0F52_P_1 */ |
9354 | { |
9801 | { |
9355 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9802 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9356 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9803 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9357 | }, |
9804 | }, |
9358 | 9805 | ||
9359 | /* VEX_LEN_0F53_P_1 */ |
9806 | /* VEX_LEN_0F53_P_1 */ |
9360 | { |
9807 | { |
9361 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9808 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9362 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9809 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9363 | }, |
9810 | }, |
9364 | 9811 | ||
9365 | /* VEX_LEN_0F58_P_1 */ |
9812 | /* VEX_LEN_0F58_P_1 */ |
9366 | { |
9813 | { |
9367 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9814 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9368 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9815 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9369 | }, |
9816 | }, |
9370 | 9817 | ||
9371 | /* VEX_LEN_0F58_P_3 */ |
9818 | /* VEX_LEN_0F58_P_3 */ |
9372 | { |
9819 | { |
9373 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9820 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9374 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9821 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9375 | }, |
9822 | }, |
9376 | 9823 | ||
9377 | /* VEX_LEN_0F59_P_1 */ |
9824 | /* VEX_LEN_0F59_P_1 */ |
9378 | { |
9825 | { |
9379 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9826 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9380 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9827 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9381 | }, |
9828 | }, |
9382 | 9829 | ||
9383 | /* VEX_LEN_0F59_P_3 */ |
9830 | /* VEX_LEN_0F59_P_3 */ |
9384 | { |
9831 | { |
9385 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9832 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9386 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9833 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9387 | }, |
9834 | }, |
9388 | 9835 | ||
9389 | /* VEX_LEN_0F5A_P_1 */ |
9836 | /* VEX_LEN_0F5A_P_1 */ |
9390 | { |
9837 | { |
9391 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9838 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9392 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9839 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9393 | }, |
9840 | }, |
9394 | 9841 | ||
9395 | /* VEX_LEN_0F5A_P_3 */ |
9842 | /* VEX_LEN_0F5A_P_3 */ |
9396 | { |
9843 | { |
9397 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9844 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9398 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9845 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9399 | }, |
9846 | }, |
9400 | 9847 | ||
9401 | /* VEX_LEN_0F5C_P_1 */ |
9848 | /* VEX_LEN_0F5C_P_1 */ |
9402 | { |
9849 | { |
9403 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9850 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9404 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9851 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9405 | }, |
9852 | }, |
9406 | 9853 | ||
9407 | /* VEX_LEN_0F5C_P_3 */ |
9854 | /* VEX_LEN_0F5C_P_3 */ |
9408 | { |
9855 | { |
9409 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9856 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9410 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9857 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9411 | }, |
9858 | }, |
9412 | 9859 | ||
9413 | /* VEX_LEN_0F5D_P_1 */ |
9860 | /* VEX_LEN_0F5D_P_1 */ |
9414 | { |
9861 | { |
9415 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9862 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9416 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9863 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9417 | }, |
9864 | }, |
9418 | 9865 | ||
9419 | /* VEX_LEN_0F5D_P_3 */ |
9866 | /* VEX_LEN_0F5D_P_3 */ |
9420 | { |
9867 | { |
9421 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9868 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9422 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9869 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9423 | }, |
9870 | }, |
9424 | 9871 | ||
9425 | /* VEX_LEN_0F5E_P_1 */ |
9872 | /* VEX_LEN_0F5E_P_1 */ |
9426 | { |
9873 | { |
9427 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9874 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9428 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9875 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9429 | }, |
9876 | }, |
9430 | 9877 | ||
9431 | /* VEX_LEN_0F5E_P_3 */ |
9878 | /* VEX_LEN_0F5E_P_3 */ |
9432 | { |
9879 | { |
9433 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9880 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9434 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9881 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9435 | }, |
9882 | }, |
9436 | 9883 | ||
9437 | /* VEX_LEN_0F5F_P_1 */ |
9884 | /* VEX_LEN_0F5F_P_1 */ |
9438 | { |
9885 | { |
9439 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9886 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9440 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9887 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9441 | }, |
9888 | }, |
9442 | 9889 | ||
9443 | /* VEX_LEN_0F5F_P_3 */ |
9890 | /* VEX_LEN_0F5F_P_3 */ |
9444 | { |
9891 | { |
9445 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9892 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9446 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9893 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9447 | }, |
9894 | }, |
9448 | 9895 | ||
9449 | /* VEX_LEN_0F6E_P_2 */ |
9896 | /* VEX_LEN_0F6E_P_2 */ |
9450 | { |
9897 | { |
9451 | { "vmovK", { XMScalar, Edq } }, |
9898 | { "vmovK", { XMScalar, Edq }, 0 }, |
9452 | { "vmovK", { XMScalar, Edq } }, |
9899 | { "vmovK", { XMScalar, Edq }, 0 }, |
9453 | }, |
9900 | }, |
9454 | 9901 | ||
9455 | /* VEX_LEN_0F7E_P_1 */ |
9902 | /* VEX_LEN_0F7E_P_1 */ |
9456 | { |
9903 | { |
9457 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9904 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9458 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9905 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9459 | }, |
9906 | }, |
9460 | 9907 | ||
9461 | /* VEX_LEN_0F7E_P_2 */ |
9908 | /* VEX_LEN_0F7E_P_2 */ |
9462 | { |
9909 | { |
9463 | { "vmovK", { Edq, XMScalar } }, |
9910 | { "vmovK", { Edq, XMScalar }, 0 }, |
9464 | { "vmovK", { Edq, XMScalar } }, |
9911 | { "vmovK", { Edq, XMScalar }, 0 }, |
9465 | }, |
9912 | }, |
9466 | 9913 | ||
9467 | /* VEX_LEN_0F90_P_0 */ |
9914 | /* VEX_LEN_0F90_P_0 */ |
9468 | { |
9915 | { |
9469 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
9916 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
9470 | }, |
9917 | }, |
- | 9918 | ||
- | 9919 | /* VEX_LEN_0F90_P_2 */ |
|
- | 9920 | { |
|
- | 9921 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
|
- | 9922 | }, |
|
9471 | 9923 | ||
9472 | /* VEX_LEN_0F91_P_0 */ |
9924 | /* VEX_LEN_0F91_P_0 */ |
9473 | { |
9925 | { |
9474 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
9926 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
9475 | }, |
9927 | }, |
- | 9928 | ||
- | 9929 | /* VEX_LEN_0F91_P_2 */ |
|
- | 9930 | { |
|
- | 9931 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
|
- | 9932 | }, |
|
9476 | 9933 | ||
9477 | /* VEX_LEN_0F92_P_0 */ |
9934 | /* VEX_LEN_0F92_P_0 */ |
9478 | { |
9935 | { |
9479 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
9936 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
9480 | }, |
9937 | }, |
- | 9938 | ||
- | 9939 | /* VEX_LEN_0F92_P_2 */ |
|
- | 9940 | { |
|
- | 9941 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
|
- | 9942 | }, |
|
- | 9943 | ||
- | 9944 | /* VEX_LEN_0F92_P_3 */ |
|
- | 9945 | { |
|
- | 9946 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, |
|
- | 9947 | }, |
|
9481 | 9948 | ||
9482 | /* VEX_LEN_0F93_P_0 */ |
9949 | /* VEX_LEN_0F93_P_0 */ |
9483 | { |
9950 | { |
9484 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
9951 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
9485 | }, |
9952 | }, |
- | 9953 | ||
- | 9954 | /* VEX_LEN_0F93_P_2 */ |
|
- | 9955 | { |
|
- | 9956 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
|
- | 9957 | }, |
|
- | 9958 | ||
- | 9959 | /* VEX_LEN_0F93_P_3 */ |
|
- | 9960 | { |
|
- | 9961 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, |
|
- | 9962 | }, |
|
9486 | 9963 | ||
9487 | /* VEX_LEN_0F98_P_0 */ |
9964 | /* VEX_LEN_0F98_P_0 */ |
9488 | { |
9965 | { |
9489 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, |
9966 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, |
9490 | }, |
9967 | }, |
- | 9968 | ||
- | 9969 | /* VEX_LEN_0F98_P_2 */ |
|
- | 9970 | { |
|
- | 9971 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, |
|
- | 9972 | }, |
|
- | 9973 | ||
- | 9974 | /* VEX_LEN_0F99_P_0 */ |
|
- | 9975 | { |
|
- | 9976 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, |
|
- | 9977 | }, |
|
- | 9978 | ||
- | 9979 | /* VEX_LEN_0F99_P_2 */ |
|
- | 9980 | { |
|
- | 9981 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, |
|
- | 9982 | }, |
|
9491 | 9983 | ||
9492 | /* VEX_LEN_0FAE_R_2_M_0 */ |
9984 | /* VEX_LEN_0FAE_R_2_M_0 */ |
9493 | { |
9985 | { |
9494 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
9986 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
9495 | }, |
9987 | }, |
9496 | 9988 | ||
9497 | /* VEX_LEN_0FAE_R_3_M_0 */ |
9989 | /* VEX_LEN_0FAE_R_3_M_0 */ |
9498 | { |
9990 | { |
9499 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
9991 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
9500 | }, |
9992 | }, |
9501 | 9993 | ||
9502 | /* VEX_LEN_0FC2_P_1 */ |
9994 | /* VEX_LEN_0FC2_P_1 */ |
9503 | { |
9995 | { |
9504 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9996 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9505 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9997 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9506 | }, |
9998 | }, |
9507 | 9999 | ||
9508 | /* VEX_LEN_0FC2_P_3 */ |
10000 | /* VEX_LEN_0FC2_P_3 */ |
9509 | { |
10001 | { |
9510 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
10002 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9511 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
10003 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9512 | }, |
10004 | }, |
9513 | 10005 | ||
9514 | /* VEX_LEN_0FC4_P_2 */ |
10006 | /* VEX_LEN_0FC4_P_2 */ |
9515 | { |
10007 | { |
9516 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
10008 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
9517 | }, |
10009 | }, |
9518 | 10010 | ||
9519 | /* VEX_LEN_0FC5_P_2 */ |
10011 | /* VEX_LEN_0FC5_P_2 */ |
9520 | { |
10012 | { |
9521 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
10013 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
9522 | }, |
10014 | }, |
9523 | 10015 | ||
9524 | /* VEX_LEN_0FD6_P_2 */ |
10016 | /* VEX_LEN_0FD6_P_2 */ |
9525 | { |
10017 | { |
9526 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
10018 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
9527 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
10019 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
9528 | }, |
10020 | }, |
9529 | 10021 | ||
9530 | /* VEX_LEN_0FF7_P_2 */ |
10022 | /* VEX_LEN_0FF7_P_2 */ |
9531 | { |
10023 | { |
9532 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
10024 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
9533 | }, |
10025 | }, |
9534 | 10026 | ||
9535 | /* VEX_LEN_0F3816_P_2 */ |
10027 | /* VEX_LEN_0F3816_P_2 */ |
9536 | { |
10028 | { |
9537 | { Bad_Opcode }, |
10029 | { Bad_Opcode }, |
9538 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, |
10030 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, |
9539 | }, |
10031 | }, |
9540 | 10032 | ||
9541 | /* VEX_LEN_0F3819_P_2 */ |
10033 | /* VEX_LEN_0F3819_P_2 */ |
9542 | { |
10034 | { |
9543 | { Bad_Opcode }, |
10035 | { Bad_Opcode }, |
9544 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, |
10036 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, |
9545 | }, |
10037 | }, |
9546 | 10038 | ||
9547 | /* VEX_LEN_0F381A_P_2_M_0 */ |
10039 | /* VEX_LEN_0F381A_P_2_M_0 */ |
9548 | { |
10040 | { |
9549 | { Bad_Opcode }, |
10041 | { Bad_Opcode }, |
9550 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, |
10042 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, |
9551 | }, |
10043 | }, |
9552 | 10044 | ||
9553 | /* VEX_LEN_0F3836_P_2 */ |
10045 | /* VEX_LEN_0F3836_P_2 */ |
9554 | { |
10046 | { |
9555 | { Bad_Opcode }, |
10047 | { Bad_Opcode }, |
9556 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, |
10048 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, |
9557 | }, |
10049 | }, |
9558 | 10050 | ||
9559 | /* VEX_LEN_0F3841_P_2 */ |
10051 | /* VEX_LEN_0F3841_P_2 */ |
9560 | { |
10052 | { |
9561 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
10053 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
9562 | }, |
10054 | }, |
9563 | 10055 | ||
9564 | /* VEX_LEN_0F385A_P_2_M_0 */ |
10056 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9565 | { |
10057 | { |
9566 | { Bad_Opcode }, |
10058 | { Bad_Opcode }, |
9567 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, |
10059 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, |
9568 | }, |
10060 | }, |
9569 | 10061 | ||
9570 | /* VEX_LEN_0F38DB_P_2 */ |
10062 | /* VEX_LEN_0F38DB_P_2 */ |
9571 | { |
10063 | { |
9572 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
10064 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
9573 | }, |
10065 | }, |
9574 | 10066 | ||
9575 | /* VEX_LEN_0F38DC_P_2 */ |
10067 | /* VEX_LEN_0F38DC_P_2 */ |
9576 | { |
10068 | { |
9577 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
10069 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
9578 | }, |
10070 | }, |
9579 | 10071 | ||
9580 | /* VEX_LEN_0F38DD_P_2 */ |
10072 | /* VEX_LEN_0F38DD_P_2 */ |
9581 | { |
10073 | { |
9582 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
10074 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
9583 | }, |
10075 | }, |
9584 | 10076 | ||
9585 | /* VEX_LEN_0F38DE_P_2 */ |
10077 | /* VEX_LEN_0F38DE_P_2 */ |
9586 | { |
10078 | { |
9587 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
10079 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
9588 | }, |
10080 | }, |
9589 | 10081 | ||
9590 | /* VEX_LEN_0F38DF_P_2 */ |
10082 | /* VEX_LEN_0F38DF_P_2 */ |
9591 | { |
10083 | { |
9592 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
10084 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
9593 | }, |
10085 | }, |
9594 | 10086 | ||
9595 | /* VEX_LEN_0F38F2_P_0 */ |
10087 | /* VEX_LEN_0F38F2_P_0 */ |
9596 | { |
10088 | { |
9597 | { "andnS", { Gdq, VexGdq, Edq } }, |
10089 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
9598 | }, |
10090 | }, |
9599 | 10091 | ||
9600 | /* VEX_LEN_0F38F3_R_1_P_0 */ |
10092 | /* VEX_LEN_0F38F3_R_1_P_0 */ |
9601 | { |
10093 | { |
9602 | { "blsrS", { VexGdq, Edq } }, |
10094 | { "blsrS", { VexGdq, Edq }, 0 }, |
9603 | }, |
10095 | }, |
9604 | 10096 | ||
9605 | /* VEX_LEN_0F38F3_R_2_P_0 */ |
10097 | /* VEX_LEN_0F38F3_R_2_P_0 */ |
9606 | { |
10098 | { |
9607 | { "blsmskS", { VexGdq, Edq } }, |
10099 | { "blsmskS", { VexGdq, Edq }, 0 }, |
9608 | }, |
10100 | }, |
9609 | 10101 | ||
9610 | /* VEX_LEN_0F38F3_R_3_P_0 */ |
10102 | /* VEX_LEN_0F38F3_R_3_P_0 */ |
9611 | { |
10103 | { |
9612 | { "blsiS", { VexGdq, Edq } }, |
10104 | { "blsiS", { VexGdq, Edq }, 0 }, |
9613 | }, |
10105 | }, |
9614 | 10106 | ||
9615 | /* VEX_LEN_0F38F5_P_0 */ |
10107 | /* VEX_LEN_0F38F5_P_0 */ |
9616 | { |
10108 | { |
9617 | { "bzhiS", { Gdq, Edq, VexGdq } }, |
10109 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
9618 | }, |
10110 | }, |
9619 | 10111 | ||
9620 | /* VEX_LEN_0F38F5_P_1 */ |
10112 | /* VEX_LEN_0F38F5_P_1 */ |
9621 | { |
10113 | { |
9622 | { "pextS", { Gdq, VexGdq, Edq } }, |
10114 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
9623 | }, |
10115 | }, |
9624 | 10116 | ||
9625 | /* VEX_LEN_0F38F5_P_3 */ |
10117 | /* VEX_LEN_0F38F5_P_3 */ |
9626 | { |
10118 | { |
9627 | { "pdepS", { Gdq, VexGdq, Edq } }, |
10119 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
9628 | }, |
10120 | }, |
9629 | 10121 | ||
9630 | /* VEX_LEN_0F38F6_P_3 */ |
10122 | /* VEX_LEN_0F38F6_P_3 */ |
9631 | { |
10123 | { |
9632 | { "mulxS", { Gdq, VexGdq, Edq } }, |
10124 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
9633 | }, |
10125 | }, |
9634 | 10126 | ||
9635 | /* VEX_LEN_0F38F7_P_0 */ |
10127 | /* VEX_LEN_0F38F7_P_0 */ |
9636 | { |
10128 | { |
9637 | { "bextrS", { Gdq, Edq, VexGdq } }, |
10129 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
9638 | }, |
10130 | }, |
9639 | 10131 | ||
9640 | /* VEX_LEN_0F38F7_P_1 */ |
10132 | /* VEX_LEN_0F38F7_P_1 */ |
9641 | { |
10133 | { |
9642 | { "sarxS", { Gdq, Edq, VexGdq } }, |
10134 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
9643 | }, |
10135 | }, |
9644 | 10136 | ||
9645 | /* VEX_LEN_0F38F7_P_2 */ |
10137 | /* VEX_LEN_0F38F7_P_2 */ |
9646 | { |
10138 | { |
9647 | { "shlxS", { Gdq, Edq, VexGdq } }, |
10139 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
9648 | }, |
10140 | }, |
9649 | 10141 | ||
9650 | /* VEX_LEN_0F38F7_P_3 */ |
10142 | /* VEX_LEN_0F38F7_P_3 */ |
9651 | { |
10143 | { |
9652 | { "shrxS", { Gdq, Edq, VexGdq } }, |
10144 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
9653 | }, |
10145 | }, |
9654 | 10146 | ||
9655 | /* VEX_LEN_0F3A00_P_2 */ |
10147 | /* VEX_LEN_0F3A00_P_2 */ |
9656 | { |
10148 | { |
9657 | { Bad_Opcode }, |
10149 | { Bad_Opcode }, |
9658 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, |
10150 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, |
9659 | }, |
10151 | }, |
9660 | 10152 | ||
9661 | /* VEX_LEN_0F3A01_P_2 */ |
10153 | /* VEX_LEN_0F3A01_P_2 */ |
9662 | { |
10154 | { |
9663 | { Bad_Opcode }, |
10155 | { Bad_Opcode }, |
9664 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, |
10156 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, |
9665 | }, |
10157 | }, |
9666 | 10158 | ||
9667 | /* VEX_LEN_0F3A06_P_2 */ |
10159 | /* VEX_LEN_0F3A06_P_2 */ |
9668 | { |
10160 | { |
9669 | { Bad_Opcode }, |
10161 | { Bad_Opcode }, |
9670 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
10162 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
9671 | }, |
10163 | }, |
9672 | 10164 | ||
9673 | /* VEX_LEN_0F3A0A_P_2 */ |
10165 | /* VEX_LEN_0F3A0A_P_2 */ |
9674 | { |
10166 | { |
9675 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
10167 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
9676 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
10168 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
9677 | }, |
10169 | }, |
9678 | 10170 | ||
9679 | /* VEX_LEN_0F3A0B_P_2 */ |
10171 | /* VEX_LEN_0F3A0B_P_2 */ |
9680 | { |
10172 | { |
9681 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
10173 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
9682 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
10174 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
9683 | }, |
10175 | }, |
9684 | 10176 | ||
9685 | /* VEX_LEN_0F3A14_P_2 */ |
10177 | /* VEX_LEN_0F3A14_P_2 */ |
9686 | { |
10178 | { |
9687 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
10179 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
9688 | }, |
10180 | }, |
9689 | 10181 | ||
9690 | /* VEX_LEN_0F3A15_P_2 */ |
10182 | /* VEX_LEN_0F3A15_P_2 */ |
9691 | { |
10183 | { |
9692 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
10184 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
9693 | }, |
10185 | }, |
9694 | 10186 | ||
9695 | /* VEX_LEN_0F3A16_P_2 */ |
10187 | /* VEX_LEN_0F3A16_P_2 */ |
9696 | { |
10188 | { |
9697 | { "vpextrK", { Edq, XM, Ib } }, |
10189 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
9698 | }, |
10190 | }, |
9699 | 10191 | ||
9700 | /* VEX_LEN_0F3A17_P_2 */ |
10192 | /* VEX_LEN_0F3A17_P_2 */ |
9701 | { |
10193 | { |
9702 | { "vextractps", { Edqd, XM, Ib } }, |
10194 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
9703 | }, |
10195 | }, |
9704 | 10196 | ||
9705 | /* VEX_LEN_0F3A18_P_2 */ |
10197 | /* VEX_LEN_0F3A18_P_2 */ |
9706 | { |
10198 | { |
9707 | { Bad_Opcode }, |
10199 | { Bad_Opcode }, |
9708 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
10200 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
9709 | }, |
10201 | }, |
9710 | 10202 | ||
9711 | /* VEX_LEN_0F3A19_P_2 */ |
10203 | /* VEX_LEN_0F3A19_P_2 */ |
9712 | { |
10204 | { |
9713 | { Bad_Opcode }, |
10205 | { Bad_Opcode }, |
9714 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
10206 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
9715 | }, |
10207 | }, |
9716 | 10208 | ||
9717 | /* VEX_LEN_0F3A20_P_2 */ |
10209 | /* VEX_LEN_0F3A20_P_2 */ |
9718 | { |
10210 | { |
9719 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
10211 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
9720 | }, |
10212 | }, |
9721 | 10213 | ||
9722 | /* VEX_LEN_0F3A21_P_2 */ |
10214 | /* VEX_LEN_0F3A21_P_2 */ |
9723 | { |
10215 | { |
9724 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
10216 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
9725 | }, |
10217 | }, |
9726 | 10218 | ||
9727 | /* VEX_LEN_0F3A22_P_2 */ |
10219 | /* VEX_LEN_0F3A22_P_2 */ |
9728 | { |
10220 | { |
9729 | { "vpinsrK", { XM, Vex128, Edq, Ib } }, |
10221 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
9730 | }, |
10222 | }, |
9731 | 10223 | ||
9732 | /* VEX_LEN_0F3A30_P_2 */ |
10224 | /* VEX_LEN_0F3A30_P_2 */ |
9733 | { |
10225 | { |
9734 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, |
10226 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, |
9735 | }, |
10227 | }, |
- | 10228 | ||
- | 10229 | /* VEX_LEN_0F3A31_P_2 */ |
|
- | 10230 | { |
|
- | 10231 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, |
|
- | 10232 | }, |
|
9736 | 10233 | ||
9737 | /* VEX_LEN_0F3A32_P_2 */ |
10234 | /* VEX_LEN_0F3A32_P_2 */ |
9738 | { |
10235 | { |
9739 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, |
10236 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, |
9740 | }, |
10237 | }, |
- | 10238 | ||
- | 10239 | /* VEX_LEN_0F3A33_P_2 */ |
|
- | 10240 | { |
|
- | 10241 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, |
|
- | 10242 | }, |
|
9741 | 10243 | ||
9742 | /* VEX_LEN_0F3A38_P_2 */ |
10244 | /* VEX_LEN_0F3A38_P_2 */ |
9743 | { |
10245 | { |
9744 | { Bad_Opcode }, |
10246 | { Bad_Opcode }, |
9745 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, |
10247 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, |
9746 | }, |
10248 | }, |
9747 | 10249 | ||
9748 | /* VEX_LEN_0F3A39_P_2 */ |
10250 | /* VEX_LEN_0F3A39_P_2 */ |
9749 | { |
10251 | { |
9750 | { Bad_Opcode }, |
10252 | { Bad_Opcode }, |
9751 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, |
10253 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, |
9752 | }, |
10254 | }, |
9753 | 10255 | ||
9754 | /* VEX_LEN_0F3A41_P_2 */ |
10256 | /* VEX_LEN_0F3A41_P_2 */ |
9755 | { |
10257 | { |
9756 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, |
10258 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, |
9757 | }, |
10259 | }, |
9758 | 10260 | ||
9759 | /* VEX_LEN_0F3A44_P_2 */ |
10261 | /* VEX_LEN_0F3A44_P_2 */ |
9760 | { |
10262 | { |
9761 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
10263 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
9762 | }, |
10264 | }, |
9763 | 10265 | ||
9764 | /* VEX_LEN_0F3A46_P_2 */ |
10266 | /* VEX_LEN_0F3A46_P_2 */ |
9765 | { |
10267 | { |
9766 | { Bad_Opcode }, |
10268 | { Bad_Opcode }, |
9767 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, |
10269 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, |
9768 | }, |
10270 | }, |
9769 | 10271 | ||
9770 | /* VEX_LEN_0F3A60_P_2 */ |
10272 | /* VEX_LEN_0F3A60_P_2 */ |
9771 | { |
10273 | { |
9772 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
10274 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
9773 | }, |
10275 | }, |
9774 | 10276 | ||
9775 | /* VEX_LEN_0F3A61_P_2 */ |
10277 | /* VEX_LEN_0F3A61_P_2 */ |
9776 | { |
10278 | { |
9777 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
10279 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
9778 | }, |
10280 | }, |
9779 | 10281 | ||
9780 | /* VEX_LEN_0F3A62_P_2 */ |
10282 | /* VEX_LEN_0F3A62_P_2 */ |
9781 | { |
10283 | { |
9782 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
10284 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
9783 | }, |
10285 | }, |
9784 | 10286 | ||
9785 | /* VEX_LEN_0F3A63_P_2 */ |
10287 | /* VEX_LEN_0F3A63_P_2 */ |
9786 | { |
10288 | { |
9787 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
10289 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
9788 | }, |
10290 | }, |
9789 | 10291 | ||
9790 | /* VEX_LEN_0F3A6A_P_2 */ |
10292 | /* VEX_LEN_0F3A6A_P_2 */ |
9791 | { |
10293 | { |
9792 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
10294 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
9793 | }, |
10295 | }, |
9794 | 10296 | ||
9795 | /* VEX_LEN_0F3A6B_P_2 */ |
10297 | /* VEX_LEN_0F3A6B_P_2 */ |
9796 | { |
10298 | { |
9797 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
10299 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
9798 | }, |
10300 | }, |
9799 | 10301 | ||
9800 | /* VEX_LEN_0F3A6E_P_2 */ |
10302 | /* VEX_LEN_0F3A6E_P_2 */ |
9801 | { |
10303 | { |
9802 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
10304 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
9803 | }, |
10305 | }, |
9804 | 10306 | ||
9805 | /* VEX_LEN_0F3A6F_P_2 */ |
10307 | /* VEX_LEN_0F3A6F_P_2 */ |
9806 | { |
10308 | { |
9807 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
10309 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
9808 | }, |
10310 | }, |
9809 | 10311 | ||
9810 | /* VEX_LEN_0F3A7A_P_2 */ |
10312 | /* VEX_LEN_0F3A7A_P_2 */ |
9811 | { |
10313 | { |
9812 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
10314 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
9813 | }, |
10315 | }, |
9814 | 10316 | ||
9815 | /* VEX_LEN_0F3A7B_P_2 */ |
10317 | /* VEX_LEN_0F3A7B_P_2 */ |
9816 | { |
10318 | { |
9817 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
10319 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
9818 | }, |
10320 | }, |
9819 | 10321 | ||
9820 | /* VEX_LEN_0F3A7E_P_2 */ |
10322 | /* VEX_LEN_0F3A7E_P_2 */ |
9821 | { |
10323 | { |
9822 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
10324 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
9823 | }, |
10325 | }, |
9824 | 10326 | ||
9825 | /* VEX_LEN_0F3A7F_P_2 */ |
10327 | /* VEX_LEN_0F3A7F_P_2 */ |
9826 | { |
10328 | { |
9827 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
10329 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
9828 | }, |
10330 | }, |
9829 | 10331 | ||
9830 | /* VEX_LEN_0F3ADF_P_2 */ |
10332 | /* VEX_LEN_0F3ADF_P_2 */ |
9831 | { |
10333 | { |
9832 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
10334 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
9833 | }, |
10335 | }, |
9834 | 10336 | ||
9835 | /* VEX_LEN_0F3AF0_P_3 */ |
10337 | /* VEX_LEN_0F3AF0_P_3 */ |
9836 | { |
10338 | { |
9837 | { "rorxS", { Gdq, Edq, Ib } }, |
10339 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
9838 | }, |
10340 | }, |
9839 | 10341 | ||
9840 | /* VEX_LEN_0FXOP_08_CC */ |
10342 | /* VEX_LEN_0FXOP_08_CC */ |
9841 | { |
10343 | { |
9842 | { "vpcomb", { XM, Vex128, EXx, Ib } }, |
10344 | { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, |
9843 | }, |
10345 | }, |
9844 | 10346 | ||
9845 | /* VEX_LEN_0FXOP_08_CD */ |
10347 | /* VEX_LEN_0FXOP_08_CD */ |
9846 | { |
10348 | { |
9847 | { "vpcomw", { XM, Vex128, EXx, Ib } }, |
10349 | { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, |
9848 | }, |
10350 | }, |
9849 | 10351 | ||
9850 | /* VEX_LEN_0FXOP_08_CE */ |
10352 | /* VEX_LEN_0FXOP_08_CE */ |
9851 | { |
10353 | { |
9852 | { "vpcomd", { XM, Vex128, EXx, Ib } }, |
10354 | { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, |
9853 | }, |
10355 | }, |
9854 | 10356 | ||
9855 | /* VEX_LEN_0FXOP_08_CF */ |
10357 | /* VEX_LEN_0FXOP_08_CF */ |
9856 | { |
10358 | { |
9857 | { "vpcomq", { XM, Vex128, EXx, Ib } }, |
10359 | { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, |
9858 | }, |
10360 | }, |
9859 | 10361 | ||
9860 | /* VEX_LEN_0FXOP_08_EC */ |
10362 | /* VEX_LEN_0FXOP_08_EC */ |
9861 | { |
10363 | { |
9862 | { "vpcomub", { XM, Vex128, EXx, Ib } }, |
10364 | { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, |
9863 | }, |
10365 | }, |
9864 | 10366 | ||
9865 | /* VEX_LEN_0FXOP_08_ED */ |
10367 | /* VEX_LEN_0FXOP_08_ED */ |
9866 | { |
10368 | { |
9867 | { "vpcomuw", { XM, Vex128, EXx, Ib } }, |
10369 | { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, |
9868 | }, |
10370 | }, |
9869 | 10371 | ||
9870 | /* VEX_LEN_0FXOP_08_EE */ |
10372 | /* VEX_LEN_0FXOP_08_EE */ |
9871 | { |
10373 | { |
9872 | { "vpcomud", { XM, Vex128, EXx, Ib } }, |
10374 | { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, |
9873 | }, |
10375 | }, |
9874 | 10376 | ||
9875 | /* VEX_LEN_0FXOP_08_EF */ |
10377 | /* VEX_LEN_0FXOP_08_EF */ |
9876 | { |
10378 | { |
9877 | { "vpcomuq", { XM, Vex128, EXx, Ib } }, |
10379 | { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, |
9878 | }, |
10380 | }, |
9879 | 10381 | ||
9880 | /* VEX_LEN_0FXOP_09_80 */ |
10382 | /* VEX_LEN_0FXOP_09_80 */ |
9881 | { |
10383 | { |
9882 | { "vfrczps", { XM, EXxmm } }, |
10384 | { "vfrczps", { XM, EXxmm }, 0 }, |
9883 | { "vfrczps", { XM, EXymmq } }, |
10385 | { "vfrczps", { XM, EXymmq }, 0 }, |
9884 | }, |
10386 | }, |
9885 | 10387 | ||
9886 | /* VEX_LEN_0FXOP_09_81 */ |
10388 | /* VEX_LEN_0FXOP_09_81 */ |
9887 | { |
10389 | { |
9888 | { "vfrczpd", { XM, EXxmm } }, |
10390 | { "vfrczpd", { XM, EXxmm }, 0 }, |
9889 | { "vfrczpd", { XM, EXymmq } }, |
10391 | { "vfrczpd", { XM, EXymmq }, 0 }, |
9890 | }, |
10392 | }, |
9891 | }; |
10393 | }; |
9892 | 10394 | ||
9893 | static const struct dis386 vex_w_table[][2] = { |
10395 | static const struct dis386 vex_w_table[][2] = { |
9894 | { |
10396 | { |
9895 | /* VEX_W_0F10_P_0 */ |
10397 | /* VEX_W_0F10_P_0 */ |
9896 | { "vmovups", { XM, EXx } }, |
10398 | { "vmovups", { XM, EXx }, 0 }, |
9897 | }, |
10399 | }, |
9898 | { |
10400 | { |
9899 | /* VEX_W_0F10_P_1 */ |
10401 | /* VEX_W_0F10_P_1 */ |
9900 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar } }, |
10402 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
9901 | }, |
10403 | }, |
9902 | { |
10404 | { |
9903 | /* VEX_W_0F10_P_2 */ |
10405 | /* VEX_W_0F10_P_2 */ |
9904 | { "vmovupd", { XM, EXx } }, |
10406 | { "vmovupd", { XM, EXx }, 0 }, |
9905 | }, |
10407 | }, |
9906 | { |
10408 | { |
9907 | /* VEX_W_0F10_P_3 */ |
10409 | /* VEX_W_0F10_P_3 */ |
9908 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } }, |
10410 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
9909 | }, |
10411 | }, |
9910 | { |
10412 | { |
9911 | /* VEX_W_0F11_P_0 */ |
10413 | /* VEX_W_0F11_P_0 */ |
9912 | { "vmovups", { EXxS, XM } }, |
10414 | { "vmovups", { EXxS, XM }, 0 }, |
9913 | }, |
10415 | }, |
9914 | { |
10416 | { |
9915 | /* VEX_W_0F11_P_1 */ |
10417 | /* VEX_W_0F11_P_1 */ |
9916 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } }, |
10418 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
9917 | }, |
10419 | }, |
9918 | { |
10420 | { |
9919 | /* VEX_W_0F11_P_2 */ |
10421 | /* VEX_W_0F11_P_2 */ |
9920 | { "vmovupd", { EXxS, XM } }, |
10422 | { "vmovupd", { EXxS, XM }, 0 }, |
9921 | }, |
10423 | }, |
9922 | { |
10424 | { |
9923 | /* VEX_W_0F11_P_3 */ |
10425 | /* VEX_W_0F11_P_3 */ |
9924 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } }, |
10426 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
9925 | }, |
10427 | }, |
9926 | { |
10428 | { |
9927 | /* VEX_W_0F12_P_0_M_0 */ |
10429 | /* VEX_W_0F12_P_0_M_0 */ |
9928 | { "vmovlps", { XM, Vex128, EXq } }, |
10430 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
9929 | }, |
10431 | }, |
9930 | { |
10432 | { |
9931 | /* VEX_W_0F12_P_0_M_1 */ |
10433 | /* VEX_W_0F12_P_0_M_1 */ |
9932 | { "vmovhlps", { XM, Vex128, EXq } }, |
10434 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
9933 | }, |
10435 | }, |
9934 | { |
10436 | { |
9935 | /* VEX_W_0F12_P_1 */ |
10437 | /* VEX_W_0F12_P_1 */ |
9936 | { "vmovsldup", { XM, EXx } }, |
10438 | { "vmovsldup", { XM, EXx }, 0 }, |
9937 | }, |
10439 | }, |
9938 | { |
10440 | { |
9939 | /* VEX_W_0F12_P_2 */ |
10441 | /* VEX_W_0F12_P_2 */ |
9940 | { "vmovlpd", { XM, Vex128, EXq } }, |
10442 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
9941 | }, |
10443 | }, |
9942 | { |
10444 | { |
9943 | /* VEX_W_0F12_P_3 */ |
10445 | /* VEX_W_0F12_P_3 */ |
9944 | { "vmovddup", { XM, EXymmq } }, |
10446 | { "vmovddup", { XM, EXymmq }, 0 }, |
9945 | }, |
10447 | }, |
9946 | { |
10448 | { |
9947 | /* VEX_W_0F13_M_0 */ |
10449 | /* VEX_W_0F13_M_0 */ |
9948 | { "vmovlpX", { EXq, XM } }, |
10450 | { "vmovlpX", { EXq, XM }, 0 }, |
9949 | }, |
10451 | }, |
9950 | { |
10452 | { |
9951 | /* VEX_W_0F14 */ |
10453 | /* VEX_W_0F14 */ |
9952 | { "vunpcklpX", { XM, Vex, EXx } }, |
10454 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
9953 | }, |
10455 | }, |
9954 | { |
10456 | { |
9955 | /* VEX_W_0F15 */ |
10457 | /* VEX_W_0F15 */ |
9956 | { "vunpckhpX", { XM, Vex, EXx } }, |
10458 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
9957 | }, |
10459 | }, |
9958 | { |
10460 | { |
9959 | /* VEX_W_0F16_P_0_M_0 */ |
10461 | /* VEX_W_0F16_P_0_M_0 */ |
9960 | { "vmovhps", { XM, Vex128, EXq } }, |
10462 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
9961 | }, |
10463 | }, |
9962 | { |
10464 | { |
9963 | /* VEX_W_0F16_P_0_M_1 */ |
10465 | /* VEX_W_0F16_P_0_M_1 */ |
9964 | { "vmovlhps", { XM, Vex128, EXq } }, |
10466 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
9965 | }, |
10467 | }, |
9966 | { |
10468 | { |
9967 | /* VEX_W_0F16_P_1 */ |
10469 | /* VEX_W_0F16_P_1 */ |
9968 | { "vmovshdup", { XM, EXx } }, |
10470 | { "vmovshdup", { XM, EXx }, 0 }, |
9969 | }, |
10471 | }, |
9970 | { |
10472 | { |
9971 | /* VEX_W_0F16_P_2 */ |
10473 | /* VEX_W_0F16_P_2 */ |
9972 | { "vmovhpd", { XM, Vex128, EXq } }, |
10474 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
9973 | }, |
10475 | }, |
9974 | { |
10476 | { |
9975 | /* VEX_W_0F17_M_0 */ |
10477 | /* VEX_W_0F17_M_0 */ |
9976 | { "vmovhpX", { EXq, XM } }, |
10478 | { "vmovhpX", { EXq, XM }, 0 }, |
9977 | }, |
10479 | }, |
9978 | { |
10480 | { |
9979 | /* VEX_W_0F28 */ |
10481 | /* VEX_W_0F28 */ |
9980 | { "vmovapX", { XM, EXx } }, |
10482 | { "vmovapX", { XM, EXx }, 0 }, |
9981 | }, |
10483 | }, |
9982 | { |
10484 | { |
9983 | /* VEX_W_0F29 */ |
10485 | /* VEX_W_0F29 */ |
9984 | { "vmovapX", { EXxS, XM } }, |
10486 | { "vmovapX", { EXxS, XM }, 0 }, |
9985 | }, |
10487 | }, |
9986 | { |
10488 | { |
9987 | /* VEX_W_0F2B_M_0 */ |
10489 | /* VEX_W_0F2B_M_0 */ |
9988 | { "vmovntpX", { Mx, XM } }, |
10490 | { "vmovntpX", { Mx, XM }, 0 }, |
9989 | }, |
10491 | }, |
9990 | { |
10492 | { |
9991 | /* VEX_W_0F2E_P_0 */ |
10493 | /* VEX_W_0F2E_P_0 */ |
9992 | { "vucomiss", { XMScalar, EXdScalar } }, |
10494 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
9993 | }, |
10495 | }, |
9994 | { |
10496 | { |
9995 | /* VEX_W_0F2E_P_2 */ |
10497 | /* VEX_W_0F2E_P_2 */ |
9996 | { "vucomisd", { XMScalar, EXqScalar } }, |
10498 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
9997 | }, |
10499 | }, |
9998 | { |
10500 | { |
9999 | /* VEX_W_0F2F_P_0 */ |
10501 | /* VEX_W_0F2F_P_0 */ |
10000 | { "vcomiss", { XMScalar, EXdScalar } }, |
10502 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
10001 | }, |
10503 | }, |
10002 | { |
10504 | { |
10003 | /* VEX_W_0F2F_P_2 */ |
10505 | /* VEX_W_0F2F_P_2 */ |
10004 | { "vcomisd", { XMScalar, EXqScalar } }, |
10506 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
10005 | }, |
10507 | }, |
10006 | { |
10508 | { |
10007 | /* VEX_W_0F41_P_0_LEN_1 */ |
10509 | /* VEX_W_0F41_P_0_LEN_1 */ |
- | 10510 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
|
- | 10511 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, |
|
- | 10512 | }, |
|
- | 10513 | { |
|
- | 10514 | /* VEX_W_0F41_P_2_LEN_1 */ |
|
10008 | { "kandw", { MaskG, MaskVex, MaskR } }, |
10515 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
- | 10516 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } |
|
10009 | }, |
10517 | }, |
10010 | { |
10518 | { |
10011 | /* VEX_W_0F42_P_0_LEN_1 */ |
10519 | /* VEX_W_0F42_P_0_LEN_1 */ |
- | 10520 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
|
- | 10521 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, |
|
- | 10522 | }, |
|
- | 10523 | { |
|
- | 10524 | /* VEX_W_0F42_P_2_LEN_1 */ |
|
- | 10525 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
|
10012 | { "kandnw", { MaskG, MaskVex, MaskR } }, |
10526 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, |
10013 | }, |
10527 | }, |
10014 | { |
10528 | { |
10015 | /* VEX_W_0F44_P_0_LEN_0 */ |
10529 | /* VEX_W_0F44_P_0_LEN_0 */ |
- | 10530 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
|
- | 10531 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, |
|
- | 10532 | }, |
|
- | 10533 | { |
|
10016 | { "knotw", { MaskG, MaskR } }, |
10534 | /* VEX_W_0F44_P_2_LEN_0 */ |
- | 10535 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
|
- | 10536 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, |
|
10017 | }, |
10537 | }, |
10018 | { |
10538 | { |
10019 | /* VEX_W_0F45_P_0_LEN_1 */ |
10539 | /* VEX_W_0F45_P_0_LEN_1 */ |
- | 10540 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, |
|
- | 10541 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, |
|
- | 10542 | }, |
|
- | 10543 | { |
|
- | 10544 | /* VEX_W_0F45_P_2_LEN_1 */ |
|
- | 10545 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, |
|
10020 | { "korw", { MaskG, MaskVex, MaskR } }, |
10546 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, |
10021 | }, |
10547 | }, |
10022 | { |
10548 | { |
10023 | /* VEX_W_0F46_P_0_LEN_1 */ |
10549 | /* VEX_W_0F46_P_0_LEN_1 */ |
- | 10550 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, |
|
- | 10551 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, |
|
- | 10552 | }, |
|
- | 10553 | { |
|
- | 10554 | /* VEX_W_0F46_P_2_LEN_1 */ |
|
- | 10555 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, |
|
10024 | { "kxnorw", { MaskG, MaskVex, MaskR } }, |
10556 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, |
10025 | }, |
10557 | }, |
10026 | { |
10558 | { |
10027 | /* VEX_W_0F47_P_0_LEN_1 */ |
10559 | /* VEX_W_0F47_P_0_LEN_1 */ |
- | 10560 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, |
|
- | 10561 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, |
|
- | 10562 | }, |
|
- | 10563 | { |
|
- | 10564 | /* VEX_W_0F47_P_2_LEN_1 */ |
|
- | 10565 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, |
|
10028 | { "kxorw", { MaskG, MaskVex, MaskR } }, |
10566 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, |
- | 10567 | }, |
|
- | 10568 | { |
|
- | 10569 | /* VEX_W_0F4A_P_0_LEN_1 */ |
|
- | 10570 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, |
|
- | 10571 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, |
|
- | 10572 | }, |
|
- | 10573 | { |
|
- | 10574 | /* VEX_W_0F4A_P_2_LEN_1 */ |
|
- | 10575 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, |
|
- | 10576 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, |
|
- | 10577 | }, |
|
- | 10578 | { |
|
- | 10579 | /* VEX_W_0F4B_P_0_LEN_1 */ |
|
- | 10580 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, |
|
- | 10581 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, |
|
10029 | }, |
10582 | }, |
10030 | { |
10583 | { |
10031 | /* VEX_W_0F4B_P_2_LEN_1 */ |
10584 | /* VEX_W_0F4B_P_2_LEN_1 */ |
10032 | { "kunpckbw", { MaskG, MaskVex, MaskR } }, |
10585 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, |
10033 | }, |
10586 | }, |
10034 | { |
10587 | { |
10035 | /* VEX_W_0F50_M_0 */ |
10588 | /* VEX_W_0F50_M_0 */ |
10036 | { "vmovmskpX", { Gdq, XS } }, |
10589 | { "vmovmskpX", { Gdq, XS }, 0 }, |
10037 | }, |
10590 | }, |
10038 | { |
10591 | { |
10039 | /* VEX_W_0F51_P_0 */ |
10592 | /* VEX_W_0F51_P_0 */ |
10040 | { "vsqrtps", { XM, EXx } }, |
10593 | { "vsqrtps", { XM, EXx }, 0 }, |
10041 | }, |
10594 | }, |
10042 | { |
10595 | { |
10043 | /* VEX_W_0F51_P_1 */ |
10596 | /* VEX_W_0F51_P_1 */ |
10044 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
10597 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10045 | }, |
10598 | }, |
10046 | { |
10599 | { |
10047 | /* VEX_W_0F51_P_2 */ |
10600 | /* VEX_W_0F51_P_2 */ |
10048 | { "vsqrtpd", { XM, EXx } }, |
10601 | { "vsqrtpd", { XM, EXx }, 0 }, |
10049 | }, |
10602 | }, |
10050 | { |
10603 | { |
10051 | /* VEX_W_0F51_P_3 */ |
10604 | /* VEX_W_0F51_P_3 */ |
10052 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } }, |
10605 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10053 | }, |
10606 | }, |
10054 | { |
10607 | { |
10055 | /* VEX_W_0F52_P_0 */ |
10608 | /* VEX_W_0F52_P_0 */ |
10056 | { "vrsqrtps", { XM, EXx } }, |
10609 | { "vrsqrtps", { XM, EXx }, 0 }, |
10057 | }, |
10610 | }, |
10058 | { |
10611 | { |
10059 | /* VEX_W_0F52_P_1 */ |
10612 | /* VEX_W_0F52_P_1 */ |
10060 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
10613 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10061 | }, |
10614 | }, |
10062 | { |
10615 | { |
10063 | /* VEX_W_0F53_P_0 */ |
10616 | /* VEX_W_0F53_P_0 */ |
10064 | { "vrcpps", { XM, EXx } }, |
10617 | { "vrcpps", { XM, EXx }, 0 }, |
10065 | }, |
10618 | }, |
10066 | { |
10619 | { |
10067 | /* VEX_W_0F53_P_1 */ |
10620 | /* VEX_W_0F53_P_1 */ |
10068 | { "vrcpss", { XMScalar, VexScalar, EXdScalar } }, |
10621 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10069 | }, |
10622 | }, |
10070 | { |
10623 | { |
10071 | /* VEX_W_0F58_P_0 */ |
10624 | /* VEX_W_0F58_P_0 */ |
10072 | { "vaddps", { XM, Vex, EXx } }, |
10625 | { "vaddps", { XM, Vex, EXx }, 0 }, |
10073 | }, |
10626 | }, |
10074 | { |
10627 | { |
10075 | /* VEX_W_0F58_P_1 */ |
10628 | /* VEX_W_0F58_P_1 */ |
10076 | { "vaddss", { XMScalar, VexScalar, EXdScalar } }, |
10629 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10077 | }, |
10630 | }, |
10078 | { |
10631 | { |
10079 | /* VEX_W_0F58_P_2 */ |
10632 | /* VEX_W_0F58_P_2 */ |
10080 | { "vaddpd", { XM, Vex, EXx } }, |
10633 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
10081 | }, |
10634 | }, |
10082 | { |
10635 | { |
10083 | /* VEX_W_0F58_P_3 */ |
10636 | /* VEX_W_0F58_P_3 */ |
10084 | { "vaddsd", { XMScalar, VexScalar, EXqScalar } }, |
10637 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10085 | }, |
10638 | }, |
10086 | { |
10639 | { |
10087 | /* VEX_W_0F59_P_0 */ |
10640 | /* VEX_W_0F59_P_0 */ |
10088 | { "vmulps", { XM, Vex, EXx } }, |
10641 | { "vmulps", { XM, Vex, EXx }, 0 }, |
10089 | }, |
10642 | }, |
10090 | { |
10643 | { |
10091 | /* VEX_W_0F59_P_1 */ |
10644 | /* VEX_W_0F59_P_1 */ |
10092 | { "vmulss", { XMScalar, VexScalar, EXdScalar } }, |
10645 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10093 | }, |
10646 | }, |
10094 | { |
10647 | { |
10095 | /* VEX_W_0F59_P_2 */ |
10648 | /* VEX_W_0F59_P_2 */ |
10096 | { "vmulpd", { XM, Vex, EXx } }, |
10649 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
10097 | }, |
10650 | }, |
10098 | { |
10651 | { |
10099 | /* VEX_W_0F59_P_3 */ |
10652 | /* VEX_W_0F59_P_3 */ |
10100 | { "vmulsd", { XMScalar, VexScalar, EXqScalar } }, |
10653 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10101 | }, |
10654 | }, |
10102 | { |
10655 | { |
10103 | /* VEX_W_0F5A_P_0 */ |
10656 | /* VEX_W_0F5A_P_0 */ |
10104 | { "vcvtps2pd", { XM, EXxmmq } }, |
10657 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
10105 | }, |
10658 | }, |
10106 | { |
10659 | { |
10107 | /* VEX_W_0F5A_P_1 */ |
10660 | /* VEX_W_0F5A_P_1 */ |
10108 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } }, |
10661 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10109 | }, |
10662 | }, |
10110 | { |
10663 | { |
10111 | /* VEX_W_0F5A_P_3 */ |
10664 | /* VEX_W_0F5A_P_3 */ |
10112 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } }, |
10665 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10113 | }, |
10666 | }, |
10114 | { |
10667 | { |
10115 | /* VEX_W_0F5B_P_0 */ |
10668 | /* VEX_W_0F5B_P_0 */ |
10116 | { "vcvtdq2ps", { XM, EXx } }, |
10669 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
10117 | }, |
10670 | }, |
10118 | { |
10671 | { |
10119 | /* VEX_W_0F5B_P_1 */ |
10672 | /* VEX_W_0F5B_P_1 */ |
10120 | { "vcvttps2dq", { XM, EXx } }, |
10673 | { "vcvttps2dq", { XM, EXx }, 0 }, |
10121 | }, |
10674 | }, |
10122 | { |
10675 | { |
10123 | /* VEX_W_0F5B_P_2 */ |
10676 | /* VEX_W_0F5B_P_2 */ |
10124 | { "vcvtps2dq", { XM, EXx } }, |
10677 | { "vcvtps2dq", { XM, EXx }, 0 }, |
10125 | }, |
10678 | }, |
10126 | { |
10679 | { |
10127 | /* VEX_W_0F5C_P_0 */ |
10680 | /* VEX_W_0F5C_P_0 */ |
10128 | { "vsubps", { XM, Vex, EXx } }, |
10681 | { "vsubps", { XM, Vex, EXx }, 0 }, |
10129 | }, |
10682 | }, |
10130 | { |
10683 | { |
10131 | /* VEX_W_0F5C_P_1 */ |
10684 | /* VEX_W_0F5C_P_1 */ |
10132 | { "vsubss", { XMScalar, VexScalar, EXdScalar } }, |
10685 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10133 | }, |
10686 | }, |
10134 | { |
10687 | { |
10135 | /* VEX_W_0F5C_P_2 */ |
10688 | /* VEX_W_0F5C_P_2 */ |
10136 | { "vsubpd", { XM, Vex, EXx } }, |
10689 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
10137 | }, |
10690 | }, |
10138 | { |
10691 | { |
10139 | /* VEX_W_0F5C_P_3 */ |
10692 | /* VEX_W_0F5C_P_3 */ |
10140 | { "vsubsd", { XMScalar, VexScalar, EXqScalar } }, |
10693 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10141 | }, |
10694 | }, |
10142 | { |
10695 | { |
10143 | /* VEX_W_0F5D_P_0 */ |
10696 | /* VEX_W_0F5D_P_0 */ |
10144 | { "vminps", { XM, Vex, EXx } }, |
10697 | { "vminps", { XM, Vex, EXx }, 0 }, |
10145 | }, |
10698 | }, |
10146 | { |
10699 | { |
10147 | /* VEX_W_0F5D_P_1 */ |
10700 | /* VEX_W_0F5D_P_1 */ |
10148 | { "vminss", { XMScalar, VexScalar, EXdScalar } }, |
10701 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10149 | }, |
10702 | }, |
10150 | { |
10703 | { |
10151 | /* VEX_W_0F5D_P_2 */ |
10704 | /* VEX_W_0F5D_P_2 */ |
10152 | { "vminpd", { XM, Vex, EXx } }, |
10705 | { "vminpd", { XM, Vex, EXx }, 0 }, |
10153 | }, |
10706 | }, |
10154 | { |
10707 | { |
10155 | /* VEX_W_0F5D_P_3 */ |
10708 | /* VEX_W_0F5D_P_3 */ |
10156 | { "vminsd", { XMScalar, VexScalar, EXqScalar } }, |
10709 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10157 | }, |
10710 | }, |
10158 | { |
10711 | { |
10159 | /* VEX_W_0F5E_P_0 */ |
10712 | /* VEX_W_0F5E_P_0 */ |
10160 | { "vdivps", { XM, Vex, EXx } }, |
10713 | { "vdivps", { XM, Vex, EXx }, 0 }, |
10161 | }, |
10714 | }, |
10162 | { |
10715 | { |
10163 | /* VEX_W_0F5E_P_1 */ |
10716 | /* VEX_W_0F5E_P_1 */ |
10164 | { "vdivss", { XMScalar, VexScalar, EXdScalar } }, |
10717 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10165 | }, |
10718 | }, |
10166 | { |
10719 | { |
10167 | /* VEX_W_0F5E_P_2 */ |
10720 | /* VEX_W_0F5E_P_2 */ |
10168 | { "vdivpd", { XM, Vex, EXx } }, |
10721 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
10169 | }, |
10722 | }, |
10170 | { |
10723 | { |
10171 | /* VEX_W_0F5E_P_3 */ |
10724 | /* VEX_W_0F5E_P_3 */ |
10172 | { "vdivsd", { XMScalar, VexScalar, EXqScalar } }, |
10725 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10173 | }, |
10726 | }, |
10174 | { |
10727 | { |
10175 | /* VEX_W_0F5F_P_0 */ |
10728 | /* VEX_W_0F5F_P_0 */ |
10176 | { "vmaxps", { XM, Vex, EXx } }, |
10729 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
10177 | }, |
10730 | }, |
10178 | { |
10731 | { |
10179 | /* VEX_W_0F5F_P_1 */ |
10732 | /* VEX_W_0F5F_P_1 */ |
10180 | { "vmaxss", { XMScalar, VexScalar, EXdScalar } }, |
10733 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10181 | }, |
10734 | }, |
10182 | { |
10735 | { |
10183 | /* VEX_W_0F5F_P_2 */ |
10736 | /* VEX_W_0F5F_P_2 */ |
10184 | { "vmaxpd", { XM, Vex, EXx } }, |
10737 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
10185 | }, |
10738 | }, |
10186 | { |
10739 | { |
10187 | /* VEX_W_0F5F_P_3 */ |
10740 | /* VEX_W_0F5F_P_3 */ |
10188 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar } }, |
10741 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10189 | }, |
10742 | }, |
10190 | { |
10743 | { |
10191 | /* VEX_W_0F60_P_2 */ |
10744 | /* VEX_W_0F60_P_2 */ |
10192 | { "vpunpcklbw", { XM, Vex, EXx } }, |
10745 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
10193 | }, |
10746 | }, |
10194 | { |
10747 | { |
10195 | /* VEX_W_0F61_P_2 */ |
10748 | /* VEX_W_0F61_P_2 */ |
10196 | { "vpunpcklwd", { XM, Vex, EXx } }, |
10749 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
10197 | }, |
10750 | }, |
10198 | { |
10751 | { |
10199 | /* VEX_W_0F62_P_2 */ |
10752 | /* VEX_W_0F62_P_2 */ |
10200 | { "vpunpckldq", { XM, Vex, EXx } }, |
10753 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
10201 | }, |
10754 | }, |
10202 | { |
10755 | { |
10203 | /* VEX_W_0F63_P_2 */ |
10756 | /* VEX_W_0F63_P_2 */ |
10204 | { "vpacksswb", { XM, Vex, EXx } }, |
10757 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
10205 | }, |
10758 | }, |
10206 | { |
10759 | { |
10207 | /* VEX_W_0F64_P_2 */ |
10760 | /* VEX_W_0F64_P_2 */ |
10208 | { "vpcmpgtb", { XM, Vex, EXx } }, |
10761 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
10209 | }, |
10762 | }, |
10210 | { |
10763 | { |
10211 | /* VEX_W_0F65_P_2 */ |
10764 | /* VEX_W_0F65_P_2 */ |
10212 | { "vpcmpgtw", { XM, Vex, EXx } }, |
10765 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
10213 | }, |
10766 | }, |
10214 | { |
10767 | { |
10215 | /* VEX_W_0F66_P_2 */ |
10768 | /* VEX_W_0F66_P_2 */ |
10216 | { "vpcmpgtd", { XM, Vex, EXx } }, |
10769 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
10217 | }, |
10770 | }, |
10218 | { |
10771 | { |
10219 | /* VEX_W_0F67_P_2 */ |
10772 | /* VEX_W_0F67_P_2 */ |
10220 | { "vpackuswb", { XM, Vex, EXx } }, |
10773 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
10221 | }, |
10774 | }, |
10222 | { |
10775 | { |
10223 | /* VEX_W_0F68_P_2 */ |
10776 | /* VEX_W_0F68_P_2 */ |
10224 | { "vpunpckhbw", { XM, Vex, EXx } }, |
10777 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
10225 | }, |
10778 | }, |
10226 | { |
10779 | { |
10227 | /* VEX_W_0F69_P_2 */ |
10780 | /* VEX_W_0F69_P_2 */ |
10228 | { "vpunpckhwd", { XM, Vex, EXx } }, |
10781 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
10229 | }, |
10782 | }, |
10230 | { |
10783 | { |
10231 | /* VEX_W_0F6A_P_2 */ |
10784 | /* VEX_W_0F6A_P_2 */ |
10232 | { "vpunpckhdq", { XM, Vex, EXx } }, |
10785 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
10233 | }, |
10786 | }, |
10234 | { |
10787 | { |
10235 | /* VEX_W_0F6B_P_2 */ |
10788 | /* VEX_W_0F6B_P_2 */ |
10236 | { "vpackssdw", { XM, Vex, EXx } }, |
10789 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
10237 | }, |
10790 | }, |
10238 | { |
10791 | { |
10239 | /* VEX_W_0F6C_P_2 */ |
10792 | /* VEX_W_0F6C_P_2 */ |
10240 | { "vpunpcklqdq", { XM, Vex, EXx } }, |
10793 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
10241 | }, |
10794 | }, |
10242 | { |
10795 | { |
10243 | /* VEX_W_0F6D_P_2 */ |
10796 | /* VEX_W_0F6D_P_2 */ |
10244 | { "vpunpckhqdq", { XM, Vex, EXx } }, |
10797 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
10245 | }, |
10798 | }, |
10246 | { |
10799 | { |
10247 | /* VEX_W_0F6F_P_1 */ |
10800 | /* VEX_W_0F6F_P_1 */ |
10248 | { "vmovdqu", { XM, EXx } }, |
10801 | { "vmovdqu", { XM, EXx }, 0 }, |
10249 | }, |
10802 | }, |
10250 | { |
10803 | { |
10251 | /* VEX_W_0F6F_P_2 */ |
10804 | /* VEX_W_0F6F_P_2 */ |
10252 | { "vmovdqa", { XM, EXx } }, |
10805 | { "vmovdqa", { XM, EXx }, 0 }, |
10253 | }, |
10806 | }, |
10254 | { |
10807 | { |
10255 | /* VEX_W_0F70_P_1 */ |
10808 | /* VEX_W_0F70_P_1 */ |
10256 | { "vpshufhw", { XM, EXx, Ib } }, |
10809 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
10257 | }, |
10810 | }, |
10258 | { |
10811 | { |
10259 | /* VEX_W_0F70_P_2 */ |
10812 | /* VEX_W_0F70_P_2 */ |
10260 | { "vpshufd", { XM, EXx, Ib } }, |
10813 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
10261 | }, |
10814 | }, |
10262 | { |
10815 | { |
10263 | /* VEX_W_0F70_P_3 */ |
10816 | /* VEX_W_0F70_P_3 */ |
10264 | { "vpshuflw", { XM, EXx, Ib } }, |
10817 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
10265 | }, |
10818 | }, |
10266 | { |
10819 | { |
10267 | /* VEX_W_0F71_R_2_P_2 */ |
10820 | /* VEX_W_0F71_R_2_P_2 */ |
10268 | { "vpsrlw", { Vex, XS, Ib } }, |
10821 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
10269 | }, |
10822 | }, |
10270 | { |
10823 | { |
10271 | /* VEX_W_0F71_R_4_P_2 */ |
10824 | /* VEX_W_0F71_R_4_P_2 */ |
10272 | { "vpsraw", { Vex, XS, Ib } }, |
10825 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
10273 | }, |
10826 | }, |
10274 | { |
10827 | { |
10275 | /* VEX_W_0F71_R_6_P_2 */ |
10828 | /* VEX_W_0F71_R_6_P_2 */ |
10276 | { "vpsllw", { Vex, XS, Ib } }, |
10829 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
10277 | }, |
10830 | }, |
10278 | { |
10831 | { |
10279 | /* VEX_W_0F72_R_2_P_2 */ |
10832 | /* VEX_W_0F72_R_2_P_2 */ |
10280 | { "vpsrld", { Vex, XS, Ib } }, |
10833 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
10281 | }, |
10834 | }, |
10282 | { |
10835 | { |
10283 | /* VEX_W_0F72_R_4_P_2 */ |
10836 | /* VEX_W_0F72_R_4_P_2 */ |
10284 | { "vpsrad", { Vex, XS, Ib } }, |
10837 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
10285 | }, |
10838 | }, |
10286 | { |
10839 | { |
10287 | /* VEX_W_0F72_R_6_P_2 */ |
10840 | /* VEX_W_0F72_R_6_P_2 */ |
10288 | { "vpslld", { Vex, XS, Ib } }, |
10841 | { "vpslld", { Vex, XS, Ib }, 0 }, |
10289 | }, |
10842 | }, |
10290 | { |
10843 | { |
10291 | /* VEX_W_0F73_R_2_P_2 */ |
10844 | /* VEX_W_0F73_R_2_P_2 */ |
10292 | { "vpsrlq", { Vex, XS, Ib } }, |
10845 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
10293 | }, |
10846 | }, |
10294 | { |
10847 | { |
10295 | /* VEX_W_0F73_R_3_P_2 */ |
10848 | /* VEX_W_0F73_R_3_P_2 */ |
10296 | { "vpsrldq", { Vex, XS, Ib } }, |
10849 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
10297 | }, |
10850 | }, |
10298 | { |
10851 | { |
10299 | /* VEX_W_0F73_R_6_P_2 */ |
10852 | /* VEX_W_0F73_R_6_P_2 */ |
10300 | { "vpsllq", { Vex, XS, Ib } }, |
10853 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
10301 | }, |
10854 | }, |
10302 | { |
10855 | { |
10303 | /* VEX_W_0F73_R_7_P_2 */ |
10856 | /* VEX_W_0F73_R_7_P_2 */ |
10304 | { "vpslldq", { Vex, XS, Ib } }, |
10857 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
10305 | }, |
10858 | }, |
10306 | { |
10859 | { |
10307 | /* VEX_W_0F74_P_2 */ |
10860 | /* VEX_W_0F74_P_2 */ |
10308 | { "vpcmpeqb", { XM, Vex, EXx } }, |
10861 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
10309 | }, |
10862 | }, |
10310 | { |
10863 | { |
10311 | /* VEX_W_0F75_P_2 */ |
10864 | /* VEX_W_0F75_P_2 */ |
10312 | { "vpcmpeqw", { XM, Vex, EXx } }, |
10865 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
10313 | }, |
10866 | }, |
10314 | { |
10867 | { |
10315 | /* VEX_W_0F76_P_2 */ |
10868 | /* VEX_W_0F76_P_2 */ |
10316 | { "vpcmpeqd", { XM, Vex, EXx } }, |
10869 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
10317 | }, |
10870 | }, |
10318 | { |
10871 | { |
10319 | /* VEX_W_0F77_P_0 */ |
10872 | /* VEX_W_0F77_P_0 */ |
10320 | { "", { VZERO } }, |
10873 | { "", { VZERO }, 0 }, |
10321 | }, |
10874 | }, |
10322 | { |
10875 | { |
10323 | /* VEX_W_0F7C_P_2 */ |
10876 | /* VEX_W_0F7C_P_2 */ |
10324 | { "vhaddpd", { XM, Vex, EXx } }, |
10877 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
10325 | }, |
10878 | }, |
10326 | { |
10879 | { |
10327 | /* VEX_W_0F7C_P_3 */ |
10880 | /* VEX_W_0F7C_P_3 */ |
10328 | { "vhaddps", { XM, Vex, EXx } }, |
10881 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
10329 | }, |
10882 | }, |
10330 | { |
10883 | { |
10331 | /* VEX_W_0F7D_P_2 */ |
10884 | /* VEX_W_0F7D_P_2 */ |
10332 | { "vhsubpd", { XM, Vex, EXx } }, |
10885 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
10333 | }, |
10886 | }, |
10334 | { |
10887 | { |
10335 | /* VEX_W_0F7D_P_3 */ |
10888 | /* VEX_W_0F7D_P_3 */ |
10336 | { "vhsubps", { XM, Vex, EXx } }, |
10889 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
10337 | }, |
10890 | }, |
10338 | { |
10891 | { |
10339 | /* VEX_W_0F7E_P_1 */ |
10892 | /* VEX_W_0F7E_P_1 */ |
10340 | { "vmovq", { XMScalar, EXqScalar } }, |
10893 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
10341 | }, |
10894 | }, |
10342 | { |
10895 | { |
10343 | /* VEX_W_0F7F_P_1 */ |
10896 | /* VEX_W_0F7F_P_1 */ |
10344 | { "vmovdqu", { EXxS, XM } }, |
10897 | { "vmovdqu", { EXxS, XM }, 0 }, |
10345 | }, |
10898 | }, |
10346 | { |
10899 | { |
10347 | /* VEX_W_0F7F_P_2 */ |
10900 | /* VEX_W_0F7F_P_2 */ |
10348 | { "vmovdqa", { EXxS, XM } }, |
10901 | { "vmovdqa", { EXxS, XM }, 0 }, |
10349 | }, |
10902 | }, |
10350 | { |
10903 | { |
10351 | /* VEX_W_0F90_P_0_LEN_0 */ |
10904 | /* VEX_W_0F90_P_0_LEN_0 */ |
10352 | { "kmovw", { MaskG, MaskE } }, |
10905 | { "kmovw", { MaskG, MaskE }, 0 }, |
- | 10906 | { "kmovq", { MaskG, MaskE }, 0 }, |
|
- | 10907 | }, |
|
- | 10908 | { |
|
- | 10909 | /* VEX_W_0F90_P_2_LEN_0 */ |
|
- | 10910 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
|
- | 10911 | { "kmovd", { MaskG, MaskBDE }, 0 }, |
|
10353 | }, |
10912 | }, |
10354 | { |
10913 | { |
10355 | /* VEX_W_0F91_P_0_LEN_0 */ |
10914 | /* VEX_W_0F91_P_0_LEN_0 */ |
- | 10915 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, |
|
- | 10916 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, |
|
- | 10917 | }, |
|
- | 10918 | { |
|
10356 | { "kmovw", { Ew, MaskG } }, |
10919 | /* VEX_W_0F91_P_2_LEN_0 */ |
- | 10920 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, |
|
- | 10921 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, |
|
10357 | }, |
10922 | }, |
10358 | { |
10923 | { |
10359 | /* VEX_W_0F92_P_0_LEN_0 */ |
10924 | /* VEX_W_0F92_P_0_LEN_0 */ |
- | 10925 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, |
|
- | 10926 | }, |
|
- | 10927 | { |
|
10360 | { "kmovw", { MaskG, Rdq } }, |
10928 | /* VEX_W_0F92_P_2_LEN_0 */ |
- | 10929 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, |
|
- | 10930 | }, |
|
- | 10931 | { |
|
- | 10932 | /* VEX_W_0F92_P_3_LEN_0 */ |
|
- | 10933 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, |
|
- | 10934 | { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, |
|
10361 | }, |
10935 | }, |
10362 | { |
10936 | { |
10363 | /* VEX_W_0F93_P_0_LEN_0 */ |
10937 | /* VEX_W_0F93_P_0_LEN_0 */ |
- | 10938 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, |
|
- | 10939 | }, |
|
- | 10940 | { |
|
10364 | { "kmovw", { Gdq, MaskR } }, |
10941 | /* VEX_W_0F93_P_2_LEN_0 */ |
- | 10942 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, |
|
- | 10943 | }, |
|
- | 10944 | { |
|
- | 10945 | /* VEX_W_0F93_P_3_LEN_0 */ |
|
- | 10946 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, |
|
- | 10947 | { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, |
|
10365 | }, |
10948 | }, |
10366 | { |
10949 | { |
10367 | /* VEX_W_0F98_P_0_LEN_0 */ |
10950 | /* VEX_W_0F98_P_0_LEN_0 */ |
- | 10951 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, |
|
- | 10952 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, |
|
- | 10953 | }, |
|
- | 10954 | { |
|
- | 10955 | /* VEX_W_0F98_P_2_LEN_0 */ |
|
- | 10956 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, |
|
10368 | { "kortestw", { MaskG, MaskR } }, |
10957 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, |
- | 10958 | }, |
|
- | 10959 | { |
|
- | 10960 | /* VEX_W_0F99_P_0_LEN_0 */ |
|
- | 10961 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, |
|
- | 10962 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, |
|
- | 10963 | }, |
|
- | 10964 | { |
|
- | 10965 | /* VEX_W_0F99_P_2_LEN_0 */ |
|
- | 10966 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, |
|
- | 10967 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, |
|
10369 | }, |
10968 | }, |
10370 | { |
10969 | { |
10371 | /* VEX_W_0FAE_R_2_M_0 */ |
10970 | /* VEX_W_0FAE_R_2_M_0 */ |
10372 | { "vldmxcsr", { Md } }, |
10971 | { "vldmxcsr", { Md }, 0 }, |
10373 | }, |
10972 | }, |
10374 | { |
10973 | { |
10375 | /* VEX_W_0FAE_R_3_M_0 */ |
10974 | /* VEX_W_0FAE_R_3_M_0 */ |
10376 | { "vstmxcsr", { Md } }, |
10975 | { "vstmxcsr", { Md }, 0 }, |
10377 | }, |
10976 | }, |
10378 | { |
10977 | { |
10379 | /* VEX_W_0FC2_P_0 */ |
10978 | /* VEX_W_0FC2_P_0 */ |
10380 | { "vcmpps", { XM, Vex, EXx, VCMP } }, |
10979 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
10381 | }, |
10980 | }, |
10382 | { |
10981 | { |
10383 | /* VEX_W_0FC2_P_1 */ |
10982 | /* VEX_W_0FC2_P_1 */ |
10384 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } }, |
10983 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
10385 | }, |
10984 | }, |
10386 | { |
10985 | { |
10387 | /* VEX_W_0FC2_P_2 */ |
10986 | /* VEX_W_0FC2_P_2 */ |
10388 | { "vcmppd", { XM, Vex, EXx, VCMP } }, |
10987 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
10389 | }, |
10988 | }, |
10390 | { |
10989 | { |
10391 | /* VEX_W_0FC2_P_3 */ |
10990 | /* VEX_W_0FC2_P_3 */ |
10392 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } }, |
10991 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
10393 | }, |
10992 | }, |
10394 | { |
10993 | { |
10395 | /* VEX_W_0FC4_P_2 */ |
10994 | /* VEX_W_0FC4_P_2 */ |
10396 | { "vpinsrw", { XM, Vex128, Edqw, Ib } }, |
10995 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
10397 | }, |
10996 | }, |
10398 | { |
10997 | { |
10399 | /* VEX_W_0FC5_P_2 */ |
10998 | /* VEX_W_0FC5_P_2 */ |
10400 | { "vpextrw", { Gdq, XS, Ib } }, |
10999 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
10401 | }, |
11000 | }, |
10402 | { |
11001 | { |
10403 | /* VEX_W_0FD0_P_2 */ |
11002 | /* VEX_W_0FD0_P_2 */ |
10404 | { "vaddsubpd", { XM, Vex, EXx } }, |
11003 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
10405 | }, |
11004 | }, |
10406 | { |
11005 | { |
10407 | /* VEX_W_0FD0_P_3 */ |
11006 | /* VEX_W_0FD0_P_3 */ |
10408 | { "vaddsubps", { XM, Vex, EXx } }, |
11007 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
10409 | }, |
11008 | }, |
10410 | { |
11009 | { |
10411 | /* VEX_W_0FD1_P_2 */ |
11010 | /* VEX_W_0FD1_P_2 */ |
10412 | { "vpsrlw", { XM, Vex, EXxmm } }, |
11011 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
10413 | }, |
11012 | }, |
10414 | { |
11013 | { |
10415 | /* VEX_W_0FD2_P_2 */ |
11014 | /* VEX_W_0FD2_P_2 */ |
10416 | { "vpsrld", { XM, Vex, EXxmm } }, |
11015 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
10417 | }, |
11016 | }, |
10418 | { |
11017 | { |
10419 | /* VEX_W_0FD3_P_2 */ |
11018 | /* VEX_W_0FD3_P_2 */ |
10420 | { "vpsrlq", { XM, Vex, EXxmm } }, |
11019 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
10421 | }, |
11020 | }, |
10422 | { |
11021 | { |
10423 | /* VEX_W_0FD4_P_2 */ |
11022 | /* VEX_W_0FD4_P_2 */ |
10424 | { "vpaddq", { XM, Vex, EXx } }, |
11023 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
10425 | }, |
11024 | }, |
10426 | { |
11025 | { |
10427 | /* VEX_W_0FD5_P_2 */ |
11026 | /* VEX_W_0FD5_P_2 */ |
10428 | { "vpmullw", { XM, Vex, EXx } }, |
11027 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
10429 | }, |
11028 | }, |
10430 | { |
11029 | { |
10431 | /* VEX_W_0FD6_P_2 */ |
11030 | /* VEX_W_0FD6_P_2 */ |
10432 | { "vmovq", { EXqScalarS, XMScalar } }, |
11031 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
10433 | }, |
11032 | }, |
10434 | { |
11033 | { |
10435 | /* VEX_W_0FD7_P_2_M_1 */ |
11034 | /* VEX_W_0FD7_P_2_M_1 */ |
10436 | { "vpmovmskb", { Gdq, XS } }, |
11035 | { "vpmovmskb", { Gdq, XS }, 0 }, |
10437 | }, |
11036 | }, |
10438 | { |
11037 | { |
10439 | /* VEX_W_0FD8_P_2 */ |
11038 | /* VEX_W_0FD8_P_2 */ |
10440 | { "vpsubusb", { XM, Vex, EXx } }, |
11039 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
10441 | }, |
11040 | }, |
10442 | { |
11041 | { |
10443 | /* VEX_W_0FD9_P_2 */ |
11042 | /* VEX_W_0FD9_P_2 */ |
10444 | { "vpsubusw", { XM, Vex, EXx } }, |
11043 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
10445 | }, |
11044 | }, |
10446 | { |
11045 | { |
10447 | /* VEX_W_0FDA_P_2 */ |
11046 | /* VEX_W_0FDA_P_2 */ |
10448 | { "vpminub", { XM, Vex, EXx } }, |
11047 | { "vpminub", { XM, Vex, EXx }, 0 }, |
10449 | }, |
11048 | }, |
10450 | { |
11049 | { |
10451 | /* VEX_W_0FDB_P_2 */ |
11050 | /* VEX_W_0FDB_P_2 */ |
10452 | { "vpand", { XM, Vex, EXx } }, |
11051 | { "vpand", { XM, Vex, EXx }, 0 }, |
10453 | }, |
11052 | }, |
10454 | { |
11053 | { |
10455 | /* VEX_W_0FDC_P_2 */ |
11054 | /* VEX_W_0FDC_P_2 */ |
10456 | { "vpaddusb", { XM, Vex, EXx } }, |
11055 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
10457 | }, |
11056 | }, |
10458 | { |
11057 | { |
10459 | /* VEX_W_0FDD_P_2 */ |
11058 | /* VEX_W_0FDD_P_2 */ |
10460 | { "vpaddusw", { XM, Vex, EXx } }, |
11059 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
10461 | }, |
11060 | }, |
10462 | { |
11061 | { |
10463 | /* VEX_W_0FDE_P_2 */ |
11062 | /* VEX_W_0FDE_P_2 */ |
10464 | { "vpmaxub", { XM, Vex, EXx } }, |
11063 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
10465 | }, |
11064 | }, |
10466 | { |
11065 | { |
10467 | /* VEX_W_0FDF_P_2 */ |
11066 | /* VEX_W_0FDF_P_2 */ |
10468 | { "vpandn", { XM, Vex, EXx } }, |
11067 | { "vpandn", { XM, Vex, EXx }, 0 }, |
10469 | }, |
11068 | }, |
10470 | { |
11069 | { |
10471 | /* VEX_W_0FE0_P_2 */ |
11070 | /* VEX_W_0FE0_P_2 */ |
10472 | { "vpavgb", { XM, Vex, EXx } }, |
11071 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
10473 | }, |
11072 | }, |
10474 | { |
11073 | { |
10475 | /* VEX_W_0FE1_P_2 */ |
11074 | /* VEX_W_0FE1_P_2 */ |
10476 | { "vpsraw", { XM, Vex, EXxmm } }, |
11075 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
10477 | }, |
11076 | }, |
10478 | { |
11077 | { |
10479 | /* VEX_W_0FE2_P_2 */ |
11078 | /* VEX_W_0FE2_P_2 */ |
10480 | { "vpsrad", { XM, Vex, EXxmm } }, |
11079 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
10481 | }, |
11080 | }, |
10482 | { |
11081 | { |
10483 | /* VEX_W_0FE3_P_2 */ |
11082 | /* VEX_W_0FE3_P_2 */ |
10484 | { "vpavgw", { XM, Vex, EXx } }, |
11083 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
10485 | }, |
11084 | }, |
10486 | { |
11085 | { |
10487 | /* VEX_W_0FE4_P_2 */ |
11086 | /* VEX_W_0FE4_P_2 */ |
10488 | { "vpmulhuw", { XM, Vex, EXx } }, |
11087 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
10489 | }, |
11088 | }, |
10490 | { |
11089 | { |
10491 | /* VEX_W_0FE5_P_2 */ |
11090 | /* VEX_W_0FE5_P_2 */ |
10492 | { "vpmulhw", { XM, Vex, EXx } }, |
11091 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
10493 | }, |
11092 | }, |
10494 | { |
11093 | { |
10495 | /* VEX_W_0FE6_P_1 */ |
11094 | /* VEX_W_0FE6_P_1 */ |
10496 | { "vcvtdq2pd", { XM, EXxmmq } }, |
11095 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
10497 | }, |
11096 | }, |
10498 | { |
11097 | { |
10499 | /* VEX_W_0FE6_P_2 */ |
11098 | /* VEX_W_0FE6_P_2 */ |
10500 | { "vcvttpd2dq%XY", { XMM, EXx } }, |
11099 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
10501 | }, |
11100 | }, |
10502 | { |
11101 | { |
10503 | /* VEX_W_0FE6_P_3 */ |
11102 | /* VEX_W_0FE6_P_3 */ |
10504 | { "vcvtpd2dq%XY", { XMM, EXx } }, |
11103 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
10505 | }, |
11104 | }, |
10506 | { |
11105 | { |
10507 | /* VEX_W_0FE7_P_2_M_0 */ |
11106 | /* VEX_W_0FE7_P_2_M_0 */ |
10508 | { "vmovntdq", { Mx, XM } }, |
11107 | { "vmovntdq", { Mx, XM }, 0 }, |
10509 | }, |
11108 | }, |
10510 | { |
11109 | { |
10511 | /* VEX_W_0FE8_P_2 */ |
11110 | /* VEX_W_0FE8_P_2 */ |
10512 | { "vpsubsb", { XM, Vex, EXx } }, |
11111 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
10513 | }, |
11112 | }, |
10514 | { |
11113 | { |
10515 | /* VEX_W_0FE9_P_2 */ |
11114 | /* VEX_W_0FE9_P_2 */ |
10516 | { "vpsubsw", { XM, Vex, EXx } }, |
11115 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
10517 | }, |
11116 | }, |
10518 | { |
11117 | { |
10519 | /* VEX_W_0FEA_P_2 */ |
11118 | /* VEX_W_0FEA_P_2 */ |
10520 | { "vpminsw", { XM, Vex, EXx } }, |
11119 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
10521 | }, |
11120 | }, |
10522 | { |
11121 | { |
10523 | /* VEX_W_0FEB_P_2 */ |
11122 | /* VEX_W_0FEB_P_2 */ |
10524 | { "vpor", { XM, Vex, EXx } }, |
11123 | { "vpor", { XM, Vex, EXx }, 0 }, |
10525 | }, |
11124 | }, |
10526 | { |
11125 | { |
10527 | /* VEX_W_0FEC_P_2 */ |
11126 | /* VEX_W_0FEC_P_2 */ |
10528 | { "vpaddsb", { XM, Vex, EXx } }, |
11127 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
10529 | }, |
11128 | }, |
10530 | { |
11129 | { |
10531 | /* VEX_W_0FED_P_2 */ |
11130 | /* VEX_W_0FED_P_2 */ |
10532 | { "vpaddsw", { XM, Vex, EXx } }, |
11131 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
10533 | }, |
11132 | }, |
10534 | { |
11133 | { |
10535 | /* VEX_W_0FEE_P_2 */ |
11134 | /* VEX_W_0FEE_P_2 */ |
10536 | { "vpmaxsw", { XM, Vex, EXx } }, |
11135 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
10537 | }, |
11136 | }, |
10538 | { |
11137 | { |
10539 | /* VEX_W_0FEF_P_2 */ |
11138 | /* VEX_W_0FEF_P_2 */ |
10540 | { "vpxor", { XM, Vex, EXx } }, |
11139 | { "vpxor", { XM, Vex, EXx }, 0 }, |
10541 | }, |
11140 | }, |
10542 | { |
11141 | { |
10543 | /* VEX_W_0FF0_P_3_M_0 */ |
11142 | /* VEX_W_0FF0_P_3_M_0 */ |
10544 | { "vlddqu", { XM, M } }, |
11143 | { "vlddqu", { XM, M }, 0 }, |
10545 | }, |
11144 | }, |
10546 | { |
11145 | { |
10547 | /* VEX_W_0FF1_P_2 */ |
11146 | /* VEX_W_0FF1_P_2 */ |
10548 | { "vpsllw", { XM, Vex, EXxmm } }, |
11147 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
10549 | }, |
11148 | }, |
10550 | { |
11149 | { |
10551 | /* VEX_W_0FF2_P_2 */ |
11150 | /* VEX_W_0FF2_P_2 */ |
10552 | { "vpslld", { XM, Vex, EXxmm } }, |
11151 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
10553 | }, |
11152 | }, |
10554 | { |
11153 | { |
10555 | /* VEX_W_0FF3_P_2 */ |
11154 | /* VEX_W_0FF3_P_2 */ |
10556 | { "vpsllq", { XM, Vex, EXxmm } }, |
11155 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
10557 | }, |
11156 | }, |
10558 | { |
11157 | { |
10559 | /* VEX_W_0FF4_P_2 */ |
11158 | /* VEX_W_0FF4_P_2 */ |
10560 | { "vpmuludq", { XM, Vex, EXx } }, |
11159 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
10561 | }, |
11160 | }, |
10562 | { |
11161 | { |
10563 | /* VEX_W_0FF5_P_2 */ |
11162 | /* VEX_W_0FF5_P_2 */ |
10564 | { "vpmaddwd", { XM, Vex, EXx } }, |
11163 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
10565 | }, |
11164 | }, |
10566 | { |
11165 | { |
10567 | /* VEX_W_0FF6_P_2 */ |
11166 | /* VEX_W_0FF6_P_2 */ |
10568 | { "vpsadbw", { XM, Vex, EXx } }, |
11167 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
10569 | }, |
11168 | }, |
10570 | { |
11169 | { |
10571 | /* VEX_W_0FF7_P_2 */ |
11170 | /* VEX_W_0FF7_P_2 */ |
10572 | { "vmaskmovdqu", { XM, XS } }, |
11171 | { "vmaskmovdqu", { XM, XS }, 0 }, |
10573 | }, |
11172 | }, |
10574 | { |
11173 | { |
10575 | /* VEX_W_0FF8_P_2 */ |
11174 | /* VEX_W_0FF8_P_2 */ |
10576 | { "vpsubb", { XM, Vex, EXx } }, |
11175 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
10577 | }, |
11176 | }, |
10578 | { |
11177 | { |
10579 | /* VEX_W_0FF9_P_2 */ |
11178 | /* VEX_W_0FF9_P_2 */ |
10580 | { "vpsubw", { XM, Vex, EXx } }, |
11179 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
10581 | }, |
11180 | }, |
10582 | { |
11181 | { |
10583 | /* VEX_W_0FFA_P_2 */ |
11182 | /* VEX_W_0FFA_P_2 */ |
10584 | { "vpsubd", { XM, Vex, EXx } }, |
11183 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
10585 | }, |
11184 | }, |
10586 | { |
11185 | { |
10587 | /* VEX_W_0FFB_P_2 */ |
11186 | /* VEX_W_0FFB_P_2 */ |
10588 | { "vpsubq", { XM, Vex, EXx } }, |
11187 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
10589 | }, |
11188 | }, |
10590 | { |
11189 | { |
10591 | /* VEX_W_0FFC_P_2 */ |
11190 | /* VEX_W_0FFC_P_2 */ |
10592 | { "vpaddb", { XM, Vex, EXx } }, |
11191 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
10593 | }, |
11192 | }, |
10594 | { |
11193 | { |
10595 | /* VEX_W_0FFD_P_2 */ |
11194 | /* VEX_W_0FFD_P_2 */ |
10596 | { "vpaddw", { XM, Vex, EXx } }, |
11195 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
10597 | }, |
11196 | }, |
10598 | { |
11197 | { |
10599 | /* VEX_W_0FFE_P_2 */ |
11198 | /* VEX_W_0FFE_P_2 */ |
10600 | { "vpaddd", { XM, Vex, EXx } }, |
11199 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
10601 | }, |
11200 | }, |
10602 | { |
11201 | { |
10603 | /* VEX_W_0F3800_P_2 */ |
11202 | /* VEX_W_0F3800_P_2 */ |
10604 | { "vpshufb", { XM, Vex, EXx } }, |
11203 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
10605 | }, |
11204 | }, |
10606 | { |
11205 | { |
10607 | /* VEX_W_0F3801_P_2 */ |
11206 | /* VEX_W_0F3801_P_2 */ |
10608 | { "vphaddw", { XM, Vex, EXx } }, |
11207 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
10609 | }, |
11208 | }, |
10610 | { |
11209 | { |
10611 | /* VEX_W_0F3802_P_2 */ |
11210 | /* VEX_W_0F3802_P_2 */ |
10612 | { "vphaddd", { XM, Vex, EXx } }, |
11211 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
10613 | }, |
11212 | }, |
10614 | { |
11213 | { |
10615 | /* VEX_W_0F3803_P_2 */ |
11214 | /* VEX_W_0F3803_P_2 */ |
10616 | { "vphaddsw", { XM, Vex, EXx } }, |
11215 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
10617 | }, |
11216 | }, |
10618 | { |
11217 | { |
10619 | /* VEX_W_0F3804_P_2 */ |
11218 | /* VEX_W_0F3804_P_2 */ |
10620 | { "vpmaddubsw", { XM, Vex, EXx } }, |
11219 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
10621 | }, |
11220 | }, |
10622 | { |
11221 | { |
10623 | /* VEX_W_0F3805_P_2 */ |
11222 | /* VEX_W_0F3805_P_2 */ |
10624 | { "vphsubw", { XM, Vex, EXx } }, |
11223 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
10625 | }, |
11224 | }, |
10626 | { |
11225 | { |
10627 | /* VEX_W_0F3806_P_2 */ |
11226 | /* VEX_W_0F3806_P_2 */ |
10628 | { "vphsubd", { XM, Vex, EXx } }, |
11227 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
10629 | }, |
11228 | }, |
10630 | { |
11229 | { |
10631 | /* VEX_W_0F3807_P_2 */ |
11230 | /* VEX_W_0F3807_P_2 */ |
10632 | { "vphsubsw", { XM, Vex, EXx } }, |
11231 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
10633 | }, |
11232 | }, |
10634 | { |
11233 | { |
10635 | /* VEX_W_0F3808_P_2 */ |
11234 | /* VEX_W_0F3808_P_2 */ |
10636 | { "vpsignb", { XM, Vex, EXx } }, |
11235 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
10637 | }, |
11236 | }, |
10638 | { |
11237 | { |
10639 | /* VEX_W_0F3809_P_2 */ |
11238 | /* VEX_W_0F3809_P_2 */ |
10640 | { "vpsignw", { XM, Vex, EXx } }, |
11239 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
10641 | }, |
11240 | }, |
10642 | { |
11241 | { |
10643 | /* VEX_W_0F380A_P_2 */ |
11242 | /* VEX_W_0F380A_P_2 */ |
10644 | { "vpsignd", { XM, Vex, EXx } }, |
11243 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
10645 | }, |
11244 | }, |
10646 | { |
11245 | { |
10647 | /* VEX_W_0F380B_P_2 */ |
11246 | /* VEX_W_0F380B_P_2 */ |
10648 | { "vpmulhrsw", { XM, Vex, EXx } }, |
11247 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
10649 | }, |
11248 | }, |
10650 | { |
11249 | { |
10651 | /* VEX_W_0F380C_P_2 */ |
11250 | /* VEX_W_0F380C_P_2 */ |
10652 | { "vpermilps", { XM, Vex, EXx } }, |
11251 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
10653 | }, |
11252 | }, |
10654 | { |
11253 | { |
10655 | /* VEX_W_0F380D_P_2 */ |
11254 | /* VEX_W_0F380D_P_2 */ |
10656 | { "vpermilpd", { XM, Vex, EXx } }, |
11255 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
10657 | }, |
11256 | }, |
10658 | { |
11257 | { |
10659 | /* VEX_W_0F380E_P_2 */ |
11258 | /* VEX_W_0F380E_P_2 */ |
10660 | { "vtestps", { XM, EXx } }, |
11259 | { "vtestps", { XM, EXx }, 0 }, |
10661 | }, |
11260 | }, |
10662 | { |
11261 | { |
10663 | /* VEX_W_0F380F_P_2 */ |
11262 | /* VEX_W_0F380F_P_2 */ |
10664 | { "vtestpd", { XM, EXx } }, |
11263 | { "vtestpd", { XM, EXx }, 0 }, |
10665 | }, |
11264 | }, |
10666 | { |
11265 | { |
10667 | /* VEX_W_0F3816_P_2 */ |
11266 | /* VEX_W_0F3816_P_2 */ |
10668 | { "vpermps", { XM, Vex, EXx } }, |
11267 | { "vpermps", { XM, Vex, EXx }, 0 }, |
10669 | }, |
11268 | }, |
10670 | { |
11269 | { |
10671 | /* VEX_W_0F3817_P_2 */ |
11270 | /* VEX_W_0F3817_P_2 */ |
10672 | { "vptest", { XM, EXx } }, |
11271 | { "vptest", { XM, EXx }, 0 }, |
10673 | }, |
11272 | }, |
10674 | { |
11273 | { |
10675 | /* VEX_W_0F3818_P_2 */ |
11274 | /* VEX_W_0F3818_P_2 */ |
10676 | { "vbroadcastss", { XM, EXxmm_md } }, |
11275 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
10677 | }, |
11276 | }, |
10678 | { |
11277 | { |
10679 | /* VEX_W_0F3819_P_2 */ |
11278 | /* VEX_W_0F3819_P_2 */ |
10680 | { "vbroadcastsd", { XM, EXxmm_mq } }, |
11279 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
10681 | }, |
11280 | }, |
10682 | { |
11281 | { |
10683 | /* VEX_W_0F381A_P_2_M_0 */ |
11282 | /* VEX_W_0F381A_P_2_M_0 */ |
10684 | { "vbroadcastf128", { XM, Mxmm } }, |
11283 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
10685 | }, |
11284 | }, |
10686 | { |
11285 | { |
10687 | /* VEX_W_0F381C_P_2 */ |
11286 | /* VEX_W_0F381C_P_2 */ |
10688 | { "vpabsb", { XM, EXx } }, |
11287 | { "vpabsb", { XM, EXx }, 0 }, |
10689 | }, |
11288 | }, |
10690 | { |
11289 | { |
10691 | /* VEX_W_0F381D_P_2 */ |
11290 | /* VEX_W_0F381D_P_2 */ |
10692 | { "vpabsw", { XM, EXx } }, |
11291 | { "vpabsw", { XM, EXx }, 0 }, |
10693 | }, |
11292 | }, |
10694 | { |
11293 | { |
10695 | /* VEX_W_0F381E_P_2 */ |
11294 | /* VEX_W_0F381E_P_2 */ |
10696 | { "vpabsd", { XM, EXx } }, |
11295 | { "vpabsd", { XM, EXx }, 0 }, |
10697 | }, |
11296 | }, |
10698 | { |
11297 | { |
10699 | /* VEX_W_0F3820_P_2 */ |
11298 | /* VEX_W_0F3820_P_2 */ |
10700 | { "vpmovsxbw", { XM, EXxmmq } }, |
11299 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
10701 | }, |
11300 | }, |
10702 | { |
11301 | { |
10703 | /* VEX_W_0F3821_P_2 */ |
11302 | /* VEX_W_0F3821_P_2 */ |
10704 | { "vpmovsxbd", { XM, EXxmmqd } }, |
11303 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
10705 | }, |
11304 | }, |
10706 | { |
11305 | { |
10707 | /* VEX_W_0F3822_P_2 */ |
11306 | /* VEX_W_0F3822_P_2 */ |
10708 | { "vpmovsxbq", { XM, EXxmmdw } }, |
11307 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
10709 | }, |
11308 | }, |
10710 | { |
11309 | { |
10711 | /* VEX_W_0F3823_P_2 */ |
11310 | /* VEX_W_0F3823_P_2 */ |
10712 | { "vpmovsxwd", { XM, EXxmmq } }, |
11311 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
10713 | }, |
11312 | }, |
10714 | { |
11313 | { |
10715 | /* VEX_W_0F3824_P_2 */ |
11314 | /* VEX_W_0F3824_P_2 */ |
10716 | { "vpmovsxwq", { XM, EXxmmqd } }, |
11315 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
10717 | }, |
11316 | }, |
10718 | { |
11317 | { |
10719 | /* VEX_W_0F3825_P_2 */ |
11318 | /* VEX_W_0F3825_P_2 */ |
10720 | { "vpmovsxdq", { XM, EXxmmq } }, |
11319 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
10721 | }, |
11320 | }, |
10722 | { |
11321 | { |
10723 | /* VEX_W_0F3828_P_2 */ |
11322 | /* VEX_W_0F3828_P_2 */ |
10724 | { "vpmuldq", { XM, Vex, EXx } }, |
11323 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
10725 | }, |
11324 | }, |
10726 | { |
11325 | { |
10727 | /* VEX_W_0F3829_P_2 */ |
11326 | /* VEX_W_0F3829_P_2 */ |
10728 | { "vpcmpeqq", { XM, Vex, EXx } }, |
11327 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
10729 | }, |
11328 | }, |
10730 | { |
11329 | { |
10731 | /* VEX_W_0F382A_P_2_M_0 */ |
11330 | /* VEX_W_0F382A_P_2_M_0 */ |
10732 | { "vmovntdqa", { XM, Mx } }, |
11331 | { "vmovntdqa", { XM, Mx }, 0 }, |
10733 | }, |
11332 | }, |
10734 | { |
11333 | { |
10735 | /* VEX_W_0F382B_P_2 */ |
11334 | /* VEX_W_0F382B_P_2 */ |
10736 | { "vpackusdw", { XM, Vex, EXx } }, |
11335 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
10737 | }, |
11336 | }, |
10738 | { |
11337 | { |
10739 | /* VEX_W_0F382C_P_2_M_0 */ |
11338 | /* VEX_W_0F382C_P_2_M_0 */ |
10740 | { "vmaskmovps", { XM, Vex, Mx } }, |
11339 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
10741 | }, |
11340 | }, |
10742 | { |
11341 | { |
10743 | /* VEX_W_0F382D_P_2_M_0 */ |
11342 | /* VEX_W_0F382D_P_2_M_0 */ |
10744 | { "vmaskmovpd", { XM, Vex, Mx } }, |
11343 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
10745 | }, |
11344 | }, |
10746 | { |
11345 | { |
10747 | /* VEX_W_0F382E_P_2_M_0 */ |
11346 | /* VEX_W_0F382E_P_2_M_0 */ |
10748 | { "vmaskmovps", { Mx, Vex, XM } }, |
11347 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
10749 | }, |
11348 | }, |
10750 | { |
11349 | { |
10751 | /* VEX_W_0F382F_P_2_M_0 */ |
11350 | /* VEX_W_0F382F_P_2_M_0 */ |
10752 | { "vmaskmovpd", { Mx, Vex, XM } }, |
11351 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
10753 | }, |
11352 | }, |
10754 | { |
11353 | { |
10755 | /* VEX_W_0F3830_P_2 */ |
11354 | /* VEX_W_0F3830_P_2 */ |
10756 | { "vpmovzxbw", { XM, EXxmmq } }, |
11355 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
10757 | }, |
11356 | }, |
10758 | { |
11357 | { |
10759 | /* VEX_W_0F3831_P_2 */ |
11358 | /* VEX_W_0F3831_P_2 */ |
10760 | { "vpmovzxbd", { XM, EXxmmqd } }, |
11359 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
10761 | }, |
11360 | }, |
10762 | { |
11361 | { |
10763 | /* VEX_W_0F3832_P_2 */ |
11362 | /* VEX_W_0F3832_P_2 */ |
10764 | { "vpmovzxbq", { XM, EXxmmdw } }, |
11363 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
10765 | }, |
11364 | }, |
10766 | { |
11365 | { |
10767 | /* VEX_W_0F3833_P_2 */ |
11366 | /* VEX_W_0F3833_P_2 */ |
10768 | { "vpmovzxwd", { XM, EXxmmq } }, |
11367 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
10769 | }, |
11368 | }, |
10770 | { |
11369 | { |
10771 | /* VEX_W_0F3834_P_2 */ |
11370 | /* VEX_W_0F3834_P_2 */ |
10772 | { "vpmovzxwq", { XM, EXxmmqd } }, |
11371 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
10773 | }, |
11372 | }, |
10774 | { |
11373 | { |
10775 | /* VEX_W_0F3835_P_2 */ |
11374 | /* VEX_W_0F3835_P_2 */ |
10776 | { "vpmovzxdq", { XM, EXxmmq } }, |
11375 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
10777 | }, |
11376 | }, |
10778 | { |
11377 | { |
10779 | /* VEX_W_0F3836_P_2 */ |
11378 | /* VEX_W_0F3836_P_2 */ |
10780 | { "vpermd", { XM, Vex, EXx } }, |
11379 | { "vpermd", { XM, Vex, EXx }, 0 }, |
10781 | }, |
11380 | }, |
10782 | { |
11381 | { |
10783 | /* VEX_W_0F3837_P_2 */ |
11382 | /* VEX_W_0F3837_P_2 */ |
10784 | { "vpcmpgtq", { XM, Vex, EXx } }, |
11383 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
10785 | }, |
11384 | }, |
10786 | { |
11385 | { |
10787 | /* VEX_W_0F3838_P_2 */ |
11386 | /* VEX_W_0F3838_P_2 */ |
10788 | { "vpminsb", { XM, Vex, EXx } }, |
11387 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
10789 | }, |
11388 | }, |
10790 | { |
11389 | { |
10791 | /* VEX_W_0F3839_P_2 */ |
11390 | /* VEX_W_0F3839_P_2 */ |
10792 | { "vpminsd", { XM, Vex, EXx } }, |
11391 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
10793 | }, |
11392 | }, |
10794 | { |
11393 | { |
10795 | /* VEX_W_0F383A_P_2 */ |
11394 | /* VEX_W_0F383A_P_2 */ |
10796 | { "vpminuw", { XM, Vex, EXx } }, |
11395 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
10797 | }, |
11396 | }, |
10798 | { |
11397 | { |
10799 | /* VEX_W_0F383B_P_2 */ |
11398 | /* VEX_W_0F383B_P_2 */ |
10800 | { "vpminud", { XM, Vex, EXx } }, |
11399 | { "vpminud", { XM, Vex, EXx }, 0 }, |
10801 | }, |
11400 | }, |
10802 | { |
11401 | { |
10803 | /* VEX_W_0F383C_P_2 */ |
11402 | /* VEX_W_0F383C_P_2 */ |
10804 | { "vpmaxsb", { XM, Vex, EXx } }, |
11403 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
10805 | }, |
11404 | }, |
10806 | { |
11405 | { |
10807 | /* VEX_W_0F383D_P_2 */ |
11406 | /* VEX_W_0F383D_P_2 */ |
10808 | { "vpmaxsd", { XM, Vex, EXx } }, |
11407 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
10809 | }, |
11408 | }, |
10810 | { |
11409 | { |
10811 | /* VEX_W_0F383E_P_2 */ |
11410 | /* VEX_W_0F383E_P_2 */ |
10812 | { "vpmaxuw", { XM, Vex, EXx } }, |
11411 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
10813 | }, |
11412 | }, |
10814 | { |
11413 | { |
10815 | /* VEX_W_0F383F_P_2 */ |
11414 | /* VEX_W_0F383F_P_2 */ |
10816 | { "vpmaxud", { XM, Vex, EXx } }, |
11415 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
10817 | }, |
11416 | }, |
10818 | { |
11417 | { |
10819 | /* VEX_W_0F3840_P_2 */ |
11418 | /* VEX_W_0F3840_P_2 */ |
10820 | { "vpmulld", { XM, Vex, EXx } }, |
11419 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
10821 | }, |
11420 | }, |
10822 | { |
11421 | { |
10823 | /* VEX_W_0F3841_P_2 */ |
11422 | /* VEX_W_0F3841_P_2 */ |
10824 | { "vphminposuw", { XM, EXx } }, |
11423 | { "vphminposuw", { XM, EXx }, 0 }, |
10825 | }, |
11424 | }, |
10826 | { |
11425 | { |
10827 | /* VEX_W_0F3846_P_2 */ |
11426 | /* VEX_W_0F3846_P_2 */ |
10828 | { "vpsravd", { XM, Vex, EXx } }, |
11427 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
10829 | }, |
11428 | }, |
10830 | { |
11429 | { |
10831 | /* VEX_W_0F3858_P_2 */ |
11430 | /* VEX_W_0F3858_P_2 */ |
10832 | { "vpbroadcastd", { XM, EXxmm_md } }, |
11431 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
10833 | }, |
11432 | }, |
10834 | { |
11433 | { |
10835 | /* VEX_W_0F3859_P_2 */ |
11434 | /* VEX_W_0F3859_P_2 */ |
10836 | { "vpbroadcastq", { XM, EXxmm_mq } }, |
11435 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
10837 | }, |
11436 | }, |
10838 | { |
11437 | { |
10839 | /* VEX_W_0F385A_P_2_M_0 */ |
11438 | /* VEX_W_0F385A_P_2_M_0 */ |
10840 | { "vbroadcasti128", { XM, Mxmm } }, |
11439 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
10841 | }, |
11440 | }, |
10842 | { |
11441 | { |
10843 | /* VEX_W_0F3878_P_2 */ |
11442 | /* VEX_W_0F3878_P_2 */ |
10844 | { "vpbroadcastb", { XM, EXxmm_mb } }, |
11443 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
10845 | }, |
11444 | }, |
10846 | { |
11445 | { |
10847 | /* VEX_W_0F3879_P_2 */ |
11446 | /* VEX_W_0F3879_P_2 */ |
10848 | { "vpbroadcastw", { XM, EXxmm_mw } }, |
11447 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
10849 | }, |
11448 | }, |
10850 | { |
11449 | { |
10851 | /* VEX_W_0F38DB_P_2 */ |
11450 | /* VEX_W_0F38DB_P_2 */ |
10852 | { "vaesimc", { XM, EXx } }, |
11451 | { "vaesimc", { XM, EXx }, 0 }, |
10853 | }, |
11452 | }, |
10854 | { |
11453 | { |
10855 | /* VEX_W_0F38DC_P_2 */ |
11454 | /* VEX_W_0F38DC_P_2 */ |
10856 | { "vaesenc", { XM, Vex128, EXx } }, |
11455 | { "vaesenc", { XM, Vex128, EXx }, 0 }, |
10857 | }, |
11456 | }, |
10858 | { |
11457 | { |
10859 | /* VEX_W_0F38DD_P_2 */ |
11458 | /* VEX_W_0F38DD_P_2 */ |
10860 | { "vaesenclast", { XM, Vex128, EXx } }, |
11459 | { "vaesenclast", { XM, Vex128, EXx }, 0 }, |
10861 | }, |
11460 | }, |
10862 | { |
11461 | { |
10863 | /* VEX_W_0F38DE_P_2 */ |
11462 | /* VEX_W_0F38DE_P_2 */ |
10864 | { "vaesdec", { XM, Vex128, EXx } }, |
11463 | { "vaesdec", { XM, Vex128, EXx }, 0 }, |
10865 | }, |
11464 | }, |
10866 | { |
11465 | { |
10867 | /* VEX_W_0F38DF_P_2 */ |
11466 | /* VEX_W_0F38DF_P_2 */ |
10868 | { "vaesdeclast", { XM, Vex128, EXx } }, |
11467 | { "vaesdeclast", { XM, Vex128, EXx }, 0 }, |
10869 | }, |
11468 | }, |
10870 | { |
11469 | { |
10871 | /* VEX_W_0F3A00_P_2 */ |
11470 | /* VEX_W_0F3A00_P_2 */ |
10872 | { Bad_Opcode }, |
11471 | { Bad_Opcode }, |
10873 | { "vpermq", { XM, EXx, Ib } }, |
11472 | { "vpermq", { XM, EXx, Ib }, 0 }, |
10874 | }, |
11473 | }, |
10875 | { |
11474 | { |
10876 | /* VEX_W_0F3A01_P_2 */ |
11475 | /* VEX_W_0F3A01_P_2 */ |
10877 | { Bad_Opcode }, |
11476 | { Bad_Opcode }, |
10878 | { "vpermpd", { XM, EXx, Ib } }, |
11477 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
10879 | }, |
11478 | }, |
10880 | { |
11479 | { |
10881 | /* VEX_W_0F3A02_P_2 */ |
11480 | /* VEX_W_0F3A02_P_2 */ |
10882 | { "vpblendd", { XM, Vex, EXx, Ib } }, |
11481 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
10883 | }, |
11482 | }, |
10884 | { |
11483 | { |
10885 | /* VEX_W_0F3A04_P_2 */ |
11484 | /* VEX_W_0F3A04_P_2 */ |
10886 | { "vpermilps", { XM, EXx, Ib } }, |
11485 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
10887 | }, |
11486 | }, |
10888 | { |
11487 | { |
10889 | /* VEX_W_0F3A05_P_2 */ |
11488 | /* VEX_W_0F3A05_P_2 */ |
10890 | { "vpermilpd", { XM, EXx, Ib } }, |
11489 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
10891 | }, |
11490 | }, |
10892 | { |
11491 | { |
10893 | /* VEX_W_0F3A06_P_2 */ |
11492 | /* VEX_W_0F3A06_P_2 */ |
10894 | { "vperm2f128", { XM, Vex256, EXx, Ib } }, |
11493 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
10895 | }, |
11494 | }, |
10896 | { |
11495 | { |
10897 | /* VEX_W_0F3A08_P_2 */ |
11496 | /* VEX_W_0F3A08_P_2 */ |
10898 | { "vroundps", { XM, EXx, Ib } }, |
11497 | { "vroundps", { XM, EXx, Ib }, 0 }, |
10899 | }, |
11498 | }, |
10900 | { |
11499 | { |
10901 | /* VEX_W_0F3A09_P_2 */ |
11500 | /* VEX_W_0F3A09_P_2 */ |
10902 | { "vroundpd", { XM, EXx, Ib } }, |
11501 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
10903 | }, |
11502 | }, |
10904 | { |
11503 | { |
10905 | /* VEX_W_0F3A0A_P_2 */ |
11504 | /* VEX_W_0F3A0A_P_2 */ |
10906 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } }, |
11505 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
10907 | }, |
11506 | }, |
10908 | { |
11507 | { |
10909 | /* VEX_W_0F3A0B_P_2 */ |
11508 | /* VEX_W_0F3A0B_P_2 */ |
10910 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } }, |
11509 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
10911 | }, |
11510 | }, |
10912 | { |
11511 | { |
10913 | /* VEX_W_0F3A0C_P_2 */ |
11512 | /* VEX_W_0F3A0C_P_2 */ |
10914 | { "vblendps", { XM, Vex, EXx, Ib } }, |
11513 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
10915 | }, |
11514 | }, |
10916 | { |
11515 | { |
10917 | /* VEX_W_0F3A0D_P_2 */ |
11516 | /* VEX_W_0F3A0D_P_2 */ |
10918 | { "vblendpd", { XM, Vex, EXx, Ib } }, |
11517 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
10919 | }, |
11518 | }, |
10920 | { |
11519 | { |
10921 | /* VEX_W_0F3A0E_P_2 */ |
11520 | /* VEX_W_0F3A0E_P_2 */ |
10922 | { "vpblendw", { XM, Vex, EXx, Ib } }, |
11521 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
10923 | }, |
11522 | }, |
10924 | { |
11523 | { |
10925 | /* VEX_W_0F3A0F_P_2 */ |
11524 | /* VEX_W_0F3A0F_P_2 */ |
10926 | { "vpalignr", { XM, Vex, EXx, Ib } }, |
11525 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
10927 | }, |
11526 | }, |
10928 | { |
11527 | { |
10929 | /* VEX_W_0F3A14_P_2 */ |
11528 | /* VEX_W_0F3A14_P_2 */ |
10930 | { "vpextrb", { Edqb, XM, Ib } }, |
11529 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
10931 | }, |
11530 | }, |
10932 | { |
11531 | { |
10933 | /* VEX_W_0F3A15_P_2 */ |
11532 | /* VEX_W_0F3A15_P_2 */ |
10934 | { "vpextrw", { Edqw, XM, Ib } }, |
11533 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
10935 | }, |
11534 | }, |
10936 | { |
11535 | { |
10937 | /* VEX_W_0F3A18_P_2 */ |
11536 | /* VEX_W_0F3A18_P_2 */ |
10938 | { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, |
11537 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
10939 | }, |
11538 | }, |
10940 | { |
11539 | { |
10941 | /* VEX_W_0F3A19_P_2 */ |
11540 | /* VEX_W_0F3A19_P_2 */ |
10942 | { "vextractf128", { EXxmm, XM, Ib } }, |
11541 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
10943 | }, |
11542 | }, |
10944 | { |
11543 | { |
10945 | /* VEX_W_0F3A20_P_2 */ |
11544 | /* VEX_W_0F3A20_P_2 */ |
10946 | { "vpinsrb", { XM, Vex128, Edqb, Ib } }, |
11545 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
10947 | }, |
11546 | }, |
10948 | { |
11547 | { |
10949 | /* VEX_W_0F3A21_P_2 */ |
11548 | /* VEX_W_0F3A21_P_2 */ |
10950 | { "vinsertps", { XM, Vex128, EXd, Ib } }, |
11549 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
10951 | }, |
11550 | }, |
10952 | { |
11551 | { |
10953 | /* VEX_W_0F3A30_P_2 */ |
11552 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
10954 | { Bad_Opcode }, |
11553 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10955 | { "kshiftrw", { MaskG, MaskR, Ib } }, |
11554 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, |
10956 | }, |
11555 | }, |
10957 | { |
11556 | { |
- | 11557 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
|
- | 11558 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
|
- | 11559 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, |
|
- | 11560 | }, |
|
- | 11561 | { |
|
10958 | /* VEX_W_0F3A32_P_2 */ |
11562 | /* VEX_W_0F3A32_P_2_LEN_0 */ |
- | 11563 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
|
- | 11564 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, |
|
- | 11565 | }, |
|
- | 11566 | { |
|
10959 | { Bad_Opcode }, |
11567 | /* VEX_W_0F3A33_P_2_LEN_0 */ |
10960 | { "kshiftlw", { MaskG, MaskR, Ib } }, |
11568 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
- | 11569 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, |
|
10961 | }, |
11570 | }, |
10962 | { |
11571 | { |
10963 | /* VEX_W_0F3A38_P_2 */ |
11572 | /* VEX_W_0F3A38_P_2 */ |
10964 | { "vinserti128", { XM, Vex256, EXxmm, Ib } }, |
11573 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
10965 | }, |
11574 | }, |
10966 | { |
11575 | { |
10967 | /* VEX_W_0F3A39_P_2 */ |
11576 | /* VEX_W_0F3A39_P_2 */ |
10968 | { "vextracti128", { EXxmm, XM, Ib } }, |
11577 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
10969 | }, |
11578 | }, |
10970 | { |
11579 | { |
10971 | /* VEX_W_0F3A40_P_2 */ |
11580 | /* VEX_W_0F3A40_P_2 */ |
10972 | { "vdpps", { XM, Vex, EXx, Ib } }, |
11581 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
10973 | }, |
11582 | }, |
10974 | { |
11583 | { |
10975 | /* VEX_W_0F3A41_P_2 */ |
11584 | /* VEX_W_0F3A41_P_2 */ |
10976 | { "vdppd", { XM, Vex128, EXx, Ib } }, |
11585 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
10977 | }, |
11586 | }, |
10978 | { |
11587 | { |
10979 | /* VEX_W_0F3A42_P_2 */ |
11588 | /* VEX_W_0F3A42_P_2 */ |
10980 | { "vmpsadbw", { XM, Vex, EXx, Ib } }, |
11589 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
10981 | }, |
11590 | }, |
10982 | { |
11591 | { |
10983 | /* VEX_W_0F3A44_P_2 */ |
11592 | /* VEX_W_0F3A44_P_2 */ |
10984 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, |
11593 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, |
10985 | }, |
11594 | }, |
10986 | { |
11595 | { |
10987 | /* VEX_W_0F3A46_P_2 */ |
11596 | /* VEX_W_0F3A46_P_2 */ |
10988 | { "vperm2i128", { XM, Vex256, EXx, Ib } }, |
11597 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
10989 | }, |
11598 | }, |
10990 | { |
11599 | { |
10991 | /* VEX_W_0F3A48_P_2 */ |
11600 | /* VEX_W_0F3A48_P_2 */ |
10992 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11601 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10993 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11602 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10994 | }, |
11603 | }, |
10995 | { |
11604 | { |
10996 | /* VEX_W_0F3A49_P_2 */ |
11605 | /* VEX_W_0F3A49_P_2 */ |
10997 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11606 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10998 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11607 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10999 | }, |
11608 | }, |
11000 | { |
11609 | { |
11001 | /* VEX_W_0F3A4A_P_2 */ |
11610 | /* VEX_W_0F3A4A_P_2 */ |
11002 | { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, |
11611 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
11003 | }, |
11612 | }, |
11004 | { |
11613 | { |
11005 | /* VEX_W_0F3A4B_P_2 */ |
11614 | /* VEX_W_0F3A4B_P_2 */ |
11006 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, |
11615 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
11007 | }, |
11616 | }, |
11008 | { |
11617 | { |
11009 | /* VEX_W_0F3A4C_P_2 */ |
11618 | /* VEX_W_0F3A4C_P_2 */ |
11010 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 } }, |
11619 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
11011 | }, |
11620 | }, |
11012 | { |
11621 | { |
11013 | /* VEX_W_0F3A60_P_2 */ |
11622 | /* VEX_W_0F3A60_P_2 */ |
11014 | { "vpcmpestrm", { XM, EXx, Ib } }, |
11623 | { "vpcmpestrm", { XM, EXx, Ib }, 0 }, |
11015 | }, |
11624 | }, |
11016 | { |
11625 | { |
11017 | /* VEX_W_0F3A61_P_2 */ |
11626 | /* VEX_W_0F3A61_P_2 */ |
11018 | { "vpcmpestri", { XM, EXx, Ib } }, |
11627 | { "vpcmpestri", { XM, EXx, Ib }, 0 }, |
11019 | }, |
11628 | }, |
11020 | { |
11629 | { |
11021 | /* VEX_W_0F3A62_P_2 */ |
11630 | /* VEX_W_0F3A62_P_2 */ |
11022 | { "vpcmpistrm", { XM, EXx, Ib } }, |
11631 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
11023 | }, |
11632 | }, |
11024 | { |
11633 | { |
11025 | /* VEX_W_0F3A63_P_2 */ |
11634 | /* VEX_W_0F3A63_P_2 */ |
11026 | { "vpcmpistri", { XM, EXx, Ib } }, |
11635 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
11027 | }, |
11636 | }, |
11028 | { |
11637 | { |
11029 | /* VEX_W_0F3ADF_P_2 */ |
11638 | /* VEX_W_0F3ADF_P_2 */ |
11030 | { "vaeskeygenassist", { XM, EXx, Ib } }, |
11639 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
11031 | }, |
11640 | }, |
11032 | #define NEED_VEX_W_TABLE |
11641 | #define NEED_VEX_W_TABLE |
11033 | #include "i386-dis-evex.h" |
11642 | #include "i386-dis-evex.h" |
11034 | #undef NEED_VEX_W_TABLE |
11643 | #undef NEED_VEX_W_TABLE |
11035 | }; |
11644 | }; |
11036 | 11645 | ||
11037 | static const struct dis386 mod_table[][2] = { |
11646 | static const struct dis386 mod_table[][2] = { |
11038 | { |
11647 | { |
11039 | /* MOD_8D */ |
11648 | /* MOD_8D */ |
11040 | { "leaS", { Gv, M } }, |
11649 | { "leaS", { Gv, M }, 0 }, |
11041 | }, |
11650 | }, |
11042 | { |
11651 | { |
11043 | /* MOD_C6_REG_7 */ |
11652 | /* MOD_C6_REG_7 */ |
11044 | { Bad_Opcode }, |
11653 | { Bad_Opcode }, |
11045 | { RM_TABLE (RM_C6_REG_7) }, |
11654 | { RM_TABLE (RM_C6_REG_7) }, |
11046 | }, |
11655 | }, |
11047 | { |
11656 | { |
11048 | /* MOD_C7_REG_7 */ |
11657 | /* MOD_C7_REG_7 */ |
11049 | { Bad_Opcode }, |
11658 | { Bad_Opcode }, |
11050 | { RM_TABLE (RM_C7_REG_7) }, |
11659 | { RM_TABLE (RM_C7_REG_7) }, |
11051 | }, |
11660 | }, |
11052 | { |
11661 | { |
- | 11662 | /* MOD_FF_REG_3 */ |
|
- | 11663 | { "Jcall^", { indirEp }, 0 }, |
|
- | 11664 | }, |
|
- | 11665 | { |
|
- | 11666 | /* MOD_FF_REG_5 */ |
|
- | 11667 | { "Jjmp^", { indirEp }, 0 }, |
|
- | 11668 | }, |
|
- | 11669 | { |
|
11053 | /* MOD_0F01_REG_0 */ |
11670 | /* MOD_0F01_REG_0 */ |
11054 | { X86_64_TABLE (X86_64_0F01_REG_0) }, |
11671 | { X86_64_TABLE (X86_64_0F01_REG_0) }, |
11055 | { RM_TABLE (RM_0F01_REG_0) }, |
11672 | { RM_TABLE (RM_0F01_REG_0) }, |
11056 | }, |
11673 | }, |
11057 | { |
11674 | { |
11058 | /* MOD_0F01_REG_1 */ |
11675 | /* MOD_0F01_REG_1 */ |
11059 | { X86_64_TABLE (X86_64_0F01_REG_1) }, |
11676 | { X86_64_TABLE (X86_64_0F01_REG_1) }, |
11060 | { RM_TABLE (RM_0F01_REG_1) }, |
11677 | { RM_TABLE (RM_0F01_REG_1) }, |
11061 | }, |
11678 | }, |
11062 | { |
11679 | { |
11063 | /* MOD_0F01_REG_2 */ |
11680 | /* MOD_0F01_REG_2 */ |
11064 | { X86_64_TABLE (X86_64_0F01_REG_2) }, |
11681 | { X86_64_TABLE (X86_64_0F01_REG_2) }, |
11065 | { RM_TABLE (RM_0F01_REG_2) }, |
11682 | { RM_TABLE (RM_0F01_REG_2) }, |
11066 | }, |
11683 | }, |
11067 | { |
11684 | { |
11068 | /* MOD_0F01_REG_3 */ |
11685 | /* MOD_0F01_REG_3 */ |
11069 | { X86_64_TABLE (X86_64_0F01_REG_3) }, |
11686 | { X86_64_TABLE (X86_64_0F01_REG_3) }, |
11070 | { RM_TABLE (RM_0F01_REG_3) }, |
11687 | { RM_TABLE (RM_0F01_REG_3) }, |
11071 | }, |
11688 | }, |
11072 | { |
11689 | { |
- | 11690 | /* MOD_0F01_REG_5 */ |
|
- | 11691 | { Bad_Opcode }, |
|
- | 11692 | { RM_TABLE (RM_0F01_REG_5) }, |
|
- | 11693 | }, |
|
- | 11694 | { |
|
11073 | /* MOD_0F01_REG_7 */ |
11695 | /* MOD_0F01_REG_7 */ |
11074 | { "invlpg", { Mb } }, |
11696 | { "invlpg", { Mb }, 0 }, |
11075 | { RM_TABLE (RM_0F01_REG_7) }, |
11697 | { RM_TABLE (RM_0F01_REG_7) }, |
11076 | }, |
11698 | }, |
11077 | { |
11699 | { |
11078 | /* MOD_0F12_PREFIX_0 */ |
11700 | /* MOD_0F12_PREFIX_0 */ |
11079 | { "movlps", { XM, EXq } }, |
11701 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11080 | { "movhlps", { XM, EXq } }, |
11702 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, |
11081 | }, |
11703 | }, |
11082 | { |
11704 | { |
11083 | /* MOD_0F13 */ |
11705 | /* MOD_0F13 */ |
11084 | { "movlpX", { EXq, XM } }, |
11706 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
11085 | }, |
11707 | }, |
11086 | { |
11708 | { |
11087 | /* MOD_0F16_PREFIX_0 */ |
11709 | /* MOD_0F16_PREFIX_0 */ |
11088 | { "movhps", { XM, EXq } }, |
11710 | { "movhps", { XM, EXq }, 0 }, |
11089 | { "movlhps", { XM, EXq } }, |
11711 | { "movlhps", { XM, EXq }, 0 }, |
11090 | }, |
11712 | }, |
11091 | { |
11713 | { |
11092 | /* MOD_0F17 */ |
11714 | /* MOD_0F17 */ |
11093 | { "movhpX", { EXq, XM } }, |
11715 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
11094 | }, |
11716 | }, |
11095 | { |
11717 | { |
11096 | /* MOD_0F18_REG_0 */ |
11718 | /* MOD_0F18_REG_0 */ |
11097 | { "prefetchnta", { Mb } }, |
11719 | { "prefetchnta", { Mb }, 0 }, |
11098 | }, |
11720 | }, |
11099 | { |
11721 | { |
11100 | /* MOD_0F18_REG_1 */ |
11722 | /* MOD_0F18_REG_1 */ |
11101 | { "prefetcht0", { Mb } }, |
11723 | { "prefetcht0", { Mb }, 0 }, |
11102 | }, |
11724 | }, |
11103 | { |
11725 | { |
11104 | /* MOD_0F18_REG_2 */ |
11726 | /* MOD_0F18_REG_2 */ |
11105 | { "prefetcht1", { Mb } }, |
11727 | { "prefetcht1", { Mb }, 0 }, |
11106 | }, |
11728 | }, |
11107 | { |
11729 | { |
11108 | /* MOD_0F18_REG_3 */ |
11730 | /* MOD_0F18_REG_3 */ |
11109 | { "prefetcht2", { Mb } }, |
11731 | { "prefetcht2", { Mb }, 0 }, |
11110 | }, |
11732 | }, |
11111 | { |
11733 | { |
11112 | /* MOD_0F18_REG_4 */ |
11734 | /* MOD_0F18_REG_4 */ |
11113 | { "nop/reserved", { Mb } }, |
11735 | { "nop/reserved", { Mb }, 0 }, |
11114 | }, |
11736 | }, |
11115 | { |
11737 | { |
11116 | /* MOD_0F18_REG_5 */ |
11738 | /* MOD_0F18_REG_5 */ |
11117 | { "nop/reserved", { Mb } }, |
11739 | { "nop/reserved", { Mb }, 0 }, |
11118 | }, |
11740 | }, |
11119 | { |
11741 | { |
11120 | /* MOD_0F18_REG_6 */ |
11742 | /* MOD_0F18_REG_6 */ |
11121 | { "nop/reserved", { Mb } }, |
11743 | { "nop/reserved", { Mb }, 0 }, |
11122 | }, |
11744 | }, |
11123 | { |
11745 | { |
11124 | /* MOD_0F18_REG_7 */ |
11746 | /* MOD_0F18_REG_7 */ |
11125 | { "nop/reserved", { Mb } }, |
11747 | { "nop/reserved", { Mb }, 0 }, |
11126 | }, |
11748 | }, |
11127 | { |
11749 | { |
11128 | /* MOD_0F1A_PREFIX_0 */ |
11750 | /* MOD_0F1A_PREFIX_0 */ |
11129 | { "bndldx", { Gbnd, Ev_bnd } }, |
11751 | { "bndldx", { Gbnd, Ev_bnd }, 0 }, |
11130 | { "nopQ", { Ev } }, |
11752 | { "nopQ", { Ev }, 0 }, |
11131 | }, |
11753 | }, |
11132 | { |
11754 | { |
11133 | /* MOD_0F1B_PREFIX_0 */ |
11755 | /* MOD_0F1B_PREFIX_0 */ |
11134 | { "bndstx", { Ev_bnd, Gbnd } }, |
11756 | { "bndstx", { Ev_bnd, Gbnd }, 0 }, |
11135 | { "nopQ", { Ev } }, |
11757 | { "nopQ", { Ev }, 0 }, |
11136 | }, |
11758 | }, |
11137 | { |
11759 | { |
11138 | /* MOD_0F1B_PREFIX_1 */ |
11760 | /* MOD_0F1B_PREFIX_1 */ |
11139 | { "bndmk", { Gbnd, Ev_bnd } }, |
11761 | { "bndmk", { Gbnd, Ev_bnd }, 0 }, |
11140 | { "nopQ", { Ev } }, |
11762 | { "nopQ", { Ev }, 0 }, |
11141 | }, |
- | |
11142 | { |
- | |
11143 | /* MOD_0F20 */ |
- | |
11144 | { Bad_Opcode }, |
- | |
11145 | { "movZ", { Rm, Cm } }, |
- | |
11146 | }, |
- | |
11147 | { |
- | |
11148 | /* MOD_0F21 */ |
- | |
11149 | { Bad_Opcode }, |
- | |
11150 | { "movZ", { Rm, Dm } }, |
- | |
11151 | }, |
- | |
11152 | { |
- | |
11153 | /* MOD_0F22 */ |
- | |
11154 | { Bad_Opcode }, |
- | |
11155 | { "movZ", { Cm, Rm } }, |
- | |
11156 | }, |
- | |
11157 | { |
- | |
11158 | /* MOD_0F23 */ |
- | |
11159 | { Bad_Opcode }, |
- | |
11160 | { "movZ", { Dm, Rm } }, |
- | |
11161 | }, |
11763 | }, |
11162 | { |
11764 | { |
11163 | /* MOD_0F24 */ |
11765 | /* MOD_0F24 */ |
11164 | { Bad_Opcode }, |
11766 | { Bad_Opcode }, |
11165 | { "movL", { Rd, Td } }, |
11767 | { "movL", { Rd, Td }, 0 }, |
11166 | }, |
11768 | }, |
11167 | { |
11769 | { |
11168 | /* MOD_0F26 */ |
11770 | /* MOD_0F26 */ |
11169 | { Bad_Opcode }, |
11771 | { Bad_Opcode }, |
11170 | { "movL", { Td, Rd } }, |
11772 | { "movL", { Td, Rd }, 0 }, |
11171 | }, |
11773 | }, |
11172 | { |
11774 | { |
11173 | /* MOD_0F2B_PREFIX_0 */ |
11775 | /* MOD_0F2B_PREFIX_0 */ |
11174 | {"movntps", { Mx, XM } }, |
11776 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
11175 | }, |
11777 | }, |
11176 | { |
11778 | { |
11177 | /* MOD_0F2B_PREFIX_1 */ |
11779 | /* MOD_0F2B_PREFIX_1 */ |
11178 | {"movntss", { Md, XM } }, |
11780 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
11179 | }, |
11781 | }, |
11180 | { |
11782 | { |
11181 | /* MOD_0F2B_PREFIX_2 */ |
11783 | /* MOD_0F2B_PREFIX_2 */ |
11182 | {"movntpd", { Mx, XM } }, |
11784 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
11183 | }, |
11785 | }, |
11184 | { |
11786 | { |
11185 | /* MOD_0F2B_PREFIX_3 */ |
11787 | /* MOD_0F2B_PREFIX_3 */ |
11186 | {"movntsd", { Mq, XM } }, |
11788 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
11187 | }, |
11789 | }, |
11188 | { |
11790 | { |
11189 | /* MOD_0F51 */ |
11791 | /* MOD_0F51 */ |
11190 | { Bad_Opcode }, |
11792 | { Bad_Opcode }, |
11191 | { "movmskpX", { Gdq, XS } }, |
11793 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
11192 | }, |
11794 | }, |
11193 | { |
11795 | { |
11194 | /* MOD_0F71_REG_2 */ |
11796 | /* MOD_0F71_REG_2 */ |
11195 | { Bad_Opcode }, |
11797 | { Bad_Opcode }, |
11196 | { "psrlw", { MS, Ib } }, |
11798 | { "psrlw", { MS, Ib }, 0 }, |
11197 | }, |
11799 | }, |
11198 | { |
11800 | { |
11199 | /* MOD_0F71_REG_4 */ |
11801 | /* MOD_0F71_REG_4 */ |
11200 | { Bad_Opcode }, |
11802 | { Bad_Opcode }, |
11201 | { "psraw", { MS, Ib } }, |
11803 | { "psraw", { MS, Ib }, 0 }, |
11202 | }, |
11804 | }, |
11203 | { |
11805 | { |
11204 | /* MOD_0F71_REG_6 */ |
11806 | /* MOD_0F71_REG_6 */ |
11205 | { Bad_Opcode }, |
11807 | { Bad_Opcode }, |
11206 | { "psllw", { MS, Ib } }, |
11808 | { "psllw", { MS, Ib }, 0 }, |
11207 | }, |
11809 | }, |
11208 | { |
11810 | { |
11209 | /* MOD_0F72_REG_2 */ |
11811 | /* MOD_0F72_REG_2 */ |
11210 | { Bad_Opcode }, |
11812 | { Bad_Opcode }, |
11211 | { "psrld", { MS, Ib } }, |
11813 | { "psrld", { MS, Ib }, 0 }, |
11212 | }, |
11814 | }, |
11213 | { |
11815 | { |
11214 | /* MOD_0F72_REG_4 */ |
11816 | /* MOD_0F72_REG_4 */ |
11215 | { Bad_Opcode }, |
11817 | { Bad_Opcode }, |
11216 | { "psrad", { MS, Ib } }, |
11818 | { "psrad", { MS, Ib }, 0 }, |
11217 | }, |
11819 | }, |
11218 | { |
11820 | { |
11219 | /* MOD_0F72_REG_6 */ |
11821 | /* MOD_0F72_REG_6 */ |
11220 | { Bad_Opcode }, |
11822 | { Bad_Opcode }, |
11221 | { "pslld", { MS, Ib } }, |
11823 | { "pslld", { MS, Ib }, 0 }, |
11222 | }, |
11824 | }, |
11223 | { |
11825 | { |
11224 | /* MOD_0F73_REG_2 */ |
11826 | /* MOD_0F73_REG_2 */ |
11225 | { Bad_Opcode }, |
11827 | { Bad_Opcode }, |
11226 | { "psrlq", { MS, Ib } }, |
11828 | { "psrlq", { MS, Ib }, 0 }, |
11227 | }, |
11829 | }, |
11228 | { |
11830 | { |
11229 | /* MOD_0F73_REG_3 */ |
11831 | /* MOD_0F73_REG_3 */ |
11230 | { Bad_Opcode }, |
11832 | { Bad_Opcode }, |
11231 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11833 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11232 | }, |
11834 | }, |
11233 | { |
11835 | { |
11234 | /* MOD_0F73_REG_6 */ |
11836 | /* MOD_0F73_REG_6 */ |
11235 | { Bad_Opcode }, |
11837 | { Bad_Opcode }, |
11236 | { "psllq", { MS, Ib } }, |
11838 | { "psllq", { MS, Ib }, 0 }, |
11237 | }, |
11839 | }, |
11238 | { |
11840 | { |
11239 | /* MOD_0F73_REG_7 */ |
11841 | /* MOD_0F73_REG_7 */ |
11240 | { Bad_Opcode }, |
11842 | { Bad_Opcode }, |
11241 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11843 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11242 | }, |
11844 | }, |
11243 | { |
11845 | { |
11244 | /* MOD_0FAE_REG_0 */ |
11846 | /* MOD_0FAE_REG_0 */ |
11245 | { "fxsave", { FXSAVE } }, |
11847 | { "fxsave", { FXSAVE }, 0 }, |
11246 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
11848 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
11247 | }, |
11849 | }, |
11248 | { |
11850 | { |
11249 | /* MOD_0FAE_REG_1 */ |
11851 | /* MOD_0FAE_REG_1 */ |
11250 | { "fxrstor", { FXSAVE } }, |
11852 | { "fxrstor", { FXSAVE }, 0 }, |
11251 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
11853 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
11252 | }, |
11854 | }, |
11253 | { |
11855 | { |
11254 | /* MOD_0FAE_REG_2 */ |
11856 | /* MOD_0FAE_REG_2 */ |
11255 | { "ldmxcsr", { Md } }, |
11857 | { "ldmxcsr", { Md }, 0 }, |
11256 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
11858 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
11257 | }, |
11859 | }, |
11258 | { |
11860 | { |
11259 | /* MOD_0FAE_REG_3 */ |
11861 | /* MOD_0FAE_REG_3 */ |
11260 | { "stmxcsr", { Md } }, |
11862 | { "stmxcsr", { Md }, 0 }, |
11261 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
11863 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
11262 | }, |
11864 | }, |
11263 | { |
11865 | { |
11264 | /* MOD_0FAE_REG_4 */ |
11866 | /* MOD_0FAE_REG_4 */ |
11265 | { "xsave", { FXSAVE } }, |
11867 | { "xsave", { FXSAVE }, 0 }, |
11266 | }, |
11868 | }, |
11267 | { |
11869 | { |
11268 | /* MOD_0FAE_REG_5 */ |
11870 | /* MOD_0FAE_REG_5 */ |
11269 | { "xrstor", { FXSAVE } }, |
11871 | { "xrstor", { FXSAVE }, 0 }, |
11270 | { RM_TABLE (RM_0FAE_REG_5) }, |
11872 | { RM_TABLE (RM_0FAE_REG_5) }, |
11271 | }, |
11873 | }, |
11272 | { |
11874 | { |
11273 | /* MOD_0FAE_REG_6 */ |
11875 | /* MOD_0FAE_REG_6 */ |
11274 | { "xsaveopt", { FXSAVE } }, |
11876 | { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, |
11275 | { RM_TABLE (RM_0FAE_REG_6) }, |
11877 | { RM_TABLE (RM_0FAE_REG_6) }, |
11276 | }, |
11878 | }, |
11277 | { |
11879 | { |
11278 | /* MOD_0FAE_REG_7 */ |
11880 | /* MOD_0FAE_REG_7 */ |
11279 | { "clflush", { Mb } }, |
11881 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
11280 | { RM_TABLE (RM_0FAE_REG_7) }, |
11882 | { RM_TABLE (RM_0FAE_REG_7) }, |
11281 | }, |
11883 | }, |
11282 | { |
11884 | { |
11283 | /* MOD_0FB2 */ |
11885 | /* MOD_0FB2 */ |
11284 | { "lssS", { Gv, Mp } }, |
11886 | { "lssS", { Gv, Mp }, 0 }, |
11285 | }, |
11887 | }, |
11286 | { |
11888 | { |
11287 | /* MOD_0FB4 */ |
11889 | /* MOD_0FB4 */ |
11288 | { "lfsS", { Gv, Mp } }, |
11890 | { "lfsS", { Gv, Mp }, 0 }, |
11289 | }, |
11891 | }, |
11290 | { |
11892 | { |
11291 | /* MOD_0FB5 */ |
11893 | /* MOD_0FB5 */ |
11292 | { "lgsS", { Gv, Mp } }, |
11894 | { "lgsS", { Gv, Mp }, 0 }, |
- | 11895 | }, |
|
- | 11896 | { |
|
- | 11897 | /* MOD_0FC3 */ |
|
- | 11898 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, |
|
- | 11899 | }, |
|
- | 11900 | { |
|
- | 11901 | /* MOD_0FC7_REG_3 */ |
|
- | 11902 | { "xrstors", { FXSAVE }, 0 }, |
|
- | 11903 | }, |
|
- | 11904 | { |
|
- | 11905 | /* MOD_0FC7_REG_4 */ |
|
- | 11906 | { "xsavec", { FXSAVE }, 0 }, |
|
- | 11907 | }, |
|
- | 11908 | { |
|
- | 11909 | /* MOD_0FC7_REG_5 */ |
|
- | 11910 | { "xsaves", { FXSAVE }, 0 }, |
|
11293 | }, |
11911 | }, |
11294 | { |
11912 | { |
11295 | /* MOD_0FC7_REG_6 */ |
11913 | /* MOD_0FC7_REG_6 */ |
11296 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, |
11914 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11297 | { "rdrand", { Ev } }, |
11915 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } |
11298 | }, |
11916 | }, |
11299 | { |
11917 | { |
11300 | /* MOD_0FC7_REG_7 */ |
11918 | /* MOD_0FC7_REG_7 */ |
11301 | { "vmptrst", { Mq } }, |
11919 | { "vmptrst", { Mq }, 0 }, |
11302 | { "rdseed", { Ev } }, |
11920 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
11303 | }, |
11921 | }, |
11304 | { |
11922 | { |
11305 | /* MOD_0FD7 */ |
11923 | /* MOD_0FD7 */ |
11306 | { Bad_Opcode }, |
11924 | { Bad_Opcode }, |
11307 | { "pmovmskb", { Gdq, MS } }, |
11925 | { "pmovmskb", { Gdq, MS }, 0 }, |
11308 | }, |
11926 | }, |
11309 | { |
11927 | { |
11310 | /* MOD_0FE7_PREFIX_2 */ |
11928 | /* MOD_0FE7_PREFIX_2 */ |
11311 | { "movntdq", { Mx, XM } }, |
11929 | { "movntdq", { Mx, XM }, 0 }, |
11312 | }, |
11930 | }, |
11313 | { |
11931 | { |
11314 | /* MOD_0FF0_PREFIX_3 */ |
11932 | /* MOD_0FF0_PREFIX_3 */ |
11315 | { "lddqu", { XM, M } }, |
11933 | { "lddqu", { XM, M }, 0 }, |
11316 | }, |
11934 | }, |
11317 | { |
11935 | { |
11318 | /* MOD_0F382A_PREFIX_2 */ |
11936 | /* MOD_0F382A_PREFIX_2 */ |
11319 | { "movntdqa", { XM, Mx } }, |
11937 | { "movntdqa", { XM, Mx }, 0 }, |
11320 | }, |
11938 | }, |
11321 | { |
11939 | { |
11322 | /* MOD_62_32BIT */ |
11940 | /* MOD_62_32BIT */ |
11323 | { "bound{S|}", { Gv, Ma } }, |
11941 | { "bound{S|}", { Gv, Ma }, 0 }, |
11324 | { EVEX_TABLE (EVEX_0F) }, |
11942 | { EVEX_TABLE (EVEX_0F) }, |
11325 | }, |
11943 | }, |
11326 | { |
11944 | { |
11327 | /* MOD_C4_32BIT */ |
11945 | /* MOD_C4_32BIT */ |
11328 | { "lesS", { Gv, Mp } }, |
11946 | { "lesS", { Gv, Mp }, 0 }, |
11329 | { VEX_C4_TABLE (VEX_0F) }, |
11947 | { VEX_C4_TABLE (VEX_0F) }, |
11330 | }, |
11948 | }, |
11331 | { |
11949 | { |
11332 | /* MOD_C5_32BIT */ |
11950 | /* MOD_C5_32BIT */ |
11333 | { "ldsS", { Gv, Mp } }, |
11951 | { "ldsS", { Gv, Mp }, 0 }, |
11334 | { VEX_C5_TABLE (VEX_0F) }, |
11952 | { VEX_C5_TABLE (VEX_0F) }, |
11335 | }, |
11953 | }, |
11336 | { |
11954 | { |
11337 | /* MOD_VEX_0F12_PREFIX_0 */ |
11955 | /* MOD_VEX_0F12_PREFIX_0 */ |
11338 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, |
11956 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, |
11339 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, |
11957 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, |
11340 | }, |
11958 | }, |
11341 | { |
11959 | { |
11342 | /* MOD_VEX_0F13 */ |
11960 | /* MOD_VEX_0F13 */ |
11343 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, |
11961 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, |
11344 | }, |
11962 | }, |
11345 | { |
11963 | { |
11346 | /* MOD_VEX_0F16_PREFIX_0 */ |
11964 | /* MOD_VEX_0F16_PREFIX_0 */ |
11347 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, |
11965 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, |
11348 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, |
11966 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, |
11349 | }, |
11967 | }, |
11350 | { |
11968 | { |
11351 | /* MOD_VEX_0F17 */ |
11969 | /* MOD_VEX_0F17 */ |
11352 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, |
11970 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, |
11353 | }, |
11971 | }, |
11354 | { |
11972 | { |
11355 | /* MOD_VEX_0F2B */ |
11973 | /* MOD_VEX_0F2B */ |
11356 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, |
11974 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, |
11357 | }, |
11975 | }, |
11358 | { |
11976 | { |
- | 11977 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ |
|
- | 11978 | { Bad_Opcode }, |
|
- | 11979 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 11980 | }, |
|
- | 11981 | { |
|
- | 11982 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ |
|
- | 11983 | { Bad_Opcode }, |
|
- | 11984 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 11985 | }, |
|
- | 11986 | { |
|
- | 11987 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ |
|
- | 11988 | { Bad_Opcode }, |
|
- | 11989 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 11990 | }, |
|
- | 11991 | { |
|
- | 11992 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ |
|
- | 11993 | { Bad_Opcode }, |
|
- | 11994 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 11995 | }, |
|
- | 11996 | { |
|
- | 11997 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ |
|
- | 11998 | { Bad_Opcode }, |
|
- | 11999 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12000 | }, |
|
- | 12001 | { |
|
- | 12002 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ |
|
- | 12003 | { Bad_Opcode }, |
|
- | 12004 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12005 | }, |
|
- | 12006 | { |
|
- | 12007 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ |
|
- | 12008 | { Bad_Opcode }, |
|
- | 12009 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12010 | }, |
|
- | 12011 | { |
|
- | 12012 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ |
|
- | 12013 | { Bad_Opcode }, |
|
- | 12014 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12015 | }, |
|
- | 12016 | { |
|
- | 12017 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ |
|
- | 12018 | { Bad_Opcode }, |
|
- | 12019 | { "knotw", { MaskG, MaskR }, 0 }, |
|
- | 12020 | }, |
|
- | 12021 | { |
|
- | 12022 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ |
|
- | 12023 | { Bad_Opcode }, |
|
- | 12024 | { "knotq", { MaskG, MaskR }, 0 }, |
|
- | 12025 | }, |
|
- | 12026 | { |
|
- | 12027 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ |
|
- | 12028 | { Bad_Opcode }, |
|
- | 12029 | { "knotb", { MaskG, MaskR }, 0 }, |
|
- | 12030 | }, |
|
- | 12031 | { |
|
- | 12032 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ |
|
- | 12033 | { Bad_Opcode }, |
|
- | 12034 | { "knotd", { MaskG, MaskR }, 0 }, |
|
- | 12035 | }, |
|
- | 12036 | { |
|
- | 12037 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ |
|
- | 12038 | { Bad_Opcode }, |
|
- | 12039 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12040 | }, |
|
- | 12041 | { |
|
- | 12042 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ |
|
- | 12043 | { Bad_Opcode }, |
|
- | 12044 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12045 | }, |
|
- | 12046 | { |
|
- | 12047 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ |
|
- | 12048 | { Bad_Opcode }, |
|
- | 12049 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12050 | }, |
|
- | 12051 | { |
|
- | 12052 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ |
|
- | 12053 | { Bad_Opcode }, |
|
- | 12054 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12055 | }, |
|
- | 12056 | { |
|
- | 12057 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ |
|
- | 12058 | { Bad_Opcode }, |
|
- | 12059 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12060 | }, |
|
- | 12061 | { |
|
- | 12062 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ |
|
- | 12063 | { Bad_Opcode }, |
|
- | 12064 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12065 | }, |
|
- | 12066 | { |
|
- | 12067 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ |
|
- | 12068 | { Bad_Opcode }, |
|
- | 12069 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12070 | }, |
|
- | 12071 | { |
|
- | 12072 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ |
|
- | 12073 | { Bad_Opcode }, |
|
- | 12074 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12075 | }, |
|
- | 12076 | { |
|
- | 12077 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ |
|
- | 12078 | { Bad_Opcode }, |
|
- | 12079 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12080 | }, |
|
- | 12081 | { |
|
- | 12082 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ |
|
- | 12083 | { Bad_Opcode }, |
|
- | 12084 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12085 | }, |
|
- | 12086 | { |
|
- | 12087 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ |
|
- | 12088 | { Bad_Opcode }, |
|
- | 12089 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12090 | }, |
|
- | 12091 | { |
|
- | 12092 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ |
|
- | 12093 | { Bad_Opcode }, |
|
- | 12094 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12095 | }, |
|
- | 12096 | { |
|
- | 12097 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ |
|
- | 12098 | { Bad_Opcode }, |
|
- | 12099 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12100 | }, |
|
- | 12101 | { |
|
- | 12102 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ |
|
- | 12103 | { Bad_Opcode }, |
|
- | 12104 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12105 | }, |
|
- | 12106 | { |
|
- | 12107 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ |
|
- | 12108 | { Bad_Opcode }, |
|
- | 12109 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12110 | }, |
|
- | 12111 | { |
|
- | 12112 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ |
|
- | 12113 | { Bad_Opcode }, |
|
- | 12114 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12115 | }, |
|
- | 12116 | { |
|
- | 12117 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ |
|
- | 12118 | { Bad_Opcode }, |
|
- | 12119 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12120 | }, |
|
- | 12121 | { |
|
- | 12122 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ |
|
- | 12123 | { Bad_Opcode }, |
|
- | 12124 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12125 | }, |
|
- | 12126 | { |
|
- | 12127 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ |
|
- | 12128 | { Bad_Opcode }, |
|
- | 12129 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12130 | }, |
|
- | 12131 | { |
|
11359 | /* MOD_VEX_0F50 */ |
12132 | /* MOD_VEX_0F50 */ |
11360 | { Bad_Opcode }, |
12133 | { Bad_Opcode }, |
11361 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
12134 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
11362 | }, |
12135 | }, |
11363 | { |
12136 | { |
11364 | /* MOD_VEX_0F71_REG_2 */ |
12137 | /* MOD_VEX_0F71_REG_2 */ |
11365 | { Bad_Opcode }, |
12138 | { Bad_Opcode }, |
11366 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
12139 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
11367 | }, |
12140 | }, |
11368 | { |
12141 | { |
11369 | /* MOD_VEX_0F71_REG_4 */ |
12142 | /* MOD_VEX_0F71_REG_4 */ |
11370 | { Bad_Opcode }, |
12143 | { Bad_Opcode }, |
11371 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
12144 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
11372 | }, |
12145 | }, |
11373 | { |
12146 | { |
11374 | /* MOD_VEX_0F71_REG_6 */ |
12147 | /* MOD_VEX_0F71_REG_6 */ |
11375 | { Bad_Opcode }, |
12148 | { Bad_Opcode }, |
11376 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
12149 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
11377 | }, |
12150 | }, |
11378 | { |
12151 | { |
11379 | /* MOD_VEX_0F72_REG_2 */ |
12152 | /* MOD_VEX_0F72_REG_2 */ |
11380 | { Bad_Opcode }, |
12153 | { Bad_Opcode }, |
11381 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
12154 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
11382 | }, |
12155 | }, |
11383 | { |
12156 | { |
11384 | /* MOD_VEX_0F72_REG_4 */ |
12157 | /* MOD_VEX_0F72_REG_4 */ |
11385 | { Bad_Opcode }, |
12158 | { Bad_Opcode }, |
11386 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
12159 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
11387 | }, |
12160 | }, |
11388 | { |
12161 | { |
11389 | /* MOD_VEX_0F72_REG_6 */ |
12162 | /* MOD_VEX_0F72_REG_6 */ |
11390 | { Bad_Opcode }, |
12163 | { Bad_Opcode }, |
11391 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
12164 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
11392 | }, |
12165 | }, |
11393 | { |
12166 | { |
11394 | /* MOD_VEX_0F73_REG_2 */ |
12167 | /* MOD_VEX_0F73_REG_2 */ |
11395 | { Bad_Opcode }, |
12168 | { Bad_Opcode }, |
11396 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
12169 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
11397 | }, |
12170 | }, |
11398 | { |
12171 | { |
11399 | /* MOD_VEX_0F73_REG_3 */ |
12172 | /* MOD_VEX_0F73_REG_3 */ |
11400 | { Bad_Opcode }, |
12173 | { Bad_Opcode }, |
11401 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
12174 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
11402 | }, |
12175 | }, |
11403 | { |
12176 | { |
11404 | /* MOD_VEX_0F73_REG_6 */ |
12177 | /* MOD_VEX_0F73_REG_6 */ |
11405 | { Bad_Opcode }, |
12178 | { Bad_Opcode }, |
11406 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
12179 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
11407 | }, |
12180 | }, |
11408 | { |
12181 | { |
11409 | /* MOD_VEX_0F73_REG_7 */ |
12182 | /* MOD_VEX_0F73_REG_7 */ |
11410 | { Bad_Opcode }, |
12183 | { Bad_Opcode }, |
11411 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
12184 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
11412 | }, |
12185 | }, |
11413 | { |
12186 | { |
- | 12187 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ |
|
- | 12188 | { "kmovw", { Ew, MaskG }, 0 }, |
|
- | 12189 | { Bad_Opcode }, |
|
- | 12190 | }, |
|
- | 12191 | { |
|
- | 12192 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ |
|
- | 12193 | { "kmovq", { Eq, MaskG }, 0 }, |
|
- | 12194 | { Bad_Opcode }, |
|
- | 12195 | }, |
|
- | 12196 | { |
|
- | 12197 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ |
|
- | 12198 | { "kmovb", { Eb, MaskG }, 0 }, |
|
- | 12199 | { Bad_Opcode }, |
|
- | 12200 | }, |
|
- | 12201 | { |
|
- | 12202 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ |
|
- | 12203 | { "kmovd", { Ed, MaskG }, 0 }, |
|
- | 12204 | { Bad_Opcode }, |
|
- | 12205 | }, |
|
- | 12206 | { |
|
- | 12207 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ |
|
- | 12208 | { Bad_Opcode }, |
|
- | 12209 | { "kmovw", { MaskG, Rdq }, 0 }, |
|
- | 12210 | }, |
|
- | 12211 | { |
|
- | 12212 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ |
|
- | 12213 | { Bad_Opcode }, |
|
- | 12214 | { "kmovb", { MaskG, Rdq }, 0 }, |
|
- | 12215 | }, |
|
- | 12216 | { |
|
- | 12217 | /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ |
|
- | 12218 | { Bad_Opcode }, |
|
- | 12219 | { "kmovd", { MaskG, Rdq }, 0 }, |
|
- | 12220 | }, |
|
- | 12221 | { |
|
- | 12222 | /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ |
|
- | 12223 | { Bad_Opcode }, |
|
- | 12224 | { "kmovq", { MaskG, Rdq }, 0 }, |
|
- | 12225 | }, |
|
- | 12226 | { |
|
- | 12227 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ |
|
- | 12228 | { Bad_Opcode }, |
|
- | 12229 | { "kmovw", { Gdq, MaskR }, 0 }, |
|
- | 12230 | }, |
|
- | 12231 | { |
|
- | 12232 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ |
|
- | 12233 | { Bad_Opcode }, |
|
- | 12234 | { "kmovb", { Gdq, MaskR }, 0 }, |
|
- | 12235 | }, |
|
- | 12236 | { |
|
- | 12237 | /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ |
|
- | 12238 | { Bad_Opcode }, |
|
- | 12239 | { "kmovd", { Gdq, MaskR }, 0 }, |
|
- | 12240 | }, |
|
- | 12241 | { |
|
- | 12242 | /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ |
|
- | 12243 | { Bad_Opcode }, |
|
- | 12244 | { "kmovq", { Gdq, MaskR }, 0 }, |
|
- | 12245 | }, |
|
- | 12246 | { |
|
- | 12247 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ |
|
- | 12248 | { Bad_Opcode }, |
|
- | 12249 | { "kortestw", { MaskG, MaskR }, 0 }, |
|
- | 12250 | }, |
|
- | 12251 | { |
|
- | 12252 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ |
|
- | 12253 | { Bad_Opcode }, |
|
- | 12254 | { "kortestq", { MaskG, MaskR }, 0 }, |
|
- | 12255 | }, |
|
- | 12256 | { |
|
- | 12257 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ |
|
- | 12258 | { Bad_Opcode }, |
|
- | 12259 | { "kortestb", { MaskG, MaskR }, 0 }, |
|
- | 12260 | }, |
|
- | 12261 | { |
|
- | 12262 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ |
|
- | 12263 | { Bad_Opcode }, |
|
- | 12264 | { "kortestd", { MaskG, MaskR }, 0 }, |
|
- | 12265 | }, |
|
- | 12266 | { |
|
- | 12267 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ |
|
- | 12268 | { Bad_Opcode }, |
|
- | 12269 | { "ktestw", { MaskG, MaskR }, 0 }, |
|
- | 12270 | }, |
|
- | 12271 | { |
|
- | 12272 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ |
|
- | 12273 | { Bad_Opcode }, |
|
- | 12274 | { "ktestq", { MaskG, MaskR }, 0 }, |
|
- | 12275 | }, |
|
- | 12276 | { |
|
- | 12277 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ |
|
- | 12278 | { Bad_Opcode }, |
|
- | 12279 | { "ktestb", { MaskG, MaskR }, 0 }, |
|
- | 12280 | }, |
|
- | 12281 | { |
|
- | 12282 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ |
|
- | 12283 | { Bad_Opcode }, |
|
- | 12284 | { "ktestd", { MaskG, MaskR }, 0 }, |
|
- | 12285 | }, |
|
- | 12286 | { |
|
11414 | /* MOD_VEX_0FAE_REG_2 */ |
12287 | /* MOD_VEX_0FAE_REG_2 */ |
11415 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, |
12288 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, |
11416 | }, |
12289 | }, |
11417 | { |
12290 | { |
11418 | /* MOD_VEX_0FAE_REG_3 */ |
12291 | /* MOD_VEX_0FAE_REG_3 */ |
11419 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, |
12292 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, |
11420 | }, |
12293 | }, |
11421 | { |
12294 | { |
11422 | /* MOD_VEX_0FD7_PREFIX_2 */ |
12295 | /* MOD_VEX_0FD7_PREFIX_2 */ |
11423 | { Bad_Opcode }, |
12296 | { Bad_Opcode }, |
11424 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
12297 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
11425 | }, |
12298 | }, |
11426 | { |
12299 | { |
11427 | /* MOD_VEX_0FE7_PREFIX_2 */ |
12300 | /* MOD_VEX_0FE7_PREFIX_2 */ |
11428 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, |
12301 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, |
11429 | }, |
12302 | }, |
11430 | { |
12303 | { |
11431 | /* MOD_VEX_0FF0_PREFIX_3 */ |
12304 | /* MOD_VEX_0FF0_PREFIX_3 */ |
11432 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, |
12305 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, |
11433 | }, |
12306 | }, |
11434 | { |
12307 | { |
11435 | /* MOD_VEX_0F381A_PREFIX_2 */ |
12308 | /* MOD_VEX_0F381A_PREFIX_2 */ |
11436 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, |
12309 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, |
11437 | }, |
12310 | }, |
11438 | { |
12311 | { |
11439 | /* MOD_VEX_0F382A_PREFIX_2 */ |
12312 | /* MOD_VEX_0F382A_PREFIX_2 */ |
11440 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
12313 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
11441 | }, |
12314 | }, |
11442 | { |
12315 | { |
11443 | /* MOD_VEX_0F382C_PREFIX_2 */ |
12316 | /* MOD_VEX_0F382C_PREFIX_2 */ |
11444 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, |
12317 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, |
11445 | }, |
12318 | }, |
11446 | { |
12319 | { |
11447 | /* MOD_VEX_0F382D_PREFIX_2 */ |
12320 | /* MOD_VEX_0F382D_PREFIX_2 */ |
11448 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, |
12321 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, |
11449 | }, |
12322 | }, |
11450 | { |
12323 | { |
11451 | /* MOD_VEX_0F382E_PREFIX_2 */ |
12324 | /* MOD_VEX_0F382E_PREFIX_2 */ |
11452 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, |
12325 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, |
11453 | }, |
12326 | }, |
11454 | { |
12327 | { |
11455 | /* MOD_VEX_0F382F_PREFIX_2 */ |
12328 | /* MOD_VEX_0F382F_PREFIX_2 */ |
11456 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, |
12329 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, |
11457 | }, |
12330 | }, |
11458 | { |
12331 | { |
11459 | /* MOD_VEX_0F385A_PREFIX_2 */ |
12332 | /* MOD_VEX_0F385A_PREFIX_2 */ |
11460 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, |
12333 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, |
11461 | }, |
12334 | }, |
11462 | { |
12335 | { |
11463 | /* MOD_VEX_0F388C_PREFIX_2 */ |
12336 | /* MOD_VEX_0F388C_PREFIX_2 */ |
11464 | { "vpmaskmov%LW", { XM, Vex, Mx } }, |
12337 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
11465 | }, |
12338 | }, |
11466 | { |
12339 | { |
11467 | /* MOD_VEX_0F388E_PREFIX_2 */ |
12340 | /* MOD_VEX_0F388E_PREFIX_2 */ |
11468 | { "vpmaskmov%LW", { Mx, Vex, XM } }, |
12341 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
- | 12342 | }, |
|
- | 12343 | { |
|
- | 12344 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ |
|
- | 12345 | { Bad_Opcode }, |
|
- | 12346 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12347 | }, |
|
- | 12348 | { |
|
- | 12349 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ |
|
- | 12350 | { Bad_Opcode }, |
|
- | 12351 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12352 | }, |
|
- | 12353 | { |
|
- | 12354 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ |
|
- | 12355 | { Bad_Opcode }, |
|
- | 12356 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12357 | }, |
|
- | 12358 | { |
|
- | 12359 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ |
|
- | 12360 | { Bad_Opcode }, |
|
- | 12361 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12362 | }, |
|
- | 12363 | { |
|
- | 12364 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ |
|
- | 12365 | { Bad_Opcode }, |
|
- | 12366 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12367 | }, |
|
- | 12368 | { |
|
- | 12369 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ |
|
- | 12370 | { Bad_Opcode }, |
|
- | 12371 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12372 | }, |
|
- | 12373 | { |
|
- | 12374 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ |
|
- | 12375 | { Bad_Opcode }, |
|
- | 12376 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12377 | }, |
|
- | 12378 | { |
|
- | 12379 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ |
|
- | 12380 | { Bad_Opcode }, |
|
- | 12381 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, |
|
11469 | }, |
12382 | }, |
11470 | #define NEED_MOD_TABLE |
12383 | #define NEED_MOD_TABLE |
11471 | #include "i386-dis-evex.h" |
12384 | #include "i386-dis-evex.h" |
11472 | #undef NEED_MOD_TABLE |
12385 | #undef NEED_MOD_TABLE |
11473 | }; |
12386 | }; |
11474 | 12387 | ||
11475 | static const struct dis386 rm_table[][8] = { |
12388 | static const struct dis386 rm_table[][8] = { |
11476 | { |
12389 | { |
11477 | /* RM_C6_REG_7 */ |
12390 | /* RM_C6_REG_7 */ |
11478 | { "xabort", { Skip_MODRM, Ib } }, |
12391 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
11479 | }, |
12392 | }, |
11480 | { |
12393 | { |
11481 | /* RM_C7_REG_7 */ |
12394 | /* RM_C7_REG_7 */ |
11482 | { "xbeginT", { Skip_MODRM, Jv } }, |
12395 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
11483 | }, |
12396 | }, |
11484 | { |
12397 | { |
11485 | /* RM_0F01_REG_0 */ |
12398 | /* RM_0F01_REG_0 */ |
11486 | { Bad_Opcode }, |
12399 | { Bad_Opcode }, |
11487 | { "vmcall", { Skip_MODRM } }, |
12400 | { "vmcall", { Skip_MODRM }, 0 }, |
11488 | { "vmlaunch", { Skip_MODRM } }, |
12401 | { "vmlaunch", { Skip_MODRM }, 0 }, |
11489 | { "vmresume", { Skip_MODRM } }, |
12402 | { "vmresume", { Skip_MODRM }, 0 }, |
11490 | { "vmxoff", { Skip_MODRM } }, |
12403 | { "vmxoff", { Skip_MODRM }, 0 }, |
11491 | }, |
12404 | }, |
11492 | { |
12405 | { |
11493 | /* RM_0F01_REG_1 */ |
12406 | /* RM_0F01_REG_1 */ |
11494 | { "monitor", { { OP_Monitor, 0 } } }, |
12407 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
11495 | { "mwait", { { OP_Mwait, 0 } } }, |
12408 | { "mwait", { { OP_Mwait, 0 } }, 0 }, |
11496 | { "clac", { Skip_MODRM } }, |
12409 | { "clac", { Skip_MODRM }, 0 }, |
11497 | { "stac", { Skip_MODRM } }, |
12410 | { "stac", { Skip_MODRM }, 0 }, |
- | 12411 | { Bad_Opcode }, |
|
- | 12412 | { Bad_Opcode }, |
|
- | 12413 | { Bad_Opcode }, |
|
- | 12414 | { "encls", { Skip_MODRM }, 0 }, |
|
11498 | }, |
12415 | }, |
11499 | { |
12416 | { |
11500 | /* RM_0F01_REG_2 */ |
12417 | /* RM_0F01_REG_2 */ |
11501 | { "xgetbv", { Skip_MODRM } }, |
12418 | { "xgetbv", { Skip_MODRM }, 0 }, |
11502 | { "xsetbv", { Skip_MODRM } }, |
12419 | { "xsetbv", { Skip_MODRM }, 0 }, |
11503 | { Bad_Opcode }, |
12420 | { Bad_Opcode }, |
11504 | { Bad_Opcode }, |
12421 | { Bad_Opcode }, |
11505 | { "vmfunc", { Skip_MODRM } }, |
12422 | { "vmfunc", { Skip_MODRM }, 0 }, |
11506 | { "xend", { Skip_MODRM } }, |
12423 | { "xend", { Skip_MODRM }, 0 }, |
11507 | { "xtest", { Skip_MODRM } }, |
12424 | { "xtest", { Skip_MODRM }, 0 }, |
11508 | { Bad_Opcode }, |
12425 | { "enclu", { Skip_MODRM }, 0 }, |
11509 | }, |
12426 | }, |
11510 | { |
12427 | { |
11511 | /* RM_0F01_REG_3 */ |
12428 | /* RM_0F01_REG_3 */ |
11512 | { "vmrun", { Skip_MODRM } }, |
12429 | { "vmrun", { Skip_MODRM }, 0 }, |
11513 | { "vmmcall", { Skip_MODRM } }, |
12430 | { "vmmcall", { Skip_MODRM }, 0 }, |
11514 | { "vmload", { Skip_MODRM } }, |
12431 | { "vmload", { Skip_MODRM }, 0 }, |
11515 | { "vmsave", { Skip_MODRM } }, |
12432 | { "vmsave", { Skip_MODRM }, 0 }, |
11516 | { "stgi", { Skip_MODRM } }, |
12433 | { "stgi", { Skip_MODRM }, 0 }, |
11517 | { "clgi", { Skip_MODRM } }, |
12434 | { "clgi", { Skip_MODRM }, 0 }, |
11518 | { "skinit", { Skip_MODRM } }, |
12435 | { "skinit", { Skip_MODRM }, 0 }, |
11519 | { "invlpga", { Skip_MODRM } }, |
12436 | { "invlpga", { Skip_MODRM }, 0 }, |
- | 12437 | }, |
|
- | 12438 | { |
|
- | 12439 | /* RM_0F01_REG_5 */ |
|
- | 12440 | { Bad_Opcode }, |
|
- | 12441 | { Bad_Opcode }, |
|
- | 12442 | { Bad_Opcode }, |
|
- | 12443 | { Bad_Opcode }, |
|
- | 12444 | { Bad_Opcode }, |
|
- | 12445 | { Bad_Opcode }, |
|
- | 12446 | { "rdpkru", { Skip_MODRM }, 0 }, |
|
- | 12447 | { "wrpkru", { Skip_MODRM }, 0 }, |
|
11520 | }, |
12448 | }, |
11521 | { |
12449 | { |
11522 | /* RM_0F01_REG_7 */ |
12450 | /* RM_0F01_REG_7 */ |
11523 | { "swapgs", { Skip_MODRM } }, |
12451 | { "swapgs", { Skip_MODRM }, 0 }, |
11524 | { "rdtscp", { Skip_MODRM } }, |
12452 | { "rdtscp", { Skip_MODRM }, 0 }, |
- | 12453 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
|
- | 12454 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, |
|
- | 12455 | { "clzero", { Skip_MODRM }, 0 }, |
|
11525 | }, |
12456 | }, |
11526 | { |
12457 | { |
11527 | /* RM_0FAE_REG_5 */ |
12458 | /* RM_0FAE_REG_5 */ |
11528 | { "lfence", { Skip_MODRM } }, |
12459 | { "lfence", { Skip_MODRM }, 0 }, |
11529 | }, |
12460 | }, |
11530 | { |
12461 | { |
11531 | /* RM_0FAE_REG_6 */ |
12462 | /* RM_0FAE_REG_6 */ |
11532 | { "mfence", { Skip_MODRM } }, |
12463 | { "mfence", { Skip_MODRM }, 0 }, |
11533 | }, |
12464 | }, |
11534 | { |
12465 | { |
11535 | /* RM_0FAE_REG_7 */ |
12466 | /* RM_0FAE_REG_7 */ |
11536 | { "sfence", { Skip_MODRM } }, |
12467 | { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) }, |
11537 | }, |
12468 | }, |
11538 | }; |
12469 | }; |
11539 | 12470 | ||
11540 | #define INTERNAL_DISASSEMBLER_ERROR _(" |
12471 | #define INTERNAL_DISASSEMBLER_ERROR _(" |
11541 | 12472 | ||
11542 | /* We use the high bit to indicate different name for the same |
12473 | /* We use the high bit to indicate different name for the same |
11543 | prefix. */ |
12474 | prefix. */ |
11544 | #define ADDR16_PREFIX (0x67 | 0x100) |
- | |
11545 | #define ADDR32_PREFIX (0x67 | 0x200) |
- | |
11546 | #define DATA16_PREFIX (0x66 | 0x100) |
- | |
11547 | #define DATA32_PREFIX (0x66 | 0x200) |
- | |
11548 | #define REP_PREFIX (0xf3 | 0x100) |
12475 | #define REP_PREFIX (0xf3 | 0x100) |
11549 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
12476 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11550 | #define XRELEASE_PREFIX (0xf3 | 0x400) |
12477 | #define XRELEASE_PREFIX (0xf3 | 0x400) |
11551 | #define BND_PREFIX (0xf2 | 0x400) |
12478 | #define BND_PREFIX (0xf2 | 0x400) |
11552 | 12479 | ||
11553 | static int |
12480 | static int |
11554 | ckprefix (void) |
12481 | ckprefix (void) |
11555 | { |
12482 | { |
11556 | int newrex, i, length; |
12483 | int newrex, i, length; |
11557 | rex = 0; |
12484 | rex = 0; |
11558 | rex_ignored = 0; |
12485 | rex_ignored = 0; |
11559 | prefixes = 0; |
12486 | prefixes = 0; |
11560 | used_prefixes = 0; |
12487 | used_prefixes = 0; |
11561 | rex_used = 0; |
12488 | rex_used = 0; |
11562 | last_lock_prefix = -1; |
12489 | last_lock_prefix = -1; |
11563 | last_repz_prefix = -1; |
12490 | last_repz_prefix = -1; |
11564 | last_repnz_prefix = -1; |
12491 | last_repnz_prefix = -1; |
11565 | last_data_prefix = -1; |
12492 | last_data_prefix = -1; |
11566 | last_addr_prefix = -1; |
12493 | last_addr_prefix = -1; |
11567 | last_rex_prefix = -1; |
12494 | last_rex_prefix = -1; |
11568 | last_seg_prefix = -1; |
12495 | last_seg_prefix = -1; |
- | 12496 | fwait_prefix = -1; |
|
- | 12497 | active_seg_prefix = 0; |
|
11569 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12498 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11570 | all_prefixes[i] = 0; |
12499 | all_prefixes[i] = 0; |
11571 | i = 0; |
12500 | i = 0; |
11572 | length = 0; |
12501 | length = 0; |
11573 | /* The maximum instruction length is 15bytes. */ |
12502 | /* The maximum instruction length is 15bytes. */ |
11574 | while (length < MAX_CODE_LENGTH - 1) |
12503 | while (length < MAX_CODE_LENGTH - 1) |
11575 | { |
12504 | { |
11576 | FETCH_DATA (the_info, codep + 1); |
12505 | FETCH_DATA (the_info, codep + 1); |
11577 | newrex = 0; |
12506 | newrex = 0; |
11578 | switch (*codep) |
12507 | switch (*codep) |
11579 | { |
12508 | { |
11580 | /* REX prefixes family. */ |
12509 | /* REX prefixes family. */ |
11581 | case 0x40: |
12510 | case 0x40: |
11582 | case 0x41: |
12511 | case 0x41: |
11583 | case 0x42: |
12512 | case 0x42: |
11584 | case 0x43: |
12513 | case 0x43: |
11585 | case 0x44: |
12514 | case 0x44: |
11586 | case 0x45: |
12515 | case 0x45: |
11587 | case 0x46: |
12516 | case 0x46: |
11588 | case 0x47: |
12517 | case 0x47: |
11589 | case 0x48: |
12518 | case 0x48: |
11590 | case 0x49: |
12519 | case 0x49: |
11591 | case 0x4a: |
12520 | case 0x4a: |
11592 | case 0x4b: |
12521 | case 0x4b: |
11593 | case 0x4c: |
12522 | case 0x4c: |
11594 | case 0x4d: |
12523 | case 0x4d: |
11595 | case 0x4e: |
12524 | case 0x4e: |
11596 | case 0x4f: |
12525 | case 0x4f: |
11597 | if (address_mode == mode_64bit) |
12526 | if (address_mode == mode_64bit) |
11598 | newrex = *codep; |
12527 | newrex = *codep; |
11599 | else |
12528 | else |
11600 | return 1; |
12529 | return 1; |
11601 | last_rex_prefix = i; |
12530 | last_rex_prefix = i; |
11602 | break; |
12531 | break; |
11603 | case 0xf3: |
12532 | case 0xf3: |
11604 | prefixes |= PREFIX_REPZ; |
12533 | prefixes |= PREFIX_REPZ; |
11605 | last_repz_prefix = i; |
12534 | last_repz_prefix = i; |
11606 | break; |
12535 | break; |
11607 | case 0xf2: |
12536 | case 0xf2: |
11608 | prefixes |= PREFIX_REPNZ; |
12537 | prefixes |= PREFIX_REPNZ; |
11609 | last_repnz_prefix = i; |
12538 | last_repnz_prefix = i; |
11610 | break; |
12539 | break; |
11611 | case 0xf0: |
12540 | case 0xf0: |
11612 | prefixes |= PREFIX_LOCK; |
12541 | prefixes |= PREFIX_LOCK; |
11613 | last_lock_prefix = i; |
12542 | last_lock_prefix = i; |
11614 | break; |
12543 | break; |
11615 | case 0x2e: |
12544 | case 0x2e: |
11616 | prefixes |= PREFIX_CS; |
12545 | prefixes |= PREFIX_CS; |
11617 | last_seg_prefix = i; |
12546 | last_seg_prefix = i; |
- | 12547 | active_seg_prefix = PREFIX_CS; |
|
11618 | break; |
12548 | break; |
11619 | case 0x36: |
12549 | case 0x36: |
11620 | prefixes |= PREFIX_SS; |
12550 | prefixes |= PREFIX_SS; |
11621 | last_seg_prefix = i; |
12551 | last_seg_prefix = i; |
- | 12552 | active_seg_prefix = PREFIX_SS; |
|
11622 | break; |
12553 | break; |
11623 | case 0x3e: |
12554 | case 0x3e: |
11624 | prefixes |= PREFIX_DS; |
12555 | prefixes |= PREFIX_DS; |
11625 | last_seg_prefix = i; |
12556 | last_seg_prefix = i; |
- | 12557 | active_seg_prefix = PREFIX_DS; |
|
11626 | break; |
12558 | break; |
11627 | case 0x26: |
12559 | case 0x26: |
11628 | prefixes |= PREFIX_ES; |
12560 | prefixes |= PREFIX_ES; |
11629 | last_seg_prefix = i; |
12561 | last_seg_prefix = i; |
- | 12562 | active_seg_prefix = PREFIX_ES; |
|
11630 | break; |
12563 | break; |
11631 | case 0x64: |
12564 | case 0x64: |
11632 | prefixes |= PREFIX_FS; |
12565 | prefixes |= PREFIX_FS; |
11633 | last_seg_prefix = i; |
12566 | last_seg_prefix = i; |
- | 12567 | active_seg_prefix = PREFIX_FS; |
|
11634 | break; |
12568 | break; |
11635 | case 0x65: |
12569 | case 0x65: |
11636 | prefixes |= PREFIX_GS; |
12570 | prefixes |= PREFIX_GS; |
11637 | last_seg_prefix = i; |
12571 | last_seg_prefix = i; |
- | 12572 | active_seg_prefix = PREFIX_GS; |
|
11638 | break; |
12573 | break; |
11639 | case 0x66: |
12574 | case 0x66: |
11640 | prefixes |= PREFIX_DATA; |
12575 | prefixes |= PREFIX_DATA; |
11641 | last_data_prefix = i; |
12576 | last_data_prefix = i; |
11642 | break; |
12577 | break; |
11643 | case 0x67: |
12578 | case 0x67: |
11644 | prefixes |= PREFIX_ADDR; |
12579 | prefixes |= PREFIX_ADDR; |
11645 | last_addr_prefix = i; |
12580 | last_addr_prefix = i; |
11646 | break; |
12581 | break; |
11647 | case FWAIT_OPCODE: |
12582 | case FWAIT_OPCODE: |
11648 | /* fwait is really an instruction. If there are prefixes |
12583 | /* fwait is really an instruction. If there are prefixes |
11649 | before the fwait, they belong to the fwait, *not* to the |
12584 | before the fwait, they belong to the fwait, *not* to the |
11650 | following instruction. */ |
12585 | following instruction. */ |
- | 12586 | fwait_prefix = i; |
|
11651 | if (prefixes || rex) |
12587 | if (prefixes || rex) |
11652 | { |
12588 | { |
11653 | prefixes |= PREFIX_FWAIT; |
12589 | prefixes |= PREFIX_FWAIT; |
11654 | codep++; |
12590 | codep++; |
11655 | /* This ensures that the previous REX prefixes are noticed |
12591 | /* This ensures that the previous REX prefixes are noticed |
11656 | as unused prefixes, as in the return case below. */ |
12592 | as unused prefixes, as in the return case below. */ |
11657 | rex_used = rex; |
12593 | rex_used = rex; |
11658 | return 1; |
12594 | return 1; |
11659 | } |
12595 | } |
11660 | prefixes = PREFIX_FWAIT; |
12596 | prefixes = PREFIX_FWAIT; |
11661 | break; |
12597 | break; |
11662 | default: |
12598 | default: |
11663 | return 1; |
12599 | return 1; |
11664 | } |
12600 | } |
11665 | /* Rex is ignored when followed by another prefix. */ |
12601 | /* Rex is ignored when followed by another prefix. */ |
11666 | if (rex) |
12602 | if (rex) |
11667 | { |
12603 | { |
11668 | rex_used = rex; |
12604 | rex_used = rex; |
11669 | return 1; |
12605 | return 1; |
11670 | } |
12606 | } |
11671 | if (*codep != FWAIT_OPCODE) |
12607 | if (*codep != FWAIT_OPCODE) |
11672 | all_prefixes[i++] = *codep; |
12608 | all_prefixes[i++] = *codep; |
11673 | rex = newrex; |
12609 | rex = newrex; |
11674 | codep++; |
12610 | codep++; |
11675 | length++; |
12611 | length++; |
11676 | } |
12612 | } |
11677 | return 0; |
12613 | return 0; |
11678 | } |
12614 | } |
11679 | - | ||
11680 | static int |
- | |
11681 | seg_prefix (int pref) |
- | |
11682 | { |
- | |
11683 | switch (pref) |
- | |
11684 | { |
- | |
11685 | case 0x2e: |
- | |
11686 | return PREFIX_CS; |
- | |
11687 | case 0x36: |
- | |
11688 | return PREFIX_SS; |
- | |
11689 | case 0x3e: |
- | |
11690 | return PREFIX_DS; |
- | |
11691 | case 0x26: |
- | |
11692 | return PREFIX_ES; |
- | |
11693 | case 0x64: |
- | |
11694 | return PREFIX_FS; |
- | |
11695 | case 0x65: |
- | |
11696 | return PREFIX_GS; |
- | |
11697 | default: |
- | |
11698 | return 0; |
- | |
11699 | } |
- | |
11700 | } |
- | |
11701 | 12615 | ||
11702 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12616 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11703 | prefix byte. */ |
12617 | prefix byte. */ |
11704 | 12618 | ||
11705 | static const char * |
12619 | static const char * |
11706 | prefix_name (int pref, int sizeflag) |
12620 | prefix_name (int pref, int sizeflag) |
11707 | { |
12621 | { |
11708 | static const char *rexes [16] = |
12622 | static const char *rexes [16] = |
11709 | { |
12623 | { |
11710 | "rex", /* 0x40 */ |
12624 | "rex", /* 0x40 */ |
11711 | "rex.B", /* 0x41 */ |
12625 | "rex.B", /* 0x41 */ |
11712 | "rex.X", /* 0x42 */ |
12626 | "rex.X", /* 0x42 */ |
11713 | "rex.XB", /* 0x43 */ |
12627 | "rex.XB", /* 0x43 */ |
11714 | "rex.R", /* 0x44 */ |
12628 | "rex.R", /* 0x44 */ |
11715 | "rex.RB", /* 0x45 */ |
12629 | "rex.RB", /* 0x45 */ |
11716 | "rex.RX", /* 0x46 */ |
12630 | "rex.RX", /* 0x46 */ |
11717 | "rex.RXB", /* 0x47 */ |
12631 | "rex.RXB", /* 0x47 */ |
11718 | "rex.W", /* 0x48 */ |
12632 | "rex.W", /* 0x48 */ |
11719 | "rex.WB", /* 0x49 */ |
12633 | "rex.WB", /* 0x49 */ |
11720 | "rex.WX", /* 0x4a */ |
12634 | "rex.WX", /* 0x4a */ |
11721 | "rex.WXB", /* 0x4b */ |
12635 | "rex.WXB", /* 0x4b */ |
11722 | "rex.WR", /* 0x4c */ |
12636 | "rex.WR", /* 0x4c */ |
11723 | "rex.WRB", /* 0x4d */ |
12637 | "rex.WRB", /* 0x4d */ |
11724 | "rex.WRX", /* 0x4e */ |
12638 | "rex.WRX", /* 0x4e */ |
11725 | "rex.WRXB", /* 0x4f */ |
12639 | "rex.WRXB", /* 0x4f */ |
11726 | }; |
12640 | }; |
11727 | 12641 | ||
11728 | switch (pref) |
12642 | switch (pref) |
11729 | { |
12643 | { |
11730 | /* REX prefixes family. */ |
12644 | /* REX prefixes family. */ |
11731 | case 0x40: |
12645 | case 0x40: |
11732 | case 0x41: |
12646 | case 0x41: |
11733 | case 0x42: |
12647 | case 0x42: |
11734 | case 0x43: |
12648 | case 0x43: |
11735 | case 0x44: |
12649 | case 0x44: |
11736 | case 0x45: |
12650 | case 0x45: |
11737 | case 0x46: |
12651 | case 0x46: |
11738 | case 0x47: |
12652 | case 0x47: |
11739 | case 0x48: |
12653 | case 0x48: |
11740 | case 0x49: |
12654 | case 0x49: |
11741 | case 0x4a: |
12655 | case 0x4a: |
11742 | case 0x4b: |
12656 | case 0x4b: |
11743 | case 0x4c: |
12657 | case 0x4c: |
11744 | case 0x4d: |
12658 | case 0x4d: |
11745 | case 0x4e: |
12659 | case 0x4e: |
11746 | case 0x4f: |
12660 | case 0x4f: |
11747 | return rexes [pref - 0x40]; |
12661 | return rexes [pref - 0x40]; |
11748 | case 0xf3: |
12662 | case 0xf3: |
11749 | return "repz"; |
12663 | return "repz"; |
11750 | case 0xf2: |
12664 | case 0xf2: |
11751 | return "repnz"; |
12665 | return "repnz"; |
11752 | case 0xf0: |
12666 | case 0xf0: |
11753 | return "lock"; |
12667 | return "lock"; |
11754 | case 0x2e: |
12668 | case 0x2e: |
11755 | return "cs"; |
12669 | return "cs"; |
11756 | case 0x36: |
12670 | case 0x36: |
11757 | return "ss"; |
12671 | return "ss"; |
11758 | case 0x3e: |
12672 | case 0x3e: |
11759 | return "ds"; |
12673 | return "ds"; |
11760 | case 0x26: |
12674 | case 0x26: |
11761 | return "es"; |
12675 | return "es"; |
11762 | case 0x64: |
12676 | case 0x64: |
11763 | return "fs"; |
12677 | return "fs"; |
11764 | case 0x65: |
12678 | case 0x65: |
11765 | return "gs"; |
12679 | return "gs"; |
11766 | case 0x66: |
12680 | case 0x66: |
11767 | return (sizeflag & DFLAG) ? "data16" : "data32"; |
12681 | return (sizeflag & DFLAG) ? "data16" : "data32"; |
11768 | case 0x67: |
12682 | case 0x67: |
11769 | if (address_mode == mode_64bit) |
12683 | if (address_mode == mode_64bit) |
11770 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
12684 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
11771 | else |
12685 | else |
11772 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
12686 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
11773 | case FWAIT_OPCODE: |
12687 | case FWAIT_OPCODE: |
11774 | return "fwait"; |
12688 | return "fwait"; |
11775 | case ADDR16_PREFIX: |
- | |
11776 | return "addr16"; |
- | |
11777 | case ADDR32_PREFIX: |
- | |
11778 | return "addr32"; |
- | |
11779 | case DATA16_PREFIX: |
- | |
11780 | return "data16"; |
- | |
11781 | case DATA32_PREFIX: |
- | |
11782 | return "data32"; |
- | |
11783 | case REP_PREFIX: |
12689 | case REP_PREFIX: |
11784 | return "rep"; |
12690 | return "rep"; |
11785 | case XACQUIRE_PREFIX: |
12691 | case XACQUIRE_PREFIX: |
11786 | return "xacquire"; |
12692 | return "xacquire"; |
11787 | case XRELEASE_PREFIX: |
12693 | case XRELEASE_PREFIX: |
11788 | return "xrelease"; |
12694 | return "xrelease"; |
11789 | case BND_PREFIX: |
12695 | case BND_PREFIX: |
11790 | return "bnd"; |
12696 | return "bnd"; |
11791 | default: |
12697 | default: |
11792 | return NULL; |
12698 | return NULL; |
11793 | } |
12699 | } |
11794 | } |
12700 | } |
11795 | 12701 | ||
11796 | static char op_out[MAX_OPERANDS][100]; |
12702 | static char op_out[MAX_OPERANDS][100]; |
11797 | static int op_ad, op_index[MAX_OPERANDS]; |
12703 | static int op_ad, op_index[MAX_OPERANDS]; |
11798 | static int two_source_ops; |
12704 | static int two_source_ops; |
11799 | static bfd_vma op_address[MAX_OPERANDS]; |
12705 | static bfd_vma op_address[MAX_OPERANDS]; |
11800 | static bfd_vma op_riprel[MAX_OPERANDS]; |
12706 | static bfd_vma op_riprel[MAX_OPERANDS]; |
11801 | static bfd_vma start_pc; |
12707 | static bfd_vma start_pc; |
11802 | 12708 | ||
11803 | /* |
12709 | /* |
11804 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. |
12710 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. |
11805 | * (see topic "Redundant prefixes" in the "Differences from 8086" |
12711 | * (see topic "Redundant prefixes" in the "Differences from 8086" |
11806 | * section of the "Virtual 8086 Mode" chapter.) |
12712 | * section of the "Virtual 8086 Mode" chapter.) |
11807 | * 'pc' should be the address of this instruction, it will |
12713 | * 'pc' should be the address of this instruction, it will |
11808 | * be used to print the target address if this is a relative jump or call |
12714 | * be used to print the target address if this is a relative jump or call |
11809 | * The function returns the length of this instruction in bytes. |
12715 | * The function returns the length of this instruction in bytes. |
11810 | */ |
12716 | */ |
11811 | 12717 | ||
11812 | static char intel_syntax; |
12718 | static char intel_syntax; |
11813 | static char intel_mnemonic = !SYSV386_COMPAT; |
12719 | static char intel_mnemonic = !SYSV386_COMPAT; |
11814 | static char open_char; |
12720 | static char open_char; |
11815 | static char close_char; |
12721 | static char close_char; |
11816 | static char separator_char; |
12722 | static char separator_char; |
11817 | static char scale_char; |
12723 | static char scale_char; |
- | 12724 | ||
- | 12725 | enum x86_64_isa |
|
- | 12726 | { |
|
- | 12727 | amd64 = 0, |
|
- | 12728 | intel64 |
|
- | 12729 | }; |
|
- | 12730 | ||
- | 12731 | static enum x86_64_isa isa64; |
|
11818 | 12732 | ||
11819 | /* Here for backwards compatibility. When gdb stops using |
12733 | /* Here for backwards compatibility. When gdb stops using |
11820 | print_insn_i386_att and print_insn_i386_intel these functions can |
12734 | print_insn_i386_att and print_insn_i386_intel these functions can |
11821 | disappear, and print_insn_i386 be merged into print_insn. */ |
12735 | disappear, and print_insn_i386 be merged into print_insn. */ |
11822 | int |
12736 | int |
11823 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
12737 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
11824 | { |
12738 | { |
11825 | intel_syntax = 0; |
12739 | intel_syntax = 0; |
11826 | 12740 | ||
11827 | return print_insn (pc, info); |
12741 | return print_insn (pc, info); |
11828 | } |
12742 | } |
11829 | 12743 | ||
11830 | int |
12744 | int |
11831 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
12745 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
11832 | { |
12746 | { |
11833 | intel_syntax = 1; |
12747 | intel_syntax = 1; |
11834 | 12748 | ||
11835 | return print_insn (pc, info); |
12749 | return print_insn (pc, info); |
11836 | } |
12750 | } |
11837 | 12751 | ||
11838 | int |
12752 | int |
11839 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
12753 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
11840 | { |
12754 | { |
11841 | intel_syntax = -1; |
12755 | intel_syntax = -1; |
11842 | 12756 | ||
11843 | return print_insn (pc, info); |
12757 | return print_insn (pc, info); |
11844 | } |
12758 | } |
11845 | 12759 | ||
11846 | void |
12760 | void |
11847 | print_i386_disassembler_options (FILE *stream) |
12761 | print_i386_disassembler_options (FILE *stream) |
11848 | { |
12762 | { |
11849 | fprintf (stream, _("\n\ |
12763 | fprintf (stream, _("\n\ |
11850 | The following i386/x86-64 specific disassembler options are supported for use\n\ |
12764 | The following i386/x86-64 specific disassembler options are supported for use\n\ |
11851 | with the -M switch (multiple options should be separated by commas):\n")); |
12765 | with the -M switch (multiple options should be separated by commas):\n")); |
11852 | 12766 | ||
11853 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); |
12767 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); |
11854 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); |
12768 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); |
11855 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); |
12769 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); |
11856 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); |
12770 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); |
11857 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); |
12771 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); |
11858 | fprintf (stream, _(" att-mnemonic\n" |
12772 | fprintf (stream, _(" att-mnemonic\n" |
11859 | " Display instruction in AT&T mnemonic\n")); |
12773 | " Display instruction in AT&T mnemonic\n")); |
11860 | fprintf (stream, _(" intel-mnemonic\n" |
12774 | fprintf (stream, _(" intel-mnemonic\n" |
11861 | " Display instruction in Intel mnemonic\n")); |
12775 | " Display instruction in Intel mnemonic\n")); |
11862 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
12776 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11863 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); |
12777 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); |
11864 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); |
12778 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); |
11865 | fprintf (stream, _(" data32 Assume 32bit data size\n")); |
12779 | fprintf (stream, _(" data32 Assume 32bit data size\n")); |
11866 | fprintf (stream, _(" data16 Assume 16bit data size\n")); |
12780 | fprintf (stream, _(" data16 Assume 16bit data size\n")); |
11867 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); |
12781 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); |
- | 12782 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
|
- | 12783 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); |
|
11868 | } |
12784 | } |
11869 | 12785 | ||
11870 | /* Bad opcode. */ |
12786 | /* Bad opcode. */ |
11871 | static const struct dis386 bad_opcode = { "(bad)", { XX } }; |
12787 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
11872 | 12788 | ||
11873 | /* Get a pointer to struct dis386 with a valid name. */ |
12789 | /* Get a pointer to struct dis386 with a valid name. */ |
11874 | 12790 | ||
11875 | static const struct dis386 * |
12791 | static const struct dis386 * |
11876 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
12792 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
11877 | { |
12793 | { |
11878 | int vindex, vex_table_index; |
12794 | int vindex, vex_table_index; |
11879 | 12795 | ||
11880 | if (dp->name != NULL) |
12796 | if (dp->name != NULL) |
11881 | return dp; |
12797 | return dp; |
11882 | 12798 | ||
11883 | switch (dp->op[0].bytemode) |
12799 | switch (dp->op[0].bytemode) |
11884 | { |
12800 | { |
11885 | case USE_REG_TABLE: |
12801 | case USE_REG_TABLE: |
11886 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; |
12802 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; |
11887 | break; |
12803 | break; |
11888 | 12804 | ||
11889 | case USE_MOD_TABLE: |
12805 | case USE_MOD_TABLE: |
11890 | vindex = modrm.mod == 0x3 ? 1 : 0; |
12806 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11891 | dp = &mod_table[dp->op[1].bytemode][vindex]; |
12807 | dp = &mod_table[dp->op[1].bytemode][vindex]; |
11892 | break; |
12808 | break; |
11893 | 12809 | ||
11894 | case USE_RM_TABLE: |
12810 | case USE_RM_TABLE: |
11895 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; |
12811 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; |
11896 | break; |
12812 | break; |
11897 | 12813 | ||
11898 | case USE_PREFIX_TABLE: |
12814 | case USE_PREFIX_TABLE: |
11899 | if (need_vex) |
12815 | if (need_vex) |
11900 | { |
12816 | { |
11901 | /* The prefix in VEX is implicit. */ |
12817 | /* The prefix in VEX is implicit. */ |
11902 | switch (vex.prefix) |
12818 | switch (vex.prefix) |
11903 | { |
12819 | { |
11904 | case 0: |
12820 | case 0: |
11905 | vindex = 0; |
12821 | vindex = 0; |
11906 | break; |
12822 | break; |
11907 | case REPE_PREFIX_OPCODE: |
12823 | case REPE_PREFIX_OPCODE: |
11908 | vindex = 1; |
12824 | vindex = 1; |
11909 | break; |
12825 | break; |
11910 | case DATA_PREFIX_OPCODE: |
12826 | case DATA_PREFIX_OPCODE: |
11911 | vindex = 2; |
12827 | vindex = 2; |
11912 | break; |
12828 | break; |
11913 | case REPNE_PREFIX_OPCODE: |
12829 | case REPNE_PREFIX_OPCODE: |
11914 | vindex = 3; |
12830 | vindex = 3; |
11915 | break; |
12831 | break; |
11916 | default: |
12832 | default: |
11917 | abort (); |
12833 | abort (); |
11918 | break; |
12834 | break; |
11919 | } |
12835 | } |
11920 | } |
12836 | } |
11921 | else |
12837 | else |
11922 | { |
12838 | { |
- | 12839 | int last_prefix = -1; |
|
- | 12840 | int prefix = 0; |
|
11923 | vindex = 0; |
12841 | vindex = 0; |
- | 12842 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
|
11924 | used_prefixes |= (prefixes & PREFIX_REPZ); |
12843 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the |
- | 12844 | last one wins. */ |
|
11925 | if (prefixes & PREFIX_REPZ) |
12845 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) |
- | 12846 | { |
|
- | 12847 | if (last_repz_prefix > last_repnz_prefix) |
|
11926 | { |
12848 | { |
11927 | vindex = 1; |
12849 | vindex = 1; |
- | 12850 | prefix = PREFIX_REPZ; |
|
11928 | all_prefixes[last_repz_prefix] = 0; |
12851 | last_prefix = last_repz_prefix; |
11929 | } |
12852 | } |
11930 | else |
12853 | else |
11931 | { |
12854 | { |
11932 | /* We should check PREFIX_REPNZ and PREFIX_REPZ before |
- | |
11933 | PREFIX_DATA. */ |
- | |
11934 | used_prefixes |= (prefixes & PREFIX_REPNZ); |
- | |
11935 | if (prefixes & PREFIX_REPNZ) |
- | |
11936 | { |
- | |
11937 | vindex = 3; |
12855 | vindex = 3; |
- | 12856 | prefix = PREFIX_REPNZ; |
|
11938 | all_prefixes[last_repnz_prefix] = 0; |
12857 | last_prefix = last_repnz_prefix; |
11939 | } |
12858 | } |
- | 12859 | ||
- | 12860 | /* Check if prefix should be ignored. */ |
|
- | 12861 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement |
|
- | 12862 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) |
|
- | 12863 | & prefix) != 0) |
|
- | 12864 | vindex = 0; |
|
11940 | else |
12865 | } |
11941 | { |
12866 | |
11942 | used_prefixes |= (prefixes & PREFIX_DATA); |
12867 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) |
11943 | if (prefixes & PREFIX_DATA) |
- | |
11944 | { |
12868 | { |
11945 | vindex = 2; |
12869 | vindex = 2; |
- | 12870 | prefix = PREFIX_DATA; |
|
11946 | all_prefixes[last_data_prefix] = 0; |
12871 | last_prefix = last_data_prefix; |
11947 | } |
- | |
11948 | } |
12872 | } |
- | 12873 | ||
- | 12874 | if (vindex != 0) |
|
- | 12875 | { |
|
- | 12876 | used_prefixes |= prefix; |
|
- | 12877 | all_prefixes[last_prefix] = 0; |
|
11949 | } |
12878 | } |
11950 | } |
12879 | } |
11951 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
12880 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
11952 | break; |
12881 | break; |
11953 | 12882 | ||
11954 | case USE_X86_64_TABLE: |
12883 | case USE_X86_64_TABLE: |
11955 | vindex = address_mode == mode_64bit ? 1 : 0; |
12884 | vindex = address_mode == mode_64bit ? 1 : 0; |
11956 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; |
12885 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; |
11957 | break; |
12886 | break; |
11958 | 12887 | ||
11959 | case USE_3BYTE_TABLE: |
12888 | case USE_3BYTE_TABLE: |
11960 | FETCH_DATA (info, codep + 2); |
12889 | FETCH_DATA (info, codep + 2); |
11961 | vindex = *codep++; |
12890 | vindex = *codep++; |
11962 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; |
12891 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; |
- | 12892 | end_codep = codep; |
|
11963 | modrm.mod = (*codep >> 6) & 3; |
12893 | modrm.mod = (*codep >> 6) & 3; |
11964 | modrm.reg = (*codep >> 3) & 7; |
12894 | modrm.reg = (*codep >> 3) & 7; |
11965 | modrm.rm = *codep & 7; |
12895 | modrm.rm = *codep & 7; |
11966 | break; |
12896 | break; |
11967 | 12897 | ||
11968 | case USE_VEX_LEN_TABLE: |
12898 | case USE_VEX_LEN_TABLE: |
11969 | if (!need_vex) |
12899 | if (!need_vex) |
11970 | abort (); |
12900 | abort (); |
11971 | 12901 | ||
11972 | switch (vex.length) |
12902 | switch (vex.length) |
11973 | { |
12903 | { |
11974 | case 128: |
12904 | case 128: |
11975 | vindex = 0; |
12905 | vindex = 0; |
11976 | break; |
12906 | break; |
11977 | case 256: |
12907 | case 256: |
11978 | vindex = 1; |
12908 | vindex = 1; |
11979 | break; |
12909 | break; |
11980 | default: |
12910 | default: |
11981 | abort (); |
12911 | abort (); |
11982 | break; |
12912 | break; |
11983 | } |
12913 | } |
11984 | 12914 | ||
11985 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
12915 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
11986 | break; |
12916 | break; |
11987 | 12917 | ||
11988 | case USE_XOP_8F_TABLE: |
12918 | case USE_XOP_8F_TABLE: |
11989 | FETCH_DATA (info, codep + 3); |
12919 | FETCH_DATA (info, codep + 3); |
11990 | /* All bits in the REX prefix are ignored. */ |
12920 | /* All bits in the REX prefix are ignored. */ |
11991 | rex_ignored = rex; |
12921 | rex_ignored = rex; |
11992 | rex = ~(*codep >> 5) & 0x7; |
12922 | rex = ~(*codep >> 5) & 0x7; |
11993 | 12923 | ||
11994 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ |
12924 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ |
11995 | switch ((*codep & 0x1f)) |
12925 | switch ((*codep & 0x1f)) |
11996 | { |
12926 | { |
11997 | default: |
12927 | default: |
11998 | dp = &bad_opcode; |
12928 | dp = &bad_opcode; |
11999 | return dp; |
12929 | return dp; |
12000 | case 0x8: |
12930 | case 0x8: |
12001 | vex_table_index = XOP_08; |
12931 | vex_table_index = XOP_08; |
12002 | break; |
12932 | break; |
12003 | case 0x9: |
12933 | case 0x9: |
12004 | vex_table_index = XOP_09; |
12934 | vex_table_index = XOP_09; |
12005 | break; |
12935 | break; |
12006 | case 0xa: |
12936 | case 0xa: |
12007 | vex_table_index = XOP_0A; |
12937 | vex_table_index = XOP_0A; |
12008 | break; |
12938 | break; |
12009 | } |
12939 | } |
12010 | codep++; |
12940 | codep++; |
12011 | vex.w = *codep & 0x80; |
12941 | vex.w = *codep & 0x80; |
12012 | if (vex.w && address_mode == mode_64bit) |
12942 | if (vex.w && address_mode == mode_64bit) |
12013 | rex |= REX_W; |
12943 | rex |= REX_W; |
12014 | 12944 | ||
12015 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
12945 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
12016 | if (address_mode != mode_64bit |
12946 | if (address_mode != mode_64bit |
12017 | && vex.register_specifier > 0x7) |
12947 | && vex.register_specifier > 0x7) |
12018 | { |
12948 | { |
12019 | dp = &bad_opcode; |
12949 | dp = &bad_opcode; |
12020 | return dp; |
12950 | return dp; |
12021 | } |
12951 | } |
12022 | 12952 | ||
12023 | vex.length = (*codep & 0x4) ? 256 : 128; |
12953 | vex.length = (*codep & 0x4) ? 256 : 128; |
12024 | switch ((*codep & 0x3)) |
12954 | switch ((*codep & 0x3)) |
12025 | { |
12955 | { |
12026 | case 0: |
12956 | case 0: |
12027 | vex.prefix = 0; |
12957 | vex.prefix = 0; |
12028 | break; |
12958 | break; |
12029 | case 1: |
12959 | case 1: |
12030 | vex.prefix = DATA_PREFIX_OPCODE; |
12960 | vex.prefix = DATA_PREFIX_OPCODE; |
12031 | break; |
12961 | break; |
12032 | case 2: |
12962 | case 2: |
12033 | vex.prefix = REPE_PREFIX_OPCODE; |
12963 | vex.prefix = REPE_PREFIX_OPCODE; |
12034 | break; |
12964 | break; |
12035 | case 3: |
12965 | case 3: |
12036 | vex.prefix = REPNE_PREFIX_OPCODE; |
12966 | vex.prefix = REPNE_PREFIX_OPCODE; |
12037 | break; |
12967 | break; |
12038 | } |
12968 | } |
12039 | need_vex = 1; |
12969 | need_vex = 1; |
12040 | need_vex_reg = 1; |
12970 | need_vex_reg = 1; |
12041 | codep++; |
12971 | codep++; |
12042 | vindex = *codep++; |
12972 | vindex = *codep++; |
12043 | dp = &xop_table[vex_table_index][vindex]; |
12973 | dp = &xop_table[vex_table_index][vindex]; |
- | 12974 | ||
12044 | 12975 | end_codep = codep; |
|
12045 | FETCH_DATA (info, codep + 1); |
12976 | FETCH_DATA (info, codep + 1); |
12046 | modrm.mod = (*codep >> 6) & 3; |
12977 | modrm.mod = (*codep >> 6) & 3; |
12047 | modrm.reg = (*codep >> 3) & 7; |
12978 | modrm.reg = (*codep >> 3) & 7; |
12048 | modrm.rm = *codep & 7; |
12979 | modrm.rm = *codep & 7; |
12049 | break; |
12980 | break; |
12050 | 12981 | ||
12051 | case USE_VEX_C4_TABLE: |
12982 | case USE_VEX_C4_TABLE: |
12052 | /* VEX prefix. */ |
12983 | /* VEX prefix. */ |
12053 | FETCH_DATA (info, codep + 3); |
12984 | FETCH_DATA (info, codep + 3); |
12054 | /* All bits in the REX prefix are ignored. */ |
12985 | /* All bits in the REX prefix are ignored. */ |
12055 | rex_ignored = rex; |
12986 | rex_ignored = rex; |
12056 | rex = ~(*codep >> 5) & 0x7; |
12987 | rex = ~(*codep >> 5) & 0x7; |
12057 | switch ((*codep & 0x1f)) |
12988 | switch ((*codep & 0x1f)) |
12058 | { |
12989 | { |
12059 | default: |
12990 | default: |
12060 | dp = &bad_opcode; |
12991 | dp = &bad_opcode; |
12061 | return dp; |
12992 | return dp; |
12062 | case 0x1: |
12993 | case 0x1: |
12063 | vex_table_index = VEX_0F; |
12994 | vex_table_index = VEX_0F; |
12064 | break; |
12995 | break; |
12065 | case 0x2: |
12996 | case 0x2: |
12066 | vex_table_index = VEX_0F38; |
12997 | vex_table_index = VEX_0F38; |
12067 | break; |
12998 | break; |
12068 | case 0x3: |
12999 | case 0x3: |
12069 | vex_table_index = VEX_0F3A; |
13000 | vex_table_index = VEX_0F3A; |
12070 | break; |
13001 | break; |
12071 | } |
13002 | } |
12072 | codep++; |
13003 | codep++; |
12073 | vex.w = *codep & 0x80; |
13004 | vex.w = *codep & 0x80; |
12074 | if (vex.w && address_mode == mode_64bit) |
13005 | if (vex.w && address_mode == mode_64bit) |
12075 | rex |= REX_W; |
13006 | rex |= REX_W; |
12076 | 13007 | ||
12077 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
13008 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
12078 | if (address_mode != mode_64bit |
13009 | if (address_mode != mode_64bit |
12079 | && vex.register_specifier > 0x7) |
13010 | && vex.register_specifier > 0x7) |
12080 | { |
13011 | { |
12081 | dp = &bad_opcode; |
13012 | dp = &bad_opcode; |
12082 | return dp; |
13013 | return dp; |
12083 | } |
13014 | } |
12084 | 13015 | ||
12085 | vex.length = (*codep & 0x4) ? 256 : 128; |
13016 | vex.length = (*codep & 0x4) ? 256 : 128; |
12086 | switch ((*codep & 0x3)) |
13017 | switch ((*codep & 0x3)) |
12087 | { |
13018 | { |
12088 | case 0: |
13019 | case 0: |
12089 | vex.prefix = 0; |
13020 | vex.prefix = 0; |
12090 | break; |
13021 | break; |
12091 | case 1: |
13022 | case 1: |
12092 | vex.prefix = DATA_PREFIX_OPCODE; |
13023 | vex.prefix = DATA_PREFIX_OPCODE; |
12093 | break; |
13024 | break; |
12094 | case 2: |
13025 | case 2: |
12095 | vex.prefix = REPE_PREFIX_OPCODE; |
13026 | vex.prefix = REPE_PREFIX_OPCODE; |
12096 | break; |
13027 | break; |
12097 | case 3: |
13028 | case 3: |
12098 | vex.prefix = REPNE_PREFIX_OPCODE; |
13029 | vex.prefix = REPNE_PREFIX_OPCODE; |
12099 | break; |
13030 | break; |
12100 | } |
13031 | } |
12101 | need_vex = 1; |
13032 | need_vex = 1; |
12102 | need_vex_reg = 1; |
13033 | need_vex_reg = 1; |
12103 | codep++; |
13034 | codep++; |
12104 | vindex = *codep++; |
13035 | vindex = *codep++; |
12105 | dp = &vex_table[vex_table_index][vindex]; |
13036 | dp = &vex_table[vex_table_index][vindex]; |
- | 13037 | end_codep = codep; |
|
12106 | /* There is no MODRM byte for VEX [82|77]. */ |
13038 | /* There is no MODRM byte for VEX [82|77]. */ |
12107 | if (vindex != 0x77 && vindex != 0x82) |
13039 | if (vindex != 0x77 && vindex != 0x82) |
12108 | { |
13040 | { |
12109 | FETCH_DATA (info, codep + 1); |
13041 | FETCH_DATA (info, codep + 1); |
12110 | modrm.mod = (*codep >> 6) & 3; |
13042 | modrm.mod = (*codep >> 6) & 3; |
12111 | modrm.reg = (*codep >> 3) & 7; |
13043 | modrm.reg = (*codep >> 3) & 7; |
12112 | modrm.rm = *codep & 7; |
13044 | modrm.rm = *codep & 7; |
12113 | } |
13045 | } |
12114 | break; |
13046 | break; |
12115 | 13047 | ||
12116 | case USE_VEX_C5_TABLE: |
13048 | case USE_VEX_C5_TABLE: |
12117 | /* VEX prefix. */ |
13049 | /* VEX prefix. */ |
12118 | FETCH_DATA (info, codep + 2); |
13050 | FETCH_DATA (info, codep + 2); |
12119 | /* All bits in the REX prefix are ignored. */ |
13051 | /* All bits in the REX prefix are ignored. */ |
12120 | rex_ignored = rex; |
13052 | rex_ignored = rex; |
12121 | rex = (*codep & 0x80) ? 0 : REX_R; |
13053 | rex = (*codep & 0x80) ? 0 : REX_R; |
12122 | 13054 | ||
12123 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
13055 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
12124 | if (address_mode != mode_64bit |
13056 | if (address_mode != mode_64bit |
12125 | && vex.register_specifier > 0x7) |
13057 | && vex.register_specifier > 0x7) |
12126 | { |
13058 | { |
12127 | dp = &bad_opcode; |
13059 | dp = &bad_opcode; |
12128 | return dp; |
13060 | return dp; |
12129 | } |
13061 | } |
12130 | 13062 | ||
12131 | vex.w = 0; |
13063 | vex.w = 0; |
12132 | 13064 | ||
12133 | vex.length = (*codep & 0x4) ? 256 : 128; |
13065 | vex.length = (*codep & 0x4) ? 256 : 128; |
12134 | switch ((*codep & 0x3)) |
13066 | switch ((*codep & 0x3)) |
12135 | { |
13067 | { |
12136 | case 0: |
13068 | case 0: |
12137 | vex.prefix = 0; |
13069 | vex.prefix = 0; |
12138 | break; |
13070 | break; |
12139 | case 1: |
13071 | case 1: |
12140 | vex.prefix = DATA_PREFIX_OPCODE; |
13072 | vex.prefix = DATA_PREFIX_OPCODE; |
12141 | break; |
13073 | break; |
12142 | case 2: |
13074 | case 2: |
12143 | vex.prefix = REPE_PREFIX_OPCODE; |
13075 | vex.prefix = REPE_PREFIX_OPCODE; |
12144 | break; |
13076 | break; |
12145 | case 3: |
13077 | case 3: |
12146 | vex.prefix = REPNE_PREFIX_OPCODE; |
13078 | vex.prefix = REPNE_PREFIX_OPCODE; |
12147 | break; |
13079 | break; |
12148 | } |
13080 | } |
12149 | need_vex = 1; |
13081 | need_vex = 1; |
12150 | need_vex_reg = 1; |
13082 | need_vex_reg = 1; |
12151 | codep++; |
13083 | codep++; |
12152 | vindex = *codep++; |
13084 | vindex = *codep++; |
12153 | dp = &vex_table[dp->op[1].bytemode][vindex]; |
13085 | dp = &vex_table[dp->op[1].bytemode][vindex]; |
- | 13086 | end_codep = codep; |
|
12154 | /* There is no MODRM byte for VEX [82|77]. */ |
13087 | /* There is no MODRM byte for VEX [82|77]. */ |
12155 | if (vindex != 0x77 && vindex != 0x82) |
13088 | if (vindex != 0x77 && vindex != 0x82) |
12156 | { |
13089 | { |
12157 | FETCH_DATA (info, codep + 1); |
13090 | FETCH_DATA (info, codep + 1); |
12158 | modrm.mod = (*codep >> 6) & 3; |
13091 | modrm.mod = (*codep >> 6) & 3; |
12159 | modrm.reg = (*codep >> 3) & 7; |
13092 | modrm.reg = (*codep >> 3) & 7; |
12160 | modrm.rm = *codep & 7; |
13093 | modrm.rm = *codep & 7; |
12161 | } |
13094 | } |
12162 | break; |
13095 | break; |
12163 | 13096 | ||
12164 | case USE_VEX_W_TABLE: |
13097 | case USE_VEX_W_TABLE: |
12165 | if (!need_vex) |
13098 | if (!need_vex) |
12166 | abort (); |
13099 | abort (); |
12167 | 13100 | ||
12168 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; |
13101 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; |
12169 | break; |
13102 | break; |
12170 | 13103 | ||
12171 | case USE_EVEX_TABLE: |
13104 | case USE_EVEX_TABLE: |
12172 | two_source_ops = 0; |
13105 | two_source_ops = 0; |
12173 | /* EVEX prefix. */ |
13106 | /* EVEX prefix. */ |
12174 | vex.evex = 1; |
13107 | vex.evex = 1; |
12175 | FETCH_DATA (info, codep + 4); |
13108 | FETCH_DATA (info, codep + 4); |
12176 | /* All bits in the REX prefix are ignored. */ |
13109 | /* All bits in the REX prefix are ignored. */ |
12177 | rex_ignored = rex; |
13110 | rex_ignored = rex; |
12178 | /* The first byte after 0x62. */ |
13111 | /* The first byte after 0x62. */ |
12179 | rex = ~(*codep >> 5) & 0x7; |
13112 | rex = ~(*codep >> 5) & 0x7; |
12180 | vex.r = *codep & 0x10; |
13113 | vex.r = *codep & 0x10; |
12181 | switch ((*codep & 0xf)) |
13114 | switch ((*codep & 0xf)) |
12182 | { |
13115 | { |
12183 | default: |
13116 | default: |
12184 | return &bad_opcode; |
13117 | return &bad_opcode; |
12185 | case 0x1: |
13118 | case 0x1: |
12186 | vex_table_index = EVEX_0F; |
13119 | vex_table_index = EVEX_0F; |
12187 | break; |
13120 | break; |
12188 | case 0x2: |
13121 | case 0x2: |
12189 | vex_table_index = EVEX_0F38; |
13122 | vex_table_index = EVEX_0F38; |
12190 | break; |
13123 | break; |
12191 | case 0x3: |
13124 | case 0x3: |
12192 | vex_table_index = EVEX_0F3A; |
13125 | vex_table_index = EVEX_0F3A; |
12193 | break; |
13126 | break; |
12194 | } |
13127 | } |
12195 | 13128 | ||
12196 | /* The second byte after 0x62. */ |
13129 | /* The second byte after 0x62. */ |
12197 | codep++; |
13130 | codep++; |
12198 | vex.w = *codep & 0x80; |
13131 | vex.w = *codep & 0x80; |
12199 | if (vex.w && address_mode == mode_64bit) |
13132 | if (vex.w && address_mode == mode_64bit) |
12200 | rex |= REX_W; |
13133 | rex |= REX_W; |
12201 | 13134 | ||
12202 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
13135 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
12203 | if (address_mode != mode_64bit) |
13136 | if (address_mode != mode_64bit) |
12204 | { |
13137 | { |
12205 | /* In 16/32-bit mode silently ignore following bits. */ |
13138 | /* In 16/32-bit mode silently ignore following bits. */ |
12206 | rex &= ~REX_B; |
13139 | rex &= ~REX_B; |
12207 | vex.r = 1; |
13140 | vex.r = 1; |
12208 | vex.v = 1; |
13141 | vex.v = 1; |
12209 | vex.register_specifier &= 0x7; |
13142 | vex.register_specifier &= 0x7; |
12210 | } |
13143 | } |
12211 | 13144 | ||
12212 | /* The U bit. */ |
13145 | /* The U bit. */ |
12213 | if (!(*codep & 0x4)) |
13146 | if (!(*codep & 0x4)) |
12214 | return &bad_opcode; |
13147 | return &bad_opcode; |
12215 | 13148 | ||
12216 | switch ((*codep & 0x3)) |
13149 | switch ((*codep & 0x3)) |
12217 | { |
13150 | { |
12218 | case 0: |
13151 | case 0: |
12219 | vex.prefix = 0; |
13152 | vex.prefix = 0; |
12220 | break; |
13153 | break; |
12221 | case 1: |
13154 | case 1: |
12222 | vex.prefix = DATA_PREFIX_OPCODE; |
13155 | vex.prefix = DATA_PREFIX_OPCODE; |
12223 | break; |
13156 | break; |
12224 | case 2: |
13157 | case 2: |
12225 | vex.prefix = REPE_PREFIX_OPCODE; |
13158 | vex.prefix = REPE_PREFIX_OPCODE; |
12226 | break; |
13159 | break; |
12227 | case 3: |
13160 | case 3: |
12228 | vex.prefix = REPNE_PREFIX_OPCODE; |
13161 | vex.prefix = REPNE_PREFIX_OPCODE; |
12229 | break; |
13162 | break; |
12230 | } |
13163 | } |
12231 | 13164 | ||
12232 | /* The third byte after 0x62. */ |
13165 | /* The third byte after 0x62. */ |
12233 | codep++; |
13166 | codep++; |
12234 | 13167 | ||
12235 | /* Remember the static rounding bits. */ |
13168 | /* Remember the static rounding bits. */ |
12236 | vex.ll = (*codep >> 5) & 3; |
13169 | vex.ll = (*codep >> 5) & 3; |
12237 | vex.b = (*codep & 0x10) != 0; |
13170 | vex.b = (*codep & 0x10) != 0; |
12238 | 13171 | ||
12239 | vex.v = *codep & 0x8; |
13172 | vex.v = *codep & 0x8; |
12240 | vex.mask_register_specifier = *codep & 0x7; |
13173 | vex.mask_register_specifier = *codep & 0x7; |
12241 | vex.zeroing = *codep & 0x80; |
13174 | vex.zeroing = *codep & 0x80; |
12242 | 13175 | ||
12243 | need_vex = 1; |
13176 | need_vex = 1; |
12244 | need_vex_reg = 1; |
13177 | need_vex_reg = 1; |
12245 | codep++; |
13178 | codep++; |
12246 | vindex = *codep++; |
13179 | vindex = *codep++; |
12247 | dp = &evex_table[vex_table_index][vindex]; |
13180 | dp = &evex_table[vex_table_index][vindex]; |
- | 13181 | end_codep = codep; |
|
12248 | FETCH_DATA (info, codep + 1); |
13182 | FETCH_DATA (info, codep + 1); |
12249 | modrm.mod = (*codep >> 6) & 3; |
13183 | modrm.mod = (*codep >> 6) & 3; |
12250 | modrm.reg = (*codep >> 3) & 7; |
13184 | modrm.reg = (*codep >> 3) & 7; |
12251 | modrm.rm = *codep & 7; |
13185 | modrm.rm = *codep & 7; |
12252 | 13186 | ||
12253 | /* Set vector length. */ |
13187 | /* Set vector length. */ |
12254 | if (modrm.mod == 3 && vex.b) |
13188 | if (modrm.mod == 3 && vex.b) |
12255 | vex.length = 512; |
13189 | vex.length = 512; |
12256 | else |
13190 | else |
12257 | { |
13191 | { |
12258 | switch (vex.ll) |
13192 | switch (vex.ll) |
12259 | { |
13193 | { |
12260 | case 0x0: |
13194 | case 0x0: |
12261 | vex.length = 128; |
13195 | vex.length = 128; |
12262 | break; |
13196 | break; |
12263 | case 0x1: |
13197 | case 0x1: |
12264 | vex.length = 256; |
13198 | vex.length = 256; |
12265 | break; |
13199 | break; |
12266 | case 0x2: |
13200 | case 0x2: |
12267 | vex.length = 512; |
13201 | vex.length = 512; |
12268 | break; |
13202 | break; |
12269 | default: |
13203 | default: |
12270 | return &bad_opcode; |
13204 | return &bad_opcode; |
12271 | } |
13205 | } |
12272 | } |
13206 | } |
12273 | break; |
13207 | break; |
12274 | 13208 | ||
12275 | case 0: |
13209 | case 0: |
12276 | dp = &bad_opcode; |
13210 | dp = &bad_opcode; |
12277 | break; |
13211 | break; |
12278 | 13212 | ||
12279 | default: |
13213 | default: |
12280 | abort (); |
13214 | abort (); |
12281 | } |
13215 | } |
12282 | 13216 | ||
12283 | if (dp->name != NULL) |
13217 | if (dp->name != NULL) |
12284 | return dp; |
13218 | return dp; |
12285 | else |
13219 | else |
12286 | return get_valid_dis386 (dp, info); |
13220 | return get_valid_dis386 (dp, info); |
12287 | } |
13221 | } |
12288 | 13222 | ||
12289 | static void |
13223 | static void |
12290 | get_sib (disassemble_info *info, int sizeflag) |
13224 | get_sib (disassemble_info *info, int sizeflag) |
12291 | { |
13225 | { |
12292 | /* If modrm.mod == 3, operand must be register. */ |
13226 | /* If modrm.mod == 3, operand must be register. */ |
12293 | if (need_modrm |
13227 | if (need_modrm |
12294 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
13228 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
12295 | && modrm.mod != 3 |
13229 | && modrm.mod != 3 |
12296 | && modrm.rm == 4) |
13230 | && modrm.rm == 4) |
12297 | { |
13231 | { |
12298 | FETCH_DATA (info, codep + 2); |
13232 | FETCH_DATA (info, codep + 2); |
12299 | sib.index = (codep [1] >> 3) & 7; |
13233 | sib.index = (codep [1] >> 3) & 7; |
12300 | sib.scale = (codep [1] >> 6) & 3; |
13234 | sib.scale = (codep [1] >> 6) & 3; |
12301 | sib.base = codep [1] & 7; |
13235 | sib.base = codep [1] & 7; |
12302 | } |
13236 | } |
12303 | } |
13237 | } |
12304 | 13238 | ||
12305 | static int |
13239 | static int |
12306 | print_insn (bfd_vma pc, disassemble_info *info) |
13240 | print_insn (bfd_vma pc, disassemble_info *info) |
12307 | { |
13241 | { |
12308 | const struct dis386 *dp; |
13242 | const struct dis386 *dp; |
12309 | int i; |
13243 | int i; |
12310 | char *op_txt[MAX_OPERANDS]; |
13244 | char *op_txt[MAX_OPERANDS]; |
12311 | int needcomma; |
13245 | int needcomma; |
12312 | int sizeflag; |
13246 | int sizeflag, orig_sizeflag; |
12313 | const char *p; |
13247 | const char *p; |
12314 | struct dis_private priv; |
13248 | struct dis_private priv; |
12315 | int prefix_length; |
13249 | int prefix_length; |
12316 | int default_prefixes; |
- | |
12317 | 13250 | ||
12318 | priv.orig_sizeflag = AFLAG | DFLAG; |
13251 | priv.orig_sizeflag = AFLAG | DFLAG; |
12319 | if ((info->mach & bfd_mach_i386_i386) != 0) |
13252 | if ((info->mach & bfd_mach_i386_i386) != 0) |
12320 | address_mode = mode_32bit; |
13253 | address_mode = mode_32bit; |
12321 | else if (info->mach == bfd_mach_i386_i8086) |
13254 | else if (info->mach == bfd_mach_i386_i8086) |
12322 | { |
13255 | { |
12323 | address_mode = mode_16bit; |
13256 | address_mode = mode_16bit; |
12324 | priv.orig_sizeflag = 0; |
13257 | priv.orig_sizeflag = 0; |
12325 | } |
13258 | } |
12326 | else |
13259 | else |
12327 | address_mode = mode_64bit; |
13260 | address_mode = mode_64bit; |
12328 | 13261 | ||
12329 | if (intel_syntax == (char) -1) |
13262 | if (intel_syntax == (char) -1) |
12330 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; |
13263 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; |
12331 | 13264 | ||
12332 | for (p = info->disassembler_options; p != NULL; ) |
13265 | for (p = info->disassembler_options; p != NULL; ) |
12333 | { |
13266 | { |
12334 | if (CONST_STRNEQ (p, "x86-64")) |
13267 | if (CONST_STRNEQ (p, "amd64")) |
- | 13268 | isa64 = amd64; |
|
- | 13269 | else if (CONST_STRNEQ (p, "intel64")) |
|
- | 13270 | isa64 = intel64; |
|
- | 13271 | else if (CONST_STRNEQ (p, "x86-64")) |
|
12335 | { |
13272 | { |
12336 | address_mode = mode_64bit; |
13273 | address_mode = mode_64bit; |
12337 | priv.orig_sizeflag = AFLAG | DFLAG; |
13274 | priv.orig_sizeflag = AFLAG | DFLAG; |
12338 | } |
13275 | } |
12339 | else if (CONST_STRNEQ (p, "i386")) |
13276 | else if (CONST_STRNEQ (p, "i386")) |
12340 | { |
13277 | { |
12341 | address_mode = mode_32bit; |
13278 | address_mode = mode_32bit; |
12342 | priv.orig_sizeflag = AFLAG | DFLAG; |
13279 | priv.orig_sizeflag = AFLAG | DFLAG; |
12343 | } |
13280 | } |
12344 | else if (CONST_STRNEQ (p, "i8086")) |
13281 | else if (CONST_STRNEQ (p, "i8086")) |
12345 | { |
13282 | { |
12346 | address_mode = mode_16bit; |
13283 | address_mode = mode_16bit; |
12347 | priv.orig_sizeflag = 0; |
13284 | priv.orig_sizeflag = 0; |
12348 | } |
13285 | } |
12349 | else if (CONST_STRNEQ (p, "intel")) |
13286 | else if (CONST_STRNEQ (p, "intel")) |
12350 | { |
13287 | { |
12351 | intel_syntax = 1; |
13288 | intel_syntax = 1; |
12352 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
13289 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
12353 | intel_mnemonic = 1; |
13290 | intel_mnemonic = 1; |
12354 | } |
13291 | } |
12355 | else if (CONST_STRNEQ (p, "att")) |
13292 | else if (CONST_STRNEQ (p, "att")) |
12356 | { |
13293 | { |
12357 | intel_syntax = 0; |
13294 | intel_syntax = 0; |
12358 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
13295 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
12359 | intel_mnemonic = 0; |
13296 | intel_mnemonic = 0; |
12360 | } |
13297 | } |
12361 | else if (CONST_STRNEQ (p, "addr")) |
13298 | else if (CONST_STRNEQ (p, "addr")) |
12362 | { |
13299 | { |
12363 | if (address_mode == mode_64bit) |
13300 | if (address_mode == mode_64bit) |
12364 | { |
13301 | { |
12365 | if (p[4] == '3' && p[5] == '2') |
13302 | if (p[4] == '3' && p[5] == '2') |
12366 | priv.orig_sizeflag &= ~AFLAG; |
13303 | priv.orig_sizeflag &= ~AFLAG; |
12367 | else if (p[4] == '6' && p[5] == '4') |
13304 | else if (p[4] == '6' && p[5] == '4') |
12368 | priv.orig_sizeflag |= AFLAG; |
13305 | priv.orig_sizeflag |= AFLAG; |
12369 | } |
13306 | } |
12370 | else |
13307 | else |
12371 | { |
13308 | { |
12372 | if (p[4] == '1' && p[5] == '6') |
13309 | if (p[4] == '1' && p[5] == '6') |
12373 | priv.orig_sizeflag &= ~AFLAG; |
13310 | priv.orig_sizeflag &= ~AFLAG; |
12374 | else if (p[4] == '3' && p[5] == '2') |
13311 | else if (p[4] == '3' && p[5] == '2') |
12375 | priv.orig_sizeflag |= AFLAG; |
13312 | priv.orig_sizeflag |= AFLAG; |
12376 | } |
13313 | } |
12377 | } |
13314 | } |
12378 | else if (CONST_STRNEQ (p, "data")) |
13315 | else if (CONST_STRNEQ (p, "data")) |
12379 | { |
13316 | { |
12380 | if (p[4] == '1' && p[5] == '6') |
13317 | if (p[4] == '1' && p[5] == '6') |
12381 | priv.orig_sizeflag &= ~DFLAG; |
13318 | priv.orig_sizeflag &= ~DFLAG; |
12382 | else if (p[4] == '3' && p[5] == '2') |
13319 | else if (p[4] == '3' && p[5] == '2') |
12383 | priv.orig_sizeflag |= DFLAG; |
13320 | priv.orig_sizeflag |= DFLAG; |
12384 | } |
13321 | } |
12385 | else if (CONST_STRNEQ (p, "suffix")) |
13322 | else if (CONST_STRNEQ (p, "suffix")) |
12386 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
13323 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
12387 | 13324 | ||
12388 | p = strchr (p, ','); |
13325 | p = strchr (p, ','); |
12389 | if (p != NULL) |
13326 | if (p != NULL) |
12390 | p++; |
13327 | p++; |
12391 | } |
13328 | } |
12392 | 13329 | ||
12393 | if (intel_syntax) |
13330 | if (intel_syntax) |
12394 | { |
13331 | { |
12395 | names64 = intel_names64; |
13332 | names64 = intel_names64; |
12396 | names32 = intel_names32; |
13333 | names32 = intel_names32; |
12397 | names16 = intel_names16; |
13334 | names16 = intel_names16; |
12398 | names8 = intel_names8; |
13335 | names8 = intel_names8; |
12399 | names8rex = intel_names8rex; |
13336 | names8rex = intel_names8rex; |
12400 | names_seg = intel_names_seg; |
13337 | names_seg = intel_names_seg; |
12401 | names_mm = intel_names_mm; |
13338 | names_mm = intel_names_mm; |
12402 | names_bnd = intel_names_bnd; |
13339 | names_bnd = intel_names_bnd; |
12403 | names_xmm = intel_names_xmm; |
13340 | names_xmm = intel_names_xmm; |
12404 | names_ymm = intel_names_ymm; |
13341 | names_ymm = intel_names_ymm; |
12405 | names_zmm = intel_names_zmm; |
13342 | names_zmm = intel_names_zmm; |
12406 | index64 = intel_index64; |
13343 | index64 = intel_index64; |
12407 | index32 = intel_index32; |
13344 | index32 = intel_index32; |
12408 | names_mask = intel_names_mask; |
13345 | names_mask = intel_names_mask; |
12409 | index16 = intel_index16; |
13346 | index16 = intel_index16; |
12410 | open_char = '['; |
13347 | open_char = '['; |
12411 | close_char = ']'; |
13348 | close_char = ']'; |
12412 | separator_char = '+'; |
13349 | separator_char = '+'; |
12413 | scale_char = '*'; |
13350 | scale_char = '*'; |
12414 | } |
13351 | } |
12415 | else |
13352 | else |
12416 | { |
13353 | { |
12417 | names64 = att_names64; |
13354 | names64 = att_names64; |
12418 | names32 = att_names32; |
13355 | names32 = att_names32; |
12419 | names16 = att_names16; |
13356 | names16 = att_names16; |
12420 | names8 = att_names8; |
13357 | names8 = att_names8; |
12421 | names8rex = att_names8rex; |
13358 | names8rex = att_names8rex; |
12422 | names_seg = att_names_seg; |
13359 | names_seg = att_names_seg; |
12423 | names_mm = att_names_mm; |
13360 | names_mm = att_names_mm; |
12424 | names_bnd = att_names_bnd; |
13361 | names_bnd = att_names_bnd; |
12425 | names_xmm = att_names_xmm; |
13362 | names_xmm = att_names_xmm; |
12426 | names_ymm = att_names_ymm; |
13363 | names_ymm = att_names_ymm; |
12427 | names_zmm = att_names_zmm; |
13364 | names_zmm = att_names_zmm; |
12428 | index64 = att_index64; |
13365 | index64 = att_index64; |
12429 | index32 = att_index32; |
13366 | index32 = att_index32; |
12430 | names_mask = att_names_mask; |
13367 | names_mask = att_names_mask; |
12431 | index16 = att_index16; |
13368 | index16 = att_index16; |
12432 | open_char = '('; |
13369 | open_char = '('; |
12433 | close_char = ')'; |
13370 | close_char = ')'; |
12434 | separator_char = ','; |
13371 | separator_char = ','; |
12435 | scale_char = ','; |
13372 | scale_char = ','; |
12436 | } |
13373 | } |
12437 | 13374 | ||
12438 | /* The output looks better if we put 7 bytes on a line, since that |
13375 | /* The output looks better if we put 7 bytes on a line, since that |
12439 | puts most long word instructions on a single line. Use 8 bytes |
13376 | puts most long word instructions on a single line. Use 8 bytes |
12440 | for Intel L1OM. */ |
13377 | for Intel L1OM. */ |
12441 | if ((info->mach & bfd_mach_l1om) != 0) |
13378 | if ((info->mach & bfd_mach_l1om) != 0) |
12442 | info->bytes_per_line = 8; |
13379 | info->bytes_per_line = 8; |
12443 | else |
13380 | else |
12444 | info->bytes_per_line = 7; |
13381 | info->bytes_per_line = 7; |
12445 | 13382 | ||
12446 | info->private_data = &priv; |
13383 | info->private_data = &priv; |
12447 | priv.max_fetched = priv.the_buffer; |
13384 | priv.max_fetched = priv.the_buffer; |
12448 | priv.insn_start = pc; |
13385 | priv.insn_start = pc; |
12449 | 13386 | ||
12450 | obuf[0] = 0; |
13387 | obuf[0] = 0; |
12451 | for (i = 0; i < MAX_OPERANDS; ++i) |
13388 | for (i = 0; i < MAX_OPERANDS; ++i) |
12452 | { |
13389 | { |
12453 | op_out[i][0] = 0; |
13390 | op_out[i][0] = 0; |
12454 | op_index[i] = -1; |
13391 | op_index[i] = -1; |
12455 | } |
13392 | } |
12456 | 13393 | ||
12457 | the_info = info; |
13394 | the_info = info; |
12458 | start_pc = pc; |
13395 | start_pc = pc; |
12459 | start_codep = priv.the_buffer; |
13396 | start_codep = priv.the_buffer; |
12460 | codep = priv.the_buffer; |
13397 | codep = priv.the_buffer; |
12461 | 13398 | ||
12462 | if (setjmp (priv.bailout) != 0) |
13399 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
12463 | { |
13400 | { |
12464 | const char *name; |
13401 | const char *name; |
12465 | 13402 | ||
12466 | /* Getting here means we tried for data but didn't get it. That |
13403 | /* Getting here means we tried for data but didn't get it. That |
12467 | means we have an incomplete instruction of some sort. Just |
13404 | means we have an incomplete instruction of some sort. Just |
12468 | print the first byte as a prefix or a .byte pseudo-op. */ |
13405 | print the first byte as a prefix or a .byte pseudo-op. */ |
12469 | if (codep > priv.the_buffer) |
13406 | if (codep > priv.the_buffer) |
12470 | { |
13407 | { |
12471 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
13408 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
12472 | if (name != NULL) |
13409 | if (name != NULL) |
12473 | (*info->fprintf_func) (info->stream, "%s", name); |
13410 | (*info->fprintf_func) (info->stream, "%s", name); |
12474 | else |
13411 | else |
12475 | { |
13412 | { |
12476 | /* Just print the first byte as a .byte instruction. */ |
13413 | /* Just print the first byte as a .byte instruction. */ |
12477 | (*info->fprintf_func) (info->stream, ".byte 0x%x", |
13414 | (*info->fprintf_func) (info->stream, ".byte 0x%x", |
12478 | (unsigned int) priv.the_buffer[0]); |
13415 | (unsigned int) priv.the_buffer[0]); |
12479 | } |
13416 | } |
12480 | 13417 | ||
12481 | return 1; |
13418 | return 1; |
12482 | } |
13419 | } |
12483 | 13420 | ||
12484 | return -1; |
13421 | return -1; |
12485 | } |
13422 | } |
12486 | 13423 | ||
12487 | obufp = obuf; |
13424 | obufp = obuf; |
12488 | sizeflag = priv.orig_sizeflag; |
13425 | sizeflag = priv.orig_sizeflag; |
12489 | 13426 | ||
12490 | if (!ckprefix () || rex_used) |
13427 | if (!ckprefix () || rex_used) |
12491 | { |
13428 | { |
12492 | /* Too many prefixes or unused REX prefixes. */ |
13429 | /* Too many prefixes or unused REX prefixes. */ |
12493 | for (i = 0; |
13430 | for (i = 0; |
12494 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
13431 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
12495 | i++) |
13432 | i++) |
12496 | (*info->fprintf_func) (info->stream, "%s%s", |
13433 | (*info->fprintf_func) (info->stream, "%s%s", |
12497 | i == 0 ? "" : " ", |
13434 | i == 0 ? "" : " ", |
12498 | prefix_name (all_prefixes[i], sizeflag)); |
13435 | prefix_name (all_prefixes[i], sizeflag)); |
12499 | return i; |
13436 | return i; |
12500 | } |
13437 | } |
12501 | 13438 | ||
12502 | insn_codep = codep; |
13439 | insn_codep = codep; |
12503 | 13440 | ||
12504 | FETCH_DATA (info, codep + 1); |
13441 | FETCH_DATA (info, codep + 1); |
12505 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); |
13442 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); |
12506 | 13443 | ||
12507 | if (((prefixes & PREFIX_FWAIT) |
13444 | if (((prefixes & PREFIX_FWAIT) |
12508 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
13445 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
12509 | { |
13446 | { |
- | 13447 | /* Handle prefixes before fwait. */ |
|
- | 13448 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
|
- | 13449 | i++) |
|
- | 13450 | (*info->fprintf_func) (info->stream, "%s ", |
|
- | 13451 | prefix_name (all_prefixes[i], sizeflag)); |
|
12510 | (*info->fprintf_func) (info->stream, "fwait"); |
13452 | (*info->fprintf_func) (info->stream, "fwait"); |
12511 | return 1; |
13453 | return i + 1; |
12512 | } |
13454 | } |
12513 | 13455 | ||
12514 | if (*codep == 0x0f) |
13456 | if (*codep == 0x0f) |
12515 | { |
13457 | { |
12516 | unsigned char threebyte; |
13458 | unsigned char threebyte; |
- | 13459 | ||
- | 13460 | codep++; |
|
12517 | FETCH_DATA (info, codep + 2); |
13461 | FETCH_DATA (info, codep + 1); |
12518 | threebyte = *++codep; |
13462 | threebyte = *codep; |
12519 | dp = &dis386_twobyte[threebyte]; |
13463 | dp = &dis386_twobyte[threebyte]; |
12520 | need_modrm = twobyte_has_modrm[*codep]; |
13464 | need_modrm = twobyte_has_modrm[*codep]; |
12521 | codep++; |
13465 | codep++; |
12522 | } |
13466 | } |
12523 | else |
13467 | else |
12524 | { |
13468 | { |
12525 | dp = &dis386[*codep]; |
13469 | dp = &dis386[*codep]; |
12526 | need_modrm = onebyte_has_modrm[*codep]; |
13470 | need_modrm = onebyte_has_modrm[*codep]; |
12527 | codep++; |
13471 | codep++; |
12528 | } |
13472 | } |
12529 | 13473 | ||
12530 | if ((prefixes & PREFIX_REPZ)) |
13474 | /* Save sizeflag for printing the extra prefixes later before updating |
12531 | used_prefixes |= PREFIX_REPZ; |
- | |
12532 | if ((prefixes & PREFIX_REPNZ)) |
13475 | it for mnemonic and operand processing. The prefix names depend |
12533 | used_prefixes |= PREFIX_REPNZ; |
- | |
12534 | if ((prefixes & PREFIX_LOCK)) |
13476 | only on the address mode. */ |
12535 | used_prefixes |= PREFIX_LOCK; |
- | |
12536 | - | ||
12537 | default_prefixes = 0; |
13477 | orig_sizeflag = sizeflag; |
12538 | if (prefixes & PREFIX_ADDR) |
- | |
12539 | { |
13478 | if (prefixes & PREFIX_ADDR) |
12540 | sizeflag ^= AFLAG; |
- | |
12541 | if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) |
- | |
12542 | { |
- | |
12543 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
- | |
12544 | all_prefixes[last_addr_prefix] = ADDR32_PREFIX; |
- | |
12545 | else |
- | |
12546 | all_prefixes[last_addr_prefix] = ADDR16_PREFIX; |
- | |
12547 | default_prefixes |= PREFIX_ADDR; |
- | |
12548 | } |
- | |
12549 | } |
- | |
12550 | 13479 | sizeflag ^= AFLAG; |
|
12551 | if ((prefixes & PREFIX_DATA)) |
- | |
12552 | { |
13480 | if ((prefixes & PREFIX_DATA)) |
12553 | sizeflag ^= DFLAG; |
- | |
12554 | if (dp->op[2].bytemode == cond_jump_mode |
- | |
12555 | && dp->op[0].bytemode == v_mode |
- | |
12556 | && !intel_syntax) |
- | |
12557 | { |
- | |
12558 | if (sizeflag & DFLAG) |
- | |
12559 | all_prefixes[last_data_prefix] = DATA32_PREFIX; |
- | |
12560 | else |
- | |
12561 | all_prefixes[last_data_prefix] = DATA16_PREFIX; |
- | |
12562 | default_prefixes |= PREFIX_DATA; |
- | |
12563 | } |
- | |
12564 | else if (rex & REX_W) |
- | |
12565 | { |
- | |
12566 | /* REX_W will override PREFIX_DATA. */ |
- | |
12567 | default_prefixes |= PREFIX_DATA; |
- | |
12568 | } |
- | |
- | 13481 | sizeflag ^= DFLAG; |
|
12569 | } |
13482 | |
12570 | 13483 | end_codep = codep; |
|
12571 | if (need_modrm) |
13484 | if (need_modrm) |
12572 | { |
13485 | { |
12573 | FETCH_DATA (info, codep + 1); |
13486 | FETCH_DATA (info, codep + 1); |
12574 | modrm.mod = (*codep >> 6) & 3; |
13487 | modrm.mod = (*codep >> 6) & 3; |
12575 | modrm.reg = (*codep >> 3) & 7; |
13488 | modrm.reg = (*codep >> 3) & 7; |
12576 | modrm.rm = *codep & 7; |
13489 | modrm.rm = *codep & 7; |
12577 | } |
13490 | } |
12578 | 13491 | ||
12579 | need_vex = 0; |
13492 | need_vex = 0; |
12580 | need_vex_reg = 0; |
13493 | need_vex_reg = 0; |
12581 | vex_w_done = 0; |
13494 | vex_w_done = 0; |
12582 | vex.evex = 0; |
13495 | vex.evex = 0; |
12583 | 13496 | ||
12584 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
13497 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
12585 | { |
13498 | { |
12586 | get_sib (info, sizeflag); |
13499 | get_sib (info, sizeflag); |
12587 | dofloat (sizeflag); |
13500 | dofloat (sizeflag); |
12588 | } |
13501 | } |
12589 | else |
13502 | else |
12590 | { |
13503 | { |
12591 | dp = get_valid_dis386 (dp, info); |
13504 | dp = get_valid_dis386 (dp, info); |
12592 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
13505 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
12593 | { |
13506 | { |
12594 | get_sib (info, sizeflag); |
13507 | get_sib (info, sizeflag); |
12595 | for (i = 0; i < MAX_OPERANDS; ++i) |
13508 | for (i = 0; i < MAX_OPERANDS; ++i) |
12596 | { |
13509 | { |
12597 | obufp = op_out[i]; |
13510 | obufp = op_out[i]; |
12598 | op_ad = MAX_OPERANDS - 1 - i; |
13511 | op_ad = MAX_OPERANDS - 1 - i; |
12599 | if (dp->op[i].rtn) |
13512 | if (dp->op[i].rtn) |
12600 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); |
13513 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); |
12601 | /* For EVEX instruction after the last operand masking |
13514 | /* For EVEX instruction after the last operand masking |
12602 | should be printed. */ |
13515 | should be printed. */ |
12603 | if (i == 0 && vex.evex) |
13516 | if (i == 0 && vex.evex) |
12604 | { |
13517 | { |
12605 | /* Don't print {%k0}. */ |
13518 | /* Don't print {%k0}. */ |
12606 | if (vex.mask_register_specifier) |
13519 | if (vex.mask_register_specifier) |
12607 | { |
13520 | { |
12608 | oappend ("{"); |
13521 | oappend ("{"); |
12609 | oappend (names_mask[vex.mask_register_specifier]); |
13522 | oappend (names_mask[vex.mask_register_specifier]); |
12610 | oappend ("}"); |
13523 | oappend ("}"); |
12611 | } |
13524 | } |
12612 | if (vex.zeroing) |
13525 | if (vex.zeroing) |
12613 | oappend ("{z}"); |
13526 | oappend ("{z}"); |
12614 | } |
13527 | } |
12615 | } |
13528 | } |
12616 | } |
13529 | } |
12617 | } |
13530 | } |
12618 | - | ||
12619 | /* See if any prefixes were not used. If so, print the first one |
- | |
12620 | separately. If we don't do this, we'll wind up printing an |
- | |
12621 | instruction stream which does not precisely correspond to the |
- | |
12622 | bytes we are disassembling. */ |
- | |
12623 | if ((prefixes & ~(used_prefixes | default_prefixes)) != 0) |
- | |
12624 | { |
- | |
12625 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
- | |
12626 | if (all_prefixes[i]) |
- | |
12627 | { |
- | |
12628 | const char *name; |
- | |
12629 | name = prefix_name (all_prefixes[i], priv.orig_sizeflag); |
- | |
12630 | if (name == NULL) |
- | |
12631 | name = INTERNAL_DISASSEMBLER_ERROR; |
- | |
12632 | (*info->fprintf_func) (info->stream, "%s", name); |
- | |
12633 | return 1; |
- | |
12634 | } |
- | |
12635 | } |
- | |
12636 | 13531 | ||
12637 | /* Check if the REX prefix is used. */ |
13532 | /* Check if the REX prefix is used. */ |
12638 | if (rex_ignored == 0 && (rex ^ rex_used) == 0) |
13533 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
12639 | all_prefixes[last_rex_prefix] = 0; |
13534 | all_prefixes[last_rex_prefix] = 0; |
12640 | 13535 | ||
12641 | /* Check if the SEG prefix is used. */ |
13536 | /* Check if the SEG prefix is used. */ |
12642 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
13537 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12643 | | PREFIX_FS | PREFIX_GS)) != 0 |
13538 | | PREFIX_FS | PREFIX_GS)) != 0 |
12644 | && (used_prefixes |
- | |
12645 | & seg_prefix (all_prefixes[last_seg_prefix])) != 0) |
13539 | && (used_prefixes & active_seg_prefix) != 0) |
12646 | all_prefixes[last_seg_prefix] = 0; |
13540 | all_prefixes[last_seg_prefix] = 0; |
12647 | 13541 | ||
12648 | /* Check if the ADDR prefix is used. */ |
13542 | /* Check if the ADDR prefix is used. */ |
12649 | if ((prefixes & PREFIX_ADDR) != 0 |
13543 | if ((prefixes & PREFIX_ADDR) != 0 |
12650 | && (used_prefixes & PREFIX_ADDR) != 0) |
13544 | && (used_prefixes & PREFIX_ADDR) != 0) |
12651 | all_prefixes[last_addr_prefix] = 0; |
13545 | all_prefixes[last_addr_prefix] = 0; |
12652 | 13546 | ||
12653 | /* Check if the DATA prefix is used. */ |
13547 | /* Check if the DATA prefix is used. */ |
12654 | if ((prefixes & PREFIX_DATA) != 0 |
13548 | if ((prefixes & PREFIX_DATA) != 0 |
12655 | && (used_prefixes & PREFIX_DATA) != 0) |
13549 | && (used_prefixes & PREFIX_DATA) != 0) |
12656 | all_prefixes[last_data_prefix] = 0; |
13550 | all_prefixes[last_data_prefix] = 0; |
- | 13551 | ||
12657 | 13552 | /* Print the extra prefixes. */ |
|
12658 | prefix_length = 0; |
13553 | prefix_length = 0; |
12659 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
13554 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12660 | if (all_prefixes[i]) |
13555 | if (all_prefixes[i]) |
12661 | { |
13556 | { |
12662 | const char *name; |
13557 | const char *name; |
12663 | name = prefix_name (all_prefixes[i], sizeflag); |
13558 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
12664 | if (name == NULL) |
13559 | if (name == NULL) |
12665 | abort (); |
13560 | abort (); |
12666 | prefix_length += strlen (name) + 1; |
13561 | prefix_length += strlen (name) + 1; |
12667 | (*info->fprintf_func) (info->stream, "%s ", name); |
13562 | (*info->fprintf_func) (info->stream, "%s ", name); |
12668 | } |
13563 | } |
- | 13564 | ||
- | 13565 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
|
- | 13566 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be |
|
- | 13567 | used by putop and MMX/SSE operand and may be overriden by the |
|
- | 13568 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix |
|
- | 13569 | separately. */ |
|
- | 13570 | if (dp->prefix_requirement == PREFIX_OPCODE |
|
- | 13571 | && dp != &bad_opcode |
|
- | 13572 | && (((prefixes |
|
- | 13573 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 |
|
- | 13574 | && (used_prefixes |
|
- | 13575 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) |
|
- | 13576 | || ((((prefixes |
|
- | 13577 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) |
|
- | 13578 | == PREFIX_DATA) |
|
- | 13579 | && (used_prefixes & PREFIX_DATA) == 0)))) |
|
- | 13580 | { |
|
- | 13581 | (*info->fprintf_func) (info->stream, "(bad)"); |
|
- | 13582 | return end_codep - priv.the_buffer; |
|
- | 13583 | } |
|
12669 | 13584 | ||
12670 | /* Check maximum code length. */ |
13585 | /* Check maximum code length. */ |
12671 | if ((codep - start_codep) > MAX_CODE_LENGTH) |
13586 | if ((codep - start_codep) > MAX_CODE_LENGTH) |
12672 | { |
13587 | { |
12673 | (*info->fprintf_func) (info->stream, "(bad)"); |
13588 | (*info->fprintf_func) (info->stream, "(bad)"); |
12674 | return MAX_CODE_LENGTH; |
13589 | return MAX_CODE_LENGTH; |
12675 | } |
13590 | } |
12676 | 13591 | ||
12677 | obufp = mnemonicendp; |
13592 | obufp = mnemonicendp; |
12678 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
13593 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
12679 | oappend (" "); |
13594 | oappend (" "); |
12680 | oappend (" "); |
13595 | oappend (" "); |
12681 | (*info->fprintf_func) (info->stream, "%s", obuf); |
13596 | (*info->fprintf_func) (info->stream, "%s", obuf); |
12682 | 13597 | ||
12683 | /* The enter and bound instructions are printed with operands in the same |
13598 | /* The enter and bound instructions are printed with operands in the same |
12684 | order as the intel book; everything else is printed in reverse order. */ |
13599 | order as the intel book; everything else is printed in reverse order. */ |
12685 | if (intel_syntax || two_source_ops) |
13600 | if (intel_syntax || two_source_ops) |
12686 | { |
13601 | { |
12687 | bfd_vma riprel; |
13602 | bfd_vma riprel; |
12688 | 13603 | ||
12689 | for (i = 0; i < MAX_OPERANDS; ++i) |
13604 | for (i = 0; i < MAX_OPERANDS; ++i) |
12690 | op_txt[i] = op_out[i]; |
13605 | op_txt[i] = op_out[i]; |
- | 13606 | ||
- | 13607 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
|
- | 13608 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) |
|
- | 13609 | { |
|
- | 13610 | op_txt[2] = op_out[3]; |
|
- | 13611 | op_txt[3] = op_out[2]; |
|
- | 13612 | } |
|
12691 | 13613 | ||
12692 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13614 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12693 | { |
13615 | { |
12694 | op_ad = op_index[i]; |
13616 | op_ad = op_index[i]; |
12695 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; |
13617 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; |
12696 | op_index[MAX_OPERANDS - 1 - i] = op_ad; |
13618 | op_index[MAX_OPERANDS - 1 - i] = op_ad; |
12697 | riprel = op_riprel[i]; |
13619 | riprel = op_riprel[i]; |
12698 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; |
13620 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; |
12699 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; |
13621 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; |
12700 | } |
13622 | } |
12701 | } |
13623 | } |
12702 | else |
13624 | else |
12703 | { |
13625 | { |
12704 | for (i = 0; i < MAX_OPERANDS; ++i) |
13626 | for (i = 0; i < MAX_OPERANDS; ++i) |
12705 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
13627 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
12706 | } |
13628 | } |
12707 | 13629 | ||
12708 | needcomma = 0; |
13630 | needcomma = 0; |
12709 | for (i = 0; i < MAX_OPERANDS; ++i) |
13631 | for (i = 0; i < MAX_OPERANDS; ++i) |
12710 | if (*op_txt[i]) |
13632 | if (*op_txt[i]) |
12711 | { |
13633 | { |
12712 | if (needcomma) |
13634 | if (needcomma) |
12713 | (*info->fprintf_func) (info->stream, ","); |
13635 | (*info->fprintf_func) (info->stream, ","); |
12714 | if (op_index[i] != -1 && !op_riprel[i]) |
13636 | if (op_index[i] != -1 && !op_riprel[i]) |
12715 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); |
13637 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); |
12716 | else |
13638 | else |
12717 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); |
13639 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); |
12718 | needcomma = 1; |
13640 | needcomma = 1; |
12719 | } |
13641 | } |
12720 | 13642 | ||
12721 | for (i = 0; i < MAX_OPERANDS; i++) |
13643 | for (i = 0; i < MAX_OPERANDS; i++) |
12722 | if (op_index[i] != -1 && op_riprel[i]) |
13644 | if (op_index[i] != -1 && op_riprel[i]) |
12723 | { |
13645 | { |
12724 | (*info->fprintf_func) (info->stream, " # "); |
13646 | (*info->fprintf_func) (info->stream, " # "); |
12725 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep |
13647 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep |
12726 | + op_address[op_index[i]]), info); |
13648 | + op_address[op_index[i]]), info); |
12727 | break; |
13649 | break; |
12728 | } |
13650 | } |
12729 | return codep - priv.the_buffer; |
13651 | return codep - priv.the_buffer; |
12730 | } |
13652 | } |
12731 | 13653 | ||
12732 | static const char *float_mem[] = { |
13654 | static const char *float_mem[] = { |
12733 | /* d8 */ |
13655 | /* d8 */ |
12734 | "fadd{s|}", |
13656 | "fadd{s|}", |
12735 | "fmul{s|}", |
13657 | "fmul{s|}", |
12736 | "fcom{s|}", |
13658 | "fcom{s|}", |
12737 | "fcomp{s|}", |
13659 | "fcomp{s|}", |
12738 | "fsub{s|}", |
13660 | "fsub{s|}", |
12739 | "fsubr{s|}", |
13661 | "fsubr{s|}", |
12740 | "fdiv{s|}", |
13662 | "fdiv{s|}", |
12741 | "fdivr{s|}", |
13663 | "fdivr{s|}", |
12742 | /* d9 */ |
13664 | /* d9 */ |
12743 | "fld{s|}", |
13665 | "fld{s|}", |
12744 | "(bad)", |
13666 | "(bad)", |
12745 | "fst{s|}", |
13667 | "fst{s|}", |
12746 | "fstp{s|}", |
13668 | "fstp{s|}", |
12747 | "fldenvIC", |
13669 | "fldenvIC", |
12748 | "fldcw", |
13670 | "fldcw", |
12749 | "fNstenvIC", |
13671 | "fNstenvIC", |
12750 | "fNstcw", |
13672 | "fNstcw", |
12751 | /* da */ |
13673 | /* da */ |
12752 | "fiadd{l|}", |
13674 | "fiadd{l|}", |
12753 | "fimul{l|}", |
13675 | "fimul{l|}", |
12754 | "ficom{l|}", |
13676 | "ficom{l|}", |
12755 | "ficomp{l|}", |
13677 | "ficomp{l|}", |
12756 | "fisub{l|}", |
13678 | "fisub{l|}", |
12757 | "fisubr{l|}", |
13679 | "fisubr{l|}", |
12758 | "fidiv{l|}", |
13680 | "fidiv{l|}", |
12759 | "fidivr{l|}", |
13681 | "fidivr{l|}", |
12760 | /* db */ |
13682 | /* db */ |
12761 | "fild{l|}", |
13683 | "fild{l|}", |
12762 | "fisttp{l|}", |
13684 | "fisttp{l|}", |
12763 | "fist{l|}", |
13685 | "fist{l|}", |
12764 | "fistp{l|}", |
13686 | "fistp{l|}", |
12765 | "(bad)", |
13687 | "(bad)", |
12766 | "fld{t||t|}", |
13688 | "fld{t||t|}", |
12767 | "(bad)", |
13689 | "(bad)", |
12768 | "fstp{t||t|}", |
13690 | "fstp{t||t|}", |
12769 | /* dc */ |
13691 | /* dc */ |
12770 | "fadd{l|}", |
13692 | "fadd{l|}", |
12771 | "fmul{l|}", |
13693 | "fmul{l|}", |
12772 | "fcom{l|}", |
13694 | "fcom{l|}", |
12773 | "fcomp{l|}", |
13695 | "fcomp{l|}", |
12774 | "fsub{l|}", |
13696 | "fsub{l|}", |
12775 | "fsubr{l|}", |
13697 | "fsubr{l|}", |
12776 | "fdiv{l|}", |
13698 | "fdiv{l|}", |
12777 | "fdivr{l|}", |
13699 | "fdivr{l|}", |
12778 | /* dd */ |
13700 | /* dd */ |
12779 | "fld{l|}", |
13701 | "fld{l|}", |
12780 | "fisttp{ll|}", |
13702 | "fisttp{ll|}", |
12781 | "fst{l||}", |
13703 | "fst{l||}", |
12782 | "fstp{l|}", |
13704 | "fstp{l|}", |
12783 | "frstorIC", |
13705 | "frstorIC", |
12784 | "(bad)", |
13706 | "(bad)", |
12785 | "fNsaveIC", |
13707 | "fNsaveIC", |
12786 | "fNstsw", |
13708 | "fNstsw", |
12787 | /* de */ |
13709 | /* de */ |
12788 | "fiadd", |
13710 | "fiadd", |
12789 | "fimul", |
13711 | "fimul", |
12790 | "ficom", |
13712 | "ficom", |
12791 | "ficomp", |
13713 | "ficomp", |
12792 | "fisub", |
13714 | "fisub", |
12793 | "fisubr", |
13715 | "fisubr", |
12794 | "fidiv", |
13716 | "fidiv", |
12795 | "fidivr", |
13717 | "fidivr", |
12796 | /* df */ |
13718 | /* df */ |
12797 | "fild", |
13719 | "fild", |
12798 | "fisttp", |
13720 | "fisttp", |
12799 | "fist", |
13721 | "fist", |
12800 | "fistp", |
13722 | "fistp", |
12801 | "fbld", |
13723 | "fbld", |
12802 | "fild{ll|}", |
13724 | "fild{ll|}", |
12803 | "fbstp", |
13725 | "fbstp", |
12804 | "fistp{ll|}", |
13726 | "fistp{ll|}", |
12805 | }; |
13727 | }; |
12806 | 13728 | ||
12807 | static const unsigned char float_mem_mode[] = { |
13729 | static const unsigned char float_mem_mode[] = { |
12808 | /* d8 */ |
13730 | /* d8 */ |
12809 | d_mode, |
13731 | d_mode, |
12810 | d_mode, |
13732 | d_mode, |
12811 | d_mode, |
13733 | d_mode, |
12812 | d_mode, |
13734 | d_mode, |
12813 | d_mode, |
13735 | d_mode, |
12814 | d_mode, |
13736 | d_mode, |
12815 | d_mode, |
13737 | d_mode, |
12816 | d_mode, |
13738 | d_mode, |
12817 | /* d9 */ |
13739 | /* d9 */ |
12818 | d_mode, |
13740 | d_mode, |
12819 | 0, |
13741 | 0, |
12820 | d_mode, |
13742 | d_mode, |
12821 | d_mode, |
13743 | d_mode, |
12822 | 0, |
13744 | 0, |
12823 | w_mode, |
13745 | w_mode, |
12824 | 0, |
13746 | 0, |
12825 | w_mode, |
13747 | w_mode, |
12826 | /* da */ |
13748 | /* da */ |
12827 | d_mode, |
13749 | d_mode, |
12828 | d_mode, |
13750 | d_mode, |
12829 | d_mode, |
13751 | d_mode, |
12830 | d_mode, |
13752 | d_mode, |
12831 | d_mode, |
13753 | d_mode, |
12832 | d_mode, |
13754 | d_mode, |
12833 | d_mode, |
13755 | d_mode, |
12834 | d_mode, |
13756 | d_mode, |
12835 | /* db */ |
13757 | /* db */ |
12836 | d_mode, |
13758 | d_mode, |
12837 | d_mode, |
13759 | d_mode, |
12838 | d_mode, |
13760 | d_mode, |
12839 | d_mode, |
13761 | d_mode, |
12840 | 0, |
13762 | 0, |
12841 | t_mode, |
13763 | t_mode, |
12842 | 0, |
13764 | 0, |
12843 | t_mode, |
13765 | t_mode, |
12844 | /* dc */ |
13766 | /* dc */ |
12845 | q_mode, |
13767 | q_mode, |
12846 | q_mode, |
13768 | q_mode, |
12847 | q_mode, |
13769 | q_mode, |
12848 | q_mode, |
13770 | q_mode, |
12849 | q_mode, |
13771 | q_mode, |
12850 | q_mode, |
13772 | q_mode, |
12851 | q_mode, |
13773 | q_mode, |
12852 | q_mode, |
13774 | q_mode, |
12853 | /* dd */ |
13775 | /* dd */ |
12854 | q_mode, |
13776 | q_mode, |
12855 | q_mode, |
13777 | q_mode, |
12856 | q_mode, |
13778 | q_mode, |
12857 | q_mode, |
13779 | q_mode, |
12858 | 0, |
13780 | 0, |
12859 | 0, |
13781 | 0, |
12860 | 0, |
13782 | 0, |
12861 | w_mode, |
13783 | w_mode, |
12862 | /* de */ |
13784 | /* de */ |
12863 | w_mode, |
13785 | w_mode, |
12864 | w_mode, |
13786 | w_mode, |
12865 | w_mode, |
13787 | w_mode, |
12866 | w_mode, |
13788 | w_mode, |
12867 | w_mode, |
13789 | w_mode, |
12868 | w_mode, |
13790 | w_mode, |
12869 | w_mode, |
13791 | w_mode, |
12870 | w_mode, |
13792 | w_mode, |
12871 | /* df */ |
13793 | /* df */ |
12872 | w_mode, |
13794 | w_mode, |
12873 | w_mode, |
13795 | w_mode, |
12874 | w_mode, |
13796 | w_mode, |
12875 | w_mode, |
13797 | w_mode, |
12876 | t_mode, |
13798 | t_mode, |
12877 | q_mode, |
13799 | q_mode, |
12878 | t_mode, |
13800 | t_mode, |
12879 | q_mode |
13801 | q_mode |
12880 | }; |
13802 | }; |
12881 | 13803 | ||
12882 | #define ST { OP_ST, 0 } |
13804 | #define ST { OP_ST, 0 } |
12883 | #define STi { OP_STi, 0 } |
13805 | #define STi { OP_STi, 0 } |
12884 | 13806 | ||
12885 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
13807 | #define FGRPd9_2 NULL, { { NULL, 0 } }, 0 |
12886 | #define FGRPd9_4 NULL, { { NULL, 1 } } |
13808 | #define FGRPd9_4 NULL, { { NULL, 1 } }, 0 |
12887 | #define FGRPd9_5 NULL, { { NULL, 2 } } |
13809 | #define FGRPd9_5 NULL, { { NULL, 2 } }, 0 |
12888 | #define FGRPd9_6 NULL, { { NULL, 3 } } |
13810 | #define FGRPd9_6 NULL, { { NULL, 3 } }, 0 |
12889 | #define FGRPd9_7 NULL, { { NULL, 4 } } |
13811 | #define FGRPd9_7 NULL, { { NULL, 4 } }, 0 |
12890 | #define FGRPda_5 NULL, { { NULL, 5 } } |
13812 | #define FGRPda_5 NULL, { { NULL, 5 } }, 0 |
12891 | #define FGRPdb_4 NULL, { { NULL, 6 } } |
13813 | #define FGRPdb_4 NULL, { { NULL, 6 } }, 0 |
12892 | #define FGRPde_3 NULL, { { NULL, 7 } } |
13814 | #define FGRPde_3 NULL, { { NULL, 7 } }, 0 |
12893 | #define FGRPdf_4 NULL, { { NULL, 8 } } |
13815 | #define FGRPdf_4 NULL, { { NULL, 8 } }, 0 |
12894 | 13816 | ||
12895 | static const struct dis386 float_reg[][8] = { |
13817 | static const struct dis386 float_reg[][8] = { |
12896 | /* d8 */ |
13818 | /* d8 */ |
12897 | { |
13819 | { |
12898 | { "fadd", { ST, STi } }, |
13820 | { "fadd", { ST, STi }, 0 }, |
12899 | { "fmul", { ST, STi } }, |
13821 | { "fmul", { ST, STi }, 0 }, |
12900 | { "fcom", { STi } }, |
13822 | { "fcom", { STi }, 0 }, |
12901 | { "fcomp", { STi } }, |
13823 | { "fcomp", { STi }, 0 }, |
12902 | { "fsub", { ST, STi } }, |
13824 | { "fsub", { ST, STi }, 0 }, |
12903 | { "fsubr", { ST, STi } }, |
13825 | { "fsubr", { ST, STi }, 0 }, |
12904 | { "fdiv", { ST, STi } }, |
13826 | { "fdiv", { ST, STi }, 0 }, |
12905 | { "fdivr", { ST, STi } }, |
13827 | { "fdivr", { ST, STi }, 0 }, |
12906 | }, |
13828 | }, |
12907 | /* d9 */ |
13829 | /* d9 */ |
12908 | { |
13830 | { |
12909 | { "fld", { STi } }, |
13831 | { "fld", { STi }, 0 }, |
12910 | { "fxch", { STi } }, |
13832 | { "fxch", { STi }, 0 }, |
12911 | { FGRPd9_2 }, |
13833 | { FGRPd9_2 }, |
12912 | { Bad_Opcode }, |
13834 | { Bad_Opcode }, |
12913 | { FGRPd9_4 }, |
13835 | { FGRPd9_4 }, |
12914 | { FGRPd9_5 }, |
13836 | { FGRPd9_5 }, |
12915 | { FGRPd9_6 }, |
13837 | { FGRPd9_6 }, |
12916 | { FGRPd9_7 }, |
13838 | { FGRPd9_7 }, |
12917 | }, |
13839 | }, |
12918 | /* da */ |
13840 | /* da */ |
12919 | { |
13841 | { |
12920 | { "fcmovb", { ST, STi } }, |
13842 | { "fcmovb", { ST, STi }, 0 }, |
12921 | { "fcmove", { ST, STi } }, |
13843 | { "fcmove", { ST, STi }, 0 }, |
12922 | { "fcmovbe",{ ST, STi } }, |
13844 | { "fcmovbe",{ ST, STi }, 0 }, |
12923 | { "fcmovu", { ST, STi } }, |
13845 | { "fcmovu", { ST, STi }, 0 }, |
12924 | { Bad_Opcode }, |
13846 | { Bad_Opcode }, |
12925 | { FGRPda_5 }, |
13847 | { FGRPda_5 }, |
12926 | { Bad_Opcode }, |
13848 | { Bad_Opcode }, |
12927 | { Bad_Opcode }, |
13849 | { Bad_Opcode }, |
12928 | }, |
13850 | }, |
12929 | /* db */ |
13851 | /* db */ |
12930 | { |
13852 | { |
12931 | { "fcmovnb",{ ST, STi } }, |
13853 | { "fcmovnb",{ ST, STi }, 0 }, |
12932 | { "fcmovne",{ ST, STi } }, |
13854 | { "fcmovne",{ ST, STi }, 0 }, |
12933 | { "fcmovnbe",{ ST, STi } }, |
13855 | { "fcmovnbe",{ ST, STi }, 0 }, |
12934 | { "fcmovnu",{ ST, STi } }, |
13856 | { "fcmovnu",{ ST, STi }, 0 }, |
12935 | { FGRPdb_4 }, |
13857 | { FGRPdb_4 }, |
12936 | { "fucomi", { ST, STi } }, |
13858 | { "fucomi", { ST, STi }, 0 }, |
12937 | { "fcomi", { ST, STi } }, |
13859 | { "fcomi", { ST, STi }, 0 }, |
12938 | { Bad_Opcode }, |
13860 | { Bad_Opcode }, |
12939 | }, |
13861 | }, |
12940 | /* dc */ |
13862 | /* dc */ |
12941 | { |
13863 | { |
12942 | { "fadd", { STi, ST } }, |
13864 | { "fadd", { STi, ST }, 0 }, |
12943 | { "fmul", { STi, ST } }, |
13865 | { "fmul", { STi, ST }, 0 }, |
12944 | { Bad_Opcode }, |
13866 | { Bad_Opcode }, |
12945 | { Bad_Opcode }, |
13867 | { Bad_Opcode }, |
12946 | { "fsub!M", { STi, ST } }, |
13868 | { "fsub!M", { STi, ST }, 0 }, |
12947 | { "fsubM", { STi, ST } }, |
13869 | { "fsubM", { STi, ST }, 0 }, |
12948 | { "fdiv!M", { STi, ST } }, |
13870 | { "fdiv!M", { STi, ST }, 0 }, |
12949 | { "fdivM", { STi, ST } }, |
13871 | { "fdivM", { STi, ST }, 0 }, |
12950 | }, |
13872 | }, |
12951 | /* dd */ |
13873 | /* dd */ |
12952 | { |
13874 | { |
12953 | { "ffree", { STi } }, |
13875 | { "ffree", { STi }, 0 }, |
12954 | { Bad_Opcode }, |
13876 | { Bad_Opcode }, |
12955 | { "fst", { STi } }, |
13877 | { "fst", { STi }, 0 }, |
12956 | { "fstp", { STi } }, |
13878 | { "fstp", { STi }, 0 }, |
12957 | { "fucom", { STi } }, |
13879 | { "fucom", { STi }, 0 }, |
12958 | { "fucomp", { STi } }, |
13880 | { "fucomp", { STi }, 0 }, |
12959 | { Bad_Opcode }, |
13881 | { Bad_Opcode }, |
12960 | { Bad_Opcode }, |
13882 | { Bad_Opcode }, |
12961 | }, |
13883 | }, |
12962 | /* de */ |
13884 | /* de */ |
12963 | { |
13885 | { |
12964 | { "faddp", { STi, ST } }, |
13886 | { "faddp", { STi, ST }, 0 }, |
12965 | { "fmulp", { STi, ST } }, |
13887 | { "fmulp", { STi, ST }, 0 }, |
12966 | { Bad_Opcode }, |
13888 | { Bad_Opcode }, |
12967 | { FGRPde_3 }, |
13889 | { FGRPde_3 }, |
12968 | { "fsub!Mp", { STi, ST } }, |
13890 | { "fsub!Mp", { STi, ST }, 0 }, |
12969 | { "fsubMp", { STi, ST } }, |
13891 | { "fsubMp", { STi, ST }, 0 }, |
12970 | { "fdiv!Mp", { STi, ST } }, |
13892 | { "fdiv!Mp", { STi, ST }, 0 }, |
12971 | { "fdivMp", { STi, ST } }, |
13893 | { "fdivMp", { STi, ST }, 0 }, |
12972 | }, |
13894 | }, |
12973 | /* df */ |
13895 | /* df */ |
12974 | { |
13896 | { |
12975 | { "ffreep", { STi } }, |
13897 | { "ffreep", { STi }, 0 }, |
12976 | { Bad_Opcode }, |
13898 | { Bad_Opcode }, |
12977 | { Bad_Opcode }, |
13899 | { Bad_Opcode }, |
12978 | { Bad_Opcode }, |
13900 | { Bad_Opcode }, |
12979 | { FGRPdf_4 }, |
13901 | { FGRPdf_4 }, |
12980 | { "fucomip", { ST, STi } }, |
13902 | { "fucomip", { ST, STi }, 0 }, |
12981 | { "fcomip", { ST, STi } }, |
13903 | { "fcomip", { ST, STi }, 0 }, |
12982 | { Bad_Opcode }, |
13904 | { Bad_Opcode }, |
12983 | }, |
13905 | }, |
12984 | }; |
13906 | }; |
12985 | 13907 | ||
12986 | static char *fgrps[][8] = { |
13908 | static char *fgrps[][8] = { |
12987 | /* d9_2 0 */ |
13909 | /* d9_2 0 */ |
12988 | { |
13910 | { |
12989 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
13911 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
12990 | }, |
13912 | }, |
12991 | 13913 | ||
12992 | /* d9_4 1 */ |
13914 | /* d9_4 1 */ |
12993 | { |
13915 | { |
12994 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", |
13916 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", |
12995 | }, |
13917 | }, |
12996 | 13918 | ||
12997 | /* d9_5 2 */ |
13919 | /* d9_5 2 */ |
12998 | { |
13920 | { |
12999 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", |
13921 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", |
13000 | }, |
13922 | }, |
13001 | 13923 | ||
13002 | /* d9_6 3 */ |
13924 | /* d9_6 3 */ |
13003 | { |
13925 | { |
13004 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", |
13926 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", |
13005 | }, |
13927 | }, |
13006 | 13928 | ||
13007 | /* d9_7 4 */ |
13929 | /* d9_7 4 */ |
13008 | { |
13930 | { |
13009 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", |
13931 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", |
13010 | }, |
13932 | }, |
13011 | 13933 | ||
13012 | /* da_5 5 */ |
13934 | /* da_5 5 */ |
13013 | { |
13935 | { |
13014 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
13936 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
13015 | }, |
13937 | }, |
13016 | 13938 | ||
13017 | /* db_4 6 */ |
13939 | /* db_4 6 */ |
13018 | { |
13940 | { |
13019 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13941 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13020 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", |
13942 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", |
13021 | }, |
13943 | }, |
13022 | 13944 | ||
13023 | /* de_3 7 */ |
13945 | /* de_3 7 */ |
13024 | { |
13946 | { |
13025 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
13947 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
13026 | }, |
13948 | }, |
13027 | 13949 | ||
13028 | /* df_4 8 */ |
13950 | /* df_4 8 */ |
13029 | { |
13951 | { |
13030 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
13952 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
13031 | }, |
13953 | }, |
13032 | }; |
13954 | }; |
13033 | 13955 | ||
13034 | static void |
13956 | static void |
13035 | swap_operand (void) |
13957 | swap_operand (void) |
13036 | { |
13958 | { |
13037 | mnemonicendp[0] = '.'; |
13959 | mnemonicendp[0] = '.'; |
13038 | mnemonicendp[1] = 's'; |
13960 | mnemonicendp[1] = 's'; |
13039 | mnemonicendp += 2; |
13961 | mnemonicendp += 2; |
13040 | } |
13962 | } |
13041 | 13963 | ||
13042 | static void |
13964 | static void |
13043 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, |
13965 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, |
13044 | int sizeflag ATTRIBUTE_UNUSED) |
13966 | int sizeflag ATTRIBUTE_UNUSED) |
13045 | { |
13967 | { |
13046 | /* Skip mod/rm byte. */ |
13968 | /* Skip mod/rm byte. */ |
13047 | MODRM_CHECK; |
13969 | MODRM_CHECK; |
13048 | codep++; |
13970 | codep++; |
13049 | } |
13971 | } |
13050 | 13972 | ||
13051 | static void |
13973 | static void |
13052 | dofloat (int sizeflag) |
13974 | dofloat (int sizeflag) |
13053 | { |
13975 | { |
13054 | const struct dis386 *dp; |
13976 | const struct dis386 *dp; |
13055 | unsigned char floatop; |
13977 | unsigned char floatop; |
13056 | 13978 | ||
13057 | floatop = codep[-1]; |
13979 | floatop = codep[-1]; |
13058 | 13980 | ||
13059 | if (modrm.mod != 3) |
13981 | if (modrm.mod != 3) |
13060 | { |
13982 | { |
13061 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
13983 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
13062 | 13984 | ||
13063 | putop (float_mem[fp_indx], sizeflag); |
13985 | putop (float_mem[fp_indx], sizeflag); |
13064 | obufp = op_out[0]; |
13986 | obufp = op_out[0]; |
13065 | op_ad = 2; |
13987 | op_ad = 2; |
13066 | OP_E (float_mem_mode[fp_indx], sizeflag); |
13988 | OP_E (float_mem_mode[fp_indx], sizeflag); |
13067 | return; |
13989 | return; |
13068 | } |
13990 | } |
13069 | /* Skip mod/rm byte. */ |
13991 | /* Skip mod/rm byte. */ |
13070 | MODRM_CHECK; |
13992 | MODRM_CHECK; |
13071 | codep++; |
13993 | codep++; |
13072 | 13994 | ||
13073 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
13995 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
13074 | if (dp->name == NULL) |
13996 | if (dp->name == NULL) |
13075 | { |
13997 | { |
13076 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
13998 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
13077 | 13999 | ||
13078 | /* Instruction fnstsw is only one with strange arg. */ |
14000 | /* Instruction fnstsw is only one with strange arg. */ |
13079 | if (floatop == 0xdf && codep[-1] == 0xe0) |
14001 | if (floatop == 0xdf && codep[-1] == 0xe0) |
13080 | strcpy (op_out[0], names16[0]); |
14002 | strcpy (op_out[0], names16[0]); |
13081 | } |
14003 | } |
13082 | else |
14004 | else |
13083 | { |
14005 | { |
13084 | putop (dp->name, sizeflag); |
14006 | putop (dp->name, sizeflag); |
13085 | 14007 | ||
13086 | obufp = op_out[0]; |
14008 | obufp = op_out[0]; |
13087 | op_ad = 2; |
14009 | op_ad = 2; |
13088 | if (dp->op[0].rtn) |
14010 | if (dp->op[0].rtn) |
13089 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); |
14011 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); |
13090 | 14012 | ||
13091 | obufp = op_out[1]; |
14013 | obufp = op_out[1]; |
13092 | op_ad = 1; |
14014 | op_ad = 1; |
13093 | if (dp->op[1].rtn) |
14015 | if (dp->op[1].rtn) |
13094 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); |
14016 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); |
13095 | } |
14017 | } |
13096 | } |
14018 | } |
13097 | 14019 | ||
13098 | /* Like oappend (below), but S is a string starting with '%'. |
14020 | /* Like oappend (below), but S is a string starting with '%'. |
13099 | In Intel syntax, the '%' is elided. */ |
14021 | In Intel syntax, the '%' is elided. */ |
13100 | static void |
14022 | static void |
13101 | oappend_maybe_intel (const char *s) |
14023 | oappend_maybe_intel (const char *s) |
13102 | { |
14024 | { |
13103 | oappend (s + intel_syntax); |
14025 | oappend (s + intel_syntax); |
13104 | } |
14026 | } |
13105 | 14027 | ||
13106 | static void |
14028 | static void |
13107 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
14029 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
13108 | { |
14030 | { |
13109 | oappend_maybe_intel ("%st"); |
14031 | oappend_maybe_intel ("%st"); |
13110 | } |
14032 | } |
13111 | 14033 | ||
13112 | static void |
14034 | static void |
13113 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
14035 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
13114 | { |
14036 | { |
13115 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
14037 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
13116 | oappend_maybe_intel (scratchbuf); |
14038 | oappend_maybe_intel (scratchbuf); |
13117 | } |
14039 | } |
13118 | 14040 | ||
13119 | /* Capital letters in template are macros. */ |
14041 | /* Capital letters in template are macros. */ |
13120 | static int |
14042 | static int |
13121 | putop (const char *in_template, int sizeflag) |
14043 | putop (const char *in_template, int sizeflag) |
13122 | { |
14044 | { |
13123 | const char *p; |
14045 | const char *p; |
13124 | int alt = 0; |
14046 | int alt = 0; |
13125 | int cond = 1; |
14047 | int cond = 1; |
13126 | unsigned int l = 0, len = 1; |
14048 | unsigned int l = 0, len = 1; |
13127 | char last[4]; |
14049 | char last[4]; |
13128 | 14050 | ||
13129 | #define SAVE_LAST(c) \ |
14051 | #define SAVE_LAST(c) \ |
13130 | if (l < len && l < sizeof (last)) \ |
14052 | if (l < len && l < sizeof (last)) \ |
13131 | last[l++] = c; \ |
14053 | last[l++] = c; \ |
13132 | else \ |
14054 | else \ |
13133 | abort (); |
14055 | abort (); |
13134 | 14056 | ||
13135 | for (p = in_template; *p; p++) |
14057 | for (p = in_template; *p; p++) |
13136 | { |
14058 | { |
13137 | switch (*p) |
14059 | switch (*p) |
13138 | { |
14060 | { |
13139 | default: |
14061 | default: |
13140 | *obufp++ = *p; |
14062 | *obufp++ = *p; |
13141 | break; |
14063 | break; |
13142 | case '%': |
14064 | case '%': |
13143 | len++; |
14065 | len++; |
13144 | break; |
14066 | break; |
13145 | case '!': |
14067 | case '!': |
13146 | cond = 0; |
14068 | cond = 0; |
13147 | break; |
14069 | break; |
13148 | case '{': |
14070 | case '{': |
13149 | alt = 0; |
14071 | alt = 0; |
13150 | if (intel_syntax) |
14072 | if (intel_syntax) |
13151 | { |
14073 | { |
13152 | while (*++p != '|') |
14074 | while (*++p != '|') |
13153 | if (*p == '}' || *p == '\0') |
14075 | if (*p == '}' || *p == '\0') |
13154 | abort (); |
14076 | abort (); |
13155 | } |
14077 | } |
13156 | /* Fall through. */ |
14078 | /* Fall through. */ |
13157 | case 'I': |
14079 | case 'I': |
13158 | alt = 1; |
14080 | alt = 1; |
13159 | continue; |
14081 | continue; |
13160 | case '|': |
14082 | case '|': |
13161 | while (*++p != '}') |
14083 | while (*++p != '}') |
13162 | { |
14084 | { |
13163 | if (*p == '\0') |
14085 | if (*p == '\0') |
13164 | abort (); |
14086 | abort (); |
13165 | } |
14087 | } |
13166 | break; |
14088 | break; |
13167 | case '}': |
14089 | case '}': |
13168 | break; |
14090 | break; |
13169 | case 'A': |
14091 | case 'A': |
13170 | if (intel_syntax) |
14092 | if (intel_syntax) |
13171 | break; |
14093 | break; |
13172 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
14094 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
13173 | *obufp++ = 'b'; |
14095 | *obufp++ = 'b'; |
13174 | break; |
14096 | break; |
13175 | case 'B': |
14097 | case 'B': |
13176 | if (l == 0 && len == 1) |
14098 | if (l == 0 && len == 1) |
13177 | { |
14099 | { |
13178 | case_B: |
14100 | case_B: |
13179 | if (intel_syntax) |
14101 | if (intel_syntax) |
13180 | break; |
14102 | break; |
13181 | if (sizeflag & SUFFIX_ALWAYS) |
14103 | if (sizeflag & SUFFIX_ALWAYS) |
13182 | *obufp++ = 'b'; |
14104 | *obufp++ = 'b'; |
13183 | } |
14105 | } |
13184 | else |
14106 | else |
13185 | { |
14107 | { |
13186 | if (l != 1 |
14108 | if (l != 1 |
13187 | || len != 2 |
14109 | || len != 2 |
13188 | || last[0] != 'L') |
14110 | || last[0] != 'L') |
13189 | { |
14111 | { |
13190 | SAVE_LAST (*p); |
14112 | SAVE_LAST (*p); |
13191 | break; |
14113 | break; |
13192 | } |
14114 | } |
13193 | 14115 | ||
13194 | if (address_mode == mode_64bit |
14116 | if (address_mode == mode_64bit |
13195 | && !(prefixes & PREFIX_ADDR)) |
14117 | && !(prefixes & PREFIX_ADDR)) |
13196 | { |
14118 | { |
13197 | *obufp++ = 'a'; |
14119 | *obufp++ = 'a'; |
13198 | *obufp++ = 'b'; |
14120 | *obufp++ = 'b'; |
13199 | *obufp++ = 's'; |
14121 | *obufp++ = 's'; |
13200 | } |
14122 | } |
13201 | 14123 | ||
13202 | goto case_B; |
14124 | goto case_B; |
13203 | } |
14125 | } |
13204 | break; |
14126 | break; |
13205 | case 'C': |
14127 | case 'C': |
13206 | if (intel_syntax && !alt) |
14128 | if (intel_syntax && !alt) |
13207 | break; |
14129 | break; |
13208 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
14130 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
13209 | { |
14131 | { |
13210 | if (sizeflag & DFLAG) |
14132 | if (sizeflag & DFLAG) |
13211 | *obufp++ = intel_syntax ? 'd' : 'l'; |
14133 | *obufp++ = intel_syntax ? 'd' : 'l'; |
13212 | else |
14134 | else |
13213 | *obufp++ = intel_syntax ? 'w' : 's'; |
14135 | *obufp++ = intel_syntax ? 'w' : 's'; |
13214 | used_prefixes |= (prefixes & PREFIX_DATA); |
14136 | used_prefixes |= (prefixes & PREFIX_DATA); |
13215 | } |
14137 | } |
13216 | break; |
14138 | break; |
13217 | case 'D': |
14139 | case 'D': |
13218 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
14140 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
13219 | break; |
14141 | break; |
13220 | USED_REX (REX_W); |
14142 | USED_REX (REX_W); |
13221 | if (modrm.mod == 3) |
14143 | if (modrm.mod == 3) |
13222 | { |
14144 | { |
13223 | if (rex & REX_W) |
14145 | if (rex & REX_W) |
13224 | *obufp++ = 'q'; |
14146 | *obufp++ = 'q'; |
13225 | else |
14147 | else |
13226 | { |
14148 | { |
13227 | if (sizeflag & DFLAG) |
14149 | if (sizeflag & DFLAG) |
13228 | *obufp++ = intel_syntax ? 'd' : 'l'; |
14150 | *obufp++ = intel_syntax ? 'd' : 'l'; |
13229 | else |
14151 | else |
13230 | *obufp++ = 'w'; |
14152 | *obufp++ = 'w'; |
13231 | used_prefixes |= (prefixes & PREFIX_DATA); |
14153 | used_prefixes |= (prefixes & PREFIX_DATA); |
13232 | } |
14154 | } |
13233 | } |
14155 | } |
13234 | else |
14156 | else |
13235 | *obufp++ = 'w'; |
14157 | *obufp++ = 'w'; |
13236 | break; |
14158 | break; |
13237 | case 'E': /* For jcxz/jecxz */ |
14159 | case 'E': /* For jcxz/jecxz */ |
13238 | if (address_mode == mode_64bit) |
14160 | if (address_mode == mode_64bit) |
13239 | { |
14161 | { |
13240 | if (sizeflag & AFLAG) |
14162 | if (sizeflag & AFLAG) |
13241 | *obufp++ = 'r'; |
14163 | *obufp++ = 'r'; |
13242 | else |
14164 | else |
13243 | *obufp++ = 'e'; |
14165 | *obufp++ = 'e'; |
13244 | } |
14166 | } |
13245 | else |
14167 | else |
13246 | if (sizeflag & AFLAG) |
14168 | if (sizeflag & AFLAG) |
13247 | *obufp++ = 'e'; |
14169 | *obufp++ = 'e'; |
13248 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14170 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13249 | break; |
14171 | break; |
13250 | case 'F': |
14172 | case 'F': |
13251 | if (intel_syntax) |
14173 | if (intel_syntax) |
13252 | break; |
14174 | break; |
13253 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
14175 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
13254 | { |
14176 | { |
13255 | if (sizeflag & AFLAG) |
14177 | if (sizeflag & AFLAG) |
13256 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
14178 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
13257 | else |
14179 | else |
13258 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
14180 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
13259 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14181 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13260 | } |
14182 | } |
13261 | break; |
14183 | break; |
13262 | case 'G': |
14184 | case 'G': |
13263 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) |
14185 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) |
13264 | break; |
14186 | break; |
13265 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
14187 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
13266 | *obufp++ = 'l'; |
14188 | *obufp++ = 'l'; |
13267 | else |
14189 | else |
13268 | *obufp++ = 'w'; |
14190 | *obufp++ = 'w'; |
13269 | if (!(rex & REX_W)) |
14191 | if (!(rex & REX_W)) |
13270 | used_prefixes |= (prefixes & PREFIX_DATA); |
14192 | used_prefixes |= (prefixes & PREFIX_DATA); |
13271 | break; |
14193 | break; |
13272 | case 'H': |
14194 | case 'H': |
13273 | if (intel_syntax) |
14195 | if (intel_syntax) |
13274 | break; |
14196 | break; |
13275 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
14197 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
13276 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) |
14198 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) |
13277 | { |
14199 | { |
13278 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); |
14200 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); |
13279 | *obufp++ = ','; |
14201 | *obufp++ = ','; |
13280 | *obufp++ = 'p'; |
14202 | *obufp++ = 'p'; |
13281 | if (prefixes & PREFIX_DS) |
14203 | if (prefixes & PREFIX_DS) |
13282 | *obufp++ = 't'; |
14204 | *obufp++ = 't'; |
13283 | else |
14205 | else |
13284 | *obufp++ = 'n'; |
14206 | *obufp++ = 'n'; |
13285 | } |
14207 | } |
13286 | break; |
14208 | break; |
13287 | case 'J': |
14209 | case 'J': |
13288 | if (intel_syntax) |
14210 | if (intel_syntax) |
13289 | break; |
14211 | break; |
13290 | *obufp++ = 'l'; |
14212 | *obufp++ = 'l'; |
13291 | break; |
14213 | break; |
13292 | case 'K': |
14214 | case 'K': |
13293 | USED_REX (REX_W); |
14215 | USED_REX (REX_W); |
13294 | if (rex & REX_W) |
14216 | if (rex & REX_W) |
13295 | *obufp++ = 'q'; |
14217 | *obufp++ = 'q'; |
13296 | else |
14218 | else |
13297 | *obufp++ = 'd'; |
14219 | *obufp++ = 'd'; |
13298 | break; |
14220 | break; |
13299 | case 'Z': |
14221 | case 'Z': |
- | 14222 | if (l != 0 || len != 1) |
|
- | 14223 | { |
|
- | 14224 | if (l != 1 || len != 2 || last[0] != 'X') |
|
- | 14225 | { |
|
- | 14226 | SAVE_LAST (*p); |
|
- | 14227 | break; |
|
- | 14228 | } |
|
- | 14229 | if (!need_vex || !vex.evex) |
|
- | 14230 | abort (); |
|
- | 14231 | if (intel_syntax |
|
- | 14232 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
|
- | 14233 | break; |
|
- | 14234 | switch (vex.length) |
|
- | 14235 | { |
|
- | 14236 | case 128: |
|
- | 14237 | *obufp++ = 'x'; |
|
- | 14238 | break; |
|
- | 14239 | case 256: |
|
- | 14240 | *obufp++ = 'y'; |
|
- | 14241 | break; |
|
- | 14242 | case 512: |
|
- | 14243 | *obufp++ = 'z'; |
|
- | 14244 | break; |
|
- | 14245 | default: |
|
- | 14246 | abort (); |
|
- | 14247 | } |
|
- | 14248 | break; |
|
- | 14249 | } |
|
13300 | if (intel_syntax) |
14250 | if (intel_syntax) |
13301 | break; |
14251 | break; |
13302 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) |
14252 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) |
13303 | { |
14253 | { |
13304 | *obufp++ = 'q'; |
14254 | *obufp++ = 'q'; |
13305 | break; |
14255 | break; |
13306 | } |
14256 | } |
13307 | /* Fall through. */ |
14257 | /* Fall through. */ |
13308 | goto case_L; |
14258 | goto case_L; |
13309 | case 'L': |
14259 | case 'L': |
13310 | if (l != 0 || len != 1) |
14260 | if (l != 0 || len != 1) |
13311 | { |
14261 | { |
13312 | SAVE_LAST (*p); |
14262 | SAVE_LAST (*p); |
13313 | break; |
14263 | break; |
13314 | } |
14264 | } |
13315 | case_L: |
14265 | case_L: |
13316 | if (intel_syntax) |
14266 | if (intel_syntax) |
13317 | break; |
14267 | break; |
13318 | if (sizeflag & SUFFIX_ALWAYS) |
14268 | if (sizeflag & SUFFIX_ALWAYS) |
13319 | *obufp++ = 'l'; |
14269 | *obufp++ = 'l'; |
13320 | break; |
14270 | break; |
13321 | case 'M': |
14271 | case 'M': |
13322 | if (intel_mnemonic != cond) |
14272 | if (intel_mnemonic != cond) |
13323 | *obufp++ = 'r'; |
14273 | *obufp++ = 'r'; |
13324 | break; |
14274 | break; |
13325 | case 'N': |
14275 | case 'N': |
13326 | if ((prefixes & PREFIX_FWAIT) == 0) |
14276 | if ((prefixes & PREFIX_FWAIT) == 0) |
13327 | *obufp++ = 'n'; |
14277 | *obufp++ = 'n'; |
13328 | else |
14278 | else |
13329 | used_prefixes |= PREFIX_FWAIT; |
14279 | used_prefixes |= PREFIX_FWAIT; |
13330 | break; |
14280 | break; |
13331 | case 'O': |
14281 | case 'O': |
13332 | USED_REX (REX_W); |
14282 | USED_REX (REX_W); |
13333 | if (rex & REX_W) |
14283 | if (rex & REX_W) |
13334 | *obufp++ = 'o'; |
14284 | *obufp++ = 'o'; |
13335 | else if (intel_syntax && (sizeflag & DFLAG)) |
14285 | else if (intel_syntax && (sizeflag & DFLAG)) |
13336 | *obufp++ = 'q'; |
14286 | *obufp++ = 'q'; |
13337 | else |
14287 | else |
13338 | *obufp++ = 'd'; |
14288 | *obufp++ = 'd'; |
13339 | if (!(rex & REX_W)) |
14289 | if (!(rex & REX_W)) |
13340 | used_prefixes |= (prefixes & PREFIX_DATA); |
14290 | used_prefixes |= (prefixes & PREFIX_DATA); |
13341 | break; |
14291 | break; |
13342 | case 'T': |
14292 | case 'T': |
13343 | if (!intel_syntax |
14293 | if (!intel_syntax |
13344 | && address_mode == mode_64bit |
14294 | && address_mode == mode_64bit |
13345 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
14295 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
13346 | { |
14296 | { |
13347 | *obufp++ = 'q'; |
14297 | *obufp++ = 'q'; |
13348 | break; |
14298 | break; |
13349 | } |
14299 | } |
13350 | /* Fall through. */ |
14300 | /* Fall through. */ |
- | 14301 | goto case_P; |
|
13351 | case 'P': |
14302 | case 'P': |
- | 14303 | if (l == 0 && len == 1) |
|
- | 14304 | { |
|
- | 14305 | case_P: |
|
13352 | if (intel_syntax) |
14306 | if (intel_syntax) |
13353 | { |
14307 | { |
13354 | if ((rex & REX_W) == 0 |
14308 | if ((rex & REX_W) == 0 |
13355 | && (prefixes & PREFIX_DATA)) |
14309 | && (prefixes & PREFIX_DATA)) |
13356 | { |
14310 | { |
13357 | if ((sizeflag & DFLAG) == 0) |
14311 | if ((sizeflag & DFLAG) == 0) |
13358 | *obufp++ = 'w'; |
14312 | *obufp++ = 'w'; |
13359 | used_prefixes |= (prefixes & PREFIX_DATA); |
14313 | used_prefixes |= (prefixes & PREFIX_DATA); |
13360 | } |
14314 | } |
13361 | break; |
14315 | break; |
13362 | } |
14316 | } |
13363 | if ((prefixes & PREFIX_DATA) |
14317 | if ((prefixes & PREFIX_DATA) |
13364 | || (rex & REX_W) |
14318 | || (rex & REX_W) |
13365 | || (sizeflag & SUFFIX_ALWAYS)) |
14319 | || (sizeflag & SUFFIX_ALWAYS)) |
13366 | { |
14320 | { |
13367 | USED_REX (REX_W); |
14321 | USED_REX (REX_W); |
13368 | if (rex & REX_W) |
14322 | if (rex & REX_W) |
13369 | *obufp++ = 'q'; |
14323 | *obufp++ = 'q'; |
13370 | else |
14324 | else |
13371 | { |
14325 | { |
13372 | if (sizeflag & DFLAG) |
14326 | if (sizeflag & DFLAG) |
13373 | *obufp++ = 'l'; |
14327 | *obufp++ = 'l'; |
13374 | else |
14328 | else |
13375 | *obufp++ = 'w'; |
14329 | *obufp++ = 'w'; |
13376 | used_prefixes |= (prefixes & PREFIX_DATA); |
14330 | used_prefixes |= (prefixes & PREFIX_DATA); |
13377 | } |
14331 | } |
13378 | } |
14332 | } |
- | 14333 | } |
|
- | 14334 | else |
|
- | 14335 | { |
|
- | 14336 | if (l != 1 || len != 2 || last[0] != 'L') |
|
- | 14337 | { |
|
- | 14338 | SAVE_LAST (*p); |
|
- | 14339 | break; |
|
- | 14340 | } |
|
- | 14341 | ||
- | 14342 | if ((prefixes & PREFIX_DATA) |
|
- | 14343 | || (rex & REX_W) |
|
- | 14344 | || (sizeflag & SUFFIX_ALWAYS)) |
|
- | 14345 | { |
|
- | 14346 | USED_REX (REX_W); |
|
- | 14347 | if (rex & REX_W) |
|
- | 14348 | *obufp++ = 'q'; |
|
- | 14349 | else |
|
- | 14350 | { |
|
- | 14351 | if (sizeflag & DFLAG) |
|
- | 14352 | *obufp++ = intel_syntax ? 'd' : 'l'; |
|
- | 14353 | else |
|
- | 14354 | *obufp++ = 'w'; |
|
- | 14355 | used_prefixes |= (prefixes & PREFIX_DATA); |
|
- | 14356 | } |
|
- | 14357 | } |
|
- | 14358 | } |
|
13379 | break; |
14359 | break; |
13380 | case 'U': |
14360 | case 'U': |
13381 | if (intel_syntax) |
14361 | if (intel_syntax) |
13382 | break; |
14362 | break; |
13383 | if (address_mode == mode_64bit |
14363 | if (address_mode == mode_64bit |
13384 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
14364 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
13385 | { |
14365 | { |
13386 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
14366 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
13387 | *obufp++ = 'q'; |
14367 | *obufp++ = 'q'; |
13388 | break; |
14368 | break; |
13389 | } |
14369 | } |
13390 | /* Fall through. */ |
14370 | /* Fall through. */ |
13391 | goto case_Q; |
14371 | goto case_Q; |
13392 | case 'Q': |
14372 | case 'Q': |
13393 | if (l == 0 && len == 1) |
14373 | if (l == 0 && len == 1) |
13394 | { |
14374 | { |
13395 | case_Q: |
14375 | case_Q: |
13396 | if (intel_syntax && !alt) |
14376 | if (intel_syntax && !alt) |
13397 | break; |
14377 | break; |
13398 | USED_REX (REX_W); |
14378 | USED_REX (REX_W); |
13399 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
14379 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
13400 | { |
14380 | { |
13401 | if (rex & REX_W) |
14381 | if (rex & REX_W) |
13402 | *obufp++ = 'q'; |
14382 | *obufp++ = 'q'; |
13403 | else |
14383 | else |
13404 | { |
14384 | { |
13405 | if (sizeflag & DFLAG) |
14385 | if (sizeflag & DFLAG) |
13406 | *obufp++ = intel_syntax ? 'd' : 'l'; |
14386 | *obufp++ = intel_syntax ? 'd' : 'l'; |
13407 | else |
14387 | else |
13408 | *obufp++ = 'w'; |
14388 | *obufp++ = 'w'; |
13409 | used_prefixes |= (prefixes & PREFIX_DATA); |
14389 | used_prefixes |= (prefixes & PREFIX_DATA); |
13410 | } |
14390 | } |
13411 | } |
14391 | } |
13412 | } |
14392 | } |
13413 | else |
14393 | else |
13414 | { |
14394 | { |
13415 | if (l != 1 || len != 2 || last[0] != 'L') |
14395 | if (l != 1 || len != 2 || last[0] != 'L') |
13416 | { |
14396 | { |
13417 | SAVE_LAST (*p); |
14397 | SAVE_LAST (*p); |
13418 | break; |
14398 | break; |
13419 | } |
14399 | } |
13420 | if (intel_syntax |
14400 | if (intel_syntax |
13421 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
14401 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
13422 | break; |
14402 | break; |
13423 | if ((rex & REX_W)) |
14403 | if ((rex & REX_W)) |
13424 | { |
14404 | { |
13425 | USED_REX (REX_W); |
14405 | USED_REX (REX_W); |
13426 | *obufp++ = 'q'; |
14406 | *obufp++ = 'q'; |
13427 | } |
14407 | } |
13428 | else |
14408 | else |
13429 | *obufp++ = 'l'; |
14409 | *obufp++ = 'l'; |
13430 | } |
14410 | } |
13431 | break; |
14411 | break; |
13432 | case 'R': |
14412 | case 'R': |
13433 | USED_REX (REX_W); |
14413 | USED_REX (REX_W); |
13434 | if (rex & REX_W) |
14414 | if (rex & REX_W) |
13435 | *obufp++ = 'q'; |
14415 | *obufp++ = 'q'; |
13436 | else if (sizeflag & DFLAG) |
14416 | else if (sizeflag & DFLAG) |
13437 | { |
14417 | { |
13438 | if (intel_syntax) |
14418 | if (intel_syntax) |
13439 | *obufp++ = 'd'; |
14419 | *obufp++ = 'd'; |
13440 | else |
14420 | else |
13441 | *obufp++ = 'l'; |
14421 | *obufp++ = 'l'; |
13442 | } |
14422 | } |
13443 | else |
14423 | else |
13444 | *obufp++ = 'w'; |
14424 | *obufp++ = 'w'; |
13445 | if (intel_syntax && !p[1] |
14425 | if (intel_syntax && !p[1] |
13446 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
14426 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
13447 | *obufp++ = 'e'; |
14427 | *obufp++ = 'e'; |
13448 | if (!(rex & REX_W)) |
14428 | if (!(rex & REX_W)) |
13449 | used_prefixes |= (prefixes & PREFIX_DATA); |
14429 | used_prefixes |= (prefixes & PREFIX_DATA); |
13450 | break; |
14430 | break; |
13451 | case 'V': |
14431 | case 'V': |
13452 | if (l == 0 && len == 1) |
14432 | if (l == 0 && len == 1) |
13453 | { |
14433 | { |
13454 | if (intel_syntax) |
14434 | if (intel_syntax) |
13455 | break; |
14435 | break; |
13456 | if (address_mode == mode_64bit |
14436 | if (address_mode == mode_64bit |
13457 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
14437 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
13458 | { |
14438 | { |
13459 | if (sizeflag & SUFFIX_ALWAYS) |
14439 | if (sizeflag & SUFFIX_ALWAYS) |
13460 | *obufp++ = 'q'; |
14440 | *obufp++ = 'q'; |
13461 | break; |
14441 | break; |
13462 | } |
14442 | } |
13463 | } |
14443 | } |
13464 | else |
14444 | else |
13465 | { |
14445 | { |
13466 | if (l != 1 |
14446 | if (l != 1 |
13467 | || len != 2 |
14447 | || len != 2 |
13468 | || last[0] != 'L') |
14448 | || last[0] != 'L') |
13469 | { |
14449 | { |
13470 | SAVE_LAST (*p); |
14450 | SAVE_LAST (*p); |
13471 | break; |
14451 | break; |
13472 | } |
14452 | } |
13473 | 14453 | ||
13474 | if (rex & REX_W) |
14454 | if (rex & REX_W) |
13475 | { |
14455 | { |
13476 | *obufp++ = 'a'; |
14456 | *obufp++ = 'a'; |
13477 | *obufp++ = 'b'; |
14457 | *obufp++ = 'b'; |
13478 | *obufp++ = 's'; |
14458 | *obufp++ = 's'; |
13479 | } |
14459 | } |
13480 | } |
14460 | } |
13481 | /* Fall through. */ |
14461 | /* Fall through. */ |
13482 | goto case_S; |
14462 | goto case_S; |
13483 | case 'S': |
14463 | case 'S': |
13484 | if (l == 0 && len == 1) |
14464 | if (l == 0 && len == 1) |
13485 | { |
14465 | { |
13486 | case_S: |
14466 | case_S: |
13487 | if (intel_syntax) |
14467 | if (intel_syntax) |
13488 | break; |
14468 | break; |
13489 | if (sizeflag & SUFFIX_ALWAYS) |
14469 | if (sizeflag & SUFFIX_ALWAYS) |
13490 | { |
14470 | { |
13491 | if (rex & REX_W) |
14471 | if (rex & REX_W) |
13492 | *obufp++ = 'q'; |
14472 | *obufp++ = 'q'; |
13493 | else |
14473 | else |
13494 | { |
14474 | { |
13495 | if (sizeflag & DFLAG) |
14475 | if (sizeflag & DFLAG) |
13496 | *obufp++ = 'l'; |
14476 | *obufp++ = 'l'; |
13497 | else |
14477 | else |
13498 | *obufp++ = 'w'; |
14478 | *obufp++ = 'w'; |
13499 | used_prefixes |= (prefixes & PREFIX_DATA); |
14479 | used_prefixes |= (prefixes & PREFIX_DATA); |
13500 | } |
14480 | } |
13501 | } |
14481 | } |
13502 | } |
14482 | } |
13503 | else |
14483 | else |
13504 | { |
14484 | { |
13505 | if (l != 1 |
14485 | if (l != 1 |
13506 | || len != 2 |
14486 | || len != 2 |
13507 | || last[0] != 'L') |
14487 | || last[0] != 'L') |
13508 | { |
14488 | { |
13509 | SAVE_LAST (*p); |
14489 | SAVE_LAST (*p); |
13510 | break; |
14490 | break; |
13511 | } |
14491 | } |
13512 | 14492 | ||
13513 | if (address_mode == mode_64bit |
14493 | if (address_mode == mode_64bit |
13514 | && !(prefixes & PREFIX_ADDR)) |
14494 | && !(prefixes & PREFIX_ADDR)) |
13515 | { |
14495 | { |
13516 | *obufp++ = 'a'; |
14496 | *obufp++ = 'a'; |
13517 | *obufp++ = 'b'; |
14497 | *obufp++ = 'b'; |
13518 | *obufp++ = 's'; |
14498 | *obufp++ = 's'; |
13519 | } |
14499 | } |
13520 | 14500 | ||
13521 | goto case_S; |
14501 | goto case_S; |
13522 | } |
14502 | } |
13523 | break; |
14503 | break; |
13524 | case 'X': |
14504 | case 'X': |
13525 | if (l != 0 || len != 1) |
14505 | if (l != 0 || len != 1) |
13526 | { |
14506 | { |
13527 | SAVE_LAST (*p); |
14507 | SAVE_LAST (*p); |
13528 | break; |
14508 | break; |
13529 | } |
14509 | } |
13530 | if (need_vex && vex.prefix) |
14510 | if (need_vex && vex.prefix) |
13531 | { |
14511 | { |
13532 | if (vex.prefix == DATA_PREFIX_OPCODE) |
14512 | if (vex.prefix == DATA_PREFIX_OPCODE) |
13533 | *obufp++ = 'd'; |
14513 | *obufp++ = 'd'; |
13534 | else |
14514 | else |
13535 | *obufp++ = 's'; |
14515 | *obufp++ = 's'; |
13536 | } |
14516 | } |
13537 | else |
14517 | else |
13538 | { |
14518 | { |
13539 | if (prefixes & PREFIX_DATA) |
14519 | if (prefixes & PREFIX_DATA) |
13540 | *obufp++ = 'd'; |
14520 | *obufp++ = 'd'; |
13541 | else |
14521 | else |
13542 | *obufp++ = 's'; |
14522 | *obufp++ = 's'; |
13543 | used_prefixes |= (prefixes & PREFIX_DATA); |
14523 | used_prefixes |= (prefixes & PREFIX_DATA); |
13544 | } |
14524 | } |
13545 | break; |
14525 | break; |
13546 | case 'Y': |
14526 | case 'Y': |
13547 | if (l == 0 && len == 1) |
14527 | if (l == 0 && len == 1) |
13548 | { |
14528 | { |
13549 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
14529 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
13550 | break; |
14530 | break; |
13551 | if (rex & REX_W) |
14531 | if (rex & REX_W) |
13552 | { |
14532 | { |
13553 | USED_REX (REX_W); |
14533 | USED_REX (REX_W); |
13554 | *obufp++ = 'q'; |
14534 | *obufp++ = 'q'; |
13555 | } |
14535 | } |
13556 | break; |
14536 | break; |
13557 | } |
14537 | } |
13558 | else |
14538 | else |
13559 | { |
14539 | { |
13560 | if (l != 1 || len != 2 || last[0] != 'X') |
14540 | if (l != 1 || len != 2 || last[0] != 'X') |
13561 | { |
14541 | { |
13562 | SAVE_LAST (*p); |
14542 | SAVE_LAST (*p); |
13563 | break; |
14543 | break; |
13564 | } |
14544 | } |
13565 | if (!need_vex) |
14545 | if (!need_vex) |
13566 | abort (); |
14546 | abort (); |
13567 | if (intel_syntax |
14547 | if (intel_syntax |
13568 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
14548 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
13569 | break; |
14549 | break; |
13570 | switch (vex.length) |
14550 | switch (vex.length) |
13571 | { |
14551 | { |
13572 | case 128: |
14552 | case 128: |
13573 | *obufp++ = 'x'; |
14553 | *obufp++ = 'x'; |
13574 | break; |
14554 | break; |
13575 | case 256: |
14555 | case 256: |
13576 | *obufp++ = 'y'; |
14556 | *obufp++ = 'y'; |
13577 | break; |
14557 | break; |
- | 14558 | case 512: |
|
- | 14559 | if (!vex.evex) |
|
13578 | default: |
14560 | default: |
13579 | abort (); |
14561 | abort (); |
13580 | } |
14562 | } |
13581 | } |
14563 | } |
13582 | break; |
14564 | break; |
13583 | case 'W': |
14565 | case 'W': |
13584 | if (l == 0 && len == 1) |
14566 | if (l == 0 && len == 1) |
13585 | { |
14567 | { |
13586 | /* operand size flag for cwtl, cbtw */ |
14568 | /* operand size flag for cwtl, cbtw */ |
13587 | USED_REX (REX_W); |
14569 | USED_REX (REX_W); |
13588 | if (rex & REX_W) |
14570 | if (rex & REX_W) |
13589 | { |
14571 | { |
13590 | if (intel_syntax) |
14572 | if (intel_syntax) |
13591 | *obufp++ = 'd'; |
14573 | *obufp++ = 'd'; |
13592 | else |
14574 | else |
13593 | *obufp++ = 'l'; |
14575 | *obufp++ = 'l'; |
13594 | } |
14576 | } |
13595 | else if (sizeflag & DFLAG) |
14577 | else if (sizeflag & DFLAG) |
13596 | *obufp++ = 'w'; |
14578 | *obufp++ = 'w'; |
13597 | else |
14579 | else |
13598 | *obufp++ = 'b'; |
14580 | *obufp++ = 'b'; |
13599 | if (!(rex & REX_W)) |
14581 | if (!(rex & REX_W)) |
13600 | used_prefixes |= (prefixes & PREFIX_DATA); |
14582 | used_prefixes |= (prefixes & PREFIX_DATA); |
13601 | } |
14583 | } |
13602 | else |
14584 | else |
13603 | { |
14585 | { |
13604 | if (l != 1 |
14586 | if (l != 1 |
13605 | || len != 2 |
14587 | || len != 2 |
13606 | || (last[0] != 'X' |
14588 | || (last[0] != 'X' |
13607 | && last[0] != 'L')) |
14589 | && last[0] != 'L')) |
13608 | { |
14590 | { |
13609 | SAVE_LAST (*p); |
14591 | SAVE_LAST (*p); |
13610 | break; |
14592 | break; |
13611 | } |
14593 | } |
13612 | if (!need_vex) |
14594 | if (!need_vex) |
13613 | abort (); |
14595 | abort (); |
13614 | if (last[0] == 'X') |
14596 | if (last[0] == 'X') |
13615 | *obufp++ = vex.w ? 'd': 's'; |
14597 | *obufp++ = vex.w ? 'd': 's'; |
13616 | else |
14598 | else |
13617 | *obufp++ = vex.w ? 'q': 'd'; |
14599 | *obufp++ = vex.w ? 'q': 'd'; |
13618 | } |
14600 | } |
13619 | break; |
14601 | break; |
- | 14602 | case '^': |
|
- | 14603 | if (intel_syntax) |
|
- | 14604 | break; |
|
- | 14605 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
|
- | 14606 | { |
|
- | 14607 | if (sizeflag & DFLAG) |
|
- | 14608 | *obufp++ = 'l'; |
|
- | 14609 | else |
|
- | 14610 | *obufp++ = 'w'; |
|
- | 14611 | used_prefixes |= (prefixes & PREFIX_DATA); |
|
- | 14612 | } |
|
- | 14613 | break; |
|
- | 14614 | case '@': |
|
- | 14615 | if (intel_syntax) |
|
- | 14616 | break; |
|
- | 14617 | if (address_mode == mode_64bit |
|
- | 14618 | && (isa64 == intel64 |
|
- | 14619 | || ((sizeflag & DFLAG) || (rex & REX_W)))) |
|
- | 14620 | *obufp++ = 'q'; |
|
- | 14621 | else if ((prefixes & PREFIX_DATA)) |
|
- | 14622 | { |
|
- | 14623 | if (!(sizeflag & DFLAG)) |
|
- | 14624 | *obufp++ = 'w'; |
|
- | 14625 | used_prefixes |= (prefixes & PREFIX_DATA); |
|
- | 14626 | } |
|
- | 14627 | break; |
|
13620 | } |
14628 | } |
13621 | alt = 0; |
14629 | alt = 0; |
13622 | } |
14630 | } |
13623 | *obufp = 0; |
14631 | *obufp = 0; |
13624 | mnemonicendp = obufp; |
14632 | mnemonicendp = obufp; |
13625 | return 0; |
14633 | return 0; |
13626 | } |
14634 | } |
13627 | 14635 | ||
13628 | static void |
14636 | static void |
13629 | oappend (const char *s) |
14637 | oappend (const char *s) |
13630 | { |
14638 | { |
13631 | obufp = stpcpy (obufp, s); |
14639 | obufp = stpcpy (obufp, s); |
13632 | } |
14640 | } |
13633 | 14641 | ||
13634 | static void |
14642 | static void |
13635 | append_seg (void) |
14643 | append_seg (void) |
13636 | { |
14644 | { |
- | 14645 | /* Only print the active segment register. */ |
|
13637 | if (prefixes & PREFIX_CS) |
14646 | if (!active_seg_prefix) |
- | 14647 | return; |
|
- | 14648 | ||
- | 14649 | used_prefixes |= active_seg_prefix; |
|
- | 14650 | switch (active_seg_prefix) |
|
13638 | { |
14651 | { |
13639 | used_prefixes |= PREFIX_CS; |
14652 | case PREFIX_CS: |
13640 | oappend_maybe_intel ("%cs:"); |
14653 | oappend_maybe_intel ("%cs:"); |
13641 | } |
14654 | break; |
13642 | if (prefixes & PREFIX_DS) |
14655 | case PREFIX_DS: |
13643 | { |
- | |
13644 | used_prefixes |= PREFIX_DS; |
- | |
13645 | oappend_maybe_intel ("%ds:"); |
14656 | oappend_maybe_intel ("%ds:"); |
13646 | } |
14657 | break; |
13647 | if (prefixes & PREFIX_SS) |
14658 | case PREFIX_SS: |
13648 | { |
- | |
13649 | used_prefixes |= PREFIX_SS; |
- | |
13650 | oappend_maybe_intel ("%ss:"); |
14659 | oappend_maybe_intel ("%ss:"); |
13651 | } |
14660 | break; |
13652 | if (prefixes & PREFIX_ES) |
14661 | case PREFIX_ES: |
13653 | { |
- | |
13654 | used_prefixes |= PREFIX_ES; |
- | |
13655 | oappend_maybe_intel ("%es:"); |
14662 | oappend_maybe_intel ("%es:"); |
13656 | } |
14663 | break; |
13657 | if (prefixes & PREFIX_FS) |
14664 | case PREFIX_FS: |
13658 | { |
- | |
13659 | used_prefixes |= PREFIX_FS; |
- | |
13660 | oappend_maybe_intel ("%fs:"); |
14665 | oappend_maybe_intel ("%fs:"); |
13661 | } |
14666 | break; |
13662 | if (prefixes & PREFIX_GS) |
14667 | case PREFIX_GS: |
13663 | { |
- | |
13664 | used_prefixes |= PREFIX_GS; |
- | |
13665 | oappend_maybe_intel ("%gs:"); |
14668 | oappend_maybe_intel ("%gs:"); |
- | 14669 | break; |
|
- | 14670 | default: |
|
- | 14671 | break; |
|
13666 | } |
14672 | } |
13667 | } |
14673 | } |
13668 | 14674 | ||
13669 | static void |
14675 | static void |
13670 | OP_indirE (int bytemode, int sizeflag) |
14676 | OP_indirE (int bytemode, int sizeflag) |
13671 | { |
14677 | { |
13672 | if (!intel_syntax) |
14678 | if (!intel_syntax) |
13673 | oappend ("*"); |
14679 | oappend ("*"); |
13674 | OP_E (bytemode, sizeflag); |
14680 | OP_E (bytemode, sizeflag); |
13675 | } |
14681 | } |
13676 | 14682 | ||
13677 | static void |
14683 | static void |
13678 | print_operand_value (char *buf, int hex, bfd_vma disp) |
14684 | print_operand_value (char *buf, int hex, bfd_vma disp) |
13679 | { |
14685 | { |
13680 | if (address_mode == mode_64bit) |
14686 | if (address_mode == mode_64bit) |
13681 | { |
14687 | { |
13682 | if (hex) |
14688 | if (hex) |
13683 | { |
14689 | { |
13684 | char tmp[30]; |
14690 | char tmp[30]; |
13685 | int i; |
14691 | int i; |
13686 | buf[0] = '0'; |
14692 | buf[0] = '0'; |
13687 | buf[1] = 'x'; |
14693 | buf[1] = 'x'; |
13688 | sprintf_vma (tmp, disp); |
14694 | sprintf_vma (tmp, disp); |
13689 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
14695 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
13690 | strcpy (buf + 2, tmp + i); |
14696 | strcpy (buf + 2, tmp + i); |
13691 | } |
14697 | } |
13692 | else |
14698 | else |
13693 | { |
14699 | { |
13694 | bfd_signed_vma v = disp; |
14700 | bfd_signed_vma v = disp; |
13695 | char tmp[30]; |
14701 | char tmp[30]; |
13696 | int i; |
14702 | int i; |
13697 | if (v < 0) |
14703 | if (v < 0) |
13698 | { |
14704 | { |
13699 | *(buf++) = '-'; |
14705 | *(buf++) = '-'; |
13700 | v = -disp; |
14706 | v = -disp; |
13701 | /* Check for possible overflow on 0x8000000000000000. */ |
14707 | /* Check for possible overflow on 0x8000000000000000. */ |
13702 | if (v < 0) |
14708 | if (v < 0) |
13703 | { |
14709 | { |
13704 | strcpy (buf, "9223372036854775808"); |
14710 | strcpy (buf, "9223372036854775808"); |
13705 | return; |
14711 | return; |
13706 | } |
14712 | } |
13707 | } |
14713 | } |
13708 | if (!v) |
14714 | if (!v) |
13709 | { |
14715 | { |
13710 | strcpy (buf, "0"); |
14716 | strcpy (buf, "0"); |
13711 | return; |
14717 | return; |
13712 | } |
14718 | } |
13713 | 14719 | ||
13714 | i = 0; |
14720 | i = 0; |
13715 | tmp[29] = 0; |
14721 | tmp[29] = 0; |
13716 | while (v) |
14722 | while (v) |
13717 | { |
14723 | { |
13718 | tmp[28 - i] = (v % 10) + '0'; |
14724 | tmp[28 - i] = (v % 10) + '0'; |
13719 | v /= 10; |
14725 | v /= 10; |
13720 | i++; |
14726 | i++; |
13721 | } |
14727 | } |
13722 | strcpy (buf, tmp + 29 - i); |
14728 | strcpy (buf, tmp + 29 - i); |
13723 | } |
14729 | } |
13724 | } |
14730 | } |
13725 | else |
14731 | else |
13726 | { |
14732 | { |
13727 | if (hex) |
14733 | if (hex) |
13728 | sprintf (buf, "0x%x", (unsigned int) disp); |
14734 | sprintf (buf, "0x%x", (unsigned int) disp); |
13729 | else |
14735 | else |
13730 | sprintf (buf, "%d", (int) disp); |
14736 | sprintf (buf, "%d", (int) disp); |
13731 | } |
14737 | } |
13732 | } |
14738 | } |
13733 | 14739 | ||
13734 | /* Put DISP in BUF as signed hex number. */ |
14740 | /* Put DISP in BUF as signed hex number. */ |
13735 | 14741 | ||
13736 | static void |
14742 | static void |
13737 | print_displacement (char *buf, bfd_vma disp) |
14743 | print_displacement (char *buf, bfd_vma disp) |
13738 | { |
14744 | { |
13739 | bfd_signed_vma val = disp; |
14745 | bfd_signed_vma val = disp; |
13740 | char tmp[30]; |
14746 | char tmp[30]; |
13741 | int i, j = 0; |
14747 | int i, j = 0; |
13742 | 14748 | ||
13743 | if (val < 0) |
14749 | if (val < 0) |
13744 | { |
14750 | { |
13745 | buf[j++] = '-'; |
14751 | buf[j++] = '-'; |
13746 | val = -disp; |
14752 | val = -disp; |
13747 | 14753 | ||
13748 | /* Check for possible overflow. */ |
14754 | /* Check for possible overflow. */ |
13749 | if (val < 0) |
14755 | if (val < 0) |
13750 | { |
14756 | { |
13751 | switch (address_mode) |
14757 | switch (address_mode) |
13752 | { |
14758 | { |
13753 | case mode_64bit: |
14759 | case mode_64bit: |
13754 | strcpy (buf + j, "0x8000000000000000"); |
14760 | strcpy (buf + j, "0x8000000000000000"); |
13755 | break; |
14761 | break; |
13756 | case mode_32bit: |
14762 | case mode_32bit: |
13757 | strcpy (buf + j, "0x80000000"); |
14763 | strcpy (buf + j, "0x80000000"); |
13758 | break; |
14764 | break; |
13759 | case mode_16bit: |
14765 | case mode_16bit: |
13760 | strcpy (buf + j, "0x8000"); |
14766 | strcpy (buf + j, "0x8000"); |
13761 | break; |
14767 | break; |
13762 | } |
14768 | } |
13763 | return; |
14769 | return; |
13764 | } |
14770 | } |
13765 | } |
14771 | } |
13766 | 14772 | ||
13767 | buf[j++] = '0'; |
14773 | buf[j++] = '0'; |
13768 | buf[j++] = 'x'; |
14774 | buf[j++] = 'x'; |
13769 | 14775 | ||
13770 | sprintf_vma (tmp, (bfd_vma) val); |
14776 | sprintf_vma (tmp, (bfd_vma) val); |
13771 | for (i = 0; tmp[i] == '0'; i++) |
14777 | for (i = 0; tmp[i] == '0'; i++) |
13772 | continue; |
14778 | continue; |
13773 | if (tmp[i] == '\0') |
14779 | if (tmp[i] == '\0') |
13774 | i--; |
14780 | i--; |
13775 | strcpy (buf + j, tmp + i); |
14781 | strcpy (buf + j, tmp + i); |
13776 | } |
14782 | } |
13777 | 14783 | ||
13778 | static void |
14784 | static void |
13779 | intel_operand_size (int bytemode, int sizeflag) |
14785 | intel_operand_size (int bytemode, int sizeflag) |
13780 | { |
14786 | { |
13781 | if (vex.evex |
14787 | if (vex.evex |
13782 | && vex.b |
14788 | && vex.b |
13783 | && (bytemode == x_mode |
14789 | && (bytemode == x_mode |
13784 | || bytemode == evex_half_bcst_xmmq_mode)) |
14790 | || bytemode == evex_half_bcst_xmmq_mode)) |
13785 | { |
14791 | { |
13786 | if (vex.w) |
14792 | if (vex.w) |
13787 | oappend ("QWORD PTR "); |
14793 | oappend ("QWORD PTR "); |
13788 | else |
14794 | else |
13789 | oappend ("DWORD PTR "); |
14795 | oappend ("DWORD PTR "); |
13790 | return; |
14796 | return; |
13791 | } |
14797 | } |
13792 | switch (bytemode) |
14798 | switch (bytemode) |
13793 | { |
14799 | { |
13794 | case b_mode: |
14800 | case b_mode: |
13795 | case b_swap_mode: |
14801 | case b_swap_mode: |
13796 | case dqb_mode: |
14802 | case dqb_mode: |
- | 14803 | case db_mode: |
|
13797 | oappend ("BYTE PTR "); |
14804 | oappend ("BYTE PTR "); |
13798 | break; |
14805 | break; |
13799 | case w_mode: |
14806 | case w_mode: |
- | 14807 | case dw_mode: |
|
13800 | case dqw_mode: |
14808 | case dqw_mode: |
- | 14809 | case dqw_swap_mode: |
|
13801 | oappend ("WORD PTR "); |
14810 | oappend ("WORD PTR "); |
13802 | break; |
14811 | break; |
13803 | case stack_v_mode: |
14812 | case stack_v_mode: |
13804 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
14813 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
13805 | { |
14814 | { |
13806 | oappend ("QWORD PTR "); |
14815 | oappend ("QWORD PTR "); |
13807 | break; |
14816 | break; |
13808 | } |
14817 | } |
13809 | /* FALLTHRU */ |
14818 | /* FALLTHRU */ |
13810 | case v_mode: |
14819 | case v_mode: |
13811 | case v_swap_mode: |
14820 | case v_swap_mode: |
13812 | case dq_mode: |
14821 | case dq_mode: |
13813 | USED_REX (REX_W); |
14822 | USED_REX (REX_W); |
13814 | if (rex & REX_W) |
14823 | if (rex & REX_W) |
13815 | oappend ("QWORD PTR "); |
14824 | oappend ("QWORD PTR "); |
13816 | else |
14825 | else |
13817 | { |
14826 | { |
13818 | if ((sizeflag & DFLAG) || bytemode == dq_mode) |
14827 | if ((sizeflag & DFLAG) || bytemode == dq_mode) |
13819 | oappend ("DWORD PTR "); |
14828 | oappend ("DWORD PTR "); |
13820 | else |
14829 | else |
13821 | oappend ("WORD PTR "); |
14830 | oappend ("WORD PTR "); |
13822 | used_prefixes |= (prefixes & PREFIX_DATA); |
14831 | used_prefixes |= (prefixes & PREFIX_DATA); |
13823 | } |
14832 | } |
13824 | break; |
14833 | break; |
13825 | case z_mode: |
14834 | case z_mode: |
13826 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
14835 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
13827 | *obufp++ = 'D'; |
14836 | *obufp++ = 'D'; |
13828 | oappend ("WORD PTR "); |
14837 | oappend ("WORD PTR "); |
13829 | if (!(rex & REX_W)) |
14838 | if (!(rex & REX_W)) |
13830 | used_prefixes |= (prefixes & PREFIX_DATA); |
14839 | used_prefixes |= (prefixes & PREFIX_DATA); |
13831 | break; |
14840 | break; |
13832 | case a_mode: |
14841 | case a_mode: |
13833 | if (sizeflag & DFLAG) |
14842 | if (sizeflag & DFLAG) |
13834 | oappend ("QWORD PTR "); |
14843 | oappend ("QWORD PTR "); |
13835 | else |
14844 | else |
13836 | oappend ("DWORD PTR "); |
14845 | oappend ("DWORD PTR "); |
13837 | used_prefixes |= (prefixes & PREFIX_DATA); |
14846 | used_prefixes |= (prefixes & PREFIX_DATA); |
13838 | break; |
14847 | break; |
13839 | case d_mode: |
14848 | case d_mode: |
13840 | case d_scalar_mode: |
14849 | case d_scalar_mode: |
13841 | case d_scalar_swap_mode: |
14850 | case d_scalar_swap_mode: |
13842 | case d_swap_mode: |
14851 | case d_swap_mode: |
13843 | case dqd_mode: |
14852 | case dqd_mode: |
13844 | oappend ("DWORD PTR "); |
14853 | oappend ("DWORD PTR "); |
13845 | break; |
14854 | break; |
13846 | case q_mode: |
14855 | case q_mode: |
13847 | case q_scalar_mode: |
14856 | case q_scalar_mode: |
13848 | case q_scalar_swap_mode: |
14857 | case q_scalar_swap_mode: |
13849 | case q_swap_mode: |
14858 | case q_swap_mode: |
13850 | oappend ("QWORD PTR "); |
14859 | oappend ("QWORD PTR "); |
13851 | break; |
14860 | break; |
13852 | case m_mode: |
14861 | case m_mode: |
13853 | if (address_mode == mode_64bit) |
14862 | if (address_mode == mode_64bit) |
13854 | oappend ("QWORD PTR "); |
14863 | oappend ("QWORD PTR "); |
13855 | else |
14864 | else |
13856 | oappend ("DWORD PTR "); |
14865 | oappend ("DWORD PTR "); |
13857 | break; |
14866 | break; |
13858 | case f_mode: |
14867 | case f_mode: |
13859 | if (sizeflag & DFLAG) |
14868 | if (sizeflag & DFLAG) |
13860 | oappend ("FWORD PTR "); |
14869 | oappend ("FWORD PTR "); |
13861 | else |
14870 | else |
13862 | oappend ("DWORD PTR "); |
14871 | oappend ("DWORD PTR "); |
13863 | used_prefixes |= (prefixes & PREFIX_DATA); |
14872 | used_prefixes |= (prefixes & PREFIX_DATA); |
13864 | break; |
14873 | break; |
13865 | case t_mode: |
14874 | case t_mode: |
13866 | oappend ("TBYTE PTR "); |
14875 | oappend ("TBYTE PTR "); |
13867 | break; |
14876 | break; |
13868 | case x_mode: |
14877 | case x_mode: |
13869 | case x_swap_mode: |
14878 | case x_swap_mode: |
13870 | case evex_x_gscat_mode: |
14879 | case evex_x_gscat_mode: |
13871 | case evex_x_nobcst_mode: |
14880 | case evex_x_nobcst_mode: |
13872 | if (need_vex) |
14881 | if (need_vex) |
13873 | { |
14882 | { |
13874 | switch (vex.length) |
14883 | switch (vex.length) |
13875 | { |
14884 | { |
13876 | case 128: |
14885 | case 128: |
13877 | oappend ("XMMWORD PTR "); |
14886 | oappend ("XMMWORD PTR "); |
13878 | break; |
14887 | break; |
13879 | case 256: |
14888 | case 256: |
13880 | oappend ("YMMWORD PTR "); |
14889 | oappend ("YMMWORD PTR "); |
13881 | break; |
14890 | break; |
13882 | case 512: |
14891 | case 512: |
13883 | oappend ("ZMMWORD PTR "); |
14892 | oappend ("ZMMWORD PTR "); |
13884 | break; |
14893 | break; |
13885 | default: |
14894 | default: |
13886 | abort (); |
14895 | abort (); |
13887 | } |
14896 | } |
13888 | } |
14897 | } |
13889 | else |
14898 | else |
13890 | oappend ("XMMWORD PTR "); |
14899 | oappend ("XMMWORD PTR "); |
13891 | break; |
14900 | break; |
13892 | case xmm_mode: |
14901 | case xmm_mode: |
13893 | oappend ("XMMWORD PTR "); |
14902 | oappend ("XMMWORD PTR "); |
13894 | break; |
14903 | break; |
13895 | case ymm_mode: |
14904 | case ymm_mode: |
13896 | oappend ("YMMWORD PTR "); |
14905 | oappend ("YMMWORD PTR "); |
13897 | break; |
14906 | break; |
13898 | case xmmq_mode: |
14907 | case xmmq_mode: |
13899 | case evex_half_bcst_xmmq_mode: |
14908 | case evex_half_bcst_xmmq_mode: |
13900 | if (!need_vex) |
14909 | if (!need_vex) |
13901 | abort (); |
14910 | abort (); |
13902 | 14911 | ||
13903 | switch (vex.length) |
14912 | switch (vex.length) |
13904 | { |
14913 | { |
13905 | case 128: |
14914 | case 128: |
13906 | oappend ("QWORD PTR "); |
14915 | oappend ("QWORD PTR "); |
13907 | break; |
14916 | break; |
13908 | case 256: |
14917 | case 256: |
13909 | oappend ("XMMWORD PTR "); |
14918 | oappend ("XMMWORD PTR "); |
13910 | break; |
14919 | break; |
13911 | case 512: |
14920 | case 512: |
13912 | oappend ("YMMWORD PTR "); |
14921 | oappend ("YMMWORD PTR "); |
13913 | break; |
14922 | break; |
13914 | default: |
14923 | default: |
13915 | abort (); |
14924 | abort (); |
13916 | } |
14925 | } |
13917 | break; |
14926 | break; |
13918 | case xmm_mb_mode: |
14927 | case xmm_mb_mode: |
13919 | if (!need_vex) |
14928 | if (!need_vex) |
13920 | abort (); |
14929 | abort (); |
13921 | 14930 | ||
13922 | switch (vex.length) |
14931 | switch (vex.length) |
13923 | { |
14932 | { |
13924 | case 128: |
14933 | case 128: |
13925 | case 256: |
14934 | case 256: |
13926 | case 512: |
14935 | case 512: |
13927 | oappend ("BYTE PTR "); |
14936 | oappend ("BYTE PTR "); |
13928 | break; |
14937 | break; |
13929 | default: |
14938 | default: |
13930 | abort (); |
14939 | abort (); |
13931 | } |
14940 | } |
13932 | break; |
14941 | break; |
13933 | case xmm_mw_mode: |
14942 | case xmm_mw_mode: |
13934 | if (!need_vex) |
14943 | if (!need_vex) |
13935 | abort (); |
14944 | abort (); |
13936 | 14945 | ||
13937 | switch (vex.length) |
14946 | switch (vex.length) |
13938 | { |
14947 | { |
13939 | case 128: |
14948 | case 128: |
13940 | case 256: |
14949 | case 256: |
13941 | case 512: |
14950 | case 512: |
13942 | oappend ("WORD PTR "); |
14951 | oappend ("WORD PTR "); |
13943 | break; |
14952 | break; |
13944 | default: |
14953 | default: |
13945 | abort (); |
14954 | abort (); |
13946 | } |
14955 | } |
13947 | break; |
14956 | break; |
13948 | case xmm_md_mode: |
14957 | case xmm_md_mode: |
13949 | if (!need_vex) |
14958 | if (!need_vex) |
13950 | abort (); |
14959 | abort (); |
13951 | 14960 | ||
13952 | switch (vex.length) |
14961 | switch (vex.length) |
13953 | { |
14962 | { |
13954 | case 128: |
14963 | case 128: |
13955 | case 256: |
14964 | case 256: |
13956 | case 512: |
14965 | case 512: |
13957 | oappend ("DWORD PTR "); |
14966 | oappend ("DWORD PTR "); |
13958 | break; |
14967 | break; |
13959 | default: |
14968 | default: |
13960 | abort (); |
14969 | abort (); |
13961 | } |
14970 | } |
13962 | break; |
14971 | break; |
13963 | case xmm_mq_mode: |
14972 | case xmm_mq_mode: |
13964 | if (!need_vex) |
14973 | if (!need_vex) |
13965 | abort (); |
14974 | abort (); |
13966 | 14975 | ||
13967 | switch (vex.length) |
14976 | switch (vex.length) |
13968 | { |
14977 | { |
13969 | case 128: |
14978 | case 128: |
13970 | case 256: |
14979 | case 256: |
13971 | case 512: |
14980 | case 512: |
13972 | oappend ("QWORD PTR "); |
14981 | oappend ("QWORD PTR "); |
13973 | break; |
14982 | break; |
13974 | default: |
14983 | default: |
13975 | abort (); |
14984 | abort (); |
13976 | } |
14985 | } |
13977 | break; |
14986 | break; |
13978 | case xmmdw_mode: |
14987 | case xmmdw_mode: |
13979 | if (!need_vex) |
14988 | if (!need_vex) |
13980 | abort (); |
14989 | abort (); |
13981 | 14990 | ||
13982 | switch (vex.length) |
14991 | switch (vex.length) |
13983 | { |
14992 | { |
13984 | case 128: |
14993 | case 128: |
13985 | oappend ("WORD PTR "); |
14994 | oappend ("WORD PTR "); |
13986 | break; |
14995 | break; |
13987 | case 256: |
14996 | case 256: |
13988 | oappend ("DWORD PTR "); |
14997 | oappend ("DWORD PTR "); |
13989 | break; |
14998 | break; |
13990 | case 512: |
14999 | case 512: |
13991 | oappend ("QWORD PTR "); |
15000 | oappend ("QWORD PTR "); |
13992 | break; |
15001 | break; |
13993 | default: |
15002 | default: |
13994 | abort (); |
15003 | abort (); |
13995 | } |
15004 | } |
13996 | break; |
15005 | break; |
13997 | case xmmqd_mode: |
15006 | case xmmqd_mode: |
13998 | if (!need_vex) |
15007 | if (!need_vex) |
13999 | abort (); |
15008 | abort (); |
14000 | 15009 | ||
14001 | switch (vex.length) |
15010 | switch (vex.length) |
14002 | { |
15011 | { |
14003 | case 128: |
15012 | case 128: |
14004 | oappend ("DWORD PTR "); |
15013 | oappend ("DWORD PTR "); |
14005 | break; |
15014 | break; |
14006 | case 256: |
15015 | case 256: |
14007 | oappend ("QWORD PTR "); |
15016 | oappend ("QWORD PTR "); |
14008 | break; |
15017 | break; |
14009 | case 512: |
15018 | case 512: |
14010 | oappend ("XMMWORD PTR "); |
15019 | oappend ("XMMWORD PTR "); |
14011 | break; |
15020 | break; |
14012 | default: |
15021 | default: |
14013 | abort (); |
15022 | abort (); |
14014 | } |
15023 | } |
14015 | break; |
15024 | break; |
14016 | case ymmq_mode: |
15025 | case ymmq_mode: |
14017 | if (!need_vex) |
15026 | if (!need_vex) |
14018 | abort (); |
15027 | abort (); |
14019 | 15028 | ||
14020 | switch (vex.length) |
15029 | switch (vex.length) |
14021 | { |
15030 | { |
14022 | case 128: |
15031 | case 128: |
14023 | oappend ("QWORD PTR "); |
15032 | oappend ("QWORD PTR "); |
14024 | break; |
15033 | break; |
14025 | case 256: |
15034 | case 256: |
14026 | oappend ("YMMWORD PTR "); |
15035 | oappend ("YMMWORD PTR "); |
14027 | break; |
15036 | break; |
14028 | case 512: |
15037 | case 512: |
14029 | oappend ("ZMMWORD PTR "); |
15038 | oappend ("ZMMWORD PTR "); |
14030 | break; |
15039 | break; |
14031 | default: |
15040 | default: |
14032 | abort (); |
15041 | abort (); |
14033 | } |
15042 | } |
14034 | break; |
15043 | break; |
14035 | case ymmxmm_mode: |
15044 | case ymmxmm_mode: |
14036 | if (!need_vex) |
15045 | if (!need_vex) |
14037 | abort (); |
15046 | abort (); |
14038 | 15047 | ||
14039 | switch (vex.length) |
15048 | switch (vex.length) |
14040 | { |
15049 | { |
14041 | case 128: |
15050 | case 128: |
14042 | case 256: |
15051 | case 256: |
14043 | oappend ("XMMWORD PTR "); |
15052 | oappend ("XMMWORD PTR "); |
14044 | break; |
15053 | break; |
14045 | default: |
15054 | default: |
14046 | abort (); |
15055 | abort (); |
14047 | } |
15056 | } |
14048 | break; |
15057 | break; |
14049 | case o_mode: |
15058 | case o_mode: |
14050 | oappend ("OWORD PTR "); |
15059 | oappend ("OWORD PTR "); |
14051 | break; |
15060 | break; |
14052 | case xmm_mdq_mode: |
15061 | case xmm_mdq_mode: |
14053 | case vex_w_dq_mode: |
15062 | case vex_w_dq_mode: |
14054 | case vex_scalar_w_dq_mode: |
15063 | case vex_scalar_w_dq_mode: |
14055 | if (!need_vex) |
15064 | if (!need_vex) |
14056 | abort (); |
15065 | abort (); |
14057 | 15066 | ||
14058 | if (vex.w) |
15067 | if (vex.w) |
14059 | oappend ("QWORD PTR "); |
15068 | oappend ("QWORD PTR "); |
14060 | else |
15069 | else |
14061 | oappend ("DWORD PTR "); |
15070 | oappend ("DWORD PTR "); |
14062 | break; |
15071 | break; |
14063 | case vex_vsib_d_w_dq_mode: |
15072 | case vex_vsib_d_w_dq_mode: |
14064 | case vex_vsib_q_w_dq_mode: |
15073 | case vex_vsib_q_w_dq_mode: |
14065 | if (!need_vex) |
15074 | if (!need_vex) |
14066 | abort (); |
15075 | abort (); |
14067 | 15076 | ||
14068 | if (!vex.evex) |
15077 | if (!vex.evex) |
14069 | { |
15078 | { |
14070 | if (vex.w) |
15079 | if (vex.w) |
14071 | oappend ("QWORD PTR "); |
15080 | oappend ("QWORD PTR "); |
14072 | else |
15081 | else |
14073 | oappend ("DWORD PTR "); |
15082 | oappend ("DWORD PTR "); |
14074 | } |
15083 | } |
14075 | else |
15084 | else |
14076 | { |
15085 | { |
14077 | if (vex.length != 512) |
15086 | switch (vex.length) |
- | 15087 | { |
|
- | 15088 | case 128: |
|
- | 15089 | oappend ("XMMWORD PTR "); |
|
- | 15090 | break; |
|
- | 15091 | case 256: |
|
- | 15092 | oappend ("YMMWORD PTR "); |
|
14078 | abort (); |
15093 | break; |
- | 15094 | case 512: |
|
14079 | oappend ("ZMMWORD PTR "); |
15095 | oappend ("ZMMWORD PTR "); |
- | 15096 | break; |
|
- | 15097 | default: |
|
- | 15098 | abort (); |
|
- | 15099 | } |
|
14080 | } |
15100 | } |
14081 | break; |
15101 | break; |
- | 15102 | case vex_vsib_q_w_d_mode: |
|
- | 15103 | case vex_vsib_d_w_d_mode: |
|
- | 15104 | if (!need_vex || !vex.evex) |
|
- | 15105 | abort (); |
|
- | 15106 | ||
- | 15107 | switch (vex.length) |
|
- | 15108 | { |
|
- | 15109 | case 128: |
|
- | 15110 | oappend ("QWORD PTR "); |
|
- | 15111 | break; |
|
- | 15112 | case 256: |
|
- | 15113 | oappend ("XMMWORD PTR "); |
|
- | 15114 | break; |
|
- | 15115 | case 512: |
|
- | 15116 | oappend ("YMMWORD PTR "); |
|
- | 15117 | break; |
|
- | 15118 | default: |
|
- | 15119 | abort (); |
|
- | 15120 | } |
|
- | 15121 | ||
- | 15122 | break; |
|
- | 15123 | case mask_bd_mode: |
|
- | 15124 | if (!need_vex || vex.length != 128) |
|
- | 15125 | abort (); |
|
- | 15126 | if (vex.w) |
|
- | 15127 | oappend ("DWORD PTR "); |
|
- | 15128 | else |
|
- | 15129 | oappend ("BYTE PTR "); |
|
- | 15130 | break; |
|
14082 | case mask_mode: |
15131 | case mask_mode: |
14083 | if (!need_vex) |
15132 | if (!need_vex) |
14084 | abort (); |
15133 | abort (); |
14085 | /* Currently the only instructions, which allows either mask or |
- | |
14086 | memory operand, are AVX512's KMOVW instructions. They need |
- | |
14087 | Word-sized operand. */ |
15134 | if (vex.w) |
14088 | if (vex.w || vex.length != 128) |
15135 | oappend ("QWORD PTR "); |
14089 | abort (); |
15136 | else |
14090 | oappend ("WORD PTR "); |
15137 | oappend ("WORD PTR "); |
14091 | break; |
15138 | break; |
14092 | case v_bnd_mode: |
15139 | case v_bnd_mode: |
14093 | default: |
15140 | default: |
14094 | break; |
15141 | break; |
14095 | } |
15142 | } |
14096 | } |
15143 | } |
14097 | 15144 | ||
14098 | static void |
15145 | static void |
14099 | OP_E_register (int bytemode, int sizeflag) |
15146 | OP_E_register (int bytemode, int sizeflag) |
14100 | { |
15147 | { |
14101 | int reg = modrm.rm; |
15148 | int reg = modrm.rm; |
14102 | const char **names; |
15149 | const char **names; |
14103 | 15150 | ||
14104 | USED_REX (REX_B); |
15151 | USED_REX (REX_B); |
14105 | if ((rex & REX_B)) |
15152 | if ((rex & REX_B)) |
14106 | reg += 8; |
15153 | reg += 8; |
14107 | 15154 | ||
14108 | if ((sizeflag & SUFFIX_ALWAYS) |
15155 | if ((sizeflag & SUFFIX_ALWAYS) |
14109 | && (bytemode == b_swap_mode || bytemode == v_swap_mode)) |
15156 | && (bytemode == b_swap_mode |
- | 15157 | || bytemode == v_swap_mode |
|
- | 15158 | || bytemode == dqw_swap_mode)) |
|
14110 | swap_operand (); |
15159 | swap_operand (); |
14111 | 15160 | ||
14112 | switch (bytemode) |
15161 | switch (bytemode) |
14113 | { |
15162 | { |
14114 | case b_mode: |
15163 | case b_mode: |
14115 | case b_swap_mode: |
15164 | case b_swap_mode: |
14116 | USED_REX (0); |
15165 | USED_REX (0); |
14117 | if (rex) |
15166 | if (rex) |
14118 | names = names8rex; |
15167 | names = names8rex; |
14119 | else |
15168 | else |
14120 | names = names8; |
15169 | names = names8; |
14121 | break; |
15170 | break; |
14122 | case w_mode: |
15171 | case w_mode: |
14123 | names = names16; |
15172 | names = names16; |
14124 | break; |
15173 | break; |
14125 | case d_mode: |
15174 | case d_mode: |
- | 15175 | case dw_mode: |
|
- | 15176 | case db_mode: |
|
14126 | names = names32; |
15177 | names = names32; |
14127 | break; |
15178 | break; |
14128 | case q_mode: |
15179 | case q_mode: |
14129 | names = names64; |
15180 | names = names64; |
14130 | break; |
15181 | break; |
14131 | case m_mode: |
15182 | case m_mode: |
14132 | case v_bnd_mode: |
15183 | case v_bnd_mode: |
14133 | names = address_mode == mode_64bit ? names64 : names32; |
15184 | names = address_mode == mode_64bit ? names64 : names32; |
14134 | break; |
15185 | break; |
14135 | case bnd_mode: |
15186 | case bnd_mode: |
14136 | names = names_bnd; |
15187 | names = names_bnd; |
14137 | break; |
15188 | break; |
14138 | case stack_v_mode: |
15189 | case stack_v_mode: |
14139 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
15190 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
14140 | { |
15191 | { |
14141 | names = names64; |
15192 | names = names64; |
14142 | break; |
15193 | break; |
14143 | } |
15194 | } |
14144 | bytemode = v_mode; |
15195 | bytemode = v_mode; |
14145 | /* FALLTHRU */ |
15196 | /* FALLTHRU */ |
14146 | case v_mode: |
15197 | case v_mode: |
14147 | case v_swap_mode: |
15198 | case v_swap_mode: |
14148 | case dq_mode: |
15199 | case dq_mode: |
14149 | case dqb_mode: |
15200 | case dqb_mode: |
14150 | case dqd_mode: |
15201 | case dqd_mode: |
14151 | case dqw_mode: |
15202 | case dqw_mode: |
- | 15203 | case dqw_swap_mode: |
|
14152 | USED_REX (REX_W); |
15204 | USED_REX (REX_W); |
14153 | if (rex & REX_W) |
15205 | if (rex & REX_W) |
14154 | names = names64; |
15206 | names = names64; |
14155 | else |
15207 | else |
14156 | { |
15208 | { |
14157 | if ((sizeflag & DFLAG) |
15209 | if ((sizeflag & DFLAG) |
14158 | || (bytemode != v_mode |
15210 | || (bytemode != v_mode |
14159 | && bytemode != v_swap_mode)) |
15211 | && bytemode != v_swap_mode)) |
14160 | names = names32; |
15212 | names = names32; |
14161 | else |
15213 | else |
14162 | names = names16; |
15214 | names = names16; |
14163 | used_prefixes |= (prefixes & PREFIX_DATA); |
15215 | used_prefixes |= (prefixes & PREFIX_DATA); |
14164 | } |
15216 | } |
14165 | break; |
15217 | break; |
- | 15218 | case mask_bd_mode: |
|
14166 | case mask_mode: |
15219 | case mask_mode: |
14167 | names = names_mask; |
15220 | names = names_mask; |
14168 | break; |
15221 | break; |
14169 | case 0: |
15222 | case 0: |
14170 | return; |
15223 | return; |
14171 | default: |
15224 | default: |
14172 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
15225 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
14173 | return; |
15226 | return; |
14174 | } |
15227 | } |
14175 | oappend (names[reg]); |
15228 | oappend (names[reg]); |
14176 | } |
15229 | } |
14177 | 15230 | ||
14178 | static void |
15231 | static void |
14179 | OP_E_memory (int bytemode, int sizeflag) |
15232 | OP_E_memory (int bytemode, int sizeflag) |
14180 | { |
15233 | { |
14181 | bfd_vma disp = 0; |
15234 | bfd_vma disp = 0; |
14182 | int add = (rex & REX_B) ? 8 : 0; |
15235 | int add = (rex & REX_B) ? 8 : 0; |
14183 | int riprel = 0; |
15236 | int riprel = 0; |
14184 | int shift; |
15237 | int shift; |
14185 | 15238 | ||
14186 | if (vex.evex) |
15239 | if (vex.evex) |
14187 | { |
15240 | { |
14188 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ |
15241 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ |
14189 | if (vex.b |
15242 | if (vex.b |
14190 | && bytemode != x_mode |
15243 | && bytemode != x_mode |
- | 15244 | && bytemode != xmmq_mode |
|
14191 | && bytemode != evex_half_bcst_xmmq_mode) |
15245 | && bytemode != evex_half_bcst_xmmq_mode) |
14192 | { |
15246 | { |
14193 | BadOp (); |
15247 | BadOp (); |
14194 | return; |
15248 | return; |
14195 | } |
15249 | } |
14196 | switch (bytemode) |
15250 | switch (bytemode) |
14197 | { |
15251 | { |
- | 15252 | case dqw_mode: |
|
- | 15253 | case dw_mode: |
|
- | 15254 | case dqw_swap_mode: |
|
- | 15255 | shift = 1; |
|
- | 15256 | break; |
|
- | 15257 | case dqb_mode: |
|
- | 15258 | case db_mode: |
|
- | 15259 | shift = 0; |
|
- | 15260 | break; |
|
14198 | case vex_vsib_d_w_dq_mode: |
15261 | case vex_vsib_d_w_dq_mode: |
- | 15262 | case vex_vsib_d_w_d_mode: |
|
- | 15263 | case vex_vsib_q_w_dq_mode: |
|
- | 15264 | case vex_vsib_q_w_d_mode: |
|
14199 | case evex_x_gscat_mode: |
15265 | case evex_x_gscat_mode: |
14200 | case xmm_mdq_mode: |
15266 | case xmm_mdq_mode: |
14201 | shift = vex.w ? 3 : 2; |
15267 | shift = vex.w ? 3 : 2; |
14202 | break; |
15268 | break; |
14203 | case vex_vsib_q_w_dq_mode: |
- | |
14204 | shift = 3; |
- | |
14205 | break; |
- | |
14206 | case x_mode: |
15269 | case x_mode: |
14207 | case evex_half_bcst_xmmq_mode: |
15270 | case evex_half_bcst_xmmq_mode: |
- | 15271 | case xmmq_mode: |
|
14208 | if (vex.b) |
15272 | if (vex.b) |
14209 | { |
15273 | { |
14210 | shift = vex.w ? 3 : 2; |
15274 | shift = vex.w ? 3 : 2; |
14211 | break; |
15275 | break; |
14212 | } |
15276 | } |
14213 | /* Fall through if vex.b == 0. */ |
15277 | /* Fall through if vex.b == 0. */ |
14214 | case xmmqd_mode: |
15278 | case xmmqd_mode: |
14215 | case xmmdw_mode: |
15279 | case xmmdw_mode: |
14216 | case xmmq_mode: |
- | |
14217 | case ymmq_mode: |
15280 | case ymmq_mode: |
14218 | case evex_x_nobcst_mode: |
15281 | case evex_x_nobcst_mode: |
14219 | case x_swap_mode: |
15282 | case x_swap_mode: |
14220 | switch (vex.length) |
15283 | switch (vex.length) |
14221 | { |
15284 | { |
14222 | case 128: |
15285 | case 128: |
14223 | shift = 4; |
15286 | shift = 4; |
14224 | break; |
15287 | break; |
14225 | case 256: |
15288 | case 256: |
14226 | shift = 5; |
15289 | shift = 5; |
14227 | break; |
15290 | break; |
14228 | case 512: |
15291 | case 512: |
14229 | shift = 6; |
15292 | shift = 6; |
14230 | break; |
15293 | break; |
14231 | default: |
15294 | default: |
14232 | abort (); |
15295 | abort (); |
14233 | } |
15296 | } |
14234 | break; |
15297 | break; |
14235 | case ymm_mode: |
15298 | case ymm_mode: |
14236 | shift = 5; |
15299 | shift = 5; |
14237 | break; |
15300 | break; |
14238 | case xmm_mode: |
15301 | case xmm_mode: |
14239 | shift = 4; |
15302 | shift = 4; |
14240 | break; |
15303 | break; |
14241 | case xmm_mq_mode: |
15304 | case xmm_mq_mode: |
14242 | case q_mode: |
15305 | case q_mode: |
14243 | case q_scalar_mode: |
15306 | case q_scalar_mode: |
14244 | case q_swap_mode: |
15307 | case q_swap_mode: |
14245 | case q_scalar_swap_mode: |
15308 | case q_scalar_swap_mode: |
14246 | shift = 3; |
15309 | shift = 3; |
14247 | break; |
15310 | break; |
14248 | case dqd_mode: |
15311 | case dqd_mode: |
14249 | case xmm_md_mode: |
15312 | case xmm_md_mode: |
14250 | case d_mode: |
15313 | case d_mode: |
14251 | case d_scalar_mode: |
15314 | case d_scalar_mode: |
14252 | case d_swap_mode: |
15315 | case d_swap_mode: |
14253 | case d_scalar_swap_mode: |
15316 | case d_scalar_swap_mode: |
14254 | shift = 2; |
15317 | shift = 2; |
14255 | break; |
15318 | break; |
14256 | case xmm_mw_mode: |
15319 | case xmm_mw_mode: |
14257 | shift = 1; |
15320 | shift = 1; |
14258 | break; |
15321 | break; |
14259 | case xmm_mb_mode: |
15322 | case xmm_mb_mode: |
14260 | shift = 0; |
15323 | shift = 0; |
14261 | break; |
15324 | break; |
14262 | default: |
15325 | default: |
14263 | abort (); |
15326 | abort (); |
14264 | } |
15327 | } |
14265 | /* Make necessary corrections to shift for modes that need it. |
15328 | /* Make necessary corrections to shift for modes that need it. |
14266 | For these modes we currently have shift 4, 5 or 6 depending on |
15329 | For these modes we currently have shift 4, 5 or 6 depending on |
14267 | vex.length (it corresponds to xmmword, ymmword or zmmword |
15330 | vex.length (it corresponds to xmmword, ymmword or zmmword |
14268 | operand). We might want to make it 3, 4 or 5 (e.g. for |
15331 | operand). We might want to make it 3, 4 or 5 (e.g. for |
14269 | xmmq_mode). In case of broadcast enabled the corrections |
15332 | xmmq_mode). In case of broadcast enabled the corrections |
14270 | aren't needed, as element size is always 32 or 64 bits. */ |
15333 | aren't needed, as element size is always 32 or 64 bits. */ |
- | 15334 | if (!vex.b |
|
14271 | if (bytemode == xmmq_mode |
15335 | && (bytemode == xmmq_mode |
14272 | || (bytemode == evex_half_bcst_xmmq_mode |
15336 | || bytemode == evex_half_bcst_xmmq_mode)) |
14273 | && !vex.b)) |
- | |
14274 | shift -= 1; |
15337 | shift -= 1; |
14275 | else if (bytemode == xmmqd_mode) |
15338 | else if (bytemode == xmmqd_mode) |
14276 | shift -= 2; |
15339 | shift -= 2; |
14277 | else if (bytemode == xmmdw_mode) |
15340 | else if (bytemode == xmmdw_mode) |
14278 | shift -= 3; |
15341 | shift -= 3; |
- | 15342 | else if (bytemode == ymmq_mode && vex.length == 128) |
|
- | 15343 | shift -= 1; |
|
14279 | } |
15344 | } |
14280 | else |
15345 | else |
14281 | shift = 0; |
15346 | shift = 0; |
14282 | 15347 | ||
14283 | USED_REX (REX_B); |
15348 | USED_REX (REX_B); |
14284 | if (intel_syntax) |
15349 | if (intel_syntax) |
14285 | intel_operand_size (bytemode, sizeflag); |
15350 | intel_operand_size (bytemode, sizeflag); |
14286 | append_seg (); |
15351 | append_seg (); |
14287 | 15352 | ||
14288 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
15353 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
14289 | { |
15354 | { |
14290 | /* 32/64 bit address mode */ |
15355 | /* 32/64 bit address mode */ |
14291 | int havedisp; |
15356 | int havedisp; |
14292 | int havesib; |
15357 | int havesib; |
14293 | int havebase; |
15358 | int havebase; |
14294 | int haveindex; |
15359 | int haveindex; |
14295 | int needindex; |
15360 | int needindex; |
14296 | int base, rbase; |
15361 | int base, rbase; |
14297 | int vindex = 0; |
15362 | int vindex = 0; |
14298 | int scale = 0; |
15363 | int scale = 0; |
14299 | int addr32flag = !((sizeflag & AFLAG) |
15364 | int addr32flag = !((sizeflag & AFLAG) |
14300 | || bytemode == v_bnd_mode |
15365 | || bytemode == v_bnd_mode |
14301 | || bytemode == bnd_mode); |
15366 | || bytemode == bnd_mode); |
14302 | const char **indexes64 = names64; |
15367 | const char **indexes64 = names64; |
14303 | const char **indexes32 = names32; |
15368 | const char **indexes32 = names32; |
14304 | 15369 | ||
14305 | havesib = 0; |
15370 | havesib = 0; |
14306 | havebase = 1; |
15371 | havebase = 1; |
14307 | haveindex = 0; |
15372 | haveindex = 0; |
14308 | base = modrm.rm; |
15373 | base = modrm.rm; |
14309 | 15374 | ||
14310 | if (base == 4) |
15375 | if (base == 4) |
14311 | { |
15376 | { |
14312 | havesib = 1; |
15377 | havesib = 1; |
14313 | vindex = sib.index; |
15378 | vindex = sib.index; |
14314 | USED_REX (REX_X); |
15379 | USED_REX (REX_X); |
14315 | if (rex & REX_X) |
15380 | if (rex & REX_X) |
14316 | vindex += 8; |
15381 | vindex += 8; |
14317 | switch (bytemode) |
15382 | switch (bytemode) |
14318 | { |
15383 | { |
14319 | case vex_vsib_d_w_dq_mode: |
15384 | case vex_vsib_d_w_dq_mode: |
- | 15385 | case vex_vsib_d_w_d_mode: |
|
14320 | case vex_vsib_q_w_dq_mode: |
15386 | case vex_vsib_q_w_dq_mode: |
- | 15387 | case vex_vsib_q_w_d_mode: |
|
14321 | if (!need_vex) |
15388 | if (!need_vex) |
14322 | abort (); |
15389 | abort (); |
14323 | if (vex.evex) |
15390 | if (vex.evex) |
14324 | { |
15391 | { |
14325 | if (!vex.v) |
15392 | if (!vex.v) |
14326 | vindex += 16; |
15393 | vindex += 16; |
14327 | } |
15394 | } |
14328 | 15395 | ||
14329 | haveindex = 1; |
15396 | haveindex = 1; |
14330 | switch (vex.length) |
15397 | switch (vex.length) |
14331 | { |
15398 | { |
14332 | case 128: |
15399 | case 128: |
14333 | indexes64 = indexes32 = names_xmm; |
15400 | indexes64 = indexes32 = names_xmm; |
14334 | break; |
15401 | break; |
14335 | case 256: |
15402 | case 256: |
- | 15403 | if (!vex.w |
|
- | 15404 | || bytemode == vex_vsib_q_w_dq_mode |
|
14336 | if (!vex.w || bytemode == vex_vsib_q_w_dq_mode) |
15405 | || bytemode == vex_vsib_q_w_d_mode) |
14337 | indexes64 = indexes32 = names_ymm; |
15406 | indexes64 = indexes32 = names_ymm; |
14338 | else |
15407 | else |
14339 | indexes64 = indexes32 = names_xmm; |
15408 | indexes64 = indexes32 = names_xmm; |
14340 | break; |
15409 | break; |
14341 | case 512: |
15410 | case 512: |
- | 15411 | if (!vex.w |
|
- | 15412 | || bytemode == vex_vsib_q_w_dq_mode |
|
14342 | if (!vex.w || bytemode == vex_vsib_q_w_dq_mode) |
15413 | || bytemode == vex_vsib_q_w_d_mode) |
14343 | indexes64 = indexes32 = names_zmm; |
15414 | indexes64 = indexes32 = names_zmm; |
14344 | else |
15415 | else |
14345 | indexes64 = indexes32 = names_ymm; |
15416 | indexes64 = indexes32 = names_ymm; |
14346 | break; |
15417 | break; |
14347 | default: |
15418 | default: |
14348 | abort (); |
15419 | abort (); |
14349 | } |
15420 | } |
14350 | break; |
15421 | break; |
14351 | default: |
15422 | default: |
14352 | haveindex = vindex != 4; |
15423 | haveindex = vindex != 4; |
14353 | break; |
15424 | break; |
14354 | } |
15425 | } |
14355 | scale = sib.scale; |
15426 | scale = sib.scale; |
14356 | base = sib.base; |
15427 | base = sib.base; |
14357 | codep++; |
15428 | codep++; |
14358 | } |
15429 | } |
14359 | rbase = base + add; |
15430 | rbase = base + add; |
14360 | 15431 | ||
14361 | switch (modrm.mod) |
15432 | switch (modrm.mod) |
14362 | { |
15433 | { |
14363 | case 0: |
15434 | case 0: |
14364 | if (base == 5) |
15435 | if (base == 5) |
14365 | { |
15436 | { |
14366 | havebase = 0; |
15437 | havebase = 0; |
14367 | if (address_mode == mode_64bit && !havesib) |
15438 | if (address_mode == mode_64bit && !havesib) |
14368 | riprel = 1; |
15439 | riprel = 1; |
14369 | disp = get32s (); |
15440 | disp = get32s (); |
14370 | } |
15441 | } |
14371 | break; |
15442 | break; |
14372 | case 1: |
15443 | case 1: |
14373 | FETCH_DATA (the_info, codep + 1); |
15444 | FETCH_DATA (the_info, codep + 1); |
14374 | disp = *codep++; |
15445 | disp = *codep++; |
14375 | if ((disp & 0x80) != 0) |
15446 | if ((disp & 0x80) != 0) |
14376 | disp -= 0x100; |
15447 | disp -= 0x100; |
14377 | if (vex.evex && shift > 0) |
15448 | if (vex.evex && shift > 0) |
14378 | disp <<= shift; |
15449 | disp <<= shift; |
14379 | break; |
15450 | break; |
14380 | case 2: |
15451 | case 2: |
14381 | disp = get32s (); |
15452 | disp = get32s (); |
14382 | break; |
15453 | break; |
14383 | } |
15454 | } |
14384 | 15455 | ||
14385 | /* In 32bit mode, we need index register to tell [offset] from |
15456 | /* In 32bit mode, we need index register to tell [offset] from |
14386 | [eiz*1 + offset]. */ |
15457 | [eiz*1 + offset]. */ |
14387 | needindex = (havesib |
15458 | needindex = (havesib |
14388 | && !havebase |
15459 | && !havebase |
14389 | && !haveindex |
15460 | && !haveindex |
14390 | && address_mode == mode_32bit); |
15461 | && address_mode == mode_32bit); |
14391 | havedisp = (havebase |
15462 | havedisp = (havebase |
14392 | || needindex |
15463 | || needindex |
14393 | || (havesib && (haveindex || scale != 0))); |
15464 | || (havesib && (haveindex || scale != 0))); |
14394 | 15465 | ||
14395 | if (!intel_syntax) |
15466 | if (!intel_syntax) |
14396 | if (modrm.mod != 0 || base == 5) |
15467 | if (modrm.mod != 0 || base == 5) |
14397 | { |
15468 | { |
14398 | if (havedisp || riprel) |
15469 | if (havedisp || riprel) |
14399 | print_displacement (scratchbuf, disp); |
15470 | print_displacement (scratchbuf, disp); |
14400 | else |
15471 | else |
14401 | print_operand_value (scratchbuf, 1, disp); |
15472 | print_operand_value (scratchbuf, 1, disp); |
14402 | oappend (scratchbuf); |
15473 | oappend (scratchbuf); |
14403 | if (riprel) |
15474 | if (riprel) |
14404 | { |
15475 | { |
14405 | set_op (disp, 1); |
15476 | set_op (disp, 1); |
14406 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
15477 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
14407 | } |
15478 | } |
14408 | } |
15479 | } |
14409 | 15480 | ||
14410 | if ((havebase || haveindex || riprel) |
15481 | if ((havebase || haveindex || riprel) |
14411 | && (bytemode != v_bnd_mode) |
15482 | && (bytemode != v_bnd_mode) |
14412 | && (bytemode != bnd_mode)) |
15483 | && (bytemode != bnd_mode)) |
14413 | used_prefixes |= PREFIX_ADDR; |
15484 | used_prefixes |= PREFIX_ADDR; |
14414 | 15485 | ||
14415 | if (havedisp || (intel_syntax && riprel)) |
15486 | if (havedisp || (intel_syntax && riprel)) |
14416 | { |
15487 | { |
14417 | *obufp++ = open_char; |
15488 | *obufp++ = open_char; |
14418 | if (intel_syntax && riprel) |
15489 | if (intel_syntax && riprel) |
14419 | { |
15490 | { |
14420 | set_op (disp, 1); |
15491 | set_op (disp, 1); |
14421 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
15492 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
14422 | } |
15493 | } |
14423 | *obufp = '\0'; |
15494 | *obufp = '\0'; |
14424 | if (havebase) |
15495 | if (havebase) |
14425 | oappend (address_mode == mode_64bit && !addr32flag |
15496 | oappend (address_mode == mode_64bit && !addr32flag |
14426 | ? names64[rbase] : names32[rbase]); |
15497 | ? names64[rbase] : names32[rbase]); |
14427 | if (havesib) |
15498 | if (havesib) |
14428 | { |
15499 | { |
14429 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
15500 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14430 | print index to tell base + index from base. */ |
15501 | print index to tell base + index from base. */ |
14431 | if (scale != 0 |
15502 | if (scale != 0 |
14432 | || needindex |
15503 | || needindex |
14433 | || haveindex |
15504 | || haveindex |
14434 | || (havebase && base != ESP_REG_NUM)) |
15505 | || (havebase && base != ESP_REG_NUM)) |
14435 | { |
15506 | { |
14436 | if (!intel_syntax || havebase) |
15507 | if (!intel_syntax || havebase) |
14437 | { |
15508 | { |
14438 | *obufp++ = separator_char; |
15509 | *obufp++ = separator_char; |
14439 | *obufp = '\0'; |
15510 | *obufp = '\0'; |
14440 | } |
15511 | } |
14441 | if (haveindex) |
15512 | if (haveindex) |
14442 | oappend (address_mode == mode_64bit && !addr32flag |
15513 | oappend (address_mode == mode_64bit && !addr32flag |
14443 | ? indexes64[vindex] : indexes32[vindex]); |
15514 | ? indexes64[vindex] : indexes32[vindex]); |
14444 | else |
15515 | else |
14445 | oappend (address_mode == mode_64bit && !addr32flag |
15516 | oappend (address_mode == mode_64bit && !addr32flag |
14446 | ? index64 : index32); |
15517 | ? index64 : index32); |
14447 | 15518 | ||
14448 | *obufp++ = scale_char; |
15519 | *obufp++ = scale_char; |
14449 | *obufp = '\0'; |
15520 | *obufp = '\0'; |
14450 | sprintf (scratchbuf, "%d", 1 << scale); |
15521 | sprintf (scratchbuf, "%d", 1 << scale); |
14451 | oappend (scratchbuf); |
15522 | oappend (scratchbuf); |
14452 | } |
15523 | } |
14453 | } |
15524 | } |
14454 | if (intel_syntax |
15525 | if (intel_syntax |
14455 | && (disp || modrm.mod != 0 || base == 5)) |
15526 | && (disp || modrm.mod != 0 || base == 5)) |
14456 | { |
15527 | { |
14457 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
15528 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
14458 | { |
15529 | { |
14459 | *obufp++ = '+'; |
15530 | *obufp++ = '+'; |
14460 | *obufp = '\0'; |
15531 | *obufp = '\0'; |
14461 | } |
15532 | } |
14462 | else if (modrm.mod != 1 && disp != -disp) |
15533 | else if (modrm.mod != 1 && disp != -disp) |
14463 | { |
15534 | { |
14464 | *obufp++ = '-'; |
15535 | *obufp++ = '-'; |
14465 | *obufp = '\0'; |
15536 | *obufp = '\0'; |
14466 | disp = - (bfd_signed_vma) disp; |
15537 | disp = - (bfd_signed_vma) disp; |
14467 | } |
15538 | } |
14468 | 15539 | ||
14469 | if (havedisp) |
15540 | if (havedisp) |
14470 | print_displacement (scratchbuf, disp); |
15541 | print_displacement (scratchbuf, disp); |
14471 | else |
15542 | else |
14472 | print_operand_value (scratchbuf, 1, disp); |
15543 | print_operand_value (scratchbuf, 1, disp); |
14473 | oappend (scratchbuf); |
15544 | oappend (scratchbuf); |
14474 | } |
15545 | } |
14475 | 15546 | ||
14476 | *obufp++ = close_char; |
15547 | *obufp++ = close_char; |
14477 | *obufp = '\0'; |
15548 | *obufp = '\0'; |
14478 | } |
15549 | } |
14479 | else if (intel_syntax) |
15550 | else if (intel_syntax) |
14480 | { |
15551 | { |
14481 | if (modrm.mod != 0 || base == 5) |
15552 | if (modrm.mod != 0 || base == 5) |
14482 | { |
15553 | { |
14483 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
- | |
14484 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) |
- | |
14485 | ; |
- | |
14486 | else |
15554 | if (!active_seg_prefix) |
14487 | { |
15555 | { |
14488 | oappend (names_seg[ds_reg - es_reg]); |
15556 | oappend (names_seg[ds_reg - es_reg]); |
14489 | oappend (":"); |
15557 | oappend (":"); |
14490 | } |
15558 | } |
14491 | print_operand_value (scratchbuf, 1, disp); |
15559 | print_operand_value (scratchbuf, 1, disp); |
14492 | oappend (scratchbuf); |
15560 | oappend (scratchbuf); |
14493 | } |
15561 | } |
14494 | } |
15562 | } |
14495 | } |
15563 | } |
14496 | else |
15564 | else |
14497 | { |
15565 | { |
14498 | /* 16 bit address mode */ |
15566 | /* 16 bit address mode */ |
14499 | used_prefixes |= prefixes & PREFIX_ADDR; |
15567 | used_prefixes |= prefixes & PREFIX_ADDR; |
14500 | switch (modrm.mod) |
15568 | switch (modrm.mod) |
14501 | { |
15569 | { |
14502 | case 0: |
15570 | case 0: |
14503 | if (modrm.rm == 6) |
15571 | if (modrm.rm == 6) |
14504 | { |
15572 | { |
14505 | disp = get16 (); |
15573 | disp = get16 (); |
14506 | if ((disp & 0x8000) != 0) |
15574 | if ((disp & 0x8000) != 0) |
14507 | disp -= 0x10000; |
15575 | disp -= 0x10000; |
14508 | } |
15576 | } |
14509 | break; |
15577 | break; |
14510 | case 1: |
15578 | case 1: |
14511 | FETCH_DATA (the_info, codep + 1); |
15579 | FETCH_DATA (the_info, codep + 1); |
14512 | disp = *codep++; |
15580 | disp = *codep++; |
14513 | if ((disp & 0x80) != 0) |
15581 | if ((disp & 0x80) != 0) |
14514 | disp -= 0x100; |
15582 | disp -= 0x100; |
14515 | break; |
15583 | break; |
14516 | case 2: |
15584 | case 2: |
14517 | disp = get16 (); |
15585 | disp = get16 (); |
14518 | if ((disp & 0x8000) != 0) |
15586 | if ((disp & 0x8000) != 0) |
14519 | disp -= 0x10000; |
15587 | disp -= 0x10000; |
14520 | break; |
15588 | break; |
14521 | } |
15589 | } |
14522 | 15590 | ||
14523 | if (!intel_syntax) |
15591 | if (!intel_syntax) |
14524 | if (modrm.mod != 0 || modrm.rm == 6) |
15592 | if (modrm.mod != 0 || modrm.rm == 6) |
14525 | { |
15593 | { |
14526 | print_displacement (scratchbuf, disp); |
15594 | print_displacement (scratchbuf, disp); |
14527 | oappend (scratchbuf); |
15595 | oappend (scratchbuf); |
14528 | } |
15596 | } |
14529 | 15597 | ||
14530 | if (modrm.mod != 0 || modrm.rm != 6) |
15598 | if (modrm.mod != 0 || modrm.rm != 6) |
14531 | { |
15599 | { |
14532 | *obufp++ = open_char; |
15600 | *obufp++ = open_char; |
14533 | *obufp = '\0'; |
15601 | *obufp = '\0'; |
14534 | oappend (index16[modrm.rm]); |
15602 | oappend (index16[modrm.rm]); |
14535 | if (intel_syntax |
15603 | if (intel_syntax |
14536 | && (disp || modrm.mod != 0 || modrm.rm == 6)) |
15604 | && (disp || modrm.mod != 0 || modrm.rm == 6)) |
14537 | { |
15605 | { |
14538 | if ((bfd_signed_vma) disp >= 0) |
15606 | if ((bfd_signed_vma) disp >= 0) |
14539 | { |
15607 | { |
14540 | *obufp++ = '+'; |
15608 | *obufp++ = '+'; |
14541 | *obufp = '\0'; |
15609 | *obufp = '\0'; |
14542 | } |
15610 | } |
14543 | else if (modrm.mod != 1) |
15611 | else if (modrm.mod != 1) |
14544 | { |
15612 | { |
14545 | *obufp++ = '-'; |
15613 | *obufp++ = '-'; |
14546 | *obufp = '\0'; |
15614 | *obufp = '\0'; |
14547 | disp = - (bfd_signed_vma) disp; |
15615 | disp = - (bfd_signed_vma) disp; |
14548 | } |
15616 | } |
14549 | 15617 | ||
14550 | print_displacement (scratchbuf, disp); |
15618 | print_displacement (scratchbuf, disp); |
14551 | oappend (scratchbuf); |
15619 | oappend (scratchbuf); |
14552 | } |
15620 | } |
14553 | 15621 | ||
14554 | *obufp++ = close_char; |
15622 | *obufp++ = close_char; |
14555 | *obufp = '\0'; |
15623 | *obufp = '\0'; |
14556 | } |
15624 | } |
14557 | else if (intel_syntax) |
15625 | else if (intel_syntax) |
14558 | { |
15626 | { |
14559 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
- | |
14560 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) |
15627 | if (!active_seg_prefix) |
14561 | ; |
- | |
14562 | else |
- | |
14563 | { |
15628 | { |
14564 | oappend (names_seg[ds_reg - es_reg]); |
15629 | oappend (names_seg[ds_reg - es_reg]); |
14565 | oappend (":"); |
15630 | oappend (":"); |
14566 | } |
15631 | } |
14567 | print_operand_value (scratchbuf, 1, disp & 0xffff); |
15632 | print_operand_value (scratchbuf, 1, disp & 0xffff); |
14568 | oappend (scratchbuf); |
15633 | oappend (scratchbuf); |
14569 | } |
15634 | } |
14570 | } |
15635 | } |
14571 | if (vex.evex && vex.b |
15636 | if (vex.evex && vex.b |
14572 | && (bytemode == x_mode |
15637 | && (bytemode == x_mode |
- | 15638 | || bytemode == xmmq_mode |
|
14573 | || bytemode == evex_half_bcst_xmmq_mode)) |
15639 | || bytemode == evex_half_bcst_xmmq_mode)) |
14574 | { |
15640 | { |
- | 15641 | if (vex.w |
|
- | 15642 | || bytemode == xmmq_mode |
|
14575 | if (vex.w || bytemode == evex_half_bcst_xmmq_mode) |
15643 | || bytemode == evex_half_bcst_xmmq_mode) |
- | 15644 | { |
|
- | 15645 | switch (vex.length) |
|
- | 15646 | { |
|
- | 15647 | case 128: |
|
- | 15648 | oappend ("{1to2}"); |
|
- | 15649 | break; |
|
- | 15650 | case 256: |
|
- | 15651 | oappend ("{1to4}"); |
|
- | 15652 | break; |
|
- | 15653 | case 512: |
|
14576 | oappend ("{1to8}"); |
15654 | oappend ("{1to8}"); |
- | 15655 | break; |
|
- | 15656 | default: |
|
- | 15657 | abort (); |
|
- | 15658 | } |
|
- | 15659 | } |
|
14577 | else |
15660 | else |
- | 15661 | { |
|
- | 15662 | switch (vex.length) |
|
- | 15663 | { |
|
- | 15664 | case 128: |
|
- | 15665 | oappend ("{1to4}"); |
|
- | 15666 | break; |
|
- | 15667 | case 256: |
|
- | 15668 | oappend ("{1to8}"); |
|
- | 15669 | break; |
|
- | 15670 | case 512: |
|
14578 | oappend ("{1to16}"); |
15671 | oappend ("{1to16}"); |
- | 15672 | break; |
|
- | 15673 | default: |
|
- | 15674 | abort (); |
|
- | 15675 | } |
|
- | 15676 | } |
|
14579 | } |
15677 | } |
14580 | } |
15678 | } |
14581 | 15679 | ||
14582 | static void |
15680 | static void |
14583 | OP_E (int bytemode, int sizeflag) |
15681 | OP_E (int bytemode, int sizeflag) |
14584 | { |
15682 | { |
14585 | /* Skip mod/rm byte. */ |
15683 | /* Skip mod/rm byte. */ |
14586 | MODRM_CHECK; |
15684 | MODRM_CHECK; |
14587 | codep++; |
15685 | codep++; |
14588 | 15686 | ||
14589 | if (modrm.mod == 3) |
15687 | if (modrm.mod == 3) |
14590 | OP_E_register (bytemode, sizeflag); |
15688 | OP_E_register (bytemode, sizeflag); |
14591 | else |
15689 | else |
14592 | OP_E_memory (bytemode, sizeflag); |
15690 | OP_E_memory (bytemode, sizeflag); |
14593 | } |
15691 | } |
14594 | 15692 | ||
14595 | static void |
15693 | static void |
14596 | OP_G (int bytemode, int sizeflag) |
15694 | OP_G (int bytemode, int sizeflag) |
14597 | { |
15695 | { |
14598 | int add = 0; |
15696 | int add = 0; |
14599 | USED_REX (REX_R); |
15697 | USED_REX (REX_R); |
14600 | if (rex & REX_R) |
15698 | if (rex & REX_R) |
14601 | add += 8; |
15699 | add += 8; |
14602 | switch (bytemode) |
15700 | switch (bytemode) |
14603 | { |
15701 | { |
14604 | case b_mode: |
15702 | case b_mode: |
14605 | USED_REX (0); |
15703 | USED_REX (0); |
14606 | if (rex) |
15704 | if (rex) |
14607 | oappend (names8rex[modrm.reg + add]); |
15705 | oappend (names8rex[modrm.reg + add]); |
14608 | else |
15706 | else |
14609 | oappend (names8[modrm.reg + add]); |
15707 | oappend (names8[modrm.reg + add]); |
14610 | break; |
15708 | break; |
14611 | case w_mode: |
15709 | case w_mode: |
14612 | oappend (names16[modrm.reg + add]); |
15710 | oappend (names16[modrm.reg + add]); |
14613 | break; |
15711 | break; |
14614 | case d_mode: |
15712 | case d_mode: |
- | 15713 | case db_mode: |
|
- | 15714 | case dw_mode: |
|
14615 | oappend (names32[modrm.reg + add]); |
15715 | oappend (names32[modrm.reg + add]); |
14616 | break; |
15716 | break; |
14617 | case q_mode: |
15717 | case q_mode: |
14618 | oappend (names64[modrm.reg + add]); |
15718 | oappend (names64[modrm.reg + add]); |
14619 | break; |
15719 | break; |
14620 | case bnd_mode: |
15720 | case bnd_mode: |
14621 | oappend (names_bnd[modrm.reg]); |
15721 | oappend (names_bnd[modrm.reg]); |
14622 | break; |
15722 | break; |
14623 | case v_mode: |
15723 | case v_mode: |
14624 | case dq_mode: |
15724 | case dq_mode: |
14625 | case dqb_mode: |
15725 | case dqb_mode: |
14626 | case dqd_mode: |
15726 | case dqd_mode: |
14627 | case dqw_mode: |
15727 | case dqw_mode: |
- | 15728 | case dqw_swap_mode: |
|
14628 | USED_REX (REX_W); |
15729 | USED_REX (REX_W); |
14629 | if (rex & REX_W) |
15730 | if (rex & REX_W) |
14630 | oappend (names64[modrm.reg + add]); |
15731 | oappend (names64[modrm.reg + add]); |
14631 | else |
15732 | else |
14632 | { |
15733 | { |
14633 | if ((sizeflag & DFLAG) || bytemode != v_mode) |
15734 | if ((sizeflag & DFLAG) || bytemode != v_mode) |
14634 | oappend (names32[modrm.reg + add]); |
15735 | oappend (names32[modrm.reg + add]); |
14635 | else |
15736 | else |
14636 | oappend (names16[modrm.reg + add]); |
15737 | oappend (names16[modrm.reg + add]); |
14637 | used_prefixes |= (prefixes & PREFIX_DATA); |
15738 | used_prefixes |= (prefixes & PREFIX_DATA); |
14638 | } |
15739 | } |
14639 | break; |
15740 | break; |
14640 | case m_mode: |
15741 | case m_mode: |
14641 | if (address_mode == mode_64bit) |
15742 | if (address_mode == mode_64bit) |
14642 | oappend (names64[modrm.reg + add]); |
15743 | oappend (names64[modrm.reg + add]); |
14643 | else |
15744 | else |
14644 | oappend (names32[modrm.reg + add]); |
15745 | oappend (names32[modrm.reg + add]); |
14645 | break; |
15746 | break; |
- | 15747 | case mask_bd_mode: |
|
14646 | case mask_mode: |
15748 | case mask_mode: |
14647 | oappend (names_mask[modrm.reg + add]); |
15749 | oappend (names_mask[modrm.reg + add]); |
14648 | break; |
15750 | break; |
14649 | default: |
15751 | default: |
14650 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
15752 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
14651 | break; |
15753 | break; |
14652 | } |
15754 | } |
14653 | } |
15755 | } |
14654 | 15756 | ||
14655 | static bfd_vma |
15757 | static bfd_vma |
14656 | get64 (void) |
15758 | get64 (void) |
14657 | { |
15759 | { |
14658 | bfd_vma x; |
15760 | bfd_vma x; |
14659 | #ifdef BFD64 |
15761 | #ifdef BFD64 |
14660 | unsigned int a; |
15762 | unsigned int a; |
14661 | unsigned int b; |
15763 | unsigned int b; |
14662 | 15764 | ||
14663 | FETCH_DATA (the_info, codep + 8); |
15765 | FETCH_DATA (the_info, codep + 8); |
14664 | a = *codep++ & 0xff; |
15766 | a = *codep++ & 0xff; |
14665 | a |= (*codep++ & 0xff) << 8; |
15767 | a |= (*codep++ & 0xff) << 8; |
14666 | a |= (*codep++ & 0xff) << 16; |
15768 | a |= (*codep++ & 0xff) << 16; |
14667 | a |= (*codep++ & 0xff) << 24; |
15769 | a |= (*codep++ & 0xffu) << 24; |
14668 | b = *codep++ & 0xff; |
15770 | b = *codep++ & 0xff; |
14669 | b |= (*codep++ & 0xff) << 8; |
15771 | b |= (*codep++ & 0xff) << 8; |
14670 | b |= (*codep++ & 0xff) << 16; |
15772 | b |= (*codep++ & 0xff) << 16; |
14671 | b |= (*codep++ & 0xff) << 24; |
15773 | b |= (*codep++ & 0xffu) << 24; |
14672 | x = a + ((bfd_vma) b << 32); |
15774 | x = a + ((bfd_vma) b << 32); |
14673 | #else |
15775 | #else |
14674 | abort (); |
15776 | abort (); |
14675 | x = 0; |
15777 | x = 0; |
14676 | #endif |
15778 | #endif |
14677 | return x; |
15779 | return x; |
14678 | } |
15780 | } |
14679 | 15781 | ||
14680 | static bfd_signed_vma |
15782 | static bfd_signed_vma |
14681 | get32 (void) |
15783 | get32 (void) |
14682 | { |
15784 | { |
14683 | bfd_signed_vma x = 0; |
15785 | bfd_signed_vma x = 0; |
14684 | 15786 | ||
14685 | FETCH_DATA (the_info, codep + 4); |
15787 | FETCH_DATA (the_info, codep + 4); |
14686 | x = *codep++ & (bfd_signed_vma) 0xff; |
15788 | x = *codep++ & (bfd_signed_vma) 0xff; |
14687 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; |
15789 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; |
14688 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; |
15790 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; |
14689 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; |
15791 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; |
14690 | return x; |
15792 | return x; |
14691 | } |
15793 | } |
14692 | 15794 | ||
14693 | static bfd_signed_vma |
15795 | static bfd_signed_vma |
14694 | get32s (void) |
15796 | get32s (void) |
14695 | { |
15797 | { |
14696 | bfd_signed_vma x = 0; |
15798 | bfd_signed_vma x = 0; |
14697 | 15799 | ||
14698 | FETCH_DATA (the_info, codep + 4); |
15800 | FETCH_DATA (the_info, codep + 4); |
14699 | x = *codep++ & (bfd_signed_vma) 0xff; |
15801 | x = *codep++ & (bfd_signed_vma) 0xff; |
14700 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; |
15802 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; |
14701 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; |
15803 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; |
14702 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; |
15804 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; |
14703 | 15805 | ||
14704 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); |
15806 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); |
14705 | 15807 | ||
14706 | return x; |
15808 | return x; |
14707 | } |
15809 | } |
14708 | 15810 | ||
14709 | static int |
15811 | static int |
14710 | get16 (void) |
15812 | get16 (void) |
14711 | { |
15813 | { |
14712 | int x = 0; |
15814 | int x = 0; |
14713 | 15815 | ||
14714 | FETCH_DATA (the_info, codep + 2); |
15816 | FETCH_DATA (the_info, codep + 2); |
14715 | x = *codep++ & 0xff; |
15817 | x = *codep++ & 0xff; |
14716 | x |= (*codep++ & 0xff) << 8; |
15818 | x |= (*codep++ & 0xff) << 8; |
14717 | return x; |
15819 | return x; |
14718 | } |
15820 | } |
14719 | 15821 | ||
14720 | static void |
15822 | static void |
14721 | set_op (bfd_vma op, int riprel) |
15823 | set_op (bfd_vma op, int riprel) |
14722 | { |
15824 | { |
14723 | op_index[op_ad] = op_ad; |
15825 | op_index[op_ad] = op_ad; |
14724 | if (address_mode == mode_64bit) |
15826 | if (address_mode == mode_64bit) |
14725 | { |
15827 | { |
14726 | op_address[op_ad] = op; |
15828 | op_address[op_ad] = op; |
14727 | op_riprel[op_ad] = riprel; |
15829 | op_riprel[op_ad] = riprel; |
14728 | } |
15830 | } |
14729 | else |
15831 | else |
14730 | { |
15832 | { |
14731 | /* Mask to get a 32-bit address. */ |
15833 | /* Mask to get a 32-bit address. */ |
14732 | op_address[op_ad] = op & 0xffffffff; |
15834 | op_address[op_ad] = op & 0xffffffff; |
14733 | op_riprel[op_ad] = riprel & 0xffffffff; |
15835 | op_riprel[op_ad] = riprel & 0xffffffff; |
14734 | } |
15836 | } |
14735 | } |
15837 | } |
14736 | 15838 | ||
14737 | static void |
15839 | static void |
14738 | OP_REG (int code, int sizeflag) |
15840 | OP_REG (int code, int sizeflag) |
14739 | { |
15841 | { |
14740 | const char *s; |
15842 | const char *s; |
14741 | int add; |
15843 | int add; |
14742 | 15844 | ||
14743 | switch (code) |
15845 | switch (code) |
14744 | { |
15846 | { |
14745 | case es_reg: case ss_reg: case cs_reg: |
15847 | case es_reg: case ss_reg: case cs_reg: |
14746 | case ds_reg: case fs_reg: case gs_reg: |
15848 | case ds_reg: case fs_reg: case gs_reg: |
14747 | oappend (names_seg[code - es_reg]); |
15849 | oappend (names_seg[code - es_reg]); |
14748 | return; |
15850 | return; |
14749 | } |
15851 | } |
14750 | 15852 | ||
14751 | USED_REX (REX_B); |
15853 | USED_REX (REX_B); |
14752 | if (rex & REX_B) |
15854 | if (rex & REX_B) |
14753 | add = 8; |
15855 | add = 8; |
14754 | else |
15856 | else |
14755 | add = 0; |
15857 | add = 0; |
14756 | 15858 | ||
14757 | switch (code) |
15859 | switch (code) |
14758 | { |
15860 | { |
14759 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15861 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14760 | case sp_reg: case bp_reg: case si_reg: case di_reg: |
15862 | case sp_reg: case bp_reg: case si_reg: case di_reg: |
14761 | s = names16[code - ax_reg + add]; |
15863 | s = names16[code - ax_reg + add]; |
14762 | break; |
15864 | break; |
14763 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15865 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14764 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: |
15866 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: |
14765 | USED_REX (0); |
15867 | USED_REX (0); |
14766 | if (rex) |
15868 | if (rex) |
14767 | s = names8rex[code - al_reg + add]; |
15869 | s = names8rex[code - al_reg + add]; |
14768 | else |
15870 | else |
14769 | s = names8[code - al_reg]; |
15871 | s = names8[code - al_reg]; |
14770 | break; |
15872 | break; |
14771 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15873 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14772 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: |
15874 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: |
14773 | if (address_mode == mode_64bit |
15875 | if (address_mode == mode_64bit |
14774 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
15876 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
14775 | { |
15877 | { |
14776 | s = names64[code - rAX_reg + add]; |
15878 | s = names64[code - rAX_reg + add]; |
14777 | break; |
15879 | break; |
14778 | } |
15880 | } |
14779 | code += eAX_reg - rAX_reg; |
15881 | code += eAX_reg - rAX_reg; |
14780 | /* Fall through. */ |
15882 | /* Fall through. */ |
14781 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15883 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14782 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: |
15884 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: |
14783 | USED_REX (REX_W); |
15885 | USED_REX (REX_W); |
14784 | if (rex & REX_W) |
15886 | if (rex & REX_W) |
14785 | s = names64[code - eAX_reg + add]; |
15887 | s = names64[code - eAX_reg + add]; |
14786 | else |
15888 | else |
14787 | { |
15889 | { |
14788 | if (sizeflag & DFLAG) |
15890 | if (sizeflag & DFLAG) |
14789 | s = names32[code - eAX_reg + add]; |
15891 | s = names32[code - eAX_reg + add]; |
14790 | else |
15892 | else |
14791 | s = names16[code - eAX_reg + add]; |
15893 | s = names16[code - eAX_reg + add]; |
14792 | used_prefixes |= (prefixes & PREFIX_DATA); |
15894 | used_prefixes |= (prefixes & PREFIX_DATA); |
14793 | } |
15895 | } |
14794 | break; |
15896 | break; |
14795 | default: |
15897 | default: |
14796 | s = INTERNAL_DISASSEMBLER_ERROR; |
15898 | s = INTERNAL_DISASSEMBLER_ERROR; |
14797 | break; |
15899 | break; |
14798 | } |
15900 | } |
14799 | oappend (s); |
15901 | oappend (s); |
14800 | } |
15902 | } |
14801 | 15903 | ||
14802 | static void |
15904 | static void |
14803 | OP_IMREG (int code, int sizeflag) |
15905 | OP_IMREG (int code, int sizeflag) |
14804 | { |
15906 | { |
14805 | const char *s; |
15907 | const char *s; |
14806 | 15908 | ||
14807 | switch (code) |
15909 | switch (code) |
14808 | { |
15910 | { |
14809 | case indir_dx_reg: |
15911 | case indir_dx_reg: |
14810 | if (intel_syntax) |
15912 | if (intel_syntax) |
14811 | s = "dx"; |
15913 | s = "dx"; |
14812 | else |
15914 | else |
14813 | s = "(%dx)"; |
15915 | s = "(%dx)"; |
14814 | break; |
15916 | break; |
14815 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15917 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14816 | case sp_reg: case bp_reg: case si_reg: case di_reg: |
15918 | case sp_reg: case bp_reg: case si_reg: case di_reg: |
14817 | s = names16[code - ax_reg]; |
15919 | s = names16[code - ax_reg]; |
14818 | break; |
15920 | break; |
14819 | case es_reg: case ss_reg: case cs_reg: |
15921 | case es_reg: case ss_reg: case cs_reg: |
14820 | case ds_reg: case fs_reg: case gs_reg: |
15922 | case ds_reg: case fs_reg: case gs_reg: |
14821 | s = names_seg[code - es_reg]; |
15923 | s = names_seg[code - es_reg]; |
14822 | break; |
15924 | break; |
14823 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15925 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14824 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: |
15926 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: |
14825 | USED_REX (0); |
15927 | USED_REX (0); |
14826 | if (rex) |
15928 | if (rex) |
14827 | s = names8rex[code - al_reg]; |
15929 | s = names8rex[code - al_reg]; |
14828 | else |
15930 | else |
14829 | s = names8[code - al_reg]; |
15931 | s = names8[code - al_reg]; |
14830 | break; |
15932 | break; |
14831 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15933 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14832 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: |
15934 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: |
14833 | USED_REX (REX_W); |
15935 | USED_REX (REX_W); |
14834 | if (rex & REX_W) |
15936 | if (rex & REX_W) |
14835 | s = names64[code - eAX_reg]; |
15937 | s = names64[code - eAX_reg]; |
14836 | else |
15938 | else |
14837 | { |
15939 | { |
14838 | if (sizeflag & DFLAG) |
15940 | if (sizeflag & DFLAG) |
14839 | s = names32[code - eAX_reg]; |
15941 | s = names32[code - eAX_reg]; |
14840 | else |
15942 | else |
14841 | s = names16[code - eAX_reg]; |
15943 | s = names16[code - eAX_reg]; |
14842 | used_prefixes |= (prefixes & PREFIX_DATA); |
15944 | used_prefixes |= (prefixes & PREFIX_DATA); |
14843 | } |
15945 | } |
14844 | break; |
15946 | break; |
14845 | case z_mode_ax_reg: |
15947 | case z_mode_ax_reg: |
14846 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
15948 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
14847 | s = *names32; |
15949 | s = *names32; |
14848 | else |
15950 | else |
14849 | s = *names16; |
15951 | s = *names16; |
14850 | if (!(rex & REX_W)) |
15952 | if (!(rex & REX_W)) |
14851 | used_prefixes |= (prefixes & PREFIX_DATA); |
15953 | used_prefixes |= (prefixes & PREFIX_DATA); |
14852 | break; |
15954 | break; |
14853 | default: |
15955 | default: |
14854 | s = INTERNAL_DISASSEMBLER_ERROR; |
15956 | s = INTERNAL_DISASSEMBLER_ERROR; |
14855 | break; |
15957 | break; |
14856 | } |
15958 | } |
14857 | oappend (s); |
15959 | oappend (s); |
14858 | } |
15960 | } |
14859 | 15961 | ||
14860 | static void |
15962 | static void |
14861 | OP_I (int bytemode, int sizeflag) |
15963 | OP_I (int bytemode, int sizeflag) |
14862 | { |
15964 | { |
14863 | bfd_signed_vma op; |
15965 | bfd_signed_vma op; |
14864 | bfd_signed_vma mask = -1; |
15966 | bfd_signed_vma mask = -1; |
14865 | 15967 | ||
14866 | switch (bytemode) |
15968 | switch (bytemode) |
14867 | { |
15969 | { |
14868 | case b_mode: |
15970 | case b_mode: |
14869 | FETCH_DATA (the_info, codep + 1); |
15971 | FETCH_DATA (the_info, codep + 1); |
14870 | op = *codep++; |
15972 | op = *codep++; |
14871 | mask = 0xff; |
15973 | mask = 0xff; |
14872 | break; |
15974 | break; |
14873 | case q_mode: |
15975 | case q_mode: |
14874 | if (address_mode == mode_64bit) |
15976 | if (address_mode == mode_64bit) |
14875 | { |
15977 | { |
14876 | op = get32s (); |
15978 | op = get32s (); |
14877 | break; |
15979 | break; |
14878 | } |
15980 | } |
14879 | /* Fall through. */ |
15981 | /* Fall through. */ |
14880 | case v_mode: |
15982 | case v_mode: |
14881 | USED_REX (REX_W); |
15983 | USED_REX (REX_W); |
14882 | if (rex & REX_W) |
15984 | if (rex & REX_W) |
14883 | op = get32s (); |
15985 | op = get32s (); |
14884 | else |
15986 | else |
14885 | { |
15987 | { |
14886 | if (sizeflag & DFLAG) |
15988 | if (sizeflag & DFLAG) |
14887 | { |
15989 | { |
14888 | op = get32 (); |
15990 | op = get32 (); |
14889 | mask = 0xffffffff; |
15991 | mask = 0xffffffff; |
14890 | } |
15992 | } |
14891 | else |
15993 | else |
14892 | { |
15994 | { |
14893 | op = get16 (); |
15995 | op = get16 (); |
14894 | mask = 0xfffff; |
15996 | mask = 0xfffff; |
14895 | } |
15997 | } |
14896 | used_prefixes |= (prefixes & PREFIX_DATA); |
15998 | used_prefixes |= (prefixes & PREFIX_DATA); |
14897 | } |
15999 | } |
14898 | break; |
16000 | break; |
14899 | case w_mode: |
16001 | case w_mode: |
14900 | mask = 0xfffff; |
16002 | mask = 0xfffff; |
14901 | op = get16 (); |
16003 | op = get16 (); |
14902 | break; |
16004 | break; |
14903 | case const_1_mode: |
16005 | case const_1_mode: |
14904 | if (intel_syntax) |
16006 | if (intel_syntax) |
14905 | oappend ("1"); |
16007 | oappend ("1"); |
14906 | return; |
16008 | return; |
14907 | default: |
16009 | default: |
14908 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
16010 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
14909 | return; |
16011 | return; |
14910 | } |
16012 | } |
14911 | 16013 | ||
14912 | op &= mask; |
16014 | op &= mask; |
14913 | scratchbuf[0] = '$'; |
16015 | scratchbuf[0] = '$'; |
14914 | print_operand_value (scratchbuf + 1, 1, op); |
16016 | print_operand_value (scratchbuf + 1, 1, op); |
14915 | oappend_maybe_intel (scratchbuf); |
16017 | oappend_maybe_intel (scratchbuf); |
14916 | scratchbuf[0] = '\0'; |
16018 | scratchbuf[0] = '\0'; |
14917 | } |
16019 | } |
14918 | 16020 | ||
14919 | static void |
16021 | static void |
14920 | OP_I64 (int bytemode, int sizeflag) |
16022 | OP_I64 (int bytemode, int sizeflag) |
14921 | { |
16023 | { |
14922 | bfd_signed_vma op; |
16024 | bfd_signed_vma op; |
14923 | bfd_signed_vma mask = -1; |
16025 | bfd_signed_vma mask = -1; |
14924 | 16026 | ||
14925 | if (address_mode != mode_64bit) |
16027 | if (address_mode != mode_64bit) |
14926 | { |
16028 | { |
14927 | OP_I (bytemode, sizeflag); |
16029 | OP_I (bytemode, sizeflag); |
14928 | return; |
16030 | return; |
14929 | } |
16031 | } |
14930 | 16032 | ||
14931 | switch (bytemode) |
16033 | switch (bytemode) |
14932 | { |
16034 | { |
14933 | case b_mode: |
16035 | case b_mode: |
14934 | FETCH_DATA (the_info, codep + 1); |
16036 | FETCH_DATA (the_info, codep + 1); |
14935 | op = *codep++; |
16037 | op = *codep++; |
14936 | mask = 0xff; |
16038 | mask = 0xff; |
14937 | break; |
16039 | break; |
14938 | case v_mode: |
16040 | case v_mode: |
14939 | USED_REX (REX_W); |
16041 | USED_REX (REX_W); |
14940 | if (rex & REX_W) |
16042 | if (rex & REX_W) |
14941 | op = get64 (); |
16043 | op = get64 (); |
14942 | else |
16044 | else |
14943 | { |
16045 | { |
14944 | if (sizeflag & DFLAG) |
16046 | if (sizeflag & DFLAG) |
14945 | { |
16047 | { |
14946 | op = get32 (); |
16048 | op = get32 (); |
14947 | mask = 0xffffffff; |
16049 | mask = 0xffffffff; |
14948 | } |
16050 | } |
14949 | else |
16051 | else |
14950 | { |
16052 | { |
14951 | op = get16 (); |
16053 | op = get16 (); |
14952 | mask = 0xfffff; |
16054 | mask = 0xfffff; |
14953 | } |
16055 | } |
14954 | used_prefixes |= (prefixes & PREFIX_DATA); |
16056 | used_prefixes |= (prefixes & PREFIX_DATA); |
14955 | } |
16057 | } |
14956 | break; |
16058 | break; |
14957 | case w_mode: |
16059 | case w_mode: |
14958 | mask = 0xfffff; |
16060 | mask = 0xfffff; |
14959 | op = get16 (); |
16061 | op = get16 (); |
14960 | break; |
16062 | break; |
14961 | default: |
16063 | default: |
14962 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
16064 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
14963 | return; |
16065 | return; |
14964 | } |
16066 | } |
14965 | 16067 | ||
14966 | op &= mask; |
16068 | op &= mask; |
14967 | scratchbuf[0] = '$'; |
16069 | scratchbuf[0] = '$'; |
14968 | print_operand_value (scratchbuf + 1, 1, op); |
16070 | print_operand_value (scratchbuf + 1, 1, op); |
14969 | oappend_maybe_intel (scratchbuf); |
16071 | oappend_maybe_intel (scratchbuf); |
14970 | scratchbuf[0] = '\0'; |
16072 | scratchbuf[0] = '\0'; |
14971 | } |
16073 | } |
14972 | 16074 | ||
14973 | static void |
16075 | static void |
14974 | OP_sI (int bytemode, int sizeflag) |
16076 | OP_sI (int bytemode, int sizeflag) |
14975 | { |
16077 | { |
14976 | bfd_signed_vma op; |
16078 | bfd_signed_vma op; |
14977 | 16079 | ||
14978 | switch (bytemode) |
16080 | switch (bytemode) |
14979 | { |
16081 | { |
14980 | case b_mode: |
16082 | case b_mode: |
14981 | case b_T_mode: |
16083 | case b_T_mode: |
14982 | FETCH_DATA (the_info, codep + 1); |
16084 | FETCH_DATA (the_info, codep + 1); |
14983 | op = *codep++; |
16085 | op = *codep++; |
14984 | if ((op & 0x80) != 0) |
16086 | if ((op & 0x80) != 0) |
14985 | op -= 0x100; |
16087 | op -= 0x100; |
14986 | if (bytemode == b_T_mode) |
16088 | if (bytemode == b_T_mode) |
14987 | { |
16089 | { |
14988 | if (address_mode != mode_64bit |
16090 | if (address_mode != mode_64bit |
14989 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
16091 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
14990 | { |
16092 | { |
14991 | /* The operand-size prefix is overridden by a REX prefix. */ |
16093 | /* The operand-size prefix is overridden by a REX prefix. */ |
14992 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
16094 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
14993 | op &= 0xffffffff; |
16095 | op &= 0xffffffff; |
14994 | else |
16096 | else |
14995 | op &= 0xffff; |
16097 | op &= 0xffff; |
14996 | } |
16098 | } |
14997 | } |
16099 | } |
14998 | else |
16100 | else |
14999 | { |
16101 | { |
15000 | if (!(rex & REX_W)) |
16102 | if (!(rex & REX_W)) |
15001 | { |
16103 | { |
15002 | if (sizeflag & DFLAG) |
16104 | if (sizeflag & DFLAG) |
15003 | op &= 0xffffffff; |
16105 | op &= 0xffffffff; |
15004 | else |
16106 | else |
15005 | op &= 0xffff; |
16107 | op &= 0xffff; |
15006 | } |
16108 | } |
15007 | } |
16109 | } |
15008 | break; |
16110 | break; |
15009 | case v_mode: |
16111 | case v_mode: |
15010 | /* The operand-size prefix is overridden by a REX prefix. */ |
16112 | /* The operand-size prefix is overridden by a REX prefix. */ |
15011 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
16113 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
15012 | op = get32s (); |
16114 | op = get32s (); |
15013 | else |
16115 | else |
15014 | op = get16 (); |
16116 | op = get16 (); |
15015 | break; |
16117 | break; |
15016 | default: |
16118 | default: |
15017 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
16119 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
15018 | return; |
16120 | return; |
15019 | } |
16121 | } |
15020 | 16122 | ||
15021 | scratchbuf[0] = '$'; |
16123 | scratchbuf[0] = '$'; |
15022 | print_operand_value (scratchbuf + 1, 1, op); |
16124 | print_operand_value (scratchbuf + 1, 1, op); |
15023 | oappend_maybe_intel (scratchbuf); |
16125 | oappend_maybe_intel (scratchbuf); |
15024 | } |
16126 | } |
15025 | 16127 | ||
15026 | static void |
16128 | static void |
15027 | OP_J (int bytemode, int sizeflag) |
16129 | OP_J (int bytemode, int sizeflag) |
15028 | { |
16130 | { |
15029 | bfd_vma disp; |
16131 | bfd_vma disp; |
15030 | bfd_vma mask = -1; |
16132 | bfd_vma mask = -1; |
15031 | bfd_vma segment = 0; |
16133 | bfd_vma segment = 0; |
15032 | 16134 | ||
15033 | switch (bytemode) |
16135 | switch (bytemode) |
15034 | { |
16136 | { |
15035 | case b_mode: |
16137 | case b_mode: |
15036 | FETCH_DATA (the_info, codep + 1); |
16138 | FETCH_DATA (the_info, codep + 1); |
15037 | disp = *codep++; |
16139 | disp = *codep++; |
15038 | if ((disp & 0x80) != 0) |
16140 | if ((disp & 0x80) != 0) |
15039 | disp -= 0x100; |
16141 | disp -= 0x100; |
15040 | break; |
16142 | break; |
15041 | case v_mode: |
16143 | case v_mode: |
- | 16144 | if (isa64 == amd64) |
|
15042 | USED_REX (REX_W); |
16145 | USED_REX (REX_W); |
- | 16146 | if ((sizeflag & DFLAG) |
|
- | 16147 | || (address_mode == mode_64bit |
|
15043 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
16148 | && (isa64 != amd64 || (rex & REX_W)))) |
15044 | disp = get32s (); |
16149 | disp = get32s (); |
15045 | else |
16150 | else |
15046 | { |
16151 | { |
15047 | disp = get16 (); |
16152 | disp = get16 (); |
15048 | if ((disp & 0x8000) != 0) |
16153 | if ((disp & 0x8000) != 0) |
15049 | disp -= 0x10000; |
16154 | disp -= 0x10000; |
15050 | /* In 16bit mode, address is wrapped around at 64k within |
16155 | /* In 16bit mode, address is wrapped around at 64k within |
15051 | the same segment. Otherwise, a data16 prefix on a jump |
16156 | the same segment. Otherwise, a data16 prefix on a jump |
15052 | instruction means that the pc is masked to 16 bits after |
16157 | instruction means that the pc is masked to 16 bits after |
15053 | the displacement is added! */ |
16158 | the displacement is added! */ |
15054 | mask = 0xffff; |
16159 | mask = 0xffff; |
15055 | if ((prefixes & PREFIX_DATA) == 0) |
16160 | if ((prefixes & PREFIX_DATA) == 0) |
15056 | segment = ((start_pc + codep - start_codep) |
16161 | segment = ((start_pc + codep - start_codep) |
15057 | & ~((bfd_vma) 0xffff)); |
16162 | & ~((bfd_vma) 0xffff)); |
15058 | } |
16163 | } |
- | 16164 | if (address_mode != mode_64bit |
|
15059 | if (!(rex & REX_W)) |
16165 | || (isa64 == amd64 && !(rex & REX_W))) |
15060 | used_prefixes |= (prefixes & PREFIX_DATA); |
16166 | used_prefixes |= (prefixes & PREFIX_DATA); |
15061 | break; |
16167 | break; |
15062 | default: |
16168 | default: |
15063 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
16169 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
15064 | return; |
16170 | return; |
15065 | } |
16171 | } |
15066 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
16172 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
15067 | set_op (disp, 0); |
16173 | set_op (disp, 0); |
15068 | print_operand_value (scratchbuf, 1, disp); |
16174 | print_operand_value (scratchbuf, 1, disp); |
15069 | oappend (scratchbuf); |
16175 | oappend (scratchbuf); |
15070 | } |
16176 | } |
15071 | 16177 | ||
15072 | static void |
16178 | static void |
15073 | OP_SEG (int bytemode, int sizeflag) |
16179 | OP_SEG (int bytemode, int sizeflag) |
15074 | { |
16180 | { |
15075 | if (bytemode == w_mode) |
16181 | if (bytemode == w_mode) |
15076 | oappend (names_seg[modrm.reg]); |
16182 | oappend (names_seg[modrm.reg]); |
15077 | else |
16183 | else |
15078 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
16184 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
15079 | } |
16185 | } |
15080 | 16186 | ||
15081 | static void |
16187 | static void |
15082 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
16188 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
15083 | { |
16189 | { |
15084 | int seg, offset; |
16190 | int seg, offset; |
15085 | 16191 | ||
15086 | if (sizeflag & DFLAG) |
16192 | if (sizeflag & DFLAG) |
15087 | { |
16193 | { |
15088 | offset = get32 (); |
16194 | offset = get32 (); |
15089 | seg = get16 (); |
16195 | seg = get16 (); |
15090 | } |
16196 | } |
15091 | else |
16197 | else |
15092 | { |
16198 | { |
15093 | offset = get16 (); |
16199 | offset = get16 (); |
15094 | seg = get16 (); |
16200 | seg = get16 (); |
15095 | } |
16201 | } |
15096 | used_prefixes |= (prefixes & PREFIX_DATA); |
16202 | used_prefixes |= (prefixes & PREFIX_DATA); |
15097 | if (intel_syntax) |
16203 | if (intel_syntax) |
15098 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
16204 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
15099 | else |
16205 | else |
15100 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); |
16206 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); |
15101 | oappend (scratchbuf); |
16207 | oappend (scratchbuf); |
15102 | } |
16208 | } |
15103 | 16209 | ||
15104 | static void |
16210 | static void |
15105 | OP_OFF (int bytemode, int sizeflag) |
16211 | OP_OFF (int bytemode, int sizeflag) |
15106 | { |
16212 | { |
15107 | bfd_vma off; |
16213 | bfd_vma off; |
15108 | 16214 | ||
15109 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16215 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15110 | intel_operand_size (bytemode, sizeflag); |
16216 | intel_operand_size (bytemode, sizeflag); |
15111 | append_seg (); |
16217 | append_seg (); |
15112 | 16218 | ||
15113 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
16219 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
15114 | off = get32 (); |
16220 | off = get32 (); |
15115 | else |
16221 | else |
15116 | off = get16 (); |
16222 | off = get16 (); |
15117 | 16223 | ||
15118 | if (intel_syntax) |
16224 | if (intel_syntax) |
15119 | { |
16225 | { |
15120 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
16226 | if (!active_seg_prefix) |
15121 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
- | |
15122 | { |
16227 | { |
15123 | oappend (names_seg[ds_reg - es_reg]); |
16228 | oappend (names_seg[ds_reg - es_reg]); |
15124 | oappend (":"); |
16229 | oappend (":"); |
15125 | } |
16230 | } |
15126 | } |
16231 | } |
15127 | print_operand_value (scratchbuf, 1, off); |
16232 | print_operand_value (scratchbuf, 1, off); |
15128 | oappend (scratchbuf); |
16233 | oappend (scratchbuf); |
15129 | } |
16234 | } |
15130 | 16235 | ||
15131 | static void |
16236 | static void |
15132 | OP_OFF64 (int bytemode, int sizeflag) |
16237 | OP_OFF64 (int bytemode, int sizeflag) |
15133 | { |
16238 | { |
15134 | bfd_vma off; |
16239 | bfd_vma off; |
15135 | 16240 | ||
15136 | if (address_mode != mode_64bit |
16241 | if (address_mode != mode_64bit |
15137 | || (prefixes & PREFIX_ADDR)) |
16242 | || (prefixes & PREFIX_ADDR)) |
15138 | { |
16243 | { |
15139 | OP_OFF (bytemode, sizeflag); |
16244 | OP_OFF (bytemode, sizeflag); |
15140 | return; |
16245 | return; |
15141 | } |
16246 | } |
15142 | 16247 | ||
15143 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16248 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15144 | intel_operand_size (bytemode, sizeflag); |
16249 | intel_operand_size (bytemode, sizeflag); |
15145 | append_seg (); |
16250 | append_seg (); |
15146 | 16251 | ||
15147 | off = get64 (); |
16252 | off = get64 (); |
15148 | 16253 | ||
15149 | if (intel_syntax) |
16254 | if (intel_syntax) |
15150 | { |
16255 | { |
15151 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
16256 | if (!active_seg_prefix) |
15152 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
- | |
15153 | { |
16257 | { |
15154 | oappend (names_seg[ds_reg - es_reg]); |
16258 | oappend (names_seg[ds_reg - es_reg]); |
15155 | oappend (":"); |
16259 | oappend (":"); |
15156 | } |
16260 | } |
15157 | } |
16261 | } |
15158 | print_operand_value (scratchbuf, 1, off); |
16262 | print_operand_value (scratchbuf, 1, off); |
15159 | oappend (scratchbuf); |
16263 | oappend (scratchbuf); |
15160 | } |
16264 | } |
15161 | 16265 | ||
15162 | static void |
16266 | static void |
15163 | ptr_reg (int code, int sizeflag) |
16267 | ptr_reg (int code, int sizeflag) |
15164 | { |
16268 | { |
15165 | const char *s; |
16269 | const char *s; |
15166 | 16270 | ||
15167 | *obufp++ = open_char; |
16271 | *obufp++ = open_char; |
15168 | used_prefixes |= (prefixes & PREFIX_ADDR); |
16272 | used_prefixes |= (prefixes & PREFIX_ADDR); |
15169 | if (address_mode == mode_64bit) |
16273 | if (address_mode == mode_64bit) |
15170 | { |
16274 | { |
15171 | if (!(sizeflag & AFLAG)) |
16275 | if (!(sizeflag & AFLAG)) |
15172 | s = names32[code - eAX_reg]; |
16276 | s = names32[code - eAX_reg]; |
15173 | else |
16277 | else |
15174 | s = names64[code - eAX_reg]; |
16278 | s = names64[code - eAX_reg]; |
15175 | } |
16279 | } |
15176 | else if (sizeflag & AFLAG) |
16280 | else if (sizeflag & AFLAG) |
15177 | s = names32[code - eAX_reg]; |
16281 | s = names32[code - eAX_reg]; |
15178 | else |
16282 | else |
15179 | s = names16[code - eAX_reg]; |
16283 | s = names16[code - eAX_reg]; |
15180 | oappend (s); |
16284 | oappend (s); |
15181 | *obufp++ = close_char; |
16285 | *obufp++ = close_char; |
15182 | *obufp = 0; |
16286 | *obufp = 0; |
15183 | } |
16287 | } |
15184 | 16288 | ||
15185 | static void |
16289 | static void |
15186 | OP_ESreg (int code, int sizeflag) |
16290 | OP_ESreg (int code, int sizeflag) |
15187 | { |
16291 | { |
15188 | if (intel_syntax) |
16292 | if (intel_syntax) |
15189 | { |
16293 | { |
15190 | switch (codep[-1]) |
16294 | switch (codep[-1]) |
15191 | { |
16295 | { |
15192 | case 0x6d: /* insw/insl */ |
16296 | case 0x6d: /* insw/insl */ |
15193 | intel_operand_size (z_mode, sizeflag); |
16297 | intel_operand_size (z_mode, sizeflag); |
15194 | break; |
16298 | break; |
15195 | case 0xa5: /* movsw/movsl/movsq */ |
16299 | case 0xa5: /* movsw/movsl/movsq */ |
15196 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ |
16300 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ |
15197 | case 0xab: /* stosw/stosl */ |
16301 | case 0xab: /* stosw/stosl */ |
15198 | case 0xaf: /* scasw/scasl */ |
16302 | case 0xaf: /* scasw/scasl */ |
15199 | intel_operand_size (v_mode, sizeflag); |
16303 | intel_operand_size (v_mode, sizeflag); |
15200 | break; |
16304 | break; |
15201 | default: |
16305 | default: |
15202 | intel_operand_size (b_mode, sizeflag); |
16306 | intel_operand_size (b_mode, sizeflag); |
15203 | } |
16307 | } |
15204 | } |
16308 | } |
15205 | oappend_maybe_intel ("%es:"); |
16309 | oappend_maybe_intel ("%es:"); |
15206 | ptr_reg (code, sizeflag); |
16310 | ptr_reg (code, sizeflag); |
15207 | } |
16311 | } |
15208 | 16312 | ||
15209 | static void |
16313 | static void |
15210 | OP_DSreg (int code, int sizeflag) |
16314 | OP_DSreg (int code, int sizeflag) |
15211 | { |
16315 | { |
15212 | if (intel_syntax) |
16316 | if (intel_syntax) |
15213 | { |
16317 | { |
15214 | switch (codep[-1]) |
16318 | switch (codep[-1]) |
15215 | { |
16319 | { |
15216 | case 0x6f: /* outsw/outsl */ |
16320 | case 0x6f: /* outsw/outsl */ |
15217 | intel_operand_size (z_mode, sizeflag); |
16321 | intel_operand_size (z_mode, sizeflag); |
15218 | break; |
16322 | break; |
15219 | case 0xa5: /* movsw/movsl/movsq */ |
16323 | case 0xa5: /* movsw/movsl/movsq */ |
15220 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ |
16324 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ |
15221 | case 0xad: /* lodsw/lodsl/lodsq */ |
16325 | case 0xad: /* lodsw/lodsl/lodsq */ |
15222 | intel_operand_size (v_mode, sizeflag); |
16326 | intel_operand_size (v_mode, sizeflag); |
15223 | break; |
16327 | break; |
15224 | default: |
16328 | default: |
15225 | intel_operand_size (b_mode, sizeflag); |
16329 | intel_operand_size (b_mode, sizeflag); |
15226 | } |
16330 | } |
15227 | } |
16331 | } |
15228 | if ((prefixes |
16332 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15229 | & (PREFIX_CS |
16333 | default segment register DS is printed. */ |
15230 | | PREFIX_DS |
- | |
15231 | | PREFIX_SS |
- | |
15232 | | PREFIX_ES |
- | |
15233 | | PREFIX_FS |
- | |
15234 | | PREFIX_GS)) == 0) |
16334 | if (!active_seg_prefix) |
15235 | prefixes |= PREFIX_DS; |
16335 | active_seg_prefix = PREFIX_DS; |
15236 | append_seg (); |
16336 | append_seg (); |
15237 | ptr_reg (code, sizeflag); |
16337 | ptr_reg (code, sizeflag); |
15238 | } |
16338 | } |
15239 | 16339 | ||
15240 | static void |
16340 | static void |
15241 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16341 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
15242 | { |
16342 | { |
15243 | int add; |
16343 | int add; |
15244 | if (rex & REX_R) |
16344 | if (rex & REX_R) |
15245 | { |
16345 | { |
15246 | USED_REX (REX_R); |
16346 | USED_REX (REX_R); |
15247 | add = 8; |
16347 | add = 8; |
15248 | } |
16348 | } |
15249 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
16349 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
15250 | { |
16350 | { |
15251 | all_prefixes[last_lock_prefix] = 0; |
16351 | all_prefixes[last_lock_prefix] = 0; |
15252 | used_prefixes |= PREFIX_LOCK; |
16352 | used_prefixes |= PREFIX_LOCK; |
15253 | add = 8; |
16353 | add = 8; |
15254 | } |
16354 | } |
15255 | else |
16355 | else |
15256 | add = 0; |
16356 | add = 0; |
15257 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
16357 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
15258 | oappend_maybe_intel (scratchbuf); |
16358 | oappend_maybe_intel (scratchbuf); |
15259 | } |
16359 | } |
15260 | 16360 | ||
15261 | static void |
16361 | static void |
15262 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16362 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
15263 | { |
16363 | { |
15264 | int add; |
16364 | int add; |
15265 | USED_REX (REX_R); |
16365 | USED_REX (REX_R); |
15266 | if (rex & REX_R) |
16366 | if (rex & REX_R) |
15267 | add = 8; |
16367 | add = 8; |
15268 | else |
16368 | else |
15269 | add = 0; |
16369 | add = 0; |
15270 | if (intel_syntax) |
16370 | if (intel_syntax) |
15271 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
16371 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
15272 | else |
16372 | else |
15273 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
16373 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
15274 | oappend (scratchbuf); |
16374 | oappend (scratchbuf); |
15275 | } |
16375 | } |
15276 | 16376 | ||
15277 | static void |
16377 | static void |
15278 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16378 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
15279 | { |
16379 | { |
15280 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
16380 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
15281 | oappend_maybe_intel (scratchbuf); |
16381 | oappend_maybe_intel (scratchbuf); |
15282 | } |
16382 | } |
15283 | 16383 | ||
15284 | static void |
16384 | static void |
15285 | OP_R (int bytemode, int sizeflag) |
16385 | OP_R (int bytemode, int sizeflag) |
15286 | { |
16386 | { |
15287 | if (modrm.mod == 3) |
16387 | /* Skip mod/rm byte. */ |
15288 | OP_E (bytemode, sizeflag); |
16388 | MODRM_CHECK; |
15289 | else |
16389 | codep++; |
15290 | BadOp (); |
16390 | OP_E_register (bytemode, sizeflag); |
15291 | } |
16391 | } |
15292 | 16392 | ||
15293 | static void |
16393 | static void |
15294 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16394 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
15295 | { |
16395 | { |
15296 | int reg = modrm.reg; |
16396 | int reg = modrm.reg; |
15297 | const char **names; |
16397 | const char **names; |
15298 | 16398 | ||
15299 | used_prefixes |= (prefixes & PREFIX_DATA); |
16399 | used_prefixes |= (prefixes & PREFIX_DATA); |
15300 | if (prefixes & PREFIX_DATA) |
16400 | if (prefixes & PREFIX_DATA) |
15301 | { |
16401 | { |
15302 | names = names_xmm; |
16402 | names = names_xmm; |
15303 | USED_REX (REX_R); |
16403 | USED_REX (REX_R); |
15304 | if (rex & REX_R) |
16404 | if (rex & REX_R) |
15305 | reg += 8; |
16405 | reg += 8; |
15306 | } |
16406 | } |
15307 | else |
16407 | else |
15308 | names = names_mm; |
16408 | names = names_mm; |
15309 | oappend (names[reg]); |
16409 | oappend (names[reg]); |
15310 | } |
16410 | } |
15311 | 16411 | ||
15312 | static void |
16412 | static void |
15313 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
16413 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
15314 | { |
16414 | { |
15315 | int reg = modrm.reg; |
16415 | int reg = modrm.reg; |
15316 | const char **names; |
16416 | const char **names; |
15317 | 16417 | ||
15318 | USED_REX (REX_R); |
16418 | USED_REX (REX_R); |
15319 | if (rex & REX_R) |
16419 | if (rex & REX_R) |
15320 | reg += 8; |
16420 | reg += 8; |
15321 | if (vex.evex) |
16421 | if (vex.evex) |
15322 | { |
16422 | { |
15323 | if (!vex.r) |
16423 | if (!vex.r) |
15324 | reg += 16; |
16424 | reg += 16; |
15325 | } |
16425 | } |
15326 | 16426 | ||
15327 | if (need_vex |
16427 | if (need_vex |
15328 | && bytemode != xmm_mode |
16428 | && bytemode != xmm_mode |
15329 | && bytemode != xmmq_mode |
16429 | && bytemode != xmmq_mode |
15330 | && bytemode != evex_half_bcst_xmmq_mode |
16430 | && bytemode != evex_half_bcst_xmmq_mode |
15331 | && bytemode != ymm_mode |
16431 | && bytemode != ymm_mode |
15332 | && bytemode != scalar_mode) |
16432 | && bytemode != scalar_mode) |
15333 | { |
16433 | { |
15334 | switch (vex.length) |
16434 | switch (vex.length) |
15335 | { |
16435 | { |
15336 | case 128: |
16436 | case 128: |
15337 | names = names_xmm; |
16437 | names = names_xmm; |
15338 | break; |
16438 | break; |
15339 | case 256: |
16439 | case 256: |
- | 16440 | if (vex.w |
|
15340 | if (vex.w || bytemode != vex_vsib_q_w_dq_mode) |
16441 | || (bytemode != vex_vsib_q_w_dq_mode |
- | 16442 | && bytemode != vex_vsib_q_w_d_mode)) |
|
15341 | names = names_ymm; |
16443 | names = names_ymm; |
15342 | else |
16444 | else |
15343 | names = names_xmm; |
16445 | names = names_xmm; |
15344 | break; |
16446 | break; |
15345 | case 512: |
16447 | case 512: |
15346 | names = names_zmm; |
16448 | names = names_zmm; |
15347 | break; |
16449 | break; |
15348 | default: |
16450 | default: |
15349 | abort (); |
16451 | abort (); |
15350 | } |
16452 | } |
15351 | } |
16453 | } |
15352 | else if (bytemode == xmmq_mode |
16454 | else if (bytemode == xmmq_mode |
15353 | || bytemode == evex_half_bcst_xmmq_mode) |
16455 | || bytemode == evex_half_bcst_xmmq_mode) |
15354 | { |
16456 | { |
15355 | switch (vex.length) |
16457 | switch (vex.length) |
15356 | { |
16458 | { |
15357 | case 128: |
16459 | case 128: |
15358 | case 256: |
16460 | case 256: |
15359 | names = names_xmm; |
16461 | names = names_xmm; |
15360 | break; |
16462 | break; |
15361 | case 512: |
16463 | case 512: |
15362 | names = names_ymm; |
16464 | names = names_ymm; |
15363 | break; |
16465 | break; |
15364 | default: |
16466 | default: |
15365 | abort (); |
16467 | abort (); |
15366 | } |
16468 | } |
15367 | } |
16469 | } |
15368 | else if (bytemode == ymm_mode) |
16470 | else if (bytemode == ymm_mode) |
15369 | names = names_ymm; |
16471 | names = names_ymm; |
15370 | else |
16472 | else |
15371 | names = names_xmm; |
16473 | names = names_xmm; |
15372 | oappend (names[reg]); |
16474 | oappend (names[reg]); |
15373 | } |
16475 | } |
15374 | 16476 | ||
15375 | static void |
16477 | static void |
15376 | OP_EM (int bytemode, int sizeflag) |
16478 | OP_EM (int bytemode, int sizeflag) |
15377 | { |
16479 | { |
15378 | int reg; |
16480 | int reg; |
15379 | const char **names; |
16481 | const char **names; |
15380 | 16482 | ||
15381 | if (modrm.mod != 3) |
16483 | if (modrm.mod != 3) |
15382 | { |
16484 | { |
15383 | if (intel_syntax |
16485 | if (intel_syntax |
15384 | && (bytemode == v_mode || bytemode == v_swap_mode)) |
16486 | && (bytemode == v_mode || bytemode == v_swap_mode)) |
15385 | { |
16487 | { |
15386 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
16488 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
15387 | used_prefixes |= (prefixes & PREFIX_DATA); |
16489 | used_prefixes |= (prefixes & PREFIX_DATA); |
15388 | } |
16490 | } |
15389 | OP_E (bytemode, sizeflag); |
16491 | OP_E (bytemode, sizeflag); |
15390 | return; |
16492 | return; |
15391 | } |
16493 | } |
15392 | 16494 | ||
15393 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
16495 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15394 | swap_operand (); |
16496 | swap_operand (); |
15395 | 16497 | ||
15396 | /* Skip mod/rm byte. */ |
16498 | /* Skip mod/rm byte. */ |
15397 | MODRM_CHECK; |
16499 | MODRM_CHECK; |
15398 | codep++; |
16500 | codep++; |
15399 | used_prefixes |= (prefixes & PREFIX_DATA); |
16501 | used_prefixes |= (prefixes & PREFIX_DATA); |
15400 | reg = modrm.rm; |
16502 | reg = modrm.rm; |
15401 | if (prefixes & PREFIX_DATA) |
16503 | if (prefixes & PREFIX_DATA) |
15402 | { |
16504 | { |
15403 | names = names_xmm; |
16505 | names = names_xmm; |
15404 | USED_REX (REX_B); |
16506 | USED_REX (REX_B); |
15405 | if (rex & REX_B) |
16507 | if (rex & REX_B) |
15406 | reg += 8; |
16508 | reg += 8; |
15407 | } |
16509 | } |
15408 | else |
16510 | else |
15409 | names = names_mm; |
16511 | names = names_mm; |
15410 | oappend (names[reg]); |
16512 | oappend (names[reg]); |
15411 | } |
16513 | } |
15412 | 16514 | ||
15413 | /* cvt* are the only instructions in sse2 which have |
16515 | /* cvt* are the only instructions in sse2 which have |
15414 | both SSE and MMX operands and also have 0x66 prefix |
16516 | both SSE and MMX operands and also have 0x66 prefix |
15415 | in their opcode. 0x66 was originally used to differentiate |
16517 | in their opcode. 0x66 was originally used to differentiate |
15416 | between SSE and MMX instruction(operands). So we have to handle the |
16518 | between SSE and MMX instruction(operands). So we have to handle the |
15417 | cvt* separately using OP_EMC and OP_MXC */ |
16519 | cvt* separately using OP_EMC and OP_MXC */ |
15418 | static void |
16520 | static void |
15419 | OP_EMC (int bytemode, int sizeflag) |
16521 | OP_EMC (int bytemode, int sizeflag) |
15420 | { |
16522 | { |
15421 | if (modrm.mod != 3) |
16523 | if (modrm.mod != 3) |
15422 | { |
16524 | { |
15423 | if (intel_syntax && bytemode == v_mode) |
16525 | if (intel_syntax && bytemode == v_mode) |
15424 | { |
16526 | { |
15425 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
16527 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
15426 | used_prefixes |= (prefixes & PREFIX_DATA); |
16528 | used_prefixes |= (prefixes & PREFIX_DATA); |
15427 | } |
16529 | } |
15428 | OP_E (bytemode, sizeflag); |
16530 | OP_E (bytemode, sizeflag); |
15429 | return; |
16531 | return; |
15430 | } |
16532 | } |
15431 | 16533 | ||
15432 | /* Skip mod/rm byte. */ |
16534 | /* Skip mod/rm byte. */ |
15433 | MODRM_CHECK; |
16535 | MODRM_CHECK; |
15434 | codep++; |
16536 | codep++; |
15435 | used_prefixes |= (prefixes & PREFIX_DATA); |
16537 | used_prefixes |= (prefixes & PREFIX_DATA); |
15436 | oappend (names_mm[modrm.rm]); |
16538 | oappend (names_mm[modrm.rm]); |
15437 | } |
16539 | } |
15438 | 16540 | ||
15439 | static void |
16541 | static void |
15440 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16542 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
15441 | { |
16543 | { |
15442 | used_prefixes |= (prefixes & PREFIX_DATA); |
16544 | used_prefixes |= (prefixes & PREFIX_DATA); |
15443 | oappend (names_mm[modrm.reg]); |
16545 | oappend (names_mm[modrm.reg]); |
15444 | } |
16546 | } |
15445 | 16547 | ||
15446 | static void |
16548 | static void |
15447 | OP_EX (int bytemode, int sizeflag) |
16549 | OP_EX (int bytemode, int sizeflag) |
15448 | { |
16550 | { |
15449 | int reg; |
16551 | int reg; |
15450 | const char **names; |
16552 | const char **names; |
15451 | 16553 | ||
15452 | /* Skip mod/rm byte. */ |
16554 | /* Skip mod/rm byte. */ |
15453 | MODRM_CHECK; |
16555 | MODRM_CHECK; |
15454 | codep++; |
16556 | codep++; |
15455 | 16557 | ||
15456 | if (modrm.mod != 3) |
16558 | if (modrm.mod != 3) |
15457 | { |
16559 | { |
15458 | OP_E_memory (bytemode, sizeflag); |
16560 | OP_E_memory (bytemode, sizeflag); |
15459 | return; |
16561 | return; |
15460 | } |
16562 | } |
15461 | 16563 | ||
15462 | reg = modrm.rm; |
16564 | reg = modrm.rm; |
15463 | USED_REX (REX_B); |
16565 | USED_REX (REX_B); |
15464 | if (rex & REX_B) |
16566 | if (rex & REX_B) |
15465 | reg += 8; |
16567 | reg += 8; |
15466 | if (vex.evex) |
16568 | if (vex.evex) |
15467 | { |
16569 | { |
15468 | USED_REX (REX_X); |
16570 | USED_REX (REX_X); |
15469 | if ((rex & REX_X)) |
16571 | if ((rex & REX_X)) |
15470 | reg += 16; |
16572 | reg += 16; |
15471 | } |
16573 | } |
15472 | 16574 | ||
15473 | if ((sizeflag & SUFFIX_ALWAYS) |
16575 | if ((sizeflag & SUFFIX_ALWAYS) |
15474 | && (bytemode == x_swap_mode |
16576 | && (bytemode == x_swap_mode |
15475 | || bytemode == d_swap_mode |
16577 | || bytemode == d_swap_mode |
- | 16578 | || bytemode == dqw_swap_mode |
|
15476 | || bytemode == d_scalar_swap_mode |
16579 | || bytemode == d_scalar_swap_mode |
15477 | || bytemode == q_swap_mode |
16580 | || bytemode == q_swap_mode |
15478 | || bytemode == q_scalar_swap_mode)) |
16581 | || bytemode == q_scalar_swap_mode)) |
15479 | swap_operand (); |
16582 | swap_operand (); |
15480 | 16583 | ||
15481 | if (need_vex |
16584 | if (need_vex |
15482 | && bytemode != xmm_mode |
16585 | && bytemode != xmm_mode |
15483 | && bytemode != xmmdw_mode |
16586 | && bytemode != xmmdw_mode |
15484 | && bytemode != xmmqd_mode |
16587 | && bytemode != xmmqd_mode |
15485 | && bytemode != xmm_mb_mode |
16588 | && bytemode != xmm_mb_mode |
15486 | && bytemode != xmm_mw_mode |
16589 | && bytemode != xmm_mw_mode |
15487 | && bytemode != xmm_md_mode |
16590 | && bytemode != xmm_md_mode |
15488 | && bytemode != xmm_mq_mode |
16591 | && bytemode != xmm_mq_mode |
15489 | && bytemode != xmm_mdq_mode |
16592 | && bytemode != xmm_mdq_mode |
15490 | && bytemode != xmmq_mode |
16593 | && bytemode != xmmq_mode |
15491 | && bytemode != evex_half_bcst_xmmq_mode |
16594 | && bytemode != evex_half_bcst_xmmq_mode |
15492 | && bytemode != ymm_mode |
16595 | && bytemode != ymm_mode |
15493 | && bytemode != d_scalar_mode |
16596 | && bytemode != d_scalar_mode |
15494 | && bytemode != d_scalar_swap_mode |
16597 | && bytemode != d_scalar_swap_mode |
15495 | && bytemode != q_scalar_mode |
16598 | && bytemode != q_scalar_mode |
15496 | && bytemode != q_scalar_swap_mode |
16599 | && bytemode != q_scalar_swap_mode |
15497 | && bytemode != vex_scalar_w_dq_mode) |
16600 | && bytemode != vex_scalar_w_dq_mode) |
15498 | { |
16601 | { |
15499 | switch (vex.length) |
16602 | switch (vex.length) |
15500 | { |
16603 | { |
15501 | case 128: |
16604 | case 128: |
15502 | names = names_xmm; |
16605 | names = names_xmm; |
15503 | break; |
16606 | break; |
15504 | case 256: |
16607 | case 256: |
15505 | names = names_ymm; |
16608 | names = names_ymm; |
15506 | break; |
16609 | break; |
15507 | case 512: |
16610 | case 512: |
15508 | names = names_zmm; |
16611 | names = names_zmm; |
15509 | break; |
16612 | break; |
15510 | default: |
16613 | default: |
15511 | abort (); |
16614 | abort (); |
15512 | } |
16615 | } |
15513 | } |
16616 | } |
15514 | else if (bytemode == xmmq_mode |
16617 | else if (bytemode == xmmq_mode |
15515 | || bytemode == evex_half_bcst_xmmq_mode) |
16618 | || bytemode == evex_half_bcst_xmmq_mode) |
15516 | { |
16619 | { |
15517 | switch (vex.length) |
16620 | switch (vex.length) |
15518 | { |
16621 | { |
15519 | case 128: |
16622 | case 128: |
15520 | case 256: |
16623 | case 256: |
15521 | names = names_xmm; |
16624 | names = names_xmm; |
15522 | break; |
16625 | break; |
15523 | case 512: |
16626 | case 512: |
15524 | names = names_ymm; |
16627 | names = names_ymm; |
15525 | break; |
16628 | break; |
15526 | default: |
16629 | default: |
15527 | abort (); |
16630 | abort (); |
15528 | } |
16631 | } |
15529 | } |
16632 | } |
15530 | else if (bytemode == ymm_mode) |
16633 | else if (bytemode == ymm_mode) |
15531 | names = names_ymm; |
16634 | names = names_ymm; |
15532 | else |
16635 | else |
15533 | names = names_xmm; |
16636 | names = names_xmm; |
15534 | oappend (names[reg]); |
16637 | oappend (names[reg]); |
15535 | } |
16638 | } |
15536 | 16639 | ||
15537 | static void |
16640 | static void |
15538 | OP_MS (int bytemode, int sizeflag) |
16641 | OP_MS (int bytemode, int sizeflag) |
15539 | { |
16642 | { |
15540 | if (modrm.mod == 3) |
16643 | if (modrm.mod == 3) |
15541 | OP_EM (bytemode, sizeflag); |
16644 | OP_EM (bytemode, sizeflag); |
15542 | else |
16645 | else |
15543 | BadOp (); |
16646 | BadOp (); |
15544 | } |
16647 | } |
15545 | 16648 | ||
15546 | static void |
16649 | static void |
15547 | OP_XS (int bytemode, int sizeflag) |
16650 | OP_XS (int bytemode, int sizeflag) |
15548 | { |
16651 | { |
15549 | if (modrm.mod == 3) |
16652 | if (modrm.mod == 3) |
15550 | OP_EX (bytemode, sizeflag); |
16653 | OP_EX (bytemode, sizeflag); |
15551 | else |
16654 | else |
15552 | BadOp (); |
16655 | BadOp (); |
15553 | } |
16656 | } |
15554 | 16657 | ||
15555 | static void |
16658 | static void |
15556 | OP_M (int bytemode, int sizeflag) |
16659 | OP_M (int bytemode, int sizeflag) |
15557 | { |
16660 | { |
15558 | if (modrm.mod == 3) |
16661 | if (modrm.mod == 3) |
15559 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16662 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15560 | BadOp (); |
16663 | BadOp (); |
15561 | else |
16664 | else |
15562 | OP_E (bytemode, sizeflag); |
16665 | OP_E (bytemode, sizeflag); |
15563 | } |
16666 | } |
15564 | 16667 | ||
15565 | static void |
16668 | static void |
15566 | OP_0f07 (int bytemode, int sizeflag) |
16669 | OP_0f07 (int bytemode, int sizeflag) |
15567 | { |
16670 | { |
15568 | if (modrm.mod != 3 || modrm.rm != 0) |
16671 | if (modrm.mod != 3 || modrm.rm != 0) |
15569 | BadOp (); |
16672 | BadOp (); |
15570 | else |
16673 | else |
15571 | OP_E (bytemode, sizeflag); |
16674 | OP_E (bytemode, sizeflag); |
15572 | } |
16675 | } |
15573 | 16676 | ||
15574 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
16677 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
15575 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
16678 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
15576 | 16679 | ||
15577 | static void |
16680 | static void |
15578 | NOP_Fixup1 (int bytemode, int sizeflag) |
16681 | NOP_Fixup1 (int bytemode, int sizeflag) |
15579 | { |
16682 | { |
15580 | if ((prefixes & PREFIX_DATA) != 0 |
16683 | if ((prefixes & PREFIX_DATA) != 0 |
15581 | || (rex != 0 |
16684 | || (rex != 0 |
15582 | && rex != 0x48 |
16685 | && rex != 0x48 |
15583 | && address_mode == mode_64bit)) |
16686 | && address_mode == mode_64bit)) |
15584 | OP_REG (bytemode, sizeflag); |
16687 | OP_REG (bytemode, sizeflag); |
15585 | else |
16688 | else |
15586 | strcpy (obuf, "nop"); |
16689 | strcpy (obuf, "nop"); |
15587 | } |
16690 | } |
15588 | 16691 | ||
15589 | static void |
16692 | static void |
15590 | NOP_Fixup2 (int bytemode, int sizeflag) |
16693 | NOP_Fixup2 (int bytemode, int sizeflag) |
15591 | { |
16694 | { |
15592 | if ((prefixes & PREFIX_DATA) != 0 |
16695 | if ((prefixes & PREFIX_DATA) != 0 |
15593 | || (rex != 0 |
16696 | || (rex != 0 |
15594 | && rex != 0x48 |
16697 | && rex != 0x48 |
15595 | && address_mode == mode_64bit)) |
16698 | && address_mode == mode_64bit)) |
15596 | OP_IMREG (bytemode, sizeflag); |
16699 | OP_IMREG (bytemode, sizeflag); |
15597 | } |
16700 | } |
15598 | 16701 | ||
15599 | static const char *const Suffix3DNow[] = { |
16702 | static const char *const Suffix3DNow[] = { |
15600 | /* 00 */ NULL, NULL, NULL, NULL, |
16703 | /* 00 */ NULL, NULL, NULL, NULL, |
15601 | /* 04 */ NULL, NULL, NULL, NULL, |
16704 | /* 04 */ NULL, NULL, NULL, NULL, |
15602 | /* 08 */ NULL, NULL, NULL, NULL, |
16705 | /* 08 */ NULL, NULL, NULL, NULL, |
15603 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
16706 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
15604 | /* 10 */ NULL, NULL, NULL, NULL, |
16707 | /* 10 */ NULL, NULL, NULL, NULL, |
15605 | /* 14 */ NULL, NULL, NULL, NULL, |
16708 | /* 14 */ NULL, NULL, NULL, NULL, |
15606 | /* 18 */ NULL, NULL, NULL, NULL, |
16709 | /* 18 */ NULL, NULL, NULL, NULL, |
15607 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
16710 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
15608 | /* 20 */ NULL, NULL, NULL, NULL, |
16711 | /* 20 */ NULL, NULL, NULL, NULL, |
15609 | /* 24 */ NULL, NULL, NULL, NULL, |
16712 | /* 24 */ NULL, NULL, NULL, NULL, |
15610 | /* 28 */ NULL, NULL, NULL, NULL, |
16713 | /* 28 */ NULL, NULL, NULL, NULL, |
15611 | /* 2C */ NULL, NULL, NULL, NULL, |
16714 | /* 2C */ NULL, NULL, NULL, NULL, |
15612 | /* 30 */ NULL, NULL, NULL, NULL, |
16715 | /* 30 */ NULL, NULL, NULL, NULL, |
15613 | /* 34 */ NULL, NULL, NULL, NULL, |
16716 | /* 34 */ NULL, NULL, NULL, NULL, |
15614 | /* 38 */ NULL, NULL, NULL, NULL, |
16717 | /* 38 */ NULL, NULL, NULL, NULL, |
15615 | /* 3C */ NULL, NULL, NULL, NULL, |
16718 | /* 3C */ NULL, NULL, NULL, NULL, |
15616 | /* 40 */ NULL, NULL, NULL, NULL, |
16719 | /* 40 */ NULL, NULL, NULL, NULL, |
15617 | /* 44 */ NULL, NULL, NULL, NULL, |
16720 | /* 44 */ NULL, NULL, NULL, NULL, |
15618 | /* 48 */ NULL, NULL, NULL, NULL, |
16721 | /* 48 */ NULL, NULL, NULL, NULL, |
15619 | /* 4C */ NULL, NULL, NULL, NULL, |
16722 | /* 4C */ NULL, NULL, NULL, NULL, |
15620 | /* 50 */ NULL, NULL, NULL, NULL, |
16723 | /* 50 */ NULL, NULL, NULL, NULL, |
15621 | /* 54 */ NULL, NULL, NULL, NULL, |
16724 | /* 54 */ NULL, NULL, NULL, NULL, |
15622 | /* 58 */ NULL, NULL, NULL, NULL, |
16725 | /* 58 */ NULL, NULL, NULL, NULL, |
15623 | /* 5C */ NULL, NULL, NULL, NULL, |
16726 | /* 5C */ NULL, NULL, NULL, NULL, |
15624 | /* 60 */ NULL, NULL, NULL, NULL, |
16727 | /* 60 */ NULL, NULL, NULL, NULL, |
15625 | /* 64 */ NULL, NULL, NULL, NULL, |
16728 | /* 64 */ NULL, NULL, NULL, NULL, |
15626 | /* 68 */ NULL, NULL, NULL, NULL, |
16729 | /* 68 */ NULL, NULL, NULL, NULL, |
15627 | /* 6C */ NULL, NULL, NULL, NULL, |
16730 | /* 6C */ NULL, NULL, NULL, NULL, |
15628 | /* 70 */ NULL, NULL, NULL, NULL, |
16731 | /* 70 */ NULL, NULL, NULL, NULL, |
15629 | /* 74 */ NULL, NULL, NULL, NULL, |
16732 | /* 74 */ NULL, NULL, NULL, NULL, |
15630 | /* 78 */ NULL, NULL, NULL, NULL, |
16733 | /* 78 */ NULL, NULL, NULL, NULL, |
15631 | /* 7C */ NULL, NULL, NULL, NULL, |
16734 | /* 7C */ NULL, NULL, NULL, NULL, |
15632 | /* 80 */ NULL, NULL, NULL, NULL, |
16735 | /* 80 */ NULL, NULL, NULL, NULL, |
15633 | /* 84 */ NULL, NULL, NULL, NULL, |
16736 | /* 84 */ NULL, NULL, NULL, NULL, |
15634 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16737 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15635 | /* 8C */ NULL, NULL, "pfpnacc", NULL, |
16738 | /* 8C */ NULL, NULL, "pfpnacc", NULL, |
15636 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16739 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15637 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", |
16740 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", |
15638 | /* 98 */ NULL, NULL, "pfsub", NULL, |
16741 | /* 98 */ NULL, NULL, "pfsub", NULL, |
15639 | /* 9C */ NULL, NULL, "pfadd", NULL, |
16742 | /* 9C */ NULL, NULL, "pfadd", NULL, |
15640 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, |
16743 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, |
15641 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", |
16744 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", |
15642 | /* A8 */ NULL, NULL, "pfsubr", NULL, |
16745 | /* A8 */ NULL, NULL, "pfsubr", NULL, |
15643 | /* AC */ NULL, NULL, "pfacc", NULL, |
16746 | /* AC */ NULL, NULL, "pfacc", NULL, |
15644 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, |
16747 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, |
15645 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
16748 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
15646 | /* B8 */ NULL, NULL, NULL, "pswapd", |
16749 | /* B8 */ NULL, NULL, NULL, "pswapd", |
15647 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16750 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15648 | /* C0 */ NULL, NULL, NULL, NULL, |
16751 | /* C0 */ NULL, NULL, NULL, NULL, |
15649 | /* C4 */ NULL, NULL, NULL, NULL, |
16752 | /* C4 */ NULL, NULL, NULL, NULL, |
15650 | /* C8 */ NULL, NULL, NULL, NULL, |
16753 | /* C8 */ NULL, NULL, NULL, NULL, |
15651 | /* CC */ NULL, NULL, NULL, NULL, |
16754 | /* CC */ NULL, NULL, NULL, NULL, |
15652 | /* D0 */ NULL, NULL, NULL, NULL, |
16755 | /* D0 */ NULL, NULL, NULL, NULL, |
15653 | /* D4 */ NULL, NULL, NULL, NULL, |
16756 | /* D4 */ NULL, NULL, NULL, NULL, |
15654 | /* D8 */ NULL, NULL, NULL, NULL, |
16757 | /* D8 */ NULL, NULL, NULL, NULL, |
15655 | /* DC */ NULL, NULL, NULL, NULL, |
16758 | /* DC */ NULL, NULL, NULL, NULL, |
15656 | /* E0 */ NULL, NULL, NULL, NULL, |
16759 | /* E0 */ NULL, NULL, NULL, NULL, |
15657 | /* E4 */ NULL, NULL, NULL, NULL, |
16760 | /* E4 */ NULL, NULL, NULL, NULL, |
15658 | /* E8 */ NULL, NULL, NULL, NULL, |
16761 | /* E8 */ NULL, NULL, NULL, NULL, |
15659 | /* EC */ NULL, NULL, NULL, NULL, |
16762 | /* EC */ NULL, NULL, NULL, NULL, |
15660 | /* F0 */ NULL, NULL, NULL, NULL, |
16763 | /* F0 */ NULL, NULL, NULL, NULL, |
15661 | /* F4 */ NULL, NULL, NULL, NULL, |
16764 | /* F4 */ NULL, NULL, NULL, NULL, |
15662 | /* F8 */ NULL, NULL, NULL, NULL, |
16765 | /* F8 */ NULL, NULL, NULL, NULL, |
15663 | /* FC */ NULL, NULL, NULL, NULL, |
16766 | /* FC */ NULL, NULL, NULL, NULL, |
15664 | }; |
16767 | }; |
15665 | 16768 | ||
15666 | static void |
16769 | static void |
15667 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16770 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
15668 | { |
16771 | { |
15669 | const char *mnemonic; |
16772 | const char *mnemonic; |
15670 | 16773 | ||
15671 | FETCH_DATA (the_info, codep + 1); |
16774 | FETCH_DATA (the_info, codep + 1); |
15672 | /* AMD 3DNow! instructions are specified by an opcode suffix in the |
16775 | /* AMD 3DNow! instructions are specified by an opcode suffix in the |
15673 | place where an 8-bit immediate would normally go. ie. the last |
16776 | place where an 8-bit immediate would normally go. ie. the last |
15674 | byte of the instruction. */ |
16777 | byte of the instruction. */ |
15675 | obufp = mnemonicendp; |
16778 | obufp = mnemonicendp; |
15676 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
16779 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
15677 | if (mnemonic) |
16780 | if (mnemonic) |
15678 | oappend (mnemonic); |
16781 | oappend (mnemonic); |
15679 | else |
16782 | else |
15680 | { |
16783 | { |
15681 | /* Since a variable sized modrm/sib chunk is between the start |
16784 | /* Since a variable sized modrm/sib chunk is between the start |
15682 | of the opcode (0x0f0f) and the opcode suffix, we need to do |
16785 | of the opcode (0x0f0f) and the opcode suffix, we need to do |
15683 | all the modrm processing first, and don't know until now that |
16786 | all the modrm processing first, and don't know until now that |
15684 | we have a bad opcode. This necessitates some cleaning up. */ |
16787 | we have a bad opcode. This necessitates some cleaning up. */ |
15685 | op_out[0][0] = '\0'; |
16788 | op_out[0][0] = '\0'; |
15686 | op_out[1][0] = '\0'; |
16789 | op_out[1][0] = '\0'; |
15687 | BadOp (); |
16790 | BadOp (); |
15688 | } |
16791 | } |
15689 | mnemonicendp = obufp; |
16792 | mnemonicendp = obufp; |
15690 | } |
16793 | } |
15691 | 16794 | ||
15692 | static struct op simd_cmp_op[] = |
16795 | static struct op simd_cmp_op[] = |
15693 | { |
16796 | { |
15694 | { STRING_COMMA_LEN ("eq") }, |
16797 | { STRING_COMMA_LEN ("eq") }, |
15695 | { STRING_COMMA_LEN ("lt") }, |
16798 | { STRING_COMMA_LEN ("lt") }, |
15696 | { STRING_COMMA_LEN ("le") }, |
16799 | { STRING_COMMA_LEN ("le") }, |
15697 | { STRING_COMMA_LEN ("unord") }, |
16800 | { STRING_COMMA_LEN ("unord") }, |
15698 | { STRING_COMMA_LEN ("neq") }, |
16801 | { STRING_COMMA_LEN ("neq") }, |
15699 | { STRING_COMMA_LEN ("nlt") }, |
16802 | { STRING_COMMA_LEN ("nlt") }, |
15700 | { STRING_COMMA_LEN ("nle") }, |
16803 | { STRING_COMMA_LEN ("nle") }, |
15701 | { STRING_COMMA_LEN ("ord") } |
16804 | { STRING_COMMA_LEN ("ord") } |
15702 | }; |
16805 | }; |
15703 | 16806 | ||
15704 | static void |
16807 | static void |
15705 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16808 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
15706 | { |
16809 | { |
15707 | unsigned int cmp_type; |
16810 | unsigned int cmp_type; |
15708 | 16811 | ||
15709 | FETCH_DATA (the_info, codep + 1); |
16812 | FETCH_DATA (the_info, codep + 1); |
15710 | cmp_type = *codep++ & 0xff; |
16813 | cmp_type = *codep++ & 0xff; |
15711 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
16814 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
15712 | { |
16815 | { |
15713 | char suffix [3]; |
16816 | char suffix [3]; |
15714 | char *p = mnemonicendp - 2; |
16817 | char *p = mnemonicendp - 2; |
15715 | suffix[0] = p[0]; |
16818 | suffix[0] = p[0]; |
15716 | suffix[1] = p[1]; |
16819 | suffix[1] = p[1]; |
15717 | suffix[2] = '\0'; |
16820 | suffix[2] = '\0'; |
15718 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16821 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15719 | mnemonicendp += simd_cmp_op[cmp_type].len; |
16822 | mnemonicendp += simd_cmp_op[cmp_type].len; |
15720 | } |
16823 | } |
15721 | else |
16824 | else |
15722 | { |
16825 | { |
15723 | /* We have a reserved extension byte. Output it directly. */ |
16826 | /* We have a reserved extension byte. Output it directly. */ |
15724 | scratchbuf[0] = '$'; |
16827 | scratchbuf[0] = '$'; |
15725 | print_operand_value (scratchbuf + 1, 1, cmp_type); |
16828 | print_operand_value (scratchbuf + 1, 1, cmp_type); |
15726 | oappend_maybe_intel (scratchbuf); |
16829 | oappend_maybe_intel (scratchbuf); |
15727 | scratchbuf[0] = '\0'; |
16830 | scratchbuf[0] = '\0'; |
15728 | } |
16831 | } |
15729 | } |
16832 | } |
15730 | 16833 | ||
15731 | static void |
16834 | static void |
- | 16835 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, |
|
- | 16836 | int sizeflag ATTRIBUTE_UNUSED) |
|
- | 16837 | { |
|
- | 16838 | /* mwaitx %eax,%ecx,%ebx */ |
|
- | 16839 | if (!intel_syntax) |
|
- | 16840 | { |
|
- | 16841 | const char **names = (address_mode == mode_64bit |
|
- | 16842 | ? names64 : names32); |
|
- | 16843 | strcpy (op_out[0], names[0]); |
|
- | 16844 | strcpy (op_out[1], names[1]); |
|
- | 16845 | strcpy (op_out[2], names[3]); |
|
- | 16846 | two_source_ops = 1; |
|
- | 16847 | } |
|
- | 16848 | /* Skip mod/rm byte. */ |
|
- | 16849 | MODRM_CHECK; |
|
- | 16850 | codep++; |
|
- | 16851 | } |
|
- | 16852 | ||
- | 16853 | static void |
|
15732 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16854 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
15733 | int sizeflag ATTRIBUTE_UNUSED) |
16855 | int sizeflag ATTRIBUTE_UNUSED) |
15734 | { |
16856 | { |
15735 | /* mwait %eax,%ecx */ |
16857 | /* mwait %eax,%ecx */ |
15736 | if (!intel_syntax) |
16858 | if (!intel_syntax) |
15737 | { |
16859 | { |
15738 | const char **names = (address_mode == mode_64bit |
16860 | const char **names = (address_mode == mode_64bit |
15739 | ? names64 : names32); |
16861 | ? names64 : names32); |
15740 | strcpy (op_out[0], names[0]); |
16862 | strcpy (op_out[0], names[0]); |
15741 | strcpy (op_out[1], names[1]); |
16863 | strcpy (op_out[1], names[1]); |
15742 | two_source_ops = 1; |
16864 | two_source_ops = 1; |
15743 | } |
16865 | } |
15744 | /* Skip mod/rm byte. */ |
16866 | /* Skip mod/rm byte. */ |
15745 | MODRM_CHECK; |
16867 | MODRM_CHECK; |
15746 | codep++; |
16868 | codep++; |
15747 | } |
16869 | } |
15748 | 16870 | ||
15749 | static void |
16871 | static void |
15750 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, |
16872 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, |
15751 | int sizeflag ATTRIBUTE_UNUSED) |
16873 | int sizeflag ATTRIBUTE_UNUSED) |
15752 | { |
16874 | { |
15753 | /* monitor %eax,%ecx,%edx" */ |
16875 | /* monitor %eax,%ecx,%edx" */ |
15754 | if (!intel_syntax) |
16876 | if (!intel_syntax) |
15755 | { |
16877 | { |
15756 | const char **op1_names; |
16878 | const char **op1_names; |
15757 | const char **names = (address_mode == mode_64bit |
16879 | const char **names = (address_mode == mode_64bit |
15758 | ? names64 : names32); |
16880 | ? names64 : names32); |
15759 | 16881 | ||
15760 | if (!(prefixes & PREFIX_ADDR)) |
16882 | if (!(prefixes & PREFIX_ADDR)) |
15761 | op1_names = (address_mode == mode_16bit |
16883 | op1_names = (address_mode == mode_16bit |
15762 | ? names16 : names); |
16884 | ? names16 : names); |
15763 | else |
16885 | else |
15764 | { |
16886 | { |
15765 | /* Remove "addr16/addr32". */ |
16887 | /* Remove "addr16/addr32". */ |
15766 | all_prefixes[last_addr_prefix] = 0; |
16888 | all_prefixes[last_addr_prefix] = 0; |
15767 | op1_names = (address_mode != mode_32bit |
16889 | op1_names = (address_mode != mode_32bit |
15768 | ? names32 : names16); |
16890 | ? names32 : names16); |
15769 | used_prefixes |= PREFIX_ADDR; |
16891 | used_prefixes |= PREFIX_ADDR; |
15770 | } |
16892 | } |
15771 | strcpy (op_out[0], op1_names[0]); |
16893 | strcpy (op_out[0], op1_names[0]); |
15772 | strcpy (op_out[1], names[1]); |
16894 | strcpy (op_out[1], names[1]); |
15773 | strcpy (op_out[2], names[2]); |
16895 | strcpy (op_out[2], names[2]); |
15774 | two_source_ops = 1; |
16896 | two_source_ops = 1; |
15775 | } |
16897 | } |
15776 | /* Skip mod/rm byte. */ |
16898 | /* Skip mod/rm byte. */ |
15777 | MODRM_CHECK; |
16899 | MODRM_CHECK; |
15778 | codep++; |
16900 | codep++; |
15779 | } |
16901 | } |
15780 | 16902 | ||
15781 | static void |
16903 | static void |
15782 | BadOp (void) |
16904 | BadOp (void) |
15783 | { |
16905 | { |
15784 | /* Throw away prefixes and 1st. opcode byte. */ |
16906 | /* Throw away prefixes and 1st. opcode byte. */ |
15785 | codep = insn_codep + 1; |
16907 | codep = insn_codep + 1; |
15786 | oappend ("(bad)"); |
16908 | oappend ("(bad)"); |
15787 | } |
16909 | } |
15788 | 16910 | ||
15789 | static void |
16911 | static void |
15790 | REP_Fixup (int bytemode, int sizeflag) |
16912 | REP_Fixup (int bytemode, int sizeflag) |
15791 | { |
16913 | { |
15792 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, |
16914 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, |
15793 | lods and stos. */ |
16915 | lods and stos. */ |
15794 | if (prefixes & PREFIX_REPZ) |
16916 | if (prefixes & PREFIX_REPZ) |
15795 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
16917 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
15796 | 16918 | ||
15797 | switch (bytemode) |
16919 | switch (bytemode) |
15798 | { |
16920 | { |
15799 | case al_reg: |
16921 | case al_reg: |
15800 | case eAX_reg: |
16922 | case eAX_reg: |
15801 | case indir_dx_reg: |
16923 | case indir_dx_reg: |
15802 | OP_IMREG (bytemode, sizeflag); |
16924 | OP_IMREG (bytemode, sizeflag); |
15803 | break; |
16925 | break; |
15804 | case eDI_reg: |
16926 | case eDI_reg: |
15805 | OP_ESreg (bytemode, sizeflag); |
16927 | OP_ESreg (bytemode, sizeflag); |
15806 | break; |
16928 | break; |
15807 | case eSI_reg: |
16929 | case eSI_reg: |
15808 | OP_DSreg (bytemode, sizeflag); |
16930 | OP_DSreg (bytemode, sizeflag); |
15809 | break; |
16931 | break; |
15810 | default: |
16932 | default: |
15811 | abort (); |
16933 | abort (); |
15812 | break; |
16934 | break; |
15813 | } |
16935 | } |
15814 | } |
16936 | } |
15815 | 16937 | ||
15816 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16938 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15817 | "bnd". */ |
16939 | "bnd". */ |
15818 | 16940 | ||
15819 | static void |
16941 | static void |
15820 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16942 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
15821 | { |
16943 | { |
15822 | if (prefixes & PREFIX_REPNZ) |
16944 | if (prefixes & PREFIX_REPNZ) |
15823 | all_prefixes[last_repnz_prefix] = BND_PREFIX; |
16945 | all_prefixes[last_repnz_prefix] = BND_PREFIX; |
15824 | } |
16946 | } |
15825 | 16947 | ||
15826 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16948 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15827 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. |
16949 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. |
15828 | */ |
16950 | */ |
15829 | 16951 | ||
15830 | static void |
16952 | static void |
15831 | HLE_Fixup1 (int bytemode, int sizeflag) |
16953 | HLE_Fixup1 (int bytemode, int sizeflag) |
15832 | { |
16954 | { |
15833 | if (modrm.mod != 3 |
16955 | if (modrm.mod != 3 |
15834 | && (prefixes & PREFIX_LOCK) != 0) |
16956 | && (prefixes & PREFIX_LOCK) != 0) |
15835 | { |
16957 | { |
15836 | if (prefixes & PREFIX_REPZ) |
16958 | if (prefixes & PREFIX_REPZ) |
15837 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
16959 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
15838 | if (prefixes & PREFIX_REPNZ) |
16960 | if (prefixes & PREFIX_REPNZ) |
15839 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
16961 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
15840 | } |
16962 | } |
15841 | 16963 | ||
15842 | OP_E (bytemode, sizeflag); |
16964 | OP_E (bytemode, sizeflag); |
15843 | } |
16965 | } |
15844 | 16966 | ||
15845 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16967 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15846 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. |
16968 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. |
15847 | */ |
16969 | */ |
15848 | 16970 | ||
15849 | static void |
16971 | static void |
15850 | HLE_Fixup2 (int bytemode, int sizeflag) |
16972 | HLE_Fixup2 (int bytemode, int sizeflag) |
15851 | { |
16973 | { |
15852 | if (modrm.mod != 3) |
16974 | if (modrm.mod != 3) |
15853 | { |
16975 | { |
15854 | if (prefixes & PREFIX_REPZ) |
16976 | if (prefixes & PREFIX_REPZ) |
15855 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
16977 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
15856 | if (prefixes & PREFIX_REPNZ) |
16978 | if (prefixes & PREFIX_REPNZ) |
15857 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
16979 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
15858 | } |
16980 | } |
15859 | 16981 | ||
15860 | OP_E (bytemode, sizeflag); |
16982 | OP_E (bytemode, sizeflag); |
15861 | } |
16983 | } |
15862 | 16984 | ||
15863 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as |
16985 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as |
15864 | "xrelease" for memory operand. No check for LOCK prefix. */ |
16986 | "xrelease" for memory operand. No check for LOCK prefix. */ |
15865 | 16987 | ||
15866 | static void |
16988 | static void |
15867 | HLE_Fixup3 (int bytemode, int sizeflag) |
16989 | HLE_Fixup3 (int bytemode, int sizeflag) |
15868 | { |
16990 | { |
15869 | if (modrm.mod != 3 |
16991 | if (modrm.mod != 3 |
15870 | && last_repz_prefix > last_repnz_prefix |
16992 | && last_repz_prefix > last_repnz_prefix |
15871 | && (prefixes & PREFIX_REPZ) != 0) |
16993 | && (prefixes & PREFIX_REPZ) != 0) |
15872 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
16994 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
15873 | 16995 | ||
15874 | OP_E (bytemode, sizeflag); |
16996 | OP_E (bytemode, sizeflag); |
15875 | } |
16997 | } |
15876 | 16998 | ||
15877 | static void |
16999 | static void |
15878 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) |
17000 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) |
15879 | { |
17001 | { |
15880 | USED_REX (REX_W); |
17002 | USED_REX (REX_W); |
15881 | if (rex & REX_W) |
17003 | if (rex & REX_W) |
15882 | { |
17004 | { |
15883 | /* Change cmpxchg8b to cmpxchg16b. */ |
17005 | /* Change cmpxchg8b to cmpxchg16b. */ |
15884 | char *p = mnemonicendp - 2; |
17006 | char *p = mnemonicendp - 2; |
15885 | mnemonicendp = stpcpy (p, "16b"); |
17007 | mnemonicendp = stpcpy (p, "16b"); |
15886 | bytemode = o_mode; |
17008 | bytemode = o_mode; |
15887 | } |
17009 | } |
15888 | else if ((prefixes & PREFIX_LOCK) != 0) |
17010 | else if ((prefixes & PREFIX_LOCK) != 0) |
15889 | { |
17011 | { |
15890 | if (prefixes & PREFIX_REPZ) |
17012 | if (prefixes & PREFIX_REPZ) |
15891 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
17013 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
15892 | if (prefixes & PREFIX_REPNZ) |
17014 | if (prefixes & PREFIX_REPNZ) |
15893 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
17015 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
15894 | } |
17016 | } |
15895 | 17017 | ||
15896 | OP_M (bytemode, sizeflag); |
17018 | OP_M (bytemode, sizeflag); |
15897 | } |
17019 | } |
15898 | 17020 | ||
15899 | static void |
17021 | static void |
15900 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) |
17022 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) |
15901 | { |
17023 | { |
15902 | const char **names; |
17024 | const char **names; |
15903 | 17025 | ||
15904 | if (need_vex) |
17026 | if (need_vex) |
15905 | { |
17027 | { |
15906 | switch (vex.length) |
17028 | switch (vex.length) |
15907 | { |
17029 | { |
15908 | case 128: |
17030 | case 128: |
15909 | names = names_xmm; |
17031 | names = names_xmm; |
15910 | break; |
17032 | break; |
15911 | case 256: |
17033 | case 256: |
15912 | names = names_ymm; |
17034 | names = names_ymm; |
15913 | break; |
17035 | break; |
15914 | default: |
17036 | default: |
15915 | abort (); |
17037 | abort (); |
15916 | } |
17038 | } |
15917 | } |
17039 | } |
15918 | else |
17040 | else |
15919 | names = names_xmm; |
17041 | names = names_xmm; |
15920 | oappend (names[reg]); |
17042 | oappend (names[reg]); |
15921 | } |
17043 | } |
15922 | 17044 | ||
15923 | static void |
17045 | static void |
15924 | CRC32_Fixup (int bytemode, int sizeflag) |
17046 | CRC32_Fixup (int bytemode, int sizeflag) |
15925 | { |
17047 | { |
15926 | /* Add proper suffix to "crc32". */ |
17048 | /* Add proper suffix to "crc32". */ |
15927 | char *p = mnemonicendp; |
17049 | char *p = mnemonicendp; |
15928 | 17050 | ||
15929 | switch (bytemode) |
17051 | switch (bytemode) |
15930 | { |
17052 | { |
15931 | case b_mode: |
17053 | case b_mode: |
15932 | if (intel_syntax) |
17054 | if (intel_syntax) |
15933 | goto skip; |
17055 | goto skip; |
15934 | 17056 | ||
15935 | *p++ = 'b'; |
17057 | *p++ = 'b'; |
15936 | break; |
17058 | break; |
15937 | case v_mode: |
17059 | case v_mode: |
15938 | if (intel_syntax) |
17060 | if (intel_syntax) |
15939 | goto skip; |
17061 | goto skip; |
15940 | 17062 | ||
15941 | USED_REX (REX_W); |
17063 | USED_REX (REX_W); |
15942 | if (rex & REX_W) |
17064 | if (rex & REX_W) |
15943 | *p++ = 'q'; |
17065 | *p++ = 'q'; |
15944 | else |
17066 | else |
15945 | { |
17067 | { |
15946 | if (sizeflag & DFLAG) |
17068 | if (sizeflag & DFLAG) |
15947 | *p++ = 'l'; |
17069 | *p++ = 'l'; |
15948 | else |
17070 | else |
15949 | *p++ = 'w'; |
17071 | *p++ = 'w'; |
15950 | used_prefixes |= (prefixes & PREFIX_DATA); |
17072 | used_prefixes |= (prefixes & PREFIX_DATA); |
15951 | } |
17073 | } |
15952 | break; |
17074 | break; |
15953 | default: |
17075 | default: |
15954 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
17076 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
15955 | break; |
17077 | break; |
15956 | } |
17078 | } |
15957 | mnemonicendp = p; |
17079 | mnemonicendp = p; |
15958 | *p = '\0'; |
17080 | *p = '\0'; |
15959 | 17081 | ||
15960 | skip: |
17082 | skip: |
15961 | if (modrm.mod == 3) |
17083 | if (modrm.mod == 3) |
15962 | { |
17084 | { |
15963 | int add; |
17085 | int add; |
15964 | 17086 | ||
15965 | /* Skip mod/rm byte. */ |
17087 | /* Skip mod/rm byte. */ |
15966 | MODRM_CHECK; |
17088 | MODRM_CHECK; |
15967 | codep++; |
17089 | codep++; |
15968 | 17090 | ||
15969 | USED_REX (REX_B); |
17091 | USED_REX (REX_B); |
15970 | add = (rex & REX_B) ? 8 : 0; |
17092 | add = (rex & REX_B) ? 8 : 0; |
15971 | if (bytemode == b_mode) |
17093 | if (bytemode == b_mode) |
15972 | { |
17094 | { |
15973 | USED_REX (0); |
17095 | USED_REX (0); |
15974 | if (rex) |
17096 | if (rex) |
15975 | oappend (names8rex[modrm.rm + add]); |
17097 | oappend (names8rex[modrm.rm + add]); |
15976 | else |
17098 | else |
15977 | oappend (names8[modrm.rm + add]); |
17099 | oappend (names8[modrm.rm + add]); |
15978 | } |
17100 | } |
15979 | else |
17101 | else |
15980 | { |
17102 | { |
15981 | USED_REX (REX_W); |
17103 | USED_REX (REX_W); |
15982 | if (rex & REX_W) |
17104 | if (rex & REX_W) |
15983 | oappend (names64[modrm.rm + add]); |
17105 | oappend (names64[modrm.rm + add]); |
15984 | else if ((prefixes & PREFIX_DATA)) |
17106 | else if ((prefixes & PREFIX_DATA)) |
15985 | oappend (names16[modrm.rm + add]); |
17107 | oappend (names16[modrm.rm + add]); |
15986 | else |
17108 | else |
15987 | oappend (names32[modrm.rm + add]); |
17109 | oappend (names32[modrm.rm + add]); |
15988 | } |
17110 | } |
15989 | } |
17111 | } |
15990 | else |
17112 | else |
15991 | OP_E (bytemode, sizeflag); |
17113 | OP_E (bytemode, sizeflag); |
15992 | } |
17114 | } |
15993 | 17115 | ||
15994 | static void |
17116 | static void |
15995 | FXSAVE_Fixup (int bytemode, int sizeflag) |
17117 | FXSAVE_Fixup (int bytemode, int sizeflag) |
15996 | { |
17118 | { |
15997 | /* Add proper suffix to "fxsave" and "fxrstor". */ |
17119 | /* Add proper suffix to "fxsave" and "fxrstor". */ |
15998 | USED_REX (REX_W); |
17120 | USED_REX (REX_W); |
15999 | if (rex & REX_W) |
17121 | if (rex & REX_W) |
16000 | { |
17122 | { |
16001 | char *p = mnemonicendp; |
17123 | char *p = mnemonicendp; |
16002 | *p++ = '6'; |
17124 | *p++ = '6'; |
16003 | *p++ = '4'; |
17125 | *p++ = '4'; |
16004 | *p = '\0'; |
17126 | *p = '\0'; |
16005 | mnemonicendp = p; |
17127 | mnemonicendp = p; |
16006 | } |
17128 | } |
16007 | OP_M (bytemode, sizeflag); |
17129 | OP_M (bytemode, sizeflag); |
16008 | } |
17130 | } |
16009 | 17131 | ||
16010 | /* Display the destination register operand for instructions with |
17132 | /* Display the destination register operand for instructions with |
16011 | VEX. */ |
17133 | VEX. */ |
16012 | 17134 | ||
16013 | static void |
17135 | static void |
16014 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
17136 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
16015 | { |
17137 | { |
16016 | int reg; |
17138 | int reg; |
16017 | const char **names; |
17139 | const char **names; |
16018 | 17140 | ||
16019 | if (!need_vex) |
17141 | if (!need_vex) |
16020 | abort (); |
17142 | abort (); |
16021 | 17143 | ||
16022 | if (!need_vex_reg) |
17144 | if (!need_vex_reg) |
16023 | return; |
17145 | return; |
16024 | 17146 | ||
16025 | reg = vex.register_specifier; |
17147 | reg = vex.register_specifier; |
16026 | if (vex.evex) |
17148 | if (vex.evex) |
16027 | { |
17149 | { |
16028 | if (!vex.v) |
17150 | if (!vex.v) |
16029 | reg += 16; |
17151 | reg += 16; |
16030 | } |
17152 | } |
16031 | 17153 | ||
16032 | if (bytemode == vex_scalar_mode) |
17154 | if (bytemode == vex_scalar_mode) |
16033 | { |
17155 | { |
16034 | oappend (names_xmm[reg]); |
17156 | oappend (names_xmm[reg]); |
16035 | return; |
17157 | return; |
16036 | } |
17158 | } |
16037 | 17159 | ||
16038 | switch (vex.length) |
17160 | switch (vex.length) |
16039 | { |
17161 | { |
16040 | case 128: |
17162 | case 128: |
16041 | switch (bytemode) |
17163 | switch (bytemode) |
16042 | { |
17164 | { |
16043 | case vex_mode: |
17165 | case vex_mode: |
16044 | case vex128_mode: |
17166 | case vex128_mode: |
16045 | case vex_vsib_q_w_dq_mode: |
17167 | case vex_vsib_q_w_dq_mode: |
- | 17168 | case vex_vsib_q_w_d_mode: |
|
16046 | names = names_xmm; |
17169 | names = names_xmm; |
16047 | break; |
17170 | break; |
16048 | case dq_mode: |
17171 | case dq_mode: |
16049 | if (vex.w) |
17172 | if (vex.w) |
16050 | names = names64; |
17173 | names = names64; |
16051 | else |
17174 | else |
16052 | names = names32; |
17175 | names = names32; |
16053 | break; |
17176 | break; |
- | 17177 | case mask_bd_mode: |
|
16054 | case mask_mode: |
17178 | case mask_mode: |
16055 | names = names_mask; |
17179 | names = names_mask; |
16056 | break; |
17180 | break; |
16057 | default: |
17181 | default: |
16058 | abort (); |
17182 | abort (); |
16059 | return; |
17183 | return; |
16060 | } |
17184 | } |
16061 | break; |
17185 | break; |
16062 | case 256: |
17186 | case 256: |
16063 | switch (bytemode) |
17187 | switch (bytemode) |
16064 | { |
17188 | { |
16065 | case vex_mode: |
17189 | case vex_mode: |
16066 | case vex256_mode: |
17190 | case vex256_mode: |
16067 | names = names_ymm; |
17191 | names = names_ymm; |
16068 | break; |
17192 | break; |
16069 | case vex_vsib_q_w_dq_mode: |
17193 | case vex_vsib_q_w_dq_mode: |
- | 17194 | case vex_vsib_q_w_d_mode: |
|
16070 | names = vex.w ? names_ymm : names_xmm; |
17195 | names = vex.w ? names_ymm : names_xmm; |
16071 | break; |
17196 | break; |
- | 17197 | case mask_bd_mode: |
|
16072 | case mask_mode: |
17198 | case mask_mode: |
16073 | names = names_mask; |
17199 | names = names_mask; |
16074 | break; |
17200 | break; |
16075 | default: |
17201 | default: |
16076 | abort (); |
17202 | abort (); |
16077 | return; |
17203 | return; |
16078 | } |
17204 | } |
16079 | break; |
17205 | break; |
16080 | case 512: |
17206 | case 512: |
16081 | names = names_zmm; |
17207 | names = names_zmm; |
16082 | break; |
17208 | break; |
16083 | default: |
17209 | default: |
16084 | abort (); |
17210 | abort (); |
16085 | break; |
17211 | break; |
16086 | } |
17212 | } |
16087 | oappend (names[reg]); |
17213 | oappend (names[reg]); |
16088 | } |
17214 | } |
16089 | 17215 | ||
16090 | /* Get the VEX immediate byte without moving codep. */ |
17216 | /* Get the VEX immediate byte without moving codep. */ |
16091 | 17217 | ||
16092 | static unsigned char |
17218 | static unsigned char |
16093 | get_vex_imm8 (int sizeflag, int opnum) |
17219 | get_vex_imm8 (int sizeflag, int opnum) |
16094 | { |
17220 | { |
16095 | int bytes_before_imm = 0; |
17221 | int bytes_before_imm = 0; |
16096 | 17222 | ||
16097 | if (modrm.mod != 3) |
17223 | if (modrm.mod != 3) |
16098 | { |
17224 | { |
16099 | /* There are SIB/displacement bytes. */ |
17225 | /* There are SIB/displacement bytes. */ |
16100 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
17226 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
16101 | { |
17227 | { |
16102 | /* 32/64 bit address mode */ |
17228 | /* 32/64 bit address mode */ |
16103 | int base = modrm.rm; |
17229 | int base = modrm.rm; |
16104 | 17230 | ||
16105 | /* Check SIB byte. */ |
17231 | /* Check SIB byte. */ |
16106 | if (base == 4) |
17232 | if (base == 4) |
16107 | { |
17233 | { |
16108 | FETCH_DATA (the_info, codep + 1); |
17234 | FETCH_DATA (the_info, codep + 1); |
16109 | base = *codep & 7; |
17235 | base = *codep & 7; |
16110 | /* When decoding the third source, don't increase |
17236 | /* When decoding the third source, don't increase |
16111 | bytes_before_imm as this has already been incremented |
17237 | bytes_before_imm as this has already been incremented |
16112 | by one in OP_E_memory while decoding the second |
17238 | by one in OP_E_memory while decoding the second |
16113 | source operand. */ |
17239 | source operand. */ |
16114 | if (opnum == 0) |
17240 | if (opnum == 0) |
16115 | bytes_before_imm++; |
17241 | bytes_before_imm++; |
16116 | } |
17242 | } |
16117 | 17243 | ||
16118 | /* Don't increase bytes_before_imm when decoding the third source, |
17244 | /* Don't increase bytes_before_imm when decoding the third source, |
16119 | it has already been incremented by OP_E_memory while decoding |
17245 | it has already been incremented by OP_E_memory while decoding |
16120 | the second source operand. */ |
17246 | the second source operand. */ |
16121 | if (opnum == 0) |
17247 | if (opnum == 0) |
16122 | { |
17248 | { |
16123 | switch (modrm.mod) |
17249 | switch (modrm.mod) |
16124 | { |
17250 | { |
16125 | case 0: |
17251 | case 0: |
16126 | /* When modrm.rm == 5 or modrm.rm == 4 and base in |
17252 | /* When modrm.rm == 5 or modrm.rm == 4 and base in |
16127 | SIB == 5, there is a 4 byte displacement. */ |
17253 | SIB == 5, there is a 4 byte displacement. */ |
16128 | if (base != 5) |
17254 | if (base != 5) |
16129 | /* No displacement. */ |
17255 | /* No displacement. */ |
16130 | break; |
17256 | break; |
16131 | case 2: |
17257 | case 2: |
16132 | /* 4 byte displacement. */ |
17258 | /* 4 byte displacement. */ |
16133 | bytes_before_imm += 4; |
17259 | bytes_before_imm += 4; |
16134 | break; |
17260 | break; |
16135 | case 1: |
17261 | case 1: |
16136 | /* 1 byte displacement. */ |
17262 | /* 1 byte displacement. */ |
16137 | bytes_before_imm++; |
17263 | bytes_before_imm++; |
16138 | break; |
17264 | break; |
16139 | } |
17265 | } |
16140 | } |
17266 | } |
16141 | } |
17267 | } |
16142 | else |
17268 | else |
16143 | { |
17269 | { |
16144 | /* 16 bit address mode */ |
17270 | /* 16 bit address mode */ |
16145 | /* Don't increase bytes_before_imm when decoding the third source, |
17271 | /* Don't increase bytes_before_imm when decoding the third source, |
16146 | it has already been incremented by OP_E_memory while decoding |
17272 | it has already been incremented by OP_E_memory while decoding |
16147 | the second source operand. */ |
17273 | the second source operand. */ |
16148 | if (opnum == 0) |
17274 | if (opnum == 0) |
16149 | { |
17275 | { |
16150 | switch (modrm.mod) |
17276 | switch (modrm.mod) |
16151 | { |
17277 | { |
16152 | case 0: |
17278 | case 0: |
16153 | /* When modrm.rm == 6, there is a 2 byte displacement. */ |
17279 | /* When modrm.rm == 6, there is a 2 byte displacement. */ |
16154 | if (modrm.rm != 6) |
17280 | if (modrm.rm != 6) |
16155 | /* No displacement. */ |
17281 | /* No displacement. */ |
16156 | break; |
17282 | break; |
16157 | case 2: |
17283 | case 2: |
16158 | /* 2 byte displacement. */ |
17284 | /* 2 byte displacement. */ |
16159 | bytes_before_imm += 2; |
17285 | bytes_before_imm += 2; |
16160 | break; |
17286 | break; |
16161 | case 1: |
17287 | case 1: |
16162 | /* 1 byte displacement: when decoding the third source, |
17288 | /* 1 byte displacement: when decoding the third source, |
16163 | don't increase bytes_before_imm as this has already |
17289 | don't increase bytes_before_imm as this has already |
16164 | been incremented by one in OP_E_memory while decoding |
17290 | been incremented by one in OP_E_memory while decoding |
16165 | the second source operand. */ |
17291 | the second source operand. */ |
16166 | if (opnum == 0) |
17292 | if (opnum == 0) |
16167 | bytes_before_imm++; |
17293 | bytes_before_imm++; |
16168 | 17294 | ||
16169 | break; |
17295 | break; |
16170 | } |
17296 | } |
16171 | } |
17297 | } |
16172 | } |
17298 | } |
16173 | } |
17299 | } |
16174 | 17300 | ||
16175 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); |
17301 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); |
16176 | return codep [bytes_before_imm]; |
17302 | return codep [bytes_before_imm]; |
16177 | } |
17303 | } |
16178 | 17304 | ||
16179 | static void |
17305 | static void |
16180 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) |
17306 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) |
16181 | { |
17307 | { |
16182 | const char **names; |
17308 | const char **names; |
16183 | 17309 | ||
16184 | if (reg == -1 && modrm.mod != 3) |
17310 | if (reg == -1 && modrm.mod != 3) |
16185 | { |
17311 | { |
16186 | OP_E_memory (bytemode, sizeflag); |
17312 | OP_E_memory (bytemode, sizeflag); |
16187 | return; |
17313 | return; |
16188 | } |
17314 | } |
16189 | else |
17315 | else |
16190 | { |
17316 | { |
16191 | if (reg == -1) |
17317 | if (reg == -1) |
16192 | { |
17318 | { |
16193 | reg = modrm.rm; |
17319 | reg = modrm.rm; |
16194 | USED_REX (REX_B); |
17320 | USED_REX (REX_B); |
16195 | if (rex & REX_B) |
17321 | if (rex & REX_B) |
16196 | reg += 8; |
17322 | reg += 8; |
16197 | } |
17323 | } |
16198 | else if (reg > 7 && address_mode != mode_64bit) |
17324 | else if (reg > 7 && address_mode != mode_64bit) |
16199 | BadOp (); |
17325 | BadOp (); |
16200 | } |
17326 | } |
16201 | 17327 | ||
16202 | switch (vex.length) |
17328 | switch (vex.length) |
16203 | { |
17329 | { |
16204 | case 128: |
17330 | case 128: |
16205 | names = names_xmm; |
17331 | names = names_xmm; |
16206 | break; |
17332 | break; |
16207 | case 256: |
17333 | case 256: |
16208 | names = names_ymm; |
17334 | names = names_ymm; |
16209 | break; |
17335 | break; |
16210 | default: |
17336 | default: |
16211 | abort (); |
17337 | abort (); |
16212 | } |
17338 | } |
16213 | oappend (names[reg]); |
17339 | oappend (names[reg]); |
16214 | } |
17340 | } |
16215 | 17341 | ||
16216 | static void |
17342 | static void |
16217 | OP_EX_VexImmW (int bytemode, int sizeflag) |
17343 | OP_EX_VexImmW (int bytemode, int sizeflag) |
16218 | { |
17344 | { |
16219 | int reg = -1; |
17345 | int reg = -1; |
16220 | static unsigned char vex_imm8; |
17346 | static unsigned char vex_imm8; |
16221 | 17347 | ||
16222 | if (vex_w_done == 0) |
17348 | if (vex_w_done == 0) |
16223 | { |
17349 | { |
16224 | vex_w_done = 1; |
17350 | vex_w_done = 1; |
16225 | 17351 | ||
16226 | /* Skip mod/rm byte. */ |
17352 | /* Skip mod/rm byte. */ |
16227 | MODRM_CHECK; |
17353 | MODRM_CHECK; |
16228 | codep++; |
17354 | codep++; |
16229 | 17355 | ||
16230 | vex_imm8 = get_vex_imm8 (sizeflag, 0); |
17356 | vex_imm8 = get_vex_imm8 (sizeflag, 0); |
16231 | 17357 | ||
16232 | if (vex.w) |
17358 | if (vex.w) |
16233 | reg = vex_imm8 >> 4; |
17359 | reg = vex_imm8 >> 4; |
16234 | 17360 | ||
16235 | OP_EX_VexReg (bytemode, sizeflag, reg); |
17361 | OP_EX_VexReg (bytemode, sizeflag, reg); |
16236 | } |
17362 | } |
16237 | else if (vex_w_done == 1) |
17363 | else if (vex_w_done == 1) |
16238 | { |
17364 | { |
16239 | vex_w_done = 2; |
17365 | vex_w_done = 2; |
16240 | 17366 | ||
16241 | if (!vex.w) |
17367 | if (!vex.w) |
16242 | reg = vex_imm8 >> 4; |
17368 | reg = vex_imm8 >> 4; |
16243 | 17369 | ||
16244 | OP_EX_VexReg (bytemode, sizeflag, reg); |
17370 | OP_EX_VexReg (bytemode, sizeflag, reg); |
16245 | } |
17371 | } |
16246 | else |
17372 | else |
16247 | { |
17373 | { |
16248 | /* Output the imm8 directly. */ |
17374 | /* Output the imm8 directly. */ |
16249 | scratchbuf[0] = '$'; |
17375 | scratchbuf[0] = '$'; |
16250 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); |
17376 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); |
16251 | oappend_maybe_intel (scratchbuf); |
17377 | oappend_maybe_intel (scratchbuf); |
16252 | scratchbuf[0] = '\0'; |
17378 | scratchbuf[0] = '\0'; |
16253 | codep++; |
17379 | codep++; |
16254 | } |
17380 | } |
16255 | } |
17381 | } |
16256 | 17382 | ||
16257 | static void |
17383 | static void |
16258 | OP_Vex_2src (int bytemode, int sizeflag) |
17384 | OP_Vex_2src (int bytemode, int sizeflag) |
16259 | { |
17385 | { |
16260 | if (modrm.mod == 3) |
17386 | if (modrm.mod == 3) |
16261 | { |
17387 | { |
16262 | int reg = modrm.rm; |
17388 | int reg = modrm.rm; |
16263 | USED_REX (REX_B); |
17389 | USED_REX (REX_B); |
16264 | if (rex & REX_B) |
17390 | if (rex & REX_B) |
16265 | reg += 8; |
17391 | reg += 8; |
16266 | oappend (names_xmm[reg]); |
17392 | oappend (names_xmm[reg]); |
16267 | } |
17393 | } |
16268 | else |
17394 | else |
16269 | { |
17395 | { |
16270 | if (intel_syntax |
17396 | if (intel_syntax |
16271 | && (bytemode == v_mode || bytemode == v_swap_mode)) |
17397 | && (bytemode == v_mode || bytemode == v_swap_mode)) |
16272 | { |
17398 | { |
16273 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
17399 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
16274 | used_prefixes |= (prefixes & PREFIX_DATA); |
17400 | used_prefixes |= (prefixes & PREFIX_DATA); |
16275 | } |
17401 | } |
16276 | OP_E (bytemode, sizeflag); |
17402 | OP_E (bytemode, sizeflag); |
16277 | } |
17403 | } |
16278 | } |
17404 | } |
16279 | 17405 | ||
16280 | static void |
17406 | static void |
16281 | OP_Vex_2src_1 (int bytemode, int sizeflag) |
17407 | OP_Vex_2src_1 (int bytemode, int sizeflag) |
16282 | { |
17408 | { |
16283 | if (modrm.mod == 3) |
17409 | if (modrm.mod == 3) |
16284 | { |
17410 | { |
16285 | /* Skip mod/rm byte. */ |
17411 | /* Skip mod/rm byte. */ |
16286 | MODRM_CHECK; |
17412 | MODRM_CHECK; |
16287 | codep++; |
17413 | codep++; |
16288 | } |
17414 | } |
16289 | 17415 | ||
16290 | if (vex.w) |
17416 | if (vex.w) |
16291 | oappend (names_xmm[vex.register_specifier]); |
17417 | oappend (names_xmm[vex.register_specifier]); |
16292 | else |
17418 | else |
16293 | OP_Vex_2src (bytemode, sizeflag); |
17419 | OP_Vex_2src (bytemode, sizeflag); |
16294 | } |
17420 | } |
16295 | 17421 | ||
16296 | static void |
17422 | static void |
16297 | OP_Vex_2src_2 (int bytemode, int sizeflag) |
17423 | OP_Vex_2src_2 (int bytemode, int sizeflag) |
16298 | { |
17424 | { |
16299 | if (vex.w) |
17425 | if (vex.w) |
16300 | OP_Vex_2src (bytemode, sizeflag); |
17426 | OP_Vex_2src (bytemode, sizeflag); |
16301 | else |
17427 | else |
16302 | oappend (names_xmm[vex.register_specifier]); |
17428 | oappend (names_xmm[vex.register_specifier]); |
16303 | } |
17429 | } |
16304 | 17430 | ||
16305 | static void |
17431 | static void |
16306 | OP_EX_VexW (int bytemode, int sizeflag) |
17432 | OP_EX_VexW (int bytemode, int sizeflag) |
16307 | { |
17433 | { |
16308 | int reg = -1; |
17434 | int reg = -1; |
16309 | 17435 | ||
16310 | if (!vex_w_done) |
17436 | if (!vex_w_done) |
16311 | { |
17437 | { |
16312 | vex_w_done = 1; |
17438 | vex_w_done = 1; |
16313 | 17439 | ||
16314 | /* Skip mod/rm byte. */ |
17440 | /* Skip mod/rm byte. */ |
16315 | MODRM_CHECK; |
17441 | MODRM_CHECK; |
16316 | codep++; |
17442 | codep++; |
16317 | 17443 | ||
16318 | if (vex.w) |
17444 | if (vex.w) |
16319 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
17445 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
16320 | } |
17446 | } |
16321 | else |
17447 | else |
16322 | { |
17448 | { |
16323 | if (!vex.w) |
17449 | if (!vex.w) |
16324 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
17450 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
16325 | } |
17451 | } |
16326 | 17452 | ||
16327 | OP_EX_VexReg (bytemode, sizeflag, reg); |
17453 | OP_EX_VexReg (bytemode, sizeflag, reg); |
16328 | } |
17454 | } |
16329 | 17455 | ||
16330 | static void |
17456 | static void |
16331 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, |
17457 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, |
16332 | int sizeflag ATTRIBUTE_UNUSED) |
17458 | int sizeflag ATTRIBUTE_UNUSED) |
16333 | { |
17459 | { |
16334 | /* Skip the immediate byte and check for invalid bits. */ |
17460 | /* Skip the immediate byte and check for invalid bits. */ |
16335 | FETCH_DATA (the_info, codep + 1); |
17461 | FETCH_DATA (the_info, codep + 1); |
16336 | if (*codep++ & 0xf) |
17462 | if (*codep++ & 0xf) |
16337 | BadOp (); |
17463 | BadOp (); |
16338 | } |
17464 | } |
16339 | 17465 | ||
16340 | static void |
17466 | static void |
16341 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
17467 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
16342 | { |
17468 | { |
16343 | int reg; |
17469 | int reg; |
16344 | const char **names; |
17470 | const char **names; |
16345 | 17471 | ||
16346 | FETCH_DATA (the_info, codep + 1); |
17472 | FETCH_DATA (the_info, codep + 1); |
16347 | reg = *codep++; |
17473 | reg = *codep++; |
16348 | 17474 | ||
16349 | if (bytemode != x_mode) |
17475 | if (bytemode != x_mode) |
16350 | abort (); |
17476 | abort (); |
16351 | 17477 | ||
16352 | if (reg & 0xf) |
17478 | if (reg & 0xf) |
16353 | BadOp (); |
17479 | BadOp (); |
16354 | 17480 | ||
16355 | reg >>= 4; |
17481 | reg >>= 4; |
16356 | if (reg > 7 && address_mode != mode_64bit) |
17482 | if (reg > 7 && address_mode != mode_64bit) |
16357 | BadOp (); |
17483 | BadOp (); |
16358 | 17484 | ||
16359 | switch (vex.length) |
17485 | switch (vex.length) |
16360 | { |
17486 | { |
16361 | case 128: |
17487 | case 128: |
16362 | names = names_xmm; |
17488 | names = names_xmm; |
16363 | break; |
17489 | break; |
16364 | case 256: |
17490 | case 256: |
16365 | names = names_ymm; |
17491 | names = names_ymm; |
16366 | break; |
17492 | break; |
16367 | default: |
17493 | default: |
16368 | abort (); |
17494 | abort (); |
16369 | } |
17495 | } |
16370 | oappend (names[reg]); |
17496 | oappend (names[reg]); |
16371 | } |
17497 | } |
16372 | 17498 | ||
16373 | static void |
17499 | static void |
16374 | OP_XMM_VexW (int bytemode, int sizeflag) |
17500 | OP_XMM_VexW (int bytemode, int sizeflag) |
16375 | { |
17501 | { |
16376 | /* Turn off the REX.W bit since it is used for swapping operands |
17502 | /* Turn off the REX.W bit since it is used for swapping operands |
16377 | now. */ |
17503 | now. */ |
16378 | rex &= ~REX_W; |
17504 | rex &= ~REX_W; |
16379 | OP_XMM (bytemode, sizeflag); |
17505 | OP_XMM (bytemode, sizeflag); |
16380 | } |
17506 | } |
16381 | 17507 | ||
16382 | static void |
17508 | static void |
16383 | OP_EX_Vex (int bytemode, int sizeflag) |
17509 | OP_EX_Vex (int bytemode, int sizeflag) |
16384 | { |
17510 | { |
16385 | if (modrm.mod != 3) |
17511 | if (modrm.mod != 3) |
16386 | { |
17512 | { |
16387 | if (vex.register_specifier != 0) |
17513 | if (vex.register_specifier != 0) |
16388 | BadOp (); |
17514 | BadOp (); |
16389 | need_vex_reg = 0; |
17515 | need_vex_reg = 0; |
16390 | } |
17516 | } |
16391 | OP_EX (bytemode, sizeflag); |
17517 | OP_EX (bytemode, sizeflag); |
16392 | } |
17518 | } |
16393 | 17519 | ||
16394 | static void |
17520 | static void |
16395 | OP_XMM_Vex (int bytemode, int sizeflag) |
17521 | OP_XMM_Vex (int bytemode, int sizeflag) |
16396 | { |
17522 | { |
16397 | if (modrm.mod != 3) |
17523 | if (modrm.mod != 3) |
16398 | { |
17524 | { |
16399 | if (vex.register_specifier != 0) |
17525 | if (vex.register_specifier != 0) |
16400 | BadOp (); |
17526 | BadOp (); |
16401 | need_vex_reg = 0; |
17527 | need_vex_reg = 0; |
16402 | } |
17528 | } |
16403 | OP_XMM (bytemode, sizeflag); |
17529 | OP_XMM (bytemode, sizeflag); |
16404 | } |
17530 | } |
16405 | 17531 | ||
16406 | static void |
17532 | static void |
16407 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
17533 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16408 | { |
17534 | { |
16409 | switch (vex.length) |
17535 | switch (vex.length) |
16410 | { |
17536 | { |
16411 | case 128: |
17537 | case 128: |
16412 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
17538 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
16413 | break; |
17539 | break; |
16414 | case 256: |
17540 | case 256: |
16415 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
17541 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
16416 | break; |
17542 | break; |
16417 | default: |
17543 | default: |
16418 | abort (); |
17544 | abort (); |
16419 | } |
17545 | } |
16420 | } |
17546 | } |
16421 | 17547 | ||
16422 | static struct op vex_cmp_op[] = |
17548 | static struct op vex_cmp_op[] = |
16423 | { |
17549 | { |
16424 | { STRING_COMMA_LEN ("eq") }, |
17550 | { STRING_COMMA_LEN ("eq") }, |
16425 | { STRING_COMMA_LEN ("lt") }, |
17551 | { STRING_COMMA_LEN ("lt") }, |
16426 | { STRING_COMMA_LEN ("le") }, |
17552 | { STRING_COMMA_LEN ("le") }, |
16427 | { STRING_COMMA_LEN ("unord") }, |
17553 | { STRING_COMMA_LEN ("unord") }, |
16428 | { STRING_COMMA_LEN ("neq") }, |
17554 | { STRING_COMMA_LEN ("neq") }, |
16429 | { STRING_COMMA_LEN ("nlt") }, |
17555 | { STRING_COMMA_LEN ("nlt") }, |
16430 | { STRING_COMMA_LEN ("nle") }, |
17556 | { STRING_COMMA_LEN ("nle") }, |
16431 | { STRING_COMMA_LEN ("ord") }, |
17557 | { STRING_COMMA_LEN ("ord") }, |
16432 | { STRING_COMMA_LEN ("eq_uq") }, |
17558 | { STRING_COMMA_LEN ("eq_uq") }, |
16433 | { STRING_COMMA_LEN ("nge") }, |
17559 | { STRING_COMMA_LEN ("nge") }, |
16434 | { STRING_COMMA_LEN ("ngt") }, |
17560 | { STRING_COMMA_LEN ("ngt") }, |
16435 | { STRING_COMMA_LEN ("false") }, |
17561 | { STRING_COMMA_LEN ("false") }, |
16436 | { STRING_COMMA_LEN ("neq_oq") }, |
17562 | { STRING_COMMA_LEN ("neq_oq") }, |
16437 | { STRING_COMMA_LEN ("ge") }, |
17563 | { STRING_COMMA_LEN ("ge") }, |
16438 | { STRING_COMMA_LEN ("gt") }, |
17564 | { STRING_COMMA_LEN ("gt") }, |
16439 | { STRING_COMMA_LEN ("true") }, |
17565 | { STRING_COMMA_LEN ("true") }, |
16440 | { STRING_COMMA_LEN ("eq_os") }, |
17566 | { STRING_COMMA_LEN ("eq_os") }, |
16441 | { STRING_COMMA_LEN ("lt_oq") }, |
17567 | { STRING_COMMA_LEN ("lt_oq") }, |
16442 | { STRING_COMMA_LEN ("le_oq") }, |
17568 | { STRING_COMMA_LEN ("le_oq") }, |
16443 | { STRING_COMMA_LEN ("unord_s") }, |
17569 | { STRING_COMMA_LEN ("unord_s") }, |
16444 | { STRING_COMMA_LEN ("neq_us") }, |
17570 | { STRING_COMMA_LEN ("neq_us") }, |
16445 | { STRING_COMMA_LEN ("nlt_uq") }, |
17571 | { STRING_COMMA_LEN ("nlt_uq") }, |
16446 | { STRING_COMMA_LEN ("nle_uq") }, |
17572 | { STRING_COMMA_LEN ("nle_uq") }, |
16447 | { STRING_COMMA_LEN ("ord_s") }, |
17573 | { STRING_COMMA_LEN ("ord_s") }, |
16448 | { STRING_COMMA_LEN ("eq_us") }, |
17574 | { STRING_COMMA_LEN ("eq_us") }, |
16449 | { STRING_COMMA_LEN ("nge_uq") }, |
17575 | { STRING_COMMA_LEN ("nge_uq") }, |
16450 | { STRING_COMMA_LEN ("ngt_uq") }, |
17576 | { STRING_COMMA_LEN ("ngt_uq") }, |
16451 | { STRING_COMMA_LEN ("false_os") }, |
17577 | { STRING_COMMA_LEN ("false_os") }, |
16452 | { STRING_COMMA_LEN ("neq_os") }, |
17578 | { STRING_COMMA_LEN ("neq_os") }, |
16453 | { STRING_COMMA_LEN ("ge_oq") }, |
17579 | { STRING_COMMA_LEN ("ge_oq") }, |
16454 | { STRING_COMMA_LEN ("gt_oq") }, |
17580 | { STRING_COMMA_LEN ("gt_oq") }, |
16455 | { STRING_COMMA_LEN ("true_us") }, |
17581 | { STRING_COMMA_LEN ("true_us") }, |
16456 | }; |
17582 | }; |
16457 | 17583 | ||
16458 | static void |
17584 | static void |
16459 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
17585 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16460 | { |
17586 | { |
16461 | unsigned int cmp_type; |
17587 | unsigned int cmp_type; |
16462 | 17588 | ||
16463 | FETCH_DATA (the_info, codep + 1); |
17589 | FETCH_DATA (the_info, codep + 1); |
16464 | cmp_type = *codep++ & 0xff; |
17590 | cmp_type = *codep++ & 0xff; |
16465 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) |
17591 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) |
16466 | { |
17592 | { |
16467 | char suffix [3]; |
17593 | char suffix [3]; |
16468 | char *p = mnemonicendp - 2; |
17594 | char *p = mnemonicendp - 2; |
16469 | suffix[0] = p[0]; |
17595 | suffix[0] = p[0]; |
16470 | suffix[1] = p[1]; |
17596 | suffix[1] = p[1]; |
16471 | suffix[2] = '\0'; |
17597 | suffix[2] = '\0'; |
16472 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
17598 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16473 | mnemonicendp += vex_cmp_op[cmp_type].len; |
17599 | mnemonicendp += vex_cmp_op[cmp_type].len; |
16474 | } |
17600 | } |
16475 | else |
17601 | else |
16476 | { |
17602 | { |
16477 | /* We have a reserved extension byte. Output it directly. */ |
17603 | /* We have a reserved extension byte. Output it directly. */ |
16478 | scratchbuf[0] = '$'; |
17604 | scratchbuf[0] = '$'; |
16479 | print_operand_value (scratchbuf + 1, 1, cmp_type); |
17605 | print_operand_value (scratchbuf + 1, 1, cmp_type); |
16480 | oappend_maybe_intel (scratchbuf); |
17606 | oappend_maybe_intel (scratchbuf); |
16481 | scratchbuf[0] = '\0'; |
17607 | scratchbuf[0] = '\0'; |
16482 | } |
17608 | } |
16483 | } |
17609 | } |
16484 | 17610 | ||
16485 | static void |
17611 | static void |
16486 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, |
17612 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, |
16487 | int sizeflag ATTRIBUTE_UNUSED) |
17613 | int sizeflag ATTRIBUTE_UNUSED) |
16488 | { |
17614 | { |
16489 | unsigned int cmp_type; |
17615 | unsigned int cmp_type; |
16490 | 17616 | ||
16491 | if (!vex.evex) |
17617 | if (!vex.evex) |
16492 | abort (); |
17618 | abort (); |
16493 | 17619 | ||
16494 | FETCH_DATA (the_info, codep + 1); |
17620 | FETCH_DATA (the_info, codep + 1); |
16495 | cmp_type = *codep++ & 0xff; |
17621 | cmp_type = *codep++ & 0xff; |
16496 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. |
17622 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. |
16497 | If it's the case, print suffix, otherwise - print the immediate. */ |
17623 | If it's the case, print suffix, otherwise - print the immediate. */ |
16498 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) |
17624 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) |
16499 | && cmp_type != 3 |
17625 | && cmp_type != 3 |
16500 | && cmp_type != 7) |
17626 | && cmp_type != 7) |
16501 | { |
17627 | { |
16502 | char suffix [3]; |
17628 | char suffix [3]; |
16503 | char *p = mnemonicendp - 2; |
17629 | char *p = mnemonicendp - 2; |
16504 | 17630 | ||
16505 | /* vpcmp* can have both one- and two-lettered suffix. */ |
17631 | /* vpcmp* can have both one- and two-lettered suffix. */ |
16506 | if (p[0] == 'p') |
17632 | if (p[0] == 'p') |
16507 | { |
17633 | { |
16508 | p++; |
17634 | p++; |
16509 | suffix[0] = p[0]; |
17635 | suffix[0] = p[0]; |
16510 | suffix[1] = '\0'; |
17636 | suffix[1] = '\0'; |
16511 | } |
17637 | } |
16512 | else |
17638 | else |
16513 | { |
17639 | { |
16514 | suffix[0] = p[0]; |
17640 | suffix[0] = p[0]; |
16515 | suffix[1] = p[1]; |
17641 | suffix[1] = p[1]; |
16516 | suffix[2] = '\0'; |
17642 | suffix[2] = '\0'; |
16517 | } |
17643 | } |
16518 | 17644 | ||
16519 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
17645 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16520 | mnemonicendp += simd_cmp_op[cmp_type].len; |
17646 | mnemonicendp += simd_cmp_op[cmp_type].len; |
16521 | } |
17647 | } |
16522 | else |
17648 | else |
16523 | { |
17649 | { |
16524 | /* We have a reserved extension byte. Output it directly. */ |
17650 | /* We have a reserved extension byte. Output it directly. */ |
16525 | scratchbuf[0] = '$'; |
17651 | scratchbuf[0] = '$'; |
16526 | print_operand_value (scratchbuf + 1, 1, cmp_type); |
17652 | print_operand_value (scratchbuf + 1, 1, cmp_type); |
16527 | oappend_maybe_intel (scratchbuf); |
17653 | oappend_maybe_intel (scratchbuf); |
16528 | scratchbuf[0] = '\0'; |
17654 | scratchbuf[0] = '\0'; |
16529 | } |
17655 | } |
16530 | } |
17656 | } |
16531 | 17657 | ||
16532 | static const struct op pclmul_op[] = |
17658 | static const struct op pclmul_op[] = |
16533 | { |
17659 | { |
16534 | { STRING_COMMA_LEN ("lql") }, |
17660 | { STRING_COMMA_LEN ("lql") }, |
16535 | { STRING_COMMA_LEN ("hql") }, |
17661 | { STRING_COMMA_LEN ("hql") }, |
16536 | { STRING_COMMA_LEN ("lqh") }, |
17662 | { STRING_COMMA_LEN ("lqh") }, |
16537 | { STRING_COMMA_LEN ("hqh") } |
17663 | { STRING_COMMA_LEN ("hqh") } |
16538 | }; |
17664 | }; |
16539 | 17665 | ||
16540 | static void |
17666 | static void |
16541 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, |
17667 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, |
16542 | int sizeflag ATTRIBUTE_UNUSED) |
17668 | int sizeflag ATTRIBUTE_UNUSED) |
16543 | { |
17669 | { |
16544 | unsigned int pclmul_type; |
17670 | unsigned int pclmul_type; |
16545 | 17671 | ||
16546 | FETCH_DATA (the_info, codep + 1); |
17672 | FETCH_DATA (the_info, codep + 1); |
16547 | pclmul_type = *codep++ & 0xff; |
17673 | pclmul_type = *codep++ & 0xff; |
16548 | switch (pclmul_type) |
17674 | switch (pclmul_type) |
16549 | { |
17675 | { |
16550 | case 0x10: |
17676 | case 0x10: |
16551 | pclmul_type = 2; |
17677 | pclmul_type = 2; |
16552 | break; |
17678 | break; |
16553 | case 0x11: |
17679 | case 0x11: |
16554 | pclmul_type = 3; |
17680 | pclmul_type = 3; |
16555 | break; |
17681 | break; |
16556 | default: |
17682 | default: |
16557 | break; |
17683 | break; |
16558 | } |
17684 | } |
16559 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
17685 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16560 | { |
17686 | { |
16561 | char suffix [4]; |
17687 | char suffix [4]; |
16562 | char *p = mnemonicendp - 3; |
17688 | char *p = mnemonicendp - 3; |
16563 | suffix[0] = p[0]; |
17689 | suffix[0] = p[0]; |
16564 | suffix[1] = p[1]; |
17690 | suffix[1] = p[1]; |
16565 | suffix[2] = p[2]; |
17691 | suffix[2] = p[2]; |
16566 | suffix[3] = '\0'; |
17692 | suffix[3] = '\0'; |
16567 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
17693 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16568 | mnemonicendp += pclmul_op[pclmul_type].len; |
17694 | mnemonicendp += pclmul_op[pclmul_type].len; |
16569 | } |
17695 | } |
16570 | else |
17696 | else |
16571 | { |
17697 | { |
16572 | /* We have a reserved extension byte. Output it directly. */ |
17698 | /* We have a reserved extension byte. Output it directly. */ |
16573 | scratchbuf[0] = '$'; |
17699 | scratchbuf[0] = '$'; |
16574 | print_operand_value (scratchbuf + 1, 1, pclmul_type); |
17700 | print_operand_value (scratchbuf + 1, 1, pclmul_type); |
16575 | oappend_maybe_intel (scratchbuf); |
17701 | oappend_maybe_intel (scratchbuf); |
16576 | scratchbuf[0] = '\0'; |
17702 | scratchbuf[0] = '\0'; |
16577 | } |
17703 | } |
16578 | } |
17704 | } |
16579 | 17705 | ||
16580 | static void |
17706 | static void |
16581 | MOVBE_Fixup (int bytemode, int sizeflag) |
17707 | MOVBE_Fixup (int bytemode, int sizeflag) |
16582 | { |
17708 | { |
16583 | /* Add proper suffix to "movbe". */ |
17709 | /* Add proper suffix to "movbe". */ |
16584 | char *p = mnemonicendp; |
17710 | char *p = mnemonicendp; |
16585 | 17711 | ||
16586 | switch (bytemode) |
17712 | switch (bytemode) |
16587 | { |
17713 | { |
16588 | case v_mode: |
17714 | case v_mode: |
16589 | if (intel_syntax) |
17715 | if (intel_syntax) |
16590 | goto skip; |
17716 | goto skip; |
16591 | 17717 | ||
16592 | USED_REX (REX_W); |
17718 | USED_REX (REX_W); |
16593 | if (sizeflag & SUFFIX_ALWAYS) |
17719 | if (sizeflag & SUFFIX_ALWAYS) |
16594 | { |
17720 | { |
16595 | if (rex & REX_W) |
17721 | if (rex & REX_W) |
16596 | *p++ = 'q'; |
17722 | *p++ = 'q'; |
16597 | else |
17723 | else |
16598 | { |
17724 | { |
16599 | if (sizeflag & DFLAG) |
17725 | if (sizeflag & DFLAG) |
16600 | *p++ = 'l'; |
17726 | *p++ = 'l'; |
16601 | else |
17727 | else |
16602 | *p++ = 'w'; |
17728 | *p++ = 'w'; |
16603 | used_prefixes |= (prefixes & PREFIX_DATA); |
17729 | used_prefixes |= (prefixes & PREFIX_DATA); |
16604 | } |
17730 | } |
16605 | } |
17731 | } |
16606 | break; |
17732 | break; |
16607 | default: |
17733 | default: |
16608 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
17734 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
16609 | break; |
17735 | break; |
16610 | } |
17736 | } |
16611 | mnemonicendp = p; |
17737 | mnemonicendp = p; |
16612 | *p = '\0'; |
17738 | *p = '\0'; |
16613 | 17739 | ||
16614 | skip: |
17740 | skip: |
16615 | OP_M (bytemode, sizeflag); |
17741 | OP_M (bytemode, sizeflag); |
16616 | } |
17742 | } |
16617 | 17743 | ||
16618 | static void |
17744 | static void |
16619 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
17745 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16620 | { |
17746 | { |
16621 | int reg; |
17747 | int reg; |
16622 | const char **names; |
17748 | const char **names; |
16623 | 17749 | ||
16624 | /* Skip mod/rm byte. */ |
17750 | /* Skip mod/rm byte. */ |
16625 | MODRM_CHECK; |
17751 | MODRM_CHECK; |
16626 | codep++; |
17752 | codep++; |
16627 | 17753 | ||
16628 | if (vex.w) |
17754 | if (vex.w) |
16629 | names = names64; |
17755 | names = names64; |
16630 | else |
17756 | else |
16631 | names = names32; |
17757 | names = names32; |
16632 | 17758 | ||
16633 | reg = modrm.rm; |
17759 | reg = modrm.rm; |
16634 | USED_REX (REX_B); |
17760 | USED_REX (REX_B); |
16635 | if (rex & REX_B) |
17761 | if (rex & REX_B) |
16636 | reg += 8; |
17762 | reg += 8; |
16637 | 17763 | ||
16638 | oappend (names[reg]); |
17764 | oappend (names[reg]); |
16639 | } |
17765 | } |
16640 | 17766 | ||
16641 | static void |
17767 | static void |
16642 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
17768 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
16643 | { |
17769 | { |
16644 | const char **names; |
17770 | const char **names; |
16645 | 17771 | ||
16646 | if (vex.w) |
17772 | if (vex.w) |
16647 | names = names64; |
17773 | names = names64; |
16648 | else |
17774 | else |
16649 | names = names32; |
17775 | names = names32; |
16650 | 17776 | ||
16651 | oappend (names[vex.register_specifier]); |
17777 | oappend (names[vex.register_specifier]); |
16652 | } |
17778 | } |
16653 | 17779 | ||
16654 | static void |
17780 | static void |
16655 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
17781 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
16656 | { |
17782 | { |
16657 | if (!vex.evex |
17783 | if (!vex.evex |
16658 | || bytemode != mask_mode) |
17784 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
16659 | abort (); |
17785 | abort (); |
16660 | 17786 | ||
16661 | USED_REX (REX_R); |
17787 | USED_REX (REX_R); |
16662 | if ((rex & REX_R) != 0 || !vex.r) |
17788 | if ((rex & REX_R) != 0 || !vex.r) |
16663 | { |
17789 | { |
16664 | BadOp (); |
17790 | BadOp (); |
16665 | return; |
17791 | return; |
16666 | } |
17792 | } |
16667 | 17793 | ||
16668 | oappend (names_mask [modrm.reg]); |
17794 | oappend (names_mask [modrm.reg]); |
16669 | } |
17795 | } |
16670 | 17796 | ||
16671 | static void |
17797 | static void |
16672 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
17798 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
16673 | { |
17799 | { |
16674 | if (!vex.evex |
17800 | if (!vex.evex |
16675 | || (bytemode != evex_rounding_mode |
17801 | || (bytemode != evex_rounding_mode |
16676 | && bytemode != evex_sae_mode)) |
17802 | && bytemode != evex_sae_mode)) |
16677 | abort (); |
17803 | abort (); |
16678 | if (modrm.mod == 3 && vex.b) |
17804 | if (modrm.mod == 3 && vex.b) |
16679 | switch (bytemode) |
17805 | switch (bytemode) |
16680 | { |
17806 | { |
16681 | case evex_rounding_mode: |
17807 | case evex_rounding_mode: |
16682 | oappend (names_rounding[vex.ll]); |
17808 | oappend (names_rounding[vex.ll]); |
16683 | break; |
17809 | break; |
16684 | case evex_sae_mode: |
17810 | case evex_sae_mode: |
16685 | oappend ("{sae}"); |
17811 | oappend ("{sae}"); |
16686 | break; |
17812 | break; |
16687 | default: |
17813 | default: |
16688 | break; |
17814 | break; |
16689 | } |
17815 | } |
16690 | }>>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>=><=>>>>>>>>>>>>>>>>>>>>>=>=> |
17816 | }>>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>=><=>>>>>>>>>>>>>>>>>>>>>><>><>><>><>><>=>=> |