Rev 5221 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 5221 | Rev 6324 | ||
---|---|---|---|
Line 1... | Line 1... | ||
1 | /* Print i386 instructions for GDB, the GNU debugger. |
1 | /* Print i386 instructions for GDB, the GNU debugger. |
2 | Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
- | |
3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
- | |
4 | Free Software Foundation, Inc. |
2 | Copyright (C) 1988-2015 Free Software Foundation, Inc. |
Line 5... | Line 3... | ||
5 | 3 | ||
Line 6... | Line 4... | ||
6 | This file is part of the GNU opcodes library. |
4 | This file is part of the GNU opcodes library. |
7 | 5 | ||
Line 102... | Line 100... | ||
102 | static void VCMP_Fixup (int, int); |
100 | static void VCMP_Fixup (int, int); |
103 | static void VPCMP_Fixup (int, int); |
101 | static void VPCMP_Fixup (int, int); |
104 | static void OP_0f07 (int, int); |
102 | static void OP_0f07 (int, int); |
105 | static void OP_Monitor (int, int); |
103 | static void OP_Monitor (int, int); |
106 | static void OP_Mwait (int, int); |
104 | static void OP_Mwait (int, int); |
- | 105 | static void OP_Mwaitx (int, int); |
|
107 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup1 (int, int); |
108 | static void NOP_Fixup2 (int, int); |
107 | static void NOP_Fixup2 (int, int); |
109 | static void OP_3DNowSuffix (int, int); |
108 | static void OP_3DNowSuffix (int, int); |
110 | static void CMP_Fixup (int, int); |
109 | static void CMP_Fixup (int, int); |
111 | static void BadOp (void); |
110 | static void BadOp (void); |
Line 131... | Line 130... | ||
131 | /* Points to first byte not fetched. */ |
130 | /* Points to first byte not fetched. */ |
132 | bfd_byte *max_fetched; |
131 | bfd_byte *max_fetched; |
133 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
132 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
134 | bfd_vma insn_start; |
133 | bfd_vma insn_start; |
135 | int orig_sizeflag; |
134 | int orig_sizeflag; |
136 | jmp_buf bailout; |
135 | OPCODES_SIGJMP_BUF bailout; |
137 | }; |
136 | }; |
Line 138... | Line 137... | ||
138 | 137 | ||
139 | enum address_mode |
138 | enum address_mode |
140 | { |
139 | { |
Line 214... | Line 213... | ||
214 | print_insn_i386 will do something sensible. Otherwise, print |
213 | print_insn_i386 will do something sensible. Otherwise, print |
215 | an error. We do that here because this is where we know |
214 | an error. We do that here because this is where we know |
216 | STATUS. */ |
215 | STATUS. */ |
217 | if (priv->max_fetched == priv->the_buffer) |
216 | if (priv->max_fetched == priv->the_buffer) |
218 | (*info->memory_error_func) (status, start, info); |
217 | (*info->memory_error_func) (status, start, info); |
219 | longjmp (priv->bailout, 1); |
218 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
220 | } |
219 | } |
221 | else |
220 | else |
222 | priv->max_fetched = addr; |
221 | priv->max_fetched = addr; |
223 | return 1; |
222 | return 1; |
224 | } |
223 | } |
Line -... | Line 224... | ||
- | 224 | ||
- | 225 | /* Possible values for prefix requirement. */ |
|
- | 226 | #define PREFIX_IGNORED_SHIFT 16 |
|
- | 227 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) |
|
- | 228 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) |
|
- | 229 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) |
|
- | 230 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) |
|
- | 231 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) |
|
- | 232 | ||
- | 233 | /* Opcode prefixes. */ |
|
- | 234 | #define PREFIX_OPCODE (PREFIX_REPZ \ |
|
- | 235 | | PREFIX_REPNZ \ |
|
- | 236 | | PREFIX_DATA) |
|
- | 237 | ||
- | 238 | /* Prefixes ignored. */ |
|
- | 239 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ |
|
- | 240 | | PREFIX_IGNORED_REPNZ \ |
|
- | 241 | | PREFIX_IGNORED_DATA) |
|
225 | 242 | ||
226 | #define XX { NULL, 0 } |
243 | #define XX { NULL, 0 } |
Line 227... | Line 244... | ||
227 | #define Bad_Opcode NULL, { { NULL, 0 } } |
244 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
228 | 245 | ||
229 | #define Eb { OP_E, b_mode } |
246 | #define Eb { OP_E, b_mode } |
230 | #define Ebnd { OP_E, bnd_mode } |
247 | #define Ebnd { OP_E, bnd_mode } |
231 | #define EbS { OP_E, b_swap_mode } |
248 | #define EbS { OP_E, b_swap_mode } |
232 | #define Ev { OP_E, v_mode } |
249 | #define Ev { OP_E, v_mode } |
233 | #define Ev_bnd { OP_E, v_bnd_mode } |
250 | #define Ev_bnd { OP_E, v_bnd_mode } |
234 | #define EvS { OP_E, v_swap_mode } |
251 | #define EvS { OP_E, v_swap_mode } |
235 | #define Ed { OP_E, d_mode } |
252 | #define Ed { OP_E, d_mode } |
- | 253 | #define Edq { OP_E, dq_mode } |
|
236 | #define Edq { OP_E, dq_mode } |
254 | #define Edqw { OP_E, dqw_mode } |
- | 255 | #define EdqwS { OP_E, dqw_swap_mode } |
|
- | 256 | #define Edqb { OP_E, dqb_mode } |
|
237 | #define Edqw { OP_E, dqw_mode } |
257 | #define Edb { OP_E, db_mode } |
238 | #define Edqb { OP_E, dqb_mode } |
258 | #define Edw { OP_E, dw_mode } |
239 | #define Edqd { OP_E, dqd_mode } |
259 | #define Edqd { OP_E, dqd_mode } |
240 | #define Eq { OP_E, q_mode } |
260 | #define Eq { OP_E, q_mode } |
241 | #define indirEv { OP_indirE, stack_v_mode } |
261 | #define indirEv { OP_indirE, stack_v_mode } |
Line 423... | Line 443... | ||
423 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
443 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
Line 424... | Line 444... | ||
424 | 444 | ||
425 | #define XMask { OP_Mask, mask_mode } |
445 | #define XMask { OP_Mask, mask_mode } |
426 | #define MaskG { OP_G, mask_mode } |
446 | #define MaskG { OP_G, mask_mode } |
- | 447 | #define MaskE { OP_E, mask_mode } |
|
427 | #define MaskE { OP_E, mask_mode } |
448 | #define MaskBDE { OP_E, mask_bd_mode } |
428 | #define MaskR { OP_R, mask_mode } |
449 | #define MaskR { OP_R, mask_mode } |
Line 429... | Line 450... | ||
429 | #define MaskVex { OP_VEX, mask_mode } |
450 | #define MaskVex { OP_VEX, mask_mode } |
- | 451 | ||
430 | 452 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
|
- | 453 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
|
Line 431... | Line 454... | ||
431 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
454 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
432 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
455 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
433 | 456 | ||
434 | /* Used handle "rep" prefix for string instructions. */ |
457 | /* Used handle "rep" prefix for string instructions. */ |
Line 531... | Line 554... | ||
531 | v_bnd_mode, |
554 | v_bnd_mode, |
532 | /* operand size depends on REX prefixes. */ |
555 | /* operand size depends on REX prefixes. */ |
533 | dq_mode, |
556 | dq_mode, |
534 | /* registers like dq_mode, memory like w_mode. */ |
557 | /* registers like dq_mode, memory like w_mode. */ |
535 | dqw_mode, |
558 | dqw_mode, |
- | 559 | dqw_swap_mode, |
|
536 | bnd_mode, |
560 | bnd_mode, |
537 | /* 4- or 6-byte pointer operand */ |
561 | /* 4- or 6-byte pointer operand */ |
538 | f_mode, |
562 | f_mode, |
539 | const_1_mode, |
563 | const_1_mode, |
540 | /* v_mode for stack-related opcodes. */ |
564 | /* v_mode for stack-related opcodes. */ |
Line 543... | Line 567... | ||
543 | z_mode, |
567 | z_mode, |
544 | /* 16-byte operand */ |
568 | /* 16-byte operand */ |
545 | o_mode, |
569 | o_mode, |
546 | /* registers like dq_mode, memory like b_mode. */ |
570 | /* registers like dq_mode, memory like b_mode. */ |
547 | dqb_mode, |
571 | dqb_mode, |
- | 572 | /* registers like d_mode, memory like b_mode. */ |
|
- | 573 | db_mode, |
|
- | 574 | /* registers like d_mode, memory like w_mode. */ |
|
- | 575 | dw_mode, |
|
548 | /* registers like dq_mode, memory like d_mode. */ |
576 | /* registers like dq_mode, memory like d_mode. */ |
549 | dqd_mode, |
577 | dqd_mode, |
550 | /* normal vex mode */ |
578 | /* normal vex mode */ |
551 | vex_mode, |
579 | vex_mode, |
552 | /* 128bit vex mode */ |
580 | /* 128bit vex mode */ |
Line 556... | Line 584... | ||
556 | /* operand size depends on the VEX.W bit. */ |
584 | /* operand size depends on the VEX.W bit. */ |
557 | vex_w_dq_mode, |
585 | vex_w_dq_mode, |
Line 558... | Line 586... | ||
558 | 586 | ||
559 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
587 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
- | 588 | vex_vsib_d_w_dq_mode, |
|
- | 589 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
|
560 | vex_vsib_d_w_dq_mode, |
590 | vex_vsib_d_w_d_mode, |
561 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
591 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
- | 592 | vex_vsib_q_w_dq_mode, |
|
- | 593 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
|
Line 562... | Line 594... | ||
562 | vex_vsib_q_w_dq_mode, |
594 | vex_vsib_q_w_d_mode, |
563 | 595 | ||
564 | /* scalar, ignore vector length. */ |
596 | /* scalar, ignore vector length. */ |
565 | scalar_mode, |
597 | scalar_mode, |
Line 581... | Line 613... | ||
581 | /* Supress all exceptions. */ |
613 | /* Supress all exceptions. */ |
582 | evex_sae_mode, |
614 | evex_sae_mode, |
Line 583... | Line 615... | ||
583 | 615 | ||
584 | /* Mask register operand. */ |
616 | /* Mask register operand. */ |
- | 617 | mask_mode, |
|
- | 618 | /* Mask register operand. */ |
|
Line 585... | Line 619... | ||
585 | mask_mode, |
619 | mask_bd_mode, |
586 | 620 | ||
587 | es_reg, |
621 | es_reg, |
588 | cs_reg, |
622 | cs_reg, |
Line 646... | Line 680... | ||
646 | USE_VEX_LEN_TABLE, |
680 | USE_VEX_LEN_TABLE, |
647 | USE_VEX_W_TABLE, |
681 | USE_VEX_W_TABLE, |
648 | USE_EVEX_TABLE |
682 | USE_EVEX_TABLE |
649 | }; |
683 | }; |
Line 650... | Line 684... | ||
650 | 684 | ||
Line 651... | Line 685... | ||
651 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
685 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
- | 686 | ||
652 | 687 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
|
653 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
688 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P |
654 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
689 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
655 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) |
690 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) |
656 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) |
691 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) |
657 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) |
692 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) |
- | 693 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
|
658 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
694 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) |
659 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) |
695 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
660 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
696 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
661 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
697 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
662 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) |
698 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) |
Line 702... | Line 738... | ||
702 | REG_XOP_LWPCB, |
738 | REG_XOP_LWPCB, |
703 | REG_XOP_LWP, |
739 | REG_XOP_LWP, |
704 | REG_XOP_TBM_01, |
740 | REG_XOP_TBM_01, |
705 | REG_XOP_TBM_02, |
741 | REG_XOP_TBM_02, |
Line -... | Line 742... | ||
- | 742 | ||
706 | 743 | REG_EVEX_0F71, |
|
707 | REG_EVEX_0F72, |
744 | REG_EVEX_0F72, |
708 | REG_EVEX_0F73, |
745 | REG_EVEX_0F73, |
709 | REG_EVEX_0F38C6, |
746 | REG_EVEX_0F38C6, |
710 | REG_EVEX_0F38C7 |
747 | REG_EVEX_0F38C7 |
Line 713... | Line 750... | ||
713 | enum |
750 | enum |
714 | { |
751 | { |
715 | MOD_8D = 0, |
752 | MOD_8D = 0, |
716 | MOD_C6_REG_7, |
753 | MOD_C6_REG_7, |
717 | MOD_C7_REG_7, |
754 | MOD_C7_REG_7, |
- | 755 | MOD_FF_REG_3, |
|
- | 756 | MOD_FF_REG_5, |
|
718 | MOD_0F01_REG_0, |
757 | MOD_0F01_REG_0, |
719 | MOD_0F01_REG_1, |
758 | MOD_0F01_REG_1, |
720 | MOD_0F01_REG_2, |
759 | MOD_0F01_REG_2, |
721 | MOD_0F01_REG_3, |
760 | MOD_0F01_REG_3, |
- | 761 | MOD_0F01_REG_5, |
|
722 | MOD_0F01_REG_7, |
762 | MOD_0F01_REG_7, |
723 | MOD_0F12_PREFIX_0, |
763 | MOD_0F12_PREFIX_0, |
724 | MOD_0F13, |
764 | MOD_0F13, |
725 | MOD_0F16_PREFIX_0, |
765 | MOD_0F16_PREFIX_0, |
726 | MOD_0F17, |
766 | MOD_0F17, |
Line 733... | Line 773... | ||
733 | MOD_0F18_REG_6, |
773 | MOD_0F18_REG_6, |
734 | MOD_0F18_REG_7, |
774 | MOD_0F18_REG_7, |
735 | MOD_0F1A_PREFIX_0, |
775 | MOD_0F1A_PREFIX_0, |
736 | MOD_0F1B_PREFIX_0, |
776 | MOD_0F1B_PREFIX_0, |
737 | MOD_0F1B_PREFIX_1, |
777 | MOD_0F1B_PREFIX_1, |
738 | MOD_0F20, |
- | |
739 | MOD_0F21, |
- | |
740 | MOD_0F22, |
- | |
741 | MOD_0F23, |
- | |
742 | MOD_0F24, |
778 | MOD_0F24, |
743 | MOD_0F26, |
779 | MOD_0F26, |
744 | MOD_0F2B_PREFIX_0, |
780 | MOD_0F2B_PREFIX_0, |
745 | MOD_0F2B_PREFIX_1, |
781 | MOD_0F2B_PREFIX_1, |
746 | MOD_0F2B_PREFIX_2, |
782 | MOD_0F2B_PREFIX_2, |
Line 765... | Line 801... | ||
765 | MOD_0FAE_REG_6, |
801 | MOD_0FAE_REG_6, |
766 | MOD_0FAE_REG_7, |
802 | MOD_0FAE_REG_7, |
767 | MOD_0FB2, |
803 | MOD_0FB2, |
768 | MOD_0FB4, |
804 | MOD_0FB4, |
769 | MOD_0FB5, |
805 | MOD_0FB5, |
- | 806 | MOD_0FC3, |
|
- | 807 | MOD_0FC7_REG_3, |
|
- | 808 | MOD_0FC7_REG_4, |
|
- | 809 | MOD_0FC7_REG_5, |
|
770 | MOD_0FC7_REG_6, |
810 | MOD_0FC7_REG_6, |
771 | MOD_0FC7_REG_7, |
811 | MOD_0FC7_REG_7, |
772 | MOD_0FD7, |
812 | MOD_0FD7, |
773 | MOD_0FE7_PREFIX_2, |
813 | MOD_0FE7_PREFIX_2, |
774 | MOD_0FF0_PREFIX_3, |
814 | MOD_0FF0_PREFIX_3, |
Line 779... | Line 819... | ||
779 | MOD_VEX_0F12_PREFIX_0, |
819 | MOD_VEX_0F12_PREFIX_0, |
780 | MOD_VEX_0F13, |
820 | MOD_VEX_0F13, |
781 | MOD_VEX_0F16_PREFIX_0, |
821 | MOD_VEX_0F16_PREFIX_0, |
782 | MOD_VEX_0F17, |
822 | MOD_VEX_0F17, |
783 | MOD_VEX_0F2B, |
823 | MOD_VEX_0F2B, |
- | 824 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
|
- | 825 | MOD_VEX_W_1_0F41_P_0_LEN_1, |
|
- | 826 | MOD_VEX_W_0_0F41_P_2_LEN_1, |
|
- | 827 | MOD_VEX_W_1_0F41_P_2_LEN_1, |
|
- | 828 | MOD_VEX_W_0_0F42_P_0_LEN_1, |
|
- | 829 | MOD_VEX_W_1_0F42_P_0_LEN_1, |
|
- | 830 | MOD_VEX_W_0_0F42_P_2_LEN_1, |
|
- | 831 | MOD_VEX_W_1_0F42_P_2_LEN_1, |
|
- | 832 | MOD_VEX_W_0_0F44_P_0_LEN_1, |
|
- | 833 | MOD_VEX_W_1_0F44_P_0_LEN_1, |
|
- | 834 | MOD_VEX_W_0_0F44_P_2_LEN_1, |
|
- | 835 | MOD_VEX_W_1_0F44_P_2_LEN_1, |
|
- | 836 | MOD_VEX_W_0_0F45_P_0_LEN_1, |
|
- | 837 | MOD_VEX_W_1_0F45_P_0_LEN_1, |
|
- | 838 | MOD_VEX_W_0_0F45_P_2_LEN_1, |
|
- | 839 | MOD_VEX_W_1_0F45_P_2_LEN_1, |
|
- | 840 | MOD_VEX_W_0_0F46_P_0_LEN_1, |
|
- | 841 | MOD_VEX_W_1_0F46_P_0_LEN_1, |
|
- | 842 | MOD_VEX_W_0_0F46_P_2_LEN_1, |
|
- | 843 | MOD_VEX_W_1_0F46_P_2_LEN_1, |
|
- | 844 | MOD_VEX_W_0_0F47_P_0_LEN_1, |
|
- | 845 | MOD_VEX_W_1_0F47_P_0_LEN_1, |
|
- | 846 | MOD_VEX_W_0_0F47_P_2_LEN_1, |
|
- | 847 | MOD_VEX_W_1_0F47_P_2_LEN_1, |
|
- | 848 | MOD_VEX_W_0_0F4A_P_0_LEN_1, |
|
- | 849 | MOD_VEX_W_1_0F4A_P_0_LEN_1, |
|
- | 850 | MOD_VEX_W_0_0F4A_P_2_LEN_1, |
|
- | 851 | MOD_VEX_W_1_0F4A_P_2_LEN_1, |
|
- | 852 | MOD_VEX_W_0_0F4B_P_0_LEN_1, |
|
- | 853 | MOD_VEX_W_1_0F4B_P_0_LEN_1, |
|
- | 854 | MOD_VEX_W_0_0F4B_P_2_LEN_1, |
|
784 | MOD_VEX_0F50, |
855 | MOD_VEX_0F50, |
785 | MOD_VEX_0F71_REG_2, |
856 | MOD_VEX_0F71_REG_2, |
786 | MOD_VEX_0F71_REG_4, |
857 | MOD_VEX_0F71_REG_4, |
787 | MOD_VEX_0F71_REG_6, |
858 | MOD_VEX_0F71_REG_6, |
788 | MOD_VEX_0F72_REG_2, |
859 | MOD_VEX_0F72_REG_2, |
Line 790... | Line 861... | ||
790 | MOD_VEX_0F72_REG_6, |
861 | MOD_VEX_0F72_REG_6, |
791 | MOD_VEX_0F73_REG_2, |
862 | MOD_VEX_0F73_REG_2, |
792 | MOD_VEX_0F73_REG_3, |
863 | MOD_VEX_0F73_REG_3, |
793 | MOD_VEX_0F73_REG_6, |
864 | MOD_VEX_0F73_REG_6, |
794 | MOD_VEX_0F73_REG_7, |
865 | MOD_VEX_0F73_REG_7, |
- | 866 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
|
- | 867 | MOD_VEX_W_1_0F91_P_0_LEN_0, |
|
- | 868 | MOD_VEX_W_0_0F91_P_2_LEN_0, |
|
- | 869 | MOD_VEX_W_1_0F91_P_2_LEN_0, |
|
- | 870 | MOD_VEX_W_0_0F92_P_0_LEN_0, |
|
- | 871 | MOD_VEX_W_0_0F92_P_2_LEN_0, |
|
- | 872 | MOD_VEX_W_0_0F92_P_3_LEN_0, |
|
- | 873 | MOD_VEX_W_1_0F92_P_3_LEN_0, |
|
- | 874 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
|
- | 875 | MOD_VEX_W_0_0F93_P_2_LEN_0, |
|
- | 876 | MOD_VEX_W_0_0F93_P_3_LEN_0, |
|
- | 877 | MOD_VEX_W_1_0F93_P_3_LEN_0, |
|
- | 878 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
|
- | 879 | MOD_VEX_W_1_0F98_P_0_LEN_0, |
|
- | 880 | MOD_VEX_W_0_0F98_P_2_LEN_0, |
|
- | 881 | MOD_VEX_W_1_0F98_P_2_LEN_0, |
|
- | 882 | MOD_VEX_W_0_0F99_P_0_LEN_0, |
|
- | 883 | MOD_VEX_W_1_0F99_P_0_LEN_0, |
|
- | 884 | MOD_VEX_W_0_0F99_P_2_LEN_0, |
|
- | 885 | MOD_VEX_W_1_0F99_P_2_LEN_0, |
|
795 | MOD_VEX_0FAE_REG_2, |
886 | MOD_VEX_0FAE_REG_2, |
796 | MOD_VEX_0FAE_REG_3, |
887 | MOD_VEX_0FAE_REG_3, |
797 | MOD_VEX_0FD7_PREFIX_2, |
888 | MOD_VEX_0FD7_PREFIX_2, |
798 | MOD_VEX_0FE7_PREFIX_2, |
889 | MOD_VEX_0FE7_PREFIX_2, |
799 | MOD_VEX_0FF0_PREFIX_3, |
890 | MOD_VEX_0FF0_PREFIX_3, |
Line 804... | Line 895... | ||
804 | MOD_VEX_0F382E_PREFIX_2, |
895 | MOD_VEX_0F382E_PREFIX_2, |
805 | MOD_VEX_0F382F_PREFIX_2, |
896 | MOD_VEX_0F382F_PREFIX_2, |
806 | MOD_VEX_0F385A_PREFIX_2, |
897 | MOD_VEX_0F385A_PREFIX_2, |
807 | MOD_VEX_0F388C_PREFIX_2, |
898 | MOD_VEX_0F388C_PREFIX_2, |
808 | MOD_VEX_0F388E_PREFIX_2, |
899 | MOD_VEX_0F388E_PREFIX_2, |
- | 900 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
|
- | 901 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, |
|
- | 902 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, |
|
- | 903 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, |
|
- | 904 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, |
|
- | 905 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, |
|
- | 906 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, |
|
- | 907 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, |
|
Line 809... | Line 908... | ||
809 | 908 | ||
810 | MOD_EVEX_0F10_PREFIX_1, |
909 | MOD_EVEX_0F10_PREFIX_1, |
811 | MOD_EVEX_0F10_PREFIX_3, |
910 | MOD_EVEX_0F10_PREFIX_3, |
812 | MOD_EVEX_0F11_PREFIX_1, |
911 | MOD_EVEX_0F11_PREFIX_1, |
Line 829... | Line 928... | ||
829 | RM_C7_REG_7, |
928 | RM_C7_REG_7, |
830 | RM_0F01_REG_0, |
929 | RM_0F01_REG_0, |
831 | RM_0F01_REG_1, |
930 | RM_0F01_REG_1, |
832 | RM_0F01_REG_2, |
931 | RM_0F01_REG_2, |
833 | RM_0F01_REG_3, |
932 | RM_0F01_REG_3, |
- | 933 | RM_0F01_REG_5, |
|
834 | RM_0F01_REG_7, |
934 | RM_0F01_REG_7, |
835 | RM_0FAE_REG_5, |
935 | RM_0FAE_REG_5, |
836 | RM_0FAE_REG_6, |
936 | RM_0FAE_REG_6, |
837 | RM_0FAE_REG_7 |
937 | RM_0FAE_REG_7 |
838 | }; |
938 | }; |
Line 880... | Line 980... | ||
880 | PREFIX_0F7F, |
980 | PREFIX_0F7F, |
881 | PREFIX_0FAE_REG_0, |
981 | PREFIX_0FAE_REG_0, |
882 | PREFIX_0FAE_REG_1, |
982 | PREFIX_0FAE_REG_1, |
883 | PREFIX_0FAE_REG_2, |
983 | PREFIX_0FAE_REG_2, |
884 | PREFIX_0FAE_REG_3, |
984 | PREFIX_0FAE_REG_3, |
- | 985 | PREFIX_0FAE_REG_6, |
|
- | 986 | PREFIX_0FAE_REG_7, |
|
- | 987 | PREFIX_RM_0_0FAE_REG_7, |
|
885 | PREFIX_0FB8, |
988 | PREFIX_0FB8, |
886 | PREFIX_0FBC, |
989 | PREFIX_0FBC, |
887 | PREFIX_0FBD, |
990 | PREFIX_0FBD, |
888 | PREFIX_0FC2, |
991 | PREFIX_0FC2, |
889 | PREFIX_0FC3, |
992 | PREFIX_MOD_0_0FC3, |
- | 993 | PREFIX_MOD_0_0FC7_REG_6, |
|
890 | PREFIX_0FC7_REG_6, |
994 | PREFIX_MOD_3_0FC7_REG_6, |
- | 995 | PREFIX_MOD_3_0FC7_REG_7, |
|
891 | PREFIX_0FD0, |
996 | PREFIX_0FD0, |
892 | PREFIX_0FD6, |
997 | PREFIX_0FD6, |
893 | PREFIX_0FE6, |
998 | PREFIX_0FE6, |
894 | PREFIX_0FE7, |
999 | PREFIX_0FE7, |
895 | PREFIX_0FF0, |
1000 | PREFIX_0FF0, |
Line 979... | Line 1084... | ||
979 | PREFIX_VEX_0F42, |
1084 | PREFIX_VEX_0F42, |
980 | PREFIX_VEX_0F44, |
1085 | PREFIX_VEX_0F44, |
981 | PREFIX_VEX_0F45, |
1086 | PREFIX_VEX_0F45, |
982 | PREFIX_VEX_0F46, |
1087 | PREFIX_VEX_0F46, |
983 | PREFIX_VEX_0F47, |
1088 | PREFIX_VEX_0F47, |
- | 1089 | PREFIX_VEX_0F4A, |
|
984 | PREFIX_VEX_0F4B, |
1090 | PREFIX_VEX_0F4B, |
985 | PREFIX_VEX_0F51, |
1091 | PREFIX_VEX_0F51, |
986 | PREFIX_VEX_0F52, |
1092 | PREFIX_VEX_0F52, |
987 | PREFIX_VEX_0F53, |
1093 | PREFIX_VEX_0F53, |
988 | PREFIX_VEX_0F58, |
1094 | PREFIX_VEX_0F58, |
Line 1031... | Line 1137... | ||
1031 | PREFIX_VEX_0F90, |
1137 | PREFIX_VEX_0F90, |
1032 | PREFIX_VEX_0F91, |
1138 | PREFIX_VEX_0F91, |
1033 | PREFIX_VEX_0F92, |
1139 | PREFIX_VEX_0F92, |
1034 | PREFIX_VEX_0F93, |
1140 | PREFIX_VEX_0F93, |
1035 | PREFIX_VEX_0F98, |
1141 | PREFIX_VEX_0F98, |
- | 1142 | PREFIX_VEX_0F99, |
|
1036 | PREFIX_VEX_0FC2, |
1143 | PREFIX_VEX_0FC2, |
1037 | PREFIX_VEX_0FC4, |
1144 | PREFIX_VEX_0FC4, |
1038 | PREFIX_VEX_0FC5, |
1145 | PREFIX_VEX_0FC5, |
1039 | PREFIX_VEX_0FD0, |
1146 | PREFIX_VEX_0FD0, |
1040 | PREFIX_VEX_0FD1, |
1147 | PREFIX_VEX_0FD1, |
Line 1219... | Line 1326... | ||
1219 | PREFIX_VEX_0F3A1D, |
1326 | PREFIX_VEX_0F3A1D, |
1220 | PREFIX_VEX_0F3A20, |
1327 | PREFIX_VEX_0F3A20, |
1221 | PREFIX_VEX_0F3A21, |
1328 | PREFIX_VEX_0F3A21, |
1222 | PREFIX_VEX_0F3A22, |
1329 | PREFIX_VEX_0F3A22, |
1223 | PREFIX_VEX_0F3A30, |
1330 | PREFIX_VEX_0F3A30, |
- | 1331 | PREFIX_VEX_0F3A31, |
|
1224 | PREFIX_VEX_0F3A32, |
1332 | PREFIX_VEX_0F3A32, |
- | 1333 | PREFIX_VEX_0F3A33, |
|
1225 | PREFIX_VEX_0F3A38, |
1334 | PREFIX_VEX_0F3A38, |
1226 | PREFIX_VEX_0F3A39, |
1335 | PREFIX_VEX_0F3A39, |
1227 | PREFIX_VEX_0F3A40, |
1336 | PREFIX_VEX_0F3A40, |
1228 | PREFIX_VEX_0F3A41, |
1337 | PREFIX_VEX_0F3A41, |
1229 | PREFIX_VEX_0F3A42, |
1338 | PREFIX_VEX_0F3A42, |
Line 1276... | Line 1385... | ||
1276 | PREFIX_EVEX_0F2C, |
1385 | PREFIX_EVEX_0F2C, |
1277 | PREFIX_EVEX_0F2D, |
1386 | PREFIX_EVEX_0F2D, |
1278 | PREFIX_EVEX_0F2E, |
1387 | PREFIX_EVEX_0F2E, |
1279 | PREFIX_EVEX_0F2F, |
1388 | PREFIX_EVEX_0F2F, |
1280 | PREFIX_EVEX_0F51, |
1389 | PREFIX_EVEX_0F51, |
- | 1390 | PREFIX_EVEX_0F54, |
|
- | 1391 | PREFIX_EVEX_0F55, |
|
- | 1392 | PREFIX_EVEX_0F56, |
|
- | 1393 | PREFIX_EVEX_0F57, |
|
1281 | PREFIX_EVEX_0F58, |
1394 | PREFIX_EVEX_0F58, |
1282 | PREFIX_EVEX_0F59, |
1395 | PREFIX_EVEX_0F59, |
1283 | PREFIX_EVEX_0F5A, |
1396 | PREFIX_EVEX_0F5A, |
1284 | PREFIX_EVEX_0F5B, |
1397 | PREFIX_EVEX_0F5B, |
1285 | PREFIX_EVEX_0F5C, |
1398 | PREFIX_EVEX_0F5C, |
1286 | PREFIX_EVEX_0F5D, |
1399 | PREFIX_EVEX_0F5D, |
1287 | PREFIX_EVEX_0F5E, |
1400 | PREFIX_EVEX_0F5E, |
1288 | PREFIX_EVEX_0F5F, |
1401 | PREFIX_EVEX_0F5F, |
- | 1402 | PREFIX_EVEX_0F60, |
|
- | 1403 | PREFIX_EVEX_0F61, |
|
1289 | PREFIX_EVEX_0F62, |
1404 | PREFIX_EVEX_0F62, |
- | 1405 | PREFIX_EVEX_0F63, |
|
- | 1406 | PREFIX_EVEX_0F64, |
|
- | 1407 | PREFIX_EVEX_0F65, |
|
1290 | PREFIX_EVEX_0F66, |
1408 | PREFIX_EVEX_0F66, |
- | 1409 | PREFIX_EVEX_0F67, |
|
- | 1410 | PREFIX_EVEX_0F68, |
|
- | 1411 | PREFIX_EVEX_0F69, |
|
1291 | PREFIX_EVEX_0F6A, |
1412 | PREFIX_EVEX_0F6A, |
- | 1413 | PREFIX_EVEX_0F6B, |
|
1292 | PREFIX_EVEX_0F6C, |
1414 | PREFIX_EVEX_0F6C, |
1293 | PREFIX_EVEX_0F6D, |
1415 | PREFIX_EVEX_0F6D, |
1294 | PREFIX_EVEX_0F6E, |
1416 | PREFIX_EVEX_0F6E, |
1295 | PREFIX_EVEX_0F6F, |
1417 | PREFIX_EVEX_0F6F, |
1296 | PREFIX_EVEX_0F70, |
1418 | PREFIX_EVEX_0F70, |
- | 1419 | PREFIX_EVEX_0F71_REG_2, |
|
- | 1420 | PREFIX_EVEX_0F71_REG_4, |
|
- | 1421 | PREFIX_EVEX_0F71_REG_6, |
|
1297 | PREFIX_EVEX_0F72_REG_0, |
1422 | PREFIX_EVEX_0F72_REG_0, |
1298 | PREFIX_EVEX_0F72_REG_1, |
1423 | PREFIX_EVEX_0F72_REG_1, |
1299 | PREFIX_EVEX_0F72_REG_2, |
1424 | PREFIX_EVEX_0F72_REG_2, |
1300 | PREFIX_EVEX_0F72_REG_4, |
1425 | PREFIX_EVEX_0F72_REG_4, |
1301 | PREFIX_EVEX_0F72_REG_6, |
1426 | PREFIX_EVEX_0F72_REG_6, |
1302 | PREFIX_EVEX_0F73_REG_2, |
1427 | PREFIX_EVEX_0F73_REG_2, |
- | 1428 | PREFIX_EVEX_0F73_REG_3, |
|
1303 | PREFIX_EVEX_0F73_REG_6, |
1429 | PREFIX_EVEX_0F73_REG_6, |
- | 1430 | PREFIX_EVEX_0F73_REG_7, |
|
- | 1431 | PREFIX_EVEX_0F74, |
|
- | 1432 | PREFIX_EVEX_0F75, |
|
1304 | PREFIX_EVEX_0F76, |
1433 | PREFIX_EVEX_0F76, |
1305 | PREFIX_EVEX_0F78, |
1434 | PREFIX_EVEX_0F78, |
1306 | PREFIX_EVEX_0F79, |
1435 | PREFIX_EVEX_0F79, |
1307 | PREFIX_EVEX_0F7A, |
1436 | PREFIX_EVEX_0F7A, |
1308 | PREFIX_EVEX_0F7B, |
1437 | PREFIX_EVEX_0F7B, |
1309 | PREFIX_EVEX_0F7E, |
1438 | PREFIX_EVEX_0F7E, |
1310 | PREFIX_EVEX_0F7F, |
1439 | PREFIX_EVEX_0F7F, |
1311 | PREFIX_EVEX_0FC2, |
1440 | PREFIX_EVEX_0FC2, |
- | 1441 | PREFIX_EVEX_0FC4, |
|
- | 1442 | PREFIX_EVEX_0FC5, |
|
1312 | PREFIX_EVEX_0FC6, |
1443 | PREFIX_EVEX_0FC6, |
- | 1444 | PREFIX_EVEX_0FD1, |
|
1313 | PREFIX_EVEX_0FD2, |
1445 | PREFIX_EVEX_0FD2, |
1314 | PREFIX_EVEX_0FD3, |
1446 | PREFIX_EVEX_0FD3, |
1315 | PREFIX_EVEX_0FD4, |
1447 | PREFIX_EVEX_0FD4, |
- | 1448 | PREFIX_EVEX_0FD5, |
|
1316 | PREFIX_EVEX_0FD6, |
1449 | PREFIX_EVEX_0FD6, |
- | 1450 | PREFIX_EVEX_0FD8, |
|
- | 1451 | PREFIX_EVEX_0FD9, |
|
- | 1452 | PREFIX_EVEX_0FDA, |
|
1317 | PREFIX_EVEX_0FDB, |
1453 | PREFIX_EVEX_0FDB, |
- | 1454 | PREFIX_EVEX_0FDC, |
|
- | 1455 | PREFIX_EVEX_0FDD, |
|
- | 1456 | PREFIX_EVEX_0FDE, |
|
1318 | PREFIX_EVEX_0FDF, |
1457 | PREFIX_EVEX_0FDF, |
- | 1458 | PREFIX_EVEX_0FE0, |
|
- | 1459 | PREFIX_EVEX_0FE1, |
|
1319 | PREFIX_EVEX_0FE2, |
1460 | PREFIX_EVEX_0FE2, |
- | 1461 | PREFIX_EVEX_0FE3, |
|
- | 1462 | PREFIX_EVEX_0FE4, |
|
- | 1463 | PREFIX_EVEX_0FE5, |
|
1320 | PREFIX_EVEX_0FE6, |
1464 | PREFIX_EVEX_0FE6, |
1321 | PREFIX_EVEX_0FE7, |
1465 | PREFIX_EVEX_0FE7, |
- | 1466 | PREFIX_EVEX_0FE8, |
|
- | 1467 | PREFIX_EVEX_0FE9, |
|
- | 1468 | PREFIX_EVEX_0FEA, |
|
1322 | PREFIX_EVEX_0FEB, |
1469 | PREFIX_EVEX_0FEB, |
- | 1470 | PREFIX_EVEX_0FEC, |
|
- | 1471 | PREFIX_EVEX_0FED, |
|
- | 1472 | PREFIX_EVEX_0FEE, |
|
1323 | PREFIX_EVEX_0FEF, |
1473 | PREFIX_EVEX_0FEF, |
- | 1474 | PREFIX_EVEX_0FF1, |
|
1324 | PREFIX_EVEX_0FF2, |
1475 | PREFIX_EVEX_0FF2, |
1325 | PREFIX_EVEX_0FF3, |
1476 | PREFIX_EVEX_0FF3, |
1326 | PREFIX_EVEX_0FF4, |
1477 | PREFIX_EVEX_0FF4, |
- | 1478 | PREFIX_EVEX_0FF5, |
|
- | 1479 | PREFIX_EVEX_0FF6, |
|
- | 1480 | PREFIX_EVEX_0FF8, |
|
- | 1481 | PREFIX_EVEX_0FF9, |
|
1327 | PREFIX_EVEX_0FFA, |
1482 | PREFIX_EVEX_0FFA, |
1328 | PREFIX_EVEX_0FFB, |
1483 | PREFIX_EVEX_0FFB, |
- | 1484 | PREFIX_EVEX_0FFC, |
|
- | 1485 | PREFIX_EVEX_0FFD, |
|
1329 | PREFIX_EVEX_0FFE, |
1486 | PREFIX_EVEX_0FFE, |
- | 1487 | PREFIX_EVEX_0F3800, |
|
- | 1488 | PREFIX_EVEX_0F3804, |
|
- | 1489 | PREFIX_EVEX_0F380B, |
|
1330 | PREFIX_EVEX_0F380C, |
1490 | PREFIX_EVEX_0F380C, |
1331 | PREFIX_EVEX_0F380D, |
1491 | PREFIX_EVEX_0F380D, |
- | 1492 | PREFIX_EVEX_0F3810, |
|
1332 | PREFIX_EVEX_0F3811, |
1493 | PREFIX_EVEX_0F3811, |
1333 | PREFIX_EVEX_0F3812, |
1494 | PREFIX_EVEX_0F3812, |
1334 | PREFIX_EVEX_0F3813, |
1495 | PREFIX_EVEX_0F3813, |
1335 | PREFIX_EVEX_0F3814, |
1496 | PREFIX_EVEX_0F3814, |
1336 | PREFIX_EVEX_0F3815, |
1497 | PREFIX_EVEX_0F3815, |
1337 | PREFIX_EVEX_0F3816, |
1498 | PREFIX_EVEX_0F3816, |
1338 | PREFIX_EVEX_0F3818, |
1499 | PREFIX_EVEX_0F3818, |
1339 | PREFIX_EVEX_0F3819, |
1500 | PREFIX_EVEX_0F3819, |
1340 | PREFIX_EVEX_0F381A, |
1501 | PREFIX_EVEX_0F381A, |
1341 | PREFIX_EVEX_0F381B, |
1502 | PREFIX_EVEX_0F381B, |
- | 1503 | PREFIX_EVEX_0F381C, |
|
- | 1504 | PREFIX_EVEX_0F381D, |
|
1342 | PREFIX_EVEX_0F381E, |
1505 | PREFIX_EVEX_0F381E, |
1343 | PREFIX_EVEX_0F381F, |
1506 | PREFIX_EVEX_0F381F, |
- | 1507 | PREFIX_EVEX_0F3820, |
|
1344 | PREFIX_EVEX_0F3821, |
1508 | PREFIX_EVEX_0F3821, |
1345 | PREFIX_EVEX_0F3822, |
1509 | PREFIX_EVEX_0F3822, |
1346 | PREFIX_EVEX_0F3823, |
1510 | PREFIX_EVEX_0F3823, |
1347 | PREFIX_EVEX_0F3824, |
1511 | PREFIX_EVEX_0F3824, |
1348 | PREFIX_EVEX_0F3825, |
1512 | PREFIX_EVEX_0F3825, |
- | 1513 | PREFIX_EVEX_0F3826, |
|
1349 | PREFIX_EVEX_0F3827, |
1514 | PREFIX_EVEX_0F3827, |
1350 | PREFIX_EVEX_0F3828, |
1515 | PREFIX_EVEX_0F3828, |
1351 | PREFIX_EVEX_0F3829, |
1516 | PREFIX_EVEX_0F3829, |
1352 | PREFIX_EVEX_0F382A, |
1517 | PREFIX_EVEX_0F382A, |
- | 1518 | PREFIX_EVEX_0F382B, |
|
1353 | PREFIX_EVEX_0F382C, |
1519 | PREFIX_EVEX_0F382C, |
1354 | PREFIX_EVEX_0F382D, |
1520 | PREFIX_EVEX_0F382D, |
- | 1521 | PREFIX_EVEX_0F3830, |
|
1355 | PREFIX_EVEX_0F3831, |
1522 | PREFIX_EVEX_0F3831, |
1356 | PREFIX_EVEX_0F3832, |
1523 | PREFIX_EVEX_0F3832, |
1357 | PREFIX_EVEX_0F3833, |
1524 | PREFIX_EVEX_0F3833, |
1358 | PREFIX_EVEX_0F3834, |
1525 | PREFIX_EVEX_0F3834, |
1359 | PREFIX_EVEX_0F3835, |
1526 | PREFIX_EVEX_0F3835, |
1360 | PREFIX_EVEX_0F3836, |
1527 | PREFIX_EVEX_0F3836, |
1361 | PREFIX_EVEX_0F3837, |
1528 | PREFIX_EVEX_0F3837, |
- | 1529 | PREFIX_EVEX_0F3838, |
|
1362 | PREFIX_EVEX_0F3839, |
1530 | PREFIX_EVEX_0F3839, |
1363 | PREFIX_EVEX_0F383A, |
1531 | PREFIX_EVEX_0F383A, |
1364 | PREFIX_EVEX_0F383B, |
1532 | PREFIX_EVEX_0F383B, |
- | 1533 | PREFIX_EVEX_0F383C, |
|
1365 | PREFIX_EVEX_0F383D, |
1534 | PREFIX_EVEX_0F383D, |
- | 1535 | PREFIX_EVEX_0F383E, |
|
1366 | PREFIX_EVEX_0F383F, |
1536 | PREFIX_EVEX_0F383F, |
1367 | PREFIX_EVEX_0F3840, |
1537 | PREFIX_EVEX_0F3840, |
1368 | PREFIX_EVEX_0F3842, |
1538 | PREFIX_EVEX_0F3842, |
1369 | PREFIX_EVEX_0F3843, |
1539 | PREFIX_EVEX_0F3843, |
1370 | PREFIX_EVEX_0F3844, |
1540 | PREFIX_EVEX_0F3844, |
Line 1379... | Line 1549... | ||
1379 | PREFIX_EVEX_0F3859, |
1549 | PREFIX_EVEX_0F3859, |
1380 | PREFIX_EVEX_0F385A, |
1550 | PREFIX_EVEX_0F385A, |
1381 | PREFIX_EVEX_0F385B, |
1551 | PREFIX_EVEX_0F385B, |
1382 | PREFIX_EVEX_0F3864, |
1552 | PREFIX_EVEX_0F3864, |
1383 | PREFIX_EVEX_0F3865, |
1553 | PREFIX_EVEX_0F3865, |
- | 1554 | PREFIX_EVEX_0F3866, |
|
- | 1555 | PREFIX_EVEX_0F3875, |
|
1384 | PREFIX_EVEX_0F3876, |
1556 | PREFIX_EVEX_0F3876, |
1385 | PREFIX_EVEX_0F3877, |
1557 | PREFIX_EVEX_0F3877, |
- | 1558 | PREFIX_EVEX_0F3878, |
|
- | 1559 | PREFIX_EVEX_0F3879, |
|
- | 1560 | PREFIX_EVEX_0F387A, |
|
- | 1561 | PREFIX_EVEX_0F387B, |
|
1386 | PREFIX_EVEX_0F387C, |
1562 | PREFIX_EVEX_0F387C, |
- | 1563 | PREFIX_EVEX_0F387D, |
|
1387 | PREFIX_EVEX_0F387E, |
1564 | PREFIX_EVEX_0F387E, |
1388 | PREFIX_EVEX_0F387F, |
1565 | PREFIX_EVEX_0F387F, |
- | 1566 | PREFIX_EVEX_0F3883, |
|
1389 | PREFIX_EVEX_0F3888, |
1567 | PREFIX_EVEX_0F3888, |
1390 | PREFIX_EVEX_0F3889, |
1568 | PREFIX_EVEX_0F3889, |
1391 | PREFIX_EVEX_0F388A, |
1569 | PREFIX_EVEX_0F388A, |
1392 | PREFIX_EVEX_0F388B, |
1570 | PREFIX_EVEX_0F388B, |
- | 1571 | PREFIX_EVEX_0F388D, |
|
1393 | PREFIX_EVEX_0F3890, |
1572 | PREFIX_EVEX_0F3890, |
1394 | PREFIX_EVEX_0F3891, |
1573 | PREFIX_EVEX_0F3891, |
1395 | PREFIX_EVEX_0F3892, |
1574 | PREFIX_EVEX_0F3892, |
1396 | PREFIX_EVEX_0F3893, |
1575 | PREFIX_EVEX_0F3893, |
1397 | PREFIX_EVEX_0F3896, |
1576 | PREFIX_EVEX_0F3896, |
Line 1416... | Line 1595... | ||
1416 | PREFIX_EVEX_0F38AB, |
1595 | PREFIX_EVEX_0F38AB, |
1417 | PREFIX_EVEX_0F38AC, |
1596 | PREFIX_EVEX_0F38AC, |
1418 | PREFIX_EVEX_0F38AD, |
1597 | PREFIX_EVEX_0F38AD, |
1419 | PREFIX_EVEX_0F38AE, |
1598 | PREFIX_EVEX_0F38AE, |
1420 | PREFIX_EVEX_0F38AF, |
1599 | PREFIX_EVEX_0F38AF, |
- | 1600 | PREFIX_EVEX_0F38B4, |
|
- | 1601 | PREFIX_EVEX_0F38B5, |
|
1421 | PREFIX_EVEX_0F38B6, |
1602 | PREFIX_EVEX_0F38B6, |
1422 | PREFIX_EVEX_0F38B7, |
1603 | PREFIX_EVEX_0F38B7, |
1423 | PREFIX_EVEX_0F38B8, |
1604 | PREFIX_EVEX_0F38B8, |
1424 | PREFIX_EVEX_0F38B9, |
1605 | PREFIX_EVEX_0F38B9, |
1425 | PREFIX_EVEX_0F38BA, |
1606 | PREFIX_EVEX_0F38BA, |
Line 1450... | Line 1631... | ||
1450 | PREFIX_EVEX_0F3A05, |
1631 | PREFIX_EVEX_0F3A05, |
1451 | PREFIX_EVEX_0F3A08, |
1632 | PREFIX_EVEX_0F3A08, |
1452 | PREFIX_EVEX_0F3A09, |
1633 | PREFIX_EVEX_0F3A09, |
1453 | PREFIX_EVEX_0F3A0A, |
1634 | PREFIX_EVEX_0F3A0A, |
1454 | PREFIX_EVEX_0F3A0B, |
1635 | PREFIX_EVEX_0F3A0B, |
- | 1636 | PREFIX_EVEX_0F3A0F, |
|
- | 1637 | PREFIX_EVEX_0F3A14, |
|
- | 1638 | PREFIX_EVEX_0F3A15, |
|
- | 1639 | PREFIX_EVEX_0F3A16, |
|
1455 | PREFIX_EVEX_0F3A17, |
1640 | PREFIX_EVEX_0F3A17, |
1456 | PREFIX_EVEX_0F3A18, |
1641 | PREFIX_EVEX_0F3A18, |
1457 | PREFIX_EVEX_0F3A19, |
1642 | PREFIX_EVEX_0F3A19, |
1458 | PREFIX_EVEX_0F3A1A, |
1643 | PREFIX_EVEX_0F3A1A, |
1459 | PREFIX_EVEX_0F3A1B, |
1644 | PREFIX_EVEX_0F3A1B, |
1460 | PREFIX_EVEX_0F3A1D, |
1645 | PREFIX_EVEX_0F3A1D, |
1461 | PREFIX_EVEX_0F3A1E, |
1646 | PREFIX_EVEX_0F3A1E, |
1462 | PREFIX_EVEX_0F3A1F, |
1647 | PREFIX_EVEX_0F3A1F, |
- | 1648 | PREFIX_EVEX_0F3A20, |
|
1463 | PREFIX_EVEX_0F3A21, |
1649 | PREFIX_EVEX_0F3A21, |
- | 1650 | PREFIX_EVEX_0F3A22, |
|
1464 | PREFIX_EVEX_0F3A23, |
1651 | PREFIX_EVEX_0F3A23, |
1465 | PREFIX_EVEX_0F3A25, |
1652 | PREFIX_EVEX_0F3A25, |
1466 | PREFIX_EVEX_0F3A26, |
1653 | PREFIX_EVEX_0F3A26, |
1467 | PREFIX_EVEX_0F3A27, |
1654 | PREFIX_EVEX_0F3A27, |
1468 | PREFIX_EVEX_0F3A38, |
1655 | PREFIX_EVEX_0F3A38, |
1469 | PREFIX_EVEX_0F3A39, |
1656 | PREFIX_EVEX_0F3A39, |
1470 | PREFIX_EVEX_0F3A3A, |
1657 | PREFIX_EVEX_0F3A3A, |
1471 | PREFIX_EVEX_0F3A3B, |
1658 | PREFIX_EVEX_0F3A3B, |
- | 1659 | PREFIX_EVEX_0F3A3E, |
|
- | 1660 | PREFIX_EVEX_0F3A3F, |
|
- | 1661 | PREFIX_EVEX_0F3A42, |
|
1472 | PREFIX_EVEX_0F3A43, |
1662 | PREFIX_EVEX_0F3A43, |
- | 1663 | PREFIX_EVEX_0F3A50, |
|
- | 1664 | PREFIX_EVEX_0F3A51, |
|
1473 | PREFIX_EVEX_0F3A54, |
1665 | PREFIX_EVEX_0F3A54, |
1474 | PREFIX_EVEX_0F3A55, |
1666 | PREFIX_EVEX_0F3A55, |
- | 1667 | PREFIX_EVEX_0F3A56, |
|
- | 1668 | PREFIX_EVEX_0F3A57, |
|
- | 1669 | PREFIX_EVEX_0F3A66, |
|
- | 1670 | PREFIX_EVEX_0F3A67 |
|
1475 | }; |
1671 | }; |
Line 1476... | Line 1672... | ||
1476 | 1672 | ||
1477 | enum |
1673 | enum |
1478 | { |
1674 | { |
Line 1497... | Line 1693... | ||
1497 | X86_64_C4, |
1693 | X86_64_C4, |
1498 | X86_64_C5, |
1694 | X86_64_C5, |
1499 | X86_64_CE, |
1695 | X86_64_CE, |
1500 | X86_64_D4, |
1696 | X86_64_D4, |
1501 | X86_64_D5, |
1697 | X86_64_D5, |
- | 1698 | X86_64_E8, |
|
- | 1699 | X86_64_E9, |
|
1502 | X86_64_EA, |
1700 | X86_64_EA, |
1503 | X86_64_0F01_REG_0, |
1701 | X86_64_0F01_REG_0, |
1504 | X86_64_0F01_REG_1, |
1702 | X86_64_0F01_REG_1, |
1505 | X86_64_0F01_REG_2, |
1703 | X86_64_0F01_REG_2, |
1506 | X86_64_0F01_REG_3 |
1704 | X86_64_0F01_REG_3 |
Line 1557... | Line 1755... | ||
1557 | VEX_LEN_0F2E_P_0, |
1755 | VEX_LEN_0F2E_P_0, |
1558 | VEX_LEN_0F2E_P_2, |
1756 | VEX_LEN_0F2E_P_2, |
1559 | VEX_LEN_0F2F_P_0, |
1757 | VEX_LEN_0F2F_P_0, |
1560 | VEX_LEN_0F2F_P_2, |
1758 | VEX_LEN_0F2F_P_2, |
1561 | VEX_LEN_0F41_P_0, |
1759 | VEX_LEN_0F41_P_0, |
- | 1760 | VEX_LEN_0F41_P_2, |
|
1562 | VEX_LEN_0F42_P_0, |
1761 | VEX_LEN_0F42_P_0, |
- | 1762 | VEX_LEN_0F42_P_2, |
|
1563 | VEX_LEN_0F44_P_0, |
1763 | VEX_LEN_0F44_P_0, |
- | 1764 | VEX_LEN_0F44_P_2, |
|
1564 | VEX_LEN_0F45_P_0, |
1765 | VEX_LEN_0F45_P_0, |
- | 1766 | VEX_LEN_0F45_P_2, |
|
1565 | VEX_LEN_0F46_P_0, |
1767 | VEX_LEN_0F46_P_0, |
- | 1768 | VEX_LEN_0F46_P_2, |
|
1566 | VEX_LEN_0F47_P_0, |
1769 | VEX_LEN_0F47_P_0, |
- | 1770 | VEX_LEN_0F47_P_2, |
|
- | 1771 | VEX_LEN_0F4A_P_0, |
|
- | 1772 | VEX_LEN_0F4A_P_2, |
|
- | 1773 | VEX_LEN_0F4B_P_0, |
|
1567 | VEX_LEN_0F4B_P_2, |
1774 | VEX_LEN_0F4B_P_2, |
1568 | VEX_LEN_0F51_P_1, |
1775 | VEX_LEN_0F51_P_1, |
1569 | VEX_LEN_0F51_P_3, |
1776 | VEX_LEN_0F51_P_3, |
1570 | VEX_LEN_0F52_P_1, |
1777 | VEX_LEN_0F52_P_1, |
1571 | VEX_LEN_0F53_P_1, |
1778 | VEX_LEN_0F53_P_1, |
Line 1585... | Line 1792... | ||
1585 | VEX_LEN_0F5F_P_3, |
1792 | VEX_LEN_0F5F_P_3, |
1586 | VEX_LEN_0F6E_P_2, |
1793 | VEX_LEN_0F6E_P_2, |
1587 | VEX_LEN_0F7E_P_1, |
1794 | VEX_LEN_0F7E_P_1, |
1588 | VEX_LEN_0F7E_P_2, |
1795 | VEX_LEN_0F7E_P_2, |
1589 | VEX_LEN_0F90_P_0, |
1796 | VEX_LEN_0F90_P_0, |
- | 1797 | VEX_LEN_0F90_P_2, |
|
1590 | VEX_LEN_0F91_P_0, |
1798 | VEX_LEN_0F91_P_0, |
- | 1799 | VEX_LEN_0F91_P_2, |
|
1591 | VEX_LEN_0F92_P_0, |
1800 | VEX_LEN_0F92_P_0, |
- | 1801 | VEX_LEN_0F92_P_2, |
|
- | 1802 | VEX_LEN_0F92_P_3, |
|
1592 | VEX_LEN_0F93_P_0, |
1803 | VEX_LEN_0F93_P_0, |
- | 1804 | VEX_LEN_0F93_P_2, |
|
- | 1805 | VEX_LEN_0F93_P_3, |
|
1593 | VEX_LEN_0F98_P_0, |
1806 | VEX_LEN_0F98_P_0, |
- | 1807 | VEX_LEN_0F98_P_2, |
|
- | 1808 | VEX_LEN_0F99_P_0, |
|
- | 1809 | VEX_LEN_0F99_P_2, |
|
1594 | VEX_LEN_0FAE_R_2_M_0, |
1810 | VEX_LEN_0FAE_R_2_M_0, |
1595 | VEX_LEN_0FAE_R_3_M_0, |
1811 | VEX_LEN_0FAE_R_3_M_0, |
1596 | VEX_LEN_0FC2_P_1, |
1812 | VEX_LEN_0FC2_P_1, |
1597 | VEX_LEN_0FC2_P_3, |
1813 | VEX_LEN_0FC2_P_3, |
1598 | VEX_LEN_0FC4_P_2, |
1814 | VEX_LEN_0FC4_P_2, |
Line 1635... | Line 1851... | ||
1635 | VEX_LEN_0F3A19_P_2, |
1851 | VEX_LEN_0F3A19_P_2, |
1636 | VEX_LEN_0F3A20_P_2, |
1852 | VEX_LEN_0F3A20_P_2, |
1637 | VEX_LEN_0F3A21_P_2, |
1853 | VEX_LEN_0F3A21_P_2, |
1638 | VEX_LEN_0F3A22_P_2, |
1854 | VEX_LEN_0F3A22_P_2, |
1639 | VEX_LEN_0F3A30_P_2, |
1855 | VEX_LEN_0F3A30_P_2, |
- | 1856 | VEX_LEN_0F3A31_P_2, |
|
1640 | VEX_LEN_0F3A32_P_2, |
1857 | VEX_LEN_0F3A32_P_2, |
- | 1858 | VEX_LEN_0F3A33_P_2, |
|
1641 | VEX_LEN_0F3A38_P_2, |
1859 | VEX_LEN_0F3A38_P_2, |
1642 | VEX_LEN_0F3A39_P_2, |
1860 | VEX_LEN_0F3A39_P_2, |
1643 | VEX_LEN_0F3A41_P_2, |
1861 | VEX_LEN_0F3A41_P_2, |
1644 | VEX_LEN_0F3A44_P_2, |
1862 | VEX_LEN_0F3A44_P_2, |
1645 | VEX_LEN_0F3A46_P_2, |
1863 | VEX_LEN_0F3A46_P_2, |
Line 1698... | Line 1916... | ||
1698 | VEX_W_0F2E_P_0, |
1916 | VEX_W_0F2E_P_0, |
1699 | VEX_W_0F2E_P_2, |
1917 | VEX_W_0F2E_P_2, |
1700 | VEX_W_0F2F_P_0, |
1918 | VEX_W_0F2F_P_0, |
1701 | VEX_W_0F2F_P_2, |
1919 | VEX_W_0F2F_P_2, |
1702 | VEX_W_0F41_P_0_LEN_1, |
1920 | VEX_W_0F41_P_0_LEN_1, |
- | 1921 | VEX_W_0F41_P_2_LEN_1, |
|
1703 | VEX_W_0F42_P_0_LEN_1, |
1922 | VEX_W_0F42_P_0_LEN_1, |
- | 1923 | VEX_W_0F42_P_2_LEN_1, |
|
1704 | VEX_W_0F44_P_0_LEN_0, |
1924 | VEX_W_0F44_P_0_LEN_0, |
- | 1925 | VEX_W_0F44_P_2_LEN_0, |
|
1705 | VEX_W_0F45_P_0_LEN_1, |
1926 | VEX_W_0F45_P_0_LEN_1, |
- | 1927 | VEX_W_0F45_P_2_LEN_1, |
|
1706 | VEX_W_0F46_P_0_LEN_1, |
1928 | VEX_W_0F46_P_0_LEN_1, |
- | 1929 | VEX_W_0F46_P_2_LEN_1, |
|
1707 | VEX_W_0F47_P_0_LEN_1, |
1930 | VEX_W_0F47_P_0_LEN_1, |
- | 1931 | VEX_W_0F47_P_2_LEN_1, |
|
- | 1932 | VEX_W_0F4A_P_0_LEN_1, |
|
- | 1933 | VEX_W_0F4A_P_2_LEN_1, |
|
- | 1934 | VEX_W_0F4B_P_0_LEN_1, |
|
1708 | VEX_W_0F4B_P_2_LEN_1, |
1935 | VEX_W_0F4B_P_2_LEN_1, |
1709 | VEX_W_0F50_M_0, |
1936 | VEX_W_0F50_M_0, |
1710 | VEX_W_0F51_P_0, |
1937 | VEX_W_0F51_P_0, |
1711 | VEX_W_0F51_P_1, |
1938 | VEX_W_0F51_P_1, |
1712 | VEX_W_0F51_P_2, |
1939 | VEX_W_0F51_P_2, |
Line 1784... | Line 2011... | ||
1784 | VEX_W_0F7D_P_3, |
2011 | VEX_W_0F7D_P_3, |
1785 | VEX_W_0F7E_P_1, |
2012 | VEX_W_0F7E_P_1, |
1786 | VEX_W_0F7F_P_1, |
2013 | VEX_W_0F7F_P_1, |
1787 | VEX_W_0F7F_P_2, |
2014 | VEX_W_0F7F_P_2, |
1788 | VEX_W_0F90_P_0_LEN_0, |
2015 | VEX_W_0F90_P_0_LEN_0, |
- | 2016 | VEX_W_0F90_P_2_LEN_0, |
|
1789 | VEX_W_0F91_P_0_LEN_0, |
2017 | VEX_W_0F91_P_0_LEN_0, |
- | 2018 | VEX_W_0F91_P_2_LEN_0, |
|
1790 | VEX_W_0F92_P_0_LEN_0, |
2019 | VEX_W_0F92_P_0_LEN_0, |
- | 2020 | VEX_W_0F92_P_2_LEN_0, |
|
- | 2021 | VEX_W_0F92_P_3_LEN_0, |
|
1791 | VEX_W_0F93_P_0_LEN_0, |
2022 | VEX_W_0F93_P_0_LEN_0, |
- | 2023 | VEX_W_0F93_P_2_LEN_0, |
|
- | 2024 | VEX_W_0F93_P_3_LEN_0, |
|
1792 | VEX_W_0F98_P_0_LEN_0, |
2025 | VEX_W_0F98_P_0_LEN_0, |
- | 2026 | VEX_W_0F98_P_2_LEN_0, |
|
- | 2027 | VEX_W_0F99_P_0_LEN_0, |
|
- | 2028 | VEX_W_0F99_P_2_LEN_0, |
|
1793 | VEX_W_0FAE_R_2_M_0, |
2029 | VEX_W_0FAE_R_2_M_0, |
1794 | VEX_W_0FAE_R_3_M_0, |
2030 | VEX_W_0FAE_R_3_M_0, |
1795 | VEX_W_0FC2_P_0, |
2031 | VEX_W_0FC2_P_0, |
1796 | VEX_W_0FC2_P_1, |
2032 | VEX_W_0FC2_P_1, |
1797 | VEX_W_0FC2_P_2, |
2033 | VEX_W_0FC2_P_2, |
Line 1934... | Line 2170... | ||
1934 | VEX_W_0F3A18_P_2, |
2170 | VEX_W_0F3A18_P_2, |
1935 | VEX_W_0F3A19_P_2, |
2171 | VEX_W_0F3A19_P_2, |
1936 | VEX_W_0F3A20_P_2, |
2172 | VEX_W_0F3A20_P_2, |
1937 | VEX_W_0F3A21_P_2, |
2173 | VEX_W_0F3A21_P_2, |
1938 | VEX_W_0F3A30_P_2_LEN_0, |
2174 | VEX_W_0F3A30_P_2_LEN_0, |
- | 2175 | VEX_W_0F3A31_P_2_LEN_0, |
|
1939 | VEX_W_0F3A32_P_2_LEN_0, |
2176 | VEX_W_0F3A32_P_2_LEN_0, |
- | 2177 | VEX_W_0F3A33_P_2_LEN_0, |
|
1940 | VEX_W_0F3A38_P_2, |
2178 | VEX_W_0F3A38_P_2, |
1941 | VEX_W_0F3A39_P_2, |
2179 | VEX_W_0F3A39_P_2, |
1942 | VEX_W_0F3A40_P_2, |
2180 | VEX_W_0F3A40_P_2, |
1943 | VEX_W_0F3A41_P_2, |
2181 | VEX_W_0F3A41_P_2, |
1944 | VEX_W_0F3A42_P_2, |
2182 | VEX_W_0F3A42_P_2, |
Line 1998... | Line 2236... | ||
1998 | EVEX_W_0F2F_P_2, |
2236 | EVEX_W_0F2F_P_2, |
1999 | EVEX_W_0F51_P_0, |
2237 | EVEX_W_0F51_P_0, |
2000 | EVEX_W_0F51_P_1, |
2238 | EVEX_W_0F51_P_1, |
2001 | EVEX_W_0F51_P_2, |
2239 | EVEX_W_0F51_P_2, |
2002 | EVEX_W_0F51_P_3, |
2240 | EVEX_W_0F51_P_3, |
- | 2241 | EVEX_W_0F54_P_0, |
|
- | 2242 | EVEX_W_0F54_P_2, |
|
- | 2243 | EVEX_W_0F55_P_0, |
|
- | 2244 | EVEX_W_0F55_P_2, |
|
- | 2245 | EVEX_W_0F56_P_0, |
|
- | 2246 | EVEX_W_0F56_P_2, |
|
- | 2247 | EVEX_W_0F57_P_0, |
|
- | 2248 | EVEX_W_0F57_P_2, |
|
2003 | EVEX_W_0F58_P_0, |
2249 | EVEX_W_0F58_P_0, |
2004 | EVEX_W_0F58_P_1, |
2250 | EVEX_W_0F58_P_1, |
2005 | EVEX_W_0F58_P_2, |
2251 | EVEX_W_0F58_P_2, |
2006 | EVEX_W_0F58_P_3, |
2252 | EVEX_W_0F58_P_3, |
2007 | EVEX_W_0F59_P_0, |
2253 | EVEX_W_0F59_P_0, |
Line 2032... | Line 2278... | ||
2032 | EVEX_W_0F5F_P_2, |
2278 | EVEX_W_0F5F_P_2, |
2033 | EVEX_W_0F5F_P_3, |
2279 | EVEX_W_0F5F_P_3, |
2034 | EVEX_W_0F62_P_2, |
2280 | EVEX_W_0F62_P_2, |
2035 | EVEX_W_0F66_P_2, |
2281 | EVEX_W_0F66_P_2, |
2036 | EVEX_W_0F6A_P_2, |
2282 | EVEX_W_0F6A_P_2, |
- | 2283 | EVEX_W_0F6B_P_2, |
|
2037 | EVEX_W_0F6C_P_2, |
2284 | EVEX_W_0F6C_P_2, |
2038 | EVEX_W_0F6D_P_2, |
2285 | EVEX_W_0F6D_P_2, |
2039 | EVEX_W_0F6E_P_2, |
2286 | EVEX_W_0F6E_P_2, |
2040 | EVEX_W_0F6F_P_1, |
2287 | EVEX_W_0F6F_P_1, |
2041 | EVEX_W_0F6F_P_2, |
2288 | EVEX_W_0F6F_P_2, |
- | 2289 | EVEX_W_0F6F_P_3, |
|
2042 | EVEX_W_0F70_P_2, |
2290 | EVEX_W_0F70_P_2, |
2043 | EVEX_W_0F72_R_2_P_2, |
2291 | EVEX_W_0F72_R_2_P_2, |
2044 | EVEX_W_0F72_R_6_P_2, |
2292 | EVEX_W_0F72_R_6_P_2, |
2045 | EVEX_W_0F73_R_2_P_2, |
2293 | EVEX_W_0F73_R_2_P_2, |
2046 | EVEX_W_0F73_R_6_P_2, |
2294 | EVEX_W_0F73_R_6_P_2, |
2047 | EVEX_W_0F76_P_2, |
2295 | EVEX_W_0F76_P_2, |
2048 | EVEX_W_0F78_P_0, |
2296 | EVEX_W_0F78_P_0, |
- | 2297 | EVEX_W_0F78_P_2, |
|
2049 | EVEX_W_0F79_P_0, |
2298 | EVEX_W_0F79_P_0, |
- | 2299 | EVEX_W_0F79_P_2, |
|
2050 | EVEX_W_0F7A_P_1, |
2300 | EVEX_W_0F7A_P_1, |
- | 2301 | EVEX_W_0F7A_P_2, |
|
2051 | EVEX_W_0F7A_P_3, |
2302 | EVEX_W_0F7A_P_3, |
2052 | EVEX_W_0F7B_P_1, |
2303 | EVEX_W_0F7B_P_1, |
- | 2304 | EVEX_W_0F7B_P_2, |
|
2053 | EVEX_W_0F7B_P_3, |
2305 | EVEX_W_0F7B_P_3, |
2054 | EVEX_W_0F7E_P_1, |
2306 | EVEX_W_0F7E_P_1, |
2055 | EVEX_W_0F7E_P_2, |
2307 | EVEX_W_0F7E_P_2, |
2056 | EVEX_W_0F7F_P_1, |
2308 | EVEX_W_0F7F_P_1, |
2057 | EVEX_W_0F7F_P_2, |
2309 | EVEX_W_0F7F_P_2, |
- | 2310 | EVEX_W_0F7F_P_3, |
|
2058 | EVEX_W_0FC2_P_0, |
2311 | EVEX_W_0FC2_P_0, |
2059 | EVEX_W_0FC2_P_1, |
2312 | EVEX_W_0FC2_P_1, |
2060 | EVEX_W_0FC2_P_2, |
2313 | EVEX_W_0FC2_P_2, |
2061 | EVEX_W_0FC2_P_3, |
2314 | EVEX_W_0FC2_P_3, |
2062 | EVEX_W_0FC6_P_0, |
2315 | EVEX_W_0FC6_P_0, |
Line 2075... | Line 2328... | ||
2075 | EVEX_W_0FFA_P_2, |
2328 | EVEX_W_0FFA_P_2, |
2076 | EVEX_W_0FFB_P_2, |
2329 | EVEX_W_0FFB_P_2, |
2077 | EVEX_W_0FFE_P_2, |
2330 | EVEX_W_0FFE_P_2, |
2078 | EVEX_W_0F380C_P_2, |
2331 | EVEX_W_0F380C_P_2, |
2079 | EVEX_W_0F380D_P_2, |
2332 | EVEX_W_0F380D_P_2, |
- | 2333 | EVEX_W_0F3810_P_1, |
|
- | 2334 | EVEX_W_0F3810_P_2, |
|
2080 | EVEX_W_0F3811_P_1, |
2335 | EVEX_W_0F3811_P_1, |
- | 2336 | EVEX_W_0F3811_P_2, |
|
2081 | EVEX_W_0F3812_P_1, |
2337 | EVEX_W_0F3812_P_1, |
- | 2338 | EVEX_W_0F3812_P_2, |
|
2082 | EVEX_W_0F3813_P_1, |
2339 | EVEX_W_0F3813_P_1, |
2083 | EVEX_W_0F3813_P_2, |
2340 | EVEX_W_0F3813_P_2, |
2084 | EVEX_W_0F3814_P_1, |
2341 | EVEX_W_0F3814_P_1, |
2085 | EVEX_W_0F3815_P_1, |
2342 | EVEX_W_0F3815_P_1, |
2086 | EVEX_W_0F3818_P_2, |
2343 | EVEX_W_0F3818_P_2, |
2087 | EVEX_W_0F3819_P_2, |
2344 | EVEX_W_0F3819_P_2, |
2088 | EVEX_W_0F381A_P_2, |
2345 | EVEX_W_0F381A_P_2, |
2089 | EVEX_W_0F381B_P_2, |
2346 | EVEX_W_0F381B_P_2, |
2090 | EVEX_W_0F381E_P_2, |
2347 | EVEX_W_0F381E_P_2, |
2091 | EVEX_W_0F381F_P_2, |
2348 | EVEX_W_0F381F_P_2, |
- | 2349 | EVEX_W_0F3820_P_1, |
|
2092 | EVEX_W_0F3821_P_1, |
2350 | EVEX_W_0F3821_P_1, |
2093 | EVEX_W_0F3822_P_1, |
2351 | EVEX_W_0F3822_P_1, |
2094 | EVEX_W_0F3823_P_1, |
2352 | EVEX_W_0F3823_P_1, |
2095 | EVEX_W_0F3824_P_1, |
2353 | EVEX_W_0F3824_P_1, |
2096 | EVEX_W_0F3825_P_1, |
2354 | EVEX_W_0F3825_P_1, |
2097 | EVEX_W_0F3825_P_2, |
2355 | EVEX_W_0F3825_P_2, |
- | 2356 | EVEX_W_0F3826_P_1, |
|
- | 2357 | EVEX_W_0F3826_P_2, |
|
- | 2358 | EVEX_W_0F3828_P_1, |
|
2098 | EVEX_W_0F3828_P_2, |
2359 | EVEX_W_0F3828_P_2, |
- | 2360 | EVEX_W_0F3829_P_1, |
|
2099 | EVEX_W_0F3829_P_2, |
2361 | EVEX_W_0F3829_P_2, |
2100 | EVEX_W_0F382A_P_1, |
2362 | EVEX_W_0F382A_P_1, |
2101 | EVEX_W_0F382A_P_2, |
2363 | EVEX_W_0F382A_P_2, |
- | 2364 | EVEX_W_0F382B_P_2, |
|
- | 2365 | EVEX_W_0F3830_P_1, |
|
2102 | EVEX_W_0F3831_P_1, |
2366 | EVEX_W_0F3831_P_1, |
2103 | EVEX_W_0F3832_P_1, |
2367 | EVEX_W_0F3832_P_1, |
2104 | EVEX_W_0F3833_P_1, |
2368 | EVEX_W_0F3833_P_1, |
2105 | EVEX_W_0F3834_P_1, |
2369 | EVEX_W_0F3834_P_1, |
2106 | EVEX_W_0F3835_P_1, |
2370 | EVEX_W_0F3835_P_1, |
2107 | EVEX_W_0F3835_P_2, |
2371 | EVEX_W_0F3835_P_2, |
2108 | EVEX_W_0F3837_P_2, |
2372 | EVEX_W_0F3837_P_2, |
- | 2373 | EVEX_W_0F3838_P_1, |
|
- | 2374 | EVEX_W_0F3839_P_1, |
|
2109 | EVEX_W_0F383A_P_1, |
2375 | EVEX_W_0F383A_P_1, |
2110 | EVEX_W_0F3840_P_2, |
2376 | EVEX_W_0F3840_P_2, |
2111 | EVEX_W_0F3858_P_2, |
2377 | EVEX_W_0F3858_P_2, |
2112 | EVEX_W_0F3859_P_2, |
2378 | EVEX_W_0F3859_P_2, |
2113 | EVEX_W_0F385A_P_2, |
2379 | EVEX_W_0F385A_P_2, |
2114 | EVEX_W_0F385B_P_2, |
2380 | EVEX_W_0F385B_P_2, |
- | 2381 | EVEX_W_0F3866_P_2, |
|
- | 2382 | EVEX_W_0F3875_P_2, |
|
- | 2383 | EVEX_W_0F3878_P_2, |
|
- | 2384 | EVEX_W_0F3879_P_2, |
|
- | 2385 | EVEX_W_0F387A_P_2, |
|
- | 2386 | EVEX_W_0F387B_P_2, |
|
- | 2387 | EVEX_W_0F387D_P_2, |
|
- | 2388 | EVEX_W_0F3883_P_2, |
|
- | 2389 | EVEX_W_0F388D_P_2, |
|
2115 | EVEX_W_0F3891_P_2, |
2390 | EVEX_W_0F3891_P_2, |
2116 | EVEX_W_0F3893_P_2, |
2391 | EVEX_W_0F3893_P_2, |
2117 | EVEX_W_0F38A1_P_2, |
2392 | EVEX_W_0F38A1_P_2, |
2118 | EVEX_W_0F38A3_P_2, |
2393 | EVEX_W_0F38A3_P_2, |
2119 | EVEX_W_0F38C7_R_1_P_2, |
2394 | EVEX_W_0F38C7_R_1_P_2, |
Line 2127... | Line 2402... | ||
2127 | EVEX_W_0F3A05_P_2, |
2402 | EVEX_W_0F3A05_P_2, |
2128 | EVEX_W_0F3A08_P_2, |
2403 | EVEX_W_0F3A08_P_2, |
2129 | EVEX_W_0F3A09_P_2, |
2404 | EVEX_W_0F3A09_P_2, |
2130 | EVEX_W_0F3A0A_P_2, |
2405 | EVEX_W_0F3A0A_P_2, |
2131 | EVEX_W_0F3A0B_P_2, |
2406 | EVEX_W_0F3A0B_P_2, |
- | 2407 | EVEX_W_0F3A16_P_2, |
|
2132 | EVEX_W_0F3A18_P_2, |
2408 | EVEX_W_0F3A18_P_2, |
2133 | EVEX_W_0F3A19_P_2, |
2409 | EVEX_W_0F3A19_P_2, |
2134 | EVEX_W_0F3A1A_P_2, |
2410 | EVEX_W_0F3A1A_P_2, |
2135 | EVEX_W_0F3A1B_P_2, |
2411 | EVEX_W_0F3A1B_P_2, |
2136 | EVEX_W_0F3A1D_P_2, |
2412 | EVEX_W_0F3A1D_P_2, |
2137 | EVEX_W_0F3A21_P_2, |
2413 | EVEX_W_0F3A21_P_2, |
- | 2414 | EVEX_W_0F3A22_P_2, |
|
2138 | EVEX_W_0F3A23_P_2, |
2415 | EVEX_W_0F3A23_P_2, |
2139 | EVEX_W_0F3A38_P_2, |
2416 | EVEX_W_0F3A38_P_2, |
2140 | EVEX_W_0F3A39_P_2, |
2417 | EVEX_W_0F3A39_P_2, |
2141 | EVEX_W_0F3A3A_P_2, |
2418 | EVEX_W_0F3A3A_P_2, |
2142 | EVEX_W_0F3A3B_P_2, |
2419 | EVEX_W_0F3A3B_P_2, |
- | 2420 | EVEX_W_0F3A3E_P_2, |
|
- | 2421 | EVEX_W_0F3A3F_P_2, |
|
- | 2422 | EVEX_W_0F3A42_P_2, |
|
2143 | EVEX_W_0F3A43_P_2, |
2423 | EVEX_W_0F3A43_P_2, |
- | 2424 | EVEX_W_0F3A50_P_2, |
|
- | 2425 | EVEX_W_0F3A51_P_2, |
|
- | 2426 | EVEX_W_0F3A56_P_2, |
|
- | 2427 | EVEX_W_0F3A57_P_2, |
|
- | 2428 | EVEX_W_0F3A66_P_2, |
|
- | 2429 | EVEX_W_0F3A67_P_2 |
|
2144 | }; |
2430 | }; |
Line 2145... | Line 2431... | ||
2145 | 2431 | ||
Line 2146... | Line 2432... | ||
2146 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
2432 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
Line 2150... | Line 2436... | ||
2150 | struct |
2436 | struct |
2151 | { |
2437 | { |
2152 | op_rtn rtn; |
2438 | op_rtn rtn; |
2153 | int bytemode; |
2439 | int bytemode; |
2154 | } op[MAX_OPERANDS]; |
2440 | } op[MAX_OPERANDS]; |
- | 2441 | unsigned int prefix_requirement; |
|
2155 | }; |
2442 | }; |
Line 2156... | Line 2443... | ||
2156 | 2443 | ||
2157 | /* Upper case letters in the instruction names here are macros. |
2444 | /* Upper case letters in the instruction names here are macros. |
2158 | 'A' => print 'b' if no register operands or suffix_always is true |
2445 | 'A' => print 'b' if no register operands or suffix_always is true |
Line 2177... | Line 2464... | ||
2177 | or suffix_always is true. print 'q' if rex prefix is present. |
2464 | or suffix_always is true. print 'q' if rex prefix is present. |
2178 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always |
2465 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always |
2179 | is true |
2466 | is true |
2180 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
2467 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
2181 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
2468 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
2182 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
2469 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
- | 2470 | prefix and behave as 'P' otherwise |
|
2183 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise |
2471 | 'U' => print 'q' in 64bit mode if instruction has no operand size |
- | 2472 | prefix and behave as 'Q' otherwise |
|
2184 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
2473 | 'V' => print 'q' in 64bit mode if instruction has no operand size |
- | 2474 | prefix and behave as 'S' otherwise |
|
2185 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
2475 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
2186 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
2476 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
2187 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2477 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2188 | suffix_always is true. |
2478 | suffix_always is true. |
2189 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
2479 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
2190 | '!' => change condition from true to false or from false to true. |
2480 | '!' => change condition from true to false or from false to true. |
2191 | '%' => add 1 upper case letter to the macro. |
2481 | '%' => add 1 upper case letter to the macro. |
- | 2482 | '^' => print 'w' or 'l' depending on operand size prefix or |
|
- | 2483 | suffix_always is true (lcall/ljmp). |
|
- | 2484 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
|
- | 2485 | on operand size prefix. |
|
Line 2192... | Line 2486... | ||
2192 | 2486 | ||
2193 | 2 upper case letter macros: |
2487 | 2 upper case letter macros: |
2194 | "XY" => print 'x' or 'y' if no register operands or suffix_always |
2488 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
- | 2489 | operands and no broadcast. |
|
- | 2490 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no |
|
2195 | is true. |
2491 | register operands and no broadcast. |
2196 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2492 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2197 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand |
2493 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand |
2198 | or suffix_always is true |
2494 | or suffix_always is true |
2199 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2495 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2200 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise |
2496 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise |
2201 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise |
2497 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise |
- | 2498 | "LW" => print 'd', 'q' depending on the VEX.W bit |
|
- | 2499 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
|
- | 2500 | an operand size prefix, or suffix_always is true. print |
|
Line 2202... | Line 2501... | ||
2202 | "LW" => print 'd', 'q' depending on the VEX.W bit |
2501 | 'q' if rex prefix is present. |
2203 | 2502 | ||
Line 2204... | Line 2503... | ||
2204 | Many of the above letters print nothing in Intel mode. See "putop" |
2503 | Many of the above letters print nothing in Intel mode. See "putop" |
2205 | for the details. |
2504 | for the details. |
Line 2206... | Line 2505... | ||
2206 | 2505 | ||
2207 | Braces '{' and '}', and vertical bars '|', indicate alternative |
2506 | Braces '{' and '}', and vertical bars '|', indicate alternative |
2208 | mnemonic strings for AT&T and Intel. */ |
2507 | mnemonic strings for AT&T and Intel. */ |
2209 | 2508 | ||
2210 | static const struct dis386 dis386[] = { |
2509 | static const struct dis386 dis386[] = { |
2211 | /* 00 */ |
2510 | /* 00 */ |
2212 | { "addB", { Ebh1, Gb } }, |
2511 | { "addB", { Ebh1, Gb }, 0 }, |
2213 | { "addS", { Evh1, Gv } }, |
2512 | { "addS", { Evh1, Gv }, 0 }, |
2214 | { "addB", { Gb, EbS } }, |
2513 | { "addB", { Gb, EbS }, 0 }, |
2215 | { "addS", { Gv, EvS } }, |
2514 | { "addS", { Gv, EvS }, 0 }, |
2216 | { "addB", { AL, Ib } }, |
2515 | { "addB", { AL, Ib }, 0 }, |
2217 | { "addS", { eAX, Iv } }, |
2516 | { "addS", { eAX, Iv }, 0 }, |
2218 | { X86_64_TABLE (X86_64_06) }, |
2517 | { X86_64_TABLE (X86_64_06) }, |
2219 | { X86_64_TABLE (X86_64_07) }, |
2518 | { X86_64_TABLE (X86_64_07) }, |
2220 | /* 08 */ |
2519 | /* 08 */ |
2221 | { "orB", { Ebh1, Gb } }, |
2520 | { "orB", { Ebh1, Gb }, 0 }, |
2222 | { "orS", { Evh1, Gv } }, |
2521 | { "orS", { Evh1, Gv }, 0 }, |
2223 | { "orB", { Gb, EbS } }, |
2522 | { "orB", { Gb, EbS }, 0 }, |
2224 | { "orS", { Gv, EvS } }, |
2523 | { "orS", { Gv, EvS }, 0 }, |
2225 | { "orB", { AL, Ib } }, |
2524 | { "orB", { AL, Ib }, 0 }, |
2226 | { "orS", { eAX, Iv } }, |
2525 | { "orS", { eAX, Iv }, 0 }, |
2227 | { X86_64_TABLE (X86_64_0D) }, |
2526 | { X86_64_TABLE (X86_64_0D) }, |
2228 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
2527 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
2229 | /* 10 */ |
2528 | /* 10 */ |
2230 | { "adcB", { Ebh1, Gb } }, |
2529 | { "adcB", { Ebh1, Gb }, 0 }, |
2231 | { "adcS", { Evh1, Gv } }, |
2530 | { "adcS", { Evh1, Gv }, 0 }, |
2232 | { "adcB", { Gb, EbS } }, |
2531 | { "adcB", { Gb, EbS }, 0 }, |
2233 | { "adcS", { Gv, EvS } }, |
2532 | { "adcS", { Gv, EvS }, 0 }, |
2234 | { "adcB", { AL, Ib } }, |
2533 | { "adcB", { AL, Ib }, 0 }, |
2235 | { "adcS", { eAX, Iv } }, |
2534 | { "adcS", { eAX, Iv }, 0 }, |
2236 | { X86_64_TABLE (X86_64_16) }, |
2535 | { X86_64_TABLE (X86_64_16) }, |
2237 | { X86_64_TABLE (X86_64_17) }, |
2536 | { X86_64_TABLE (X86_64_17) }, |
2238 | /* 18 */ |
2537 | /* 18 */ |
2239 | { "sbbB", { Ebh1, Gb } }, |
2538 | { "sbbB", { Ebh1, Gb }, 0 }, |
2240 | { "sbbS", { Evh1, Gv } }, |
2539 | { "sbbS", { Evh1, Gv }, 0 }, |
2241 | { "sbbB", { Gb, EbS } }, |
2540 | { "sbbB", { Gb, EbS }, 0 }, |
2242 | { "sbbS", { Gv, EvS } }, |
2541 | { "sbbS", { Gv, EvS }, 0 }, |
2243 | { "sbbB", { AL, Ib } }, |
2542 | { "sbbB", { AL, Ib }, 0 }, |
2244 | { "sbbS", { eAX, Iv } }, |
2543 | { "sbbS", { eAX, Iv }, 0 }, |
2245 | { X86_64_TABLE (X86_64_1E) }, |
2544 | { X86_64_TABLE (X86_64_1E) }, |
2246 | { X86_64_TABLE (X86_64_1F) }, |
2545 | { X86_64_TABLE (X86_64_1F) }, |
2247 | /* 20 */ |
2546 | /* 20 */ |
2248 | { "andB", { Ebh1, Gb } }, |
2547 | { "andB", { Ebh1, Gb }, 0 }, |
2249 | { "andS", { Evh1, Gv } }, |
2548 | { "andS", { Evh1, Gv }, 0 }, |
2250 | { "andB", { Gb, EbS } }, |
2549 | { "andB", { Gb, EbS }, 0 }, |
2251 | { "andS", { Gv, EvS } }, |
2550 | { "andS", { Gv, EvS }, 0 }, |
2252 | { "andB", { AL, Ib } }, |
2551 | { "andB", { AL, Ib }, 0 }, |
2253 | { "andS", { eAX, Iv } }, |
2552 | { "andS", { eAX, Iv }, 0 }, |
2254 | { Bad_Opcode }, /* SEG ES prefix */ |
2553 | { Bad_Opcode }, /* SEG ES prefix */ |
2255 | { X86_64_TABLE (X86_64_27) }, |
2554 | { X86_64_TABLE (X86_64_27) }, |
2256 | /* 28 */ |
2555 | /* 28 */ |
2257 | { "subB", { Ebh1, Gb } }, |
2556 | { "subB", { Ebh1, Gb }, 0 }, |
2258 | { "subS", { Evh1, Gv } }, |
2557 | { "subS", { Evh1, Gv }, 0 }, |
2259 | { "subB", { Gb, EbS } }, |
2558 | { "subB", { Gb, EbS }, 0 }, |
2260 | { "subS", { Gv, EvS } }, |
2559 | { "subS", { Gv, EvS }, 0 }, |
2261 | { "subB", { AL, Ib } }, |
2560 | { "subB", { AL, Ib }, 0 }, |
2262 | { "subS", { eAX, Iv } }, |
2561 | { "subS", { eAX, Iv }, 0 }, |
2263 | { Bad_Opcode }, /* SEG CS prefix */ |
2562 | { Bad_Opcode }, /* SEG CS prefix */ |
2264 | { X86_64_TABLE (X86_64_2F) }, |
2563 | { X86_64_TABLE (X86_64_2F) }, |
2265 | /* 30 */ |
2564 | /* 30 */ |
2266 | { "xorB", { Ebh1, Gb } }, |
2565 | { "xorB", { Ebh1, Gb }, 0 }, |
2267 | { "xorS", { Evh1, Gv } }, |
2566 | { "xorS", { Evh1, Gv }, 0 }, |
2268 | { "xorB", { Gb, EbS } }, |
2567 | { "xorB", { Gb, EbS }, 0 }, |
2269 | { "xorS", { Gv, EvS } }, |
2568 | { "xorS", { Gv, EvS }, 0 }, |
2270 | { "xorB", { AL, Ib } }, |
2569 | { "xorB", { AL, Ib }, 0 }, |
2271 | { "xorS", { eAX, Iv } }, |
2570 | { "xorS", { eAX, Iv }, 0 }, |
2272 | { Bad_Opcode }, /* SEG SS prefix */ |
2571 | { Bad_Opcode }, /* SEG SS prefix */ |
2273 | { X86_64_TABLE (X86_64_37) }, |
2572 | { X86_64_TABLE (X86_64_37) }, |
2274 | /* 38 */ |
2573 | /* 38 */ |
2275 | { "cmpB", { Eb, Gb } }, |
2574 | { "cmpB", { Eb, Gb }, 0 }, |
2276 | { "cmpS", { Ev, Gv } }, |
2575 | { "cmpS", { Ev, Gv }, 0 }, |
2277 | { "cmpB", { Gb, EbS } }, |
2576 | { "cmpB", { Gb, EbS }, 0 }, |
2278 | { "cmpS", { Gv, EvS } }, |
2577 | { "cmpS", { Gv, EvS }, 0 }, |
2279 | { "cmpB", { AL, Ib } }, |
2578 | { "cmpB", { AL, Ib }, 0 }, |
2280 | { "cmpS", { eAX, Iv } }, |
2579 | { "cmpS", { eAX, Iv }, 0 }, |
2281 | { Bad_Opcode }, /* SEG DS prefix */ |
2580 | { Bad_Opcode }, /* SEG DS prefix */ |
2282 | { X86_64_TABLE (X86_64_3F) }, |
2581 | { X86_64_TABLE (X86_64_3F) }, |
2283 | /* 40 */ |
2582 | /* 40 */ |
2284 | { "inc{S|}", { RMeAX } }, |
2583 | { "inc{S|}", { RMeAX }, 0 }, |
2285 | { "inc{S|}", { RMeCX } }, |
2584 | { "inc{S|}", { RMeCX }, 0 }, |
2286 | { "inc{S|}", { RMeDX } }, |
2585 | { "inc{S|}", { RMeDX }, 0 }, |
2287 | { "inc{S|}", { RMeBX } }, |
2586 | { "inc{S|}", { RMeBX }, 0 }, |
2288 | { "inc{S|}", { RMeSP } }, |
2587 | { "inc{S|}", { RMeSP }, 0 }, |
2289 | { "inc{S|}", { RMeBP } }, |
2588 | { "inc{S|}", { RMeBP }, 0 }, |
2290 | { "inc{S|}", { RMeSI } }, |
2589 | { "inc{S|}", { RMeSI }, 0 }, |
2291 | { "inc{S|}", { RMeDI } }, |
2590 | { "inc{S|}", { RMeDI }, 0 }, |
2292 | /* 48 */ |
2591 | /* 48 */ |
2293 | { "dec{S|}", { RMeAX } }, |
2592 | { "dec{S|}", { RMeAX }, 0 }, |
2294 | { "dec{S|}", { RMeCX } }, |
2593 | { "dec{S|}", { RMeCX }, 0 }, |
2295 | { "dec{S|}", { RMeDX } }, |
2594 | { "dec{S|}", { RMeDX }, 0 }, |
2296 | { "dec{S|}", { RMeBX } }, |
2595 | { "dec{S|}", { RMeBX }, 0 }, |
2297 | { "dec{S|}", { RMeSP } }, |
2596 | { "dec{S|}", { RMeSP }, 0 }, |
2298 | { "dec{S|}", { RMeBP } }, |
2597 | { "dec{S|}", { RMeBP }, 0 }, |
2299 | { "dec{S|}", { RMeSI } }, |
2598 | { "dec{S|}", { RMeSI }, 0 }, |
2300 | { "dec{S|}", { RMeDI } }, |
2599 | { "dec{S|}", { RMeDI }, 0 }, |
2301 | /* 50 */ |
2600 | /* 50 */ |
2302 | { "pushV", { RMrAX } }, |
2601 | { "pushV", { RMrAX }, 0 }, |
2303 | { "pushV", { RMrCX } }, |
2602 | { "pushV", { RMrCX }, 0 }, |
2304 | { "pushV", { RMrDX } }, |
2603 | { "pushV", { RMrDX }, 0 }, |
2305 | { "pushV", { RMrBX } }, |
2604 | { "pushV", { RMrBX }, 0 }, |
2306 | { "pushV", { RMrSP } }, |
2605 | { "pushV", { RMrSP }, 0 }, |
2307 | { "pushV", { RMrBP } }, |
2606 | { "pushV", { RMrBP }, 0 }, |
2308 | { "pushV", { RMrSI } }, |
2607 | { "pushV", { RMrSI }, 0 }, |
2309 | { "pushV", { RMrDI } }, |
2608 | { "pushV", { RMrDI }, 0 }, |
2310 | /* 58 */ |
2609 | /* 58 */ |
2311 | { "popV", { RMrAX } }, |
2610 | { "popV", { RMrAX }, 0 }, |
2312 | { "popV", { RMrCX } }, |
2611 | { "popV", { RMrCX }, 0 }, |
2313 | { "popV", { RMrDX } }, |
2612 | { "popV", { RMrDX }, 0 }, |
2314 | { "popV", { RMrBX } }, |
2613 | { "popV", { RMrBX }, 0 }, |
2315 | { "popV", { RMrSP } }, |
2614 | { "popV", { RMrSP }, 0 }, |
2316 | { "popV", { RMrBP } }, |
2615 | { "popV", { RMrBP }, 0 }, |
2317 | { "popV", { RMrSI } }, |
2616 | { "popV", { RMrSI }, 0 }, |
2318 | { "popV", { RMrDI } }, |
2617 | { "popV", { RMrDI }, 0 }, |
2319 | /* 60 */ |
2618 | /* 60 */ |
2320 | { X86_64_TABLE (X86_64_60) }, |
2619 | { X86_64_TABLE (X86_64_60) }, |
2321 | { X86_64_TABLE (X86_64_61) }, |
2620 | { X86_64_TABLE (X86_64_61) }, |
2322 | { X86_64_TABLE (X86_64_62) }, |
2621 | { X86_64_TABLE (X86_64_62) }, |
2323 | { X86_64_TABLE (X86_64_63) }, |
2622 | { X86_64_TABLE (X86_64_63) }, |
2324 | { Bad_Opcode }, /* seg fs */ |
2623 | { Bad_Opcode }, /* seg fs */ |
2325 | { Bad_Opcode }, /* seg gs */ |
2624 | { Bad_Opcode }, /* seg gs */ |
2326 | { Bad_Opcode }, /* op size prefix */ |
2625 | { Bad_Opcode }, /* op size prefix */ |
2327 | { Bad_Opcode }, /* adr size prefix */ |
2626 | { Bad_Opcode }, /* adr size prefix */ |
2328 | /* 68 */ |
2627 | /* 68 */ |
2329 | { "pushT", { sIv } }, |
2628 | { "pushT", { sIv }, 0 }, |
2330 | { "imulS", { Gv, Ev, Iv } }, |
2629 | { "imulS", { Gv, Ev, Iv }, 0 }, |
2331 | { "pushT", { sIbT } }, |
2630 | { "pushT", { sIbT }, 0 }, |
2332 | { "imulS", { Gv, Ev, sIb } }, |
2631 | { "imulS", { Gv, Ev, sIb }, 0 }, |
2333 | { "ins{b|}", { Ybr, indirDX } }, |
2632 | { "ins{b|}", { Ybr, indirDX }, 0 }, |
2334 | { X86_64_TABLE (X86_64_6D) }, |
2633 | { X86_64_TABLE (X86_64_6D) }, |
2335 | { "outs{b|}", { indirDXr, Xb } }, |
2634 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
2336 | { X86_64_TABLE (X86_64_6F) }, |
2635 | { X86_64_TABLE (X86_64_6F) }, |
2337 | /* 70 */ |
2636 | /* 70 */ |
2338 | { "joH", { Jb, BND, cond_jump_flag } }, |
2637 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2339 | { "jnoH", { Jb, BND, cond_jump_flag } }, |
2638 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, |
2340 | { "jbH", { Jb, BND, cond_jump_flag } }, |
2639 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, |
2341 | { "jaeH", { Jb, BND, cond_jump_flag } }, |
2640 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, |
2342 | { "jeH", { Jb, BND, cond_jump_flag } }, |
2641 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, |
2343 | { "jneH", { Jb, BND, cond_jump_flag } }, |
2642 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, |
2344 | { "jbeH", { Jb, BND, cond_jump_flag } }, |
2643 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, |
2345 | { "jaH", { Jb, BND, cond_jump_flag } }, |
2644 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, |
2346 | /* 78 */ |
2645 | /* 78 */ |
2347 | { "jsH", { Jb, BND, cond_jump_flag } }, |
2646 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2348 | { "jnsH", { Jb, BND, cond_jump_flag } }, |
2647 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, |
2349 | { "jpH", { Jb, BND, cond_jump_flag } }, |
2648 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, |
2350 | { "jnpH", { Jb, BND, cond_jump_flag } }, |
2649 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, |
2351 | { "jlH", { Jb, BND, cond_jump_flag } }, |
2650 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, |
2352 | { "jgeH", { Jb, BND, cond_jump_flag } }, |
2651 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, |
2353 | { "jleH", { Jb, BND, cond_jump_flag } }, |
2652 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, |
2354 | { "jgH", { Jb, BND, cond_jump_flag } }, |
2653 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, |
2355 | /* 80 */ |
2654 | /* 80 */ |
2356 | { REG_TABLE (REG_80) }, |
2655 | { REG_TABLE (REG_80) }, |
2357 | { REG_TABLE (REG_81) }, |
2656 | { REG_TABLE (REG_81) }, |
2358 | { Bad_Opcode }, |
2657 | { Bad_Opcode }, |
2359 | { REG_TABLE (REG_82) }, |
2658 | { REG_TABLE (REG_82) }, |
2360 | { "testB", { Eb, Gb } }, |
2659 | { "testB", { Eb, Gb }, 0 }, |
2361 | { "testS", { Ev, Gv } }, |
2660 | { "testS", { Ev, Gv }, 0 }, |
2362 | { "xchgB", { Ebh2, Gb } }, |
2661 | { "xchgB", { Ebh2, Gb }, 0 }, |
2363 | { "xchgS", { Evh2, Gv } }, |
2662 | { "xchgS", { Evh2, Gv }, 0 }, |
2364 | /* 88 */ |
2663 | /* 88 */ |
2365 | { "movB", { Ebh3, Gb } }, |
2664 | { "movB", { Ebh3, Gb }, 0 }, |
2366 | { "movS", { Evh3, Gv } }, |
2665 | { "movS", { Evh3, Gv }, 0 }, |
2367 | { "movB", { Gb, EbS } }, |
2666 | { "movB", { Gb, EbS }, 0 }, |
2368 | { "movS", { Gv, EvS } }, |
2667 | { "movS", { Gv, EvS }, 0 }, |
2369 | { "movD", { Sv, Sw } }, |
2668 | { "movD", { Sv, Sw }, 0 }, |
2370 | { MOD_TABLE (MOD_8D) }, |
2669 | { MOD_TABLE (MOD_8D) }, |
2371 | { "movD", { Sw, Sv } }, |
2670 | { "movD", { Sw, Sv }, 0 }, |
2372 | { REG_TABLE (REG_8F) }, |
2671 | { REG_TABLE (REG_8F) }, |
2373 | /* 90 */ |
2672 | /* 90 */ |
2374 | { PREFIX_TABLE (PREFIX_90) }, |
2673 | { PREFIX_TABLE (PREFIX_90) }, |
2375 | { "xchgS", { RMeCX, eAX } }, |
2674 | { "xchgS", { RMeCX, eAX }, 0 }, |
2376 | { "xchgS", { RMeDX, eAX } }, |
2675 | { "xchgS", { RMeDX, eAX }, 0 }, |
2377 | { "xchgS", { RMeBX, eAX } }, |
2676 | { "xchgS", { RMeBX, eAX }, 0 }, |
2378 | { "xchgS", { RMeSP, eAX } }, |
2677 | { "xchgS", { RMeSP, eAX }, 0 }, |
2379 | { "xchgS", { RMeBP, eAX } }, |
2678 | { "xchgS", { RMeBP, eAX }, 0 }, |
2380 | { "xchgS", { RMeSI, eAX } }, |
2679 | { "xchgS", { RMeSI, eAX }, 0 }, |
2381 | { "xchgS", { RMeDI, eAX } }, |
2680 | { "xchgS", { RMeDI, eAX }, 0 }, |
2382 | /* 98 */ |
2681 | /* 98 */ |
2383 | { "cW{t|}R", { XX } }, |
2682 | { "cW{t|}R", { XX }, 0 }, |
2384 | { "cR{t|}O", { XX } }, |
2683 | { "cR{t|}O", { XX }, 0 }, |
2385 | { X86_64_TABLE (X86_64_9A) }, |
2684 | { X86_64_TABLE (X86_64_9A) }, |
2386 | { Bad_Opcode }, /* fwait */ |
2685 | { Bad_Opcode }, /* fwait */ |
2387 | { "pushfT", { XX } }, |
2686 | { "pushfT", { XX }, 0 }, |
2388 | { "popfT", { XX } }, |
2687 | { "popfT", { XX }, 0 }, |
2389 | { "sahf", { XX } }, |
2688 | { "sahf", { XX }, 0 }, |
2390 | { "lahf", { XX } }, |
2689 | { "lahf", { XX }, 0 }, |
2391 | /* a0 */ |
2690 | /* a0 */ |
2392 | { "mov%LB", { AL, Ob } }, |
2691 | { "mov%LB", { AL, Ob }, 0 }, |
2393 | { "mov%LS", { eAX, Ov } }, |
2692 | { "mov%LS", { eAX, Ov }, 0 }, |
2394 | { "mov%LB", { Ob, AL } }, |
2693 | { "mov%LB", { Ob, AL }, 0 }, |
2395 | { "mov%LS", { Ov, eAX } }, |
2694 | { "mov%LS", { Ov, eAX }, 0 }, |
2396 | { "movs{b|}", { Ybr, Xb } }, |
2695 | { "movs{b|}", { Ybr, Xb }, 0 }, |
2397 | { "movs{R|}", { Yvr, Xv } }, |
2696 | { "movs{R|}", { Yvr, Xv }, 0 }, |
2398 | { "cmps{b|}", { Xb, Yb } }, |
2697 | { "cmps{b|}", { Xb, Yb }, 0 }, |
2399 | { "cmps{R|}", { Xv, Yv } }, |
2698 | { "cmps{R|}", { Xv, Yv }, 0 }, |
2400 | /* a8 */ |
2699 | /* a8 */ |
2401 | { "testB", { AL, Ib } }, |
2700 | { "testB", { AL, Ib }, 0 }, |
2402 | { "testS", { eAX, Iv } }, |
2701 | { "testS", { eAX, Iv }, 0 }, |
2403 | { "stosB", { Ybr, AL } }, |
2702 | { "stosB", { Ybr, AL }, 0 }, |
2404 | { "stosS", { Yvr, eAX } }, |
2703 | { "stosS", { Yvr, eAX }, 0 }, |
2405 | { "lodsB", { ALr, Xb } }, |
2704 | { "lodsB", { ALr, Xb }, 0 }, |
2406 | { "lodsS", { eAXr, Xv } }, |
2705 | { "lodsS", { eAXr, Xv }, 0 }, |
2407 | { "scasB", { AL, Yb } }, |
2706 | { "scasB", { AL, Yb }, 0 }, |
2408 | { "scasS", { eAX, Yv } }, |
2707 | { "scasS", { eAX, Yv }, 0 }, |
2409 | /* b0 */ |
2708 | /* b0 */ |
2410 | { "movB", { RMAL, Ib } }, |
2709 | { "movB", { RMAL, Ib }, 0 }, |
2411 | { "movB", { RMCL, Ib } }, |
2710 | { "movB", { RMCL, Ib }, 0 }, |
2412 | { "movB", { RMDL, Ib } }, |
2711 | { "movB", { RMDL, Ib }, 0 }, |
2413 | { "movB", { RMBL, Ib } }, |
2712 | { "movB", { RMBL, Ib }, 0 }, |
2414 | { "movB", { RMAH, Ib } }, |
2713 | { "movB", { RMAH, Ib }, 0 }, |
2415 | { "movB", { RMCH, Ib } }, |
2714 | { "movB", { RMCH, Ib }, 0 }, |
2416 | { "movB", { RMDH, Ib } }, |
2715 | { "movB", { RMDH, Ib }, 0 }, |
2417 | { "movB", { RMBH, Ib } }, |
2716 | { "movB", { RMBH, Ib }, 0 }, |
2418 | /* b8 */ |
2717 | /* b8 */ |
2419 | { "mov%LV", { RMeAX, Iv64 } }, |
2718 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2420 | { "mov%LV", { RMeCX, Iv64 } }, |
2719 | { "mov%LV", { RMeCX, Iv64 }, 0 }, |
2421 | { "mov%LV", { RMeDX, Iv64 } }, |
2720 | { "mov%LV", { RMeDX, Iv64 }, 0 }, |
2422 | { "mov%LV", { RMeBX, Iv64 } }, |
2721 | { "mov%LV", { RMeBX, Iv64 }, 0 }, |
2423 | { "mov%LV", { RMeSP, Iv64 } }, |
2722 | { "mov%LV", { RMeSP, Iv64 }, 0 }, |
2424 | { "mov%LV", { RMeBP, Iv64 } }, |
2723 | { "mov%LV", { RMeBP, Iv64 }, 0 }, |
2425 | { "mov%LV", { RMeSI, Iv64 } }, |
2724 | { "mov%LV", { RMeSI, Iv64 }, 0 }, |
2426 | { "mov%LV", { RMeDI, Iv64 } }, |
2725 | { "mov%LV", { RMeDI, Iv64 }, 0 }, |
2427 | /* c0 */ |
2726 | /* c0 */ |
2428 | { REG_TABLE (REG_C0) }, |
2727 | { REG_TABLE (REG_C0) }, |
2429 | { REG_TABLE (REG_C1) }, |
2728 | { REG_TABLE (REG_C1) }, |
2430 | { "retT", { Iw, BND } }, |
2729 | { "retT", { Iw, BND }, 0 }, |
2431 | { "retT", { BND } }, |
2730 | { "retT", { BND }, 0 }, |
2432 | { X86_64_TABLE (X86_64_C4) }, |
2731 | { X86_64_TABLE (X86_64_C4) }, |
2433 | { X86_64_TABLE (X86_64_C5) }, |
2732 | { X86_64_TABLE (X86_64_C5) }, |
2434 | { REG_TABLE (REG_C6) }, |
2733 | { REG_TABLE (REG_C6) }, |
2435 | { REG_TABLE (REG_C7) }, |
2734 | { REG_TABLE (REG_C7) }, |
2436 | /* c8 */ |
2735 | /* c8 */ |
2437 | { "enterT", { Iw, Ib } }, |
2736 | { "enterT", { Iw, Ib }, 0 }, |
2438 | { "leaveT", { XX } }, |
2737 | { "leaveT", { XX }, 0 }, |
2439 | { "Jret{|f}P", { Iw } }, |
2738 | { "Jret{|f}P", { Iw }, 0 }, |
2440 | { "Jret{|f}P", { XX } }, |
2739 | { "Jret{|f}P", { XX }, 0 }, |
2441 | { "int3", { XX } }, |
2740 | { "int3", { XX }, 0 }, |
2442 | { "int", { Ib } }, |
2741 | { "int", { Ib }, 0 }, |
2443 | { X86_64_TABLE (X86_64_CE) }, |
2742 | { X86_64_TABLE (X86_64_CE) }, |
2444 | { "iretP", { XX } }, |
2743 | { "iret%LP", { XX }, 0 }, |
2445 | /* d0 */ |
2744 | /* d0 */ |
2446 | { REG_TABLE (REG_D0) }, |
2745 | { REG_TABLE (REG_D0) }, |
2447 | { REG_TABLE (REG_D1) }, |
2746 | { REG_TABLE (REG_D1) }, |
2448 | { REG_TABLE (REG_D2) }, |
2747 | { REG_TABLE (REG_D2) }, |
2449 | { REG_TABLE (REG_D3) }, |
2748 | { REG_TABLE (REG_D3) }, |
2450 | { X86_64_TABLE (X86_64_D4) }, |
2749 | { X86_64_TABLE (X86_64_D4) }, |
2451 | { X86_64_TABLE (X86_64_D5) }, |
2750 | { X86_64_TABLE (X86_64_D5) }, |
2452 | { Bad_Opcode }, |
2751 | { Bad_Opcode }, |
2453 | { "xlat", { DSBX } }, |
2752 | { "xlat", { DSBX }, 0 }, |
2454 | /* d8 */ |
2753 | /* d8 */ |
2455 | { FLOAT }, |
2754 | { FLOAT }, |
2456 | { FLOAT }, |
2755 | { FLOAT }, |
2457 | { FLOAT }, |
2756 | { FLOAT }, |
2458 | { FLOAT }, |
2757 | { FLOAT }, |
2459 | { FLOAT }, |
2758 | { FLOAT }, |
2460 | { FLOAT }, |
2759 | { FLOAT }, |
2461 | { FLOAT }, |
2760 | { FLOAT }, |
2462 | { FLOAT }, |
2761 | { FLOAT }, |
2463 | /* e0 */ |
2762 | /* e0 */ |
2464 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
2763 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2465 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, |
2764 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2466 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, |
2765 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2467 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, |
2766 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2468 | { "inB", { AL, Ib } }, |
2767 | { "inB", { AL, Ib }, 0 }, |
2469 | { "inG", { zAX, Ib } }, |
2768 | { "inG", { zAX, Ib }, 0 }, |
2470 | { "outB", { Ib, AL } }, |
2769 | { "outB", { Ib, AL }, 0 }, |
2471 | { "outG", { Ib, zAX } }, |
2770 | { "outG", { Ib, zAX }, 0 }, |
2472 | /* e8 */ |
2771 | /* e8 */ |
2473 | { "callT", { Jv, BND } }, |
2772 | { X86_64_TABLE (X86_64_E8) }, |
2474 | { "jmpT", { Jv, BND } }, |
2773 | { X86_64_TABLE (X86_64_E9) }, |
2475 | { X86_64_TABLE (X86_64_EA) }, |
2774 | { X86_64_TABLE (X86_64_EA) }, |
2476 | { "jmp", { Jb, BND } }, |
2775 | { "jmp", { Jb, BND }, 0 }, |
2477 | { "inB", { AL, indirDX } }, |
2776 | { "inB", { AL, indirDX }, 0 }, |
2478 | { "inG", { zAX, indirDX } }, |
2777 | { "inG", { zAX, indirDX }, 0 }, |
2479 | { "outB", { indirDX, AL } }, |
2778 | { "outB", { indirDX, AL }, 0 }, |
2480 | { "outG", { indirDX, zAX } }, |
2779 | { "outG", { indirDX, zAX }, 0 }, |
2481 | /* f0 */ |
2780 | /* f0 */ |
2482 | { Bad_Opcode }, /* lock prefix */ |
2781 | { Bad_Opcode }, /* lock prefix */ |
2483 | { "icebp", { XX } }, |
2782 | { "icebp", { XX }, 0 }, |
2484 | { Bad_Opcode }, /* repne */ |
2783 | { Bad_Opcode }, /* repne */ |
2485 | { Bad_Opcode }, /* repz */ |
2784 | { Bad_Opcode }, /* repz */ |
2486 | { "hlt", { XX } }, |
2785 | { "hlt", { XX }, 0 }, |
2487 | { "cmc", { XX } }, |
2786 | { "cmc", { XX }, 0 }, |
2488 | { REG_TABLE (REG_F6) }, |
2787 | { REG_TABLE (REG_F6) }, |
2489 | { REG_TABLE (REG_F7) }, |
2788 | { REG_TABLE (REG_F7) }, |
2490 | /* f8 */ |
2789 | /* f8 */ |
2491 | { "clc", { XX } }, |
2790 | { "clc", { XX }, 0 }, |
2492 | { "stc", { XX } }, |
2791 | { "stc", { XX }, 0 }, |
2493 | { "cli", { XX } }, |
2792 | { "cli", { XX }, 0 }, |
2494 | { "sti", { XX } }, |
2793 | { "sti", { XX }, 0 }, |
2495 | { "cld", { XX } }, |
2794 | { "cld", { XX }, 0 }, |
Line 2496... | Line 2795... | ||
2496 | { "std", { XX } }, |
2795 | { "std", { XX }, 0 }, |
2497 | { REG_TABLE (REG_FE) }, |
2796 | { REG_TABLE (REG_FE) }, |
2498 | { REG_TABLE (REG_FF) }, |
2797 | { REG_TABLE (REG_FF) }, |
2499 | }; |
2798 | }; |
2500 | 2799 | ||
2501 | static const struct dis386 dis386_twobyte[] = { |
2800 | static const struct dis386 dis386_twobyte[] = { |
2502 | /* 00 */ |
2801 | /* 00 */ |
2503 | { REG_TABLE (REG_0F00 ) }, |
2802 | { REG_TABLE (REG_0F00 ) }, |
2504 | { REG_TABLE (REG_0F01 ) }, |
2803 | { REG_TABLE (REG_0F01 ) }, |
2505 | { "larS", { Gv, Ew } }, |
2804 | { "larS", { Gv, Ew }, 0 }, |
2506 | { "lslS", { Gv, Ew } }, |
2805 | { "lslS", { Gv, Ew }, 0 }, |
2507 | { Bad_Opcode }, |
2806 | { Bad_Opcode }, |
2508 | { "syscall", { XX } }, |
2807 | { "syscall", { XX }, 0 }, |
2509 | { "clts", { XX } }, |
2808 | { "clts", { XX }, 0 }, |
2510 | { "sysretP", { XX } }, |
2809 | { "sysret%LP", { XX }, 0 }, |
2511 | /* 08 */ |
2810 | /* 08 */ |
2512 | { "invd", { XX } }, |
2811 | { "invd", { XX }, 0 }, |
2513 | { "wbinvd", { XX } }, |
2812 | { "wbinvd", { XX }, 0 }, |
2514 | { Bad_Opcode }, |
2813 | { Bad_Opcode }, |
2515 | { "ud2", { XX } }, |
2814 | { "ud2", { XX }, 0 }, |
2516 | { Bad_Opcode }, |
2815 | { Bad_Opcode }, |
2517 | { REG_TABLE (REG_0F0D) }, |
2816 | { REG_TABLE (REG_0F0D) }, |
2518 | { "femms", { XX } }, |
2817 | { "femms", { XX }, 0 }, |
2519 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ |
2818 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ |
2520 | /* 10 */ |
2819 | /* 10 */ |
2521 | { PREFIX_TABLE (PREFIX_0F10) }, |
2820 | { PREFIX_TABLE (PREFIX_0F10) }, |
2522 | { PREFIX_TABLE (PREFIX_0F11) }, |
2821 | { PREFIX_TABLE (PREFIX_0F11) }, |
2523 | { PREFIX_TABLE (PREFIX_0F12) }, |
2822 | { PREFIX_TABLE (PREFIX_0F12) }, |
2524 | { MOD_TABLE (MOD_0F13) }, |
2823 | { MOD_TABLE (MOD_0F13) }, |
2525 | { "unpcklpX", { XM, EXx } }, |
2824 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2526 | { "unpckhpX", { XM, EXx } }, |
2825 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, |
2527 | { PREFIX_TABLE (PREFIX_0F16) }, |
2826 | { PREFIX_TABLE (PREFIX_0F16) }, |
2528 | { MOD_TABLE (MOD_0F17) }, |
2827 | { MOD_TABLE (MOD_0F17) }, |
2529 | /* 18 */ |
2828 | /* 18 */ |
2530 | { REG_TABLE (REG_0F18) }, |
2829 | { REG_TABLE (REG_0F18) }, |
2531 | { "nopQ", { Ev } }, |
2830 | { "nopQ", { Ev }, 0 }, |
2532 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2831 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2533 | { PREFIX_TABLE (PREFIX_0F1B) }, |
2832 | { PREFIX_TABLE (PREFIX_0F1B) }, |
2534 | { "nopQ", { Ev } }, |
2833 | { "nopQ", { Ev }, 0 }, |
2535 | { "nopQ", { Ev } }, |
2834 | { "nopQ", { Ev }, 0 }, |
2536 | { "nopQ", { Ev } }, |
2835 | { "nopQ", { Ev }, 0 }, |
2537 | { "nopQ", { Ev } }, |
2836 | { "nopQ", { Ev }, 0 }, |
2538 | /* 20 */ |
2837 | /* 20 */ |
2539 | { MOD_TABLE (MOD_0F20) }, |
2838 | { "movZ", { Rm, Cm }, 0 }, |
2540 | { MOD_TABLE (MOD_0F21) }, |
2839 | { "movZ", { Rm, Dm }, 0 }, |
2541 | { MOD_TABLE (MOD_0F22) }, |
2840 | { "movZ", { Cm, Rm }, 0 }, |
2542 | { MOD_TABLE (MOD_0F23) }, |
2841 | { "movZ", { Dm, Rm }, 0 }, |
2543 | { MOD_TABLE (MOD_0F24) }, |
2842 | { MOD_TABLE (MOD_0F24) }, |
2544 | { Bad_Opcode }, |
2843 | { Bad_Opcode }, |
2545 | { MOD_TABLE (MOD_0F26) }, |
2844 | { MOD_TABLE (MOD_0F26) }, |
2546 | { Bad_Opcode }, |
2845 | { Bad_Opcode }, |
2547 | /* 28 */ |
2846 | /* 28 */ |
2548 | { "movapX", { XM, EXx } }, |
2847 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2549 | { "movapX", { EXxS, XM } }, |
2848 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, |
2550 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2849 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2551 | { PREFIX_TABLE (PREFIX_0F2B) }, |
2850 | { PREFIX_TABLE (PREFIX_0F2B) }, |
2552 | { PREFIX_TABLE (PREFIX_0F2C) }, |
2851 | { PREFIX_TABLE (PREFIX_0F2C) }, |
2553 | { PREFIX_TABLE (PREFIX_0F2D) }, |
2852 | { PREFIX_TABLE (PREFIX_0F2D) }, |
2554 | { PREFIX_TABLE (PREFIX_0F2E) }, |
2853 | { PREFIX_TABLE (PREFIX_0F2E) }, |
2555 | { PREFIX_TABLE (PREFIX_0F2F) }, |
2854 | { PREFIX_TABLE (PREFIX_0F2F) }, |
2556 | /* 30 */ |
2855 | /* 30 */ |
2557 | { "wrmsr", { XX } }, |
2856 | { "wrmsr", { XX }, 0 }, |
2558 | { "rdtsc", { XX } }, |
2857 | { "rdtsc", { XX }, 0 }, |
2559 | { "rdmsr", { XX } }, |
2858 | { "rdmsr", { XX }, 0 }, |
2560 | { "rdpmc", { XX } }, |
2859 | { "rdpmc", { XX }, 0 }, |
2561 | { "sysenter", { XX } }, |
2860 | { "sysenter", { XX }, 0 }, |
2562 | { "sysexit", { XX } }, |
2861 | { "sysexit", { XX }, 0 }, |
2563 | { Bad_Opcode }, |
2862 | { Bad_Opcode }, |
2564 | { "getsec", { XX } }, |
2863 | { "getsec", { XX }, 0 }, |
2565 | /* 38 */ |
2864 | /* 38 */ |
2566 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
2865 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
2567 | { Bad_Opcode }, |
2866 | { Bad_Opcode }, |
2568 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
2867 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
2569 | { Bad_Opcode }, |
2868 | { Bad_Opcode }, |
2570 | { Bad_Opcode }, |
2869 | { Bad_Opcode }, |
2571 | { Bad_Opcode }, |
2870 | { Bad_Opcode }, |
2572 | { Bad_Opcode }, |
2871 | { Bad_Opcode }, |
2573 | { Bad_Opcode }, |
2872 | { Bad_Opcode }, |
2574 | /* 40 */ |
2873 | /* 40 */ |
2575 | { "cmovoS", { Gv, Ev } }, |
2874 | { "cmovoS", { Gv, Ev }, 0 }, |
2576 | { "cmovnoS", { Gv, Ev } }, |
2875 | { "cmovnoS", { Gv, Ev }, 0 }, |
2577 | { "cmovbS", { Gv, Ev } }, |
2876 | { "cmovbS", { Gv, Ev }, 0 }, |
2578 | { "cmovaeS", { Gv, Ev } }, |
2877 | { "cmovaeS", { Gv, Ev }, 0 }, |
2579 | { "cmoveS", { Gv, Ev } }, |
2878 | { "cmoveS", { Gv, Ev }, 0 }, |
2580 | { "cmovneS", { Gv, Ev } }, |
2879 | { "cmovneS", { Gv, Ev }, 0 }, |
2581 | { "cmovbeS", { Gv, Ev } }, |
2880 | { "cmovbeS", { Gv, Ev }, 0 }, |
2582 | { "cmovaS", { Gv, Ev } }, |
2881 | { "cmovaS", { Gv, Ev }, 0 }, |
2583 | /* 48 */ |
2882 | /* 48 */ |
2584 | { "cmovsS", { Gv, Ev } }, |
2883 | { "cmovsS", { Gv, Ev }, 0 }, |
2585 | { "cmovnsS", { Gv, Ev } }, |
2884 | { "cmovnsS", { Gv, Ev }, 0 }, |
2586 | { "cmovpS", { Gv, Ev } }, |
2885 | { "cmovpS", { Gv, Ev }, 0 }, |
2587 | { "cmovnpS", { Gv, Ev } }, |
2886 | { "cmovnpS", { Gv, Ev }, 0 }, |
2588 | { "cmovlS", { Gv, Ev } }, |
2887 | { "cmovlS", { Gv, Ev }, 0 }, |
2589 | { "cmovgeS", { Gv, Ev } }, |
2888 | { "cmovgeS", { Gv, Ev }, 0 }, |
2590 | { "cmovleS", { Gv, Ev } }, |
2889 | { "cmovleS", { Gv, Ev }, 0 }, |
2591 | { "cmovgS", { Gv, Ev } }, |
2890 | { "cmovgS", { Gv, Ev }, 0 }, |
2592 | /* 50 */ |
2891 | /* 50 */ |
2593 | { MOD_TABLE (MOD_0F51) }, |
2892 | { MOD_TABLE (MOD_0F51) }, |
2594 | { PREFIX_TABLE (PREFIX_0F51) }, |
2893 | { PREFIX_TABLE (PREFIX_0F51) }, |
2595 | { PREFIX_TABLE (PREFIX_0F52) }, |
2894 | { PREFIX_TABLE (PREFIX_0F52) }, |
2596 | { PREFIX_TABLE (PREFIX_0F53) }, |
2895 | { PREFIX_TABLE (PREFIX_0F53) }, |
2597 | { "andpX", { XM, EXx } }, |
2896 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2598 | { "andnpX", { XM, EXx } }, |
2897 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, |
2599 | { "orpX", { XM, EXx } }, |
2898 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, |
2600 | { "xorpX", { XM, EXx } }, |
2899 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, |
Line 2609... | Line 2908... | ||
2609 | { PREFIX_TABLE (PREFIX_0F5F) }, |
2908 | { PREFIX_TABLE (PREFIX_0F5F) }, |
2610 | /* 60 */ |
2909 | /* 60 */ |
2611 | { PREFIX_TABLE (PREFIX_0F60) }, |
2910 | { PREFIX_TABLE (PREFIX_0F60) }, |
2612 | { PREFIX_TABLE (PREFIX_0F61) }, |
2911 | { PREFIX_TABLE (PREFIX_0F61) }, |
2613 | { PREFIX_TABLE (PREFIX_0F62) }, |
2912 | { PREFIX_TABLE (PREFIX_0F62) }, |
2614 | { "packsswb", { MX, EM } }, |
2913 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2615 | { "pcmpgtb", { MX, EM } }, |
2914 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, |
2616 | { "pcmpgtw", { MX, EM } }, |
2915 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, |
2617 | { "pcmpgtd", { MX, EM } }, |
2916 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, |
2618 | { "packuswb", { MX, EM } }, |
2917 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, |
2619 | /* 68 */ |
2918 | /* 68 */ |
2620 | { "punpckhbw", { MX, EM } }, |
2919 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2621 | { "punpckhwd", { MX, EM } }, |
2920 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, |
2622 | { "punpckhdq", { MX, EM } }, |
2921 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, |
2623 | { "packssdw", { MX, EM } }, |
2922 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, |
2624 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2923 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2625 | { PREFIX_TABLE (PREFIX_0F6D) }, |
2924 | { PREFIX_TABLE (PREFIX_0F6D) }, |
2626 | { "movK", { MX, Edq } }, |
2925 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
2627 | { PREFIX_TABLE (PREFIX_0F6F) }, |
2926 | { PREFIX_TABLE (PREFIX_0F6F) }, |
2628 | /* 70 */ |
2927 | /* 70 */ |
2629 | { PREFIX_TABLE (PREFIX_0F70) }, |
2928 | { PREFIX_TABLE (PREFIX_0F70) }, |
2630 | { REG_TABLE (REG_0F71) }, |
2929 | { REG_TABLE (REG_0F71) }, |
2631 | { REG_TABLE (REG_0F72) }, |
2930 | { REG_TABLE (REG_0F72) }, |
2632 | { REG_TABLE (REG_0F73) }, |
2931 | { REG_TABLE (REG_0F73) }, |
2633 | { "pcmpeqb", { MX, EM } }, |
2932 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2634 | { "pcmpeqw", { MX, EM } }, |
2933 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, |
2635 | { "pcmpeqd", { MX, EM } }, |
2934 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, |
2636 | { "emms", { XX } }, |
2935 | { "emms", { XX }, PREFIX_OPCODE }, |
2637 | /* 78 */ |
2936 | /* 78 */ |
2638 | { PREFIX_TABLE (PREFIX_0F78) }, |
2937 | { PREFIX_TABLE (PREFIX_0F78) }, |
2639 | { PREFIX_TABLE (PREFIX_0F79) }, |
2938 | { PREFIX_TABLE (PREFIX_0F79) }, |
2640 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
2939 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
2641 | { Bad_Opcode }, |
2940 | { Bad_Opcode }, |
2642 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2941 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2643 | { PREFIX_TABLE (PREFIX_0F7D) }, |
2942 | { PREFIX_TABLE (PREFIX_0F7D) }, |
2644 | { PREFIX_TABLE (PREFIX_0F7E) }, |
2943 | { PREFIX_TABLE (PREFIX_0F7E) }, |
2645 | { PREFIX_TABLE (PREFIX_0F7F) }, |
2944 | { PREFIX_TABLE (PREFIX_0F7F) }, |
2646 | /* 80 */ |
2945 | /* 80 */ |
2647 | { "joH", { Jv, BND, cond_jump_flag } }, |
2946 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2648 | { "jnoH", { Jv, BND, cond_jump_flag } }, |
2947 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, |
2649 | { "jbH", { Jv, BND, cond_jump_flag } }, |
2948 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, |
2650 | { "jaeH", { Jv, BND, cond_jump_flag } }, |
2949 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, |
2651 | { "jeH", { Jv, BND, cond_jump_flag } }, |
2950 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, |
2652 | { "jneH", { Jv, BND, cond_jump_flag } }, |
2951 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, |
2653 | { "jbeH", { Jv, BND, cond_jump_flag } }, |
2952 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, |
2654 | { "jaH", { Jv, BND, cond_jump_flag } }, |
2953 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, |
2655 | /* 88 */ |
2954 | /* 88 */ |
2656 | { "jsH", { Jv, BND, cond_jump_flag } }, |
2955 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2657 | { "jnsH", { Jv, BND, cond_jump_flag } }, |
2956 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, |
2658 | { "jpH", { Jv, BND, cond_jump_flag } }, |
2957 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, |
2659 | { "jnpH", { Jv, BND, cond_jump_flag } }, |
2958 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, |
2660 | { "jlH", { Jv, BND, cond_jump_flag } }, |
2959 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, |
2661 | { "jgeH", { Jv, BND, cond_jump_flag } }, |
2960 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, |
2662 | { "jleH", { Jv, BND, cond_jump_flag } }, |
2961 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, |
2663 | { "jgH", { Jv, BND, cond_jump_flag } }, |
2962 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, |
2664 | /* 90 */ |
2963 | /* 90 */ |
2665 | { "seto", { Eb } }, |
2964 | { "seto", { Eb }, 0 }, |
2666 | { "setno", { Eb } }, |
2965 | { "setno", { Eb }, 0 }, |
2667 | { "setb", { Eb } }, |
2966 | { "setb", { Eb }, 0 }, |
2668 | { "setae", { Eb } }, |
2967 | { "setae", { Eb }, 0 }, |
2669 | { "sete", { Eb } }, |
2968 | { "sete", { Eb }, 0 }, |
2670 | { "setne", { Eb } }, |
2969 | { "setne", { Eb }, 0 }, |
2671 | { "setbe", { Eb } }, |
2970 | { "setbe", { Eb }, 0 }, |
2672 | { "seta", { Eb } }, |
2971 | { "seta", { Eb }, 0 }, |
2673 | /* 98 */ |
2972 | /* 98 */ |
2674 | { "sets", { Eb } }, |
2973 | { "sets", { Eb }, 0 }, |
2675 | { "setns", { Eb } }, |
2974 | { "setns", { Eb }, 0 }, |
2676 | { "setp", { Eb } }, |
2975 | { "setp", { Eb }, 0 }, |
2677 | { "setnp", { Eb } }, |
2976 | { "setnp", { Eb }, 0 }, |
2678 | { "setl", { Eb } }, |
2977 | { "setl", { Eb }, 0 }, |
2679 | { "setge", { Eb } }, |
2978 | { "setge", { Eb }, 0 }, |
2680 | { "setle", { Eb } }, |
2979 | { "setle", { Eb }, 0 }, |
2681 | { "setg", { Eb } }, |
2980 | { "setg", { Eb }, 0 }, |
2682 | /* a0 */ |
2981 | /* a0 */ |
2683 | { "pushT", { fs } }, |
2982 | { "pushT", { fs }, 0 }, |
2684 | { "popT", { fs } }, |
2983 | { "popT", { fs }, 0 }, |
2685 | { "cpuid", { XX } }, |
2984 | { "cpuid", { XX }, 0 }, |
2686 | { "btS", { Ev, Gv } }, |
2985 | { "btS", { Ev, Gv }, 0 }, |
2687 | { "shldS", { Ev, Gv, Ib } }, |
2986 | { "shldS", { Ev, Gv, Ib }, 0 }, |
2688 | { "shldS", { Ev, Gv, CL } }, |
2987 | { "shldS", { Ev, Gv, CL }, 0 }, |
2689 | { REG_TABLE (REG_0FA6) }, |
2988 | { REG_TABLE (REG_0FA6) }, |
2690 | { REG_TABLE (REG_0FA7) }, |
2989 | { REG_TABLE (REG_0FA7) }, |
2691 | /* a8 */ |
2990 | /* a8 */ |
2692 | { "pushT", { gs } }, |
2991 | { "pushT", { gs }, 0 }, |
2693 | { "popT", { gs } }, |
2992 | { "popT", { gs }, 0 }, |
2694 | { "rsm", { XX } }, |
2993 | { "rsm", { XX }, 0 }, |
2695 | { "btsS", { Evh1, Gv } }, |
2994 | { "btsS", { Evh1, Gv }, 0 }, |
2696 | { "shrdS", { Ev, Gv, Ib } }, |
2995 | { "shrdS", { Ev, Gv, Ib }, 0 }, |
2697 | { "shrdS", { Ev, Gv, CL } }, |
2996 | { "shrdS", { Ev, Gv, CL }, 0 }, |
2698 | { REG_TABLE (REG_0FAE) }, |
2997 | { REG_TABLE (REG_0FAE) }, |
2699 | { "imulS", { Gv, Ev } }, |
2998 | { "imulS", { Gv, Ev }, 0 }, |
2700 | /* b0 */ |
2999 | /* b0 */ |
2701 | { "cmpxchgB", { Ebh1, Gb } }, |
3000 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2702 | { "cmpxchgS", { Evh1, Gv } }, |
3001 | { "cmpxchgS", { Evh1, Gv }, 0 }, |
2703 | { MOD_TABLE (MOD_0FB2) }, |
3002 | { MOD_TABLE (MOD_0FB2) }, |
2704 | { "btrS", { Evh1, Gv } }, |
3003 | { "btrS", { Evh1, Gv }, 0 }, |
2705 | { MOD_TABLE (MOD_0FB4) }, |
3004 | { MOD_TABLE (MOD_0FB4) }, |
2706 | { MOD_TABLE (MOD_0FB5) }, |
3005 | { MOD_TABLE (MOD_0FB5) }, |
2707 | { "movz{bR|x}", { Gv, Eb } }, |
3006 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2708 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ |
3007 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ |
2709 | /* b8 */ |
3008 | /* b8 */ |
2710 | { PREFIX_TABLE (PREFIX_0FB8) }, |
3009 | { PREFIX_TABLE (PREFIX_0FB8) }, |
2711 | { "ud1", { XX } }, |
3010 | { "ud1", { XX }, 0 }, |
2712 | { REG_TABLE (REG_0FBA) }, |
3011 | { REG_TABLE (REG_0FBA) }, |
2713 | { "btcS", { Evh1, Gv } }, |
3012 | { "btcS", { Evh1, Gv }, 0 }, |
2714 | { PREFIX_TABLE (PREFIX_0FBC) }, |
3013 | { PREFIX_TABLE (PREFIX_0FBC) }, |
2715 | { PREFIX_TABLE (PREFIX_0FBD) }, |
3014 | { PREFIX_TABLE (PREFIX_0FBD) }, |
2716 | { "movs{bR|x}", { Gv, Eb } }, |
3015 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2717 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ |
3016 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ |
2718 | /* c0 */ |
3017 | /* c0 */ |
2719 | { "xaddB", { Ebh1, Gb } }, |
3018 | { "xaddB", { Ebh1, Gb }, 0 }, |
2720 | { "xaddS", { Evh1, Gv } }, |
3019 | { "xaddS", { Evh1, Gv }, 0 }, |
2721 | { PREFIX_TABLE (PREFIX_0FC2) }, |
3020 | { PREFIX_TABLE (PREFIX_0FC2) }, |
2722 | { PREFIX_TABLE (PREFIX_0FC3) }, |
3021 | { MOD_TABLE (MOD_0FC3) }, |
2723 | { "pinsrw", { MX, Edqw, Ib } }, |
3022 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2724 | { "pextrw", { Gdq, MS, Ib } }, |
3023 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, |
2725 | { "shufpX", { XM, EXx, Ib } }, |
3024 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, |
2726 | { REG_TABLE (REG_0FC7) }, |
3025 | { REG_TABLE (REG_0FC7) }, |
2727 | /* c8 */ |
3026 | /* c8 */ |
2728 | { "bswap", { RMeAX } }, |
3027 | { "bswap", { RMeAX }, 0 }, |
2729 | { "bswap", { RMeCX } }, |
3028 | { "bswap", { RMeCX }, 0 }, |
2730 | { "bswap", { RMeDX } }, |
3029 | { "bswap", { RMeDX }, 0 }, |
2731 | { "bswap", { RMeBX } }, |
3030 | { "bswap", { RMeBX }, 0 }, |
2732 | { "bswap", { RMeSP } }, |
3031 | { "bswap", { RMeSP }, 0 }, |
2733 | { "bswap", { RMeBP } }, |
3032 | { "bswap", { RMeBP }, 0 }, |
2734 | { "bswap", { RMeSI } }, |
3033 | { "bswap", { RMeSI }, 0 }, |
2735 | { "bswap", { RMeDI } }, |
3034 | { "bswap", { RMeDI }, 0 }, |
2736 | /* d0 */ |
3035 | /* d0 */ |
2737 | { PREFIX_TABLE (PREFIX_0FD0) }, |
3036 | { PREFIX_TABLE (PREFIX_0FD0) }, |
2738 | { "psrlw", { MX, EM } }, |
3037 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2739 | { "psrld", { MX, EM } }, |
3038 | { "psrld", { MX, EM }, PREFIX_OPCODE }, |
2740 | { "psrlq", { MX, EM } }, |
3039 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, |
2741 | { "paddq", { MX, EM } }, |
3040 | { "paddq", { MX, EM }, PREFIX_OPCODE }, |
2742 | { "pmullw", { MX, EM } }, |
3041 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, |
2743 | { PREFIX_TABLE (PREFIX_0FD6) }, |
3042 | { PREFIX_TABLE (PREFIX_0FD6) }, |
2744 | { MOD_TABLE (MOD_0FD7) }, |
3043 | { MOD_TABLE (MOD_0FD7) }, |
2745 | /* d8 */ |
3044 | /* d8 */ |
2746 | { "psubusb", { MX, EM } }, |
3045 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2747 | { "psubusw", { MX, EM } }, |
3046 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, |
2748 | { "pminub", { MX, EM } }, |
3047 | { "pminub", { MX, EM }, PREFIX_OPCODE }, |
2749 | { "pand", { MX, EM } }, |
3048 | { "pand", { MX, EM }, PREFIX_OPCODE }, |
2750 | { "paddusb", { MX, EM } }, |
3049 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, |
2751 | { "paddusw", { MX, EM } }, |
3050 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, |
2752 | { "pmaxub", { MX, EM } }, |
3051 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, |
2753 | { "pandn", { MX, EM } }, |
3052 | { "pandn", { MX, EM }, PREFIX_OPCODE }, |
2754 | /* e0 */ |
3053 | /* e0 */ |
2755 | { "pavgb", { MX, EM } }, |
3054 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2756 | { "psraw", { MX, EM } }, |
3055 | { "psraw", { MX, EM }, PREFIX_OPCODE }, |
2757 | { "psrad", { MX, EM } }, |
3056 | { "psrad", { MX, EM }, PREFIX_OPCODE }, |
2758 | { "pavgw", { MX, EM } }, |
3057 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, |
2759 | { "pmulhuw", { MX, EM } }, |
3058 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, |
2760 | { "pmulhw", { MX, EM } }, |
3059 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, |
2761 | { PREFIX_TABLE (PREFIX_0FE6) }, |
3060 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2762 | { PREFIX_TABLE (PREFIX_0FE7) }, |
3061 | { PREFIX_TABLE (PREFIX_0FE7) }, |
2763 | /* e8 */ |
3062 | /* e8 */ |
2764 | { "psubsb", { MX, EM } }, |
3063 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2765 | { "psubsw", { MX, EM } }, |
3064 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, |
2766 | { "pminsw", { MX, EM } }, |
3065 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, |
2767 | { "por", { MX, EM } }, |
3066 | { "por", { MX, EM }, PREFIX_OPCODE }, |
2768 | { "paddsb", { MX, EM } }, |
3067 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, |
2769 | { "paddsw", { MX, EM } }, |
3068 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, |
2770 | { "pmaxsw", { MX, EM } }, |
3069 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, |
2771 | { "pxor", { MX, EM } }, |
3070 | { "pxor", { MX, EM }, PREFIX_OPCODE }, |
2772 | /* f0 */ |
3071 | /* f0 */ |
2773 | { PREFIX_TABLE (PREFIX_0FF0) }, |
3072 | { PREFIX_TABLE (PREFIX_0FF0) }, |
2774 | { "psllw", { MX, EM } }, |
3073 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2775 | { "pslld", { MX, EM } }, |
3074 | { "pslld", { MX, EM }, PREFIX_OPCODE }, |
2776 | { "psllq", { MX, EM } }, |
3075 | { "psllq", { MX, EM }, PREFIX_OPCODE }, |
2777 | { "pmuludq", { MX, EM } }, |
3076 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, |
2778 | { "pmaddwd", { MX, EM } }, |
3077 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, |
2779 | { "psadbw", { MX, EM } }, |
3078 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, |
2780 | { PREFIX_TABLE (PREFIX_0FF7) }, |
3079 | { PREFIX_TABLE (PREFIX_0FF7) }, |
2781 | /* f8 */ |
3080 | /* f8 */ |
2782 | { "psubb", { MX, EM } }, |
3081 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2783 | { "psubw", { MX, EM } }, |
3082 | { "psubw", { MX, EM }, PREFIX_OPCODE }, |
2784 | { "psubd", { MX, EM } }, |
3083 | { "psubd", { MX, EM }, PREFIX_OPCODE }, |
2785 | { "psubq", { MX, EM } }, |
3084 | { "psubq", { MX, EM }, PREFIX_OPCODE }, |
2786 | { "paddb", { MX, EM } }, |
3085 | { "paddb", { MX, EM }, PREFIX_OPCODE }, |
2787 | { "paddw", { MX, EM } }, |
3086 | { "paddw", { MX, EM }, PREFIX_OPCODE }, |
2788 | { "paddd", { MX, EM } }, |
3087 | { "paddd", { MX, EM }, PREFIX_OPCODE }, |
2789 | { Bad_Opcode }, |
3088 | { Bad_Opcode }, |
2790 | }; |
3089 | }; |
Line 2791... | Line 3090... | ||
2791 | 3090 | ||
2792 | static const unsigned char onebyte_has_modrm[256] = { |
3091 | static const unsigned char onebyte_has_modrm[256] = { |
Line 2840... | Line 3139... | ||
2840 | static char *mnemonicendp; |
3139 | static char *mnemonicendp; |
2841 | static char scratchbuf[100]; |
3140 | static char scratchbuf[100]; |
2842 | static unsigned char *start_codep; |
3141 | static unsigned char *start_codep; |
2843 | static unsigned char *insn_codep; |
3142 | static unsigned char *insn_codep; |
2844 | static unsigned char *codep; |
3143 | static unsigned char *codep; |
- | 3144 | static unsigned char *end_codep; |
|
2845 | static int last_lock_prefix; |
3145 | static int last_lock_prefix; |
2846 | static int last_repz_prefix; |
3146 | static int last_repz_prefix; |
2847 | static int last_repnz_prefix; |
3147 | static int last_repnz_prefix; |
2848 | static int last_data_prefix; |
3148 | static int last_data_prefix; |
2849 | static int last_addr_prefix; |
3149 | static int last_addr_prefix; |
2850 | static int last_rex_prefix; |
3150 | static int last_rex_prefix; |
2851 | static int last_seg_prefix; |
3151 | static int last_seg_prefix; |
- | 3152 | static int fwait_prefix; |
|
- | 3153 | /* The active segment register prefix. */ |
|
- | 3154 | static int active_seg_prefix; |
|
2852 | #define MAX_CODE_LENGTH 15 |
3155 | #define MAX_CODE_LENGTH 15 |
2853 | /* We can up to 14 prefixes since the maximum instruction length is |
3156 | /* We can up to 14 prefixes since the maximum instruction length is |
2854 | 15bytes. */ |
3157 | 15bytes. */ |
2855 | static int all_prefixes[MAX_CODE_LENGTH - 1]; |
3158 | static int all_prefixes[MAX_CODE_LENGTH - 1]; |
2856 | static disassemble_info *the_info; |
3159 | static disassemble_info *the_info; |
Line 3067... | Line 3370... | ||
3067 | }; |
3370 | }; |
Line 3068... | Line 3371... | ||
3068 | 3371 | ||
3069 | static const struct dis386 reg_table[][8] = { |
3372 | static const struct dis386 reg_table[][8] = { |
3070 | /* REG_80 */ |
3373 | /* REG_80 */ |
3071 | { |
3374 | { |
3072 | { "addA", { Ebh1, Ib } }, |
3375 | { "addA", { Ebh1, Ib }, 0 }, |
3073 | { "orA", { Ebh1, Ib } }, |
3376 | { "orA", { Ebh1, Ib }, 0 }, |
3074 | { "adcA", { Ebh1, Ib } }, |
3377 | { "adcA", { Ebh1, Ib }, 0 }, |
3075 | { "sbbA", { Ebh1, Ib } }, |
3378 | { "sbbA", { Ebh1, Ib }, 0 }, |
3076 | { "andA", { Ebh1, Ib } }, |
3379 | { "andA", { Ebh1, Ib }, 0 }, |
3077 | { "subA", { Ebh1, Ib } }, |
3380 | { "subA", { Ebh1, Ib }, 0 }, |
3078 | { "xorA", { Ebh1, Ib } }, |
3381 | { "xorA", { Ebh1, Ib }, 0 }, |
3079 | { "cmpA", { Eb, Ib } }, |
3382 | { "cmpA", { Eb, Ib }, 0 }, |
3080 | }, |
3383 | }, |
3081 | /* REG_81 */ |
3384 | /* REG_81 */ |
3082 | { |
3385 | { |
3083 | { "addQ", { Evh1, Iv } }, |
3386 | { "addQ", { Evh1, Iv }, 0 }, |
3084 | { "orQ", { Evh1, Iv } }, |
3387 | { "orQ", { Evh1, Iv }, 0 }, |
3085 | { "adcQ", { Evh1, Iv } }, |
3388 | { "adcQ", { Evh1, Iv }, 0 }, |
3086 | { "sbbQ", { Evh1, Iv } }, |
3389 | { "sbbQ", { Evh1, Iv }, 0 }, |
3087 | { "andQ", { Evh1, Iv } }, |
3390 | { "andQ", { Evh1, Iv }, 0 }, |
3088 | { "subQ", { Evh1, Iv } }, |
3391 | { "subQ", { Evh1, Iv }, 0 }, |
3089 | { "xorQ", { Evh1, Iv } }, |
3392 | { "xorQ", { Evh1, Iv }, 0 }, |
3090 | { "cmpQ", { Ev, Iv } }, |
3393 | { "cmpQ", { Ev, Iv }, 0 }, |
3091 | }, |
3394 | }, |
3092 | /* REG_82 */ |
3395 | /* REG_82 */ |
3093 | { |
3396 | { |
3094 | { "addQ", { Evh1, sIb } }, |
3397 | { "addQ", { Evh1, sIb }, 0 }, |
3095 | { "orQ", { Evh1, sIb } }, |
3398 | { "orQ", { Evh1, sIb }, 0 }, |
3096 | { "adcQ", { Evh1, sIb } }, |
3399 | { "adcQ", { Evh1, sIb }, 0 }, |
3097 | { "sbbQ", { Evh1, sIb } }, |
3400 | { "sbbQ", { Evh1, sIb }, 0 }, |
3098 | { "andQ", { Evh1, sIb } }, |
3401 | { "andQ", { Evh1, sIb }, 0 }, |
3099 | { "subQ", { Evh1, sIb } }, |
3402 | { "subQ", { Evh1, sIb }, 0 }, |
3100 | { "xorQ", { Evh1, sIb } }, |
3403 | { "xorQ", { Evh1, sIb }, 0 }, |
3101 | { "cmpQ", { Ev, sIb } }, |
3404 | { "cmpQ", { Ev, sIb }, 0 }, |
3102 | }, |
3405 | }, |
3103 | /* REG_8F */ |
3406 | /* REG_8F */ |
3104 | { |
3407 | { |
3105 | { "popU", { stackEv } }, |
3408 | { "popU", { stackEv }, 0 }, |
3106 | { XOP_8F_TABLE (XOP_09) }, |
3409 | { XOP_8F_TABLE (XOP_09) }, |
3107 | { Bad_Opcode }, |
3410 | { Bad_Opcode }, |
3108 | { Bad_Opcode }, |
3411 | { Bad_Opcode }, |
3109 | { Bad_Opcode }, |
3412 | { Bad_Opcode }, |
3110 | { XOP_8F_TABLE (XOP_09) }, |
3413 | { XOP_8F_TABLE (XOP_09) }, |
3111 | }, |
3414 | }, |
3112 | /* REG_C0 */ |
3415 | /* REG_C0 */ |
3113 | { |
3416 | { |
3114 | { "rolA", { Eb, Ib } }, |
3417 | { "rolA", { Eb, Ib }, 0 }, |
3115 | { "rorA", { Eb, Ib } }, |
3418 | { "rorA", { Eb, Ib }, 0 }, |
3116 | { "rclA", { Eb, Ib } }, |
3419 | { "rclA", { Eb, Ib }, 0 }, |
3117 | { "rcrA", { Eb, Ib } }, |
3420 | { "rcrA", { Eb, Ib }, 0 }, |
3118 | { "shlA", { Eb, Ib } }, |
3421 | { "shlA", { Eb, Ib }, 0 }, |
3119 | { "shrA", { Eb, Ib } }, |
3422 | { "shrA", { Eb, Ib }, 0 }, |
3120 | { Bad_Opcode }, |
3423 | { Bad_Opcode }, |
3121 | { "sarA", { Eb, Ib } }, |
3424 | { "sarA", { Eb, Ib }, 0 }, |
3122 | }, |
3425 | }, |
3123 | /* REG_C1 */ |
3426 | /* REG_C1 */ |
3124 | { |
3427 | { |
3125 | { "rolQ", { Ev, Ib } }, |
3428 | { "rolQ", { Ev, Ib }, 0 }, |
3126 | { "rorQ", { Ev, Ib } }, |
3429 | { "rorQ", { Ev, Ib }, 0 }, |
3127 | { "rclQ", { Ev, Ib } }, |
3430 | { "rclQ", { Ev, Ib }, 0 }, |
3128 | { "rcrQ", { Ev, Ib } }, |
3431 | { "rcrQ", { Ev, Ib }, 0 }, |
3129 | { "shlQ", { Ev, Ib } }, |
3432 | { "shlQ", { Ev, Ib }, 0 }, |
3130 | { "shrQ", { Ev, Ib } }, |
3433 | { "shrQ", { Ev, Ib }, 0 }, |
3131 | { Bad_Opcode }, |
3434 | { Bad_Opcode }, |
3132 | { "sarQ", { Ev, Ib } }, |
3435 | { "sarQ", { Ev, Ib }, 0 }, |
3133 | }, |
3436 | }, |
3134 | /* REG_C6 */ |
3437 | /* REG_C6 */ |
3135 | { |
3438 | { |
3136 | { "movA", { Ebh3, Ib } }, |
3439 | { "movA", { Ebh3, Ib }, 0 }, |
3137 | { Bad_Opcode }, |
3440 | { Bad_Opcode }, |
3138 | { Bad_Opcode }, |
3441 | { Bad_Opcode }, |
3139 | { Bad_Opcode }, |
3442 | { Bad_Opcode }, |
3140 | { Bad_Opcode }, |
3443 | { Bad_Opcode }, |
3141 | { Bad_Opcode }, |
3444 | { Bad_Opcode }, |
3142 | { Bad_Opcode }, |
3445 | { Bad_Opcode }, |
3143 | { MOD_TABLE (MOD_C6_REG_7) }, |
3446 | { MOD_TABLE (MOD_C6_REG_7) }, |
3144 | }, |
3447 | }, |
3145 | /* REG_C7 */ |
3448 | /* REG_C7 */ |
3146 | { |
3449 | { |
3147 | { "movQ", { Evh3, Iv } }, |
3450 | { "movQ", { Evh3, Iv }, 0 }, |
3148 | { Bad_Opcode }, |
3451 | { Bad_Opcode }, |
3149 | { Bad_Opcode }, |
3452 | { Bad_Opcode }, |
3150 | { Bad_Opcode }, |
3453 | { Bad_Opcode }, |
3151 | { Bad_Opcode }, |
3454 | { Bad_Opcode }, |
3152 | { Bad_Opcode }, |
3455 | { Bad_Opcode }, |
3153 | { Bad_Opcode }, |
3456 | { Bad_Opcode }, |
3154 | { MOD_TABLE (MOD_C7_REG_7) }, |
3457 | { MOD_TABLE (MOD_C7_REG_7) }, |
3155 | }, |
3458 | }, |
3156 | /* REG_D0 */ |
3459 | /* REG_D0 */ |
3157 | { |
3460 | { |
3158 | { "rolA", { Eb, I1 } }, |
3461 | { "rolA", { Eb, I1 }, 0 }, |
3159 | { "rorA", { Eb, I1 } }, |
3462 | { "rorA", { Eb, I1 }, 0 }, |
3160 | { "rclA", { Eb, I1 } }, |
3463 | { "rclA", { Eb, I1 }, 0 }, |
3161 | { "rcrA", { Eb, I1 } }, |
3464 | { "rcrA", { Eb, I1 }, 0 }, |
3162 | { "shlA", { Eb, I1 } }, |
3465 | { "shlA", { Eb, I1 }, 0 }, |
3163 | { "shrA", { Eb, I1 } }, |
3466 | { "shrA", { Eb, I1 }, 0 }, |
3164 | { Bad_Opcode }, |
3467 | { Bad_Opcode }, |
3165 | { "sarA", { Eb, I1 } }, |
3468 | { "sarA", { Eb, I1 }, 0 }, |
3166 | }, |
3469 | }, |
3167 | /* REG_D1 */ |
3470 | /* REG_D1 */ |
3168 | { |
3471 | { |
3169 | { "rolQ", { Ev, I1 } }, |
3472 | { "rolQ", { Ev, I1 }, 0 }, |
3170 | { "rorQ", { Ev, I1 } }, |
3473 | { "rorQ", { Ev, I1 }, 0 }, |
3171 | { "rclQ", { Ev, I1 } }, |
3474 | { "rclQ", { Ev, I1 }, 0 }, |
3172 | { "rcrQ", { Ev, I1 } }, |
3475 | { "rcrQ", { Ev, I1 }, 0 }, |
3173 | { "shlQ", { Ev, I1 } }, |
3476 | { "shlQ", { Ev, I1 }, 0 }, |
3174 | { "shrQ", { Ev, I1 } }, |
3477 | { "shrQ", { Ev, I1 }, 0 }, |
3175 | { Bad_Opcode }, |
3478 | { Bad_Opcode }, |
3176 | { "sarQ", { Ev, I1 } }, |
3479 | { "sarQ", { Ev, I1 }, 0 }, |
3177 | }, |
3480 | }, |
3178 | /* REG_D2 */ |
3481 | /* REG_D2 */ |
3179 | { |
3482 | { |
3180 | { "rolA", { Eb, CL } }, |
3483 | { "rolA", { Eb, CL }, 0 }, |
3181 | { "rorA", { Eb, CL } }, |
3484 | { "rorA", { Eb, CL }, 0 }, |
3182 | { "rclA", { Eb, CL } }, |
3485 | { "rclA", { Eb, CL }, 0 }, |
3183 | { "rcrA", { Eb, CL } }, |
3486 | { "rcrA", { Eb, CL }, 0 }, |
3184 | { "shlA", { Eb, CL } }, |
3487 | { "shlA", { Eb, CL }, 0 }, |
3185 | { "shrA", { Eb, CL } }, |
3488 | { "shrA", { Eb, CL }, 0 }, |
3186 | { Bad_Opcode }, |
3489 | { Bad_Opcode }, |
3187 | { "sarA", { Eb, CL } }, |
3490 | { "sarA", { Eb, CL }, 0 }, |
3188 | }, |
3491 | }, |
3189 | /* REG_D3 */ |
3492 | /* REG_D3 */ |
3190 | { |
3493 | { |
3191 | { "rolQ", { Ev, CL } }, |
3494 | { "rolQ", { Ev, CL }, 0 }, |
3192 | { "rorQ", { Ev, CL } }, |
3495 | { "rorQ", { Ev, CL }, 0 }, |
3193 | { "rclQ", { Ev, CL } }, |
3496 | { "rclQ", { Ev, CL }, 0 }, |
3194 | { "rcrQ", { Ev, CL } }, |
3497 | { "rcrQ", { Ev, CL }, 0 }, |
3195 | { "shlQ", { Ev, CL } }, |
3498 | { "shlQ", { Ev, CL }, 0 }, |
3196 | { "shrQ", { Ev, CL } }, |
3499 | { "shrQ", { Ev, CL }, 0 }, |
3197 | { Bad_Opcode }, |
3500 | { Bad_Opcode }, |
3198 | { "sarQ", { Ev, CL } }, |
3501 | { "sarQ", { Ev, CL }, 0 }, |
3199 | }, |
3502 | }, |
3200 | /* REG_F6 */ |
3503 | /* REG_F6 */ |
3201 | { |
3504 | { |
3202 | { "testA", { Eb, Ib } }, |
3505 | { "testA", { Eb, Ib }, 0 }, |
3203 | { Bad_Opcode }, |
3506 | { Bad_Opcode }, |
3204 | { "notA", { Ebh1 } }, |
3507 | { "notA", { Ebh1 }, 0 }, |
3205 | { "negA", { Ebh1 } }, |
3508 | { "negA", { Ebh1 }, 0 }, |
3206 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ |
3509 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ |
3207 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ |
3510 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ |
3208 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ |
3511 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ |
3209 | { "idivA", { Eb } }, /* and idiv for consistency. */ |
3512 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ |
3210 | }, |
3513 | }, |
3211 | /* REG_F7 */ |
3514 | /* REG_F7 */ |
3212 | { |
3515 | { |
3213 | { "testQ", { Ev, Iv } }, |
3516 | { "testQ", { Ev, Iv }, 0 }, |
3214 | { Bad_Opcode }, |
3517 | { Bad_Opcode }, |
3215 | { "notQ", { Evh1 } }, |
3518 | { "notQ", { Evh1 }, 0 }, |
3216 | { "negQ", { Evh1 } }, |
3519 | { "negQ", { Evh1 }, 0 }, |
3217 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ |
3520 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ |
3218 | { "imulQ", { Ev } }, |
3521 | { "imulQ", { Ev }, 0 }, |
3219 | { "divQ", { Ev } }, |
3522 | { "divQ", { Ev }, 0 }, |
3220 | { "idivQ", { Ev } }, |
3523 | { "idivQ", { Ev }, 0 }, |
3221 | }, |
3524 | }, |
3222 | /* REG_FE */ |
3525 | /* REG_FE */ |
3223 | { |
3526 | { |
3224 | { "incA", { Ebh1 } }, |
3527 | { "incA", { Ebh1 }, 0 }, |
3225 | { "decA", { Ebh1 } }, |
3528 | { "decA", { Ebh1 }, 0 }, |
3226 | }, |
3529 | }, |
3227 | /* REG_FF */ |
3530 | /* REG_FF */ |
3228 | { |
3531 | { |
3229 | { "incQ", { Evh1 } }, |
3532 | { "incQ", { Evh1 }, 0 }, |
3230 | { "decQ", { Evh1 } }, |
3533 | { "decQ", { Evh1 }, 0 }, |
3231 | { "call{T|}", { indirEv, BND } }, |
3534 | { "call{T|}", { indirEv, BND }, 0 }, |
3232 | { "Jcall{T|}", { indirEp } }, |
3535 | { MOD_TABLE (MOD_FF_REG_3) }, |
3233 | { "jmp{T|}", { indirEv, BND } }, |
3536 | { "jmp{T|}", { indirEv, BND }, 0 }, |
3234 | { "Jjmp{T|}", { indirEp } }, |
3537 | { MOD_TABLE (MOD_FF_REG_5) }, |
3235 | { "pushU", { stackEv } }, |
3538 | { "pushU", { stackEv }, 0 }, |
3236 | { Bad_Opcode }, |
3539 | { Bad_Opcode }, |
3237 | }, |
3540 | }, |
3238 | /* REG_0F00 */ |
3541 | /* REG_0F00 */ |
3239 | { |
3542 | { |
3240 | { "sldtD", { Sv } }, |
3543 | { "sldtD", { Sv }, 0 }, |
3241 | { "strD", { Sv } }, |
3544 | { "strD", { Sv }, 0 }, |
3242 | { "lldt", { Ew } }, |
3545 | { "lldt", { Ew }, 0 }, |
3243 | { "ltr", { Ew } }, |
3546 | { "ltr", { Ew }, 0 }, |
3244 | { "verr", { Ew } }, |
3547 | { "verr", { Ew }, 0 }, |
3245 | { "verw", { Ew } }, |
3548 | { "verw", { Ew }, 0 }, |
3246 | { Bad_Opcode }, |
3549 | { Bad_Opcode }, |
3247 | { Bad_Opcode }, |
3550 | { Bad_Opcode }, |
3248 | }, |
3551 | }, |
3249 | /* REG_0F01 */ |
3552 | /* REG_0F01 */ |
3250 | { |
3553 | { |
3251 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3554 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3252 | { MOD_TABLE (MOD_0F01_REG_1) }, |
3555 | { MOD_TABLE (MOD_0F01_REG_1) }, |
3253 | { MOD_TABLE (MOD_0F01_REG_2) }, |
3556 | { MOD_TABLE (MOD_0F01_REG_2) }, |
3254 | { MOD_TABLE (MOD_0F01_REG_3) }, |
3557 | { MOD_TABLE (MOD_0F01_REG_3) }, |
3255 | { "smswD", { Sv } }, |
3558 | { "smswD", { Sv }, 0 }, |
3256 | { Bad_Opcode }, |
3559 | { MOD_TABLE (MOD_0F01_REG_5) }, |
3257 | { "lmsw", { Ew } }, |
3560 | { "lmsw", { Ew }, 0 }, |
3258 | { MOD_TABLE (MOD_0F01_REG_7) }, |
3561 | { MOD_TABLE (MOD_0F01_REG_7) }, |
3259 | }, |
3562 | }, |
3260 | /* REG_0F0D */ |
3563 | /* REG_0F0D */ |
3261 | { |
3564 | { |
3262 | { "prefetch", { Mb } }, |
3565 | { "prefetch", { Mb }, 0 }, |
3263 | { "prefetchw", { Mb } }, |
3566 | { "prefetchw", { Mb }, 0 }, |
3264 | { "prefetchwt1", { Mb } }, |
3567 | { "prefetchwt1", { Mb }, 0 }, |
3265 | { "prefetch", { Mb } }, |
3568 | { "prefetch", { Mb }, 0 }, |
3266 | { "prefetch", { Mb } }, |
3569 | { "prefetch", { Mb }, 0 }, |
3267 | { "prefetch", { Mb } }, |
3570 | { "prefetch", { Mb }, 0 }, |
3268 | { "prefetch", { Mb } }, |
3571 | { "prefetch", { Mb }, 0 }, |
3269 | { "prefetch", { Mb } }, |
3572 | { "prefetch", { Mb }, 0 }, |
3270 | }, |
3573 | }, |
3271 | /* REG_0F18 */ |
3574 | /* REG_0F18 */ |
3272 | { |
3575 | { |
3273 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3576 | { MOD_TABLE (MOD_0F18_REG_0) }, |
Line 3310... | Line 3613... | ||
3310 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3613 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3311 | { MOD_TABLE (MOD_0F73_REG_7) }, |
3614 | { MOD_TABLE (MOD_0F73_REG_7) }, |
3312 | }, |
3615 | }, |
3313 | /* REG_0FA6 */ |
3616 | /* REG_0FA6 */ |
3314 | { |
3617 | { |
3315 | { "montmul", { { OP_0f07, 0 } } }, |
3618 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3316 | { "xsha1", { { OP_0f07, 0 } } }, |
3619 | { "xsha1", { { OP_0f07, 0 } }, 0 }, |
3317 | { "xsha256", { { OP_0f07, 0 } } }, |
3620 | { "xsha256", { { OP_0f07, 0 } }, 0 }, |
3318 | }, |
3621 | }, |
3319 | /* REG_0FA7 */ |
3622 | /* REG_0FA7 */ |
3320 | { |
3623 | { |
3321 | { "xstore-rng", { { OP_0f07, 0 } } }, |
3624 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3322 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, |
3625 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, |
3323 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, |
3626 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, |
3324 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, |
3627 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, |
3325 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, |
3628 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, |
3326 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, |
3629 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, |
3327 | }, |
3630 | }, |
3328 | /* REG_0FAE */ |
3631 | /* REG_0FAE */ |
3329 | { |
3632 | { |
3330 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3633 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3331 | { MOD_TABLE (MOD_0FAE_REG_1) }, |
3634 | { MOD_TABLE (MOD_0FAE_REG_1) }, |
Line 3340... | Line 3643... | ||
3340 | { |
3643 | { |
3341 | { Bad_Opcode }, |
3644 | { Bad_Opcode }, |
3342 | { Bad_Opcode }, |
3645 | { Bad_Opcode }, |
3343 | { Bad_Opcode }, |
3646 | { Bad_Opcode }, |
3344 | { Bad_Opcode }, |
3647 | { Bad_Opcode }, |
3345 | { "btQ", { Ev, Ib } }, |
3648 | { "btQ", { Ev, Ib }, 0 }, |
3346 | { "btsQ", { Evh1, Ib } }, |
3649 | { "btsQ", { Evh1, Ib }, 0 }, |
3347 | { "btrQ", { Evh1, Ib } }, |
3650 | { "btrQ", { Evh1, Ib }, 0 }, |
3348 | { "btcQ", { Evh1, Ib } }, |
3651 | { "btcQ", { Evh1, Ib }, 0 }, |
3349 | }, |
3652 | }, |
3350 | /* REG_0FC7 */ |
3653 | /* REG_0FC7 */ |
3351 | { |
3654 | { |
3352 | { Bad_Opcode }, |
3655 | { Bad_Opcode }, |
3353 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
3656 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
3354 | { Bad_Opcode }, |
- | |
3355 | { Bad_Opcode }, |
- | |
3356 | { Bad_Opcode }, |
- | |
3357 | { Bad_Opcode }, |
3657 | { Bad_Opcode }, |
- | 3658 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
|
- | 3659 | { MOD_TABLE (MOD_0FC7_REG_4) }, |
|
- | 3660 | { MOD_TABLE (MOD_0FC7_REG_5) }, |
|
3358 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3661 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3359 | { MOD_TABLE (MOD_0FC7_REG_7) }, |
3662 | { MOD_TABLE (MOD_0FC7_REG_7) }, |
3360 | }, |
3663 | }, |
3361 | /* REG_VEX_0F71 */ |
3664 | /* REG_VEX_0F71 */ |
3362 | { |
3665 | { |
Line 3403... | Line 3706... | ||
3403 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, |
3706 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, |
3404 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, |
3707 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, |
3405 | }, |
3708 | }, |
3406 | /* REG_XOP_LWPCB */ |
3709 | /* REG_XOP_LWPCB */ |
3407 | { |
3710 | { |
3408 | { "llwpcb", { { OP_LWPCB_E, 0 } } }, |
3711 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3409 | { "slwpcb", { { OP_LWPCB_E, 0 } } }, |
3712 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3410 | }, |
3713 | }, |
3411 | /* REG_XOP_LWP */ |
3714 | /* REG_XOP_LWP */ |
3412 | { |
3715 | { |
3413 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, |
3716 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3414 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, |
3717 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3415 | }, |
3718 | }, |
3416 | /* REG_XOP_TBM_01 */ |
3719 | /* REG_XOP_TBM_01 */ |
3417 | { |
3720 | { |
3418 | { Bad_Opcode }, |
3721 | { Bad_Opcode }, |
3419 | { "blcfill", { { OP_LWP_E, 0 }, Ev } }, |
3722 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3420 | { "blsfill", { { OP_LWP_E, 0 }, Ev } }, |
3723 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3421 | { "blcs", { { OP_LWP_E, 0 }, Ev } }, |
3724 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3422 | { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, |
3725 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3423 | { "blcic", { { OP_LWP_E, 0 }, Ev } }, |
3726 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3424 | { "blsic", { { OP_LWP_E, 0 }, Ev } }, |
3727 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3425 | { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, |
3728 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3426 | }, |
3729 | }, |
3427 | /* REG_XOP_TBM_02 */ |
3730 | /* REG_XOP_TBM_02 */ |
3428 | { |
3731 | { |
3429 | { Bad_Opcode }, |
3732 | { Bad_Opcode }, |
3430 | { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, |
3733 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3431 | { Bad_Opcode }, |
3734 | { Bad_Opcode }, |
3432 | { Bad_Opcode }, |
3735 | { Bad_Opcode }, |
3433 | { Bad_Opcode }, |
3736 | { Bad_Opcode }, |
3434 | { Bad_Opcode }, |
3737 | { Bad_Opcode }, |
3435 | { "blci", { { OP_LWP_E, 0 }, Ev } }, |
3738 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3436 | }, |
3739 | }, |
3437 | #define NEED_REG_TABLE |
3740 | #define NEED_REG_TABLE |
3438 | #include "i386-dis-evex.h" |
3741 | #include "i386-dis-evex.h" |
3439 | #undef NEED_REG_TABLE |
3742 | #undef NEED_REG_TABLE |
3440 | }; |
3743 | }; |
Line 3441... | Line 3744... | ||
3441 | 3744 | ||
3442 | static const struct dis386 prefix_table[][4] = { |
3745 | static const struct dis386 prefix_table[][4] = { |
3443 | /* PREFIX_90 */ |
3746 | /* PREFIX_90 */ |
3444 | { |
3747 | { |
3445 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
3748 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3446 | { "pause", { XX } }, |
3749 | { "pause", { XX }, 0 }, |
- | 3750 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
|
3447 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
3751 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
Line 3448... | Line 3752... | ||
3448 | }, |
3752 | }, |
3449 | 3753 | ||
3450 | /* PREFIX_0F10 */ |
3754 | /* PREFIX_0F10 */ |
3451 | { |
3755 | { |
3452 | { "movups", { XM, EXx } }, |
3756 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3453 | { "movss", { XM, EXd } }, |
3757 | { "movss", { XM, EXd }, PREFIX_OPCODE }, |
3454 | { "movupd", { XM, EXx } }, |
3758 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, |
Line 3455... | Line 3759... | ||
3455 | { "movsd", { XM, EXq } }, |
3759 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, |
3456 | }, |
3760 | }, |
3457 | 3761 | ||
3458 | /* PREFIX_0F11 */ |
3762 | /* PREFIX_0F11 */ |
3459 | { |
3763 | { |
3460 | { "movups", { EXxS, XM } }, |
3764 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3461 | { "movss", { EXdS, XM } }, |
3765 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, |
Line 3462... | Line 3766... | ||
3462 | { "movupd", { EXxS, XM } }, |
3766 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, |
3463 | { "movsd", { EXqS, XM } }, |
3767 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, |
3464 | }, |
3768 | }, |
3465 | 3769 | ||
3466 | /* PREFIX_0F12 */ |
3770 | /* PREFIX_0F12 */ |
3467 | { |
3771 | { |
3468 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
3772 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
Line 3469... | Line 3773... | ||
3469 | { "movsldup", { XM, EXx } }, |
3773 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3470 | { "movlpd", { XM, EXq } }, |
3774 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, |
3471 | { "movddup", { XM, EXq } }, |
3775 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
3472 | }, |
3776 | }, |
3473 | 3777 | ||
3474 | /* PREFIX_0F16 */ |
3778 | /* PREFIX_0F16 */ |
Line 3475... | Line 3779... | ||
3475 | { |
3779 | { |
3476 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
3780 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
3477 | { "movshdup", { XM, EXx } }, |
3781 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3478 | { "movhpd", { XM, EXq } }, |
3782 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, |
3479 | }, |
3783 | }, |
3480 | 3784 | ||
3481 | /* PREFIX_0F1A */ |
3785 | /* PREFIX_0F1A */ |
Line 3482... | Line 3786... | ||
3482 | { |
3786 | { |
3483 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, |
3787 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, |
3484 | { "bndcl", { Gbnd, Ev_bnd } }, |
3788 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3485 | { "bndmov", { Gbnd, Ebnd } }, |
3789 | { "bndmov", { Gbnd, Ebnd }, 0 }, |
3486 | { "bndcu", { Gbnd, Ev_bnd } }, |
3790 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, |
3487 | }, |
3791 | }, |
3488 | 3792 | ||
Line 3489... | Line 3793... | ||
3489 | /* PREFIX_0F1B */ |
3793 | /* PREFIX_0F1B */ |
3490 | { |
3794 | { |
3491 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, |
3795 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, |
3492 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, |
3796 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, |
3493 | { "bndmov", { Ebnd, Gbnd } }, |
3797 | { "bndmov", { Ebnd, Gbnd }, 0 }, |
3494 | { "bndcn", { Gbnd, Ev_bnd } }, |
3798 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
3495 | }, |
3799 | }, |
Line 3496... | Line 3800... | ||
3496 | 3800 | ||
3497 | /* PREFIX_0F2A */ |
3801 | /* PREFIX_0F2A */ |
3498 | { |
3802 | { |
Line 3510... | Line 3814... | ||
3510 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, |
3814 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, |
3511 | }, |
3815 | }, |
Line 3512... | Line 3816... | ||
3512 | 3816 | ||
3513 | /* PREFIX_0F2C */ |
3817 | /* PREFIX_0F2C */ |
3514 | { |
3818 | { |
3515 | { "cvttps2pi", { MXC, EXq } }, |
3819 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3516 | { "cvttss2siY", { Gv, EXd } }, |
3820 | { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, |
3517 | { "cvttpd2pi", { MXC, EXx } }, |
3821 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
3518 | { "cvttsd2siY", { Gv, EXq } }, |
3822 | { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, |
Line 3519... | Line 3823... | ||
3519 | }, |
3823 | }, |
3520 | 3824 | ||
3521 | /* PREFIX_0F2D */ |
3825 | /* PREFIX_0F2D */ |
3522 | { |
3826 | { |
3523 | { "cvtps2pi", { MXC, EXq } }, |
3827 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3524 | { "cvtss2siY", { Gv, EXd } }, |
3828 | { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, |
3525 | { "cvtpd2pi", { MXC, EXx } }, |
3829 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
Line 3526... | Line 3830... | ||
3526 | { "cvtsd2siY", { Gv, EXq } }, |
3830 | { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, |
3527 | }, |
3831 | }, |
3528 | 3832 | ||
3529 | /* PREFIX_0F2E */ |
3833 | /* PREFIX_0F2E */ |
3530 | { |
3834 | { |
3531 | { "ucomiss",{ XM, EXd } }, |
3835 | { "ucomiss",{ XM, EXd }, 0 }, |
Line 3532... | Line 3836... | ||
3532 | { Bad_Opcode }, |
3836 | { Bad_Opcode }, |
3533 | { "ucomisd",{ XM, EXq } }, |
3837 | { "ucomisd",{ XM, EXq }, 0 }, |
3534 | }, |
3838 | }, |
3535 | 3839 | ||
3536 | /* PREFIX_0F2F */ |
3840 | /* PREFIX_0F2F */ |
3537 | { |
3841 | { |
Line 3538... | Line 3842... | ||
3538 | { "comiss", { XM, EXd } }, |
3842 | { "comiss", { XM, EXd }, 0 }, |
3539 | { Bad_Opcode }, |
3843 | { Bad_Opcode }, |
3540 | { "comisd", { XM, EXq } }, |
3844 | { "comisd", { XM, EXq }, 0 }, |
3541 | }, |
3845 | }, |
3542 | 3846 | ||
3543 | /* PREFIX_0F51 */ |
3847 | /* PREFIX_0F51 */ |
3544 | { |
3848 | { |
Line 3545... | Line 3849... | ||
3545 | { "sqrtps", { XM, EXx } }, |
3849 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3546 | { "sqrtss", { XM, EXd } }, |
3850 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, |
3547 | { "sqrtpd", { XM, EXx } }, |
3851 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, |
3548 | { "sqrtsd", { XM, EXq } }, |
3852 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, |
3549 | }, |
3853 | }, |
Line 3550... | Line 3854... | ||
3550 | 3854 | ||
3551 | /* PREFIX_0F52 */ |
3855 | /* PREFIX_0F52 */ |
3552 | { |
3856 | { |
3553 | { "rsqrtps",{ XM, EXx } }, |
3857 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3554 | { "rsqrtss",{ XM, EXd } }, |
3858 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, |
Line 3555... | Line 3859... | ||
3555 | }, |
3859 | }, |
3556 | 3860 | ||
3557 | /* PREFIX_0F53 */ |
3861 | /* PREFIX_0F53 */ |
3558 | { |
3862 | { |
3559 | { "rcpps", { XM, EXx } }, |
3863 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3560 | { "rcpss", { XM, EXd } }, |
3864 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, |
3561 | }, |
3865 | }, |
Line 3562... | Line 3866... | ||
3562 | 3866 | ||
3563 | /* PREFIX_0F58 */ |
3867 | /* PREFIX_0F58 */ |
3564 | { |
3868 | { |
3565 | { "addps", { XM, EXx } }, |
3869 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3566 | { "addss", { XM, EXd } }, |
3870 | { "addss", { XM, EXd }, PREFIX_OPCODE }, |
3567 | { "addpd", { XM, EXx } }, |
3871 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, |
3568 | { "addsd", { XM, EXq } }, |
3872 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, |
Line 3569... | Line 3873... | ||
3569 | }, |
3873 | }, |
3570 | 3874 | ||
3571 | /* PREFIX_0F59 */ |
3875 | /* PREFIX_0F59 */ |
3572 | { |
3876 | { |
3573 | { "mulps", { XM, EXx } }, |
3877 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3574 | { "mulss", { XM, EXd } }, |
3878 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, |
3575 | { "mulpd", { XM, EXx } }, |
3879 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, |
Line 3576... | Line 3880... | ||
3576 | { "mulsd", { XM, EXq } }, |
3880 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, |
3577 | }, |
3881 | }, |
3578 | 3882 | ||
3579 | /* PREFIX_0F5A */ |
3883 | /* PREFIX_0F5A */ |
3580 | { |
3884 | { |
3581 | { "cvtps2pd", { XM, EXq } }, |
3885 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
Line 3582... | Line 3886... | ||
3582 | { "cvtss2sd", { XM, EXd } }, |
3886 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, |
3583 | { "cvtpd2ps", { XM, EXx } }, |
3887 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, |
3584 | { "cvtsd2ss", { XM, EXq } }, |
3888 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, |
3585 | }, |
3889 | }, |
3586 | 3890 | ||
3587 | /* PREFIX_0F5B */ |
3891 | /* PREFIX_0F5B */ |
3588 | { |
3892 | { |
Line 3589... | Line 3893... | ||
3589 | { "cvtdq2ps", { XM, EXx } }, |
3893 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3590 | { "cvttps2dq", { XM, EXx } }, |
3894 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, |
3591 | { "cvtps2dq", { XM, EXx } }, |
3895 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, |
3592 | }, |
3896 | }, |
3593 | 3897 | ||
3594 | /* PREFIX_0F5C */ |
3898 | /* PREFIX_0F5C */ |
3595 | { |
3899 | { |
Line 3596... | Line 3900... | ||
3596 | { "subps", { XM, EXx } }, |
3900 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3597 | { "subss", { XM, EXd } }, |
3901 | { "subss", { XM, EXd }, PREFIX_OPCODE }, |
3598 | { "subpd", { XM, EXx } }, |
3902 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, |
3599 | { "subsd", { XM, EXq } }, |
3903 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, |
3600 | }, |
3904 | }, |
3601 | 3905 | ||
3602 | /* PREFIX_0F5D */ |
3906 | /* PREFIX_0F5D */ |
Line 3603... | Line 3907... | ||
3603 | { |
3907 | { |
3604 | { "minps", { XM, EXx } }, |
3908 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3605 | { "minss", { XM, EXd } }, |
3909 | { "minss", { XM, EXd }, PREFIX_OPCODE }, |
3606 | { "minpd", { XM, EXx } }, |
3910 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, |
3607 | { "minsd", { XM, EXq } }, |
3911 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, |
3608 | }, |
3912 | }, |
3609 | 3913 | ||
Line 3610... | Line 3914... | ||
3610 | /* PREFIX_0F5E */ |
3914 | /* PREFIX_0F5E */ |
3611 | { |
3915 | { |
3612 | { "divps", { XM, EXx } }, |
3916 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3613 | { "divss", { XM, EXd } }, |
3917 | { "divss", { XM, EXd }, PREFIX_OPCODE }, |
3614 | { "divpd", { XM, EXx } }, |
3918 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, |
3615 | { "divsd", { XM, EXq } }, |
3919 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, |
Line 3616... | Line 3920... | ||
3616 | }, |
3920 | }, |
3617 | 3921 | ||
3618 | /* PREFIX_0F5F */ |
3922 | /* PREFIX_0F5F */ |
3619 | { |
3923 | { |
3620 | { "maxps", { XM, EXx } }, |
3924 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3621 | { "maxss", { XM, EXd } }, |
3925 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, |
Line 3622... | Line 3926... | ||
3622 | { "maxpd", { XM, EXx } }, |
3926 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, |
3623 | { "maxsd", { XM, EXq } }, |
3927 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, |
3624 | }, |
3928 | }, |
3625 | 3929 | ||
3626 | /* PREFIX_0F60 */ |
3930 | /* PREFIX_0F60 */ |
3627 | { |
3931 | { |
Line 3628... | Line 3932... | ||
3628 | { "punpcklbw",{ MX, EMd } }, |
3932 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
3629 | { Bad_Opcode }, |
3933 | { Bad_Opcode }, |
3630 | { "punpcklbw",{ MX, EMx } }, |
3934 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
3631 | }, |
3935 | }, |
3632 | 3936 | ||
3633 | /* PREFIX_0F61 */ |
3937 | /* PREFIX_0F61 */ |
Line 3634... | Line 3938... | ||
3634 | { |
3938 | { |
3635 | { "punpcklwd",{ MX, EMd } }, |
3939 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
3636 | { Bad_Opcode }, |
3940 | { Bad_Opcode }, |
3637 | { "punpcklwd",{ MX, EMx } }, |
3941 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
3638 | }, |
3942 | }, |
3639 | 3943 | ||
Line 3640... | Line 3944... | ||
3640 | /* PREFIX_0F62 */ |
3944 | /* PREFIX_0F62 */ |
3641 | { |
3945 | { |
3642 | { "punpckldq",{ MX, EMd } }, |
3946 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
3643 | { Bad_Opcode }, |
3947 | { Bad_Opcode }, |
3644 | { "punpckldq",{ MX, EMx } }, |
3948 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
3645 | }, |
3949 | }, |
Line 3646... | Line 3950... | ||
3646 | 3950 | ||
3647 | /* PREFIX_0F6C */ |
3951 | /* PREFIX_0F6C */ |
3648 | { |
3952 | { |
3649 | { Bad_Opcode }, |
3953 | { Bad_Opcode }, |
3650 | { Bad_Opcode }, |
3954 | { Bad_Opcode }, |
3651 | { "punpcklqdq", { XM, EXx } }, |
3955 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
3652 | }, |
3956 | }, |
Line 3653... | Line 3957... | ||
3653 | 3957 | ||
3654 | /* PREFIX_0F6D */ |
3958 | /* PREFIX_0F6D */ |
3655 | { |
3959 | { |
3656 | { Bad_Opcode }, |
3960 | { Bad_Opcode }, |
3657 | { Bad_Opcode }, |
3961 | { Bad_Opcode }, |
3658 | { "punpckhqdq", { XM, EXx } }, |
3962 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
Line 3659... | Line 3963... | ||
3659 | }, |
3963 | }, |
3660 | 3964 | ||
3661 | /* PREFIX_0F6F */ |
3965 | /* PREFIX_0F6F */ |
3662 | { |
3966 | { |
3663 | { "movq", { MX, EM } }, |
3967 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3664 | { "movdqu", { XM, EXx } }, |
3968 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, |
Line 3665... | Line 3969... | ||
3665 | { "movdqa", { XM, EXx } }, |
3969 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, |
3666 | }, |
3970 | }, |
3667 | 3971 | ||
3668 | /* PREFIX_0F70 */ |
3972 | /* PREFIX_0F70 */ |
3669 | { |
3973 | { |
3670 | { "pshufw", { MX, EM, Ib } }, |
3974 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3671 | { "pshufhw",{ XM, EXx, Ib } }, |
3975 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, |
Line 3672... | Line 3976... | ||
3672 | { "pshufd", { XM, EXx, Ib } }, |
3976 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
3673 | { "pshuflw",{ XM, EXx, Ib } }, |
3977 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, |
3674 | }, |
3978 | }, |
3675 | 3979 | ||
3676 | /* PREFIX_0F73_REG_3 */ |
3980 | /* PREFIX_0F73_REG_3 */ |
3677 | { |
3981 | { |
3678 | { Bad_Opcode }, |
3982 | { Bad_Opcode }, |
Line 3679... | Line 3983... | ||
3679 | { Bad_Opcode }, |
3983 | { Bad_Opcode }, |
3680 | { "psrldq", { XS, Ib } }, |
3984 | { "psrldq", { XS, Ib }, 0 }, |
3681 | }, |
3985 | }, |
3682 | 3986 | ||
3683 | /* PREFIX_0F73_REG_7 */ |
3987 | /* PREFIX_0F73_REG_7 */ |
3684 | { |
3988 | { |
3685 | { Bad_Opcode }, |
3989 | { Bad_Opcode }, |
Line 3686... | Line 3990... | ||
3686 | { Bad_Opcode }, |
3990 | { Bad_Opcode }, |
3687 | { "pslldq", { XS, Ib } }, |
3991 | { "pslldq", { XS, Ib }, 0 }, |
3688 | }, |
3992 | }, |
3689 | 3993 | ||
3690 | /* PREFIX_0F78 */ |
3994 | /* PREFIX_0F78 */ |
3691 | { |
3995 | { |
3692 | {"vmread", { Em, Gm } }, |
3996 | {"vmread", { Em, Gm }, 0 }, |
Line 3693... | Line 3997... | ||
3693 | { Bad_Opcode }, |
3997 | { Bad_Opcode }, |
3694 | {"extrq", { XS, Ib, Ib } }, |
3998 | {"extrq", { XS, Ib, Ib }, 0 }, |
3695 | {"insertq", { XM, XS, Ib, Ib } }, |
3999 | {"insertq", { XM, XS, Ib, Ib }, 0 }, |
3696 | }, |
4000 | }, |
3697 | 4001 | ||
3698 | /* PREFIX_0F79 */ |
4002 | /* PREFIX_0F79 */ |
Line 3699... | Line 4003... | ||
3699 | { |
4003 | { |
3700 | {"vmwrite", { Gm, Em } }, |
4004 | {"vmwrite", { Gm, Em }, 0 }, |
3701 | { Bad_Opcode }, |
4005 | { Bad_Opcode }, |
3702 | {"extrq", { XM, XS } }, |
4006 | {"extrq", { XM, XS }, 0 }, |
3703 | {"insertq", { XM, XS } }, |
4007 | {"insertq", { XM, XS }, 0 }, |
3704 | }, |
4008 | }, |
Line 3705... | Line 4009... | ||
3705 | 4009 | ||
3706 | /* PREFIX_0F7C */ |
4010 | /* PREFIX_0F7C */ |
3707 | { |
4011 | { |
3708 | { Bad_Opcode }, |
4012 | { Bad_Opcode }, |
3709 | { Bad_Opcode }, |
4013 | { Bad_Opcode }, |
Line 3710... | Line 4014... | ||
3710 | { "haddpd", { XM, EXx } }, |
4014 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3711 | { "haddps", { XM, EXx } }, |
4015 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, |
3712 | }, |
4016 | }, |
3713 | 4017 | ||
3714 | /* PREFIX_0F7D */ |
4018 | /* PREFIX_0F7D */ |
Line 3715... | Line 4019... | ||
3715 | { |
4019 | { |
3716 | { Bad_Opcode }, |
4020 | { Bad_Opcode }, |
3717 | { Bad_Opcode }, |
4021 | { Bad_Opcode }, |
3718 | { "hsubpd", { XM, EXx } }, |
4022 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3719 | { "hsubps", { XM, EXx } }, |
4023 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, |
Line 3720... | Line 4024... | ||
3720 | }, |
4024 | }, |
3721 | 4025 | ||
3722 | /* PREFIX_0F7E */ |
4026 | /* PREFIX_0F7E */ |
3723 | { |
4027 | { |
- | 4028 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
|
- | 4029 | { "movq", { XM, EXq }, PREFIX_OPCODE }, |
|
- | 4030 | { "movK", { Edq, XM }, PREFIX_OPCODE }, |
|
- | 4031 | }, |
|
- | 4032 | ||
- | 4033 | /* PREFIX_0F7F */ |
|
- | 4034 | { |
|
- | 4035 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
|
- | 4036 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, |
|
- | 4037 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, |
|
- | 4038 | }, |
|
- | 4039 | ||
- | 4040 | /* PREFIX_0FAE_REG_0 */ |
|
- | 4041 | { |
|
- | 4042 | { Bad_Opcode }, |
|
- | 4043 | { "rdfsbase", { Ev }, 0 }, |
|
- | 4044 | }, |
|
- | 4045 | ||
- | 4046 | /* PREFIX_0FAE_REG_1 */ |
|
- | 4047 | { |
|
- | 4048 | { Bad_Opcode }, |
|
3724 | { "movK", { Edq, MX } }, |
4049 | { "rdgsbase", { Ev }, 0 }, |
Line 3725... | Line 4050... | ||
3725 | { "movq", { XM, EXq } }, |
4050 | }, |
3726 | { "movK", { Edq, XM } }, |
4051 | |
3727 | }, |
4052 | /* PREFIX_0FAE_REG_2 */ |
3728 | 4053 | { |
|
3729 | /* PREFIX_0F7F */ |
4054 | { Bad_Opcode }, |
Line 3730... | Line 4055... | ||
3730 | { |
4055 | { "wrfsbase", { Ev }, 0 }, |
3731 | { "movq", { EMS, MX } }, |
4056 | }, |
3732 | { "movdqu", { EXxS, XM } }, |
4057 | |
3733 | { "movdqa", { EXxS, XM } }, |
4058 | /* PREFIX_0FAE_REG_3 */ |
3734 | }, |
4059 | { |
3735 | 4060 | { Bad_Opcode }, |
|
Line 3736... | Line 4061... | ||
3736 | /* PREFIX_0FAE_REG_0 */ |
4061 | { "wrgsbase", { Ev }, 0 }, |
3737 | { |
4062 | }, |
3738 | { Bad_Opcode }, |
4063 | |
3739 | { "rdfsbase", { Ev } }, |
4064 | /* PREFIX_0FAE_REG_6 */ |
3740 | }, |
4065 | { |
3741 | 4066 | { "xsaveopt", { FXSAVE }, 0 }, |
|
Line 3742... | Line 4067... | ||
3742 | /* PREFIX_0FAE_REG_1 */ |
4067 | { Bad_Opcode }, |
3743 | { |
4068 | { "clwb", { Mb }, 0 }, |
3744 | { Bad_Opcode }, |
4069 | }, |
3745 | { "rdgsbase", { Ev } }, |
4070 | |
3746 | }, |
4071 | /* PREFIX_0FAE_REG_7 */ |
3747 | 4072 | { |
|
3748 | /* PREFIX_0FAE_REG_2 */ |
4073 | { "clflush", { Mb }, 0 }, |
Line 3749... | Line 4074... | ||
3749 | { |
4074 | { Bad_Opcode }, |
3750 | { Bad_Opcode }, |
4075 | { "clflushopt", { Mb }, 0 }, |
3751 | { "wrfsbase", { Ev } }, |
4076 | }, |
3752 | }, |
4077 | |
Line 3753... | Line 4078... | ||
3753 | 4078 | /* PREFIX_RM_0_0FAE_REG_7 */ |
|
3754 | /* PREFIX_0FAE_REG_3 */ |
4079 | { |
3755 | { |
4080 | { "sfence", { Skip_MODRM }, 0 }, |
3756 | { Bad_Opcode }, |
4081 | { Bad_Opcode }, |
3757 | { "wrgsbase", { Ev } }, |
4082 | { "pcommit", { Skip_MODRM }, 0 }, |
- | 4083 | }, |
|
- | 4084 | ||
- | 4085 | /* PREFIX_0FB8 */ |
|
- | 4086 | { |
|
- | 4087 | { Bad_Opcode }, |
|
- | 4088 | { "popcntS", { Gv, Ev }, 0 }, |
|
- | 4089 | }, |
|
- | 4090 | ||
- | 4091 | /* PREFIX_0FBC */ |
|
- | 4092 | { |
|
- | 4093 | { "bsfS", { Gv, Ev }, 0 }, |
|
- | 4094 | { "tzcntS", { Gv, Ev }, 0 }, |
|
- | 4095 | { "bsfS", { Gv, Ev }, 0 }, |
|
- | 4096 | }, |
|
3758 | }, |
4097 | |
Line 3759... | Line 4098... | ||
3759 | 4098 | /* PREFIX_0FBD */ |
|
3760 | /* PREFIX_0FB8 */ |
4099 | { |
3761 | { |
4100 | { "bsrS", { Gv, Ev }, 0 }, |
3762 | { Bad_Opcode }, |
4101 | { "lzcntS", { Gv, Ev }, 0 }, |
3763 | { "popcntS", { Gv, Ev } }, |
4102 | { "bsrS", { Gv, Ev }, 0 }, |
3764 | }, |
4103 | }, |
3765 | 4104 | ||
Line 3766... | Line 4105... | ||
3766 | /* PREFIX_0FBC */ |
4105 | /* PREFIX_0FC2 */ |
3767 | { |
4106 | { |
3768 | { "bsfS", { Gv, Ev } }, |
4107 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
3769 | { "tzcntS", { Gv, Ev } }, |
4108 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, |
3770 | { "bsfS", { Gv, Ev } }, |
4109 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, |
3771 | }, |
4110 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, |
3772 | 4111 | }, |
|
Line 3773... | Line 4112... | ||
3773 | /* PREFIX_0FBD */ |
4112 | |
3774 | { |
4113 | /* PREFIX_MOD_0_0FC3 */ |
3775 | { "bsrS", { Gv, Ev } }, |
4114 | { |
3776 | { "lzcntS", { Gv, Ev } }, |
4115 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
3777 | { "bsrS", { Gv, Ev } }, |
4116 | }, |
3778 | }, |
4117 | |
3779 | 4118 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
|
Line 3780... | Line 4119... | ||
3780 | /* PREFIX_0FC2 */ |
4119 | { |
3781 | { |
4120 | { "vmptrld",{ Mq }, 0 }, |
3782 | { "cmpps", { XM, EXx, CMP } }, |
4121 | { "vmxon", { Mq }, 0 }, |
3783 | { "cmpss", { XM, EXd, CMP } }, |
4122 | { "vmclear",{ Mq }, 0 }, |
3784 | { "cmppd", { XM, EXx, CMP } }, |
4123 | }, |
3785 | { "cmpsd", { XM, EXq, CMP } }, |
4124 | |
Line 3786... | Line 4125... | ||
3786 | }, |
4125 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
Line 3836... | Line 4175... | ||
3836 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4175 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
3837 | }, |
4176 | }, |
Line 3838... | Line 4177... | ||
3838 | 4177 | ||
3839 | /* PREFIX_0FF7 */ |
4178 | /* PREFIX_0FF7 */ |
3840 | { |
4179 | { |
3841 | { "maskmovq", { MX, MS } }, |
4180 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
3842 | { Bad_Opcode }, |
4181 | { Bad_Opcode }, |
3843 | { "maskmovdqu", { XM, XS } }, |
4182 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
Line 3844... | Line 4183... | ||
3844 | }, |
4183 | }, |
3845 | 4184 | ||
3846 | /* PREFIX_0F3810 */ |
4185 | /* PREFIX_0F3810 */ |
3847 | { |
4186 | { |
3848 | { Bad_Opcode }, |
4187 | { Bad_Opcode }, |
3849 | { Bad_Opcode }, |
4188 | { Bad_Opcode }, |
Line 3850... | Line 4189... | ||
3850 | { "pblendvb", { XM, EXx, XMM0 } }, |
4189 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
3851 | }, |
4190 | }, |
3852 | 4191 | ||
3853 | /* PREFIX_0F3814 */ |
4192 | /* PREFIX_0F3814 */ |
3854 | { |
4193 | { |
3855 | { Bad_Opcode }, |
4194 | { Bad_Opcode }, |
Line 3856... | Line 4195... | ||
3856 | { Bad_Opcode }, |
4195 | { Bad_Opcode }, |
3857 | { "blendvps", { XM, EXx, XMM0 } }, |
4196 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
3858 | }, |
4197 | }, |
3859 | 4198 | ||
3860 | /* PREFIX_0F3815 */ |
4199 | /* PREFIX_0F3815 */ |
3861 | { |
4200 | { |
Line 3862... | Line 4201... | ||
3862 | { Bad_Opcode }, |
4201 | { Bad_Opcode }, |
3863 | { Bad_Opcode }, |
4202 | { Bad_Opcode }, |
3864 | { "blendvpd", { XM, EXx, XMM0 } }, |
4203 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
3865 | }, |
4204 | }, |
3866 | 4205 | ||
3867 | /* PREFIX_0F3817 */ |
4206 | /* PREFIX_0F3817 */ |
Line 3868... | Line 4207... | ||
3868 | { |
4207 | { |
3869 | { Bad_Opcode }, |
4208 | { Bad_Opcode }, |
3870 | { Bad_Opcode }, |
4209 | { Bad_Opcode }, |
3871 | { "ptest", { XM, EXx } }, |
4210 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
3872 | }, |
4211 | }, |
3873 | 4212 | ||
Line 3874... | Line 4213... | ||
3874 | /* PREFIX_0F3820 */ |
4213 | /* PREFIX_0F3820 */ |
3875 | { |
4214 | { |
3876 | { Bad_Opcode }, |
4215 | { Bad_Opcode }, |
3877 | { Bad_Opcode }, |
4216 | { Bad_Opcode }, |
3878 | { "pmovsxbw", { XM, EXq } }, |
4217 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
3879 | }, |
4218 | }, |
Line 3880... | Line 4219... | ||
3880 | 4219 | ||
3881 | /* PREFIX_0F3821 */ |
4220 | /* PREFIX_0F3821 */ |
3882 | { |
4221 | { |
3883 | { Bad_Opcode }, |
4222 | { Bad_Opcode }, |
3884 | { Bad_Opcode }, |
4223 | { Bad_Opcode }, |
3885 | { "pmovsxbd", { XM, EXd } }, |
4224 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
Line 3886... | Line 4225... | ||
3886 | }, |
4225 | }, |
3887 | 4226 | ||
3888 | /* PREFIX_0F3822 */ |
4227 | /* PREFIX_0F3822 */ |
3889 | { |
4228 | { |
3890 | { Bad_Opcode }, |
4229 | { Bad_Opcode }, |
3891 | { Bad_Opcode }, |
4230 | { Bad_Opcode }, |
Line 3892... | Line 4231... | ||
3892 | { "pmovsxbq", { XM, EXw } }, |
4231 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
3893 | }, |
4232 | }, |
3894 | 4233 | ||
3895 | /* PREFIX_0F3823 */ |
4234 | /* PREFIX_0F3823 */ |
3896 | { |
4235 | { |
3897 | { Bad_Opcode }, |
4236 | { Bad_Opcode }, |
Line 3898... | Line 4237... | ||
3898 | { Bad_Opcode }, |
4237 | { Bad_Opcode }, |
3899 | { "pmovsxwd", { XM, EXq } }, |
4238 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
3900 | }, |
4239 | }, |
3901 | 4240 | ||
3902 | /* PREFIX_0F3824 */ |
4241 | /* PREFIX_0F3824 */ |
3903 | { |
4242 | { |
Line 3904... | Line 4243... | ||
3904 | { Bad_Opcode }, |
4243 | { Bad_Opcode }, |
3905 | { Bad_Opcode }, |
4244 | { Bad_Opcode }, |
3906 | { "pmovsxwq", { XM, EXd } }, |
4245 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
3907 | }, |
4246 | }, |
3908 | 4247 | ||
3909 | /* PREFIX_0F3825 */ |
4248 | /* PREFIX_0F3825 */ |
Line 3910... | Line 4249... | ||
3910 | { |
4249 | { |
3911 | { Bad_Opcode }, |
4250 | { Bad_Opcode }, |
3912 | { Bad_Opcode }, |
4251 | { Bad_Opcode }, |
3913 | { "pmovsxdq", { XM, EXq } }, |
4252 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
3914 | }, |
4253 | }, |
3915 | 4254 | ||
Line 3916... | Line 4255... | ||
3916 | /* PREFIX_0F3828 */ |
4255 | /* PREFIX_0F3828 */ |
3917 | { |
4256 | { |
3918 | { Bad_Opcode }, |
4257 | { Bad_Opcode }, |
Line 3936... | Line 4275... | ||
3936 | 4275 | ||
3937 | /* PREFIX_0F382B */ |
4276 | /* PREFIX_0F382B */ |
3938 | { |
4277 | { |
3939 | { Bad_Opcode }, |
4278 | { Bad_Opcode }, |
3940 | { Bad_Opcode }, |
4279 | { Bad_Opcode }, |
3941 | { "packusdw", { XM, EXx } }, |
4280 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
Line 3942... | Line 4281... | ||
3942 | }, |
4281 | }, |
3943 | 4282 | ||
3944 | /* PREFIX_0F3830 */ |
4283 | /* PREFIX_0F3830 */ |
3945 | { |
4284 | { |
3946 | { Bad_Opcode }, |
4285 | { Bad_Opcode }, |
3947 | { Bad_Opcode }, |
4286 | { Bad_Opcode }, |
Line 3948... | Line 4287... | ||
3948 | { "pmovzxbw", { XM, EXq } }, |
4287 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
3949 | }, |
4288 | }, |
3950 | 4289 | ||
3951 | /* PREFIX_0F3831 */ |
4290 | /* PREFIX_0F3831 */ |
3952 | { |
4291 | { |
3953 | { Bad_Opcode }, |
4292 | { Bad_Opcode }, |
Line 3954... | Line 4293... | ||
3954 | { Bad_Opcode }, |
4293 | { Bad_Opcode }, |
3955 | { "pmovzxbd", { XM, EXd } }, |
4294 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
3956 | }, |
4295 | }, |
3957 | 4296 | ||
3958 | /* PREFIX_0F3832 */ |
4297 | /* PREFIX_0F3832 */ |
3959 | { |
4298 | { |
Line 3960... | Line 4299... | ||
3960 | { Bad_Opcode }, |
4299 | { Bad_Opcode }, |
3961 | { Bad_Opcode }, |
4300 | { Bad_Opcode }, |
3962 | { "pmovzxbq", { XM, EXw } }, |
4301 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
3963 | }, |
4302 | }, |
3964 | 4303 | ||
3965 | /* PREFIX_0F3833 */ |
4304 | /* PREFIX_0F3833 */ |
Line 3966... | Line 4305... | ||
3966 | { |
4305 | { |
3967 | { Bad_Opcode }, |
4306 | { Bad_Opcode }, |
3968 | { Bad_Opcode }, |
4307 | { Bad_Opcode }, |
3969 | { "pmovzxwd", { XM, EXq } }, |
4308 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
3970 | }, |
4309 | }, |
3971 | 4310 | ||
Line 3972... | Line 4311... | ||
3972 | /* PREFIX_0F3834 */ |
4311 | /* PREFIX_0F3834 */ |
3973 | { |
4312 | { |
3974 | { Bad_Opcode }, |
4313 | { Bad_Opcode }, |
3975 | { Bad_Opcode }, |
4314 | { Bad_Opcode }, |
3976 | { "pmovzxwq", { XM, EXd } }, |
4315 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
3977 | }, |
4316 | }, |
Line 3978... | Line 4317... | ||
3978 | 4317 | ||
3979 | /* PREFIX_0F3835 */ |
4318 | /* PREFIX_0F3835 */ |
3980 | { |
4319 | { |
3981 | { Bad_Opcode }, |
4320 | { Bad_Opcode }, |
3982 | { Bad_Opcode }, |
4321 | { Bad_Opcode }, |
3983 | { "pmovzxdq", { XM, EXq } }, |
4322 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
Line 3984... | Line 4323... | ||
3984 | }, |
4323 | }, |
3985 | 4324 | ||
3986 | /* PREFIX_0F3837 */ |
4325 | /* PREFIX_0F3837 */ |
3987 | { |
4326 | { |
3988 | { Bad_Opcode }, |
4327 | { Bad_Opcode }, |
3989 | { Bad_Opcode }, |
4328 | { Bad_Opcode }, |
Line 3990... | Line 4329... | ||
3990 | { "pcmpgtq", { XM, EXx } }, |
4329 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
3991 | }, |
4330 | }, |
3992 | 4331 | ||
3993 | /* PREFIX_0F3838 */ |
4332 | /* PREFIX_0F3838 */ |
3994 | { |
4333 | { |
3995 | { Bad_Opcode }, |
4334 | { Bad_Opcode }, |
Line 3996... | Line 4335... | ||
3996 | { Bad_Opcode }, |
4335 | { Bad_Opcode }, |
3997 | { "pminsb", { XM, EXx } }, |
4336 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
3998 | }, |
4337 | }, |
3999 | 4338 | ||
4000 | /* PREFIX_0F3839 */ |
4339 | /* PREFIX_0F3839 */ |
4001 | { |
4340 | { |
Line 4002... | Line 4341... | ||
4002 | { Bad_Opcode }, |
4341 | { Bad_Opcode }, |
4003 | { Bad_Opcode }, |
4342 | { Bad_Opcode }, |
4004 | { "pminsd", { XM, EXx } }, |
4343 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
4005 | }, |
4344 | }, |
4006 | 4345 | ||
4007 | /* PREFIX_0F383A */ |
4346 | /* PREFIX_0F383A */ |
Line 4008... | Line 4347... | ||
4008 | { |
4347 | { |
4009 | { Bad_Opcode }, |
4348 | { Bad_Opcode }, |
4010 | { Bad_Opcode }, |
4349 | { Bad_Opcode }, |
4011 | { "pminuw", { XM, EXx } }, |
4350 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
4012 | }, |
4351 | }, |
4013 | 4352 | ||
Line 4014... | Line 4353... | ||
4014 | /* PREFIX_0F383B */ |
4353 | /* PREFIX_0F383B */ |
4015 | { |
4354 | { |
4016 | { Bad_Opcode }, |
4355 | { Bad_Opcode }, |
4017 | { Bad_Opcode }, |
4356 | { Bad_Opcode }, |
4018 | { "pminud", { XM, EXx } }, |
4357 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
4019 | }, |
4358 | }, |
Line 4020... | Line 4359... | ||
4020 | 4359 | ||
4021 | /* PREFIX_0F383C */ |
4360 | /* PREFIX_0F383C */ |
4022 | { |
4361 | { |
4023 | { Bad_Opcode }, |
4362 | { Bad_Opcode }, |
4024 | { Bad_Opcode }, |
4363 | { Bad_Opcode }, |
4025 | { "pmaxsb", { XM, EXx } }, |
4364 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
Line 4026... | Line 4365... | ||
4026 | }, |
4365 | }, |
4027 | 4366 | ||
4028 | /* PREFIX_0F383D */ |
4367 | /* PREFIX_0F383D */ |
4029 | { |
4368 | { |
4030 | { Bad_Opcode }, |
4369 | { Bad_Opcode }, |
4031 | { Bad_Opcode }, |
4370 | { Bad_Opcode }, |
Line 4032... | Line 4371... | ||
4032 | { "pmaxsd", { XM, EXx } }, |
4371 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
4033 | }, |
4372 | }, |
4034 | 4373 | ||
4035 | /* PREFIX_0F383E */ |
4374 | /* PREFIX_0F383E */ |
4036 | { |
4375 | { |
4037 | { Bad_Opcode }, |
4376 | { Bad_Opcode }, |
Line 4038... | Line 4377... | ||
4038 | { Bad_Opcode }, |
4377 | { Bad_Opcode }, |
4039 | { "pmaxuw", { XM, EXx } }, |
4378 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
4040 | }, |
4379 | }, |
4041 | 4380 | ||
4042 | /* PREFIX_0F383F */ |
4381 | /* PREFIX_0F383F */ |
4043 | { |
4382 | { |
Line 4044... | Line 4383... | ||
4044 | { Bad_Opcode }, |
4383 | { Bad_Opcode }, |
4045 | { Bad_Opcode }, |
4384 | { Bad_Opcode }, |
4046 | { "pmaxud", { XM, EXx } }, |
4385 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
4047 | }, |
4386 | }, |
4048 | 4387 | ||
4049 | /* PREFIX_0F3840 */ |
4388 | /* PREFIX_0F3840 */ |
Line 4050... | Line 4389... | ||
4050 | { |
4389 | { |
4051 | { Bad_Opcode }, |
4390 | { Bad_Opcode }, |
4052 | { Bad_Opcode }, |
4391 | { Bad_Opcode }, |
4053 | { "pmulld", { XM, EXx } }, |
4392 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
4054 | }, |
4393 | }, |
4055 | 4394 | ||
Line 4056... | Line 4395... | ||
4056 | /* PREFIX_0F3841 */ |
4395 | /* PREFIX_0F3841 */ |
4057 | { |
4396 | { |
4058 | { Bad_Opcode }, |
4397 | { Bad_Opcode }, |
4059 | { Bad_Opcode }, |
4398 | { Bad_Opcode }, |
4060 | { "phminposuw", { XM, EXx } }, |
4399 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
4061 | }, |
4400 | }, |
Line 4062... | Line 4401... | ||
4062 | 4401 | ||
4063 | /* PREFIX_0F3880 */ |
4402 | /* PREFIX_0F3880 */ |
4064 | { |
4403 | { |
4065 | { Bad_Opcode }, |
4404 | { Bad_Opcode }, |
Line 4066... | Line 4405... | ||
4066 | { Bad_Opcode }, |
4405 | { Bad_Opcode }, |
4067 | { "invept", { Gm, Mo } }, |
4406 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
4068 | }, |
4407 | }, |
4069 | 4408 | ||
Line 4070... | Line 4409... | ||
4070 | /* PREFIX_0F3881 */ |
4409 | /* PREFIX_0F3881 */ |
4071 | { |
4410 | { |
4072 | { Bad_Opcode }, |
4411 | { Bad_Opcode }, |
4073 | { Bad_Opcode }, |
4412 | { Bad_Opcode }, |
Line 4074... | Line 4413... | ||
4074 | { "invvpid", { Gm, Mo } }, |
4413 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
4075 | }, |
4414 | }, |
4076 | 4415 | ||
4077 | /* PREFIX_0F3882 */ |
4416 | /* PREFIX_0F3882 */ |
Line 4078... | Line 4417... | ||
4078 | { |
4417 | { |
4079 | { Bad_Opcode }, |
4418 | { Bad_Opcode }, |
4080 | { Bad_Opcode }, |
4419 | { Bad_Opcode }, |
4081 | { "invpcid", { Gm, M } }, |
4420 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
Line 4082... | Line 4421... | ||
4082 | }, |
4421 | }, |
4083 | 4422 | ||
4084 | /* PREFIX_0F38C8 */ |
4423 | /* PREFIX_0F38C8 */ |
4085 | { |
4424 | { |
Line 4086... | Line 4425... | ||
4086 | { "sha1nexte", { XM, EXxmm } }, |
4425 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
4087 | }, |
4426 | }, |
4088 | 4427 | ||
4089 | /* PREFIX_0F38C9 */ |
4428 | /* PREFIX_0F38C9 */ |
4090 | { |
4429 | { |
4091 | { "sha1msg1", { XM, EXxmm } }, |
4430 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
Line 4092... | Line 4431... | ||
4092 | }, |
4431 | }, |
4093 | 4432 | ||
4094 | /* PREFIX_0F38CA */ |
4433 | /* PREFIX_0F38CA */ |
4095 | { |
4434 | { |
4096 | { "sha1msg2", { XM, EXxmm } }, |
4435 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
4097 | }, |
4436 | }, |
Line 4098... | Line 4437... | ||
4098 | 4437 | ||
4099 | /* PREFIX_0F38CB */ |
4438 | /* PREFIX_0F38CB */ |
4100 | { |
4439 | { |
4101 | { "sha256rnds2", { XM, EXxmm, XMM0 } }, |
4440 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
4102 | }, |
4441 | }, |
4103 | 4442 | ||
Line 4104... | Line 4443... | ||
4104 | /* PREFIX_0F38CC */ |
4443 | /* PREFIX_0F38CC */ |
4105 | { |
4444 | { |
4106 | { "sha256msg1", { XM, EXxmm } }, |
4445 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
4107 | }, |
4446 | }, |
4108 | 4447 | ||
4109 | /* PREFIX_0F38CD */ |
4448 | /* PREFIX_0F38CD */ |
Line 4110... | Line 4449... | ||
4110 | { |
4449 | { |
4111 | { "sha256msg2", { XM, EXxmm } }, |
4450 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
4112 | }, |
4451 | }, |
4113 | 4452 | ||
4114 | /* PREFIX_0F38DB */ |
4453 | /* PREFIX_0F38DB */ |
4115 | { |
4454 | { |
Line 4116... | Line 4455... | ||
4116 | { Bad_Opcode }, |
4455 | { Bad_Opcode }, |
4117 | { Bad_Opcode }, |
4456 | { Bad_Opcode }, |
4118 | { "aesimc", { XM, EXx } }, |
4457 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
4119 | }, |
4458 | }, |
4120 | 4459 | ||
4121 | /* PREFIX_0F38DC */ |
4460 | /* PREFIX_0F38DC */ |
4122 | { |
4461 | { |
Line 4123... | Line 4462... | ||
4123 | { Bad_Opcode }, |
4462 | { Bad_Opcode }, |
4124 | { Bad_Opcode }, |
4463 | { Bad_Opcode }, |
4125 | { "aesenc", { XM, EXx } }, |
4464 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
4126 | }, |
4465 | }, |
4127 | 4466 | ||
4128 | /* PREFIX_0F38DD */ |
4467 | /* PREFIX_0F38DD */ |
4129 | { |
4468 | { |
Line 4130... | Line 4469... | ||
4130 | { Bad_Opcode }, |
4469 | { Bad_Opcode }, |
4131 | { Bad_Opcode }, |
4470 | { Bad_Opcode }, |
4132 | { "aesenclast", { XM, EXx } }, |
4471 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
4133 | }, |
4472 | }, |
4134 | 4473 | ||
4135 | /* PREFIX_0F38DE */ |
4474 | /* PREFIX_0F38DE */ |
4136 | { |
4475 | { |
Line 4137... | Line 4476... | ||
4137 | { Bad_Opcode }, |
4476 | { Bad_Opcode }, |
4138 | { Bad_Opcode }, |
4477 | { Bad_Opcode }, |
4139 | { "aesdec", { XM, EXx } }, |
4478 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
4140 | }, |
4479 | }, |
4141 | 4480 | ||
4142 | /* PREFIX_0F38DF */ |
4481 | /* PREFIX_0F38DF */ |
Line 4143... | Line 4482... | ||
4143 | { |
4482 | { |
4144 | { Bad_Opcode }, |
4483 | { Bad_Opcode }, |
4145 | { Bad_Opcode }, |
4484 | { Bad_Opcode }, |
4146 | { "aesdeclast", { XM, EXx } }, |
4485 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
4147 | }, |
4486 | }, |
4148 | 4487 | ||
Line 4149... | Line 4488... | ||
4149 | /* PREFIX_0F38F0 */ |
4488 | /* PREFIX_0F38F0 */ |
4150 | { |
4489 | { |
4151 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
4490 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4152 | { Bad_Opcode }, |
4491 | { Bad_Opcode }, |
4153 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
4492 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4154 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, |
4493 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, |
Line 4155... | Line 4494... | ||
4155 | }, |
4494 | }, |
4156 | 4495 | ||
4157 | /* PREFIX_0F38F1 */ |
4496 | /* PREFIX_0F38F1 */ |
4158 | { |
4497 | { |
4159 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
4498 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4160 | { Bad_Opcode }, |
4499 | { Bad_Opcode }, |
Line 4161... | Line 4500... | ||
4161 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
4500 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4162 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, |
4501 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, |
4163 | }, |
4502 | }, |
4164 | 4503 | ||
4165 | /* PREFIX_0F38F6 */ |
4504 | /* PREFIX_0F38F6 */ |
4166 | { |
4505 | { |
Line 4167... | Line 4506... | ||
4167 | { Bad_Opcode }, |
4506 | { Bad_Opcode }, |
4168 | { "adoxS", { Gdq, Edq} }, |
4507 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4169 | { "adcxS", { Gdq, Edq} }, |
4508 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4170 | { Bad_Opcode }, |
4509 | { Bad_Opcode }, |
4171 | }, |
4510 | }, |
4172 | 4511 | ||
Line 4173... | Line 4512... | ||
4173 | /* PREFIX_0F3A08 */ |
4512 | /* PREFIX_0F3A08 */ |
4174 | { |
4513 | { |
4175 | { Bad_Opcode }, |
4514 | { Bad_Opcode }, |
4176 | { Bad_Opcode }, |
4515 | { Bad_Opcode }, |
4177 | { "roundps", { XM, EXx, Ib } }, |
4516 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4178 | }, |
4517 | }, |
Line 4179... | Line 4518... | ||
4179 | 4518 | ||
4180 | /* PREFIX_0F3A09 */ |
4519 | /* PREFIX_0F3A09 */ |
4181 | { |
4520 | { |
4182 | { Bad_Opcode }, |
4521 | { Bad_Opcode }, |
4183 | { Bad_Opcode }, |
4522 | { Bad_Opcode }, |
4184 | { "roundpd", { XM, EXx, Ib } }, |
4523 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
Line 4185... | Line 4524... | ||
4185 | }, |
4524 | }, |
4186 | 4525 | ||
4187 | /* PREFIX_0F3A0A */ |
4526 | /* PREFIX_0F3A0A */ |
4188 | { |
4527 | { |
4189 | { Bad_Opcode }, |
4528 | { Bad_Opcode }, |
4190 | { Bad_Opcode }, |
4529 | { Bad_Opcode }, |
Line 4191... | Line 4530... | ||
4191 | { "roundss", { XM, EXd, Ib } }, |
4530 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
4192 | }, |
4531 | }, |
4193 | 4532 | ||
4194 | /* PREFIX_0F3A0B */ |
4533 | /* PREFIX_0F3A0B */ |
4195 | { |
4534 | { |
4196 | { Bad_Opcode }, |
4535 | { Bad_Opcode }, |
Line 4197... | Line 4536... | ||
4197 | { Bad_Opcode }, |
4536 | { Bad_Opcode }, |
4198 | { "roundsd", { XM, EXq, Ib } }, |
4537 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
4199 | }, |
4538 | }, |
4200 | 4539 | ||
4201 | /* PREFIX_0F3A0C */ |
4540 | /* PREFIX_0F3A0C */ |
4202 | { |
4541 | { |
Line 4203... | Line 4542... | ||
4203 | { Bad_Opcode }, |
4542 | { Bad_Opcode }, |
4204 | { Bad_Opcode }, |
4543 | { Bad_Opcode }, |
4205 | { "blendps", { XM, EXx, Ib } }, |
4544 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4206 | }, |
4545 | }, |
4207 | 4546 | ||
4208 | /* PREFIX_0F3A0D */ |
4547 | /* PREFIX_0F3A0D */ |
Line 4209... | Line 4548... | ||
4209 | { |
4548 | { |
4210 | { Bad_Opcode }, |
4549 | { Bad_Opcode }, |
4211 | { Bad_Opcode }, |
4550 | { Bad_Opcode }, |
4212 | { "blendpd", { XM, EXx, Ib } }, |
4551 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4213 | }, |
4552 | }, |
4214 | 4553 | ||
Line 4215... | Line 4554... | ||
4215 | /* PREFIX_0F3A0E */ |
4554 | /* PREFIX_0F3A0E */ |
4216 | { |
4555 | { |
4217 | { Bad_Opcode }, |
4556 | { Bad_Opcode }, |
4218 | { Bad_Opcode }, |
4557 | { Bad_Opcode }, |
4219 | { "pblendw", { XM, EXx, Ib } }, |
4558 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4220 | }, |
4559 | }, |
Line 4221... | Line 4560... | ||
4221 | 4560 | ||
4222 | /* PREFIX_0F3A14 */ |
4561 | /* PREFIX_0F3A14 */ |
4223 | { |
4562 | { |
4224 | { Bad_Opcode }, |
4563 | { Bad_Opcode }, |
4225 | { Bad_Opcode }, |
4564 | { Bad_Opcode }, |
4226 | { "pextrb", { Edqb, XM, Ib } }, |
4565 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
Line 4227... | Line 4566... | ||
4227 | }, |
4566 | }, |
4228 | 4567 | ||
4229 | /* PREFIX_0F3A15 */ |
4568 | /* PREFIX_0F3A15 */ |
4230 | { |
4569 | { |
4231 | { Bad_Opcode }, |
4570 | { Bad_Opcode }, |
4232 | { Bad_Opcode }, |
4571 | { Bad_Opcode }, |
Line 4233... | Line 4572... | ||
4233 | { "pextrw", { Edqw, XM, Ib } }, |
4572 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
4234 | }, |
4573 | }, |
4235 | 4574 | ||
4236 | /* PREFIX_0F3A16 */ |
4575 | /* PREFIX_0F3A16 */ |
4237 | { |
4576 | { |
4238 | { Bad_Opcode }, |
4577 | { Bad_Opcode }, |
Line 4239... | Line 4578... | ||
4239 | { Bad_Opcode }, |
4578 | { Bad_Opcode }, |
4240 | { "pextrK", { Edq, XM, Ib } }, |
4579 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
4241 | }, |
4580 | }, |
4242 | 4581 | ||
4243 | /* PREFIX_0F3A17 */ |
4582 | /* PREFIX_0F3A17 */ |
4244 | { |
4583 | { |
Line 4245... | Line 4584... | ||
4245 | { Bad_Opcode }, |
4584 | { Bad_Opcode }, |
4246 | { Bad_Opcode }, |
4585 | { Bad_Opcode }, |
4247 | { "extractps", { Edqd, XM, Ib } }, |
4586 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
4248 | }, |
4587 | }, |
4249 | 4588 | ||
4250 | /* PREFIX_0F3A20 */ |
4589 | /* PREFIX_0F3A20 */ |
Line 4251... | Line 4590... | ||
4251 | { |
4590 | { |
4252 | { Bad_Opcode }, |
4591 | { Bad_Opcode }, |
4253 | { Bad_Opcode }, |
4592 | { Bad_Opcode }, |
4254 | { "pinsrb", { XM, Edqb, Ib } }, |
4593 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
4255 | }, |
4594 | }, |
4256 | 4595 | ||
Line 4257... | Line 4596... | ||
4257 | /* PREFIX_0F3A21 */ |
4596 | /* PREFIX_0F3A21 */ |
4258 | { |
4597 | { |
4259 | { Bad_Opcode }, |
4598 | { Bad_Opcode }, |
4260 | { Bad_Opcode }, |
4599 | { Bad_Opcode }, |
4261 | { "insertps", { XM, EXd, Ib } }, |
4600 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
4262 | }, |
4601 | }, |
Line 4263... | Line 4602... | ||
4263 | 4602 | ||
4264 | /* PREFIX_0F3A22 */ |
4603 | /* PREFIX_0F3A22 */ |
4265 | { |
4604 | { |
4266 | { Bad_Opcode }, |
4605 | { Bad_Opcode }, |
4267 | { Bad_Opcode }, |
4606 | { Bad_Opcode }, |
4268 | { "pinsrK", { XM, Edq, Ib } }, |
4607 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
Line 4269... | Line 4608... | ||
4269 | }, |
4608 | }, |
4270 | 4609 | ||
4271 | /* PREFIX_0F3A40 */ |
4610 | /* PREFIX_0F3A40 */ |
4272 | { |
4611 | { |
Line 4273... | Line 4612... | ||
4273 | { Bad_Opcode }, |
4612 | { Bad_Opcode }, |
4274 | { Bad_Opcode }, |
4613 | { Bad_Opcode }, |
4275 | { "dpps", { XM, EXx, Ib } }, |
4614 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
4276 | }, |
4615 | }, |
4277 | 4616 | ||
4278 | /* PREFIX_0F3A41 */ |
4617 | /* PREFIX_0F3A41 */ |
Line 4279... | Line 4618... | ||
4279 | { |
4618 | { |
4280 | { Bad_Opcode }, |
4619 | { Bad_Opcode }, |
4281 | { Bad_Opcode }, |
4620 | { Bad_Opcode }, |
Line 4406... | Line 4745... | ||
4406 | }, |
4745 | }, |
Line 4407... | Line 4746... | ||
4407 | 4746 | ||
4408 | /* PREFIX_VEX_0F41 */ |
4747 | /* PREFIX_VEX_0F41 */ |
4409 | { |
4748 | { |
- | 4749 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, |
|
- | 4750 | { Bad_Opcode }, |
|
4410 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, |
4751 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, |
Line 4411... | Line 4752... | ||
4411 | }, |
4752 | }, |
4412 | 4753 | ||
4413 | /* PREFIX_VEX_0F42 */ |
4754 | /* PREFIX_VEX_0F42 */ |
- | 4755 | { |
|
- | 4756 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, |
|
4414 | { |
4757 | { Bad_Opcode }, |
Line 4415... | Line 4758... | ||
4415 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, |
4758 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, |
4416 | }, |
4759 | }, |
4417 | 4760 | ||
- | 4761 | /* PREFIX_VEX_0F44 */ |
|
- | 4762 | { |
|
4418 | /* PREFIX_VEX_0F44 */ |
4763 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, |
Line 4419... | Line 4764... | ||
4419 | { |
4764 | { Bad_Opcode }, |
4420 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, |
4765 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, |
4421 | }, |
4766 | }, |
- | 4767 | ||
- | 4768 | /* PREFIX_VEX_0F45 */ |
|
4422 | 4769 | { |
|
Line 4423... | Line 4770... | ||
4423 | /* PREFIX_VEX_0F45 */ |
4770 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, |
4424 | { |
4771 | { Bad_Opcode }, |
4425 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, |
4772 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, |
- | 4773 | }, |
|
- | 4774 | ||
4426 | }, |
4775 | /* PREFIX_VEX_0F46 */ |
Line 4427... | Line 4776... | ||
4427 | 4776 | { |
|
4428 | /* PREFIX_VEX_0F46 */ |
4777 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, |
4429 | { |
4778 | { Bad_Opcode }, |
- | 4779 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, |
|
- | 4780 | }, |
|
4430 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, |
4781 | |
Line 4431... | Line 4782... | ||
4431 | }, |
4782 | /* PREFIX_VEX_0F47 */ |
4432 | 4783 | { |
|
- | 4784 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, |
|
4433 | /* PREFIX_VEX_0F47 */ |
4785 | { Bad_Opcode }, |
- | 4786 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, |
|
- | 4787 | }, |
|
- | 4788 | ||
- | 4789 | /* PREFIX_VEX_0F4A */ |
|
- | 4790 | { |
|
- | 4791 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
|
4434 | { |
4792 | { Bad_Opcode }, |
4435 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, |
4793 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4436 | }, |
4794 | }, |
Line 4437... | Line 4795... | ||
4437 | 4795 | ||
Line 4480... | Line 4838... | ||
4480 | 4838 | ||
4481 | /* PREFIX_VEX_0F5A */ |
4839 | /* PREFIX_VEX_0F5A */ |
4482 | { |
4840 | { |
4483 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4841 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4484 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, |
4842 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, |
4485 | { "vcvtpd2ps%XY", { XMM, EXx } }, |
4843 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
4486 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
4844 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
Line 4487... | Line 4845... | ||
4487 | }, |
4845 | }, |
4488 | 4846 | ||
Line 4772... | Line 5130... | ||
4772 | }, |
5130 | }, |
Line 4773... | Line 5131... | ||
4773 | 5131 | ||
4774 | /* PREFIX_VEX_0F90 */ |
5132 | /* PREFIX_VEX_0F90 */ |
4775 | { |
5133 | { |
- | 5134 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, |
|
- | 5135 | { Bad_Opcode }, |
|
4776 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, |
5136 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, |
Line 4777... | Line 5137... | ||
4777 | }, |
5137 | }, |
4778 | 5138 | ||
4779 | /* PREFIX_VEX_0F91 */ |
5139 | /* PREFIX_VEX_0F91 */ |
- | 5140 | { |
|
- | 5141 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, |
|
4780 | { |
5142 | { Bad_Opcode }, |
Line 4781... | Line 5143... | ||
4781 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, |
5143 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, |
4782 | }, |
5144 | }, |
4783 | 5145 | ||
- | 5146 | /* PREFIX_VEX_0F92 */ |
|
- | 5147 | { |
|
- | 5148 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, |
|
4784 | /* PREFIX_VEX_0F92 */ |
5149 | { Bad_Opcode }, |
Line 4785... | Line 5150... | ||
4785 | { |
5150 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
4786 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, |
5151 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
4787 | }, |
5152 | }, |
- | 5153 | ||
- | 5154 | /* PREFIX_VEX_0F93 */ |
|
- | 5155 | { |
|
4788 | 5156 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, |
|
Line 4789... | Line 5157... | ||
4789 | /* PREFIX_VEX_0F93 */ |
5157 | { Bad_Opcode }, |
4790 | { |
5158 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
4791 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, |
5159 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
- | 5160 | }, |
|
- | 5161 | ||
- | 5162 | /* PREFIX_VEX_0F98 */ |
|
- | 5163 | { |
|
- | 5164 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, |
|
- | 5165 | { Bad_Opcode }, |
|
- | 5166 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, |
|
- | 5167 | }, |
|
- | 5168 | ||
4792 | }, |
5169 | /* PREFIX_VEX_0F99 */ |
Line 4793... | Line 5170... | ||
4793 | 5170 | { |
|
4794 | /* PREFIX_VEX_0F98 */ |
5171 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, |
4795 | { |
5172 | { Bad_Opcode }, |
Line 5264... | Line 5641... | ||
5264 | 5641 | ||
5265 | /* PREFIX_VEX_0F3813 */ |
5642 | /* PREFIX_VEX_0F3813 */ |
5266 | { |
5643 | { |
5267 | { Bad_Opcode }, |
5644 | { Bad_Opcode }, |
5268 | { Bad_Opcode }, |
5645 | { Bad_Opcode }, |
5269 | { "vcvtph2ps", { XM, EXxmmq } }, |
5646 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
Line 5270... | Line 5647... | ||
5270 | }, |
5647 | }, |
5271 | 5648 | ||
5272 | /* PREFIX_VEX_0F3816 */ |
5649 | /* PREFIX_VEX_0F3816 */ |
Line 5551... | Line 5928... | ||
5551 | 5928 | ||
5552 | /* PREFIX_VEX_0F3845 */ |
5929 | /* PREFIX_VEX_0F3845 */ |
5553 | { |
5930 | { |
5554 | { Bad_Opcode }, |
5931 | { Bad_Opcode }, |
5555 | { Bad_Opcode }, |
5932 | { Bad_Opcode }, |
5556 | { "vpsrlv%LW", { XM, Vex, EXx } }, |
5933 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
Line 5557... | Line 5934... | ||
5557 | }, |
5934 | }, |
5558 | 5935 | ||
5559 | /* PREFIX_VEX_0F3846 */ |
5936 | /* PREFIX_VEX_0F3846 */ |
Line 5565... | Line 5942... | ||
5565 | 5942 | ||
5566 | /* PREFIX_VEX_0F3847 */ |
5943 | /* PREFIX_VEX_0F3847 */ |
5567 | { |
5944 | { |
5568 | { Bad_Opcode }, |
5945 | { Bad_Opcode }, |
5569 | { Bad_Opcode }, |
5946 | { Bad_Opcode }, |
5570 | { "vpsllv%LW", { XM, Vex, EXx } }, |
5947 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
Line 5571... | Line 5948... | ||
5571 | }, |
5948 | }, |
5572 | 5949 | ||
5573 | /* PREFIX_VEX_0F3858 */ |
5950 | /* PREFIX_VEX_0F3858 */ |
Line 5621... | Line 5998... | ||
5621 | 5998 | ||
5622 | /* PREFIX_VEX_0F3890 */ |
5999 | /* PREFIX_VEX_0F3890 */ |
5623 | { |
6000 | { |
5624 | { Bad_Opcode }, |
6001 | { Bad_Opcode }, |
5625 | { Bad_Opcode }, |
6002 | { Bad_Opcode }, |
5626 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } }, |
6003 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
Line 5627... | Line 6004... | ||
5627 | }, |
6004 | }, |
5628 | 6005 | ||
5629 | /* PREFIX_VEX_0F3891 */ |
6006 | /* PREFIX_VEX_0F3891 */ |
5630 | { |
6007 | { |
5631 | { Bad_Opcode }, |
6008 | { Bad_Opcode }, |
5632 | { Bad_Opcode }, |
6009 | { Bad_Opcode }, |
Line 5633... | Line 6010... | ||
5633 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, |
6010 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
5634 | }, |
6011 | }, |
5635 | 6012 | ||
5636 | /* PREFIX_VEX_0F3892 */ |
6013 | /* PREFIX_VEX_0F3892 */ |
5637 | { |
6014 | { |
5638 | { Bad_Opcode }, |
6015 | { Bad_Opcode }, |
Line 5639... | Line 6016... | ||
5639 | { Bad_Opcode }, |
6016 | { Bad_Opcode }, |
5640 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } }, |
6017 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
5641 | }, |
6018 | }, |
5642 | 6019 | ||
5643 | /* PREFIX_VEX_0F3893 */ |
6020 | /* PREFIX_VEX_0F3893 */ |
5644 | { |
6021 | { |
Line 5645... | Line 6022... | ||
5645 | { Bad_Opcode }, |
6022 | { Bad_Opcode }, |
5646 | { Bad_Opcode }, |
6023 | { Bad_Opcode }, |
5647 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, |
6024 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
5648 | }, |
6025 | }, |
5649 | 6026 | ||
5650 | /* PREFIX_VEX_0F3896 */ |
6027 | /* PREFIX_VEX_0F3896 */ |
Line 5651... | Line 6028... | ||
5651 | { |
6028 | { |
5652 | { Bad_Opcode }, |
6029 | { Bad_Opcode }, |
5653 | { Bad_Opcode }, |
6030 | { Bad_Opcode }, |
5654 | { "vfmaddsub132p%XW", { XM, Vex, EXx } }, |
6031 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
5655 | }, |
6032 | }, |
5656 | 6033 | ||
Line 5657... | Line 6034... | ||
5657 | /* PREFIX_VEX_0F3897 */ |
6034 | /* PREFIX_VEX_0F3897 */ |
5658 | { |
6035 | { |
5659 | { Bad_Opcode }, |
6036 | { Bad_Opcode }, |
5660 | { Bad_Opcode }, |
6037 | { Bad_Opcode }, |
5661 | { "vfmsubadd132p%XW", { XM, Vex, EXx } }, |
6038 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
5662 | }, |
6039 | }, |
Line 5663... | Line 6040... | ||
5663 | 6040 | ||
5664 | /* PREFIX_VEX_0F3898 */ |
6041 | /* PREFIX_VEX_0F3898 */ |
5665 | { |
6042 | { |
5666 | { Bad_Opcode }, |
6043 | { Bad_Opcode }, |
5667 | { Bad_Opcode }, |
6044 | { Bad_Opcode }, |
5668 | { "vfmadd132p%XW", { XM, Vex, EXx } }, |
6045 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
Line 5669... | Line 6046... | ||
5669 | }, |
6046 | }, |
5670 | 6047 | ||
5671 | /* PREFIX_VEX_0F3899 */ |
6048 | /* PREFIX_VEX_0F3899 */ |
5672 | { |
6049 | { |
5673 | { Bad_Opcode }, |
6050 | { Bad_Opcode }, |
5674 | { Bad_Opcode }, |
6051 | { Bad_Opcode }, |
Line 5675... | Line 6052... | ||
5675 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6052 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5676 | }, |
6053 | }, |
5677 | 6054 | ||
5678 | /* PREFIX_VEX_0F389A */ |
6055 | /* PREFIX_VEX_0F389A */ |
5679 | { |
6056 | { |
5680 | { Bad_Opcode }, |
6057 | { Bad_Opcode }, |
Line 5681... | Line 6058... | ||
5681 | { Bad_Opcode }, |
6058 | { Bad_Opcode }, |
5682 | { "vfmsub132p%XW", { XM, Vex, EXx } }, |
6059 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
5683 | }, |
6060 | }, |
5684 | 6061 | ||
5685 | /* PREFIX_VEX_0F389B */ |
6062 | /* PREFIX_VEX_0F389B */ |
5686 | { |
6063 | { |
Line 5687... | Line 6064... | ||
5687 | { Bad_Opcode }, |
6064 | { Bad_Opcode }, |
5688 | { Bad_Opcode }, |
6065 | { Bad_Opcode }, |
5689 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6066 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5690 | }, |
6067 | }, |
5691 | 6068 | ||
5692 | /* PREFIX_VEX_0F389C */ |
6069 | /* PREFIX_VEX_0F389C */ |
Line 5693... | Line 6070... | ||
5693 | { |
6070 | { |
5694 | { Bad_Opcode }, |
6071 | { Bad_Opcode }, |
5695 | { Bad_Opcode }, |
6072 | { Bad_Opcode }, |
5696 | { "vfnmadd132p%XW", { XM, Vex, EXx } }, |
6073 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
5697 | }, |
6074 | }, |
5698 | 6075 | ||
Line 5699... | Line 6076... | ||
5699 | /* PREFIX_VEX_0F389D */ |
6076 | /* PREFIX_VEX_0F389D */ |
5700 | { |
6077 | { |
5701 | { Bad_Opcode }, |
6078 | { Bad_Opcode }, |
5702 | { Bad_Opcode }, |
6079 | { Bad_Opcode }, |
5703 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6080 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5704 | }, |
6081 | }, |
Line 5705... | Line 6082... | ||
5705 | 6082 | ||
5706 | /* PREFIX_VEX_0F389E */ |
6083 | /* PREFIX_VEX_0F389E */ |
5707 | { |
6084 | { |
5708 | { Bad_Opcode }, |
6085 | { Bad_Opcode }, |
5709 | { Bad_Opcode }, |
6086 | { Bad_Opcode }, |
5710 | { "vfnmsub132p%XW", { XM, Vex, EXx } }, |
6087 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
5711 | }, |
6088 | }, |
Line 5712... | Line 6089... | ||
5712 | 6089 | ||
5713 | /* PREFIX_VEX_0F389F */ |
6090 | /* PREFIX_VEX_0F389F */ |
5714 | { |
6091 | { |
5715 | { Bad_Opcode }, |
6092 | { Bad_Opcode }, |
5716 | { Bad_Opcode }, |
6093 | { Bad_Opcode }, |
5717 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6094 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
Line 5718... | Line 6095... | ||
5718 | }, |
6095 | }, |
5719 | 6096 | ||
5720 | /* PREFIX_VEX_0F38A6 */ |
6097 | /* PREFIX_VEX_0F38A6 */ |
5721 | { |
6098 | { |
5722 | { Bad_Opcode }, |
6099 | { Bad_Opcode }, |
5723 | { Bad_Opcode }, |
6100 | { Bad_Opcode }, |
Line 5724... | Line 6101... | ||
5724 | { "vfmaddsub213p%XW", { XM, Vex, EXx } }, |
6101 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
5725 | { Bad_Opcode }, |
6102 | { Bad_Opcode }, |
5726 | }, |
6103 | }, |
5727 | 6104 | ||
5728 | /* PREFIX_VEX_0F38A7 */ |
6105 | /* PREFIX_VEX_0F38A7 */ |
5729 | { |
6106 | { |
Line 5730... | Line 6107... | ||
5730 | { Bad_Opcode }, |
6107 | { Bad_Opcode }, |
5731 | { Bad_Opcode }, |
6108 | { Bad_Opcode }, |
5732 | { "vfmsubadd213p%XW", { XM, Vex, EXx } }, |
6109 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
5733 | }, |
6110 | }, |
5734 | 6111 | ||
5735 | /* PREFIX_VEX_0F38A8 */ |
6112 | /* PREFIX_VEX_0F38A8 */ |
Line 5736... | Line 6113... | ||
5736 | { |
6113 | { |
5737 | { Bad_Opcode }, |
6114 | { Bad_Opcode }, |
5738 | { Bad_Opcode }, |
6115 | { Bad_Opcode }, |
5739 | { "vfmadd213p%XW", { XM, Vex, EXx } }, |
6116 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
5740 | }, |
6117 | }, |
5741 | 6118 | ||
Line 5742... | Line 6119... | ||
5742 | /* PREFIX_VEX_0F38A9 */ |
6119 | /* PREFIX_VEX_0F38A9 */ |
5743 | { |
6120 | { |
5744 | { Bad_Opcode }, |
6121 | { Bad_Opcode }, |
5745 | { Bad_Opcode }, |
6122 | { Bad_Opcode }, |
5746 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6123 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5747 | }, |
6124 | }, |
Line 5748... | Line 6125... | ||
5748 | 6125 | ||
5749 | /* PREFIX_VEX_0F38AA */ |
6126 | /* PREFIX_VEX_0F38AA */ |
5750 | { |
6127 | { |
5751 | { Bad_Opcode }, |
6128 | { Bad_Opcode }, |
5752 | { Bad_Opcode }, |
6129 | { Bad_Opcode }, |
5753 | { "vfmsub213p%XW", { XM, Vex, EXx } }, |
6130 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
Line 5754... | Line 6131... | ||
5754 | }, |
6131 | }, |
5755 | 6132 | ||
5756 | /* PREFIX_VEX_0F38AB */ |
6133 | /* PREFIX_VEX_0F38AB */ |
5757 | { |
6134 | { |
5758 | { Bad_Opcode }, |
6135 | { Bad_Opcode }, |
5759 | { Bad_Opcode }, |
6136 | { Bad_Opcode }, |
Line 5760... | Line 6137... | ||
5760 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6137 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5761 | }, |
6138 | }, |
5762 | 6139 | ||
5763 | /* PREFIX_VEX_0F38AC */ |
6140 | /* PREFIX_VEX_0F38AC */ |
5764 | { |
6141 | { |
5765 | { Bad_Opcode }, |
6142 | { Bad_Opcode }, |
Line 5766... | Line 6143... | ||
5766 | { Bad_Opcode }, |
6143 | { Bad_Opcode }, |
5767 | { "vfnmadd213p%XW", { XM, Vex, EXx } }, |
6144 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
5768 | }, |
6145 | }, |
5769 | 6146 | ||
5770 | /* PREFIX_VEX_0F38AD */ |
6147 | /* PREFIX_VEX_0F38AD */ |
5771 | { |
6148 | { |
Line 5772... | Line 6149... | ||
5772 | { Bad_Opcode }, |
6149 | { Bad_Opcode }, |
5773 | { Bad_Opcode }, |
6150 | { Bad_Opcode }, |
5774 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6151 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5775 | }, |
6152 | }, |
5776 | 6153 | ||
5777 | /* PREFIX_VEX_0F38AE */ |
6154 | /* PREFIX_VEX_0F38AE */ |
Line 5778... | Line 6155... | ||
5778 | { |
6155 | { |
5779 | { Bad_Opcode }, |
6156 | { Bad_Opcode }, |
5780 | { Bad_Opcode }, |
6157 | { Bad_Opcode }, |
5781 | { "vfnmsub213p%XW", { XM, Vex, EXx } }, |
6158 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
5782 | }, |
6159 | }, |
5783 | 6160 | ||
Line 5784... | Line 6161... | ||
5784 | /* PREFIX_VEX_0F38AF */ |
6161 | /* PREFIX_VEX_0F38AF */ |
5785 | { |
6162 | { |
5786 | { Bad_Opcode }, |
6163 | { Bad_Opcode }, |
5787 | { Bad_Opcode }, |
6164 | { Bad_Opcode }, |
5788 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6165 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5789 | }, |
6166 | }, |
Line 5790... | Line 6167... | ||
5790 | 6167 | ||
5791 | /* PREFIX_VEX_0F38B6 */ |
6168 | /* PREFIX_VEX_0F38B6 */ |
5792 | { |
6169 | { |
5793 | { Bad_Opcode }, |
6170 | { Bad_Opcode }, |
5794 | { Bad_Opcode }, |
6171 | { Bad_Opcode }, |
5795 | { "vfmaddsub231p%XW", { XM, Vex, EXx } }, |
6172 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
Line 5796... | Line 6173... | ||
5796 | }, |
6173 | }, |
5797 | 6174 | ||
5798 | /* PREFIX_VEX_0F38B7 */ |
6175 | /* PREFIX_VEX_0F38B7 */ |
5799 | { |
6176 | { |
5800 | { Bad_Opcode }, |
6177 | { Bad_Opcode }, |
5801 | { Bad_Opcode }, |
6178 | { Bad_Opcode }, |
Line 5802... | Line 6179... | ||
5802 | { "vfmsubadd231p%XW", { XM, Vex, EXx } }, |
6179 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
5803 | }, |
6180 | }, |
5804 | 6181 | ||
5805 | /* PREFIX_VEX_0F38B8 */ |
6182 | /* PREFIX_VEX_0F38B8 */ |
5806 | { |
6183 | { |
5807 | { Bad_Opcode }, |
6184 | { Bad_Opcode }, |
Line 5808... | Line 6185... | ||
5808 | { Bad_Opcode }, |
6185 | { Bad_Opcode }, |
5809 | { "vfmadd231p%XW", { XM, Vex, EXx } }, |
6186 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
5810 | }, |
6187 | }, |
5811 | 6188 | ||
5812 | /* PREFIX_VEX_0F38B9 */ |
6189 | /* PREFIX_VEX_0F38B9 */ |
5813 | { |
6190 | { |
Line 5814... | Line 6191... | ||
5814 | { Bad_Opcode }, |
6191 | { Bad_Opcode }, |
5815 | { Bad_Opcode }, |
6192 | { Bad_Opcode }, |
5816 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
6193 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
5817 | }, |
6194 | }, |
5818 | 6195 | ||
5819 | /* PREFIX_VEX_0F38BA */ |
6196 | /* PREFIX_VEX_0F38BA */ |
Line 5820... | Line 6197... | ||
5820 | { |
6197 | { |
5821 | { Bad_Opcode }, |
6198 | { Bad_Opcode }, |
5822 | { Bad_Opcode }, |
6199 | { Bad_Opcode }, |
5823 | { "vfmsub231p%XW", { XM, Vex, EXx } }, |
6200 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
5824 | }, |
6201 | }, |
5825 | 6202 | ||
Line 5826... | Line 6203... | ||
5826 | /* PREFIX_VEX_0F38BB */ |
6203 | /* PREFIX_VEX_0F38BB */ |
5827 | { |
6204 | { |
5828 | { Bad_Opcode }, |
6205 | { Bad_Opcode }, |
Line 6079... | Line 6456... | ||
6079 | 6456 | ||
6080 | /* PREFIX_VEX_0F3A1D */ |
6457 | /* PREFIX_VEX_0F3A1D */ |
6081 | { |
6458 | { |
6082 | { Bad_Opcode }, |
6459 | { Bad_Opcode }, |
6083 | { Bad_Opcode }, |
6460 | { Bad_Opcode }, |
6084 | { "vcvtps2ph", { EXxmmq, XM, Ib } }, |
6461 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
Line 6085... | Line 6462... | ||
6085 | }, |
6462 | }, |
6086 | 6463 | ||
6087 | /* PREFIX_VEX_0F3A20 */ |
6464 | /* PREFIX_VEX_0F3A20 */ |
Line 6110... | Line 6487... | ||
6110 | { Bad_Opcode }, |
6487 | { Bad_Opcode }, |
6111 | { Bad_Opcode }, |
6488 | { Bad_Opcode }, |
6112 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, |
6489 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, |
6113 | }, |
6490 | }, |
Line -... | Line 6491... | ||
- | 6491 | ||
- | 6492 | /* PREFIX_VEX_0F3A31 */ |
|
- | 6493 | { |
|
- | 6494 | { Bad_Opcode }, |
|
- | 6495 | { Bad_Opcode }, |
|
- | 6496 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, |
|
- | 6497 | }, |
|
6114 | 6498 | ||
6115 | /* PREFIX_VEX_0F3A32 */ |
6499 | /* PREFIX_VEX_0F3A32 */ |
6116 | { |
6500 | { |
6117 | { Bad_Opcode }, |
6501 | { Bad_Opcode }, |
6118 | { Bad_Opcode }, |
6502 | { Bad_Opcode }, |
6119 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, |
6503 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, |
Line -... | Line 6504... | ||
- | 6504 | }, |
|
- | 6505 | ||
- | 6506 | /* PREFIX_VEX_0F3A33 */ |
|
- | 6507 | { |
|
- | 6508 | { Bad_Opcode }, |
|
- | 6509 | { Bad_Opcode }, |
|
- | 6510 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, |
|
6120 | }, |
6511 | }, |
6121 | 6512 | ||
6122 | /* PREFIX_VEX_0F3A38 */ |
6513 | /* PREFIX_VEX_0F3A38 */ |
6123 | { |
6514 | { |
6124 | { Bad_Opcode }, |
6515 | { Bad_Opcode }, |
Line 6205... | Line 6596... | ||
6205 | 6596 | ||
6206 | /* PREFIX_VEX_0F3A5C */ |
6597 | /* PREFIX_VEX_0F3A5C */ |
6207 | { |
6598 | { |
6208 | { Bad_Opcode }, |
6599 | { Bad_Opcode }, |
6209 | { Bad_Opcode }, |
6600 | { Bad_Opcode }, |
6210 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6601 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
Line 6211... | Line 6602... | ||
6211 | }, |
6602 | }, |
6212 | 6603 | ||
6213 | /* PREFIX_VEX_0F3A5D */ |
6604 | /* PREFIX_VEX_0F3A5D */ |
6214 | { |
6605 | { |
6215 | { Bad_Opcode }, |
6606 | { Bad_Opcode }, |
6216 | { Bad_Opcode }, |
6607 | { Bad_Opcode }, |
Line 6217... | Line 6608... | ||
6217 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6608 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6218 | }, |
6609 | }, |
6219 | 6610 | ||
6220 | /* PREFIX_VEX_0F3A5E */ |
6611 | /* PREFIX_VEX_0F3A5E */ |
6221 | { |
6612 | { |
6222 | { Bad_Opcode }, |
6613 | { Bad_Opcode }, |
Line 6223... | Line 6614... | ||
6223 | { Bad_Opcode }, |
6614 | { Bad_Opcode }, |
6224 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6615 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6225 | }, |
6616 | }, |
6226 | 6617 | ||
6227 | /* PREFIX_VEX_0F3A5F */ |
6618 | /* PREFIX_VEX_0F3A5F */ |
6228 | { |
6619 | { |
Line 6229... | Line 6620... | ||
6229 | { Bad_Opcode }, |
6620 | { Bad_Opcode }, |
6230 | { Bad_Opcode }, |
6621 | { Bad_Opcode }, |
6231 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6622 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
Line 6262... | Line 6653... | ||
6262 | 6653 | ||
6263 | /* PREFIX_VEX_0F3A68 */ |
6654 | /* PREFIX_VEX_0F3A68 */ |
6264 | { |
6655 | { |
6265 | { Bad_Opcode }, |
6656 | { Bad_Opcode }, |
6266 | { Bad_Opcode }, |
6657 | { Bad_Opcode }, |
6267 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6658 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
Line 6268... | Line 6659... | ||
6268 | }, |
6659 | }, |
6269 | 6660 | ||
6270 | /* PREFIX_VEX_0F3A69 */ |
6661 | /* PREFIX_VEX_0F3A69 */ |
6271 | { |
6662 | { |
6272 | { Bad_Opcode }, |
6663 | { Bad_Opcode }, |
6273 | { Bad_Opcode }, |
6664 | { Bad_Opcode }, |
Line 6274... | Line 6665... | ||
6274 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6665 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6275 | }, |
6666 | }, |
6276 | 6667 | ||
Line 6290... | Line 6681... | ||
6290 | 6681 | ||
6291 | /* PREFIX_VEX_0F3A6C */ |
6682 | /* PREFIX_VEX_0F3A6C */ |
6292 | { |
6683 | { |
6293 | { Bad_Opcode }, |
6684 | { Bad_Opcode }, |
6294 | { Bad_Opcode }, |
6685 | { Bad_Opcode }, |
6295 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6686 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
Line 6296... | Line 6687... | ||
6296 | }, |
6687 | }, |
6297 | 6688 | ||
6298 | /* PREFIX_VEX_0F3A6D */ |
6689 | /* PREFIX_VEX_0F3A6D */ |
6299 | { |
6690 | { |
6300 | { Bad_Opcode }, |
6691 | { Bad_Opcode }, |
6301 | { Bad_Opcode }, |
6692 | { Bad_Opcode }, |
Line 6302... | Line 6693... | ||
6302 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6693 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6303 | }, |
6694 | }, |
6304 | 6695 | ||
Line 6318... | Line 6709... | ||
6318 | 6709 | ||
6319 | /* PREFIX_VEX_0F3A78 */ |
6710 | /* PREFIX_VEX_0F3A78 */ |
6320 | { |
6711 | { |
6321 | { Bad_Opcode }, |
6712 | { Bad_Opcode }, |
6322 | { Bad_Opcode }, |
6713 | { Bad_Opcode }, |
6323 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6714 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
Line 6324... | Line 6715... | ||
6324 | }, |
6715 | }, |
6325 | 6716 | ||
6326 | /* PREFIX_VEX_0F3A79 */ |
6717 | /* PREFIX_VEX_0F3A79 */ |
6327 | { |
6718 | { |
6328 | { Bad_Opcode }, |
6719 | { Bad_Opcode }, |
6329 | { Bad_Opcode }, |
6720 | { Bad_Opcode }, |
Line 6330... | Line 6721... | ||
6330 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6721 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6331 | }, |
6722 | }, |
6332 | 6723 | ||
Line 6346... | Line 6737... | ||
6346 | 6737 | ||
6347 | /* PREFIX_VEX_0F3A7C */ |
6738 | /* PREFIX_VEX_0F3A7C */ |
6348 | { |
6739 | { |
6349 | { Bad_Opcode }, |
6740 | { Bad_Opcode }, |
6350 | { Bad_Opcode }, |
6741 | { Bad_Opcode }, |
6351 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6742 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6352 | { Bad_Opcode }, |
6743 | { Bad_Opcode }, |
Line 6353... | Line 6744... | ||
6353 | }, |
6744 | }, |
6354 | 6745 | ||
6355 | /* PREFIX_VEX_0F3A7D */ |
6746 | /* PREFIX_VEX_0F3A7D */ |
6356 | { |
6747 | { |
6357 | { Bad_Opcode }, |
6748 | { Bad_Opcode }, |
6358 | { Bad_Opcode }, |
6749 | { Bad_Opcode }, |
Line 6359... | Line 6750... | ||
6359 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6750 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
6360 | }, |
6751 | }, |
6361 | 6752 | ||
Line 6394... | Line 6785... | ||
6394 | }; |
6785 | }; |
Line 6395... | Line 6786... | ||
6395 | 6786 | ||
6396 | static const struct dis386 x86_64_table[][2] = { |
6787 | static const struct dis386 x86_64_table[][2] = { |
6397 | /* X86_64_06 */ |
6788 | /* X86_64_06 */ |
6398 | { |
6789 | { |
6399 | { "pushP", { es } }, |
6790 | { "pushP", { es }, 0 }, |
Line 6400... | Line 6791... | ||
6400 | }, |
6791 | }, |
6401 | 6792 | ||
6402 | /* X86_64_07 */ |
6793 | /* X86_64_07 */ |
6403 | { |
6794 | { |
Line 6404... | Line 6795... | ||
6404 | { "popP", { es } }, |
6795 | { "popP", { es }, 0 }, |
6405 | }, |
6796 | }, |
6406 | 6797 | ||
6407 | /* X86_64_0D */ |
6798 | /* X86_64_0D */ |
Line 6408... | Line 6799... | ||
6408 | { |
6799 | { |
6409 | { "pushP", { cs } }, |
6800 | { "pushP", { cs }, 0 }, |
6410 | }, |
6801 | }, |
6411 | 6802 | ||
Line 6412... | Line 6803... | ||
6412 | /* X86_64_16 */ |
6803 | /* X86_64_16 */ |
6413 | { |
6804 | { |
6414 | { "pushP", { ss } }, |
6805 | { "pushP", { ss }, 0 }, |
6415 | }, |
6806 | }, |
Line 6416... | Line 6807... | ||
6416 | 6807 | ||
6417 | /* X86_64_17 */ |
6808 | /* X86_64_17 */ |
6418 | { |
6809 | { |
6419 | { "popP", { ss } }, |
6810 | { "popP", { ss }, 0 }, |
Line 6420... | Line 6811... | ||
6420 | }, |
6811 | }, |
6421 | 6812 | ||
6422 | /* X86_64_1E */ |
6813 | /* X86_64_1E */ |
6423 | { |
6814 | { |
Line 6424... | Line 6815... | ||
6424 | { "pushP", { ds } }, |
6815 | { "pushP", { ds }, 0 }, |
6425 | }, |
6816 | }, |
6426 | 6817 | ||
6427 | /* X86_64_1F */ |
6818 | /* X86_64_1F */ |
Line 6428... | Line 6819... | ||
6428 | { |
6819 | { |
6429 | { "popP", { ds } }, |
6820 | { "popP", { ds }, 0 }, |
6430 | }, |
6821 | }, |
6431 | 6822 | ||
Line 6432... | Line 6823... | ||
6432 | /* X86_64_27 */ |
6823 | /* X86_64_27 */ |
6433 | { |
6824 | { |
6434 | { "daa", { XX } }, |
6825 | { "daa", { XX }, 0 }, |
6435 | }, |
6826 | }, |
Line 6436... | Line 6827... | ||
6436 | 6827 | ||
6437 | /* X86_64_2F */ |
6828 | /* X86_64_2F */ |
6438 | { |
6829 | { |
6439 | { "das", { XX } }, |
6830 | { "das", { XX }, 0 }, |
Line 6440... | Line 6831... | ||
6440 | }, |
6831 | }, |
6441 | 6832 | ||
6442 | /* X86_64_37 */ |
6833 | /* X86_64_37 */ |
6443 | { |
6834 | { |
Line 6444... | Line 6835... | ||
6444 | { "aaa", { XX } }, |
6835 | { "aaa", { XX }, 0 }, |
6445 | }, |
6836 | }, |
6446 | 6837 | ||
6447 | /* X86_64_3F */ |
6838 | /* X86_64_3F */ |
Line 6448... | Line 6839... | ||
6448 | { |
6839 | { |
6449 | { "aas", { XX } }, |
6840 | { "aas", { XX }, 0 }, |
6450 | }, |
6841 | }, |
6451 | 6842 | ||
6452 | /* X86_64_60 */ |
6843 | /* X86_64_60 */ |
Line 6453... | Line 6844... | ||
6453 | { |
6844 | { |
6454 | { "pushaP", { XX } }, |
6845 | { "pushaP", { XX }, 0 }, |
6455 | }, |
6846 | }, |
6456 | 6847 | ||
6457 | /* X86_64_61 */ |
6848 | /* X86_64_61 */ |
Line 6458... | Line 6849... | ||
6458 | { |
6849 | { |
6459 | { "popaP", { XX } }, |
6850 | { "popaP", { XX }, 0 }, |
6460 | }, |
6851 | }, |
6461 | 6852 | ||
6462 | /* X86_64_62 */ |
6853 | /* X86_64_62 */ |
Line 6463... | Line 6854... | ||
6463 | { |
6854 | { |
6464 | { MOD_TABLE (MOD_62_32BIT) }, |
6855 | { MOD_TABLE (MOD_62_32BIT) }, |
6465 | { EVEX_TABLE (EVEX_0F) }, |
6856 | { EVEX_TABLE (EVEX_0F) }, |
6466 | }, |
6857 | }, |
6467 | 6858 | ||
Line 6468... | Line 6859... | ||
6468 | /* X86_64_63 */ |
6859 | /* X86_64_63 */ |
6469 | { |
6860 | { |
6470 | { "arpl", { Ew, Gw } }, |
6861 | { "arpl", { Ew, Gw }, 0 }, |
6471 | { "movs{lq|xd}", { Gv, Ed } }, |
6862 | { "movs{lq|xd}", { Gv, Ed }, 0 }, |
Line 6472... | Line 6863... | ||
6472 | }, |
6863 | }, |
6473 | 6864 | ||
6474 | /* X86_64_6D */ |
6865 | /* X86_64_6D */ |
Line 6500... | Line 6891... | ||
6500 | { VEX_C5_TABLE (VEX_0F) }, |
6891 | { VEX_C5_TABLE (VEX_0F) }, |
6501 | }, |
6892 | }, |
Line 6502... | Line 6893... | ||
6502 | 6893 | ||
6503 | /* X86_64_CE */ |
6894 | /* X86_64_CE */ |
6504 | { |
6895 | { |
6505 | { "into", { XX } }, |
6896 | { "into", { XX }, 0 }, |
Line 6506... | Line 6897... | ||
6506 | }, |
6897 | }, |
6507 | 6898 | ||
6508 | /* X86_64_D4 */ |
6899 | /* X86_64_D4 */ |
6509 | { |
6900 | { |
Line 6510... | Line 6901... | ||
6510 | { "aam", { Ib } }, |
6901 | { "aam", { Ib }, 0 }, |
6511 | }, |
6902 | }, |
6512 | 6903 | ||
- | 6904 | /* X86_64_D5 */ |
|
- | 6905 | { |
|
- | 6906 | { "aad", { Ib }, 0 }, |
|
- | 6907 | }, |
|
- | 6908 | ||
- | 6909 | /* X86_64_E8 */ |
|
- | 6910 | { |
|
- | 6911 | { "callP", { Jv, BND }, 0 }, |
|
- | 6912 | { "call@", { Jv, BND }, 0 } |
|
- | 6913 | }, |
|
- | 6914 | ||
- | 6915 | /* X86_64_E9 */ |
|
6513 | /* X86_64_D5 */ |
6916 | { |
Line 6514... | Line 6917... | ||
6514 | { |
6917 | { "jmpP", { Jv, BND }, 0 }, |
6515 | { "aad", { Ib } }, |
6918 | { "jmp@", { Jv, BND }, 0 } |
6516 | }, |
6919 | }, |
6517 | 6920 | ||
Line 6518... | Line 6921... | ||
6518 | /* X86_64_EA */ |
6921 | /* X86_64_EA */ |
6519 | { |
6922 | { |
6520 | { "Jjmp{T|}", { Ap } }, |
6923 | { "Jjmp{T|}", { Ap }, 0 }, |
6521 | }, |
6924 | }, |
6522 | 6925 | ||
Line 6523... | Line 6926... | ||
6523 | /* X86_64_0F01_REG_0 */ |
6926 | /* X86_64_0F01_REG_0 */ |
6524 | { |
6927 | { |
6525 | { "sgdt{Q|IQ}", { M } }, |
6928 | { "sgdt{Q|IQ}", { M }, 0 }, |
6526 | { "sgdt", { M } }, |
6929 | { "sgdt", { M }, 0 }, |
6527 | }, |
6930 | }, |
Line 6528... | Line 6931... | ||
6528 | 6931 | ||
6529 | /* X86_64_0F01_REG_1 */ |
6932 | /* X86_64_0F01_REG_1 */ |
6530 | { |
6933 | { |
6531 | { "sidt{Q|IQ}", { M } }, |
6934 | { "sidt{Q|IQ}", { M }, 0 }, |
6532 | { "sidt", { M } }, |
6935 | { "sidt", { M }, 0 }, |
Line 6533... | Line 6936... | ||
6533 | }, |
6936 | }, |
6534 | 6937 | ||
6535 | /* X86_64_0F01_REG_2 */ |
6938 | /* X86_64_0F01_REG_2 */ |
6536 | { |
6939 | { |
6537 | { "lgdt{Q|Q}", { M } }, |
6940 | { "lgdt{Q|Q}", { M }, 0 }, |
6538 | { "lgdt", { M } }, |
6941 | { "lgdt", { M }, 0 }, |
Line 6539... | Line 6942... | ||
6539 | }, |
6942 | }, |
Line 6540... | Line 6943... | ||
6540 | 6943 | ||
6541 | /* X86_64_0F01_REG_3 */ |
6944 | /* X86_64_0F01_REG_3 */ |
6542 | { |
6945 | { |
6543 | { "lidt{Q|Q}", { M } }, |
6946 | { "lidt{Q|Q}", { M }, 0 }, |
6544 | { "lidt", { M } }, |
6947 | { "lidt", { M }, 0 }, |
6545 | }, |
6948 | }, |
6546 | }; |
6949 | }; |
6547 | 6950 | ||
6548 | static const struct dis386 three_byte_table[][256] = { |
6951 | static const struct dis386 three_byte_table[][256] = { |
6549 | 6952 | ||
6550 | /* THREE_BYTE_0F38 */ |
6953 | /* THREE_BYTE_0F38 */ |
6551 | { |
6954 | { |
6552 | /* 00 */ |
6955 | /* 00 */ |
6553 | { "pshufb", { MX, EM } }, |
6956 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6554 | { "phaddw", { MX, EM } }, |
6957 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, |
6555 | { "phaddd", { MX, EM } }, |
6958 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, |
6556 | { "phaddsw", { MX, EM } }, |
6959 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, |
6557 | { "pmaddubsw", { MX, EM } }, |
6960 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, |
6558 | { "phsubw", { MX, EM } }, |
6961 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, |
6559 | { "phsubd", { MX, EM } }, |
6962 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, |
6560 | { "phsubsw", { MX, EM } }, |
6963 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, |
Line 6579... | Line 6982... | ||
6579 | /* 18 */ |
6982 | /* 18 */ |
6580 | { Bad_Opcode }, |
6983 | { Bad_Opcode }, |
6581 | { Bad_Opcode }, |
6984 | { Bad_Opcode }, |
6582 | { Bad_Opcode }, |
6985 | { Bad_Opcode }, |
6583 | { Bad_Opcode }, |
6986 | { Bad_Opcode }, |
6584 | { "pabsb", { MX, EM } }, |
6987 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6585 | { "pabsw", { MX, EM } }, |
6988 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, |
6586 | { "pabsd", { MX, EM } }, |
6989 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, |
6587 | { Bad_Opcode }, |
6990 | { Bad_Opcode }, |
6588 | /* 20 */ |
6991 | /* 20 */ |
6589 | { PREFIX_TABLE (PREFIX_0F3820) }, |
6992 | { PREFIX_TABLE (PREFIX_0F3820) }, |
6590 | { PREFIX_TABLE (PREFIX_0F3821) }, |
6993 | { PREFIX_TABLE (PREFIX_0F3821) }, |
6591 | { PREFIX_TABLE (PREFIX_0F3822) }, |
6994 | { PREFIX_TABLE (PREFIX_0F3822) }, |
Line 6855... | Line 7258... | ||
6855 | { PREFIX_TABLE (PREFIX_0F3A0A) }, |
7258 | { PREFIX_TABLE (PREFIX_0F3A0A) }, |
6856 | { PREFIX_TABLE (PREFIX_0F3A0B) }, |
7259 | { PREFIX_TABLE (PREFIX_0F3A0B) }, |
6857 | { PREFIX_TABLE (PREFIX_0F3A0C) }, |
7260 | { PREFIX_TABLE (PREFIX_0F3A0C) }, |
6858 | { PREFIX_TABLE (PREFIX_0F3A0D) }, |
7261 | { PREFIX_TABLE (PREFIX_0F3A0D) }, |
6859 | { PREFIX_TABLE (PREFIX_0F3A0E) }, |
7262 | { PREFIX_TABLE (PREFIX_0F3A0E) }, |
6860 | { "palignr", { MX, EM, Ib } }, |
7263 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
6861 | /* 10 */ |
7264 | /* 10 */ |
6862 | { Bad_Opcode }, |
7265 | { Bad_Opcode }, |
6863 | { Bad_Opcode }, |
7266 | { Bad_Opcode }, |
6864 | { Bad_Opcode }, |
7267 | { Bad_Opcode }, |
6865 | { Bad_Opcode }, |
7268 | { Bad_Opcode }, |
Line 7167... | Line 7570... | ||
7167 | { Bad_Opcode }, |
7570 | { Bad_Opcode }, |
7168 | { Bad_Opcode }, |
7571 | { Bad_Opcode }, |
7169 | { Bad_Opcode }, |
7572 | { Bad_Opcode }, |
7170 | { Bad_Opcode }, |
7573 | { Bad_Opcode }, |
7171 | /* 20 */ |
7574 | /* 20 */ |
7172 | { "ptest", { XX } }, |
7575 | { "ptest", { XX }, PREFIX_OPCODE }, |
7173 | { Bad_Opcode }, |
7576 | { Bad_Opcode }, |
7174 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, |
7175 | { Bad_Opcode }, |
7578 | { Bad_Opcode }, |
7176 | { Bad_Opcode }, |
7579 | { Bad_Opcode }, |
7177 | { Bad_Opcode }, |
7580 | { Bad_Opcode }, |
Line 7204... | Line 7607... | ||
7204 | { Bad_Opcode }, |
7607 | { Bad_Opcode }, |
7205 | { Bad_Opcode }, |
7608 | { Bad_Opcode }, |
7206 | { Bad_Opcode }, |
7609 | { Bad_Opcode }, |
7207 | /* 40 */ |
7610 | /* 40 */ |
7208 | { Bad_Opcode }, |
7611 | { Bad_Opcode }, |
7209 | { "phaddbw", { XM, EXq } }, |
7612 | { "phaddbw", { XM, EXq }, PREFIX_OPCODE }, |
7210 | { "phaddbd", { XM, EXq } }, |
7613 | { "phaddbd", { XM, EXq }, PREFIX_OPCODE }, |
7211 | { "phaddbq", { XM, EXq } }, |
7614 | { "phaddbq", { XM, EXq }, PREFIX_OPCODE }, |
7212 | { Bad_Opcode }, |
7615 | { Bad_Opcode }, |
7213 | { Bad_Opcode }, |
7616 | { Bad_Opcode }, |
7214 | { "phaddwd", { XM, EXq } }, |
7617 | { "phaddwd", { XM, EXq }, PREFIX_OPCODE }, |
7215 | { "phaddwq", { XM, EXq } }, |
7618 | { "phaddwq", { XM, EXq }, PREFIX_OPCODE }, |
7216 | /* 48 */ |
7619 | /* 48 */ |
7217 | { Bad_Opcode }, |
7620 | { Bad_Opcode }, |
7218 | { Bad_Opcode }, |
7621 | { Bad_Opcode }, |
7219 | { Bad_Opcode }, |
7622 | { Bad_Opcode }, |
7220 | { "phadddq", { XM, EXq } }, |
7623 | { "phadddq", { XM, EXq }, PREFIX_OPCODE }, |
7221 | { Bad_Opcode }, |
7624 | { Bad_Opcode }, |
7222 | { Bad_Opcode }, |
7625 | { Bad_Opcode }, |
7223 | { Bad_Opcode }, |
7626 | { Bad_Opcode }, |
7224 | { Bad_Opcode }, |
7627 | { Bad_Opcode }, |
7225 | /* 50 */ |
7628 | /* 50 */ |
7226 | { Bad_Opcode }, |
7629 | { Bad_Opcode }, |
7227 | { "phaddubw", { XM, EXq } }, |
7630 | { "phaddubw", { XM, EXq }, PREFIX_OPCODE }, |
7228 | { "phaddubd", { XM, EXq } }, |
7631 | { "phaddubd", { XM, EXq }, PREFIX_OPCODE }, |
7229 | { "phaddubq", { XM, EXq } }, |
7632 | { "phaddubq", { XM, EXq }, PREFIX_OPCODE }, |
7230 | { Bad_Opcode }, |
7633 | { Bad_Opcode }, |
7231 | { Bad_Opcode }, |
7634 | { Bad_Opcode }, |
7232 | { "phadduwd", { XM, EXq } }, |
7635 | { "phadduwd", { XM, EXq }, PREFIX_OPCODE }, |
7233 | { "phadduwq", { XM, EXq } }, |
7636 | { "phadduwq", { XM, EXq }, PREFIX_OPCODE }, |
7234 | /* 58 */ |
7637 | /* 58 */ |
7235 | { Bad_Opcode }, |
7638 | { Bad_Opcode }, |
7236 | { Bad_Opcode }, |
7639 | { Bad_Opcode }, |
7237 | { Bad_Opcode }, |
7640 | { Bad_Opcode }, |
7238 | { "phaddudq", { XM, EXq } }, |
7641 | { "phaddudq", { XM, EXq }, PREFIX_OPCODE }, |
7239 | { Bad_Opcode }, |
7642 | { Bad_Opcode }, |
7240 | { Bad_Opcode }, |
7643 | { Bad_Opcode }, |
7241 | { Bad_Opcode }, |
7644 | { Bad_Opcode }, |
7242 | { Bad_Opcode }, |
7645 | { Bad_Opcode }, |
7243 | /* 60 */ |
7646 | /* 60 */ |
7244 | { Bad_Opcode }, |
7647 | { Bad_Opcode }, |
7245 | { "phsubbw", { XM, EXq } }, |
7648 | { "phsubbw", { XM, EXq }, PREFIX_OPCODE }, |
7246 | { "phsubbd", { XM, EXq } }, |
7649 | { "phsubbd", { XM, EXq }, PREFIX_OPCODE }, |
7247 | { "phsubbq", { XM, EXq } }, |
7650 | { "phsubbq", { XM, EXq }, PREFIX_OPCODE }, |
7248 | { Bad_Opcode }, |
7651 | { Bad_Opcode }, |
7249 | { Bad_Opcode }, |
7652 | { Bad_Opcode }, |
7250 | { Bad_Opcode }, |
7653 | { Bad_Opcode }, |
7251 | { Bad_Opcode }, |
7654 | { Bad_Opcode }, |
7252 | /* 68 */ |
7655 | /* 68 */ |
Line 7574... | Line 7977... | ||
7574 | { Bad_Opcode }, |
7977 | { Bad_Opcode }, |
7575 | { Bad_Opcode }, |
7978 | { Bad_Opcode }, |
7576 | { Bad_Opcode }, |
7979 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, |
7980 | { Bad_Opcode }, |
7578 | { Bad_Opcode }, |
7981 | { Bad_Opcode }, |
7579 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7982 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7580 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7983 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7581 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7984 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7582 | /* 88 */ |
7985 | /* 88 */ |
7583 | { Bad_Opcode }, |
7986 | { Bad_Opcode }, |
7584 | { Bad_Opcode }, |
7987 | { Bad_Opcode }, |
7585 | { Bad_Opcode }, |
7988 | { Bad_Opcode }, |
7586 | { Bad_Opcode }, |
7989 | { Bad_Opcode }, |
7587 | { Bad_Opcode }, |
7990 | { Bad_Opcode }, |
7588 | { Bad_Opcode }, |
7991 | { Bad_Opcode }, |
7589 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7992 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7590 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7993 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7591 | /* 90 */ |
7994 | /* 90 */ |
7592 | { Bad_Opcode }, |
7995 | { Bad_Opcode }, |
7593 | { Bad_Opcode }, |
7996 | { Bad_Opcode }, |
7594 | { Bad_Opcode }, |
7997 | { Bad_Opcode }, |
7595 | { Bad_Opcode }, |
7998 | { Bad_Opcode }, |
7596 | { Bad_Opcode }, |
7999 | { Bad_Opcode }, |
7597 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8000 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7598 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8001 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7599 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8002 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7600 | /* 98 */ |
8003 | /* 98 */ |
7601 | { Bad_Opcode }, |
8004 | { Bad_Opcode }, |
7602 | { Bad_Opcode }, |
8005 | { Bad_Opcode }, |
7603 | { Bad_Opcode }, |
8006 | { Bad_Opcode }, |
7604 | { Bad_Opcode }, |
8007 | { Bad_Opcode }, |
7605 | { Bad_Opcode }, |
8008 | { Bad_Opcode }, |
7606 | { Bad_Opcode }, |
8009 | { Bad_Opcode }, |
7607 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8010 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7608 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8011 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7609 | /* a0 */ |
8012 | /* a0 */ |
7610 | { Bad_Opcode }, |
8013 | { Bad_Opcode }, |
7611 | { Bad_Opcode }, |
8014 | { Bad_Opcode }, |
7612 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8015 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7613 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8016 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7614 | { Bad_Opcode }, |
8017 | { Bad_Opcode }, |
7615 | { Bad_Opcode }, |
8018 | { Bad_Opcode }, |
7616 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8019 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7617 | { Bad_Opcode }, |
8020 | { Bad_Opcode }, |
7618 | /* a8 */ |
8021 | /* a8 */ |
7619 | { Bad_Opcode }, |
8022 | { Bad_Opcode }, |
7620 | { Bad_Opcode }, |
8023 | { Bad_Opcode }, |
7621 | { Bad_Opcode }, |
8024 | { Bad_Opcode }, |
Line 7629... | Line 8032... | ||
7629 | { Bad_Opcode }, |
8032 | { Bad_Opcode }, |
7630 | { Bad_Opcode }, |
8033 | { Bad_Opcode }, |
7631 | { Bad_Opcode }, |
8034 | { Bad_Opcode }, |
7632 | { Bad_Opcode }, |
8035 | { Bad_Opcode }, |
7633 | { Bad_Opcode }, |
8036 | { Bad_Opcode }, |
7634 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
8037 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7635 | { Bad_Opcode }, |
8038 | { Bad_Opcode }, |
7636 | /* b8 */ |
8039 | /* b8 */ |
7637 | { Bad_Opcode }, |
8040 | { Bad_Opcode }, |
7638 | { Bad_Opcode }, |
8041 | { Bad_Opcode }, |
7639 | { Bad_Opcode }, |
8042 | { Bad_Opcode }, |
Line 7641... | Line 8044... | ||
7641 | { Bad_Opcode }, |
8044 | { Bad_Opcode }, |
7642 | { Bad_Opcode }, |
8045 | { Bad_Opcode }, |
7643 | { Bad_Opcode }, |
8046 | { Bad_Opcode }, |
7644 | { Bad_Opcode }, |
8047 | { Bad_Opcode }, |
7645 | /* c0 */ |
8048 | /* c0 */ |
7646 | { "vprotb", { XM, Vex_2src_1, Ib } }, |
8049 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7647 | { "vprotw", { XM, Vex_2src_1, Ib } }, |
8050 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, |
7648 | { "vprotd", { XM, Vex_2src_1, Ib } }, |
8051 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, |
7649 | { "vprotq", { XM, Vex_2src_1, Ib } }, |
8052 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, |
7650 | { Bad_Opcode }, |
8053 | { Bad_Opcode }, |
7651 | { Bad_Opcode }, |
8054 | { Bad_Opcode }, |
7652 | { Bad_Opcode }, |
8055 | { Bad_Opcode }, |
7653 | { Bad_Opcode }, |
8056 | { Bad_Opcode }, |
7654 | /* c8 */ |
8057 | /* c8 */ |
Line 7862... | Line 8265... | ||
7862 | { Bad_Opcode }, |
8265 | { Bad_Opcode }, |
7863 | { Bad_Opcode }, |
8266 | { Bad_Opcode }, |
7864 | /* 80 */ |
8267 | /* 80 */ |
7865 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
8268 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7866 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, |
8269 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, |
7867 | { "vfrczss", { XM, EXd } }, |
8270 | { "vfrczss", { XM, EXd }, 0 }, |
7868 | { "vfrczsd", { XM, EXq } }, |
8271 | { "vfrczsd", { XM, EXq }, 0 }, |
7869 | { Bad_Opcode }, |
8272 | { Bad_Opcode }, |
7870 | { Bad_Opcode }, |
8273 | { Bad_Opcode }, |
7871 | { Bad_Opcode }, |
8274 | { Bad_Opcode }, |
7872 | { Bad_Opcode }, |
8275 | { Bad_Opcode }, |
7873 | /* 88 */ |
8276 | /* 88 */ |
Line 7878... | Line 8281... | ||
7878 | { Bad_Opcode }, |
8281 | { Bad_Opcode }, |
7879 | { Bad_Opcode }, |
8282 | { Bad_Opcode }, |
7880 | { Bad_Opcode }, |
8283 | { Bad_Opcode }, |
7881 | { Bad_Opcode }, |
8284 | { Bad_Opcode }, |
7882 | /* 90 */ |
8285 | /* 90 */ |
7883 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, |
8286 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7884 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, |
8287 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7885 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, |
8288 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7886 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, |
8289 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7887 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, |
8290 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7888 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, |
8291 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7889 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, |
8292 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7890 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, |
8293 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7891 | /* 98 */ |
8294 | /* 98 */ |
7892 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, |
8295 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7893 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, |
8296 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7894 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, |
8297 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7895 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, |
8298 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7896 | { Bad_Opcode }, |
8299 | { Bad_Opcode }, |
7897 | { Bad_Opcode }, |
8300 | { Bad_Opcode }, |
7898 | { Bad_Opcode }, |
8301 | { Bad_Opcode }, |
7899 | { Bad_Opcode }, |
8302 | { Bad_Opcode }, |
7900 | /* a0 */ |
8303 | /* a0 */ |
Line 7933... | Line 8336... | ||
7933 | { Bad_Opcode }, |
8336 | { Bad_Opcode }, |
7934 | { Bad_Opcode }, |
8337 | { Bad_Opcode }, |
7935 | { Bad_Opcode }, |
8338 | { Bad_Opcode }, |
7936 | /* c0 */ |
8339 | /* c0 */ |
7937 | { Bad_Opcode }, |
8340 | { Bad_Opcode }, |
7938 | { "vphaddbw", { XM, EXxmm } }, |
8341 | { "vphaddbw", { XM, EXxmm }, 0 }, |
7939 | { "vphaddbd", { XM, EXxmm } }, |
8342 | { "vphaddbd", { XM, EXxmm }, 0 }, |
7940 | { "vphaddbq", { XM, EXxmm } }, |
8343 | { "vphaddbq", { XM, EXxmm }, 0 }, |
7941 | { Bad_Opcode }, |
8344 | { Bad_Opcode }, |
7942 | { Bad_Opcode }, |
8345 | { Bad_Opcode }, |
7943 | { "vphaddwd", { XM, EXxmm } }, |
8346 | { "vphaddwd", { XM, EXxmm }, 0 }, |
7944 | { "vphaddwq", { XM, EXxmm } }, |
8347 | { "vphaddwq", { XM, EXxmm }, 0 }, |
7945 | /* c8 */ |
8348 | /* c8 */ |
7946 | { Bad_Opcode }, |
8349 | { Bad_Opcode }, |
7947 | { Bad_Opcode }, |
8350 | { Bad_Opcode }, |
7948 | { Bad_Opcode }, |
8351 | { Bad_Opcode }, |
7949 | { "vphadddq", { XM, EXxmm } }, |
8352 | { "vphadddq", { XM, EXxmm }, 0 }, |
7950 | { Bad_Opcode }, |
8353 | { Bad_Opcode }, |
7951 | { Bad_Opcode }, |
8354 | { Bad_Opcode }, |
7952 | { Bad_Opcode }, |
8355 | { Bad_Opcode }, |
7953 | { Bad_Opcode }, |
8356 | { Bad_Opcode }, |
7954 | /* d0 */ |
8357 | /* d0 */ |
7955 | { Bad_Opcode }, |
8358 | { Bad_Opcode }, |
7956 | { "vphaddubw", { XM, EXxmm } }, |
8359 | { "vphaddubw", { XM, EXxmm }, 0 }, |
7957 | { "vphaddubd", { XM, EXxmm } }, |
8360 | { "vphaddubd", { XM, EXxmm }, 0 }, |
7958 | { "vphaddubq", { XM, EXxmm } }, |
8361 | { "vphaddubq", { XM, EXxmm }, 0 }, |
7959 | { Bad_Opcode }, |
8362 | { Bad_Opcode }, |
7960 | { Bad_Opcode }, |
8363 | { Bad_Opcode }, |
7961 | { "vphadduwd", { XM, EXxmm } }, |
8364 | { "vphadduwd", { XM, EXxmm }, 0 }, |
7962 | { "vphadduwq", { XM, EXxmm } }, |
8365 | { "vphadduwq", { XM, EXxmm }, 0 }, |
7963 | /* d8 */ |
8366 | /* d8 */ |
7964 | { Bad_Opcode }, |
8367 | { Bad_Opcode }, |
7965 | { Bad_Opcode }, |
8368 | { Bad_Opcode }, |
7966 | { Bad_Opcode }, |
8369 | { Bad_Opcode }, |
7967 | { "vphaddudq", { XM, EXxmm } }, |
8370 | { "vphaddudq", { XM, EXxmm }, 0 }, |
7968 | { Bad_Opcode }, |
8371 | { Bad_Opcode }, |
7969 | { Bad_Opcode }, |
8372 | { Bad_Opcode }, |
7970 | { Bad_Opcode }, |
8373 | { Bad_Opcode }, |
7971 | { Bad_Opcode }, |
8374 | { Bad_Opcode }, |
7972 | /* e0 */ |
8375 | /* e0 */ |
7973 | { Bad_Opcode }, |
8376 | { Bad_Opcode }, |
7974 | { "vphsubbw", { XM, EXxmm } }, |
8377 | { "vphsubbw", { XM, EXxmm }, 0 }, |
7975 | { "vphsubwd", { XM, EXxmm } }, |
8378 | { "vphsubwd", { XM, EXxmm }, 0 }, |
7976 | { "vphsubdq", { XM, EXxmm } }, |
8379 | { "vphsubdq", { XM, EXxmm }, 0 }, |
7977 | { Bad_Opcode }, |
8380 | { Bad_Opcode }, |
7978 | { Bad_Opcode }, |
8381 | { Bad_Opcode }, |
7979 | { Bad_Opcode }, |
8382 | { Bad_Opcode }, |
7980 | { Bad_Opcode }, |
8383 | { Bad_Opcode }, |
7981 | /* e8 */ |
8384 | /* e8 */ |
Line 8025... | Line 8428... | ||
8025 | { Bad_Opcode }, |
8428 | { Bad_Opcode }, |
8026 | { Bad_Opcode }, |
8429 | { Bad_Opcode }, |
8027 | { Bad_Opcode }, |
8430 | { Bad_Opcode }, |
8028 | { Bad_Opcode }, |
8431 | { Bad_Opcode }, |
8029 | /* 10 */ |
8432 | /* 10 */ |
8030 | { "bextr", { Gv, Ev, Iq } }, |
8433 | { "bextr", { Gv, Ev, Iq }, 0 }, |
8031 | { Bad_Opcode }, |
8434 | { Bad_Opcode }, |
8032 | { REG_TABLE (REG_XOP_LWP) }, |
8435 | { REG_TABLE (REG_XOP_LWP) }, |
8033 | { Bad_Opcode }, |
8436 | { Bad_Opcode }, |
8034 | { Bad_Opcode }, |
8437 | { Bad_Opcode }, |
8035 | { Bad_Opcode }, |
8438 | { Bad_Opcode }, |
Line 8384... | Line 8787... | ||
8384 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, |
8385 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, |
8386 | /* 48 */ |
8789 | /* 48 */ |
8387 | { Bad_Opcode }, |
8790 | { Bad_Opcode }, |
8388 | { Bad_Opcode }, |
8791 | { Bad_Opcode }, |
8389 | { Bad_Opcode }, |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
8390 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
8391 | { Bad_Opcode }, |
8794 | { Bad_Opcode }, |
8392 | { Bad_Opcode }, |
8795 | { Bad_Opcode }, |
8393 | { Bad_Opcode }, |
8796 | { Bad_Opcode }, |
8394 | { Bad_Opcode }, |
8797 | { Bad_Opcode }, |
8395 | /* 50 */ |
8798 | /* 50 */ |
8396 | { MOD_TABLE (MOD_VEX_0F50) }, |
8799 | { MOD_TABLE (MOD_VEX_0F50) }, |
8397 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, |
8800 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, |
8398 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, |
8399 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, |
8802 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, |
8400 | { "vandpX", { XM, Vex, EXx } }, |
8803 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8401 | { "vandnpX", { XM, Vex, EXx } }, |
8804 | { "vandnpX", { XM, Vex, EXx }, 0 }, |
8402 | { "vorpX", { XM, Vex, EXx } }, |
8805 | { "vorpX", { XM, Vex, EXx }, 0 }, |
8403 | { "vxorpX", { XM, Vex, EXx } }, |
8806 | { "vxorpX", { XM, Vex, EXx }, 0 }, |
8404 | /* 58 */ |
8807 | /* 58 */ |
8405 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8406 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, |
8407 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, |
8810 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, |
8408 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, |
8811 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, |
Line 8473... | Line 8876... | ||
8473 | { Bad_Opcode }, |
8876 | { Bad_Opcode }, |
8474 | { Bad_Opcode }, |
8877 | { Bad_Opcode }, |
8475 | { Bad_Opcode }, |
8878 | { Bad_Opcode }, |
8476 | /* 98 */ |
8879 | /* 98 */ |
8477 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
8880 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
8478 | { Bad_Opcode }, |
8881 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
8479 | { Bad_Opcode }, |
8882 | { Bad_Opcode }, |
8480 | { Bad_Opcode }, |
8883 | { Bad_Opcode }, |
8481 | { Bad_Opcode }, |
8884 | { Bad_Opcode }, |
8482 | { Bad_Opcode }, |
8885 | { Bad_Opcode }, |
8483 | { Bad_Opcode }, |
8886 | { Bad_Opcode }, |
Line 8523... | Line 8926... | ||
8523 | { Bad_Opcode }, |
8926 | { Bad_Opcode }, |
8524 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
8927 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
8525 | { Bad_Opcode }, |
8928 | { Bad_Opcode }, |
8526 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8929 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8527 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, |
8930 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, |
8528 | { "vshufpX", { XM, Vex, EXx, Ib } }, |
8931 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
8529 | { Bad_Opcode }, |
8932 | { Bad_Opcode }, |
8530 | /* c8 */ |
8933 | /* c8 */ |
8531 | { Bad_Opcode }, |
8934 | { Bad_Opcode }, |
8532 | { Bad_Opcode }, |
8935 | { Bad_Opcode }, |
8533 | { Bad_Opcode }, |
8936 | { Bad_Opcode }, |
Line 8938... | Line 9341... | ||
8938 | { Bad_Opcode }, |
9341 | { Bad_Opcode }, |
8939 | { Bad_Opcode }, |
9342 | { Bad_Opcode }, |
8940 | { Bad_Opcode }, |
9343 | { Bad_Opcode }, |
8941 | /* 30 */ |
9344 | /* 30 */ |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
9345 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
8943 | { Bad_Opcode }, |
9346 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
9347 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
8945 | { Bad_Opcode }, |
9348 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
8946 | { Bad_Opcode }, |
9349 | { Bad_Opcode }, |
8947 | { Bad_Opcode }, |
9350 | { Bad_Opcode }, |
8948 | { Bad_Opcode }, |
9351 | { Bad_Opcode }, |
8949 | { Bad_Opcode }, |
9352 | { Bad_Opcode }, |
8950 | /* 38 */ |
9353 | /* 38 */ |
Line 9243... | Line 9646... | ||
9243 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
9646 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
9244 | }, |
9647 | }, |
Line 9245... | Line 9648... | ||
9245 | 9648 | ||
9246 | /* VEX_LEN_0F2A_P_1 */ |
9649 | /* VEX_LEN_0F2A_P_1 */ |
9247 | { |
9650 | { |
9248 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, |
9651 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9249 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, |
9652 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
Line 9250... | Line 9653... | ||
9250 | }, |
9653 | }, |
9251 | 9654 | ||
9252 | /* VEX_LEN_0F2A_P_3 */ |
9655 | /* VEX_LEN_0F2A_P_3 */ |
9253 | { |
9656 | { |
9254 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, |
9657 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
Line 9255... | Line 9658... | ||
9255 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, |
9658 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9256 | }, |
9659 | }, |
9257 | 9660 | ||
9258 | /* VEX_LEN_0F2C_P_1 */ |
9661 | /* VEX_LEN_0F2C_P_1 */ |
9259 | { |
9662 | { |
Line 9260... | Line 9663... | ||
9260 | { "vcvttss2siY", { Gv, EXdScalar } }, |
9663 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
9261 | { "vcvttss2siY", { Gv, EXdScalar } }, |
9664 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
9262 | }, |
9665 | }, |
9263 | 9666 | ||
9264 | /* VEX_LEN_0F2C_P_3 */ |
9667 | /* VEX_LEN_0F2C_P_3 */ |
Line 9265... | Line 9668... | ||
9265 | { |
9668 | { |
9266 | { "vcvttsd2siY", { Gv, EXqScalar } }, |
9669 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
9267 | { "vcvttsd2siY", { Gv, EXqScalar } }, |
9670 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
9268 | }, |
9671 | }, |
9269 | 9672 | ||
Line 9270... | Line 9673... | ||
9270 | /* VEX_LEN_0F2D_P_1 */ |
9673 | /* VEX_LEN_0F2D_P_1 */ |
9271 | { |
9674 | { |
9272 | { "vcvtss2siY", { Gv, EXdScalar } }, |
9675 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
9273 | { "vcvtss2siY", { Gv, EXdScalar } }, |
9676 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
9274 | }, |
9677 | }, |
Line 9275... | Line 9678... | ||
9275 | 9678 | ||
9276 | /* VEX_LEN_0F2D_P_3 */ |
9679 | /* VEX_LEN_0F2D_P_3 */ |
9277 | { |
9680 | { |
Line 9306... | Line 9709... | ||
9306 | /* VEX_LEN_0F41_P_0 */ |
9709 | /* VEX_LEN_0F41_P_0 */ |
9307 | { |
9710 | { |
9308 | { Bad_Opcode }, |
9711 | { Bad_Opcode }, |
9309 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, |
9712 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, |
9310 | }, |
9713 | }, |
- | 9714 | /* VEX_LEN_0F41_P_2 */ |
|
- | 9715 | { |
|
- | 9716 | { Bad_Opcode }, |
|
- | 9717 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, |
|
- | 9718 | }, |
|
9311 | /* VEX_LEN_0F42_P_0 */ |
9719 | /* VEX_LEN_0F42_P_0 */ |
9312 | { |
9720 | { |
9313 | { Bad_Opcode }, |
9721 | { Bad_Opcode }, |
9314 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, |
9722 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, |
9315 | }, |
9723 | }, |
- | 9724 | /* VEX_LEN_0F42_P_2 */ |
|
- | 9725 | { |
|
- | 9726 | { Bad_Opcode }, |
|
- | 9727 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, |
|
- | 9728 | }, |
|
9316 | /* VEX_LEN_0F44_P_0 */ |
9729 | /* VEX_LEN_0F44_P_0 */ |
9317 | { |
9730 | { |
9318 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, |
9731 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, |
9319 | }, |
9732 | }, |
- | 9733 | /* VEX_LEN_0F44_P_2 */ |
|
- | 9734 | { |
|
- | 9735 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, |
|
- | 9736 | }, |
|
9320 | /* VEX_LEN_0F45_P_0 */ |
9737 | /* VEX_LEN_0F45_P_0 */ |
9321 | { |
9738 | { |
9322 | { Bad_Opcode }, |
9739 | { Bad_Opcode }, |
9323 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, |
9740 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, |
9324 | }, |
9741 | }, |
- | 9742 | /* VEX_LEN_0F45_P_2 */ |
|
- | 9743 | { |
|
- | 9744 | { Bad_Opcode }, |
|
- | 9745 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, |
|
- | 9746 | }, |
|
9325 | /* VEX_LEN_0F46_P_0 */ |
9747 | /* VEX_LEN_0F46_P_0 */ |
9326 | { |
9748 | { |
9327 | { Bad_Opcode }, |
9749 | { Bad_Opcode }, |
9328 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, |
9750 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, |
9329 | }, |
9751 | }, |
- | 9752 | /* VEX_LEN_0F46_P_2 */ |
|
- | 9753 | { |
|
- | 9754 | { Bad_Opcode }, |
|
- | 9755 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, |
|
- | 9756 | }, |
|
9330 | /* VEX_LEN_0F47_P_0 */ |
9757 | /* VEX_LEN_0F47_P_0 */ |
9331 | { |
9758 | { |
9332 | { Bad_Opcode }, |
9759 | { Bad_Opcode }, |
9333 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, |
9760 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, |
9334 | }, |
9761 | }, |
- | 9762 | /* VEX_LEN_0F47_P_2 */ |
|
- | 9763 | { |
|
- | 9764 | { Bad_Opcode }, |
|
- | 9765 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, |
|
- | 9766 | }, |
|
- | 9767 | /* VEX_LEN_0F4A_P_0 */ |
|
- | 9768 | { |
|
- | 9769 | { Bad_Opcode }, |
|
- | 9770 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, |
|
- | 9771 | }, |
|
- | 9772 | /* VEX_LEN_0F4A_P_2 */ |
|
- | 9773 | { |
|
- | 9774 | { Bad_Opcode }, |
|
- | 9775 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, |
|
- | 9776 | }, |
|
- | 9777 | /* VEX_LEN_0F4B_P_0 */ |
|
- | 9778 | { |
|
- | 9779 | { Bad_Opcode }, |
|
- | 9780 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, |
|
- | 9781 | }, |
|
9335 | /* VEX_LEN_0F4B_P_2 */ |
9782 | /* VEX_LEN_0F4B_P_2 */ |
9336 | { |
9783 | { |
9337 | { Bad_Opcode }, |
9784 | { Bad_Opcode }, |
9338 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, |
9785 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, |
9339 | }, |
9786 | }, |
Line 9446... | Line 9893... | ||
9446 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9893 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9447 | }, |
9894 | }, |
Line 9448... | Line 9895... | ||
9448 | 9895 | ||
9449 | /* VEX_LEN_0F6E_P_2 */ |
9896 | /* VEX_LEN_0F6E_P_2 */ |
9450 | { |
9897 | { |
9451 | { "vmovK", { XMScalar, Edq } }, |
9898 | { "vmovK", { XMScalar, Edq }, 0 }, |
9452 | { "vmovK", { XMScalar, Edq } }, |
9899 | { "vmovK", { XMScalar, Edq }, 0 }, |
Line 9453... | Line 9900... | ||
9453 | }, |
9900 | }, |
9454 | 9901 | ||
9455 | /* VEX_LEN_0F7E_P_1 */ |
9902 | /* VEX_LEN_0F7E_P_1 */ |
9456 | { |
9903 | { |
9457 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9904 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
Line 9458... | Line 9905... | ||
9458 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9905 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9459 | }, |
9906 | }, |
9460 | 9907 | ||
9461 | /* VEX_LEN_0F7E_P_2 */ |
9908 | /* VEX_LEN_0F7E_P_2 */ |
9462 | { |
9909 | { |
Line 9463... | Line 9910... | ||
9463 | { "vmovK", { Edq, XMScalar } }, |
9910 | { "vmovK", { Edq, XMScalar }, 0 }, |
9464 | { "vmovK", { Edq, XMScalar } }, |
9911 | { "vmovK", { Edq, XMScalar }, 0 }, |
9465 | }, |
9912 | }, |
9466 | 9913 | ||
Line -... | Line 9914... | ||
- | 9914 | /* VEX_LEN_0F90_P_0 */ |
|
- | 9915 | { |
|
- | 9916 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
|
- | 9917 | }, |
|
- | 9918 | ||
9467 | /* VEX_LEN_0F90_P_0 */ |
9919 | /* VEX_LEN_0F90_P_2 */ |
9468 | { |
9920 | { |
9469 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
9921 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
9470 | }, |
9922 | }, |
Line -... | Line 9923... | ||
- | 9923 | ||
- | 9924 | /* VEX_LEN_0F91_P_0 */ |
|
- | 9925 | { |
|
- | 9926 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
|
- | 9927 | }, |
|
9471 | 9928 | ||
9472 | /* VEX_LEN_0F91_P_0 */ |
9929 | /* VEX_LEN_0F91_P_2 */ |
9473 | { |
9930 | { |
9474 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
9931 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
Line -... | Line 9932... | ||
- | 9932 | }, |
|
- | 9933 | ||
- | 9934 | /* VEX_LEN_0F92_P_0 */ |
|
- | 9935 | { |
|
- | 9936 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
|
- | 9937 | }, |
|
- | 9938 | ||
- | 9939 | /* VEX_LEN_0F92_P_2 */ |
|
- | 9940 | { |
|
- | 9941 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
|
9475 | }, |
9942 | }, |
9476 | 9943 | ||
9477 | /* VEX_LEN_0F92_P_0 */ |
9944 | /* VEX_LEN_0F92_P_3 */ |
9478 | { |
9945 | { |
Line -... | Line 9946... | ||
- | 9946 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, |
|
- | 9947 | }, |
|
- | 9948 | ||
- | 9949 | /* VEX_LEN_0F93_P_0 */ |
|
- | 9950 | { |
|
- | 9951 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
|
- | 9952 | }, |
|
- | 9953 | ||
- | 9954 | /* VEX_LEN_0F93_P_2 */ |
|
- | 9955 | { |
|
9479 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
9956 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
9480 | }, |
9957 | }, |
9481 | 9958 | ||
9482 | /* VEX_LEN_0F93_P_0 */ |
9959 | /* VEX_LEN_0F93_P_3 */ |
Line -... | Line 9960... | ||
- | 9960 | { |
|
- | 9961 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, |
|
- | 9962 | }, |
|
- | 9963 | ||
- | 9964 | /* VEX_LEN_0F98_P_0 */ |
|
- | 9965 | { |
|
- | 9966 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, |
|
- | 9967 | }, |
|
- | 9968 | ||
- | 9969 | /* VEX_LEN_0F98_P_2 */ |
|
- | 9970 | { |
|
- | 9971 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, |
|
- | 9972 | }, |
|
- | 9973 | ||
- | 9974 | /* VEX_LEN_0F99_P_0 */ |
|
9483 | { |
9975 | { |
9484 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
9976 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, |
9485 | }, |
9977 | }, |
9486 | 9978 | ||
Line 9592... | Line 10084... | ||
9592 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
10084 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
9593 | }, |
10085 | }, |
Line 9594... | Line 10086... | ||
9594 | 10086 | ||
9595 | /* VEX_LEN_0F38F2_P_0 */ |
10087 | /* VEX_LEN_0F38F2_P_0 */ |
9596 | { |
10088 | { |
9597 | { "andnS", { Gdq, VexGdq, Edq } }, |
10089 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
Line 9598... | Line 10090... | ||
9598 | }, |
10090 | }, |
9599 | 10091 | ||
9600 | /* VEX_LEN_0F38F3_R_1_P_0 */ |
10092 | /* VEX_LEN_0F38F3_R_1_P_0 */ |
9601 | { |
10093 | { |
Line 9602... | Line 10094... | ||
9602 | { "blsrS", { VexGdq, Edq } }, |
10094 | { "blsrS", { VexGdq, Edq }, 0 }, |
9603 | }, |
10095 | }, |
9604 | 10096 | ||
9605 | /* VEX_LEN_0F38F3_R_2_P_0 */ |
10097 | /* VEX_LEN_0F38F3_R_2_P_0 */ |
Line 9606... | Line 10098... | ||
9606 | { |
10098 | { |
9607 | { "blsmskS", { VexGdq, Edq } }, |
10099 | { "blsmskS", { VexGdq, Edq }, 0 }, |
9608 | }, |
10100 | }, |
9609 | 10101 | ||
Line 9610... | Line 10102... | ||
9610 | /* VEX_LEN_0F38F3_R_3_P_0 */ |
10102 | /* VEX_LEN_0F38F3_R_3_P_0 */ |
9611 | { |
10103 | { |
9612 | { "blsiS", { VexGdq, Edq } }, |
10104 | { "blsiS", { VexGdq, Edq }, 0 }, |
9613 | }, |
10105 | }, |
Line 9614... | Line 10106... | ||
9614 | 10106 | ||
9615 | /* VEX_LEN_0F38F5_P_0 */ |
10107 | /* VEX_LEN_0F38F5_P_0 */ |
9616 | { |
10108 | { |
9617 | { "bzhiS", { Gdq, Edq, VexGdq } }, |
10109 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
Line 9618... | Line 10110... | ||
9618 | }, |
10110 | }, |
9619 | 10111 | ||
9620 | /* VEX_LEN_0F38F5_P_1 */ |
10112 | /* VEX_LEN_0F38F5_P_1 */ |
9621 | { |
10113 | { |
Line 9622... | Line 10114... | ||
9622 | { "pextS", { Gdq, VexGdq, Edq } }, |
10114 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
9623 | }, |
10115 | }, |
9624 | 10116 | ||
9625 | /* VEX_LEN_0F38F5_P_3 */ |
10117 | /* VEX_LEN_0F38F5_P_3 */ |
Line 9626... | Line 10118... | ||
9626 | { |
10118 | { |
9627 | { "pdepS", { Gdq, VexGdq, Edq } }, |
10119 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
9628 | }, |
10120 | }, |
9629 | 10121 | ||
Line 9630... | Line 10122... | ||
9630 | /* VEX_LEN_0F38F6_P_3 */ |
10122 | /* VEX_LEN_0F38F6_P_3 */ |
9631 | { |
10123 | { |
9632 | { "mulxS", { Gdq, VexGdq, Edq } }, |
10124 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
9633 | }, |
10125 | }, |
Line 9634... | Line 10126... | ||
9634 | 10126 | ||
9635 | /* VEX_LEN_0F38F7_P_0 */ |
10127 | /* VEX_LEN_0F38F7_P_0 */ |
9636 | { |
10128 | { |
9637 | { "bextrS", { Gdq, Edq, VexGdq } }, |
10129 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
Line 9638... | Line 10130... | ||
9638 | }, |
10130 | }, |
9639 | 10131 | ||
9640 | /* VEX_LEN_0F38F7_P_1 */ |
10132 | /* VEX_LEN_0F38F7_P_1 */ |
9641 | { |
10133 | { |
Line 9642... | Line 10134... | ||
9642 | { "sarxS", { Gdq, Edq, VexGdq } }, |
10134 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
9643 | }, |
10135 | }, |
9644 | 10136 | ||
Line 9692... | Line 10184... | ||
9692 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
10184 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
9693 | }, |
10185 | }, |
Line 9694... | Line 10186... | ||
9694 | 10186 | ||
9695 | /* VEX_LEN_0F3A16_P_2 */ |
10187 | /* VEX_LEN_0F3A16_P_2 */ |
9696 | { |
10188 | { |
9697 | { "vpextrK", { Edq, XM, Ib } }, |
10189 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
Line 9698... | Line 10190... | ||
9698 | }, |
10190 | }, |
9699 | 10191 | ||
9700 | /* VEX_LEN_0F3A17_P_2 */ |
10192 | /* VEX_LEN_0F3A17_P_2 */ |
9701 | { |
10193 | { |
Line 9702... | Line 10194... | ||
9702 | { "vextractps", { Edqd, XM, Ib } }, |
10194 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
9703 | }, |
10195 | }, |
9704 | 10196 | ||
Line 9724... | Line 10216... | ||
9724 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
10216 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
9725 | }, |
10217 | }, |
Line 9726... | Line 10218... | ||
9726 | 10218 | ||
9727 | /* VEX_LEN_0F3A22_P_2 */ |
10219 | /* VEX_LEN_0F3A22_P_2 */ |
9728 | { |
10220 | { |
9729 | { "vpinsrK", { XM, Vex128, Edq, Ib } }, |
10221 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
Line 9730... | Line 10222... | ||
9730 | }, |
10222 | }, |
9731 | 10223 | ||
9732 | /* VEX_LEN_0F3A30_P_2 */ |
10224 | /* VEX_LEN_0F3A30_P_2 */ |
9733 | { |
10225 | { |
Line -... | Line 10226... | ||
- | 10226 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, |
|
- | 10227 | }, |
|
- | 10228 | ||
- | 10229 | /* VEX_LEN_0F3A31_P_2 */ |
|
- | 10230 | { |
|
9734 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, |
10231 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, |
9735 | }, |
10232 | }, |
9736 | 10233 | ||
9737 | /* VEX_LEN_0F3A32_P_2 */ |
10234 | /* VEX_LEN_0F3A32_P_2 */ |
Line -... | Line 10235... | ||
- | 10235 | { |
|
- | 10236 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, |
|
- | 10237 | }, |
|
- | 10238 | ||
- | 10239 | /* VEX_LEN_0F3A33_P_2 */ |
|
9738 | { |
10240 | { |
9739 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, |
10241 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, |
9740 | }, |
10242 | }, |
9741 | 10243 | ||
9742 | /* VEX_LEN_0F3A38_P_2 */ |
10244 | /* VEX_LEN_0F3A38_P_2 */ |
Line 9787... | Line 10289... | ||
9787 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
10289 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
9788 | }, |
10290 | }, |
Line 9789... | Line 10291... | ||
9789 | 10291 | ||
9790 | /* VEX_LEN_0F3A6A_P_2 */ |
10292 | /* VEX_LEN_0F3A6A_P_2 */ |
9791 | { |
10293 | { |
9792 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
10294 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
Line 9793... | Line 10295... | ||
9793 | }, |
10295 | }, |
9794 | 10296 | ||
9795 | /* VEX_LEN_0F3A6B_P_2 */ |
10297 | /* VEX_LEN_0F3A6B_P_2 */ |
9796 | { |
10298 | { |
Line 9797... | Line 10299... | ||
9797 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
10299 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
9798 | }, |
10300 | }, |
9799 | 10301 | ||
9800 | /* VEX_LEN_0F3A6E_P_2 */ |
10302 | /* VEX_LEN_0F3A6E_P_2 */ |
Line 9801... | Line 10303... | ||
9801 | { |
10303 | { |
9802 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
10304 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
9803 | }, |
10305 | }, |
9804 | 10306 | ||
Line 9805... | Line 10307... | ||
9805 | /* VEX_LEN_0F3A6F_P_2 */ |
10307 | /* VEX_LEN_0F3A6F_P_2 */ |
9806 | { |
10308 | { |
9807 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
10309 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
9808 | }, |
10310 | }, |
Line 9809... | Line 10311... | ||
9809 | 10311 | ||
9810 | /* VEX_LEN_0F3A7A_P_2 */ |
10312 | /* VEX_LEN_0F3A7A_P_2 */ |
9811 | { |
10313 | { |
9812 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
10314 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
Line 9813... | Line 10315... | ||
9813 | }, |
10315 | }, |
9814 | 10316 | ||
9815 | /* VEX_LEN_0F3A7B_P_2 */ |
10317 | /* VEX_LEN_0F3A7B_P_2 */ |
9816 | { |
10318 | { |
Line 9817... | Line 10319... | ||
9817 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
10319 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
9818 | }, |
10320 | }, |
9819 | 10321 | ||
9820 | /* VEX_LEN_0F3A7E_P_2 */ |
10322 | /* VEX_LEN_0F3A7E_P_2 */ |
Line 9821... | Line 10323... | ||
9821 | { |
10323 | { |
9822 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
10324 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
9823 | }, |
10325 | }, |
9824 | 10326 | ||
Line 9825... | Line 10327... | ||
9825 | /* VEX_LEN_0F3A7F_P_2 */ |
10327 | /* VEX_LEN_0F3A7F_P_2 */ |
9826 | { |
10328 | { |
9827 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
10329 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
9828 | }, |
10330 | }, |
Line 9829... | Line 10331... | ||
9829 | 10331 | ||
9830 | /* VEX_LEN_0F3ADF_P_2 */ |
10332 | /* VEX_LEN_0F3ADF_P_2 */ |
9831 | { |
10333 | { |
9832 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
10334 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
Line 9833... | Line 10335... | ||
9833 | }, |
10335 | }, |
9834 | 10336 | ||
9835 | /* VEX_LEN_0F3AF0_P_3 */ |
10337 | /* VEX_LEN_0F3AF0_P_3 */ |
9836 | { |
10338 | { |
Line 9837... | Line 10339... | ||
9837 | { "rorxS", { Gdq, Edq, Ib } }, |
10339 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
9838 | }, |
10340 | }, |
9839 | 10341 | ||
9840 | /* VEX_LEN_0FXOP_08_CC */ |
10342 | /* VEX_LEN_0FXOP_08_CC */ |
Line 9841... | Line 10343... | ||
9841 | { |
10343 | { |
9842 | { "vpcomb", { XM, Vex128, EXx, Ib } }, |
10344 | { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, |
9843 | }, |
10345 | }, |
9844 | 10346 | ||
Line 9845... | Line 10347... | ||
9845 | /* VEX_LEN_0FXOP_08_CD */ |
10347 | /* VEX_LEN_0FXOP_08_CD */ |
9846 | { |
10348 | { |
9847 | { "vpcomw", { XM, Vex128, EXx, Ib } }, |
10349 | { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, |
9848 | }, |
10350 | }, |
Line 9849... | Line 10351... | ||
9849 | 10351 | ||
9850 | /* VEX_LEN_0FXOP_08_CE */ |
10352 | /* VEX_LEN_0FXOP_08_CE */ |
9851 | { |
10353 | { |
9852 | { "vpcomd", { XM, Vex128, EXx, Ib } }, |
10354 | { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, |
Line 9853... | Line 10355... | ||
9853 | }, |
10355 | }, |
9854 | 10356 | ||
9855 | /* VEX_LEN_0FXOP_08_CF */ |
10357 | /* VEX_LEN_0FXOP_08_CF */ |
9856 | { |
10358 | { |
Line 9857... | Line 10359... | ||
9857 | { "vpcomq", { XM, Vex128, EXx, Ib } }, |
10359 | { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, |
9858 | }, |
10360 | }, |
9859 | 10361 | ||
9860 | /* VEX_LEN_0FXOP_08_EC */ |
10362 | /* VEX_LEN_0FXOP_08_EC */ |
Line 9861... | Line 10363... | ||
9861 | { |
10363 | { |
9862 | { "vpcomub", { XM, Vex128, EXx, Ib } }, |
10364 | { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, |
9863 | }, |
10365 | }, |
9864 | 10366 | ||
9865 | /* VEX_LEN_0FXOP_08_ED */ |
10367 | /* VEX_LEN_0FXOP_08_ED */ |
Line 9866... | Line 10368... | ||
9866 | { |
10368 | { |
9867 | { "vpcomuw", { XM, Vex128, EXx, Ib } }, |
10369 | { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, |
9868 | }, |
10370 | }, |
9869 | 10371 | ||
9870 | /* VEX_LEN_0FXOP_08_EE */ |
10372 | /* VEX_LEN_0FXOP_08_EE */ |
9871 | { |
10373 | { |
Line 9872... | Line 10374... | ||
9872 | { "vpcomud", { XM, Vex128, EXx, Ib } }, |
10374 | { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, |
9873 | }, |
10375 | }, |
9874 | 10376 | ||
9875 | /* VEX_LEN_0FXOP_08_EF */ |
10377 | /* VEX_LEN_0FXOP_08_EF */ |
9876 | { |
10378 | { |
9877 | { "vpcomuq", { XM, Vex128, EXx, Ib } }, |
10379 | { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, |
9878 | }, |
10380 | }, |
9879 | 10381 | ||
9880 | /* VEX_LEN_0FXOP_09_80 */ |
10382 | /* VEX_LEN_0FXOP_09_80 */ |
9881 | { |
10383 | { |
9882 | { "vfrczps", { XM, EXxmm } }, |
10384 | { "vfrczps", { XM, EXxmm }, 0 }, |
9883 | { "vfrczps", { XM, EXymmq } }, |
10385 | { "vfrczps", { XM, EXymmq }, 0 }, |
9884 | }, |
10386 | }, |
9885 | 10387 | ||
9886 | /* VEX_LEN_0FXOP_09_81 */ |
10388 | /* VEX_LEN_0FXOP_09_81 */ |
9887 | { |
10389 | { |
9888 | { "vfrczpd", { XM, EXxmm } }, |
10390 | { "vfrczpd", { XM, EXxmm }, 0 }, |
9889 | { "vfrczpd", { XM, EXymmq } }, |
10391 | { "vfrczpd", { XM, EXymmq }, 0 }, |
9890 | }, |
10392 | }, |
9891 | }; |
10393 | }; |
9892 | 10394 | ||
9893 | static const struct dis386 vex_w_table[][2] = { |
10395 | static const struct dis386 vex_w_table[][2] = { |
9894 | { |
10396 | { |
9895 | /* VEX_W_0F10_P_0 */ |
10397 | /* VEX_W_0F10_P_0 */ |
9896 | { "vmovups", { XM, EXx } }, |
10398 | { "vmovups", { XM, EXx }, 0 }, |
9897 | }, |
10399 | }, |
9898 | { |
10400 | { |
9899 | /* VEX_W_0F10_P_1 */ |
10401 | /* VEX_W_0F10_P_1 */ |
9900 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar } }, |
10402 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
9901 | }, |
10403 | }, |
9902 | { |
10404 | { |
9903 | /* VEX_W_0F10_P_2 */ |
10405 | /* VEX_W_0F10_P_2 */ |
9904 | { "vmovupd", { XM, EXx } }, |
10406 | { "vmovupd", { XM, EXx }, 0 }, |
9905 | }, |
10407 | }, |
9906 | { |
10408 | { |
9907 | /* VEX_W_0F10_P_3 */ |
10409 | /* VEX_W_0F10_P_3 */ |
9908 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } }, |
10410 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
9909 | }, |
10411 | }, |
9910 | { |
10412 | { |
9911 | /* VEX_W_0F11_P_0 */ |
10413 | /* VEX_W_0F11_P_0 */ |
9912 | { "vmovups", { EXxS, XM } }, |
10414 | { "vmovups", { EXxS, XM }, 0 }, |
9913 | }, |
10415 | }, |
9914 | { |
10416 | { |
9915 | /* VEX_W_0F11_P_1 */ |
10417 | /* VEX_W_0F11_P_1 */ |
9916 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } }, |
10418 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
9917 | }, |
10419 | }, |
9918 | { |
10420 | { |
9919 | /* VEX_W_0F11_P_2 */ |
10421 | /* VEX_W_0F11_P_2 */ |
9920 | { "vmovupd", { EXxS, XM } }, |
10422 | { "vmovupd", { EXxS, XM }, 0 }, |
9921 | }, |
10423 | }, |
9922 | { |
10424 | { |
9923 | /* VEX_W_0F11_P_3 */ |
10425 | /* VEX_W_0F11_P_3 */ |
9924 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } }, |
10426 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
9925 | }, |
10427 | }, |
9926 | { |
10428 | { |
9927 | /* VEX_W_0F12_P_0_M_0 */ |
10429 | /* VEX_W_0F12_P_0_M_0 */ |
9928 | { "vmovlps", { XM, Vex128, EXq } }, |
10430 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
9929 | }, |
10431 | }, |
9930 | { |
10432 | { |
9931 | /* VEX_W_0F12_P_0_M_1 */ |
10433 | /* VEX_W_0F12_P_0_M_1 */ |
9932 | { "vmovhlps", { XM, Vex128, EXq } }, |
10434 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
9933 | }, |
10435 | }, |
9934 | { |
10436 | { |
9935 | /* VEX_W_0F12_P_1 */ |
10437 | /* VEX_W_0F12_P_1 */ |
9936 | { "vmovsldup", { XM, EXx } }, |
10438 | { "vmovsldup", { XM, EXx }, 0 }, |
9937 | }, |
10439 | }, |
9938 | { |
10440 | { |
9939 | /* VEX_W_0F12_P_2 */ |
10441 | /* VEX_W_0F12_P_2 */ |
9940 | { "vmovlpd", { XM, Vex128, EXq } }, |
10442 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
9941 | }, |
10443 | }, |
9942 | { |
10444 | { |
9943 | /* VEX_W_0F12_P_3 */ |
10445 | /* VEX_W_0F12_P_3 */ |
9944 | { "vmovddup", { XM, EXymmq } }, |
10446 | { "vmovddup", { XM, EXymmq }, 0 }, |
9945 | }, |
10447 | }, |
9946 | { |
10448 | { |
9947 | /* VEX_W_0F13_M_0 */ |
10449 | /* VEX_W_0F13_M_0 */ |
9948 | { "vmovlpX", { EXq, XM } }, |
10450 | { "vmovlpX", { EXq, XM }, 0 }, |
9949 | }, |
10451 | }, |
9950 | { |
10452 | { |
9951 | /* VEX_W_0F14 */ |
10453 | /* VEX_W_0F14 */ |
9952 | { "vunpcklpX", { XM, Vex, EXx } }, |
10454 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
9953 | }, |
10455 | }, |
9954 | { |
10456 | { |
9955 | /* VEX_W_0F15 */ |
10457 | /* VEX_W_0F15 */ |
9956 | { "vunpckhpX", { XM, Vex, EXx } }, |
10458 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
9957 | }, |
10459 | }, |
9958 | { |
10460 | { |
9959 | /* VEX_W_0F16_P_0_M_0 */ |
10461 | /* VEX_W_0F16_P_0_M_0 */ |
9960 | { "vmovhps", { XM, Vex128, EXq } }, |
10462 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
9961 | }, |
10463 | }, |
9962 | { |
10464 | { |
9963 | /* VEX_W_0F16_P_0_M_1 */ |
10465 | /* VEX_W_0F16_P_0_M_1 */ |
9964 | { "vmovlhps", { XM, Vex128, EXq } }, |
10466 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
9965 | }, |
10467 | }, |
9966 | { |
10468 | { |
9967 | /* VEX_W_0F16_P_1 */ |
10469 | /* VEX_W_0F16_P_1 */ |
9968 | { "vmovshdup", { XM, EXx } }, |
10470 | { "vmovshdup", { XM, EXx }, 0 }, |
9969 | }, |
10471 | }, |
9970 | { |
10472 | { |
9971 | /* VEX_W_0F16_P_2 */ |
10473 | /* VEX_W_0F16_P_2 */ |
9972 | { "vmovhpd", { XM, Vex128, EXq } }, |
10474 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
9973 | }, |
10475 | }, |
9974 | { |
10476 | { |
9975 | /* VEX_W_0F17_M_0 */ |
10477 | /* VEX_W_0F17_M_0 */ |
9976 | { "vmovhpX", { EXq, XM } }, |
10478 | { "vmovhpX", { EXq, XM }, 0 }, |
9977 | }, |
10479 | }, |
9978 | { |
10480 | { |
9979 | /* VEX_W_0F28 */ |
10481 | /* VEX_W_0F28 */ |
9980 | { "vmovapX", { XM, EXx } }, |
10482 | { "vmovapX", { XM, EXx }, 0 }, |
9981 | }, |
10483 | }, |
9982 | { |
10484 | { |
9983 | /* VEX_W_0F29 */ |
10485 | /* VEX_W_0F29 */ |
9984 | { "vmovapX", { EXxS, XM } }, |
10486 | { "vmovapX", { EXxS, XM }, 0 }, |
9985 | }, |
10487 | }, |
9986 | { |
10488 | { |
- | 10489 | /* VEX_W_0F2B_M_0 */ |
|
- | 10490 | { "vmovntpX", { Mx, XM }, 0 }, |
|
- | 10491 | }, |
|
- | 10492 | { |
|
- | 10493 | /* VEX_W_0F2E_P_0 */ |
|
9987 | /* VEX_W_0F2B_M_0 */ |
10494 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
- | 10495 | }, |
|
9988 | { "vmovntpX", { Mx, XM } }, |
10496 | { |
9989 | }, |
10497 | /* VEX_W_0F2E_P_2 */ |
9990 | { |
10498 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
- | 10499 | }, |
|
- | 10500 | { |
|
- | 10501 | /* VEX_W_0F2F_P_0 */ |
|
- | 10502 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
|
- | 10503 | }, |
|
- | 10504 | { |
|
9991 | /* VEX_W_0F2E_P_0 */ |
10505 | /* VEX_W_0F2F_P_2 */ |
9992 | { "vucomiss", { XMScalar, EXdScalar } }, |
10506 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
9993 | }, |
10507 | }, |
9994 | { |
10508 | { |
- | 10509 | /* VEX_W_0F41_P_0_LEN_1 */ |
|
- | 10510 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
|
- | 10511 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, |
|
- | 10512 | }, |
|
9995 | /* VEX_W_0F2E_P_2 */ |
10513 | { |
- | 10514 | /* VEX_W_0F41_P_2_LEN_1 */ |
|
- | 10515 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
|
9996 | { "vucomisd", { XMScalar, EXqScalar } }, |
10516 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } |
9997 | }, |
10517 | }, |
9998 | { |
10518 | { |
- | 10519 | /* VEX_W_0F42_P_0_LEN_1 */ |
|
- | 10520 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
|
- | 10521 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, |
|
- | 10522 | }, |
|
- | 10523 | { |
|
- | 10524 | /* VEX_W_0F42_P_2_LEN_1 */ |
|
9999 | /* VEX_W_0F2F_P_0 */ |
10525 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10000 | { "vcomiss", { XMScalar, EXdScalar } }, |
10526 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, |
10001 | }, |
10527 | }, |
10002 | { |
10528 | { |
- | 10529 | /* VEX_W_0F44_P_0_LEN_0 */ |
|
- | 10530 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
|
- | 10531 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, |
|
- | 10532 | }, |
|
- | 10533 | { |
|
- | 10534 | /* VEX_W_0F44_P_2_LEN_0 */ |
|
10003 | /* VEX_W_0F2F_P_2 */ |
10535 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10004 | { "vcomisd", { XMScalar, EXqScalar } }, |
10536 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, |
10005 | }, |
10537 | }, |
10006 | { |
10538 | { |
- | 10539 | /* VEX_W_0F45_P_0_LEN_1 */ |
|
- | 10540 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, |
|
- | 10541 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, |
|
- | 10542 | }, |
|
- | 10543 | { |
|
- | 10544 | /* VEX_W_0F45_P_2_LEN_1 */ |
|
10007 | /* VEX_W_0F41_P_0_LEN_1 */ |
10545 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, |
- | 10546 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, |
|
- | 10547 | }, |
|
- | 10548 | { |
|
- | 10549 | /* VEX_W_0F46_P_0_LEN_1 */ |
|
- | 10550 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, |
|
- | 10551 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, |
|
- | 10552 | }, |
|
- | 10553 | { |
|
- | 10554 | /* VEX_W_0F46_P_2_LEN_1 */ |
|
- | 10555 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, |
|
- | 10556 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, |
|
- | 10557 | }, |
|
- | 10558 | { |
|
- | 10559 | /* VEX_W_0F47_P_0_LEN_1 */ |
|
- | 10560 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, |
|
10008 | { "kandw", { MaskG, MaskVex, MaskR } }, |
10561 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, |
10009 | }, |
10562 | }, |
10010 | { |
10563 | { |
10011 | /* VEX_W_0F42_P_0_LEN_1 */ |
10564 | /* VEX_W_0F47_P_2_LEN_1 */ |
10012 | { "kandnw", { MaskG, MaskVex, MaskR } }, |
10565 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, |
10013 | }, |
10566 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, |
10014 | { |
10567 | }, |
10015 | /* VEX_W_0F44_P_0_LEN_0 */ |
10568 | { |
10016 | { "knotw", { MaskG, MaskR } }, |
10569 | /* VEX_W_0F4A_P_0_LEN_1 */ |
10017 | }, |
10570 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, |
10018 | { |
10571 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, |
10019 | /* VEX_W_0F45_P_0_LEN_1 */ |
10572 | }, |
10020 | { "korw", { MaskG, MaskVex, MaskR } }, |
10573 | { |
10021 | }, |
10574 | /* VEX_W_0F4A_P_2_LEN_1 */ |
10022 | { |
10575 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, |
10023 | /* VEX_W_0F46_P_0_LEN_1 */ |
10576 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, |
10024 | { "kxnorw", { MaskG, MaskVex, MaskR } }, |
10577 | }, |
10025 | }, |
10578 | { |
10026 | { |
10579 | /* VEX_W_0F4B_P_0_LEN_1 */ |
10027 | /* VEX_W_0F47_P_0_LEN_1 */ |
10580 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, |
10028 | { "kxorw", { MaskG, MaskVex, MaskR } }, |
10581 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, |
10029 | }, |
10582 | }, |
10030 | { |
10583 | { |
10031 | /* VEX_W_0F4B_P_2_LEN_1 */ |
10584 | /* VEX_W_0F4B_P_2_LEN_1 */ |
10032 | { "kunpckbw", { MaskG, MaskVex, MaskR } }, |
10585 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, |
10033 | }, |
10586 | }, |
10034 | { |
10587 | { |
10035 | /* VEX_W_0F50_M_0 */ |
10588 | /* VEX_W_0F50_M_0 */ |
10036 | { "vmovmskpX", { Gdq, XS } }, |
10589 | { "vmovmskpX", { Gdq, XS }, 0 }, |
10037 | }, |
10590 | }, |
10038 | { |
10591 | { |
10039 | /* VEX_W_0F51_P_0 */ |
10592 | /* VEX_W_0F51_P_0 */ |
10040 | { "vsqrtps", { XM, EXx } }, |
10593 | { "vsqrtps", { XM, EXx }, 0 }, |
10041 | }, |
10594 | }, |
10042 | { |
10595 | { |
10043 | /* VEX_W_0F51_P_1 */ |
10596 | /* VEX_W_0F51_P_1 */ |
10044 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
10597 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10045 | }, |
10598 | }, |
10046 | { |
10599 | { |
10047 | /* VEX_W_0F51_P_2 */ |
10600 | /* VEX_W_0F51_P_2 */ |
10048 | { "vsqrtpd", { XM, EXx } }, |
10601 | { "vsqrtpd", { XM, EXx }, 0 }, |
10049 | }, |
10602 | }, |
10050 | { |
10603 | { |
10051 | /* VEX_W_0F51_P_3 */ |
10604 | /* VEX_W_0F51_P_3 */ |
10052 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } }, |
10605 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10053 | }, |
10606 | }, |
10054 | { |
10607 | { |
10055 | /* VEX_W_0F52_P_0 */ |
10608 | /* VEX_W_0F52_P_0 */ |
10056 | { "vrsqrtps", { XM, EXx } }, |
10609 | { "vrsqrtps", { XM, EXx }, 0 }, |
10057 | }, |
10610 | }, |
10058 | { |
10611 | { |
10059 | /* VEX_W_0F52_P_1 */ |
10612 | /* VEX_W_0F52_P_1 */ |
10060 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
10613 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10061 | }, |
10614 | }, |
10062 | { |
10615 | { |
10063 | /* VEX_W_0F53_P_0 */ |
10616 | /* VEX_W_0F53_P_0 */ |
10064 | { "vrcpps", { XM, EXx } }, |
10617 | { "vrcpps", { XM, EXx }, 0 }, |
10065 | }, |
10618 | }, |
10066 | { |
10619 | { |
10067 | /* VEX_W_0F53_P_1 */ |
10620 | /* VEX_W_0F53_P_1 */ |
10068 | { "vrcpss", { XMScalar, VexScalar, EXdScalar } }, |
10621 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10069 | }, |
10622 | }, |
10070 | { |
10623 | { |
10071 | /* VEX_W_0F58_P_0 */ |
10624 | /* VEX_W_0F58_P_0 */ |
10072 | { "vaddps", { XM, Vex, EXx } }, |
10625 | { "vaddps", { XM, Vex, EXx }, 0 }, |
10073 | }, |
10626 | }, |
10074 | { |
10627 | { |
10075 | /* VEX_W_0F58_P_1 */ |
10628 | /* VEX_W_0F58_P_1 */ |
10076 | { "vaddss", { XMScalar, VexScalar, EXdScalar } }, |
10629 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10077 | }, |
10630 | }, |
10078 | { |
10631 | { |
10079 | /* VEX_W_0F58_P_2 */ |
10632 | /* VEX_W_0F58_P_2 */ |
10080 | { "vaddpd", { XM, Vex, EXx } }, |
10633 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
10081 | }, |
10634 | }, |
10082 | { |
10635 | { |
10083 | /* VEX_W_0F58_P_3 */ |
10636 | /* VEX_W_0F58_P_3 */ |
10084 | { "vaddsd", { XMScalar, VexScalar, EXqScalar } }, |
10637 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10085 | }, |
10638 | }, |
10086 | { |
10639 | { |
10087 | /* VEX_W_0F59_P_0 */ |
10640 | /* VEX_W_0F59_P_0 */ |
10088 | { "vmulps", { XM, Vex, EXx } }, |
10641 | { "vmulps", { XM, Vex, EXx }, 0 }, |
10089 | }, |
10642 | }, |
10090 | { |
10643 | { |
10091 | /* VEX_W_0F59_P_1 */ |
10644 | /* VEX_W_0F59_P_1 */ |
10092 | { "vmulss", { XMScalar, VexScalar, EXdScalar } }, |
10645 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10093 | }, |
10646 | }, |
10094 | { |
10647 | { |
10095 | /* VEX_W_0F59_P_2 */ |
10648 | /* VEX_W_0F59_P_2 */ |
10096 | { "vmulpd", { XM, Vex, EXx } }, |
10649 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
10097 | }, |
10650 | }, |
10098 | { |
10651 | { |
10099 | /* VEX_W_0F59_P_3 */ |
10652 | /* VEX_W_0F59_P_3 */ |
10100 | { "vmulsd", { XMScalar, VexScalar, EXqScalar } }, |
10653 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10101 | }, |
10654 | }, |
10102 | { |
10655 | { |
10103 | /* VEX_W_0F5A_P_0 */ |
10656 | /* VEX_W_0F5A_P_0 */ |
10104 | { "vcvtps2pd", { XM, EXxmmq } }, |
10657 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
10105 | }, |
10658 | }, |
10106 | { |
10659 | { |
10107 | /* VEX_W_0F5A_P_1 */ |
10660 | /* VEX_W_0F5A_P_1 */ |
10108 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } }, |
10661 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10109 | }, |
10662 | }, |
10110 | { |
10663 | { |
10111 | /* VEX_W_0F5A_P_3 */ |
10664 | /* VEX_W_0F5A_P_3 */ |
10112 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } }, |
10665 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10113 | }, |
10666 | }, |
10114 | { |
10667 | { |
10115 | /* VEX_W_0F5B_P_0 */ |
10668 | /* VEX_W_0F5B_P_0 */ |
10116 | { "vcvtdq2ps", { XM, EXx } }, |
10669 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
10117 | }, |
10670 | }, |
10118 | { |
10671 | { |
10119 | /* VEX_W_0F5B_P_1 */ |
10672 | /* VEX_W_0F5B_P_1 */ |
10120 | { "vcvttps2dq", { XM, EXx } }, |
10673 | { "vcvttps2dq", { XM, EXx }, 0 }, |
10121 | }, |
10674 | }, |
10122 | { |
10675 | { |
10123 | /* VEX_W_0F5B_P_2 */ |
10676 | /* VEX_W_0F5B_P_2 */ |
10124 | { "vcvtps2dq", { XM, EXx } }, |
10677 | { "vcvtps2dq", { XM, EXx }, 0 }, |
10125 | }, |
10678 | }, |
10126 | { |
10679 | { |
10127 | /* VEX_W_0F5C_P_0 */ |
10680 | /* VEX_W_0F5C_P_0 */ |
10128 | { "vsubps", { XM, Vex, EXx } }, |
10681 | { "vsubps", { XM, Vex, EXx }, 0 }, |
10129 | }, |
10682 | }, |
10130 | { |
10683 | { |
10131 | /* VEX_W_0F5C_P_1 */ |
10684 | /* VEX_W_0F5C_P_1 */ |
10132 | { "vsubss", { XMScalar, VexScalar, EXdScalar } }, |
10685 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10133 | }, |
10686 | }, |
10134 | { |
10687 | { |
10135 | /* VEX_W_0F5C_P_2 */ |
10688 | /* VEX_W_0F5C_P_2 */ |
10136 | { "vsubpd", { XM, Vex, EXx } }, |
10689 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
10137 | }, |
10690 | }, |
10138 | { |
10691 | { |
10139 | /* VEX_W_0F5C_P_3 */ |
10692 | /* VEX_W_0F5C_P_3 */ |
10140 | { "vsubsd", { XMScalar, VexScalar, EXqScalar } }, |
10693 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10141 | }, |
10694 | }, |
10142 | { |
10695 | { |
10143 | /* VEX_W_0F5D_P_0 */ |
10696 | /* VEX_W_0F5D_P_0 */ |
10144 | { "vminps", { XM, Vex, EXx } }, |
10697 | { "vminps", { XM, Vex, EXx }, 0 }, |
10145 | }, |
10698 | }, |
10146 | { |
10699 | { |
10147 | /* VEX_W_0F5D_P_1 */ |
10700 | /* VEX_W_0F5D_P_1 */ |
10148 | { "vminss", { XMScalar, VexScalar, EXdScalar } }, |
10701 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10149 | }, |
10702 | }, |
10150 | { |
10703 | { |
10151 | /* VEX_W_0F5D_P_2 */ |
10704 | /* VEX_W_0F5D_P_2 */ |
10152 | { "vminpd", { XM, Vex, EXx } }, |
10705 | { "vminpd", { XM, Vex, EXx }, 0 }, |
10153 | }, |
10706 | }, |
10154 | { |
10707 | { |
10155 | /* VEX_W_0F5D_P_3 */ |
10708 | /* VEX_W_0F5D_P_3 */ |
10156 | { "vminsd", { XMScalar, VexScalar, EXqScalar } }, |
10709 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10157 | }, |
10710 | }, |
10158 | { |
10711 | { |
10159 | /* VEX_W_0F5E_P_0 */ |
10712 | /* VEX_W_0F5E_P_0 */ |
10160 | { "vdivps", { XM, Vex, EXx } }, |
10713 | { "vdivps", { XM, Vex, EXx }, 0 }, |
10161 | }, |
10714 | }, |
10162 | { |
10715 | { |
10163 | /* VEX_W_0F5E_P_1 */ |
10716 | /* VEX_W_0F5E_P_1 */ |
10164 | { "vdivss", { XMScalar, VexScalar, EXdScalar } }, |
10717 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10165 | }, |
10718 | }, |
10166 | { |
10719 | { |
10167 | /* VEX_W_0F5E_P_2 */ |
10720 | /* VEX_W_0F5E_P_2 */ |
10168 | { "vdivpd", { XM, Vex, EXx } }, |
10721 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
10169 | }, |
10722 | }, |
10170 | { |
10723 | { |
10171 | /* VEX_W_0F5E_P_3 */ |
10724 | /* VEX_W_0F5E_P_3 */ |
10172 | { "vdivsd", { XMScalar, VexScalar, EXqScalar } }, |
10725 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10173 | }, |
10726 | }, |
10174 | { |
10727 | { |
10175 | /* VEX_W_0F5F_P_0 */ |
10728 | /* VEX_W_0F5F_P_0 */ |
10176 | { "vmaxps", { XM, Vex, EXx } }, |
10729 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
10177 | }, |
10730 | }, |
10178 | { |
10731 | { |
10179 | /* VEX_W_0F5F_P_1 */ |
10732 | /* VEX_W_0F5F_P_1 */ |
10180 | { "vmaxss", { XMScalar, VexScalar, EXdScalar } }, |
10733 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
10181 | }, |
10734 | }, |
10182 | { |
10735 | { |
10183 | /* VEX_W_0F5F_P_2 */ |
10736 | /* VEX_W_0F5F_P_2 */ |
10184 | { "vmaxpd", { XM, Vex, EXx } }, |
10737 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
10185 | }, |
10738 | }, |
10186 | { |
10739 | { |
10187 | /* VEX_W_0F5F_P_3 */ |
10740 | /* VEX_W_0F5F_P_3 */ |
10188 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar } }, |
10741 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
10189 | }, |
10742 | }, |
10190 | { |
10743 | { |
10191 | /* VEX_W_0F60_P_2 */ |
10744 | /* VEX_W_0F60_P_2 */ |
10192 | { "vpunpcklbw", { XM, Vex, EXx } }, |
10745 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
10193 | }, |
10746 | }, |
10194 | { |
10747 | { |
10195 | /* VEX_W_0F61_P_2 */ |
10748 | /* VEX_W_0F61_P_2 */ |
10196 | { "vpunpcklwd", { XM, Vex, EXx } }, |
10749 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
10197 | }, |
10750 | }, |
10198 | { |
10751 | { |
10199 | /* VEX_W_0F62_P_2 */ |
10752 | /* VEX_W_0F62_P_2 */ |
10200 | { "vpunpckldq", { XM, Vex, EXx } }, |
10753 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
10201 | }, |
10754 | }, |
10202 | { |
10755 | { |
10203 | /* VEX_W_0F63_P_2 */ |
10756 | /* VEX_W_0F63_P_2 */ |
10204 | { "vpacksswb", { XM, Vex, EXx } }, |
10757 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
10205 | }, |
10758 | }, |
10206 | { |
10759 | { |
10207 | /* VEX_W_0F64_P_2 */ |
10760 | /* VEX_W_0F64_P_2 */ |
10208 | { "vpcmpgtb", { XM, Vex, EXx } }, |
10761 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
10209 | }, |
10762 | }, |
10210 | { |
10763 | { |
10211 | /* VEX_W_0F65_P_2 */ |
10764 | /* VEX_W_0F65_P_2 */ |
10212 | { "vpcmpgtw", { XM, Vex, EXx } }, |
10765 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
10213 | }, |
10766 | }, |
10214 | { |
10767 | { |
10215 | /* VEX_W_0F66_P_2 */ |
10768 | /* VEX_W_0F66_P_2 */ |
10216 | { "vpcmpgtd", { XM, Vex, EXx } }, |
10769 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
10217 | }, |
10770 | }, |
10218 | { |
10771 | { |
10219 | /* VEX_W_0F67_P_2 */ |
10772 | /* VEX_W_0F67_P_2 */ |
10220 | { "vpackuswb", { XM, Vex, EXx } }, |
10773 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
10221 | }, |
10774 | }, |
10222 | { |
10775 | { |
10223 | /* VEX_W_0F68_P_2 */ |
10776 | /* VEX_W_0F68_P_2 */ |
10224 | { "vpunpckhbw", { XM, Vex, EXx } }, |
10777 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
10225 | }, |
10778 | }, |
10226 | { |
10779 | { |
10227 | /* VEX_W_0F69_P_2 */ |
10780 | /* VEX_W_0F69_P_2 */ |
10228 | { "vpunpckhwd", { XM, Vex, EXx } }, |
10781 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
10229 | }, |
10782 | }, |
10230 | { |
10783 | { |
10231 | /* VEX_W_0F6A_P_2 */ |
10784 | /* VEX_W_0F6A_P_2 */ |
10232 | { "vpunpckhdq", { XM, Vex, EXx } }, |
10785 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
10233 | }, |
10786 | }, |
10234 | { |
10787 | { |
10235 | /* VEX_W_0F6B_P_2 */ |
10788 | /* VEX_W_0F6B_P_2 */ |
10236 | { "vpackssdw", { XM, Vex, EXx } }, |
10789 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
10237 | }, |
10790 | }, |
10238 | { |
10791 | { |
10239 | /* VEX_W_0F6C_P_2 */ |
10792 | /* VEX_W_0F6C_P_2 */ |
10240 | { "vpunpcklqdq", { XM, Vex, EXx } }, |
10793 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
10241 | }, |
10794 | }, |
10242 | { |
10795 | { |
10243 | /* VEX_W_0F6D_P_2 */ |
10796 | /* VEX_W_0F6D_P_2 */ |
10244 | { "vpunpckhqdq", { XM, Vex, EXx } }, |
10797 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
10245 | }, |
10798 | }, |
10246 | { |
10799 | { |
10247 | /* VEX_W_0F6F_P_1 */ |
10800 | /* VEX_W_0F6F_P_1 */ |
10248 | { "vmovdqu", { XM, EXx } }, |
10801 | { "vmovdqu", { XM, EXx }, 0 }, |
10249 | }, |
10802 | }, |
10250 | { |
10803 | { |
10251 | /* VEX_W_0F6F_P_2 */ |
10804 | /* VEX_W_0F6F_P_2 */ |
10252 | { "vmovdqa", { XM, EXx } }, |
10805 | { "vmovdqa", { XM, EXx }, 0 }, |
10253 | }, |
10806 | }, |
10254 | { |
10807 | { |
10255 | /* VEX_W_0F70_P_1 */ |
10808 | /* VEX_W_0F70_P_1 */ |
10256 | { "vpshufhw", { XM, EXx, Ib } }, |
10809 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
10257 | }, |
10810 | }, |
10258 | { |
10811 | { |
10259 | /* VEX_W_0F70_P_2 */ |
10812 | /* VEX_W_0F70_P_2 */ |
10260 | { "vpshufd", { XM, EXx, Ib } }, |
10813 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
10261 | }, |
10814 | }, |
10262 | { |
10815 | { |
10263 | /* VEX_W_0F70_P_3 */ |
10816 | /* VEX_W_0F70_P_3 */ |
10264 | { "vpshuflw", { XM, EXx, Ib } }, |
10817 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
10265 | }, |
10818 | }, |
10266 | { |
10819 | { |
10267 | /* VEX_W_0F71_R_2_P_2 */ |
10820 | /* VEX_W_0F71_R_2_P_2 */ |
10268 | { "vpsrlw", { Vex, XS, Ib } }, |
10821 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
10269 | }, |
10822 | }, |
10270 | { |
10823 | { |
10271 | /* VEX_W_0F71_R_4_P_2 */ |
10824 | /* VEX_W_0F71_R_4_P_2 */ |
10272 | { "vpsraw", { Vex, XS, Ib } }, |
10825 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
10273 | }, |
10826 | }, |
10274 | { |
10827 | { |
10275 | /* VEX_W_0F71_R_6_P_2 */ |
10828 | /* VEX_W_0F71_R_6_P_2 */ |
10276 | { "vpsllw", { Vex, XS, Ib } }, |
10829 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
10277 | }, |
10830 | }, |
10278 | { |
10831 | { |
10279 | /* VEX_W_0F72_R_2_P_2 */ |
10832 | /* VEX_W_0F72_R_2_P_2 */ |
10280 | { "vpsrld", { Vex, XS, Ib } }, |
10833 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
10281 | }, |
10834 | }, |
10282 | { |
10835 | { |
10283 | /* VEX_W_0F72_R_4_P_2 */ |
10836 | /* VEX_W_0F72_R_4_P_2 */ |
10284 | { "vpsrad", { Vex, XS, Ib } }, |
10837 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
10285 | }, |
10838 | }, |
10286 | { |
10839 | { |
10287 | /* VEX_W_0F72_R_6_P_2 */ |
10840 | /* VEX_W_0F72_R_6_P_2 */ |
10288 | { "vpslld", { Vex, XS, Ib } }, |
10841 | { "vpslld", { Vex, XS, Ib }, 0 }, |
10289 | }, |
10842 | }, |
10290 | { |
10843 | { |
10291 | /* VEX_W_0F73_R_2_P_2 */ |
10844 | /* VEX_W_0F73_R_2_P_2 */ |
10292 | { "vpsrlq", { Vex, XS, Ib } }, |
10845 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
10293 | }, |
10846 | }, |
10294 | { |
10847 | { |
10295 | /* VEX_W_0F73_R_3_P_2 */ |
10848 | /* VEX_W_0F73_R_3_P_2 */ |
10296 | { "vpsrldq", { Vex, XS, Ib } }, |
10849 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
10297 | }, |
10850 | }, |
10298 | { |
10851 | { |
10299 | /* VEX_W_0F73_R_6_P_2 */ |
10852 | /* VEX_W_0F73_R_6_P_2 */ |
10300 | { "vpsllq", { Vex, XS, Ib } }, |
10853 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
10301 | }, |
10854 | }, |
10302 | { |
10855 | { |
10303 | /* VEX_W_0F73_R_7_P_2 */ |
10856 | /* VEX_W_0F73_R_7_P_2 */ |
10304 | { "vpslldq", { Vex, XS, Ib } }, |
10857 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
10305 | }, |
10858 | }, |
10306 | { |
10859 | { |
10307 | /* VEX_W_0F74_P_2 */ |
10860 | /* VEX_W_0F74_P_2 */ |
10308 | { "vpcmpeqb", { XM, Vex, EXx } }, |
10861 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
10309 | }, |
10862 | }, |
10310 | { |
10863 | { |
10311 | /* VEX_W_0F75_P_2 */ |
10864 | /* VEX_W_0F75_P_2 */ |
10312 | { "vpcmpeqw", { XM, Vex, EXx } }, |
10865 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
10313 | }, |
10866 | }, |
10314 | { |
10867 | { |
10315 | /* VEX_W_0F76_P_2 */ |
10868 | /* VEX_W_0F76_P_2 */ |
10316 | { "vpcmpeqd", { XM, Vex, EXx } }, |
10869 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
10317 | }, |
10870 | }, |
10318 | { |
10871 | { |
10319 | /* VEX_W_0F77_P_0 */ |
10872 | /* VEX_W_0F77_P_0 */ |
10320 | { "", { VZERO } }, |
10873 | { "", { VZERO }, 0 }, |
10321 | }, |
10874 | }, |
10322 | { |
10875 | { |
10323 | /* VEX_W_0F7C_P_2 */ |
10876 | /* VEX_W_0F7C_P_2 */ |
10324 | { "vhaddpd", { XM, Vex, EXx } }, |
10877 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
10325 | }, |
10878 | }, |
10326 | { |
10879 | { |
10327 | /* VEX_W_0F7C_P_3 */ |
10880 | /* VEX_W_0F7C_P_3 */ |
10328 | { "vhaddps", { XM, Vex, EXx } }, |
10881 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
10329 | }, |
10882 | }, |
10330 | { |
10883 | { |
10331 | /* VEX_W_0F7D_P_2 */ |
10884 | /* VEX_W_0F7D_P_2 */ |
- | 10885 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
|
- | 10886 | }, |
|
- | 10887 | { |
|
- | 10888 | /* VEX_W_0F7D_P_3 */ |
|
- | 10889 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
|
- | 10890 | }, |
|
10332 | { "vhsubpd", { XM, Vex, EXx } }, |
10891 | { |
10333 | }, |
10892 | /* VEX_W_0F7E_P_1 */ |
10334 | { |
10893 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
- | 10894 | }, |
|
- | 10895 | { |
|
- | 10896 | /* VEX_W_0F7F_P_1 */ |
|
- | 10897 | { "vmovdqu", { EXxS, XM }, 0 }, |
|
10335 | /* VEX_W_0F7D_P_3 */ |
10898 | }, |
- | 10899 | { |
|
- | 10900 | /* VEX_W_0F7F_P_2 */ |
|
10336 | { "vhsubps", { XM, Vex, EXx } }, |
10901 | { "vmovdqa", { EXxS, XM }, 0 }, |
10337 | }, |
10902 | }, |
10338 | { |
10903 | { |
- | 10904 | /* VEX_W_0F90_P_0_LEN_0 */ |
|
- | 10905 | { "kmovw", { MaskG, MaskE }, 0 }, |
|
- | 10906 | { "kmovq", { MaskG, MaskE }, 0 }, |
|
10339 | /* VEX_W_0F7E_P_1 */ |
10907 | }, |
- | 10908 | { |
|
- | 10909 | /* VEX_W_0F90_P_2_LEN_0 */ |
|
- | 10910 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
|
- | 10911 | { "kmovd", { MaskG, MaskBDE }, 0 }, |
|
- | 10912 | }, |
|
- | 10913 | { |
|
10340 | { "vmovq", { XMScalar, EXqScalar } }, |
10914 | /* VEX_W_0F91_P_0_LEN_0 */ |
10341 | }, |
10915 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, |
10342 | { |
10916 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, |
- | 10917 | }, |
|
- | 10918 | { |
|
- | 10919 | /* VEX_W_0F91_P_2_LEN_0 */ |
|
10343 | /* VEX_W_0F7F_P_1 */ |
10920 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, |
- | 10921 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, |
|
- | 10922 | }, |
|
- | 10923 | { |
|
- | 10924 | /* VEX_W_0F92_P_0_LEN_0 */ |
|
- | 10925 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, |
|
- | 10926 | }, |
|
10344 | { "vmovdqu", { EXxS, XM } }, |
10927 | { |
10345 | }, |
10928 | /* VEX_W_0F92_P_2_LEN_0 */ |
10346 | { |
10929 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, |
- | 10930 | }, |
|
- | 10931 | { |
|
- | 10932 | /* VEX_W_0F92_P_3_LEN_0 */ |
|
- | 10933 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, |
|
- | 10934 | { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, |
|
- | 10935 | }, |
|
10347 | /* VEX_W_0F7F_P_2 */ |
10936 | { |
- | 10937 | /* VEX_W_0F93_P_0_LEN_0 */ |
|
- | 10938 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, |
|
- | 10939 | }, |
|
- | 10940 | { |
|
- | 10941 | /* VEX_W_0F93_P_2_LEN_0 */ |
|
- | 10942 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, |
|
- | 10943 | }, |
|
- | 10944 | { |
|
- | 10945 | /* VEX_W_0F93_P_3_LEN_0 */ |
|
- | 10946 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, |
|
10348 | { "vmovdqa", { EXxS, XM } }, |
10947 | { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, |
10349 | }, |
10948 | }, |
10350 | { |
10949 | { |
10351 | /* VEX_W_0F90_P_0_LEN_0 */ |
10950 | /* VEX_W_0F98_P_0_LEN_0 */ |
10352 | { "kmovw", { MaskG, MaskE } }, |
10951 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, |
10353 | }, |
10952 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, |
10354 | { |
10953 | }, |
10355 | /* VEX_W_0F91_P_0_LEN_0 */ |
10954 | { |
10356 | { "kmovw", { Ew, MaskG } }, |
10955 | /* VEX_W_0F98_P_2_LEN_0 */ |
10357 | }, |
10956 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, |
10358 | { |
10957 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, |
10359 | /* VEX_W_0F92_P_0_LEN_0 */ |
10958 | }, |
10360 | { "kmovw", { MaskG, Rdq } }, |
10959 | { |
10361 | }, |
10960 | /* VEX_W_0F99_P_0_LEN_0 */ |
10362 | { |
10961 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, |
10363 | /* VEX_W_0F93_P_0_LEN_0 */ |
10962 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, |
10364 | { "kmovw", { Gdq, MaskR } }, |
10963 | }, |
10365 | }, |
10964 | { |
10366 | { |
10965 | /* VEX_W_0F99_P_2_LEN_0 */ |
10367 | /* VEX_W_0F98_P_0_LEN_0 */ |
10966 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, |
10368 | { "kortestw", { MaskG, MaskR } }, |
10967 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, |
10369 | }, |
10968 | }, |
10370 | { |
10969 | { |
10371 | /* VEX_W_0FAE_R_2_M_0 */ |
10970 | /* VEX_W_0FAE_R_2_M_0 */ |
10372 | { "vldmxcsr", { Md } }, |
10971 | { "vldmxcsr", { Md }, 0 }, |
10373 | }, |
10972 | }, |
10374 | { |
10973 | { |
10375 | /* VEX_W_0FAE_R_3_M_0 */ |
10974 | /* VEX_W_0FAE_R_3_M_0 */ |
10376 | { "vstmxcsr", { Md } }, |
10975 | { "vstmxcsr", { Md }, 0 }, |
10377 | }, |
10976 | }, |
10378 | { |
10977 | { |
10379 | /* VEX_W_0FC2_P_0 */ |
10978 | /* VEX_W_0FC2_P_0 */ |
10380 | { "vcmpps", { XM, Vex, EXx, VCMP } }, |
10979 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
10381 | }, |
10980 | }, |
10382 | { |
10981 | { |
10383 | /* VEX_W_0FC2_P_1 */ |
10982 | /* VEX_W_0FC2_P_1 */ |
10384 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } }, |
10983 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
10385 | }, |
10984 | }, |
10386 | { |
10985 | { |
10387 | /* VEX_W_0FC2_P_2 */ |
10986 | /* VEX_W_0FC2_P_2 */ |
10388 | { "vcmppd", { XM, Vex, EXx, VCMP } }, |
10987 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
10389 | }, |
10988 | }, |
10390 | { |
10989 | { |
10391 | /* VEX_W_0FC2_P_3 */ |
10990 | /* VEX_W_0FC2_P_3 */ |
10392 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } }, |
10991 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
10393 | }, |
10992 | }, |
10394 | { |
10993 | { |
10395 | /* VEX_W_0FC4_P_2 */ |
10994 | /* VEX_W_0FC4_P_2 */ |
10396 | { "vpinsrw", { XM, Vex128, Edqw, Ib } }, |
10995 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
10397 | }, |
10996 | }, |
10398 | { |
10997 | { |
10399 | /* VEX_W_0FC5_P_2 */ |
10998 | /* VEX_W_0FC5_P_2 */ |
10400 | { "vpextrw", { Gdq, XS, Ib } }, |
10999 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
10401 | }, |
11000 | }, |
10402 | { |
11001 | { |
10403 | /* VEX_W_0FD0_P_2 */ |
11002 | /* VEX_W_0FD0_P_2 */ |
10404 | { "vaddsubpd", { XM, Vex, EXx } }, |
11003 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
10405 | }, |
11004 | }, |
10406 | { |
11005 | { |
10407 | /* VEX_W_0FD0_P_3 */ |
11006 | /* VEX_W_0FD0_P_3 */ |
10408 | { "vaddsubps", { XM, Vex, EXx } }, |
11007 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
10409 | }, |
11008 | }, |
10410 | { |
11009 | { |
10411 | /* VEX_W_0FD1_P_2 */ |
11010 | /* VEX_W_0FD1_P_2 */ |
10412 | { "vpsrlw", { XM, Vex, EXxmm } }, |
11011 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
10413 | }, |
11012 | }, |
10414 | { |
11013 | { |
10415 | /* VEX_W_0FD2_P_2 */ |
11014 | /* VEX_W_0FD2_P_2 */ |
10416 | { "vpsrld", { XM, Vex, EXxmm } }, |
11015 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
10417 | }, |
11016 | }, |
10418 | { |
11017 | { |
10419 | /* VEX_W_0FD3_P_2 */ |
11018 | /* VEX_W_0FD3_P_2 */ |
10420 | { "vpsrlq", { XM, Vex, EXxmm } }, |
11019 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
10421 | }, |
11020 | }, |
10422 | { |
11021 | { |
10423 | /* VEX_W_0FD4_P_2 */ |
11022 | /* VEX_W_0FD4_P_2 */ |
10424 | { "vpaddq", { XM, Vex, EXx } }, |
11023 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
10425 | }, |
11024 | }, |
10426 | { |
11025 | { |
10427 | /* VEX_W_0FD5_P_2 */ |
11026 | /* VEX_W_0FD5_P_2 */ |
10428 | { "vpmullw", { XM, Vex, EXx } }, |
11027 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
10429 | }, |
11028 | }, |
10430 | { |
11029 | { |
10431 | /* VEX_W_0FD6_P_2 */ |
11030 | /* VEX_W_0FD6_P_2 */ |
10432 | { "vmovq", { EXqScalarS, XMScalar } }, |
11031 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
10433 | }, |
11032 | }, |
10434 | { |
11033 | { |
10435 | /* VEX_W_0FD7_P_2_M_1 */ |
11034 | /* VEX_W_0FD7_P_2_M_1 */ |
10436 | { "vpmovmskb", { Gdq, XS } }, |
11035 | { "vpmovmskb", { Gdq, XS }, 0 }, |
10437 | }, |
11036 | }, |
10438 | { |
11037 | { |
10439 | /* VEX_W_0FD8_P_2 */ |
11038 | /* VEX_W_0FD8_P_2 */ |
10440 | { "vpsubusb", { XM, Vex, EXx } }, |
11039 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
10441 | }, |
11040 | }, |
10442 | { |
11041 | { |
10443 | /* VEX_W_0FD9_P_2 */ |
11042 | /* VEX_W_0FD9_P_2 */ |
10444 | { "vpsubusw", { XM, Vex, EXx } }, |
11043 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
10445 | }, |
11044 | }, |
10446 | { |
11045 | { |
10447 | /* VEX_W_0FDA_P_2 */ |
11046 | /* VEX_W_0FDA_P_2 */ |
10448 | { "vpminub", { XM, Vex, EXx } }, |
11047 | { "vpminub", { XM, Vex, EXx }, 0 }, |
10449 | }, |
11048 | }, |
10450 | { |
11049 | { |
10451 | /* VEX_W_0FDB_P_2 */ |
11050 | /* VEX_W_0FDB_P_2 */ |
10452 | { "vpand", { XM, Vex, EXx } }, |
11051 | { "vpand", { XM, Vex, EXx }, 0 }, |
10453 | }, |
11052 | }, |
10454 | { |
11053 | { |
10455 | /* VEX_W_0FDC_P_2 */ |
11054 | /* VEX_W_0FDC_P_2 */ |
10456 | { "vpaddusb", { XM, Vex, EXx } }, |
11055 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
10457 | }, |
11056 | }, |
10458 | { |
11057 | { |
10459 | /* VEX_W_0FDD_P_2 */ |
11058 | /* VEX_W_0FDD_P_2 */ |
10460 | { "vpaddusw", { XM, Vex, EXx } }, |
11059 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
10461 | }, |
11060 | }, |
10462 | { |
11061 | { |
10463 | /* VEX_W_0FDE_P_2 */ |
11062 | /* VEX_W_0FDE_P_2 */ |
10464 | { "vpmaxub", { XM, Vex, EXx } }, |
11063 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
10465 | }, |
11064 | }, |
10466 | { |
11065 | { |
10467 | /* VEX_W_0FDF_P_2 */ |
11066 | /* VEX_W_0FDF_P_2 */ |
10468 | { "vpandn", { XM, Vex, EXx } }, |
11067 | { "vpandn", { XM, Vex, EXx }, 0 }, |
10469 | }, |
11068 | }, |
10470 | { |
11069 | { |
10471 | /* VEX_W_0FE0_P_2 */ |
11070 | /* VEX_W_0FE0_P_2 */ |
10472 | { "vpavgb", { XM, Vex, EXx } }, |
11071 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
10473 | }, |
11072 | }, |
10474 | { |
11073 | { |
10475 | /* VEX_W_0FE1_P_2 */ |
11074 | /* VEX_W_0FE1_P_2 */ |
10476 | { "vpsraw", { XM, Vex, EXxmm } }, |
11075 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
10477 | }, |
11076 | }, |
10478 | { |
11077 | { |
10479 | /* VEX_W_0FE2_P_2 */ |
11078 | /* VEX_W_0FE2_P_2 */ |
10480 | { "vpsrad", { XM, Vex, EXxmm } }, |
11079 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
10481 | }, |
11080 | }, |
10482 | { |
11081 | { |
10483 | /* VEX_W_0FE3_P_2 */ |
11082 | /* VEX_W_0FE3_P_2 */ |
10484 | { "vpavgw", { XM, Vex, EXx } }, |
11083 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
10485 | }, |
11084 | }, |
10486 | { |
11085 | { |
10487 | /* VEX_W_0FE4_P_2 */ |
11086 | /* VEX_W_0FE4_P_2 */ |
10488 | { "vpmulhuw", { XM, Vex, EXx } }, |
11087 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
10489 | }, |
11088 | }, |
10490 | { |
11089 | { |
10491 | /* VEX_W_0FE5_P_2 */ |
11090 | /* VEX_W_0FE5_P_2 */ |
10492 | { "vpmulhw", { XM, Vex, EXx } }, |
11091 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
10493 | }, |
11092 | }, |
10494 | { |
11093 | { |
10495 | /* VEX_W_0FE6_P_1 */ |
11094 | /* VEX_W_0FE6_P_1 */ |
10496 | { "vcvtdq2pd", { XM, EXxmmq } }, |
11095 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
10497 | }, |
11096 | }, |
10498 | { |
11097 | { |
10499 | /* VEX_W_0FE6_P_2 */ |
11098 | /* VEX_W_0FE6_P_2 */ |
10500 | { "vcvttpd2dq%XY", { XMM, EXx } }, |
11099 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
10501 | }, |
11100 | }, |
10502 | { |
11101 | { |
10503 | /* VEX_W_0FE6_P_3 */ |
11102 | /* VEX_W_0FE6_P_3 */ |
10504 | { "vcvtpd2dq%XY", { XMM, EXx } }, |
11103 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
10505 | }, |
11104 | }, |
10506 | { |
11105 | { |
10507 | /* VEX_W_0FE7_P_2_M_0 */ |
11106 | /* VEX_W_0FE7_P_2_M_0 */ |
10508 | { "vmovntdq", { Mx, XM } }, |
11107 | { "vmovntdq", { Mx, XM }, 0 }, |
10509 | }, |
11108 | }, |
10510 | { |
11109 | { |
10511 | /* VEX_W_0FE8_P_2 */ |
11110 | /* VEX_W_0FE8_P_2 */ |
10512 | { "vpsubsb", { XM, Vex, EXx } }, |
11111 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
10513 | }, |
11112 | }, |
10514 | { |
11113 | { |
10515 | /* VEX_W_0FE9_P_2 */ |
11114 | /* VEX_W_0FE9_P_2 */ |
10516 | { "vpsubsw", { XM, Vex, EXx } }, |
11115 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
10517 | }, |
11116 | }, |
10518 | { |
11117 | { |
10519 | /* VEX_W_0FEA_P_2 */ |
11118 | /* VEX_W_0FEA_P_2 */ |
10520 | { "vpminsw", { XM, Vex, EXx } }, |
11119 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
10521 | }, |
11120 | }, |
10522 | { |
11121 | { |
10523 | /* VEX_W_0FEB_P_2 */ |
11122 | /* VEX_W_0FEB_P_2 */ |
10524 | { "vpor", { XM, Vex, EXx } }, |
11123 | { "vpor", { XM, Vex, EXx }, 0 }, |
10525 | }, |
11124 | }, |
10526 | { |
11125 | { |
10527 | /* VEX_W_0FEC_P_2 */ |
11126 | /* VEX_W_0FEC_P_2 */ |
10528 | { "vpaddsb", { XM, Vex, EXx } }, |
11127 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
10529 | }, |
11128 | }, |
10530 | { |
11129 | { |
10531 | /* VEX_W_0FED_P_2 */ |
11130 | /* VEX_W_0FED_P_2 */ |
10532 | { "vpaddsw", { XM, Vex, EXx } }, |
11131 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
10533 | }, |
11132 | }, |
10534 | { |
11133 | { |
10535 | /* VEX_W_0FEE_P_2 */ |
11134 | /* VEX_W_0FEE_P_2 */ |
10536 | { "vpmaxsw", { XM, Vex, EXx } }, |
11135 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
10537 | }, |
11136 | }, |
10538 | { |
11137 | { |
10539 | /* VEX_W_0FEF_P_2 */ |
11138 | /* VEX_W_0FEF_P_2 */ |
10540 | { "vpxor", { XM, Vex, EXx } }, |
11139 | { "vpxor", { XM, Vex, EXx }, 0 }, |
10541 | }, |
11140 | }, |
10542 | { |
11141 | { |
10543 | /* VEX_W_0FF0_P_3_M_0 */ |
11142 | /* VEX_W_0FF0_P_3_M_0 */ |
10544 | { "vlddqu", { XM, M } }, |
11143 | { "vlddqu", { XM, M }, 0 }, |
10545 | }, |
11144 | }, |
10546 | { |
11145 | { |
10547 | /* VEX_W_0FF1_P_2 */ |
11146 | /* VEX_W_0FF1_P_2 */ |
10548 | { "vpsllw", { XM, Vex, EXxmm } }, |
11147 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
10549 | }, |
11148 | }, |
10550 | { |
11149 | { |
10551 | /* VEX_W_0FF2_P_2 */ |
11150 | /* VEX_W_0FF2_P_2 */ |
10552 | { "vpslld", { XM, Vex, EXxmm } }, |
11151 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
10553 | }, |
11152 | }, |
10554 | { |
11153 | { |
10555 | /* VEX_W_0FF3_P_2 */ |
11154 | /* VEX_W_0FF3_P_2 */ |
10556 | { "vpsllq", { XM, Vex, EXxmm } }, |
11155 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
10557 | }, |
11156 | }, |
10558 | { |
11157 | { |
10559 | /* VEX_W_0FF4_P_2 */ |
11158 | /* VEX_W_0FF4_P_2 */ |
10560 | { "vpmuludq", { XM, Vex, EXx } }, |
11159 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
10561 | }, |
11160 | }, |
10562 | { |
11161 | { |
10563 | /* VEX_W_0FF5_P_2 */ |
11162 | /* VEX_W_0FF5_P_2 */ |
10564 | { "vpmaddwd", { XM, Vex, EXx } }, |
11163 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
10565 | }, |
11164 | }, |
10566 | { |
11165 | { |
10567 | /* VEX_W_0FF6_P_2 */ |
11166 | /* VEX_W_0FF6_P_2 */ |
10568 | { "vpsadbw", { XM, Vex, EXx } }, |
11167 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
10569 | }, |
11168 | }, |
10570 | { |
11169 | { |
10571 | /* VEX_W_0FF7_P_2 */ |
11170 | /* VEX_W_0FF7_P_2 */ |
10572 | { "vmaskmovdqu", { XM, XS } }, |
11171 | { "vmaskmovdqu", { XM, XS }, 0 }, |
10573 | }, |
11172 | }, |
10574 | { |
11173 | { |
10575 | /* VEX_W_0FF8_P_2 */ |
11174 | /* VEX_W_0FF8_P_2 */ |
10576 | { "vpsubb", { XM, Vex, EXx } }, |
11175 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
10577 | }, |
11176 | }, |
10578 | { |
11177 | { |
10579 | /* VEX_W_0FF9_P_2 */ |
11178 | /* VEX_W_0FF9_P_2 */ |
10580 | { "vpsubw", { XM, Vex, EXx } }, |
11179 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
10581 | }, |
11180 | }, |
10582 | { |
11181 | { |
10583 | /* VEX_W_0FFA_P_2 */ |
11182 | /* VEX_W_0FFA_P_2 */ |
10584 | { "vpsubd", { XM, Vex, EXx } }, |
11183 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
10585 | }, |
11184 | }, |
10586 | { |
11185 | { |
10587 | /* VEX_W_0FFB_P_2 */ |
11186 | /* VEX_W_0FFB_P_2 */ |
10588 | { "vpsubq", { XM, Vex, EXx } }, |
11187 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
10589 | }, |
11188 | }, |
10590 | { |
11189 | { |
10591 | /* VEX_W_0FFC_P_2 */ |
11190 | /* VEX_W_0FFC_P_2 */ |
10592 | { "vpaddb", { XM, Vex, EXx } }, |
11191 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
10593 | }, |
11192 | }, |
10594 | { |
11193 | { |
10595 | /* VEX_W_0FFD_P_2 */ |
11194 | /* VEX_W_0FFD_P_2 */ |
10596 | { "vpaddw", { XM, Vex, EXx } }, |
11195 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
10597 | }, |
11196 | }, |
10598 | { |
11197 | { |
10599 | /* VEX_W_0FFE_P_2 */ |
11198 | /* VEX_W_0FFE_P_2 */ |
10600 | { "vpaddd", { XM, Vex, EXx } }, |
11199 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
10601 | }, |
11200 | }, |
10602 | { |
11201 | { |
10603 | /* VEX_W_0F3800_P_2 */ |
11202 | /* VEX_W_0F3800_P_2 */ |
10604 | { "vpshufb", { XM, Vex, EXx } }, |
11203 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
10605 | }, |
11204 | }, |
10606 | { |
11205 | { |
10607 | /* VEX_W_0F3801_P_2 */ |
11206 | /* VEX_W_0F3801_P_2 */ |
10608 | { "vphaddw", { XM, Vex, EXx } }, |
11207 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
10609 | }, |
11208 | }, |
10610 | { |
11209 | { |
10611 | /* VEX_W_0F3802_P_2 */ |
11210 | /* VEX_W_0F3802_P_2 */ |
10612 | { "vphaddd", { XM, Vex, EXx } }, |
11211 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
10613 | }, |
11212 | }, |
10614 | { |
11213 | { |
10615 | /* VEX_W_0F3803_P_2 */ |
11214 | /* VEX_W_0F3803_P_2 */ |
10616 | { "vphaddsw", { XM, Vex, EXx } }, |
11215 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
10617 | }, |
11216 | }, |
10618 | { |
11217 | { |
10619 | /* VEX_W_0F3804_P_2 */ |
11218 | /* VEX_W_0F3804_P_2 */ |
10620 | { "vpmaddubsw", { XM, Vex, EXx } }, |
11219 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
10621 | }, |
11220 | }, |
10622 | { |
11221 | { |
10623 | /* VEX_W_0F3805_P_2 */ |
11222 | /* VEX_W_0F3805_P_2 */ |
10624 | { "vphsubw", { XM, Vex, EXx } }, |
11223 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
10625 | }, |
11224 | }, |
10626 | { |
11225 | { |
10627 | /* VEX_W_0F3806_P_2 */ |
11226 | /* VEX_W_0F3806_P_2 */ |
10628 | { "vphsubd", { XM, Vex, EXx } }, |
11227 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
10629 | }, |
11228 | }, |
10630 | { |
11229 | { |
10631 | /* VEX_W_0F3807_P_2 */ |
11230 | /* VEX_W_0F3807_P_2 */ |
10632 | { "vphsubsw", { XM, Vex, EXx } }, |
11231 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
10633 | }, |
11232 | }, |
10634 | { |
11233 | { |
10635 | /* VEX_W_0F3808_P_2 */ |
11234 | /* VEX_W_0F3808_P_2 */ |
10636 | { "vpsignb", { XM, Vex, EXx } }, |
11235 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
10637 | }, |
11236 | }, |
10638 | { |
11237 | { |
10639 | /* VEX_W_0F3809_P_2 */ |
11238 | /* VEX_W_0F3809_P_2 */ |
10640 | { "vpsignw", { XM, Vex, EXx } }, |
11239 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
10641 | }, |
11240 | }, |
10642 | { |
11241 | { |
10643 | /* VEX_W_0F380A_P_2 */ |
11242 | /* VEX_W_0F380A_P_2 */ |
10644 | { "vpsignd", { XM, Vex, EXx } }, |
11243 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
10645 | }, |
11244 | }, |
10646 | { |
11245 | { |
10647 | /* VEX_W_0F380B_P_2 */ |
11246 | /* VEX_W_0F380B_P_2 */ |
10648 | { "vpmulhrsw", { XM, Vex, EXx } }, |
11247 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
10649 | }, |
11248 | }, |
10650 | { |
11249 | { |
10651 | /* VEX_W_0F380C_P_2 */ |
11250 | /* VEX_W_0F380C_P_2 */ |
10652 | { "vpermilps", { XM, Vex, EXx } }, |
11251 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
10653 | }, |
11252 | }, |
10654 | { |
11253 | { |
10655 | /* VEX_W_0F380D_P_2 */ |
11254 | /* VEX_W_0F380D_P_2 */ |
10656 | { "vpermilpd", { XM, Vex, EXx } }, |
11255 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
10657 | }, |
11256 | }, |
10658 | { |
11257 | { |
10659 | /* VEX_W_0F380E_P_2 */ |
11258 | /* VEX_W_0F380E_P_2 */ |
10660 | { "vtestps", { XM, EXx } }, |
11259 | { "vtestps", { XM, EXx }, 0 }, |
10661 | }, |
11260 | }, |
10662 | { |
11261 | { |
10663 | /* VEX_W_0F380F_P_2 */ |
11262 | /* VEX_W_0F380F_P_2 */ |
10664 | { "vtestpd", { XM, EXx } }, |
11263 | { "vtestpd", { XM, EXx }, 0 }, |
10665 | }, |
11264 | }, |
10666 | { |
11265 | { |
10667 | /* VEX_W_0F3816_P_2 */ |
11266 | /* VEX_W_0F3816_P_2 */ |
10668 | { "vpermps", { XM, Vex, EXx } }, |
11267 | { "vpermps", { XM, Vex, EXx }, 0 }, |
10669 | }, |
11268 | }, |
10670 | { |
11269 | { |
10671 | /* VEX_W_0F3817_P_2 */ |
11270 | /* VEX_W_0F3817_P_2 */ |
10672 | { "vptest", { XM, EXx } }, |
11271 | { "vptest", { XM, EXx }, 0 }, |
10673 | }, |
11272 | }, |
10674 | { |
11273 | { |
10675 | /* VEX_W_0F3818_P_2 */ |
11274 | /* VEX_W_0F3818_P_2 */ |
10676 | { "vbroadcastss", { XM, EXxmm_md } }, |
11275 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
10677 | }, |
11276 | }, |
10678 | { |
11277 | { |
10679 | /* VEX_W_0F3819_P_2 */ |
11278 | /* VEX_W_0F3819_P_2 */ |
10680 | { "vbroadcastsd", { XM, EXxmm_mq } }, |
11279 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
10681 | }, |
11280 | }, |
10682 | { |
11281 | { |
10683 | /* VEX_W_0F381A_P_2_M_0 */ |
11282 | /* VEX_W_0F381A_P_2_M_0 */ |
10684 | { "vbroadcastf128", { XM, Mxmm } }, |
11283 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
10685 | }, |
11284 | }, |
10686 | { |
11285 | { |
10687 | /* VEX_W_0F381C_P_2 */ |
11286 | /* VEX_W_0F381C_P_2 */ |
10688 | { "vpabsb", { XM, EXx } }, |
11287 | { "vpabsb", { XM, EXx }, 0 }, |
10689 | }, |
11288 | }, |
10690 | { |
11289 | { |
10691 | /* VEX_W_0F381D_P_2 */ |
11290 | /* VEX_W_0F381D_P_2 */ |
10692 | { "vpabsw", { XM, EXx } }, |
11291 | { "vpabsw", { XM, EXx }, 0 }, |
10693 | }, |
11292 | }, |
10694 | { |
11293 | { |
10695 | /* VEX_W_0F381E_P_2 */ |
11294 | /* VEX_W_0F381E_P_2 */ |
10696 | { "vpabsd", { XM, EXx } }, |
11295 | { "vpabsd", { XM, EXx }, 0 }, |
10697 | }, |
11296 | }, |
10698 | { |
11297 | { |
10699 | /* VEX_W_0F3820_P_2 */ |
11298 | /* VEX_W_0F3820_P_2 */ |
10700 | { "vpmovsxbw", { XM, EXxmmq } }, |
11299 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
10701 | }, |
11300 | }, |
10702 | { |
11301 | { |
10703 | /* VEX_W_0F3821_P_2 */ |
11302 | /* VEX_W_0F3821_P_2 */ |
10704 | { "vpmovsxbd", { XM, EXxmmqd } }, |
11303 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
10705 | }, |
11304 | }, |
10706 | { |
11305 | { |
10707 | /* VEX_W_0F3822_P_2 */ |
11306 | /* VEX_W_0F3822_P_2 */ |
10708 | { "vpmovsxbq", { XM, EXxmmdw } }, |
11307 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
10709 | }, |
11308 | }, |
10710 | { |
11309 | { |
10711 | /* VEX_W_0F3823_P_2 */ |
11310 | /* VEX_W_0F3823_P_2 */ |
10712 | { "vpmovsxwd", { XM, EXxmmq } }, |
11311 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
10713 | }, |
11312 | }, |
10714 | { |
11313 | { |
10715 | /* VEX_W_0F3824_P_2 */ |
11314 | /* VEX_W_0F3824_P_2 */ |
10716 | { "vpmovsxwq", { XM, EXxmmqd } }, |
11315 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
10717 | }, |
11316 | }, |
10718 | { |
11317 | { |
10719 | /* VEX_W_0F3825_P_2 */ |
11318 | /* VEX_W_0F3825_P_2 */ |
10720 | { "vpmovsxdq", { XM, EXxmmq } }, |
11319 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
10721 | }, |
11320 | }, |
10722 | { |
11321 | { |
10723 | /* VEX_W_0F3828_P_2 */ |
11322 | /* VEX_W_0F3828_P_2 */ |
10724 | { "vpmuldq", { XM, Vex, EXx } }, |
11323 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
10725 | }, |
11324 | }, |
10726 | { |
11325 | { |
10727 | /* VEX_W_0F3829_P_2 */ |
11326 | /* VEX_W_0F3829_P_2 */ |
10728 | { "vpcmpeqq", { XM, Vex, EXx } }, |
11327 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
10729 | }, |
11328 | }, |
10730 | { |
11329 | { |
10731 | /* VEX_W_0F382A_P_2_M_0 */ |
11330 | /* VEX_W_0F382A_P_2_M_0 */ |
10732 | { "vmovntdqa", { XM, Mx } }, |
11331 | { "vmovntdqa", { XM, Mx }, 0 }, |
10733 | }, |
11332 | }, |
10734 | { |
11333 | { |
10735 | /* VEX_W_0F382B_P_2 */ |
11334 | /* VEX_W_0F382B_P_2 */ |
10736 | { "vpackusdw", { XM, Vex, EXx } }, |
11335 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
10737 | }, |
11336 | }, |
10738 | { |
11337 | { |
10739 | /* VEX_W_0F382C_P_2_M_0 */ |
11338 | /* VEX_W_0F382C_P_2_M_0 */ |
10740 | { "vmaskmovps", { XM, Vex, Mx } }, |
11339 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
10741 | }, |
11340 | }, |
10742 | { |
11341 | { |
10743 | /* VEX_W_0F382D_P_2_M_0 */ |
11342 | /* VEX_W_0F382D_P_2_M_0 */ |
10744 | { "vmaskmovpd", { XM, Vex, Mx } }, |
11343 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
10745 | }, |
11344 | }, |
10746 | { |
11345 | { |
10747 | /* VEX_W_0F382E_P_2_M_0 */ |
11346 | /* VEX_W_0F382E_P_2_M_0 */ |
10748 | { "vmaskmovps", { Mx, Vex, XM } }, |
11347 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
10749 | }, |
11348 | }, |
10750 | { |
11349 | { |
10751 | /* VEX_W_0F382F_P_2_M_0 */ |
11350 | /* VEX_W_0F382F_P_2_M_0 */ |
10752 | { "vmaskmovpd", { Mx, Vex, XM } }, |
11351 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
10753 | }, |
11352 | }, |
10754 | { |
11353 | { |
10755 | /* VEX_W_0F3830_P_2 */ |
11354 | /* VEX_W_0F3830_P_2 */ |
10756 | { "vpmovzxbw", { XM, EXxmmq } }, |
11355 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
10757 | }, |
11356 | }, |
10758 | { |
11357 | { |
10759 | /* VEX_W_0F3831_P_2 */ |
11358 | /* VEX_W_0F3831_P_2 */ |
10760 | { "vpmovzxbd", { XM, EXxmmqd } }, |
11359 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
10761 | }, |
11360 | }, |
10762 | { |
11361 | { |
10763 | /* VEX_W_0F3832_P_2 */ |
11362 | /* VEX_W_0F3832_P_2 */ |
10764 | { "vpmovzxbq", { XM, EXxmmdw } }, |
11363 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
10765 | }, |
11364 | }, |
10766 | { |
11365 | { |
10767 | /* VEX_W_0F3833_P_2 */ |
11366 | /* VEX_W_0F3833_P_2 */ |
10768 | { "vpmovzxwd", { XM, EXxmmq } }, |
11367 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
10769 | }, |
11368 | }, |
10770 | { |
11369 | { |
10771 | /* VEX_W_0F3834_P_2 */ |
11370 | /* VEX_W_0F3834_P_2 */ |
10772 | { "vpmovzxwq", { XM, EXxmmqd } }, |
11371 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
10773 | }, |
11372 | }, |
10774 | { |
11373 | { |
10775 | /* VEX_W_0F3835_P_2 */ |
11374 | /* VEX_W_0F3835_P_2 */ |
10776 | { "vpmovzxdq", { XM, EXxmmq } }, |
11375 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
10777 | }, |
11376 | }, |
10778 | { |
11377 | { |
10779 | /* VEX_W_0F3836_P_2 */ |
11378 | /* VEX_W_0F3836_P_2 */ |
10780 | { "vpermd", { XM, Vex, EXx } }, |
11379 | { "vpermd", { XM, Vex, EXx }, 0 }, |
10781 | }, |
11380 | }, |
10782 | { |
11381 | { |
10783 | /* VEX_W_0F3837_P_2 */ |
11382 | /* VEX_W_0F3837_P_2 */ |
10784 | { "vpcmpgtq", { XM, Vex, EXx } }, |
11383 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
10785 | }, |
11384 | }, |
10786 | { |
11385 | { |
10787 | /* VEX_W_0F3838_P_2 */ |
11386 | /* VEX_W_0F3838_P_2 */ |
10788 | { "vpminsb", { XM, Vex, EXx } }, |
11387 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
10789 | }, |
11388 | }, |
10790 | { |
11389 | { |
10791 | /* VEX_W_0F3839_P_2 */ |
11390 | /* VEX_W_0F3839_P_2 */ |
10792 | { "vpminsd", { XM, Vex, EXx } }, |
11391 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
10793 | }, |
11392 | }, |
10794 | { |
11393 | { |
10795 | /* VEX_W_0F383A_P_2 */ |
11394 | /* VEX_W_0F383A_P_2 */ |
10796 | { "vpminuw", { XM, Vex, EXx } }, |
11395 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
10797 | }, |
11396 | }, |
10798 | { |
11397 | { |
10799 | /* VEX_W_0F383B_P_2 */ |
11398 | /* VEX_W_0F383B_P_2 */ |
10800 | { "vpminud", { XM, Vex, EXx } }, |
11399 | { "vpminud", { XM, Vex, EXx }, 0 }, |
10801 | }, |
11400 | }, |
10802 | { |
11401 | { |
10803 | /* VEX_W_0F383C_P_2 */ |
11402 | /* VEX_W_0F383C_P_2 */ |
10804 | { "vpmaxsb", { XM, Vex, EXx } }, |
11403 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
10805 | }, |
11404 | }, |
10806 | { |
11405 | { |
10807 | /* VEX_W_0F383D_P_2 */ |
11406 | /* VEX_W_0F383D_P_2 */ |
10808 | { "vpmaxsd", { XM, Vex, EXx } }, |
11407 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
10809 | }, |
11408 | }, |
10810 | { |
11409 | { |
10811 | /* VEX_W_0F383E_P_2 */ |
11410 | /* VEX_W_0F383E_P_2 */ |
10812 | { "vpmaxuw", { XM, Vex, EXx } }, |
11411 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
10813 | }, |
11412 | }, |
10814 | { |
11413 | { |
10815 | /* VEX_W_0F383F_P_2 */ |
11414 | /* VEX_W_0F383F_P_2 */ |
10816 | { "vpmaxud", { XM, Vex, EXx } }, |
11415 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
10817 | }, |
11416 | }, |
10818 | { |
11417 | { |
10819 | /* VEX_W_0F3840_P_2 */ |
11418 | /* VEX_W_0F3840_P_2 */ |
10820 | { "vpmulld", { XM, Vex, EXx } }, |
11419 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
10821 | }, |
11420 | }, |
10822 | { |
11421 | { |
10823 | /* VEX_W_0F3841_P_2 */ |
11422 | /* VEX_W_0F3841_P_2 */ |
10824 | { "vphminposuw", { XM, EXx } }, |
11423 | { "vphminposuw", { XM, EXx }, 0 }, |
10825 | }, |
11424 | }, |
10826 | { |
11425 | { |
10827 | /* VEX_W_0F3846_P_2 */ |
11426 | /* VEX_W_0F3846_P_2 */ |
10828 | { "vpsravd", { XM, Vex, EXx } }, |
11427 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
10829 | }, |
11428 | }, |
10830 | { |
11429 | { |
10831 | /* VEX_W_0F3858_P_2 */ |
11430 | /* VEX_W_0F3858_P_2 */ |
10832 | { "vpbroadcastd", { XM, EXxmm_md } }, |
11431 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
10833 | }, |
11432 | }, |
10834 | { |
11433 | { |
10835 | /* VEX_W_0F3859_P_2 */ |
11434 | /* VEX_W_0F3859_P_2 */ |
10836 | { "vpbroadcastq", { XM, EXxmm_mq } }, |
11435 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
10837 | }, |
11436 | }, |
10838 | { |
11437 | { |
10839 | /* VEX_W_0F385A_P_2_M_0 */ |
11438 | /* VEX_W_0F385A_P_2_M_0 */ |
10840 | { "vbroadcasti128", { XM, Mxmm } }, |
11439 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
10841 | }, |
11440 | }, |
10842 | { |
11441 | { |
10843 | /* VEX_W_0F3878_P_2 */ |
11442 | /* VEX_W_0F3878_P_2 */ |
10844 | { "vpbroadcastb", { XM, EXxmm_mb } }, |
11443 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
10845 | }, |
11444 | }, |
10846 | { |
11445 | { |
10847 | /* VEX_W_0F3879_P_2 */ |
11446 | /* VEX_W_0F3879_P_2 */ |
10848 | { "vpbroadcastw", { XM, EXxmm_mw } }, |
11447 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
10849 | }, |
11448 | }, |
10850 | { |
11449 | { |
10851 | /* VEX_W_0F38DB_P_2 */ |
11450 | /* VEX_W_0F38DB_P_2 */ |
10852 | { "vaesimc", { XM, EXx } }, |
11451 | { "vaesimc", { XM, EXx }, 0 }, |
10853 | }, |
11452 | }, |
10854 | { |
11453 | { |
10855 | /* VEX_W_0F38DC_P_2 */ |
11454 | /* VEX_W_0F38DC_P_2 */ |
10856 | { "vaesenc", { XM, Vex128, EXx } }, |
11455 | { "vaesenc", { XM, Vex128, EXx }, 0 }, |
10857 | }, |
11456 | }, |
10858 | { |
11457 | { |
10859 | /* VEX_W_0F38DD_P_2 */ |
11458 | /* VEX_W_0F38DD_P_2 */ |
10860 | { "vaesenclast", { XM, Vex128, EXx } }, |
11459 | { "vaesenclast", { XM, Vex128, EXx }, 0 }, |
10861 | }, |
11460 | }, |
10862 | { |
11461 | { |
10863 | /* VEX_W_0F38DE_P_2 */ |
11462 | /* VEX_W_0F38DE_P_2 */ |
10864 | { "vaesdec", { XM, Vex128, EXx } }, |
11463 | { "vaesdec", { XM, Vex128, EXx }, 0 }, |
10865 | }, |
11464 | }, |
10866 | { |
11465 | { |
10867 | /* VEX_W_0F38DF_P_2 */ |
11466 | /* VEX_W_0F38DF_P_2 */ |
10868 | { "vaesdeclast", { XM, Vex128, EXx } }, |
11467 | { "vaesdeclast", { XM, Vex128, EXx }, 0 }, |
10869 | }, |
11468 | }, |
10870 | { |
11469 | { |
10871 | /* VEX_W_0F3A00_P_2 */ |
11470 | /* VEX_W_0F3A00_P_2 */ |
10872 | { Bad_Opcode }, |
11471 | { Bad_Opcode }, |
10873 | { "vpermq", { XM, EXx, Ib } }, |
11472 | { "vpermq", { XM, EXx, Ib }, 0 }, |
10874 | }, |
11473 | }, |
10875 | { |
11474 | { |
10876 | /* VEX_W_0F3A01_P_2 */ |
11475 | /* VEX_W_0F3A01_P_2 */ |
10877 | { Bad_Opcode }, |
11476 | { Bad_Opcode }, |
10878 | { "vpermpd", { XM, EXx, Ib } }, |
11477 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
10879 | }, |
11478 | }, |
10880 | { |
11479 | { |
10881 | /* VEX_W_0F3A02_P_2 */ |
11480 | /* VEX_W_0F3A02_P_2 */ |
10882 | { "vpblendd", { XM, Vex, EXx, Ib } }, |
11481 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
10883 | }, |
11482 | }, |
10884 | { |
11483 | { |
10885 | /* VEX_W_0F3A04_P_2 */ |
11484 | /* VEX_W_0F3A04_P_2 */ |
10886 | { "vpermilps", { XM, EXx, Ib } }, |
11485 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
10887 | }, |
11486 | }, |
10888 | { |
11487 | { |
10889 | /* VEX_W_0F3A05_P_2 */ |
11488 | /* VEX_W_0F3A05_P_2 */ |
10890 | { "vpermilpd", { XM, EXx, Ib } }, |
11489 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
10891 | }, |
11490 | }, |
10892 | { |
11491 | { |
10893 | /* VEX_W_0F3A06_P_2 */ |
11492 | /* VEX_W_0F3A06_P_2 */ |
10894 | { "vperm2f128", { XM, Vex256, EXx, Ib } }, |
11493 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
10895 | }, |
11494 | }, |
10896 | { |
11495 | { |
10897 | /* VEX_W_0F3A08_P_2 */ |
11496 | /* VEX_W_0F3A08_P_2 */ |
10898 | { "vroundps", { XM, EXx, Ib } }, |
11497 | { "vroundps", { XM, EXx, Ib }, 0 }, |
10899 | }, |
11498 | }, |
10900 | { |
11499 | { |
10901 | /* VEX_W_0F3A09_P_2 */ |
11500 | /* VEX_W_0F3A09_P_2 */ |
10902 | { "vroundpd", { XM, EXx, Ib } }, |
11501 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
10903 | }, |
11502 | }, |
10904 | { |
11503 | { |
10905 | /* VEX_W_0F3A0A_P_2 */ |
11504 | /* VEX_W_0F3A0A_P_2 */ |
10906 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } }, |
11505 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
10907 | }, |
11506 | }, |
10908 | { |
11507 | { |
10909 | /* VEX_W_0F3A0B_P_2 */ |
11508 | /* VEX_W_0F3A0B_P_2 */ |
10910 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } }, |
11509 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
10911 | }, |
11510 | }, |
10912 | { |
11511 | { |
10913 | /* VEX_W_0F3A0C_P_2 */ |
11512 | /* VEX_W_0F3A0C_P_2 */ |
10914 | { "vblendps", { XM, Vex, EXx, Ib } }, |
11513 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
10915 | }, |
11514 | }, |
10916 | { |
11515 | { |
10917 | /* VEX_W_0F3A0D_P_2 */ |
11516 | /* VEX_W_0F3A0D_P_2 */ |
10918 | { "vblendpd", { XM, Vex, EXx, Ib } }, |
11517 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
10919 | }, |
11518 | }, |
10920 | { |
11519 | { |
10921 | /* VEX_W_0F3A0E_P_2 */ |
11520 | /* VEX_W_0F3A0E_P_2 */ |
10922 | { "vpblendw", { XM, Vex, EXx, Ib } }, |
11521 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
10923 | }, |
11522 | }, |
10924 | { |
11523 | { |
10925 | /* VEX_W_0F3A0F_P_2 */ |
11524 | /* VEX_W_0F3A0F_P_2 */ |
10926 | { "vpalignr", { XM, Vex, EXx, Ib } }, |
11525 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
10927 | }, |
11526 | }, |
10928 | { |
11527 | { |
10929 | /* VEX_W_0F3A14_P_2 */ |
11528 | /* VEX_W_0F3A14_P_2 */ |
10930 | { "vpextrb", { Edqb, XM, Ib } }, |
11529 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
10931 | }, |
11530 | }, |
10932 | { |
11531 | { |
10933 | /* VEX_W_0F3A15_P_2 */ |
11532 | /* VEX_W_0F3A15_P_2 */ |
10934 | { "vpextrw", { Edqw, XM, Ib } }, |
11533 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
10935 | }, |
11534 | }, |
10936 | { |
11535 | { |
- | 11536 | /* VEX_W_0F3A18_P_2 */ |
|
- | 11537 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
|
- | 11538 | }, |
|
- | 11539 | { |
|
- | 11540 | /* VEX_W_0F3A19_P_2 */ |
|
10937 | /* VEX_W_0F3A18_P_2 */ |
11541 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
- | 11542 | }, |
|
- | 11543 | { |
|
- | 11544 | /* VEX_W_0F3A20_P_2 */ |
|
- | 11545 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
|
10938 | { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, |
11546 | }, |
10939 | }, |
11547 | { |
- | 11548 | /* VEX_W_0F3A21_P_2 */ |
|
10940 | { |
11549 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
10941 | /* VEX_W_0F3A19_P_2 */ |
11550 | }, |
10942 | { "vextractf128", { EXxmm, XM, Ib } }, |
11551 | { |
10943 | }, |
11552 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
10944 | { |
11553 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10945 | /* VEX_W_0F3A20_P_2 */ |
11554 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, |
10946 | { "vpinsrb", { XM, Vex128, Edqb, Ib } }, |
11555 | }, |
10947 | }, |
11556 | { |
10948 | { |
11557 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
10949 | /* VEX_W_0F3A21_P_2 */ |
11558 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10950 | { "vinsertps", { XM, Vex128, EXd, Ib } }, |
11559 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, |
10951 | }, |
11560 | }, |
10952 | { |
11561 | { |
10953 | /* VEX_W_0F3A30_P_2 */ |
11562 | /* VEX_W_0F3A32_P_2_LEN_0 */ |
10954 | { Bad_Opcode }, |
11563 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10955 | { "kshiftrw", { MaskG, MaskR, Ib } }, |
11564 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, |
10956 | }, |
11565 | }, |
10957 | { |
11566 | { |
10958 | /* VEX_W_0F3A32_P_2 */ |
11567 | /* VEX_W_0F3A33_P_2_LEN_0 */ |
10959 | { Bad_Opcode }, |
11568 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10960 | { "kshiftlw", { MaskG, MaskR, Ib } }, |
11569 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, |
10961 | }, |
11570 | }, |
10962 | { |
11571 | { |
10963 | /* VEX_W_0F3A38_P_2 */ |
11572 | /* VEX_W_0F3A38_P_2 */ |
10964 | { "vinserti128", { XM, Vex256, EXxmm, Ib } }, |
11573 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
10965 | }, |
11574 | }, |
10966 | { |
11575 | { |
10967 | /* VEX_W_0F3A39_P_2 */ |
11576 | /* VEX_W_0F3A39_P_2 */ |
10968 | { "vextracti128", { EXxmm, XM, Ib } }, |
11577 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
10969 | }, |
11578 | }, |
10970 | { |
11579 | { |
10971 | /* VEX_W_0F3A40_P_2 */ |
11580 | /* VEX_W_0F3A40_P_2 */ |
10972 | { "vdpps", { XM, Vex, EXx, Ib } }, |
11581 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
10973 | }, |
11582 | }, |
10974 | { |
11583 | { |
10975 | /* VEX_W_0F3A41_P_2 */ |
11584 | /* VEX_W_0F3A41_P_2 */ |
10976 | { "vdppd", { XM, Vex128, EXx, Ib } }, |
11585 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
10977 | }, |
11586 | }, |
10978 | { |
11587 | { |
10979 | /* VEX_W_0F3A42_P_2 */ |
11588 | /* VEX_W_0F3A42_P_2 */ |
10980 | { "vmpsadbw", { XM, Vex, EXx, Ib } }, |
11589 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
10981 | }, |
11590 | }, |
10982 | { |
11591 | { |
10983 | /* VEX_W_0F3A44_P_2 */ |
11592 | /* VEX_W_0F3A44_P_2 */ |
10984 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, |
11593 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, |
10985 | }, |
11594 | }, |
10986 | { |
11595 | { |
10987 | /* VEX_W_0F3A46_P_2 */ |
11596 | /* VEX_W_0F3A46_P_2 */ |
10988 | { "vperm2i128", { XM, Vex256, EXx, Ib } }, |
11597 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
10989 | }, |
11598 | }, |
10990 | { |
11599 | { |
10991 | /* VEX_W_0F3A48_P_2 */ |
11600 | /* VEX_W_0F3A48_P_2 */ |
10992 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11601 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10993 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11602 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10994 | }, |
11603 | }, |
10995 | { |
11604 | { |
10996 | /* VEX_W_0F3A49_P_2 */ |
11605 | /* VEX_W_0F3A49_P_2 */ |
10997 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11606 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10998 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11607 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10999 | }, |
11608 | }, |
11000 | { |
11609 | { |
11001 | /* VEX_W_0F3A4A_P_2 */ |
11610 | /* VEX_W_0F3A4A_P_2 */ |
11002 | { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, |
11611 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
11003 | }, |
11612 | }, |
11004 | { |
11613 | { |
11005 | /* VEX_W_0F3A4B_P_2 */ |
11614 | /* VEX_W_0F3A4B_P_2 */ |
11006 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, |
11615 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
11007 | }, |
11616 | }, |
11008 | { |
11617 | { |
11009 | /* VEX_W_0F3A4C_P_2 */ |
11618 | /* VEX_W_0F3A4C_P_2 */ |
11010 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 } }, |
11619 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
11011 | }, |
11620 | }, |
11012 | { |
11621 | { |
11013 | /* VEX_W_0F3A60_P_2 */ |
11622 | /* VEX_W_0F3A60_P_2 */ |
11014 | { "vpcmpestrm", { XM, EXx, Ib } }, |
11623 | { "vpcmpestrm", { XM, EXx, Ib }, 0 }, |
Line 11015... | Line 11624... | ||
11015 | }, |
11624 | }, |
11016 | { |
11625 | { |
11017 | /* VEX_W_0F3A61_P_2 */ |
11626 | /* VEX_W_0F3A61_P_2 */ |
11018 | { "vpcmpestri", { XM, EXx, Ib } }, |
11627 | { "vpcmpestri", { XM, EXx, Ib }, 0 }, |
11019 | }, |
11628 | }, |
11020 | { |
11629 | { |
11021 | /* VEX_W_0F3A62_P_2 */ |
11630 | /* VEX_W_0F3A62_P_2 */ |
11022 | { "vpcmpistrm", { XM, EXx, Ib } }, |
11631 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
11023 | }, |
11632 | }, |
Line 11048... | Line 11657... | ||
11048 | /* MOD_C7_REG_7 */ |
11657 | /* MOD_C7_REG_7 */ |
11049 | { Bad_Opcode }, |
11658 | { Bad_Opcode }, |
11050 | { RM_TABLE (RM_C7_REG_7) }, |
11659 | { RM_TABLE (RM_C7_REG_7) }, |
11051 | }, |
11660 | }, |
11052 | { |
11661 | { |
- | 11662 | /* MOD_FF_REG_3 */ |
|
- | 11663 | { "Jcall^", { indirEp }, 0 }, |
|
- | 11664 | }, |
|
- | 11665 | { |
|
- | 11666 | /* MOD_FF_REG_5 */ |
|
- | 11667 | { "Jjmp^", { indirEp }, 0 }, |
|
- | 11668 | }, |
|
- | 11669 | { |
|
11053 | /* MOD_0F01_REG_0 */ |
11670 | /* MOD_0F01_REG_0 */ |
11054 | { X86_64_TABLE (X86_64_0F01_REG_0) }, |
11671 | { X86_64_TABLE (X86_64_0F01_REG_0) }, |
11055 | { RM_TABLE (RM_0F01_REG_0) }, |
11672 | { RM_TABLE (RM_0F01_REG_0) }, |
11056 | }, |
11673 | }, |
11057 | { |
11674 | { |
Line 11068... | Line 11685... | ||
11068 | /* MOD_0F01_REG_3 */ |
11685 | /* MOD_0F01_REG_3 */ |
11069 | { X86_64_TABLE (X86_64_0F01_REG_3) }, |
11686 | { X86_64_TABLE (X86_64_0F01_REG_3) }, |
11070 | { RM_TABLE (RM_0F01_REG_3) }, |
11687 | { RM_TABLE (RM_0F01_REG_3) }, |
11071 | }, |
11688 | }, |
11072 | { |
11689 | { |
- | 11690 | /* MOD_0F01_REG_5 */ |
|
- | 11691 | { Bad_Opcode }, |
|
- | 11692 | { RM_TABLE (RM_0F01_REG_5) }, |
|
- | 11693 | }, |
|
- | 11694 | { |
|
11073 | /* MOD_0F01_REG_7 */ |
11695 | /* MOD_0F01_REG_7 */ |
11074 | { "invlpg", { Mb } }, |
11696 | { "invlpg", { Mb }, 0 }, |
11075 | { RM_TABLE (RM_0F01_REG_7) }, |
11697 | { RM_TABLE (RM_0F01_REG_7) }, |
11076 | }, |
11698 | }, |
11077 | { |
11699 | { |
11078 | /* MOD_0F12_PREFIX_0 */ |
11700 | /* MOD_0F12_PREFIX_0 */ |
11079 | { "movlps", { XM, EXq } }, |
11701 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11080 | { "movhlps", { XM, EXq } }, |
11702 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, |
11081 | }, |
11703 | }, |
11082 | { |
11704 | { |
11083 | /* MOD_0F13 */ |
11705 | /* MOD_0F13 */ |
11084 | { "movlpX", { EXq, XM } }, |
11706 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
11085 | }, |
11707 | }, |
11086 | { |
11708 | { |
11087 | /* MOD_0F16_PREFIX_0 */ |
11709 | /* MOD_0F16_PREFIX_0 */ |
11088 | { "movhps", { XM, EXq } }, |
11710 | { "movhps", { XM, EXq }, 0 }, |
11089 | { "movlhps", { XM, EXq } }, |
11711 | { "movlhps", { XM, EXq }, 0 }, |
11090 | }, |
11712 | }, |
11091 | { |
11713 | { |
11092 | /* MOD_0F17 */ |
11714 | /* MOD_0F17 */ |
11093 | { "movhpX", { EXq, XM } }, |
11715 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
11094 | }, |
11716 | }, |
11095 | { |
11717 | { |
11096 | /* MOD_0F18_REG_0 */ |
11718 | /* MOD_0F18_REG_0 */ |
11097 | { "prefetchnta", { Mb } }, |
11719 | { "prefetchnta", { Mb }, 0 }, |
11098 | }, |
11720 | }, |
11099 | { |
11721 | { |
11100 | /* MOD_0F18_REG_1 */ |
11722 | /* MOD_0F18_REG_1 */ |
11101 | { "prefetcht0", { Mb } }, |
11723 | { "prefetcht0", { Mb }, 0 }, |
11102 | }, |
11724 | }, |
11103 | { |
11725 | { |
11104 | /* MOD_0F18_REG_2 */ |
11726 | /* MOD_0F18_REG_2 */ |
11105 | { "prefetcht1", { Mb } }, |
11727 | { "prefetcht1", { Mb }, 0 }, |
11106 | }, |
11728 | }, |
11107 | { |
11729 | { |
11108 | /* MOD_0F18_REG_3 */ |
11730 | /* MOD_0F18_REG_3 */ |
11109 | { "prefetcht2", { Mb } }, |
11731 | { "prefetcht2", { Mb }, 0 }, |
11110 | }, |
11732 | }, |
11111 | { |
11733 | { |
11112 | /* MOD_0F18_REG_4 */ |
11734 | /* MOD_0F18_REG_4 */ |
11113 | { "nop/reserved", { Mb } }, |
11735 | { "nop/reserved", { Mb }, 0 }, |
11114 | }, |
11736 | }, |
11115 | { |
11737 | { |
11116 | /* MOD_0F18_REG_5 */ |
11738 | /* MOD_0F18_REG_5 */ |
11117 | { "nop/reserved", { Mb } }, |
11739 | { "nop/reserved", { Mb }, 0 }, |
11118 | }, |
11740 | }, |
11119 | { |
11741 | { |
11120 | /* MOD_0F18_REG_6 */ |
11742 | /* MOD_0F18_REG_6 */ |
11121 | { "nop/reserved", { Mb } }, |
11743 | { "nop/reserved", { Mb }, 0 }, |
11122 | }, |
11744 | }, |
11123 | { |
11745 | { |
11124 | /* MOD_0F18_REG_7 */ |
11746 | /* MOD_0F18_REG_7 */ |
11125 | { "nop/reserved", { Mb } }, |
11747 | { "nop/reserved", { Mb }, 0 }, |
11126 | }, |
11748 | }, |
11127 | { |
11749 | { |
11128 | /* MOD_0F1A_PREFIX_0 */ |
11750 | /* MOD_0F1A_PREFIX_0 */ |
11129 | { "bndldx", { Gbnd, Ev_bnd } }, |
11751 | { "bndldx", { Gbnd, Ev_bnd }, 0 }, |
11130 | { "nopQ", { Ev } }, |
11752 | { "nopQ", { Ev }, 0 }, |
11131 | }, |
11753 | }, |
11132 | { |
11754 | { |
11133 | /* MOD_0F1B_PREFIX_0 */ |
11755 | /* MOD_0F1B_PREFIX_0 */ |
11134 | { "bndstx", { Ev_bnd, Gbnd } }, |
11756 | { "bndstx", { Ev_bnd, Gbnd }, 0 }, |
11135 | { "nopQ", { Ev } }, |
11757 | { "nopQ", { Ev }, 0 }, |
11136 | }, |
11758 | }, |
11137 | { |
11759 | { |
11138 | /* MOD_0F1B_PREFIX_1 */ |
11760 | /* MOD_0F1B_PREFIX_1 */ |
11139 | { "bndmk", { Gbnd, Ev_bnd } }, |
11761 | { "bndmk", { Gbnd, Ev_bnd }, 0 }, |
11140 | { "nopQ", { Ev } }, |
11762 | { "nopQ", { Ev }, 0 }, |
11141 | }, |
- | |
11142 | { |
- | |
11143 | /* MOD_0F20 */ |
- | |
11144 | { Bad_Opcode }, |
- | |
11145 | { "movZ", { Rm, Cm } }, |
- | |
11146 | }, |
- | |
11147 | { |
- | |
11148 | /* MOD_0F21 */ |
- | |
11149 | { Bad_Opcode }, |
- | |
11150 | { "movZ", { Rm, Dm } }, |
- | |
11151 | }, |
- | |
11152 | { |
- | |
11153 | /* MOD_0F22 */ |
- | |
11154 | { Bad_Opcode }, |
- | |
11155 | { "movZ", { Cm, Rm } }, |
- | |
11156 | }, |
- | |
11157 | { |
- | |
11158 | /* MOD_0F23 */ |
- | |
11159 | { Bad_Opcode }, |
- | |
11160 | { "movZ", { Dm, Rm } }, |
- | |
11161 | }, |
11763 | }, |
11162 | { |
11764 | { |
11163 | /* MOD_0F24 */ |
11765 | /* MOD_0F24 */ |
11164 | { Bad_Opcode }, |
11766 | { Bad_Opcode }, |
11165 | { "movL", { Rd, Td } }, |
11767 | { "movL", { Rd, Td }, 0 }, |
11166 | }, |
11768 | }, |
11167 | { |
11769 | { |
11168 | /* MOD_0F26 */ |
11770 | /* MOD_0F26 */ |
11169 | { Bad_Opcode }, |
11771 | { Bad_Opcode }, |
11170 | { "movL", { Td, Rd } }, |
11772 | { "movL", { Td, Rd }, 0 }, |
11171 | }, |
11773 | }, |
11172 | { |
11774 | { |
11173 | /* MOD_0F2B_PREFIX_0 */ |
11775 | /* MOD_0F2B_PREFIX_0 */ |
11174 | {"movntps", { Mx, XM } }, |
11776 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
11175 | }, |
11777 | }, |
11176 | { |
11778 | { |
11177 | /* MOD_0F2B_PREFIX_1 */ |
11779 | /* MOD_0F2B_PREFIX_1 */ |
11178 | {"movntss", { Md, XM } }, |
11780 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
11179 | }, |
11781 | }, |
11180 | { |
11782 | { |
11181 | /* MOD_0F2B_PREFIX_2 */ |
11783 | /* MOD_0F2B_PREFIX_2 */ |
11182 | {"movntpd", { Mx, XM } }, |
11784 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
11183 | }, |
11785 | }, |
11184 | { |
11786 | { |
11185 | /* MOD_0F2B_PREFIX_3 */ |
11787 | /* MOD_0F2B_PREFIX_3 */ |
11186 | {"movntsd", { Mq, XM } }, |
11788 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
11187 | }, |
11789 | }, |
11188 | { |
11790 | { |
11189 | /* MOD_0F51 */ |
11791 | /* MOD_0F51 */ |
11190 | { Bad_Opcode }, |
11792 | { Bad_Opcode }, |
11191 | { "movmskpX", { Gdq, XS } }, |
11793 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
11192 | }, |
11794 | }, |
11193 | { |
11795 | { |
11194 | /* MOD_0F71_REG_2 */ |
11796 | /* MOD_0F71_REG_2 */ |
11195 | { Bad_Opcode }, |
11797 | { Bad_Opcode }, |
11196 | { "psrlw", { MS, Ib } }, |
11798 | { "psrlw", { MS, Ib }, 0 }, |
11197 | }, |
11799 | }, |
11198 | { |
11800 | { |
11199 | /* MOD_0F71_REG_4 */ |
11801 | /* MOD_0F71_REG_4 */ |
11200 | { Bad_Opcode }, |
11802 | { Bad_Opcode }, |
11201 | { "psraw", { MS, Ib } }, |
11803 | { "psraw", { MS, Ib }, 0 }, |
11202 | }, |
11804 | }, |
11203 | { |
11805 | { |
11204 | /* MOD_0F71_REG_6 */ |
11806 | /* MOD_0F71_REG_6 */ |
11205 | { Bad_Opcode }, |
11807 | { Bad_Opcode }, |
11206 | { "psllw", { MS, Ib } }, |
11808 | { "psllw", { MS, Ib }, 0 }, |
11207 | }, |
11809 | }, |
11208 | { |
11810 | { |
11209 | /* MOD_0F72_REG_2 */ |
11811 | /* MOD_0F72_REG_2 */ |
11210 | { Bad_Opcode }, |
11812 | { Bad_Opcode }, |
11211 | { "psrld", { MS, Ib } }, |
11813 | { "psrld", { MS, Ib }, 0 }, |
11212 | }, |
11814 | }, |
11213 | { |
11815 | { |
11214 | /* MOD_0F72_REG_4 */ |
11816 | /* MOD_0F72_REG_4 */ |
11215 | { Bad_Opcode }, |
11817 | { Bad_Opcode }, |
11216 | { "psrad", { MS, Ib } }, |
11818 | { "psrad", { MS, Ib }, 0 }, |
11217 | }, |
11819 | }, |
11218 | { |
11820 | { |
11219 | /* MOD_0F72_REG_6 */ |
11821 | /* MOD_0F72_REG_6 */ |
11220 | { Bad_Opcode }, |
11822 | { Bad_Opcode }, |
11221 | { "pslld", { MS, Ib } }, |
11823 | { "pslld", { MS, Ib }, 0 }, |
11222 | }, |
11824 | }, |
11223 | { |
11825 | { |
11224 | /* MOD_0F73_REG_2 */ |
11826 | /* MOD_0F73_REG_2 */ |
11225 | { Bad_Opcode }, |
11827 | { Bad_Opcode }, |
11226 | { "psrlq", { MS, Ib } }, |
11828 | { "psrlq", { MS, Ib }, 0 }, |
11227 | }, |
11829 | }, |
11228 | { |
11830 | { |
11229 | /* MOD_0F73_REG_3 */ |
11831 | /* MOD_0F73_REG_3 */ |
11230 | { Bad_Opcode }, |
11832 | { Bad_Opcode }, |
11231 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11833 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11232 | }, |
11834 | }, |
11233 | { |
11835 | { |
11234 | /* MOD_0F73_REG_6 */ |
11836 | /* MOD_0F73_REG_6 */ |
11235 | { Bad_Opcode }, |
11837 | { Bad_Opcode }, |
11236 | { "psllq", { MS, Ib } }, |
11838 | { "psllq", { MS, Ib }, 0 }, |
11237 | }, |
11839 | }, |
11238 | { |
11840 | { |
11239 | /* MOD_0F73_REG_7 */ |
11841 | /* MOD_0F73_REG_7 */ |
11240 | { Bad_Opcode }, |
11842 | { Bad_Opcode }, |
11241 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11843 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11242 | }, |
11844 | }, |
11243 | { |
11845 | { |
11244 | /* MOD_0FAE_REG_0 */ |
11846 | /* MOD_0FAE_REG_0 */ |
11245 | { "fxsave", { FXSAVE } }, |
11847 | { "fxsave", { FXSAVE }, 0 }, |
11246 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
11848 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
11247 | }, |
11849 | }, |
11248 | { |
11850 | { |
11249 | /* MOD_0FAE_REG_1 */ |
11851 | /* MOD_0FAE_REG_1 */ |
11250 | { "fxrstor", { FXSAVE } }, |
11852 | { "fxrstor", { FXSAVE }, 0 }, |
11251 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
11853 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
11252 | }, |
11854 | }, |
11253 | { |
11855 | { |
11254 | /* MOD_0FAE_REG_2 */ |
11856 | /* MOD_0FAE_REG_2 */ |
11255 | { "ldmxcsr", { Md } }, |
11857 | { "ldmxcsr", { Md }, 0 }, |
11256 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
11858 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
11257 | }, |
11859 | }, |
11258 | { |
11860 | { |
11259 | /* MOD_0FAE_REG_3 */ |
11861 | /* MOD_0FAE_REG_3 */ |
11260 | { "stmxcsr", { Md } }, |
11862 | { "stmxcsr", { Md }, 0 }, |
11261 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
11863 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
11262 | }, |
11864 | }, |
11263 | { |
11865 | { |
11264 | /* MOD_0FAE_REG_4 */ |
11866 | /* MOD_0FAE_REG_4 */ |
11265 | { "xsave", { FXSAVE } }, |
11867 | { "xsave", { FXSAVE }, 0 }, |
11266 | }, |
11868 | }, |
11267 | { |
11869 | { |
11268 | /* MOD_0FAE_REG_5 */ |
11870 | /* MOD_0FAE_REG_5 */ |
11269 | { "xrstor", { FXSAVE } }, |
11871 | { "xrstor", { FXSAVE }, 0 }, |
11270 | { RM_TABLE (RM_0FAE_REG_5) }, |
11872 | { RM_TABLE (RM_0FAE_REG_5) }, |
11271 | }, |
11873 | }, |
11272 | { |
11874 | { |
11273 | /* MOD_0FAE_REG_6 */ |
11875 | /* MOD_0FAE_REG_6 */ |
11274 | { "xsaveopt", { FXSAVE } }, |
11876 | { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, |
11275 | { RM_TABLE (RM_0FAE_REG_6) }, |
11877 | { RM_TABLE (RM_0FAE_REG_6) }, |
11276 | }, |
11878 | }, |
11277 | { |
11879 | { |
11278 | /* MOD_0FAE_REG_7 */ |
11880 | /* MOD_0FAE_REG_7 */ |
11279 | { "clflush", { Mb } }, |
11881 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
11280 | { RM_TABLE (RM_0FAE_REG_7) }, |
11882 | { RM_TABLE (RM_0FAE_REG_7) }, |
11281 | }, |
11883 | }, |
11282 | { |
11884 | { |
11283 | /* MOD_0FB2 */ |
11885 | /* MOD_0FB2 */ |
11284 | { "lssS", { Gv, Mp } }, |
11886 | { "lssS", { Gv, Mp }, 0 }, |
11285 | }, |
11887 | }, |
11286 | { |
11888 | { |
11287 | /* MOD_0FB4 */ |
11889 | /* MOD_0FB4 */ |
11288 | { "lfsS", { Gv, Mp } }, |
11890 | { "lfsS", { Gv, Mp }, 0 }, |
11289 | }, |
11891 | }, |
11290 | { |
11892 | { |
11291 | /* MOD_0FB5 */ |
11893 | /* MOD_0FB5 */ |
11292 | { "lgsS", { Gv, Mp } }, |
11894 | { "lgsS", { Gv, Mp }, 0 }, |
- | 11895 | }, |
|
- | 11896 | { |
|
- | 11897 | /* MOD_0FC3 */ |
|
- | 11898 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, |
|
- | 11899 | }, |
|
- | 11900 | { |
|
- | 11901 | /* MOD_0FC7_REG_3 */ |
|
- | 11902 | { "xrstors", { FXSAVE }, 0 }, |
|
- | 11903 | }, |
|
- | 11904 | { |
|
- | 11905 | /* MOD_0FC7_REG_4 */ |
|
- | 11906 | { "xsavec", { FXSAVE }, 0 }, |
|
- | 11907 | }, |
|
- | 11908 | { |
|
- | 11909 | /* MOD_0FC7_REG_5 */ |
|
- | 11910 | { "xsaves", { FXSAVE }, 0 }, |
|
11293 | }, |
11911 | }, |
11294 | { |
11912 | { |
11295 | /* MOD_0FC7_REG_6 */ |
11913 | /* MOD_0FC7_REG_6 */ |
11296 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, |
11914 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11297 | { "rdrand", { Ev } }, |
11915 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } |
11298 | }, |
11916 | }, |
11299 | { |
11917 | { |
11300 | /* MOD_0FC7_REG_7 */ |
11918 | /* MOD_0FC7_REG_7 */ |
11301 | { "vmptrst", { Mq } }, |
11919 | { "vmptrst", { Mq }, 0 }, |
11302 | { "rdseed", { Ev } }, |
11920 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
11303 | }, |
11921 | }, |
11304 | { |
11922 | { |
11305 | /* MOD_0FD7 */ |
11923 | /* MOD_0FD7 */ |
11306 | { Bad_Opcode }, |
11924 | { Bad_Opcode }, |
11307 | { "pmovmskb", { Gdq, MS } }, |
11925 | { "pmovmskb", { Gdq, MS }, 0 }, |
11308 | }, |
11926 | }, |
11309 | { |
11927 | { |
11310 | /* MOD_0FE7_PREFIX_2 */ |
11928 | /* MOD_0FE7_PREFIX_2 */ |
11311 | { "movntdq", { Mx, XM } }, |
11929 | { "movntdq", { Mx, XM }, 0 }, |
11312 | }, |
11930 | }, |
11313 | { |
11931 | { |
11314 | /* MOD_0FF0_PREFIX_3 */ |
11932 | /* MOD_0FF0_PREFIX_3 */ |
11315 | { "lddqu", { XM, M } }, |
11933 | { "lddqu", { XM, M }, 0 }, |
11316 | }, |
11934 | }, |
11317 | { |
11935 | { |
11318 | /* MOD_0F382A_PREFIX_2 */ |
11936 | /* MOD_0F382A_PREFIX_2 */ |
11319 | { "movntdqa", { XM, Mx } }, |
11937 | { "movntdqa", { XM, Mx }, 0 }, |
11320 | }, |
11938 | }, |
11321 | { |
11939 | { |
11322 | /* MOD_62_32BIT */ |
11940 | /* MOD_62_32BIT */ |
11323 | { "bound{S|}", { Gv, Ma } }, |
11941 | { "bound{S|}", { Gv, Ma }, 0 }, |
11324 | { EVEX_TABLE (EVEX_0F) }, |
11942 | { EVEX_TABLE (EVEX_0F) }, |
11325 | }, |
11943 | }, |
11326 | { |
11944 | { |
11327 | /* MOD_C4_32BIT */ |
11945 | /* MOD_C4_32BIT */ |
11328 | { "lesS", { Gv, Mp } }, |
11946 | { "lesS", { Gv, Mp }, 0 }, |
11329 | { VEX_C4_TABLE (VEX_0F) }, |
11947 | { VEX_C4_TABLE (VEX_0F) }, |
11330 | }, |
11948 | }, |
11331 | { |
11949 | { |
11332 | /* MOD_C5_32BIT */ |
11950 | /* MOD_C5_32BIT */ |
11333 | { "ldsS", { Gv, Mp } }, |
11951 | { "ldsS", { Gv, Mp }, 0 }, |
11334 | { VEX_C5_TABLE (VEX_0F) }, |
11952 | { VEX_C5_TABLE (VEX_0F) }, |
11335 | }, |
11953 | }, |
11336 | { |
11954 | { |
11337 | /* MOD_VEX_0F12_PREFIX_0 */ |
11955 | /* MOD_VEX_0F12_PREFIX_0 */ |
11338 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, |
11956 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, |
Line 11354... | Line 11972... | ||
11354 | { |
11972 | { |
11355 | /* MOD_VEX_0F2B */ |
11973 | /* MOD_VEX_0F2B */ |
11356 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, |
11974 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, |
11357 | }, |
11975 | }, |
11358 | { |
11976 | { |
- | 11977 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ |
|
- | 11978 | { Bad_Opcode }, |
|
- | 11979 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 11980 | }, |
|
- | 11981 | { |
|
- | 11982 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ |
|
- | 11983 | { Bad_Opcode }, |
|
- | 11984 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 11985 | }, |
|
- | 11986 | { |
|
- | 11987 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ |
|
- | 11988 | { Bad_Opcode }, |
|
- | 11989 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 11990 | }, |
|
- | 11991 | { |
|
- | 11992 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ |
|
- | 11993 | { Bad_Opcode }, |
|
- | 11994 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 11995 | }, |
|
- | 11996 | { |
|
- | 11997 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ |
|
- | 11998 | { Bad_Opcode }, |
|
- | 11999 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12000 | }, |
|
- | 12001 | { |
|
- | 12002 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ |
|
- | 12003 | { Bad_Opcode }, |
|
- | 12004 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12005 | }, |
|
- | 12006 | { |
|
- | 12007 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ |
|
- | 12008 | { Bad_Opcode }, |
|
- | 12009 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12010 | }, |
|
- | 12011 | { |
|
- | 12012 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ |
|
- | 12013 | { Bad_Opcode }, |
|
- | 12014 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12015 | }, |
|
- | 12016 | { |
|
- | 12017 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ |
|
- | 12018 | { Bad_Opcode }, |
|
- | 12019 | { "knotw", { MaskG, MaskR }, 0 }, |
|
- | 12020 | }, |
|
- | 12021 | { |
|
- | 12022 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ |
|
- | 12023 | { Bad_Opcode }, |
|
- | 12024 | { "knotq", { MaskG, MaskR }, 0 }, |
|
- | 12025 | }, |
|
- | 12026 | { |
|
- | 12027 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ |
|
- | 12028 | { Bad_Opcode }, |
|
- | 12029 | { "knotb", { MaskG, MaskR }, 0 }, |
|
- | 12030 | }, |
|
- | 12031 | { |
|
- | 12032 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ |
|
- | 12033 | { Bad_Opcode }, |
|
- | 12034 | { "knotd", { MaskG, MaskR }, 0 }, |
|
- | 12035 | }, |
|
- | 12036 | { |
|
- | 12037 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ |
|
- | 12038 | { Bad_Opcode }, |
|
- | 12039 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12040 | }, |
|
- | 12041 | { |
|
- | 12042 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ |
|
- | 12043 | { Bad_Opcode }, |
|
- | 12044 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12045 | }, |
|
- | 12046 | { |
|
- | 12047 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ |
|
- | 12048 | { Bad_Opcode }, |
|
- | 12049 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12050 | }, |
|
- | 12051 | { |
|
- | 12052 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ |
|
- | 12053 | { Bad_Opcode }, |
|
- | 12054 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12055 | }, |
|
- | 12056 | { |
|
- | 12057 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ |
|
- | 12058 | { Bad_Opcode }, |
|
- | 12059 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12060 | }, |
|
- | 12061 | { |
|
- | 12062 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ |
|
- | 12063 | { Bad_Opcode }, |
|
- | 12064 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12065 | }, |
|
- | 12066 | { |
|
- | 12067 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ |
|
- | 12068 | { Bad_Opcode }, |
|
- | 12069 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12070 | }, |
|
- | 12071 | { |
|
- | 12072 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ |
|
- | 12073 | { Bad_Opcode }, |
|
- | 12074 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12075 | }, |
|
- | 12076 | { |
|
- | 12077 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ |
|
- | 12078 | { Bad_Opcode }, |
|
- | 12079 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12080 | }, |
|
- | 12081 | { |
|
- | 12082 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ |
|
- | 12083 | { Bad_Opcode }, |
|
- | 12084 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12085 | }, |
|
- | 12086 | { |
|
- | 12087 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ |
|
- | 12088 | { Bad_Opcode }, |
|
- | 12089 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12090 | }, |
|
- | 12091 | { |
|
- | 12092 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ |
|
- | 12093 | { Bad_Opcode }, |
|
- | 12094 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12095 | }, |
|
- | 12096 | { |
|
- | 12097 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ |
|
- | 12098 | { Bad_Opcode }, |
|
- | 12099 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12100 | }, |
|
- | 12101 | { |
|
- | 12102 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ |
|
- | 12103 | { Bad_Opcode }, |
|
- | 12104 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12105 | }, |
|
- | 12106 | { |
|
- | 12107 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ |
|
- | 12108 | { Bad_Opcode }, |
|
- | 12109 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12110 | }, |
|
- | 12111 | { |
|
- | 12112 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ |
|
- | 12113 | { Bad_Opcode }, |
|
- | 12114 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12115 | }, |
|
- | 12116 | { |
|
- | 12117 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ |
|
- | 12118 | { Bad_Opcode }, |
|
- | 12119 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12120 | }, |
|
- | 12121 | { |
|
- | 12122 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ |
|
- | 12123 | { Bad_Opcode }, |
|
- | 12124 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12125 | }, |
|
- | 12126 | { |
|
- | 12127 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ |
|
- | 12128 | { Bad_Opcode }, |
|
- | 12129 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, |
|
- | 12130 | }, |
|
- | 12131 | { |
|
11359 | /* MOD_VEX_0F50 */ |
12132 | /* MOD_VEX_0F50 */ |
11360 | { Bad_Opcode }, |
12133 | { Bad_Opcode }, |
11361 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
12134 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
11362 | }, |
12135 | }, |
11363 | { |
12136 | { |
Line 11409... | Line 12182... | ||
11409 | /* MOD_VEX_0F73_REG_7 */ |
12182 | /* MOD_VEX_0F73_REG_7 */ |
11410 | { Bad_Opcode }, |
12183 | { Bad_Opcode }, |
11411 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
12184 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
11412 | }, |
12185 | }, |
11413 | { |
12186 | { |
- | 12187 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ |
|
- | 12188 | { "kmovw", { Ew, MaskG }, 0 }, |
|
- | 12189 | { Bad_Opcode }, |
|
- | 12190 | }, |
|
- | 12191 | { |
|
- | 12192 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ |
|
- | 12193 | { "kmovq", { Eq, MaskG }, 0 }, |
|
- | 12194 | { Bad_Opcode }, |
|
- | 12195 | }, |
|
- | 12196 | { |
|
- | 12197 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ |
|
- | 12198 | { "kmovb", { Eb, MaskG }, 0 }, |
|
- | 12199 | { Bad_Opcode }, |
|
- | 12200 | }, |
|
- | 12201 | { |
|
- | 12202 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ |
|
- | 12203 | { "kmovd", { Ed, MaskG }, 0 }, |
|
- | 12204 | { Bad_Opcode }, |
|
- | 12205 | }, |
|
- | 12206 | { |
|
- | 12207 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ |
|
- | 12208 | { Bad_Opcode }, |
|
- | 12209 | { "kmovw", { MaskG, Rdq }, 0 }, |
|
- | 12210 | }, |
|
- | 12211 | { |
|
- | 12212 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ |
|
- | 12213 | { Bad_Opcode }, |
|
- | 12214 | { "kmovb", { MaskG, Rdq }, 0 }, |
|
- | 12215 | }, |
|
- | 12216 | { |
|
- | 12217 | /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ |
|
- | 12218 | { Bad_Opcode }, |
|
- | 12219 | { "kmovd", { MaskG, Rdq }, 0 }, |
|
- | 12220 | }, |
|
- | 12221 | { |
|
- | 12222 | /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ |
|
- | 12223 | { Bad_Opcode }, |
|
- | 12224 | { "kmovq", { MaskG, Rdq }, 0 }, |
|
- | 12225 | }, |
|
- | 12226 | { |
|
- | 12227 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ |
|
- | 12228 | { Bad_Opcode }, |
|
- | 12229 | { "kmovw", { Gdq, MaskR }, 0 }, |
|
- | 12230 | }, |
|
- | 12231 | { |
|
- | 12232 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ |
|
- | 12233 | { Bad_Opcode }, |
|
- | 12234 | { "kmovb", { Gdq, MaskR }, 0 }, |
|
- | 12235 | }, |
|
- | 12236 | { |
|
- | 12237 | /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ |
|
- | 12238 | { Bad_Opcode }, |
|
- | 12239 | { "kmovd", { Gdq, MaskR }, 0 }, |
|
- | 12240 | }, |
|
- | 12241 | { |
|
- | 12242 | /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ |
|
- | 12243 | { Bad_Opcode }, |
|
- | 12244 | { "kmovq", { Gdq, MaskR }, 0 }, |
|
- | 12245 | }, |
|
- | 12246 | { |
|
- | 12247 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ |
|
- | 12248 | { Bad_Opcode }, |
|
- | 12249 | { "kortestw", { MaskG, MaskR }, 0 }, |
|
- | 12250 | }, |
|
- | 12251 | { |
|
- | 12252 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ |
|
- | 12253 | { Bad_Opcode }, |
|
- | 12254 | { "kortestq", { MaskG, MaskR }, 0 }, |
|
- | 12255 | }, |
|
- | 12256 | { |
|
- | 12257 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ |
|
- | 12258 | { Bad_Opcode }, |
|
- | 12259 | { "kortestb", { MaskG, MaskR }, 0 }, |
|
- | 12260 | }, |
|
- | 12261 | { |
|
- | 12262 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ |
|
- | 12263 | { Bad_Opcode }, |
|
- | 12264 | { "kortestd", { MaskG, MaskR }, 0 }, |
|
- | 12265 | }, |
|
- | 12266 | { |
|
- | 12267 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ |
|
- | 12268 | { Bad_Opcode }, |
|
- | 12269 | { "ktestw", { MaskG, MaskR }, 0 }, |
|
- | 12270 | }, |
|
- | 12271 | { |
|
- | 12272 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ |
|
- | 12273 | { Bad_Opcode }, |
|
- | 12274 | { "ktestq", { MaskG, MaskR }, 0 }, |
|
- | 12275 | }, |
|
- | 12276 | { |
|
- | 12277 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ |
|
- | 12278 | { Bad_Opcode }, |
|
- | 12279 | { "ktestb", { MaskG, MaskR }, 0 }, |
|
- | 12280 | }, |
|
- | 12281 | { |
|
- | 12282 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ |
|
- | 12283 | { Bad_Opcode }, |
|
- | 12284 | { "ktestd", { MaskG, MaskR }, 0 }, |
|
- | 12285 | }, |
|
- | 12286 | { |
|
11414 | /* MOD_VEX_0FAE_REG_2 */ |
12287 | /* MOD_VEX_0FAE_REG_2 */ |
11415 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, |
12288 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, |
11416 | }, |
12289 | }, |
11417 | { |
12290 | { |
11418 | /* MOD_VEX_0FAE_REG_3 */ |
12291 | /* MOD_VEX_0FAE_REG_3 */ |
Line 11459... | Line 12332... | ||
11459 | /* MOD_VEX_0F385A_PREFIX_2 */ |
12332 | /* MOD_VEX_0F385A_PREFIX_2 */ |
11460 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, |
12333 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, |
11461 | }, |
12334 | }, |
11462 | { |
12335 | { |
11463 | /* MOD_VEX_0F388C_PREFIX_2 */ |
12336 | /* MOD_VEX_0F388C_PREFIX_2 */ |
11464 | { "vpmaskmov%LW", { XM, Vex, Mx } }, |
12337 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
11465 | }, |
12338 | }, |
11466 | { |
12339 | { |
11467 | /* MOD_VEX_0F388E_PREFIX_2 */ |
12340 | /* MOD_VEX_0F388E_PREFIX_2 */ |
11468 | { "vpmaskmov%LW", { Mx, Vex, XM } }, |
12341 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
- | 12342 | }, |
|
- | 12343 | { |
|
- | 12344 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ |
|
- | 12345 | { Bad_Opcode }, |
|
- | 12346 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12347 | }, |
|
- | 12348 | { |
|
- | 12349 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ |
|
- | 12350 | { Bad_Opcode }, |
|
- | 12351 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12352 | }, |
|
- | 12353 | { |
|
- | 12354 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ |
|
- | 12355 | { Bad_Opcode }, |
|
- | 12356 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12357 | }, |
|
- | 12358 | { |
|
- | 12359 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ |
|
- | 12360 | { Bad_Opcode }, |
|
- | 12361 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12362 | }, |
|
- | 12363 | { |
|
- | 12364 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ |
|
- | 12365 | { Bad_Opcode }, |
|
- | 12366 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12367 | }, |
|
- | 12368 | { |
|
- | 12369 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ |
|
- | 12370 | { Bad_Opcode }, |
|
- | 12371 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12372 | }, |
|
- | 12373 | { |
|
- | 12374 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ |
|
- | 12375 | { Bad_Opcode }, |
|
- | 12376 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, |
|
- | 12377 | }, |
|
- | 12378 | { |
|
- | 12379 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ |
|
- | 12380 | { Bad_Opcode }, |
|
- | 12381 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, |
|
11469 | }, |
12382 | }, |
11470 | #define NEED_MOD_TABLE |
12383 | #define NEED_MOD_TABLE |
11471 | #include "i386-dis-evex.h" |
12384 | #include "i386-dis-evex.h" |
11472 | #undef NEED_MOD_TABLE |
12385 | #undef NEED_MOD_TABLE |
11473 | }; |
12386 | }; |
Line 11474... | Line 12387... | ||
11474 | 12387 | ||
11475 | static const struct dis386 rm_table[][8] = { |
12388 | static const struct dis386 rm_table[][8] = { |
11476 | { |
12389 | { |
11477 | /* RM_C6_REG_7 */ |
12390 | /* RM_C6_REG_7 */ |
11478 | { "xabort", { Skip_MODRM, Ib } }, |
12391 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
11479 | }, |
12392 | }, |
11480 | { |
12393 | { |
11481 | /* RM_C7_REG_7 */ |
12394 | /* RM_C7_REG_7 */ |
11482 | { "xbeginT", { Skip_MODRM, Jv } }, |
12395 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
11483 | }, |
12396 | }, |
11484 | { |
12397 | { |
11485 | /* RM_0F01_REG_0 */ |
12398 | /* RM_0F01_REG_0 */ |
11486 | { Bad_Opcode }, |
12399 | { Bad_Opcode }, |
11487 | { "vmcall", { Skip_MODRM } }, |
12400 | { "vmcall", { Skip_MODRM }, 0 }, |
11488 | { "vmlaunch", { Skip_MODRM } }, |
12401 | { "vmlaunch", { Skip_MODRM }, 0 }, |
11489 | { "vmresume", { Skip_MODRM } }, |
12402 | { "vmresume", { Skip_MODRM }, 0 }, |
11490 | { "vmxoff", { Skip_MODRM } }, |
12403 | { "vmxoff", { Skip_MODRM }, 0 }, |
11491 | }, |
12404 | }, |
11492 | { |
12405 | { |
11493 | /* RM_0F01_REG_1 */ |
12406 | /* RM_0F01_REG_1 */ |
11494 | { "monitor", { { OP_Monitor, 0 } } }, |
12407 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
11495 | { "mwait", { { OP_Mwait, 0 } } }, |
12408 | { "mwait", { { OP_Mwait, 0 } }, 0 }, |
11496 | { "clac", { Skip_MODRM } }, |
12409 | { "clac", { Skip_MODRM }, 0 }, |
- | 12410 | { "stac", { Skip_MODRM }, 0 }, |
|
- | 12411 | { Bad_Opcode }, |
|
- | 12412 | { Bad_Opcode }, |
|
- | 12413 | { Bad_Opcode }, |
|
11497 | { "stac", { Skip_MODRM } }, |
12414 | { "encls", { Skip_MODRM }, 0 }, |
11498 | }, |
12415 | }, |
11499 | { |
12416 | { |
11500 | /* RM_0F01_REG_2 */ |
12417 | /* RM_0F01_REG_2 */ |
11501 | { "xgetbv", { Skip_MODRM } }, |
12418 | { "xgetbv", { Skip_MODRM }, 0 }, |
11502 | { "xsetbv", { Skip_MODRM } }, |
12419 | { "xsetbv", { Skip_MODRM }, 0 }, |
11503 | { Bad_Opcode }, |
12420 | { Bad_Opcode }, |
11504 | { Bad_Opcode }, |
12421 | { Bad_Opcode }, |
11505 | { "vmfunc", { Skip_MODRM } }, |
12422 | { "vmfunc", { Skip_MODRM }, 0 }, |
11506 | { "xend", { Skip_MODRM } }, |
12423 | { "xend", { Skip_MODRM }, 0 }, |
11507 | { "xtest", { Skip_MODRM } }, |
12424 | { "xtest", { Skip_MODRM }, 0 }, |
11508 | { Bad_Opcode }, |
12425 | { "enclu", { Skip_MODRM }, 0 }, |
11509 | }, |
12426 | }, |
11510 | { |
12427 | { |
11511 | /* RM_0F01_REG_3 */ |
12428 | /* RM_0F01_REG_3 */ |
11512 | { "vmrun", { Skip_MODRM } }, |
12429 | { "vmrun", { Skip_MODRM }, 0 }, |
11513 | { "vmmcall", { Skip_MODRM } }, |
12430 | { "vmmcall", { Skip_MODRM }, 0 }, |
11514 | { "vmload", { Skip_MODRM } }, |
12431 | { "vmload", { Skip_MODRM }, 0 }, |
11515 | { "vmsave", { Skip_MODRM } }, |
12432 | { "vmsave", { Skip_MODRM }, 0 }, |
11516 | { "stgi", { Skip_MODRM } }, |
12433 | { "stgi", { Skip_MODRM }, 0 }, |
11517 | { "clgi", { Skip_MODRM } }, |
12434 | { "clgi", { Skip_MODRM }, 0 }, |
11518 | { "skinit", { Skip_MODRM } }, |
12435 | { "skinit", { Skip_MODRM }, 0 }, |
- | 12436 | { "invlpga", { Skip_MODRM }, 0 }, |
|
- | 12437 | }, |
|
- | 12438 | { |
|
- | 12439 | /* RM_0F01_REG_5 */ |
|
- | 12440 | { Bad_Opcode }, |
|
- | 12441 | { Bad_Opcode }, |
|
- | 12442 | { Bad_Opcode }, |
|
- | 12443 | { Bad_Opcode }, |
|
- | 12444 | { Bad_Opcode }, |
|
- | 12445 | { Bad_Opcode }, |
|
- | 12446 | { "rdpkru", { Skip_MODRM }, 0 }, |
|
11519 | { "invlpga", { Skip_MODRM } }, |
12447 | { "wrpkru", { Skip_MODRM }, 0 }, |
11520 | }, |
12448 | }, |
11521 | { |
12449 | { |
11522 | /* RM_0F01_REG_7 */ |
12450 | /* RM_0F01_REG_7 */ |
11523 | { "swapgs", { Skip_MODRM } }, |
12451 | { "swapgs", { Skip_MODRM }, 0 }, |
- | 12452 | { "rdtscp", { Skip_MODRM }, 0 }, |
|
- | 12453 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
|
- | 12454 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, |
|
11524 | { "rdtscp", { Skip_MODRM } }, |
12455 | { "clzero", { Skip_MODRM }, 0 }, |
11525 | }, |
12456 | }, |
11526 | { |
12457 | { |
11527 | /* RM_0FAE_REG_5 */ |
12458 | /* RM_0FAE_REG_5 */ |
11528 | { "lfence", { Skip_MODRM } }, |
12459 | { "lfence", { Skip_MODRM }, 0 }, |
11529 | }, |
12460 | }, |
11530 | { |
12461 | { |
11531 | /* RM_0FAE_REG_6 */ |
12462 | /* RM_0FAE_REG_6 */ |
11532 | { "mfence", { Skip_MODRM } }, |
12463 | { "mfence", { Skip_MODRM }, 0 }, |
11533 | }, |
12464 | }, |
11534 | { |
12465 | { |
11535 | /* RM_0FAE_REG_7 */ |
12466 | /* RM_0FAE_REG_7 */ |
11536 | { "sfence", { Skip_MODRM } }, |
12467 | { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) }, |
11537 | }, |
12468 | }, |
Line 11538... | Line 12469... | ||
11538 | }; |
12469 | }; |
Line 11539... | Line 12470... | ||
11539 | 12470 | ||
11540 | #define INTERNAL_DISASSEMBLER_ERROR _(" |
12471 | #define INTERNAL_DISASSEMBLER_ERROR _(" |
11541 | - | ||
11542 | /* We use the high bit to indicate different name for the same |
- | |
11543 | prefix. */ |
- | |
11544 | #define ADDR16_PREFIX (0x67 | 0x100) |
- | |
11545 | #define ADDR32_PREFIX (0x67 | 0x200) |
12472 | |
11546 | #define DATA16_PREFIX (0x66 | 0x100) |
12473 | /* We use the high bit to indicate different name for the same |
11547 | #define DATA32_PREFIX (0x66 | 0x200) |
12474 | prefix. */ |
11548 | #define REP_PREFIX (0xf3 | 0x100) |
12475 | #define REP_PREFIX (0xf3 | 0x100) |
Line 11564... | Line 12491... | ||
11564 | last_repnz_prefix = -1; |
12491 | last_repnz_prefix = -1; |
11565 | last_data_prefix = -1; |
12492 | last_data_prefix = -1; |
11566 | last_addr_prefix = -1; |
12493 | last_addr_prefix = -1; |
11567 | last_rex_prefix = -1; |
12494 | last_rex_prefix = -1; |
11568 | last_seg_prefix = -1; |
12495 | last_seg_prefix = -1; |
- | 12496 | fwait_prefix = -1; |
|
- | 12497 | active_seg_prefix = 0; |
|
11569 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12498 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11570 | all_prefixes[i] = 0; |
12499 | all_prefixes[i] = 0; |
11571 | i = 0; |
12500 | i = 0; |
11572 | length = 0; |
12501 | length = 0; |
11573 | /* The maximum instruction length is 15bytes. */ |
12502 | /* The maximum instruction length is 15bytes. */ |
Line 11613... | Line 12542... | ||
11613 | last_lock_prefix = i; |
12542 | last_lock_prefix = i; |
11614 | break; |
12543 | break; |
11615 | case 0x2e: |
12544 | case 0x2e: |
11616 | prefixes |= PREFIX_CS; |
12545 | prefixes |= PREFIX_CS; |
11617 | last_seg_prefix = i; |
12546 | last_seg_prefix = i; |
- | 12547 | active_seg_prefix = PREFIX_CS; |
|
11618 | break; |
12548 | break; |
11619 | case 0x36: |
12549 | case 0x36: |
11620 | prefixes |= PREFIX_SS; |
12550 | prefixes |= PREFIX_SS; |
11621 | last_seg_prefix = i; |
12551 | last_seg_prefix = i; |
- | 12552 | active_seg_prefix = PREFIX_SS; |
|
11622 | break; |
12553 | break; |
11623 | case 0x3e: |
12554 | case 0x3e: |
11624 | prefixes |= PREFIX_DS; |
12555 | prefixes |= PREFIX_DS; |
11625 | last_seg_prefix = i; |
12556 | last_seg_prefix = i; |
- | 12557 | active_seg_prefix = PREFIX_DS; |
|
11626 | break; |
12558 | break; |
11627 | case 0x26: |
12559 | case 0x26: |
11628 | prefixes |= PREFIX_ES; |
12560 | prefixes |= PREFIX_ES; |
11629 | last_seg_prefix = i; |
12561 | last_seg_prefix = i; |
- | 12562 | active_seg_prefix = PREFIX_ES; |
|
11630 | break; |
12563 | break; |
11631 | case 0x64: |
12564 | case 0x64: |
11632 | prefixes |= PREFIX_FS; |
12565 | prefixes |= PREFIX_FS; |
11633 | last_seg_prefix = i; |
12566 | last_seg_prefix = i; |
- | 12567 | active_seg_prefix = PREFIX_FS; |
|
11634 | break; |
12568 | break; |
11635 | case 0x65: |
12569 | case 0x65: |
11636 | prefixes |= PREFIX_GS; |
12570 | prefixes |= PREFIX_GS; |
11637 | last_seg_prefix = i; |
12571 | last_seg_prefix = i; |
- | 12572 | active_seg_prefix = PREFIX_GS; |
|
11638 | break; |
12573 | break; |
11639 | case 0x66: |
12574 | case 0x66: |
11640 | prefixes |= PREFIX_DATA; |
12575 | prefixes |= PREFIX_DATA; |
11641 | last_data_prefix = i; |
12576 | last_data_prefix = i; |
11642 | break; |
12577 | break; |
Line 11646... | Line 12581... | ||
11646 | break; |
12581 | break; |
11647 | case FWAIT_OPCODE: |
12582 | case FWAIT_OPCODE: |
11648 | /* fwait is really an instruction. If there are prefixes |
12583 | /* fwait is really an instruction. If there are prefixes |
11649 | before the fwait, they belong to the fwait, *not* to the |
12584 | before the fwait, they belong to the fwait, *not* to the |
11650 | following instruction. */ |
12585 | following instruction. */ |
- | 12586 | fwait_prefix = i; |
|
11651 | if (prefixes || rex) |
12587 | if (prefixes || rex) |
11652 | { |
12588 | { |
11653 | prefixes |= PREFIX_FWAIT; |
12589 | prefixes |= PREFIX_FWAIT; |
11654 | codep++; |
12590 | codep++; |
11655 | /* This ensures that the previous REX prefixes are noticed |
12591 | /* This ensures that the previous REX prefixes are noticed |
Line 11675... | Line 12611... | ||
11675 | length++; |
12611 | length++; |
11676 | } |
12612 | } |
11677 | return 0; |
12613 | return 0; |
11678 | } |
12614 | } |
Line 11679... | Line -... | ||
11679 | - | ||
11680 | static int |
- | |
11681 | seg_prefix (int pref) |
- | |
11682 | { |
- | |
11683 | switch (pref) |
- | |
11684 | { |
- | |
11685 | case 0x2e: |
- | |
11686 | return PREFIX_CS; |
- | |
11687 | case 0x36: |
- | |
11688 | return PREFIX_SS; |
- | |
11689 | case 0x3e: |
- | |
11690 | return PREFIX_DS; |
- | |
11691 | case 0x26: |
- | |
11692 | return PREFIX_ES; |
- | |
11693 | case 0x64: |
- | |
11694 | return PREFIX_FS; |
- | |
11695 | case 0x65: |
- | |
11696 | return PREFIX_GS; |
- | |
11697 | default: |
- | |
11698 | return 0; |
- | |
11699 | } |
- | |
11700 | } |
- | |
11701 | 12615 | ||
11702 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12616 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
Line 11703... | Line 12617... | ||
11703 | prefix byte. */ |
12617 | prefix byte. */ |
11704 | 12618 | ||
Line 11770... | Line 12684... | ||
11770 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
12684 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
11771 | else |
12685 | else |
11772 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
12686 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
11773 | case FWAIT_OPCODE: |
12687 | case FWAIT_OPCODE: |
11774 | return "fwait"; |
12688 | return "fwait"; |
11775 | case ADDR16_PREFIX: |
- | |
11776 | return "addr16"; |
- | |
11777 | case ADDR32_PREFIX: |
- | |
11778 | return "addr32"; |
- | |
11779 | case DATA16_PREFIX: |
- | |
11780 | return "data16"; |
- | |
11781 | case DATA32_PREFIX: |
- | |
11782 | return "data32"; |
- | |
11783 | case REP_PREFIX: |
12689 | case REP_PREFIX: |
11784 | return "rep"; |
12690 | return "rep"; |
11785 | case XACQUIRE_PREFIX: |
12691 | case XACQUIRE_PREFIX: |
11786 | return "xacquire"; |
12692 | return "xacquire"; |
11787 | case XRELEASE_PREFIX: |
12693 | case XRELEASE_PREFIX: |
Line 11814... | Line 12720... | ||
11814 | static char open_char; |
12720 | static char open_char; |
11815 | static char close_char; |
12721 | static char close_char; |
11816 | static char separator_char; |
12722 | static char separator_char; |
11817 | static char scale_char; |
12723 | static char scale_char; |
Line -... | Line 12724... | ||
- | 12724 | ||
- | 12725 | enum x86_64_isa |
|
- | 12726 | { |
|
- | 12727 | amd64 = 0, |
|
- | 12728 | intel64 |
|
- | 12729 | }; |
|
- | 12730 | ||
- | 12731 | static enum x86_64_isa isa64; |
|
11818 | 12732 | ||
11819 | /* Here for backwards compatibility. When gdb stops using |
12733 | /* Here for backwards compatibility. When gdb stops using |
11820 | print_insn_i386_att and print_insn_i386_intel these functions can |
12734 | print_insn_i386_att and print_insn_i386_intel these functions can |
11821 | disappear, and print_insn_i386 be merged into print_insn. */ |
12735 | disappear, and print_insn_i386 be merged into print_insn. */ |
11822 | int |
12736 | int |
Line 11863... | Line 12777... | ||
11863 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); |
12777 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); |
11864 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); |
12778 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); |
11865 | fprintf (stream, _(" data32 Assume 32bit data size\n")); |
12779 | fprintf (stream, _(" data32 Assume 32bit data size\n")); |
11866 | fprintf (stream, _(" data16 Assume 16bit data size\n")); |
12780 | fprintf (stream, _(" data16 Assume 16bit data size\n")); |
11867 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); |
12781 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); |
- | 12782 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
|
- | 12783 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); |
|
11868 | } |
12784 | } |
Line 11869... | Line 12785... | ||
11869 | 12785 | ||
11870 | /* Bad opcode. */ |
12786 | /* Bad opcode. */ |
Line 11871... | Line 12787... | ||
11871 | static const struct dis386 bad_opcode = { "(bad)", { XX } }; |
12787 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
Line 11872... | Line 12788... | ||
11872 | 12788 | ||
11873 | /* Get a pointer to struct dis386 with a valid name. */ |
12789 | /* Get a pointer to struct dis386 with a valid name. */ |
Line 11918... | Line 12834... | ||
11918 | break; |
12834 | break; |
11919 | } |
12835 | } |
11920 | } |
12836 | } |
11921 | else |
12837 | else |
11922 | { |
12838 | { |
- | 12839 | int last_prefix = -1; |
|
- | 12840 | int prefix = 0; |
|
11923 | vindex = 0; |
12841 | vindex = 0; |
- | 12842 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
|
11924 | used_prefixes |= (prefixes & PREFIX_REPZ); |
12843 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the |
- | 12844 | last one wins. */ |
|
11925 | if (prefixes & PREFIX_REPZ) |
12845 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) |
- | 12846 | { |
|
- | 12847 | if (last_repz_prefix > last_repnz_prefix) |
|
11926 | { |
12848 | { |
11927 | vindex = 1; |
12849 | vindex = 1; |
- | 12850 | prefix = PREFIX_REPZ; |
|
11928 | all_prefixes[last_repz_prefix] = 0; |
12851 | last_prefix = last_repz_prefix; |
11929 | } |
12852 | } |
11930 | else |
12853 | else |
11931 | { |
12854 | { |
11932 | /* We should check PREFIX_REPNZ and PREFIX_REPZ before |
- | |
11933 | PREFIX_DATA. */ |
- | |
11934 | used_prefixes |= (prefixes & PREFIX_REPNZ); |
- | |
11935 | if (prefixes & PREFIX_REPNZ) |
- | |
11936 | { |
- | |
11937 | vindex = 3; |
12855 | vindex = 3; |
- | 12856 | prefix = PREFIX_REPNZ; |
|
11938 | all_prefixes[last_repnz_prefix] = 0; |
12857 | last_prefix = last_repnz_prefix; |
11939 | } |
12858 | } |
- | 12859 | ||
- | 12860 | /* Check if prefix should be ignored. */ |
|
- | 12861 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement |
|
- | 12862 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) |
|
- | 12863 | & prefix) != 0) |
|
- | 12864 | vindex = 0; |
|
11940 | else |
12865 | } |
11941 | { |
12866 | |
11942 | used_prefixes |= (prefixes & PREFIX_DATA); |
12867 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) |
11943 | if (prefixes & PREFIX_DATA) |
- | |
11944 | { |
12868 | { |
11945 | vindex = 2; |
12869 | vindex = 2; |
- | 12870 | prefix = PREFIX_DATA; |
|
11946 | all_prefixes[last_data_prefix] = 0; |
12871 | last_prefix = last_data_prefix; |
11947 | } |
- | |
11948 | } |
12872 | } |
- | 12873 | ||
- | 12874 | if (vindex != 0) |
|
- | 12875 | { |
|
- | 12876 | used_prefixes |= prefix; |
|
- | 12877 | all_prefixes[last_prefix] = 0; |
|
11949 | } |
12878 | } |
11950 | } |
12879 | } |
11951 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
12880 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
11952 | break; |
12881 | break; |
Line 11958... | Line 12887... | ||
11958 | 12887 | ||
11959 | case USE_3BYTE_TABLE: |
12888 | case USE_3BYTE_TABLE: |
11960 | FETCH_DATA (info, codep + 2); |
12889 | FETCH_DATA (info, codep + 2); |
11961 | vindex = *codep++; |
12890 | vindex = *codep++; |
- | 12891 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; |
|
11962 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; |
12892 | end_codep = codep; |
11963 | modrm.mod = (*codep >> 6) & 3; |
12893 | modrm.mod = (*codep >> 6) & 3; |
11964 | modrm.reg = (*codep >> 3) & 7; |
12894 | modrm.reg = (*codep >> 3) & 7; |
11965 | modrm.rm = *codep & 7; |
12895 | modrm.rm = *codep & 7; |
Line 12040... | Line 12970... | ||
12040 | need_vex_reg = 1; |
12970 | need_vex_reg = 1; |
12041 | codep++; |
12971 | codep++; |
12042 | vindex = *codep++; |
12972 | vindex = *codep++; |
12043 | dp = &xop_table[vex_table_index][vindex]; |
12973 | dp = &xop_table[vex_table_index][vindex]; |
Line -... | Line 12974... | ||
- | 12974 | ||
12044 | 12975 | end_codep = codep; |
|
12045 | FETCH_DATA (info, codep + 1); |
12976 | FETCH_DATA (info, codep + 1); |
12046 | modrm.mod = (*codep >> 6) & 3; |
12977 | modrm.mod = (*codep >> 6) & 3; |
12047 | modrm.reg = (*codep >> 3) & 7; |
12978 | modrm.reg = (*codep >> 3) & 7; |
12048 | modrm.rm = *codep & 7; |
12979 | modrm.rm = *codep & 7; |
Line 12101... | Line 13032... | ||
12101 | need_vex = 1; |
13032 | need_vex = 1; |
12102 | need_vex_reg = 1; |
13033 | need_vex_reg = 1; |
12103 | codep++; |
13034 | codep++; |
12104 | vindex = *codep++; |
13035 | vindex = *codep++; |
12105 | dp = &vex_table[vex_table_index][vindex]; |
13036 | dp = &vex_table[vex_table_index][vindex]; |
- | 13037 | end_codep = codep; |
|
12106 | /* There is no MODRM byte for VEX [82|77]. */ |
13038 | /* There is no MODRM byte for VEX [82|77]. */ |
12107 | if (vindex != 0x77 && vindex != 0x82) |
13039 | if (vindex != 0x77 && vindex != 0x82) |
12108 | { |
13040 | { |
12109 | FETCH_DATA (info, codep + 1); |
13041 | FETCH_DATA (info, codep + 1); |
12110 | modrm.mod = (*codep >> 6) & 3; |
13042 | modrm.mod = (*codep >> 6) & 3; |
Line 12149... | Line 13081... | ||
12149 | need_vex = 1; |
13081 | need_vex = 1; |
12150 | need_vex_reg = 1; |
13082 | need_vex_reg = 1; |
12151 | codep++; |
13083 | codep++; |
12152 | vindex = *codep++; |
13084 | vindex = *codep++; |
12153 | dp = &vex_table[dp->op[1].bytemode][vindex]; |
13085 | dp = &vex_table[dp->op[1].bytemode][vindex]; |
- | 13086 | end_codep = codep; |
|
12154 | /* There is no MODRM byte for VEX [82|77]. */ |
13087 | /* There is no MODRM byte for VEX [82|77]. */ |
12155 | if (vindex != 0x77 && vindex != 0x82) |
13088 | if (vindex != 0x77 && vindex != 0x82) |
12156 | { |
13089 | { |
12157 | FETCH_DATA (info, codep + 1); |
13090 | FETCH_DATA (info, codep + 1); |
12158 | modrm.mod = (*codep >> 6) & 3; |
13091 | modrm.mod = (*codep >> 6) & 3; |
Line 12243... | Line 13176... | ||
12243 | need_vex = 1; |
13176 | need_vex = 1; |
12244 | need_vex_reg = 1; |
13177 | need_vex_reg = 1; |
12245 | codep++; |
13178 | codep++; |
12246 | vindex = *codep++; |
13179 | vindex = *codep++; |
12247 | dp = &evex_table[vex_table_index][vindex]; |
13180 | dp = &evex_table[vex_table_index][vindex]; |
- | 13181 | end_codep = codep; |
|
12248 | FETCH_DATA (info, codep + 1); |
13182 | FETCH_DATA (info, codep + 1); |
12249 | modrm.mod = (*codep >> 6) & 3; |
13183 | modrm.mod = (*codep >> 6) & 3; |
12250 | modrm.reg = (*codep >> 3) & 7; |
13184 | modrm.reg = (*codep >> 3) & 7; |
12251 | modrm.rm = *codep & 7; |
13185 | modrm.rm = *codep & 7; |
Line 12307... | Line 13241... | ||
12307 | { |
13241 | { |
12308 | const struct dis386 *dp; |
13242 | const struct dis386 *dp; |
12309 | int i; |
13243 | int i; |
12310 | char *op_txt[MAX_OPERANDS]; |
13244 | char *op_txt[MAX_OPERANDS]; |
12311 | int needcomma; |
13245 | int needcomma; |
12312 | int sizeflag; |
13246 | int sizeflag, orig_sizeflag; |
12313 | const char *p; |
13247 | const char *p; |
12314 | struct dis_private priv; |
13248 | struct dis_private priv; |
12315 | int prefix_length; |
13249 | int prefix_length; |
12316 | int default_prefixes; |
- | |
Line 12317... | Line 13250... | ||
12317 | 13250 | ||
12318 | priv.orig_sizeflag = AFLAG | DFLAG; |
13251 | priv.orig_sizeflag = AFLAG | DFLAG; |
12319 | if ((info->mach & bfd_mach_i386_i386) != 0) |
13252 | if ((info->mach & bfd_mach_i386_i386) != 0) |
12320 | address_mode = mode_32bit; |
13253 | address_mode = mode_32bit; |
Line 12329... | Line 13262... | ||
12329 | if (intel_syntax == (char) -1) |
13262 | if (intel_syntax == (char) -1) |
12330 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; |
13263 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; |
Line 12331... | Line 13264... | ||
12331 | 13264 | ||
12332 | for (p = info->disassembler_options; p != NULL; ) |
13265 | for (p = info->disassembler_options; p != NULL; ) |
12333 | { |
13266 | { |
- | 13267 | if (CONST_STRNEQ (p, "amd64")) |
|
- | 13268 | isa64 = amd64; |
|
- | 13269 | else if (CONST_STRNEQ (p, "intel64")) |
|
- | 13270 | isa64 = intel64; |
|
12334 | if (CONST_STRNEQ (p, "x86-64")) |
13271 | else if (CONST_STRNEQ (p, "x86-64")) |
12335 | { |
13272 | { |
12336 | address_mode = mode_64bit; |
13273 | address_mode = mode_64bit; |
12337 | priv.orig_sizeflag = AFLAG | DFLAG; |
13274 | priv.orig_sizeflag = AFLAG | DFLAG; |
12338 | } |
13275 | } |
Line 12457... | Line 13394... | ||
12457 | the_info = info; |
13394 | the_info = info; |
12458 | start_pc = pc; |
13395 | start_pc = pc; |
12459 | start_codep = priv.the_buffer; |
13396 | start_codep = priv.the_buffer; |
12460 | codep = priv.the_buffer; |
13397 | codep = priv.the_buffer; |
Line 12461... | Line 13398... | ||
12461 | 13398 | ||
12462 | if (setjmp (priv.bailout) != 0) |
13399 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
12463 | { |
13400 | { |
Line 12464... | Line 13401... | ||
12464 | const char *name; |
13401 | const char *name; |
12465 | 13402 | ||
Line 12505... | Line 13442... | ||
12505 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); |
13442 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); |
Line 12506... | Line 13443... | ||
12506 | 13443 | ||
12507 | if (((prefixes & PREFIX_FWAIT) |
13444 | if (((prefixes & PREFIX_FWAIT) |
12508 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
13445 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
- | 13446 | { |
|
- | 13447 | /* Handle prefixes before fwait. */ |
|
- | 13448 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
|
- | 13449 | i++) |
|
- | 13450 | (*info->fprintf_func) (info->stream, "%s ", |
|
12509 | { |
13451 | prefix_name (all_prefixes[i], sizeflag)); |
12510 | (*info->fprintf_func) (info->stream, "fwait"); |
13452 | (*info->fprintf_func) (info->stream, "fwait"); |
12511 | return 1; |
13453 | return i + 1; |
Line 12512... | Line 13454... | ||
12512 | } |
13454 | } |
12513 | 13455 | ||
12514 | if (*codep == 0x0f) |
13456 | if (*codep == 0x0f) |
- | 13457 | { |
|
- | 13458 | unsigned char threebyte; |
|
12515 | { |
13459 | |
12516 | unsigned char threebyte; |
13460 | codep++; |
12517 | FETCH_DATA (info, codep + 2); |
13461 | FETCH_DATA (info, codep + 1); |
12518 | threebyte = *++codep; |
13462 | threebyte = *codep; |
12519 | dp = &dis386_twobyte[threebyte]; |
13463 | dp = &dis386_twobyte[threebyte]; |
12520 | need_modrm = twobyte_has_modrm[*codep]; |
13464 | need_modrm = twobyte_has_modrm[*codep]; |
12521 | codep++; |
13465 | codep++; |
Line 12525... | Line 13469... | ||
12525 | dp = &dis386[*codep]; |
13469 | dp = &dis386[*codep]; |
12526 | need_modrm = onebyte_has_modrm[*codep]; |
13470 | need_modrm = onebyte_has_modrm[*codep]; |
12527 | codep++; |
13471 | codep++; |
12528 | } |
13472 | } |
Line 12529... | Line 13473... | ||
12529 | 13473 | ||
12530 | if ((prefixes & PREFIX_REPZ)) |
13474 | /* Save sizeflag for printing the extra prefixes later before updating |
12531 | used_prefixes |= PREFIX_REPZ; |
- | |
12532 | if ((prefixes & PREFIX_REPNZ)) |
13475 | it for mnemonic and operand processing. The prefix names depend |
12533 | used_prefixes |= PREFIX_REPNZ; |
- | |
12534 | if ((prefixes & PREFIX_LOCK)) |
13476 | only on the address mode. */ |
12535 | used_prefixes |= PREFIX_LOCK; |
- | |
12536 | - | ||
12537 | default_prefixes = 0; |
13477 | orig_sizeflag = sizeflag; |
12538 | if (prefixes & PREFIX_ADDR) |
- | |
12539 | { |
13478 | if (prefixes & PREFIX_ADDR) |
12540 | sizeflag ^= AFLAG; |
- | |
12541 | if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) |
- | |
12542 | { |
- | |
12543 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
- | |
12544 | all_prefixes[last_addr_prefix] = ADDR32_PREFIX; |
- | |
12545 | else |
- | |
12546 | all_prefixes[last_addr_prefix] = ADDR16_PREFIX; |
- | |
12547 | default_prefixes |= PREFIX_ADDR; |
- | |
12548 | } |
- | |
12549 | } |
- | |
12550 | 13479 | sizeflag ^= AFLAG; |
|
12551 | if ((prefixes & PREFIX_DATA)) |
- | |
12552 | { |
13480 | if ((prefixes & PREFIX_DATA)) |
12553 | sizeflag ^= DFLAG; |
- | |
12554 | if (dp->op[2].bytemode == cond_jump_mode |
- | |
12555 | && dp->op[0].bytemode == v_mode |
- | |
12556 | && !intel_syntax) |
- | |
12557 | { |
- | |
12558 | if (sizeflag & DFLAG) |
- | |
12559 | all_prefixes[last_data_prefix] = DATA32_PREFIX; |
- | |
12560 | else |
- | |
12561 | all_prefixes[last_data_prefix] = DATA16_PREFIX; |
- | |
12562 | default_prefixes |= PREFIX_DATA; |
- | |
12563 | } |
- | |
12564 | else if (rex & REX_W) |
- | |
12565 | { |
- | |
12566 | /* REX_W will override PREFIX_DATA. */ |
- | |
12567 | default_prefixes |= PREFIX_DATA; |
- | |
12568 | } |
- | |
Line -... | Line 13481... | ||
- | 13481 | sizeflag ^= DFLAG; |
|
12569 | } |
13482 | |
12570 | 13483 | end_codep = codep; |
|
12571 | if (need_modrm) |
13484 | if (need_modrm) |
12572 | { |
13485 | { |
12573 | FETCH_DATA (info, codep + 1); |
13486 | FETCH_DATA (info, codep + 1); |
Line 12614... | Line 13527... | ||
12614 | } |
13527 | } |
12615 | } |
13528 | } |
12616 | } |
13529 | } |
12617 | } |
13530 | } |
Line 12618... | Line -... | ||
12618 | - | ||
12619 | /* See if any prefixes were not used. If so, print the first one |
- | |
12620 | separately. If we don't do this, we'll wind up printing an |
- | |
12621 | instruction stream which does not precisely correspond to the |
- | |
12622 | bytes we are disassembling. */ |
- | |
12623 | if ((prefixes & ~(used_prefixes | default_prefixes)) != 0) |
- | |
12624 | { |
- | |
12625 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
- | |
12626 | if (all_prefixes[i]) |
- | |
12627 | { |
- | |
12628 | const char *name; |
- | |
12629 | name = prefix_name (all_prefixes[i], priv.orig_sizeflag); |
- | |
12630 | if (name == NULL) |
- | |
12631 | name = INTERNAL_DISASSEMBLER_ERROR; |
- | |
12632 | (*info->fprintf_func) (info->stream, "%s", name); |
- | |
12633 | return 1; |
- | |
12634 | } |
- | |
12635 | } |
- | |
12636 | 13531 | ||
12637 | /* Check if the REX prefix is used. */ |
13532 | /* Check if the REX prefix is used. */ |
12638 | if (rex_ignored == 0 && (rex ^ rex_used) == 0) |
13533 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
Line 12639... | Line 13534... | ||
12639 | all_prefixes[last_rex_prefix] = 0; |
13534 | all_prefixes[last_rex_prefix] = 0; |
12640 | 13535 | ||
12641 | /* Check if the SEG prefix is used. */ |
13536 | /* Check if the SEG prefix is used. */ |
12642 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
- | |
12643 | | PREFIX_FS | PREFIX_GS)) != 0 |
13537 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12644 | && (used_prefixes |
13538 | | PREFIX_FS | PREFIX_GS)) != 0 |
Line 12645... | Line 13539... | ||
12645 | & seg_prefix (all_prefixes[last_seg_prefix])) != 0) |
13539 | && (used_prefixes & active_seg_prefix) != 0) |
12646 | all_prefixes[last_seg_prefix] = 0; |
13540 | all_prefixes[last_seg_prefix] = 0; |
12647 | 13541 | ||
Line 12653... | Line 13547... | ||
12653 | /* Check if the DATA prefix is used. */ |
13547 | /* Check if the DATA prefix is used. */ |
12654 | if ((prefixes & PREFIX_DATA) != 0 |
13548 | if ((prefixes & PREFIX_DATA) != 0 |
12655 | && (used_prefixes & PREFIX_DATA) != 0) |
13549 | && (used_prefixes & PREFIX_DATA) != 0) |
12656 | all_prefixes[last_data_prefix] = 0; |
13550 | all_prefixes[last_data_prefix] = 0; |
Line -... | Line 13551... | ||
- | 13551 | ||
12657 | 13552 | /* Print the extra prefixes. */ |
|
12658 | prefix_length = 0; |
13553 | prefix_length = 0; |
12659 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
13554 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12660 | if (all_prefixes[i]) |
13555 | if (all_prefixes[i]) |
12661 | { |
13556 | { |
12662 | const char *name; |
13557 | const char *name; |
12663 | name = prefix_name (all_prefixes[i], sizeflag); |
13558 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
12664 | if (name == NULL) |
13559 | if (name == NULL) |
12665 | abort (); |
13560 | abort (); |
12666 | prefix_length += strlen (name) + 1; |
13561 | prefix_length += strlen (name) + 1; |
12667 | (*info->fprintf_func) (info->stream, "%s ", name); |
13562 | (*info->fprintf_func) (info->stream, "%s ", name); |
Line -... | Line 13563... | ||
- | 13563 | } |
|
- | 13564 | ||
- | 13565 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
|
- | 13566 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be |
|
- | 13567 | used by putop and MMX/SSE operand and may be overriden by the |
|
- | 13568 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix |
|
- | 13569 | separately. */ |
|
- | 13570 | if (dp->prefix_requirement == PREFIX_OPCODE |
|
- | 13571 | && dp != &bad_opcode |
|
- | 13572 | && (((prefixes |
|
- | 13573 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 |
|
- | 13574 | && (used_prefixes |
|
- | 13575 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) |
|
- | 13576 | || ((((prefixes |
|
- | 13577 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) |
|
- | 13578 | == PREFIX_DATA) |
|
- | 13579 | && (used_prefixes & PREFIX_DATA) == 0)))) |
|
- | 13580 | { |
|
- | 13581 | (*info->fprintf_func) (info->stream, "(bad)"); |
|
- | 13582 | return end_codep - priv.the_buffer; |
|
12668 | } |
13583 | } |
12669 | 13584 | ||
12670 | /* Check maximum code length. */ |
13585 | /* Check maximum code length. */ |
12671 | if ((codep - start_codep) > MAX_CODE_LENGTH) |
13586 | if ((codep - start_codep) > MAX_CODE_LENGTH) |
12672 | { |
13587 | { |
Line 12687... | Line 13602... | ||
12687 | bfd_vma riprel; |
13602 | bfd_vma riprel; |
Line 12688... | Line 13603... | ||
12688 | 13603 | ||
12689 | for (i = 0; i < MAX_OPERANDS; ++i) |
13604 | for (i = 0; i < MAX_OPERANDS; ++i) |
Line -... | Line 13605... | ||
- | 13605 | op_txt[i] = op_out[i]; |
|
- | 13606 | ||
- | 13607 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
|
- | 13608 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) |
|
- | 13609 | { |
|
- | 13610 | op_txt[2] = op_out[3]; |
|
- | 13611 | op_txt[3] = op_out[2]; |
|
12690 | op_txt[i] = op_out[i]; |
13612 | } |
12691 | 13613 | ||
12692 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13614 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12693 | { |
13615 | { |
12694 | op_ad = op_index[i]; |
13616 | op_ad = op_index[i]; |
Line 12880... | Line 13802... | ||
12880 | }; |
13802 | }; |
Line 12881... | Line 13803... | ||
12881 | 13803 | ||
12882 | #define ST { OP_ST, 0 } |
13804 | #define ST { OP_ST, 0 } |
Line 12883... | Line 13805... | ||
12883 | #define STi { OP_STi, 0 } |
13805 | #define STi { OP_STi, 0 } |
12884 | 13806 | ||
12885 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
13807 | #define FGRPd9_2 NULL, { { NULL, 0 } }, 0 |
12886 | #define FGRPd9_4 NULL, { { NULL, 1 } } |
13808 | #define FGRPd9_4 NULL, { { NULL, 1 } }, 0 |
12887 | #define FGRPd9_5 NULL, { { NULL, 2 } } |
13809 | #define FGRPd9_5 NULL, { { NULL, 2 } }, 0 |
12888 | #define FGRPd9_6 NULL, { { NULL, 3 } } |
13810 | #define FGRPd9_6 NULL, { { NULL, 3 } }, 0 |
12889 | #define FGRPd9_7 NULL, { { NULL, 4 } } |
13811 | #define FGRPd9_7 NULL, { { NULL, 4 } }, 0 |
12890 | #define FGRPda_5 NULL, { { NULL, 5 } } |
13812 | #define FGRPda_5 NULL, { { NULL, 5 } }, 0 |
12891 | #define FGRPdb_4 NULL, { { NULL, 6 } } |
13813 | #define FGRPdb_4 NULL, { { NULL, 6 } }, 0 |
Line 12892... | Line 13814... | ||
12892 | #define FGRPde_3 NULL, { { NULL, 7 } } |
13814 | #define FGRPde_3 NULL, { { NULL, 7 } }, 0 |
12893 | #define FGRPdf_4 NULL, { { NULL, 8 } } |
13815 | #define FGRPdf_4 NULL, { { NULL, 8 } }, 0 |
12894 | 13816 | ||
12895 | static const struct dis386 float_reg[][8] = { |
13817 | static const struct dis386 float_reg[][8] = { |
12896 | /* d8 */ |
13818 | /* d8 */ |
12897 | { |
13819 | { |
12898 | { "fadd", { ST, STi } }, |
13820 | { "fadd", { ST, STi }, 0 }, |
12899 | { "fmul", { ST, STi } }, |
13821 | { "fmul", { ST, STi }, 0 }, |
12900 | { "fcom", { STi } }, |
13822 | { "fcom", { STi }, 0 }, |
12901 | { "fcomp", { STi } }, |
13823 | { "fcomp", { STi }, 0 }, |
12902 | { "fsub", { ST, STi } }, |
13824 | { "fsub", { ST, STi }, 0 }, |
12903 | { "fsubr", { ST, STi } }, |
13825 | { "fsubr", { ST, STi }, 0 }, |
12904 | { "fdiv", { ST, STi } }, |
13826 | { "fdiv", { ST, STi }, 0 }, |
12905 | { "fdivr", { ST, STi } }, |
13827 | { "fdivr", { ST, STi }, 0 }, |
12906 | }, |
13828 | }, |
12907 | /* d9 */ |
13829 | /* d9 */ |
12908 | { |
13830 | { |
12909 | { "fld", { STi } }, |
13831 | { "fld", { STi }, 0 }, |
12910 | { "fxch", { STi } }, |
13832 | { "fxch", { STi }, 0 }, |
12911 | { FGRPd9_2 }, |
13833 | { FGRPd9_2 }, |
12912 | { Bad_Opcode }, |
13834 | { Bad_Opcode }, |
12913 | { FGRPd9_4 }, |
13835 | { FGRPd9_4 }, |
12914 | { FGRPd9_5 }, |
13836 | { FGRPd9_5 }, |
12915 | { FGRPd9_6 }, |
13837 | { FGRPd9_6 }, |
12916 | { FGRPd9_7 }, |
13838 | { FGRPd9_7 }, |
12917 | }, |
13839 | }, |
12918 | /* da */ |
13840 | /* da */ |
12919 | { |
13841 | { |
12920 | { "fcmovb", { ST, STi } }, |
13842 | { "fcmovb", { ST, STi }, 0 }, |
12921 | { "fcmove", { ST, STi } }, |
13843 | { "fcmove", { ST, STi }, 0 }, |
12922 | { "fcmovbe",{ ST, STi } }, |
13844 | { "fcmovbe",{ ST, STi }, 0 }, |
12923 | { "fcmovu", { ST, STi } }, |
13845 | { "fcmovu", { ST, STi }, 0 }, |
12924 | { Bad_Opcode }, |
13846 | { Bad_Opcode }, |
12925 | { FGRPda_5 }, |
13847 | { FGRPda_5 }, |
12926 | { Bad_Opcode }, |
13848 | { Bad_Opcode }, |
12927 | { Bad_Opcode }, |
13849 | { Bad_Opcode }, |
12928 | }, |
13850 | }, |
12929 | /* db */ |
13851 | /* db */ |
12930 | { |
13852 | { |
12931 | { "fcmovnb",{ ST, STi } }, |
13853 | { "fcmovnb",{ ST, STi }, 0 }, |
12932 | { "fcmovne",{ ST, STi } }, |
13854 | { "fcmovne",{ ST, STi }, 0 }, |
12933 | { "fcmovnbe",{ ST, STi } }, |
13855 | { "fcmovnbe",{ ST, STi }, 0 }, |
12934 | { "fcmovnu",{ ST, STi } }, |
13856 | { "fcmovnu",{ ST, STi }, 0 }, |
12935 | { FGRPdb_4 }, |
13857 | { FGRPdb_4 }, |
12936 | { "fucomi", { ST, STi } }, |
13858 | { "fucomi", { ST, STi }, 0 }, |
12937 | { "fcomi", { ST, STi } }, |
13859 | { "fcomi", { ST, STi }, 0 }, |
12938 | { Bad_Opcode }, |
13860 | { Bad_Opcode }, |
12939 | }, |
13861 | }, |
12940 | /* dc */ |
13862 | /* dc */ |
12941 | { |
13863 | { |
12942 | { "fadd", { STi, ST } }, |
13864 | { "fadd", { STi, ST }, 0 }, |
12943 | { "fmul", { STi, ST } }, |
13865 | { "fmul", { STi, ST }, 0 }, |
12944 | { Bad_Opcode }, |
13866 | { Bad_Opcode }, |
12945 | { Bad_Opcode }, |
13867 | { Bad_Opcode }, |
12946 | { "fsub!M", { STi, ST } }, |
13868 | { "fsub!M", { STi, ST }, 0 }, |
12947 | { "fsubM", { STi, ST } }, |
13869 | { "fsubM", { STi, ST }, 0 }, |
12948 | { "fdiv!M", { STi, ST } }, |
13870 | { "fdiv!M", { STi, ST }, 0 }, |
12949 | { "fdivM", { STi, ST } }, |
13871 | { "fdivM", { STi, ST }, 0 }, |
12950 | }, |
13872 | }, |
12951 | /* dd */ |
13873 | /* dd */ |
12952 | { |
13874 | { |
12953 | { "ffree", { STi } }, |
13875 | { "ffree", { STi }, 0 }, |
12954 | { Bad_Opcode }, |
13876 | { Bad_Opcode }, |
12955 | { "fst", { STi } }, |
13877 | { "fst", { STi }, 0 }, |
12956 | { "fstp", { STi } }, |
13878 | { "fstp", { STi }, 0 }, |
12957 | { "fucom", { STi } }, |
13879 | { "fucom", { STi }, 0 }, |
12958 | { "fucomp", { STi } }, |
13880 | { "fucomp", { STi }, 0 }, |
12959 | { Bad_Opcode }, |
13881 | { Bad_Opcode }, |
12960 | { Bad_Opcode }, |
13882 | { Bad_Opcode }, |
12961 | }, |
13883 | }, |
12962 | /* de */ |
13884 | /* de */ |
12963 | { |
13885 | { |
12964 | { "faddp", { STi, ST } }, |
13886 | { "faddp", { STi, ST }, 0 }, |
12965 | { "fmulp", { STi, ST } }, |
13887 | { "fmulp", { STi, ST }, 0 }, |
12966 | { Bad_Opcode }, |
13888 | { Bad_Opcode }, |
12967 | { FGRPde_3 }, |
13889 | { FGRPde_3 }, |
12968 | { "fsub!Mp", { STi, ST } }, |
13890 | { "fsub!Mp", { STi, ST }, 0 }, |
12969 | { "fsubMp", { STi, ST } }, |
13891 | { "fsubMp", { STi, ST }, 0 }, |
12970 | { "fdiv!Mp", { STi, ST } }, |
13892 | { "fdiv!Mp", { STi, ST }, 0 }, |
12971 | { "fdivMp", { STi, ST } }, |
13893 | { "fdivMp", { STi, ST }, 0 }, |
12972 | }, |
13894 | }, |
12973 | /* df */ |
13895 | /* df */ |
12974 | { |
13896 | { |
12975 | { "ffreep", { STi } }, |
13897 | { "ffreep", { STi }, 0 }, |
12976 | { Bad_Opcode }, |
13898 | { Bad_Opcode }, |
12977 | { Bad_Opcode }, |
13899 | { Bad_Opcode }, |
12978 | { Bad_Opcode }, |
13900 | { Bad_Opcode }, |
12979 | { FGRPdf_4 }, |
13901 | { FGRPdf_4 }, |
12980 | { "fucomip", { ST, STi } }, |
13902 | { "fucomip", { ST, STi }, 0 }, |
12981 | { "fcomip", { ST, STi } }, |
13903 | { "fcomip", { ST, STi }, 0 }, |
Line 12982... | Line 13904... | ||
12982 | { Bad_Opcode }, |
13904 | { Bad_Opcode }, |
Line 13295... | Line 14217... | ||
13295 | *obufp++ = 'q'; |
14217 | *obufp++ = 'q'; |
13296 | else |
14218 | else |
13297 | *obufp++ = 'd'; |
14219 | *obufp++ = 'd'; |
13298 | break; |
14220 | break; |
13299 | case 'Z': |
14221 | case 'Z': |
- | 14222 | if (l != 0 || len != 1) |
|
- | 14223 | { |
|
- | 14224 | if (l != 1 || len != 2 || last[0] != 'X') |
|
- | 14225 | { |
|
- | 14226 | SAVE_LAST (*p); |
|
- | 14227 | break; |
|
- | 14228 | } |
|
- | 14229 | if (!need_vex || !vex.evex) |
|
- | 14230 | abort (); |
|
- | 14231 | if (intel_syntax |
|
- | 14232 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
|
- | 14233 | break; |
|
- | 14234 | switch (vex.length) |
|
- | 14235 | { |
|
- | 14236 | case 128: |
|
- | 14237 | *obufp++ = 'x'; |
|
- | 14238 | break; |
|
- | 14239 | case 256: |
|
- | 14240 | *obufp++ = 'y'; |
|
- | 14241 | break; |
|
- | 14242 | case 512: |
|
- | 14243 | *obufp++ = 'z'; |
|
- | 14244 | break; |
|
- | 14245 | default: |
|
- | 14246 | abort (); |
|
- | 14247 | } |
|
- | 14248 | break; |
|
- | 14249 | } |
|
13300 | if (intel_syntax) |
14250 | if (intel_syntax) |
13301 | break; |
14251 | break; |
13302 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) |
14252 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) |
13303 | { |
14253 | { |
13304 | *obufp++ = 'q'; |
14254 | *obufp++ = 'q'; |
Line 13346... | Line 14296... | ||
13346 | { |
14296 | { |
13347 | *obufp++ = 'q'; |
14297 | *obufp++ = 'q'; |
13348 | break; |
14298 | break; |
13349 | } |
14299 | } |
13350 | /* Fall through. */ |
14300 | /* Fall through. */ |
- | 14301 | goto case_P; |
|
13351 | case 'P': |
14302 | case 'P': |
- | 14303 | if (l == 0 && len == 1) |
|
- | 14304 | { |
|
- | 14305 | case_P: |
|
13352 | if (intel_syntax) |
14306 | if (intel_syntax) |
13353 | { |
14307 | { |
13354 | if ((rex & REX_W) == 0 |
14308 | if ((rex & REX_W) == 0 |
13355 | && (prefixes & PREFIX_DATA)) |
14309 | && (prefixes & PREFIX_DATA)) |
13356 | { |
14310 | { |
Line 13374... | Line 14328... | ||
13374 | else |
14328 | else |
13375 | *obufp++ = 'w'; |
14329 | *obufp++ = 'w'; |
13376 | used_prefixes |= (prefixes & PREFIX_DATA); |
14330 | used_prefixes |= (prefixes & PREFIX_DATA); |
13377 | } |
14331 | } |
13378 | } |
14332 | } |
- | 14333 | } |
|
- | 14334 | else |
|
- | 14335 | { |
|
- | 14336 | if (l != 1 || len != 2 || last[0] != 'L') |
|
- | 14337 | { |
|
- | 14338 | SAVE_LAST (*p); |
|
- | 14339 | break; |
|
- | 14340 | } |
|
- | 14341 | ||
- | 14342 | if ((prefixes & PREFIX_DATA) |
|
- | 14343 | || (rex & REX_W) |
|
- | 14344 | || (sizeflag & SUFFIX_ALWAYS)) |
|
- | 14345 | { |
|
- | 14346 | USED_REX (REX_W); |
|
- | 14347 | if (rex & REX_W) |
|
- | 14348 | *obufp++ = 'q'; |
|
- | 14349 | else |
|
- | 14350 | { |
|
- | 14351 | if (sizeflag & DFLAG) |
|
- | 14352 | *obufp++ = intel_syntax ? 'd' : 'l'; |
|
- | 14353 | else |
|
- | 14354 | *obufp++ = 'w'; |
|
- | 14355 | used_prefixes |= (prefixes & PREFIX_DATA); |
|
- | 14356 | } |
|
- | 14357 | } |
|
- | 14358 | } |
|
13379 | break; |
14359 | break; |
13380 | case 'U': |
14360 | case 'U': |
13381 | if (intel_syntax) |
14361 | if (intel_syntax) |
13382 | break; |
14362 | break; |
13383 | if (address_mode == mode_64bit |
14363 | if (address_mode == mode_64bit |
Line 13563... | Line 14543... | ||
13563 | break; |
14543 | break; |
13564 | } |
14544 | } |
13565 | if (!need_vex) |
14545 | if (!need_vex) |
13566 | abort (); |
14546 | abort (); |
13567 | if (intel_syntax |
14547 | if (intel_syntax |
13568 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
14548 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
13569 | break; |
14549 | break; |
13570 | switch (vex.length) |
14550 | switch (vex.length) |
13571 | { |
14551 | { |
13572 | case 128: |
14552 | case 128: |
13573 | *obufp++ = 'x'; |
14553 | *obufp++ = 'x'; |
13574 | break; |
14554 | break; |
13575 | case 256: |
14555 | case 256: |
13576 | *obufp++ = 'y'; |
14556 | *obufp++ = 'y'; |
13577 | break; |
14557 | break; |
- | 14558 | case 512: |
|
- | 14559 | if (!vex.evex) |
|
13578 | default: |
14560 | default: |
13579 | abort (); |
14561 | abort (); |
13580 | } |
14562 | } |
13581 | } |
14563 | } |
13582 | break; |
14564 | break; |
Line 13615... | Line 14597... | ||
13615 | *obufp++ = vex.w ? 'd': 's'; |
14597 | *obufp++ = vex.w ? 'd': 's'; |
13616 | else |
14598 | else |
13617 | *obufp++ = vex.w ? 'q': 'd'; |
14599 | *obufp++ = vex.w ? 'q': 'd'; |
13618 | } |
14600 | } |
13619 | break; |
14601 | break; |
- | 14602 | case '^': |
|
- | 14603 | if (intel_syntax) |
|
- | 14604 | break; |
|
- | 14605 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
|
- | 14606 | { |
|
- | 14607 | if (sizeflag & DFLAG) |
|
- | 14608 | *obufp++ = 'l'; |
|
- | 14609 | else |
|
- | 14610 | *obufp++ = 'w'; |
|
- | 14611 | used_prefixes |= (prefixes & PREFIX_DATA); |
|
- | 14612 | } |
|
- | 14613 | break; |
|
- | 14614 | case '@': |
|
- | 14615 | if (intel_syntax) |
|
- | 14616 | break; |
|
- | 14617 | if (address_mode == mode_64bit |
|
- | 14618 | && (isa64 == intel64 |
|
- | 14619 | || ((sizeflag & DFLAG) || (rex & REX_W)))) |
|
- | 14620 | *obufp++ = 'q'; |
|
- | 14621 | else if ((prefixes & PREFIX_DATA)) |
|
- | 14622 | { |
|
- | 14623 | if (!(sizeflag & DFLAG)) |
|
- | 14624 | *obufp++ = 'w'; |
|
- | 14625 | used_prefixes |= (prefixes & PREFIX_DATA); |
|
- | 14626 | } |
|
- | 14627 | break; |
|
13620 | } |
14628 | } |
13621 | alt = 0; |
14629 | alt = 0; |
13622 | } |
14630 | } |
13623 | *obufp = 0; |
14631 | *obufp = 0; |
13624 | mnemonicendp = obufp; |
14632 | mnemonicendp = obufp; |
Line 13632... | Line 14640... | ||
13632 | } |
14640 | } |
Line 13633... | Line 14641... | ||
13633 | 14641 | ||
13634 | static void |
14642 | static void |
13635 | append_seg (void) |
14643 | append_seg (void) |
- | 14644 | { |
|
13636 | { |
14645 | /* Only print the active segment register. */ |
- | 14646 | if (!active_seg_prefix) |
|
- | 14647 | return; |
|
- | 14648 | ||
- | 14649 | used_prefixes |= active_seg_prefix; |
|
13637 | if (prefixes & PREFIX_CS) |
14650 | switch (active_seg_prefix) |
13638 | { |
14651 | { |
13639 | used_prefixes |= PREFIX_CS; |
14652 | case PREFIX_CS: |
13640 | oappend_maybe_intel ("%cs:"); |
14653 | oappend_maybe_intel ("%cs:"); |
13641 | } |
14654 | break; |
13642 | if (prefixes & PREFIX_DS) |
- | |
13643 | { |
- | |
13644 | used_prefixes |= PREFIX_DS; |
14655 | case PREFIX_DS: |
13645 | oappend_maybe_intel ("%ds:"); |
14656 | oappend_maybe_intel ("%ds:"); |
13646 | } |
14657 | break; |
13647 | if (prefixes & PREFIX_SS) |
- | |
13648 | { |
- | |
13649 | used_prefixes |= PREFIX_SS; |
14658 | case PREFIX_SS: |
13650 | oappend_maybe_intel ("%ss:"); |
14659 | oappend_maybe_intel ("%ss:"); |
13651 | } |
14660 | break; |
13652 | if (prefixes & PREFIX_ES) |
- | |
13653 | { |
- | |
13654 | used_prefixes |= PREFIX_ES; |
14661 | case PREFIX_ES: |
13655 | oappend_maybe_intel ("%es:"); |
14662 | oappend_maybe_intel ("%es:"); |
13656 | } |
14663 | break; |
13657 | if (prefixes & PREFIX_FS) |
- | |
13658 | { |
- | |
13659 | used_prefixes |= PREFIX_FS; |
14664 | case PREFIX_FS: |
13660 | oappend_maybe_intel ("%fs:"); |
14665 | oappend_maybe_intel ("%fs:"); |
13661 | } |
14666 | break; |
13662 | if (prefixes & PREFIX_GS) |
- | |
13663 | { |
- | |
13664 | used_prefixes |= PREFIX_GS; |
14667 | case PREFIX_GS: |
- | 14668 | oappend_maybe_intel ("%gs:"); |
|
- | 14669 | break; |
|
- | 14670 | default: |
|
13665 | oappend_maybe_intel ("%gs:"); |
14671 | break; |
13666 | } |
14672 | } |
Line 13667... | Line 14673... | ||
13667 | } |
14673 | } |
13668 | 14674 | ||
Line 13792... | Line 14798... | ||
13792 | switch (bytemode) |
14798 | switch (bytemode) |
13793 | { |
14799 | { |
13794 | case b_mode: |
14800 | case b_mode: |
13795 | case b_swap_mode: |
14801 | case b_swap_mode: |
13796 | case dqb_mode: |
14802 | case dqb_mode: |
- | 14803 | case db_mode: |
|
13797 | oappend ("BYTE PTR "); |
14804 | oappend ("BYTE PTR "); |
13798 | break; |
14805 | break; |
13799 | case w_mode: |
14806 | case w_mode: |
- | 14807 | case dw_mode: |
|
13800 | case dqw_mode: |
14808 | case dqw_mode: |
- | 14809 | case dqw_swap_mode: |
|
13801 | oappend ("WORD PTR "); |
14810 | oappend ("WORD PTR "); |
13802 | break; |
14811 | break; |
13803 | case stack_v_mode: |
14812 | case stack_v_mode: |
13804 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
14813 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
13805 | { |
14814 | { |
Line 14072... | Line 15081... | ||
14072 | else |
15081 | else |
14073 | oappend ("DWORD PTR "); |
15082 | oappend ("DWORD PTR "); |
14074 | } |
15083 | } |
14075 | else |
15084 | else |
14076 | { |
15085 | { |
14077 | if (vex.length != 512) |
15086 | switch (vex.length) |
- | 15087 | { |
|
- | 15088 | case 128: |
|
- | 15089 | oappend ("XMMWORD PTR "); |
|
- | 15090 | break; |
|
- | 15091 | case 256: |
|
- | 15092 | oappend ("YMMWORD PTR "); |
|
14078 | abort (); |
15093 | break; |
- | 15094 | case 512: |
|
14079 | oappend ("ZMMWORD PTR "); |
15095 | oappend ("ZMMWORD PTR "); |
- | 15096 | break; |
|
- | 15097 | default: |
|
- | 15098 | abort (); |
|
- | 15099 | } |
|
14080 | } |
15100 | } |
14081 | break; |
15101 | break; |
- | 15102 | case vex_vsib_q_w_d_mode: |
|
- | 15103 | case vex_vsib_d_w_d_mode: |
|
- | 15104 | if (!need_vex || !vex.evex) |
|
- | 15105 | abort (); |
|
- | 15106 | ||
- | 15107 | switch (vex.length) |
|
- | 15108 | { |
|
- | 15109 | case 128: |
|
- | 15110 | oappend ("QWORD PTR "); |
|
- | 15111 | break; |
|
- | 15112 | case 256: |
|
- | 15113 | oappend ("XMMWORD PTR "); |
|
- | 15114 | break; |
|
- | 15115 | case 512: |
|
- | 15116 | oappend ("YMMWORD PTR "); |
|
- | 15117 | break; |
|
- | 15118 | default: |
|
- | 15119 | abort (); |
|
- | 15120 | } |
|
- | 15121 | ||
- | 15122 | break; |
|
- | 15123 | case mask_bd_mode: |
|
- | 15124 | if (!need_vex || vex.length != 128) |
|
- | 15125 | abort (); |
|
- | 15126 | if (vex.w) |
|
- | 15127 | oappend ("DWORD PTR "); |
|
- | 15128 | else |
|
- | 15129 | oappend ("BYTE PTR "); |
|
- | 15130 | break; |
|
14082 | case mask_mode: |
15131 | case mask_mode: |
14083 | if (!need_vex) |
15132 | if (!need_vex) |
14084 | abort (); |
15133 | abort (); |
14085 | /* Currently the only instructions, which allows either mask or |
- | |
14086 | memory operand, are AVX512's KMOVW instructions. They need |
- | |
14087 | Word-sized operand. */ |
15134 | if (vex.w) |
14088 | if (vex.w || vex.length != 128) |
15135 | oappend ("QWORD PTR "); |
14089 | abort (); |
15136 | else |
14090 | oappend ("WORD PTR "); |
15137 | oappend ("WORD PTR "); |
14091 | break; |
15138 | break; |
14092 | case v_bnd_mode: |
15139 | case v_bnd_mode: |
14093 | default: |
15140 | default: |
14094 | break; |
15141 | break; |
Line 14104... | Line 15151... | ||
14104 | USED_REX (REX_B); |
15151 | USED_REX (REX_B); |
14105 | if ((rex & REX_B)) |
15152 | if ((rex & REX_B)) |
14106 | reg += 8; |
15153 | reg += 8; |
Line 14107... | Line 15154... | ||
14107 | 15154 | ||
14108 | if ((sizeflag & SUFFIX_ALWAYS) |
15155 | if ((sizeflag & SUFFIX_ALWAYS) |
- | 15156 | && (bytemode == b_swap_mode |
|
- | 15157 | || bytemode == v_swap_mode |
|
14109 | && (bytemode == b_swap_mode || bytemode == v_swap_mode)) |
15158 | || bytemode == dqw_swap_mode)) |
Line 14110... | Line 15159... | ||
14110 | swap_operand (); |
15159 | swap_operand (); |
14111 | 15160 | ||
14112 | switch (bytemode) |
15161 | switch (bytemode) |
Line 14121... | Line 15170... | ||
14121 | break; |
15170 | break; |
14122 | case w_mode: |
15171 | case w_mode: |
14123 | names = names16; |
15172 | names = names16; |
14124 | break; |
15173 | break; |
14125 | case d_mode: |
15174 | case d_mode: |
- | 15175 | case dw_mode: |
|
- | 15176 | case db_mode: |
|
14126 | names = names32; |
15177 | names = names32; |
14127 | break; |
15178 | break; |
14128 | case q_mode: |
15179 | case q_mode: |
14129 | names = names64; |
15180 | names = names64; |
14130 | break; |
15181 | break; |
Line 14147... | Line 15198... | ||
14147 | case v_swap_mode: |
15198 | case v_swap_mode: |
14148 | case dq_mode: |
15199 | case dq_mode: |
14149 | case dqb_mode: |
15200 | case dqb_mode: |
14150 | case dqd_mode: |
15201 | case dqd_mode: |
14151 | case dqw_mode: |
15202 | case dqw_mode: |
- | 15203 | case dqw_swap_mode: |
|
14152 | USED_REX (REX_W); |
15204 | USED_REX (REX_W); |
14153 | if (rex & REX_W) |
15205 | if (rex & REX_W) |
14154 | names = names64; |
15206 | names = names64; |
14155 | else |
15207 | else |
14156 | { |
15208 | { |
Line 14161... | Line 15213... | ||
14161 | else |
15213 | else |
14162 | names = names16; |
15214 | names = names16; |
14163 | used_prefixes |= (prefixes & PREFIX_DATA); |
15215 | used_prefixes |= (prefixes & PREFIX_DATA); |
14164 | } |
15216 | } |
14165 | break; |
15217 | break; |
- | 15218 | case mask_bd_mode: |
|
14166 | case mask_mode: |
15219 | case mask_mode: |
14167 | names = names_mask; |
15220 | names = names_mask; |
14168 | break; |
15221 | break; |
14169 | case 0: |
15222 | case 0: |
14170 | return; |
15223 | return; |
Line 14186... | Line 15239... | ||
14186 | if (vex.evex) |
15239 | if (vex.evex) |
14187 | { |
15240 | { |
14188 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ |
15241 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ |
14189 | if (vex.b |
15242 | if (vex.b |
14190 | && bytemode != x_mode |
15243 | && bytemode != x_mode |
- | 15244 | && bytemode != xmmq_mode |
|
14191 | && bytemode != evex_half_bcst_xmmq_mode) |
15245 | && bytemode != evex_half_bcst_xmmq_mode) |
14192 | { |
15246 | { |
14193 | BadOp (); |
15247 | BadOp (); |
14194 | return; |
15248 | return; |
14195 | } |
15249 | } |
14196 | switch (bytemode) |
15250 | switch (bytemode) |
14197 | { |
15251 | { |
- | 15252 | case dqw_mode: |
|
- | 15253 | case dw_mode: |
|
- | 15254 | case dqw_swap_mode: |
|
- | 15255 | shift = 1; |
|
- | 15256 | break; |
|
- | 15257 | case dqb_mode: |
|
- | 15258 | case db_mode: |
|
- | 15259 | shift = 0; |
|
- | 15260 | break; |
|
14198 | case vex_vsib_d_w_dq_mode: |
15261 | case vex_vsib_d_w_dq_mode: |
- | 15262 | case vex_vsib_d_w_d_mode: |
|
- | 15263 | case vex_vsib_q_w_dq_mode: |
|
- | 15264 | case vex_vsib_q_w_d_mode: |
|
14199 | case evex_x_gscat_mode: |
15265 | case evex_x_gscat_mode: |
14200 | case xmm_mdq_mode: |
15266 | case xmm_mdq_mode: |
14201 | shift = vex.w ? 3 : 2; |
15267 | shift = vex.w ? 3 : 2; |
14202 | break; |
15268 | break; |
14203 | case vex_vsib_q_w_dq_mode: |
- | |
14204 | shift = 3; |
- | |
14205 | break; |
- | |
14206 | case x_mode: |
15269 | case x_mode: |
14207 | case evex_half_bcst_xmmq_mode: |
15270 | case evex_half_bcst_xmmq_mode: |
- | 15271 | case xmmq_mode: |
|
14208 | if (vex.b) |
15272 | if (vex.b) |
14209 | { |
15273 | { |
14210 | shift = vex.w ? 3 : 2; |
15274 | shift = vex.w ? 3 : 2; |
14211 | break; |
15275 | break; |
14212 | } |
15276 | } |
14213 | /* Fall through if vex.b == 0. */ |
15277 | /* Fall through if vex.b == 0. */ |
14214 | case xmmqd_mode: |
15278 | case xmmqd_mode: |
14215 | case xmmdw_mode: |
15279 | case xmmdw_mode: |
14216 | case xmmq_mode: |
- | |
14217 | case ymmq_mode: |
15280 | case ymmq_mode: |
14218 | case evex_x_nobcst_mode: |
15281 | case evex_x_nobcst_mode: |
14219 | case x_swap_mode: |
15282 | case x_swap_mode: |
14220 | switch (vex.length) |
15283 | switch (vex.length) |
14221 | { |
15284 | { |
Line 14266... | Line 15329... | ||
14266 | For these modes we currently have shift 4, 5 or 6 depending on |
15329 | For these modes we currently have shift 4, 5 or 6 depending on |
14267 | vex.length (it corresponds to xmmword, ymmword or zmmword |
15330 | vex.length (it corresponds to xmmword, ymmword or zmmword |
14268 | operand). We might want to make it 3, 4 or 5 (e.g. for |
15331 | operand). We might want to make it 3, 4 or 5 (e.g. for |
14269 | xmmq_mode). In case of broadcast enabled the corrections |
15332 | xmmq_mode). In case of broadcast enabled the corrections |
14270 | aren't needed, as element size is always 32 or 64 bits. */ |
15333 | aren't needed, as element size is always 32 or 64 bits. */ |
- | 15334 | if (!vex.b |
|
14271 | if (bytemode == xmmq_mode |
15335 | && (bytemode == xmmq_mode |
14272 | || (bytemode == evex_half_bcst_xmmq_mode |
15336 | || bytemode == evex_half_bcst_xmmq_mode)) |
14273 | && !vex.b)) |
- | |
14274 | shift -= 1; |
15337 | shift -= 1; |
14275 | else if (bytemode == xmmqd_mode) |
15338 | else if (bytemode == xmmqd_mode) |
14276 | shift -= 2; |
15339 | shift -= 2; |
14277 | else if (bytemode == xmmdw_mode) |
15340 | else if (bytemode == xmmdw_mode) |
14278 | shift -= 3; |
15341 | shift -= 3; |
- | 15342 | else if (bytemode == ymmq_mode && vex.length == 128) |
|
- | 15343 | shift -= 1; |
|
14279 | } |
15344 | } |
14280 | else |
15345 | else |
14281 | shift = 0; |
15346 | shift = 0; |
Line 14282... | Line 15347... | ||
14282 | 15347 | ||
Line 14315... | Line 15380... | ||
14315 | if (rex & REX_X) |
15380 | if (rex & REX_X) |
14316 | vindex += 8; |
15381 | vindex += 8; |
14317 | switch (bytemode) |
15382 | switch (bytemode) |
14318 | { |
15383 | { |
14319 | case vex_vsib_d_w_dq_mode: |
15384 | case vex_vsib_d_w_dq_mode: |
- | 15385 | case vex_vsib_d_w_d_mode: |
|
14320 | case vex_vsib_q_w_dq_mode: |
15386 | case vex_vsib_q_w_dq_mode: |
- | 15387 | case vex_vsib_q_w_d_mode: |
|
14321 | if (!need_vex) |
15388 | if (!need_vex) |
14322 | abort (); |
15389 | abort (); |
14323 | if (vex.evex) |
15390 | if (vex.evex) |
14324 | { |
15391 | { |
14325 | if (!vex.v) |
15392 | if (!vex.v) |
Line 14331... | Line 15398... | ||
14331 | { |
15398 | { |
14332 | case 128: |
15399 | case 128: |
14333 | indexes64 = indexes32 = names_xmm; |
15400 | indexes64 = indexes32 = names_xmm; |
14334 | break; |
15401 | break; |
14335 | case 256: |
15402 | case 256: |
- | 15403 | if (!vex.w |
|
- | 15404 | || bytemode == vex_vsib_q_w_dq_mode |
|
14336 | if (!vex.w || bytemode == vex_vsib_q_w_dq_mode) |
15405 | || bytemode == vex_vsib_q_w_d_mode) |
14337 | indexes64 = indexes32 = names_ymm; |
15406 | indexes64 = indexes32 = names_ymm; |
14338 | else |
15407 | else |
14339 | indexes64 = indexes32 = names_xmm; |
15408 | indexes64 = indexes32 = names_xmm; |
14340 | break; |
15409 | break; |
14341 | case 512: |
15410 | case 512: |
- | 15411 | if (!vex.w |
|
- | 15412 | || bytemode == vex_vsib_q_w_dq_mode |
|
14342 | if (!vex.w || bytemode == vex_vsib_q_w_dq_mode) |
15413 | || bytemode == vex_vsib_q_w_d_mode) |
14343 | indexes64 = indexes32 = names_zmm; |
15414 | indexes64 = indexes32 = names_zmm; |
14344 | else |
15415 | else |
14345 | indexes64 = indexes32 = names_ymm; |
15416 | indexes64 = indexes32 = names_ymm; |
14346 | break; |
15417 | break; |
14347 | default: |
15418 | default: |
Line 14478... | Line 15549... | ||
14478 | } |
15549 | } |
14479 | else if (intel_syntax) |
15550 | else if (intel_syntax) |
14480 | { |
15551 | { |
14481 | if (modrm.mod != 0 || base == 5) |
15552 | if (modrm.mod != 0 || base == 5) |
14482 | { |
15553 | { |
14483 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
- | |
14484 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) |
- | |
14485 | ; |
- | |
14486 | else |
15554 | if (!active_seg_prefix) |
14487 | { |
15555 | { |
14488 | oappend (names_seg[ds_reg - es_reg]); |
15556 | oappend (names_seg[ds_reg - es_reg]); |
14489 | oappend (":"); |
15557 | oappend (":"); |
14490 | } |
15558 | } |
14491 | print_operand_value (scratchbuf, 1, disp); |
15559 | print_operand_value (scratchbuf, 1, disp); |
Line 14554... | Line 15622... | ||
14554 | *obufp++ = close_char; |
15622 | *obufp++ = close_char; |
14555 | *obufp = '\0'; |
15623 | *obufp = '\0'; |
14556 | } |
15624 | } |
14557 | else if (intel_syntax) |
15625 | else if (intel_syntax) |
14558 | { |
15626 | { |
14559 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
- | |
14560 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) |
15627 | if (!active_seg_prefix) |
14561 | ; |
- | |
14562 | else |
- | |
14563 | { |
15628 | { |
14564 | oappend (names_seg[ds_reg - es_reg]); |
15629 | oappend (names_seg[ds_reg - es_reg]); |
14565 | oappend (":"); |
15630 | oappend (":"); |
14566 | } |
15631 | } |
14567 | print_operand_value (scratchbuf, 1, disp & 0xffff); |
15632 | print_operand_value (scratchbuf, 1, disp & 0xffff); |
14568 | oappend (scratchbuf); |
15633 | oappend (scratchbuf); |
14569 | } |
15634 | } |
14570 | } |
15635 | } |
14571 | if (vex.evex && vex.b |
15636 | if (vex.evex && vex.b |
14572 | && (bytemode == x_mode |
15637 | && (bytemode == x_mode |
- | 15638 | || bytemode == xmmq_mode |
|
14573 | || bytemode == evex_half_bcst_xmmq_mode)) |
15639 | || bytemode == evex_half_bcst_xmmq_mode)) |
14574 | { |
15640 | { |
- | 15641 | if (vex.w |
|
- | 15642 | || bytemode == xmmq_mode |
|
14575 | if (vex.w || bytemode == evex_half_bcst_xmmq_mode) |
15643 | || bytemode == evex_half_bcst_xmmq_mode) |
- | 15644 | { |
|
- | 15645 | switch (vex.length) |
|
- | 15646 | { |
|
- | 15647 | case 128: |
|
- | 15648 | oappend ("{1to2}"); |
|
- | 15649 | break; |
|
- | 15650 | case 256: |
|
- | 15651 | oappend ("{1to4}"); |
|
- | 15652 | break; |
|
- | 15653 | case 512: |
|
14576 | oappend ("{1to8}"); |
15654 | oappend ("{1to8}"); |
- | 15655 | break; |
|
- | 15656 | default: |
|
- | 15657 | abort (); |
|
- | 15658 | } |
|
- | 15659 | } |
|
14577 | else |
15660 | else |
- | 15661 | { |
|
- | 15662 | switch (vex.length) |
|
- | 15663 | { |
|
- | 15664 | case 128: |
|
- | 15665 | oappend ("{1to4}"); |
|
- | 15666 | break; |
|
- | 15667 | case 256: |
|
- | 15668 | oappend ("{1to8}"); |
|
- | 15669 | break; |
|
- | 15670 | case 512: |
|
14578 | oappend ("{1to16}"); |
15671 | oappend ("{1to16}"); |
- | 15672 | break; |
|
- | 15673 | default: |
|
- | 15674 | abort (); |
|
- | 15675 | } |
|
- | 15676 | } |
|
14579 | } |
15677 | } |
14580 | } |
15678 | } |
Line 14581... | Line 15679... | ||
14581 | 15679 | ||
14582 | static void |
15680 | static void |
Line 14610... | Line 15708... | ||
14610 | break; |
15708 | break; |
14611 | case w_mode: |
15709 | case w_mode: |
14612 | oappend (names16[modrm.reg + add]); |
15710 | oappend (names16[modrm.reg + add]); |
14613 | break; |
15711 | break; |
14614 | case d_mode: |
15712 | case d_mode: |
- | 15713 | case db_mode: |
|
- | 15714 | case dw_mode: |
|
14615 | oappend (names32[modrm.reg + add]); |
15715 | oappend (names32[modrm.reg + add]); |
14616 | break; |
15716 | break; |
14617 | case q_mode: |
15717 | case q_mode: |
14618 | oappend (names64[modrm.reg + add]); |
15718 | oappend (names64[modrm.reg + add]); |
14619 | break; |
15719 | break; |
Line 14623... | Line 15723... | ||
14623 | case v_mode: |
15723 | case v_mode: |
14624 | case dq_mode: |
15724 | case dq_mode: |
14625 | case dqb_mode: |
15725 | case dqb_mode: |
14626 | case dqd_mode: |
15726 | case dqd_mode: |
14627 | case dqw_mode: |
15727 | case dqw_mode: |
- | 15728 | case dqw_swap_mode: |
|
14628 | USED_REX (REX_W); |
15729 | USED_REX (REX_W); |
14629 | if (rex & REX_W) |
15730 | if (rex & REX_W) |
14630 | oappend (names64[modrm.reg + add]); |
15731 | oappend (names64[modrm.reg + add]); |
14631 | else |
15732 | else |
14632 | { |
15733 | { |
Line 14641... | Line 15742... | ||
14641 | if (address_mode == mode_64bit) |
15742 | if (address_mode == mode_64bit) |
14642 | oappend (names64[modrm.reg + add]); |
15743 | oappend (names64[modrm.reg + add]); |
14643 | else |
15744 | else |
14644 | oappend (names32[modrm.reg + add]); |
15745 | oappend (names32[modrm.reg + add]); |
14645 | break; |
15746 | break; |
- | 15747 | case mask_bd_mode: |
|
14646 | case mask_mode: |
15748 | case mask_mode: |
14647 | oappend (names_mask[modrm.reg + add]); |
15749 | oappend (names_mask[modrm.reg + add]); |
14648 | break; |
15750 | break; |
14649 | default: |
15751 | default: |
14650 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
15752 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
Line 14662... | Line 15764... | ||
14662 | 15764 | ||
14663 | FETCH_DATA (the_info, codep + 8); |
15765 | FETCH_DATA (the_info, codep + 8); |
14664 | a = *codep++ & 0xff; |
15766 | a = *codep++ & 0xff; |
14665 | a |= (*codep++ & 0xff) << 8; |
15767 | a |= (*codep++ & 0xff) << 8; |
14666 | a |= (*codep++ & 0xff) << 16; |
15768 | a |= (*codep++ & 0xff) << 16; |
14667 | a |= (*codep++ & 0xff) << 24; |
15769 | a |= (*codep++ & 0xffu) << 24; |
14668 | b = *codep++ & 0xff; |
15770 | b = *codep++ & 0xff; |
14669 | b |= (*codep++ & 0xff) << 8; |
15771 | b |= (*codep++ & 0xff) << 8; |
14670 | b |= (*codep++ & 0xff) << 16; |
15772 | b |= (*codep++ & 0xff) << 16; |
14671 | b |= (*codep++ & 0xff) << 24; |
15773 | b |= (*codep++ & 0xffu) << 24; |
14672 | x = a + ((bfd_vma) b << 32); |
15774 | x = a + ((bfd_vma) b << 32); |
14673 | #else |
15775 | #else |
14674 | abort (); |
15776 | abort (); |
14675 | x = 0; |
15777 | x = 0; |
Line 15037... | Line 16139... | ||
15037 | disp = *codep++; |
16139 | disp = *codep++; |
15038 | if ((disp & 0x80) != 0) |
16140 | if ((disp & 0x80) != 0) |
15039 | disp -= 0x100; |
16141 | disp -= 0x100; |
15040 | break; |
16142 | break; |
15041 | case v_mode: |
16143 | case v_mode: |
- | 16144 | if (isa64 == amd64) |
|
15042 | USED_REX (REX_W); |
16145 | USED_REX (REX_W); |
- | 16146 | if ((sizeflag & DFLAG) |
|
- | 16147 | || (address_mode == mode_64bit |
|
15043 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
16148 | && (isa64 != amd64 || (rex & REX_W)))) |
15044 | disp = get32s (); |
16149 | disp = get32s (); |
15045 | else |
16150 | else |
15046 | { |
16151 | { |
15047 | disp = get16 (); |
16152 | disp = get16 (); |
15048 | if ((disp & 0x8000) != 0) |
16153 | if ((disp & 0x8000) != 0) |
Line 15054... | Line 16159... | ||
15054 | mask = 0xffff; |
16159 | mask = 0xffff; |
15055 | if ((prefixes & PREFIX_DATA) == 0) |
16160 | if ((prefixes & PREFIX_DATA) == 0) |
15056 | segment = ((start_pc + codep - start_codep) |
16161 | segment = ((start_pc + codep - start_codep) |
15057 | & ~((bfd_vma) 0xffff)); |
16162 | & ~((bfd_vma) 0xffff)); |
15058 | } |
16163 | } |
- | 16164 | if (address_mode != mode_64bit |
|
15059 | if (!(rex & REX_W)) |
16165 | || (isa64 == amd64 && !(rex & REX_W))) |
15060 | used_prefixes |= (prefixes & PREFIX_DATA); |
16166 | used_prefixes |= (prefixes & PREFIX_DATA); |
15061 | break; |
16167 | break; |
15062 | default: |
16168 | default: |
15063 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
16169 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
15064 | return; |
16170 | return; |
Line 15115... | Line 16221... | ||
15115 | else |
16221 | else |
15116 | off = get16 (); |
16222 | off = get16 (); |
Line 15117... | Line 16223... | ||
15117 | 16223 | ||
15118 | if (intel_syntax) |
16224 | if (intel_syntax) |
15119 | { |
16225 | { |
15120 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
- | |
15121 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
16226 | if (!active_seg_prefix) |
15122 | { |
16227 | { |
15123 | oappend (names_seg[ds_reg - es_reg]); |
16228 | oappend (names_seg[ds_reg - es_reg]); |
15124 | oappend (":"); |
16229 | oappend (":"); |
15125 | } |
16230 | } |
Line 15146... | Line 16251... | ||
15146 | 16251 | ||
Line 15147... | Line 16252... | ||
15147 | off = get64 (); |
16252 | off = get64 (); |
15148 | 16253 | ||
15149 | if (intel_syntax) |
16254 | if (intel_syntax) |
15150 | { |
- | |
15151 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
16255 | { |
15152 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
16256 | if (!active_seg_prefix) |
15153 | { |
16257 | { |
15154 | oappend (names_seg[ds_reg - es_reg]); |
16258 | oappend (names_seg[ds_reg - es_reg]); |
15155 | oappend (":"); |
16259 | oappend (":"); |
Line 15223... | Line 16327... | ||
15223 | break; |
16327 | break; |
15224 | default: |
16328 | default: |
15225 | intel_operand_size (b_mode, sizeflag); |
16329 | intel_operand_size (b_mode, sizeflag); |
15226 | } |
16330 | } |
15227 | } |
16331 | } |
15228 | if ((prefixes |
16332 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15229 | & (PREFIX_CS |
16333 | default segment register DS is printed. */ |
15230 | | PREFIX_DS |
- | |
15231 | | PREFIX_SS |
- | |
15232 | | PREFIX_ES |
- | |
15233 | | PREFIX_FS |
- | |
15234 | | PREFIX_GS)) == 0) |
16334 | if (!active_seg_prefix) |
15235 | prefixes |= PREFIX_DS; |
16335 | active_seg_prefix = PREFIX_DS; |
15236 | append_seg (); |
16336 | append_seg (); |
15237 | ptr_reg (code, sizeflag); |
16337 | ptr_reg (code, sizeflag); |
15238 | } |
16338 | } |
Line 15239... | Line 16339... | ||
15239 | 16339 | ||
Line 15282... | Line 16382... | ||
15282 | } |
16382 | } |
Line 15283... | Line 16383... | ||
15283 | 16383 | ||
15284 | static void |
16384 | static void |
15285 | OP_R (int bytemode, int sizeflag) |
16385 | OP_R (int bytemode, int sizeflag) |
15286 | { |
16386 | { |
15287 | if (modrm.mod == 3) |
16387 | /* Skip mod/rm byte. */ |
15288 | OP_E (bytemode, sizeflag); |
16388 | MODRM_CHECK; |
15289 | else |
16389 | codep++; |
15290 | BadOp (); |
16390 | OP_E_register (bytemode, sizeflag); |
Line 15291... | Line 16391... | ||
15291 | } |
16391 | } |
15292 | 16392 | ||
15293 | static void |
16393 | static void |
Line 15335... | Line 16435... | ||
15335 | { |
16435 | { |
15336 | case 128: |
16436 | case 128: |
15337 | names = names_xmm; |
16437 | names = names_xmm; |
15338 | break; |
16438 | break; |
15339 | case 256: |
16439 | case 256: |
- | 16440 | if (vex.w |
|
15340 | if (vex.w || bytemode != vex_vsib_q_w_dq_mode) |
16441 | || (bytemode != vex_vsib_q_w_dq_mode |
- | 16442 | && bytemode != vex_vsib_q_w_d_mode)) |
|
15341 | names = names_ymm; |
16443 | names = names_ymm; |
15342 | else |
16444 | else |
15343 | names = names_xmm; |
16445 | names = names_xmm; |
15344 | break; |
16446 | break; |
15345 | case 512: |
16447 | case 512: |
Line 15471... | Line 16573... | ||
15471 | } |
16573 | } |
Line 15472... | Line 16574... | ||
15472 | 16574 | ||
15473 | if ((sizeflag & SUFFIX_ALWAYS) |
16575 | if ((sizeflag & SUFFIX_ALWAYS) |
15474 | && (bytemode == x_swap_mode |
16576 | && (bytemode == x_swap_mode |
- | 16577 | || bytemode == d_swap_mode |
|
15475 | || bytemode == d_swap_mode |
16578 | || bytemode == dqw_swap_mode |
15476 | || bytemode == d_scalar_swap_mode |
16579 | || bytemode == d_scalar_swap_mode |
15477 | || bytemode == q_swap_mode |
16580 | || bytemode == q_swap_mode |
15478 | || bytemode == q_scalar_swap_mode)) |
16581 | || bytemode == q_scalar_swap_mode)) |
Line 15727... | Line 16830... | ||
15727 | scratchbuf[0] = '\0'; |
16830 | scratchbuf[0] = '\0'; |
15728 | } |
16831 | } |
15729 | } |
16832 | } |
Line 15730... | Line 16833... | ||
15730 | 16833 | ||
- | 16834 | static void |
|
- | 16835 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, |
|
- | 16836 | int sizeflag ATTRIBUTE_UNUSED) |
|
- | 16837 | { |
|
- | 16838 | /* mwaitx %eax,%ecx,%ebx */ |
|
- | 16839 | if (!intel_syntax) |
|
- | 16840 | { |
|
- | 16841 | const char **names = (address_mode == mode_64bit |
|
- | 16842 | ? names64 : names32); |
|
- | 16843 | strcpy (op_out[0], names[0]); |
|
- | 16844 | strcpy (op_out[1], names[1]); |
|
- | 16845 | strcpy (op_out[2], names[3]); |
|
- | 16846 | two_source_ops = 1; |
|
- | 16847 | } |
|
- | 16848 | /* Skip mod/rm byte. */ |
|
- | 16849 | MODRM_CHECK; |
|
- | 16850 | codep++; |
|
- | 16851 | } |
|
- | 16852 | ||
15731 | static void |
16853 | static void |
15732 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16854 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
15733 | int sizeflag ATTRIBUTE_UNUSED) |
16855 | int sizeflag ATTRIBUTE_UNUSED) |
15734 | { |
16856 | { |
15735 | /* mwait %eax,%ecx */ |
16857 | /* mwait %eax,%ecx */ |
Line 16041... | Line 17163... | ||
16041 | switch (bytemode) |
17163 | switch (bytemode) |
16042 | { |
17164 | { |
16043 | case vex_mode: |
17165 | case vex_mode: |
16044 | case vex128_mode: |
17166 | case vex128_mode: |
16045 | case vex_vsib_q_w_dq_mode: |
17167 | case vex_vsib_q_w_dq_mode: |
- | 17168 | case vex_vsib_q_w_d_mode: |
|
16046 | names = names_xmm; |
17169 | names = names_xmm; |
16047 | break; |
17170 | break; |
16048 | case dq_mode: |
17171 | case dq_mode: |
16049 | if (vex.w) |
17172 | if (vex.w) |
16050 | names = names64; |
17173 | names = names64; |
16051 | else |
17174 | else |
16052 | names = names32; |
17175 | names = names32; |
16053 | break; |
17176 | break; |
- | 17177 | case mask_bd_mode: |
|
16054 | case mask_mode: |
17178 | case mask_mode: |
16055 | names = names_mask; |
17179 | names = names_mask; |
16056 | break; |
17180 | break; |
16057 | default: |
17181 | default: |
16058 | abort (); |
17182 | abort (); |
Line 16065... | Line 17189... | ||
16065 | case vex_mode: |
17189 | case vex_mode: |
16066 | case vex256_mode: |
17190 | case vex256_mode: |
16067 | names = names_ymm; |
17191 | names = names_ymm; |
16068 | break; |
17192 | break; |
16069 | case vex_vsib_q_w_dq_mode: |
17193 | case vex_vsib_q_w_dq_mode: |
- | 17194 | case vex_vsib_q_w_d_mode: |
|
16070 | names = vex.w ? names_ymm : names_xmm; |
17195 | names = vex.w ? names_ymm : names_xmm; |
16071 | break; |
17196 | break; |
- | 17197 | case mask_bd_mode: |
|
16072 | case mask_mode: |
17198 | case mask_mode: |
16073 | names = names_mask; |
17199 | names = names_mask; |
16074 | break; |
17200 | break; |
16075 | default: |
17201 | default: |
16076 | abort (); |
17202 | abort (); |
Line 16653... | Line 17779... | ||
16653 | 17779 | ||
16654 | static void |
17780 | static void |
16655 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
17781 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
16656 | { |
17782 | { |
16657 | if (!vex.evex |
17783 | if (!vex.evex |
16658 | || bytemode != mask_mode) |
17784 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
Line 16659... | Line 17785... | ||
16659 | abort (); |
17785 | abort (); |
16660 | 17786 | ||
16661 | USED_REX (REX_R); |
17787 | USED_REX (REX_R); |