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/* Definitions for opcode table for the sparc.
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/* Definitions for opcode table for the sparc.
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   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
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   2003, 2005, 2010, 2011 Free Software Foundation, Inc.
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   Copyright (C) 1989-2015 Free Software Foundation, Inc.
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   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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   the GNU Binutils.
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   the GNU Binutils.
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  unsigned long lose;	/* Bits that must not be set.  */
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  unsigned long lose;	/* Bits that must not be set.  */
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  const char *args;
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  const char *args;
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  /* This was called "delayed" in versions before the flags.  */
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  /* This was called "delayed" in versions before the flags.  */
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  unsigned int flags;
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  unsigned int flags;
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  unsigned int hwcaps;
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  unsigned int hwcaps;
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  unsigned int hwcaps2;
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  short architecture;	/* Bitmask of sparc_opcode_arch_val's.  */
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  short architecture;	/* Bitmask of sparc_opcode_arch_val's.  */
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} sparc_opcode;
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} sparc_opcode;
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/* FIXME: Add F_ANACHRONISTIC flag for v9.  */
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/* FIXME: Add F_ANACHRONISTIC flag for v9.  */
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#define F_FBR		0x00000040 /* Floating point branch.  */
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#define F_FBR		0x00000040 /* Floating point branch.  */
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#define F_PREFERRED	0x00000080 /* A preferred alias.  */
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#define F_PREFERRED	0x00000080 /* A preferred alias.  */
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#define F_PREF_ALIAS	(F_ALIAS|F_PREFERRED)
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#define F_PREF_ALIAS	(F_ALIAS|F_PREFERRED)
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/* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_*
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/* These must match the HWCAP_* values precisely.  */
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   values precisely.  See include/elf/sparc.h.  */
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#define HWCAP_MUL32	0x00000001 /* umul/umulcc/smul/smulcc insns */
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#define HWCAP_MUL32	0x00000001 /* umul/umulcc/smul/smulcc insns */
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#define HWCAP_DIV32	0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
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#define HWCAP_DIV32	0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
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#define HWCAP_FSMULD	0x00000004 /* 'fsmuld' insn */
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#define HWCAP_FSMULD	0x00000004 /* 'fsmuld' insn */
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#define HWCAP_MONT	0x04000000 /* Montgomery Mult/Sqrt */
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#define HWCAP_MONT	0x04000000 /* Montgomery Mult/Sqrt */
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#define HWCAP_PAUSE	0x08000000 /* Pause insn */
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#define HWCAP_PAUSE	0x08000000 /* Pause insn */
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#define HWCAP_CBCOND	0x10000000 /* Compare and Branch insns */
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#define HWCAP_CBCOND	0x10000000 /* Compare and Branch insns */
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#define HWCAP_CRC32C	0x20000000 /* CRC32C insn */
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#define HWCAP_CRC32C	0x20000000 /* CRC32C insn */
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#define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
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#define HWCAP2_VIS3B     0x00000002 /* Subset of VIS3 present on sparc64 X+.  */
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#define HWCAP2_ADP       0x00000004 /* Application Data Protection */
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#define HWCAP2_SPARC5    0x00000008 /* The 29 new fp and sub instructions */
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#define HWCAP2_MWAIT     0x00000010 /* mwait instruction and load/monitor ASIs */
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#define HWCAP2_XMPMUL    0x00000020 /* XOR multiple precision multiply */
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#define HWCAP2_XMONT     0x00000040 /* XOR Montgomery mult/sqr instructions */
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#define HWCAP2_NSEC      \
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                         0x00000080 /* pause insn with support for nsec timings */
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#define HWCAP2_FJATHHPC  0x00001000 /* Fujitsu HPC instrs */
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#define HWCAP2_FJDES     0x00002000 /* Fujitsu DES instrs */
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#define HWCAP2_FJAES     0x00010000 /* Fujitsu AES instrs */
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/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
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/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
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   macro), which is 64 bits. It is handled as a special case.
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   macro), which is 64 bits. It is handled as a special case.
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	4	frs3 floating point register.
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	4	frs3 floating point register.
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	5	frs3 floating point register (doube/even).
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	5	frs3 floating point register (doube/even).
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	g	frsd floating point register.
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	g	frsd floating point register.
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	H	frsd floating point register (double/even).
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	H	frsd floating point register (double/even).
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	J	frsd floating point register (quad/multiple of 4).
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	J	frsd floating point register (quad/multiple of 4).
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	}       frsd floating point register (double/even) that is == frs2
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	b	crs1 coprocessor register
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	b	crs1 coprocessor register
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	c	crs2 coprocessor register
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	c	crs2 coprocessor register
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	D	crsd coprocessor register
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	D	crsd coprocessor register
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	m	alternate space register (asr) in rd
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	m	alternate space register (asr) in rd
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	M	alternate space register (asr) in rs1
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	M	alternate space register (asr) in rs1
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	U	sparclet coprocessor registers in rs1 position
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	U	sparclet coprocessor registers in rs1 position
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	E	%ccr. (v9)
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	E	%ccr. (v9)
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	s	%fprs. (v9)
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	s	%fprs. (v9)
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	P	%pc.  (v9)
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	P	%pc.  (v9)
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	W	%tick.	(v9)
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	W	%tick.	(v9)
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	{	%mcdper. (v9b)
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	o	%asi. (v9)
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	o	%asi. (v9)
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	6	%fcc0. (v9)
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	6	%fcc0. (v9)
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	7	%fcc1. (v9)
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	7	%fcc1. (v9)
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	8	%fcc2. (v9)
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	8	%fcc2. (v9)
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	9	%fcc3. (v9)
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	9	%fcc3. (v9)