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| 1 | /* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table |
1 | /* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table |
| 2 | Copyright 1999, 2000, 2002, 2003, 2010, 2012 |
- | |
| 3 | Free Software Foundation, Inc. |
2 | Copyright (C) 1999-2015 Free Software Foundation, Inc. |
| 4 | Written by Stephane Carrez (stcarrez@nerim.fr) |
3 | Written by Stephane Carrez (stcarrez@nerim.fr) |
| 5 | 4 | ||
| 6 | This file is part of GDB, GAS, and the GNU binutils. |
5 | This file is part of GDB, GAS, and the GNU binutils. |
| 7 | 6 | ||
| 8 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
7 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
| 9 | them and/or modify them under the terms of the GNU General Public |
8 | them and/or modify them under the terms of the GNU General Public |
| 10 | License as published by the Free Software Foundation; either version 3, |
9 | License as published by the Free Software Foundation; either version 3, |
| 11 | or (at your option) any later version. |
10 | or (at your option) any later version. |
| 12 | 11 | ||
| 13 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
| 14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
| 15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
| 16 | the GNU General Public License for more details. |
15 | the GNU General Public License for more details. |
| 17 | 16 | ||
| 18 | You should have received a copy of the GNU General Public License |
17 | You should have received a copy of the GNU General Public License |
| 19 | along with this file; see the file COPYING3. If not, write to the Free |
18 | along with this file; see the file COPYING3. If not, write to the Free |
| 20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| 21 | MA 02110-1301, USA. */ |
20 | MA 02110-1301, USA. */ |
| 22 | 21 | ||
| 23 | #ifndef _OPCODE_M68HC11_H |
22 | #ifndef _OPCODE_M68HC11_H |
| 24 | #define _OPCODE_M68HC11_H |
23 | #define _OPCODE_M68HC11_H |
| 25 | 24 | ||
| 26 | /* Flags for the definition of the 68HC11 & 68HC12 CCR. */ |
25 | /* Flags for the definition of the 68HC11 & 68HC12 CCR. */ |
| 27 | #define M6811_S_BIT 0x80 /* Stop disable */ |
26 | #define M6811_S_BIT 0x80 /* Stop disable */ |
| 28 | #define M6811_X_BIT 0x40 /* X-interrupt mask */ |
27 | #define M6811_X_BIT 0x40 /* X-interrupt mask */ |
| 29 | #define M6811_H_BIT 0x20 /* Half carry flag */ |
28 | #define M6811_H_BIT 0x20 /* Half carry flag */ |
| 30 | #define M6811_I_BIT 0x10 /* I-interrupt mask */ |
29 | #define M6811_I_BIT 0x10 /* I-interrupt mask */ |
| 31 | #define M6811_N_BIT 0x08 /* Negative */ |
30 | #define M6811_N_BIT 0x08 /* Negative */ |
| 32 | #define M6811_Z_BIT 0x04 /* Zero */ |
31 | #define M6811_Z_BIT 0x04 /* Zero */ |
| 33 | #define M6811_V_BIT 0x02 /* Overflow */ |
32 | #define M6811_V_BIT 0x02 /* Overflow */ |
| 34 | #define M6811_C_BIT 0x01 /* Carry */ |
33 | #define M6811_C_BIT 0x01 /* Carry */ |
| 35 | 34 | ||
| 36 | /* 68HC11 register address offsets (range 0..0x3F or 0..64). |
35 | /* 68HC11 register address offsets (range 0..0x3F or 0..64). |
| 37 | The absolute address of the I/O register depends on the setting |
36 | The absolute address of the I/O register depends on the setting |
| 38 | of the M6811_INIT register. At init time, the I/O registers are |
37 | of the M6811_INIT register. At init time, the I/O registers are |
| 39 | mapped at 0x1000. Address of registers is then: |
38 | mapped at 0x1000. Address of registers is then: |
| 40 | 39 | ||
| 41 | 0x1000 + M6811_xxx. */ |
40 | 0x1000 + M6811_xxx. */ |
| 42 | #define M6811_PORTA 0x00 /* Port A register */ |
41 | #define M6811_PORTA 0x00 /* Port A register */ |
| 43 | #define M6811__RES1 0x01 /* Unused/Reserved */ |
42 | #define M6811__RES1 0x01 /* Unused/Reserved */ |
| 44 | #define M6811_PIOC 0x02 /* Parallel I/O Control register */ |
43 | #define M6811_PIOC 0x02 /* Parallel I/O Control register */ |
| 45 | #define M6811_PORTC 0x03 /* Port C register */ |
44 | #define M6811_PORTC 0x03 /* Port C register */ |
| 46 | #define M6811_PORTB 0x04 /* Port B register */ |
45 | #define M6811_PORTB 0x04 /* Port B register */ |
| 47 | #define M6811_PORTCL 0x05 /* Alternate latched port C */ |
46 | #define M6811_PORTCL 0x05 /* Alternate latched port C */ |
| 48 | #define M6811__RES6 0x06 /* Unused/Reserved */ |
47 | #define M6811__RES6 0x06 /* Unused/Reserved */ |
| 49 | #define M6811_DDRC 0x07 /* Data direction register for port C */ |
48 | #define M6811_DDRC 0x07 /* Data direction register for port C */ |
| 50 | #define M6811_PORTD 0x08 /* Port D register */ |
49 | #define M6811_PORTD 0x08 /* Port D register */ |
| 51 | #define M6811_DDRD 0x09 /* Data direction register for port D */ |
50 | #define M6811_DDRD 0x09 /* Data direction register for port D */ |
| 52 | #define M6811_PORTE 0x0A /* Port E input register */ |
51 | #define M6811_PORTE 0x0A /* Port E input register */ |
| 53 | #define M6811_CFORC 0x0B /* Compare Force Register */ |
52 | #define M6811_CFORC 0x0B /* Compare Force Register */ |
| 54 | #define M6811_OC1M 0x0C /* OC1 Action Mask register */ |
53 | #define M6811_OC1M 0x0C /* OC1 Action Mask register */ |
| 55 | #define M6811_OC1D 0x0D /* OC1 Action Data register */ |
54 | #define M6811_OC1D 0x0D /* OC1 Action Data register */ |
| 56 | #define M6811_TCTN 0x0E /* Timer Counter Register */ |
55 | #define M6811_TCTN 0x0E /* Timer Counter Register */ |
| 57 | #define M6811_TCTN_H 0x0E /* " " " High part */ |
56 | #define M6811_TCTN_H 0x0E /* " " " High part */ |
| 58 | #define M6811_TCTN_L 0x0F /* " " " Low part */ |
57 | #define M6811_TCTN_L 0x0F /* " " " Low part */ |
| 59 | #define M6811_TIC1 0x10 /* Input capture 1 register */ |
58 | #define M6811_TIC1 0x10 /* Input capture 1 register */ |
| 60 | #define M6811_TIC1_H 0x10 /* " " " High part */ |
59 | #define M6811_TIC1_H 0x10 /* " " " High part */ |
| 61 | #define M6811_TIC1_L 0x11 /* " " " Low part */ |
60 | #define M6811_TIC1_L 0x11 /* " " " Low part */ |
| 62 | #define M6811_TIC2 0x12 /* Input capture 2 register */ |
61 | #define M6811_TIC2 0x12 /* Input capture 2 register */ |
| 63 | #define M6811_TIC2_H 0x12 /* " " " High part */ |
62 | #define M6811_TIC2_H 0x12 /* " " " High part */ |
| 64 | #define M6811_TIC2_L 0x13 /* " " " Low part */ |
63 | #define M6811_TIC2_L 0x13 /* " " " Low part */ |
| 65 | #define M6811_TIC3 0x14 /* Input capture 3 register */ |
64 | #define M6811_TIC3 0x14 /* Input capture 3 register */ |
| 66 | #define M6811_TIC3_H 0x14 /* " " " High part */ |
65 | #define M6811_TIC3_H 0x14 /* " " " High part */ |
| 67 | #define M6811_TIC3_L 0x15 /* " " " Low part */ |
66 | #define M6811_TIC3_L 0x15 /* " " " Low part */ |
| 68 | #define M6811_TOC1 0x16 /* Output Compare 1 register */ |
67 | #define M6811_TOC1 0x16 /* Output Compare 1 register */ |
| 69 | #define M6811_TOC1_H 0x16 /* " " " High part */ |
68 | #define M6811_TOC1_H 0x16 /* " " " High part */ |
| 70 | #define M6811_TOC1_L 0x17 /* " " " Low part */ |
69 | #define M6811_TOC1_L 0x17 /* " " " Low part */ |
| 71 | #define M6811_TOC2 0x18 /* Output Compare 2 register */ |
70 | #define M6811_TOC2 0x18 /* Output Compare 2 register */ |
| 72 | #define M6811_TOC2_H 0x18 /* " " " High part */ |
71 | #define M6811_TOC2_H 0x18 /* " " " High part */ |
| 73 | #define M6811_TOC2_L 0x19 /* " " " Low part */ |
72 | #define M6811_TOC2_L 0x19 /* " " " Low part */ |
| 74 | #define M6811_TOC3 0x1A /* Output Compare 3 register */ |
73 | #define M6811_TOC3 0x1A /* Output Compare 3 register */ |
| 75 | #define M6811_TOC3_H 0x1A /* " " " High part */ |
74 | #define M6811_TOC3_H 0x1A /* " " " High part */ |
| 76 | #define M6811_TOC3_L 0x1B /* " " " Low part */ |
75 | #define M6811_TOC3_L 0x1B /* " " " Low part */ |
| 77 | #define M6811_TOC4 0x1C /* Output Compare 4 register */ |
76 | #define M6811_TOC4 0x1C /* Output Compare 4 register */ |
| 78 | #define M6811_TOC4_H 0x1C /* " " " High part */ |
77 | #define M6811_TOC4_H 0x1C /* " " " High part */ |
| 79 | #define M6811_TOC4_L 0x1D /* " " " Low part */ |
78 | #define M6811_TOC4_L 0x1D /* " " " Low part */ |
| 80 | #define M6811_TOC5 0x1E /* Output Compare 5 register */ |
79 | #define M6811_TOC5 0x1E /* Output Compare 5 register */ |
| 81 | #define M6811_TOC5_H 0x1E /* " " " High part */ |
80 | #define M6811_TOC5_H 0x1E /* " " " High part */ |
| 82 | #define M6811_TOC5_L 0x1F /* " " " Low part */ |
81 | #define M6811_TOC5_L 0x1F /* " " " Low part */ |
| 83 | #define M6811_TCTL1 0x20 /* Timer Control register 1 */ |
82 | #define M6811_TCTL1 0x20 /* Timer Control register 1 */ |
| 84 | #define M6811_TCTL2 0x21 /* Timer Control register 2 */ |
83 | #define M6811_TCTL2 0x21 /* Timer Control register 2 */ |
| 85 | #define M6811_TMSK1 0x22 /* Timer Interrupt Mask Register 1 */ |
84 | #define M6811_TMSK1 0x22 /* Timer Interrupt Mask Register 1 */ |
| 86 | #define M6811_TFLG1 0x23 /* Timer Interrupt Flag Register 1 */ |
85 | #define M6811_TFLG1 0x23 /* Timer Interrupt Flag Register 1 */ |
| 87 | #define M6811_TMSK2 0x24 /* Timer Interrupt Mask Register 2 */ |
86 | #define M6811_TMSK2 0x24 /* Timer Interrupt Mask Register 2 */ |
| 88 | #define M6811_TFLG2 0x25 /* Timer Interrupt Flag Register 2 */ |
87 | #define M6811_TFLG2 0x25 /* Timer Interrupt Flag Register 2 */ |
| 89 | #define M6811_PACTL 0x26 /* Pulse Accumulator Control Register */ |
88 | #define M6811_PACTL 0x26 /* Pulse Accumulator Control Register */ |
| 90 | #define M6811_PACNT 0x27 /* Pulse Accumulator Count Register */ |
89 | #define M6811_PACNT 0x27 /* Pulse Accumulator Count Register */ |
| 91 | #define M6811_SPCR 0x28 /* SPI Control register */ |
90 | #define M6811_SPCR 0x28 /* SPI Control register */ |
| 92 | #define M6811_SPSR 0x29 /* SPI Status register */ |
91 | #define M6811_SPSR 0x29 /* SPI Status register */ |
| 93 | #define M6811_SPDR 0x2A /* SPI Data register */ |
92 | #define M6811_SPDR 0x2A /* SPI Data register */ |
| 94 | #define M6811_BAUD 0x2B /* SCI Baud register */ |
93 | #define M6811_BAUD 0x2B /* SCI Baud register */ |
| 95 | #define M6811_SCCR1 0x2C /* SCI Control register 1 */ |
94 | #define M6811_SCCR1 0x2C /* SCI Control register 1 */ |
| 96 | #define M6811_SCCR2 0x2D /* SCI Control register 2 */ |
95 | #define M6811_SCCR2 0x2D /* SCI Control register 2 */ |
| 97 | #define M6811_SCSR 0x2E /* SCI Status register */ |
96 | #define M6811_SCSR 0x2E /* SCI Status register */ |
| 98 | #define M6811_SCDR 0x2F /* SCI Data (Read => RDR, Write => TDR) */ |
97 | #define M6811_SCDR 0x2F /* SCI Data (Read => RDR, Write => TDR) */ |
| 99 | #define M6811_ADCTL 0x30 /* A/D Control register */ |
98 | #define M6811_ADCTL 0x30 /* A/D Control register */ |
| 100 | #define M6811_ADR1 0x31 /* A/D, Analog Result register 1 */ |
99 | #define M6811_ADR1 0x31 /* A/D, Analog Result register 1 */ |
| 101 | #define M6811_ADR2 0x32 /* A/D, Analog Result register 2 */ |
100 | #define M6811_ADR2 0x32 /* A/D, Analog Result register 2 */ |
| 102 | #define M6811_ADR3 0x33 /* A/D, Analog Result register 3 */ |
101 | #define M6811_ADR3 0x33 /* A/D, Analog Result register 3 */ |
| 103 | #define M6811_ADR4 0x34 /* A/D, Analog Result register 4 */ |
102 | #define M6811_ADR4 0x34 /* A/D, Analog Result register 4 */ |
| 104 | #define M6811__RES35 0x35 |
103 | #define M6811__RES35 0x35 |
| 105 | #define M6811__RES36 0x36 |
104 | #define M6811__RES36 0x36 |
| 106 | #define M6811__RES37 0x37 |
105 | #define M6811__RES37 0x37 |
| 107 | #define M6811__RES38 0x38 |
106 | #define M6811__RES38 0x38 |
| 108 | #define M6811_OPTION 0x39 /* System Configuration Options */ |
107 | #define M6811_OPTION 0x39 /* System Configuration Options */ |
| 109 | #define M6811_COPRST 0x3A /* Arm/Reset COP Timer Circuitry */ |
108 | #define M6811_COPRST 0x3A /* Arm/Reset COP Timer Circuitry */ |
| 110 | #define M6811_PPROG 0x3B /* EEPROM Programming Control Register */ |
109 | #define M6811_PPROG 0x3B /* EEPROM Programming Control Register */ |
| 111 | #define M6811_HPRIO 0x3C /* Highest priority I-Bit int and misc */ |
110 | #define M6811_HPRIO 0x3C /* Highest priority I-Bit int and misc */ |
| 112 | #define M6811_INIT 0x3D /* Ram and I/O mapping register */ |
111 | #define M6811_INIT 0x3D /* Ram and I/O mapping register */ |
| 113 | #define M6811_TEST1 0x3E /* Factory test control register */ |
112 | #define M6811_TEST1 0x3E /* Factory test control register */ |
| 114 | #define M6811_CONFIG 0x3F /* COP, ROM and EEPROM enables */ |
113 | #define M6811_CONFIG 0x3F /* COP, ROM and EEPROM enables */ |
| 115 | 114 | ||
| 116 | 115 | ||
| 117 | /* Flags of the CONFIG register (in EEPROM). */ |
116 | /* Flags of the CONFIG register (in EEPROM). */ |
| 118 | #define M6811_NOSEC 0x08 /* Security mode disable */ |
117 | #define M6811_NOSEC 0x08 /* Security mode disable */ |
| 119 | #define M6811_NOCOP 0x04 /* COP system disable */ |
118 | #define M6811_NOCOP 0x04 /* COP system disable */ |
| 120 | #define M6811_ROMON 0x02 /* Enable on-chip rom */ |
119 | #define M6811_ROMON 0x02 /* Enable on-chip rom */ |
| 121 | #define M6811_EEON 0x01 /* Enable on-chip eeprom */ |
120 | #define M6811_EEON 0x01 /* Enable on-chip eeprom */ |
| 122 | 121 | ||
| 123 | /* Flags of the PPROG register. */ |
122 | /* Flags of the PPROG register. */ |
| 124 | #define M6811_BYTE 0x10 /* Byte mode */ |
123 | #define M6811_BYTE 0x10 /* Byte mode */ |
| 125 | #define M6811_ROW 0x08 /* Row mode */ |
124 | #define M6811_ROW 0x08 /* Row mode */ |
| 126 | #define M6811_ERASE 0x04 /* Erase mode select (1 = erase, 0 = read) */ |
125 | #define M6811_ERASE 0x04 /* Erase mode select (1 = erase, 0 = read) */ |
| 127 | #define M6811_EELAT 0x02 /* EEPROM Latch Control */ |
126 | #define M6811_EELAT 0x02 /* EEPROM Latch Control */ |
| 128 | #define M6811_EEPGM 0x01 /* EEPROM Programming Voltage Enable */ |
127 | #define M6811_EEPGM 0x01 /* EEPROM Programming Voltage Enable */ |
| 129 | 128 | ||
| 130 | /* Flags of the PIOC register. */ |
129 | /* Flags of the PIOC register. */ |
| 131 | #define M6811_STAF 0x80 /* Strobe A Interrupt Status Flag */ |
130 | #define M6811_STAF 0x80 /* Strobe A Interrupt Status Flag */ |
| 132 | #define M6811_STAI 0x40 /* Strobe A Interrupt Enable Mask */ |
131 | #define M6811_STAI 0x40 /* Strobe A Interrupt Enable Mask */ |
| 133 | #define M6811_CWOM 0x20 /* Port C Wire OR mode */ |
132 | #define M6811_CWOM 0x20 /* Port C Wire OR mode */ |
| 134 | #define M6811_HNDS 0x10 /* Handshake mode */ |
133 | #define M6811_HNDS 0x10 /* Handshake mode */ |
| 135 | #define M6811_OIN 0x08 /* Output or Input handshaking */ |
134 | #define M6811_OIN 0x08 /* Output or Input handshaking */ |
| 136 | #define M6811_PLS 0x04 /* Pulse/Interlocked Handshake Operation */ |
135 | #define M6811_PLS 0x04 /* Pulse/Interlocked Handshake Operation */ |
| 137 | #define M6811_EGA 0x02 /* Active Edge for Strobe A */ |
136 | #define M6811_EGA 0x02 /* Active Edge for Strobe A */ |
| 138 | #define M6811_INVB 0x01 /* Invert Strobe B */ |
137 | #define M6811_INVB 0x01 /* Invert Strobe B */ |
| 139 | 138 | ||
| 140 | /* Flags of the SCCR1 register. */ |
139 | /* Flags of the SCCR1 register. */ |
| 141 | #define M6811_R8 0x80 /* Receive Data bit 8 */ |
140 | #define M6811_R8 0x80 /* Receive Data bit 8 */ |
| 142 | #define M6811_T8 0x40 /* Transmit data bit 8 */ |
141 | #define M6811_T8 0x40 /* Transmit data bit 8 */ |
| 143 | #define M6811__SCCR1_5 0x20 /* Unused */ |
142 | #define M6811__SCCR1_5 0x20 /* Unused */ |
| 144 | #define M6811_M 0x10 /* SCI Character length */ |
143 | #define M6811_M 0x10 /* SCI Character length */ |
| 145 | #define M6811_WAKE 0x08 /* Wake up method select (0=idle, 1=addr mark) */ |
144 | #define M6811_WAKE 0x08 /* Wake up method select (0=idle, 1=addr mark) */ |
| 146 | 145 | ||
| 147 | /* Flags of the SCCR2 register. */ |
146 | /* Flags of the SCCR2 register. */ |
| 148 | #define M6811_TIE 0x80 /* Transmit Interrupt enable */ |
147 | #define M6811_TIE 0x80 /* Transmit Interrupt enable */ |
| 149 | #define M6811_TCIE 0x40 /* Transmit Complete Interrupt Enable */ |
148 | #define M6811_TCIE 0x40 /* Transmit Complete Interrupt Enable */ |
| 150 | #define M6811_RIE 0x20 /* Receive Interrupt Enable */ |
149 | #define M6811_RIE 0x20 /* Receive Interrupt Enable */ |
| 151 | #define M6811_ILIE 0x10 /* Idle Line Interrupt Enable */ |
150 | #define M6811_ILIE 0x10 /* Idle Line Interrupt Enable */ |
| 152 | #define M6811_TE 0x08 /* Transmit Enable */ |
151 | #define M6811_TE 0x08 /* Transmit Enable */ |
| 153 | #define M6811_RE 0x04 /* Receive Enable */ |
152 | #define M6811_RE 0x04 /* Receive Enable */ |
| 154 | #define M6811_RWU 0x02 /* Receiver Wake Up */ |
153 | #define M6811_RWU 0x02 /* Receiver Wake Up */ |
| 155 | #define M6811_SBK 0x01 /* Send Break */ |
154 | #define M6811_SBK 0x01 /* Send Break */ |
| 156 | 155 | ||
| 157 | /* Flags of the SCSR register. */ |
156 | /* Flags of the SCSR register. */ |
| 158 | #define M6811_TDRE 0x80 /* Transmit Data Register Empty */ |
157 | #define M6811_TDRE 0x80 /* Transmit Data Register Empty */ |
| 159 | #define M6811_TC 0x40 /* Transmit Complete */ |
158 | #define M6811_TC 0x40 /* Transmit Complete */ |
| 160 | #define M6811_RDRF 0x20 /* Receive Data Register Full */ |
159 | #define M6811_RDRF 0x20 /* Receive Data Register Full */ |
| 161 | #define M6811_IDLE 0x10 /* Idle Line Detect */ |
160 | #define M6811_IDLE 0x10 /* Idle Line Detect */ |
| 162 | #define M6811_OR 0x08 /* Overrun Error */ |
161 | #define M6811_OR 0x08 /* Overrun Error */ |
| 163 | #define M6811_NF 0x04 /* Noise Flag */ |
162 | #define M6811_NF 0x04 /* Noise Flag */ |
| 164 | #define M6811_FE 0x02 /* Framing Error */ |
163 | #define M6811_FE 0x02 /* Framing Error */ |
| 165 | #define M6811__SCSR_0 0x01 /* Unused */ |
164 | #define M6811__SCSR_0 0x01 /* Unused */ |
| 166 | 165 | ||
| 167 | /* Flags of the BAUD register. */ |
166 | /* Flags of the BAUD register. */ |
| 168 | #define M6811_TCLR 0x80 /* Clear Baud Rate (TEST mode) */ |
167 | #define M6811_TCLR 0x80 /* Clear Baud Rate (TEST mode) */ |
| 169 | #define M6811__BAUD_6 0x40 /* Not used */ |
168 | #define M6811__BAUD_6 0x40 /* Not used */ |
| 170 | #define M6811_SCP1 0x20 /* SCI Baud rate prescaler select */ |
169 | #define M6811_SCP1 0x20 /* SCI Baud rate prescaler select */ |
| 171 | #define M6811_SCP0 0x10 |
170 | #define M6811_SCP0 0x10 |
| 172 | #define M6811_RCKB 0x08 /* Baud Rate Clock Check (TEST mode) */ |
171 | #define M6811_RCKB 0x08 /* Baud Rate Clock Check (TEST mode) */ |
| 173 | #define M6811_SCR2 0x04 /* SCI Baud rate select */ |
172 | #define M6811_SCR2 0x04 /* SCI Baud rate select */ |
| 174 | #define M6811_SCR1 0x02 |
173 | #define M6811_SCR1 0x02 |
| 175 | #define M6811_SCR0 0x01 |
174 | #define M6811_SCR0 0x01 |
| 176 | 175 | ||
| 177 | #define M6811_BAUD_DIV_1 (0) |
176 | #define M6811_BAUD_DIV_1 (0) |
| 178 | #define M6811_BAUD_DIV_3 (M6811_SCP0) |
177 | #define M6811_BAUD_DIV_3 (M6811_SCP0) |
| 179 | #define M6811_BAUD_DIV_4 (M6811_SCP1) |
178 | #define M6811_BAUD_DIV_4 (M6811_SCP1) |
| 180 | #define M6811_BAUD_DIV_13 (M6811_SCP1|M6811_SCP0) |
179 | #define M6811_BAUD_DIV_13 (M6811_SCP1|M6811_SCP0) |
| 181 | 180 | ||
| 182 | /* Flags of the SPCR register. */ |
181 | /* Flags of the SPCR register. */ |
| 183 | #define M6811_SPIE 0x80 /* Serial Peripheral Interrupt Enable */ |
182 | #define M6811_SPIE 0x80 /* Serial Peripheral Interrupt Enable */ |
| 184 | #define M6811_SPE 0x40 /* Serial Peripheral System Enable */ |
183 | #define M6811_SPE 0x40 /* Serial Peripheral System Enable */ |
| 185 | #define M6811_DWOM 0x20 /* Port D Wire-OR mode option */ |
184 | #define M6811_DWOM 0x20 /* Port D Wire-OR mode option */ |
| 186 | #define M6811_MSTR 0x10 /* Master Mode Select */ |
185 | #define M6811_MSTR 0x10 /* Master Mode Select */ |
| 187 | #define M6811_CPOL 0x08 /* Clock Polarity */ |
186 | #define M6811_CPOL 0x08 /* Clock Polarity */ |
| 188 | #define M6811_CPHA 0x04 /* Clock Phase */ |
187 | #define M6811_CPHA 0x04 /* Clock Phase */ |
| 189 | #define M6811_SPR1 0x02 /* SPI Clock Rate Select */ |
188 | #define M6811_SPR1 0x02 /* SPI Clock Rate Select */ |
| 190 | #define M6811_SPR0 0x01 |
189 | #define M6811_SPR0 0x01 |
| 191 | 190 | ||
| 192 | /* Flags of the SPSR register. */ |
191 | /* Flags of the SPSR register. */ |
| 193 | #define M6811_SPIF 0x80 /* SPI Transfer Complete flag */ |
192 | #define M6811_SPIF 0x80 /* SPI Transfer Complete flag */ |
| 194 | #define M6811_WCOL 0x40 /* Write Collision */ |
193 | #define M6811_WCOL 0x40 /* Write Collision */ |
| 195 | #define M6811_MODF 0x10 /* Mode Fault */ |
194 | #define M6811_MODF 0x10 /* Mode Fault */ |
| 196 | 195 | ||
| 197 | /* Flags of the ADCTL register. */ |
196 | /* Flags of the ADCTL register. */ |
| 198 | #define M6811_CCF 0x80 /* Conversions Complete Flag */ |
197 | #define M6811_CCF 0x80 /* Conversions Complete Flag */ |
| 199 | #define M6811_SCAN 0x20 /* Continuous Scan Control */ |
198 | #define M6811_SCAN 0x20 /* Continuous Scan Control */ |
| 200 | #define M6811_MULT 0x10 /* Multiple Channel/Single Channel Control */ |
199 | #define M6811_MULT 0x10 /* Multiple Channel/Single Channel Control */ |
| 201 | #define M6811_CD 0x08 /* Channel Select D */ |
200 | #define M6811_CD 0x08 /* Channel Select D */ |
| 202 | #define M6811_CC 0x04 /* C */ |
201 | #define M6811_CC 0x04 /* C */ |
| 203 | #define M6811_CB 0x02 /* B */ |
202 | #define M6811_CB 0x02 /* B */ |
| 204 | #define M6811_CA 0x01 /* A */ |
203 | #define M6811_CA 0x01 /* A */ |
| 205 | 204 | ||
| 206 | /* Flags of the CFORC register. */ |
205 | /* Flags of the CFORC register. */ |
| 207 | #define M6811_FOC1 0x80 /* Force Output Compare 1 */ |
206 | #define M6811_FOC1 0x80 /* Force Output Compare 1 */ |
| 208 | #define M6811_FOC2 0x40 /* 2 */ |
207 | #define M6811_FOC2 0x40 /* 2 */ |
| 209 | #define M6811_FOC3 0x20 /* 3 */ |
208 | #define M6811_FOC3 0x20 /* 3 */ |
| 210 | #define M6811_FOC4 0x10 /* 4 */ |
209 | #define M6811_FOC4 0x10 /* 4 */ |
| 211 | #define M6811_FOC5 0x08 /* 5 */ |
210 | #define M6811_FOC5 0x08 /* 5 */ |
| 212 | 211 | ||
| 213 | /* Flags of the OC1M register. */ |
212 | /* Flags of the OC1M register. */ |
| 214 | #define M6811_OC1M7 0x80 /* Output Compare 7 */ |
213 | #define M6811_OC1M7 0x80 /* Output Compare 7 */ |
| 215 | #define M6811_OC1M6 0x40 /* 6 */ |
214 | #define M6811_OC1M6 0x40 /* 6 */ |
| 216 | #define M6811_OC1M5 0x20 /* 5 */ |
215 | #define M6811_OC1M5 0x20 /* 5 */ |
| 217 | #define M6811_OC1M4 0x10 /* 4 */ |
216 | #define M6811_OC1M4 0x10 /* 4 */ |
| 218 | #define M6811_OC1M3 0x08 /* 3 */ |
217 | #define M6811_OC1M3 0x08 /* 3 */ |
| 219 | 218 | ||
| 220 | /* Flags of the OC1D register. */ |
219 | /* Flags of the OC1D register. */ |
| 221 | #define M6811_OC1D7 0x80 |
220 | #define M6811_OC1D7 0x80 |
| 222 | #define M6811_OC1D6 0x40 |
221 | #define M6811_OC1D6 0x40 |
| 223 | #define M6811_OC1D5 0x20 |
222 | #define M6811_OC1D5 0x20 |
| 224 | #define M6811_OC1D4 0x10 |
223 | #define M6811_OC1D4 0x10 |
| 225 | #define M6811_OC1D3 0x08 |
224 | #define M6811_OC1D3 0x08 |
| 226 | 225 | ||
| 227 | /* Flags of the TCTL1 register. */ |
226 | /* Flags of the TCTL1 register. */ |
| 228 | #define M6811_OM2 0x80 /* Output Mode 2 */ |
227 | #define M6811_OM2 0x80 /* Output Mode 2 */ |
| 229 | #define M6811_OL2 0x40 /* Output Level 2 */ |
228 | #define M6811_OL2 0x40 /* Output Level 2 */ |
| 230 | #define M6811_OM3 0x20 |
229 | #define M6811_OM3 0x20 |
| 231 | #define M6811_OL3 0x10 |
230 | #define M6811_OL3 0x10 |
| 232 | #define M6811_OM4 0x08 |
231 | #define M6811_OM4 0x08 |
| 233 | #define M6811_OL4 0x04 |
232 | #define M6811_OL4 0x04 |
| 234 | #define M6811_OM5 0x02 |
233 | #define M6811_OM5 0x02 |
| 235 | #define M6811_OL5 0x01 |
234 | #define M6811_OL5 0x01 |
| 236 | 235 | ||
| 237 | /* Flags of the TCTL2 register. */ |
236 | /* Flags of the TCTL2 register. */ |
| 238 | #define M6811_EDG1B 0x20 /* Input Edge Capture Control 1 */ |
237 | #define M6811_EDG1B 0x20 /* Input Edge Capture Control 1 */ |
| 239 | #define M6811_EDG1A 0x10 |
238 | #define M6811_EDG1A 0x10 |
| 240 | #define M6811_EDG2B 0x08 /* Input 2 */ |
239 | #define M6811_EDG2B 0x08 /* Input 2 */ |
| 241 | #define M6811_EDG2A 0x04 |
240 | #define M6811_EDG2A 0x04 |
| 242 | #define M6811_EDG3B 0x02 /* Input 3 */ |
241 | #define M6811_EDG3B 0x02 /* Input 3 */ |
| 243 | #define M6811_EDG3A 0x01 |
242 | #define M6811_EDG3A 0x01 |
| 244 | 243 | ||
| 245 | /* Flags of the TMSK1 register. */ |
244 | /* Flags of the TMSK1 register. */ |
| 246 | #define M6811_OC1I 0x80 /* Output Compare 1 Interrupt */ |
245 | #define M6811_OC1I 0x80 /* Output Compare 1 Interrupt */ |
| 247 | #define M6811_OC2I 0x40 /* 2 */ |
246 | #define M6811_OC2I 0x40 /* 2 */ |
| 248 | #define M6811_OC3I 0x20 /* 3 */ |
247 | #define M6811_OC3I 0x20 /* 3 */ |
| 249 | #define M6811_OC4I 0x10 /* 4 */ |
248 | #define M6811_OC4I 0x10 /* 4 */ |
| 250 | #define M6811_OC5I 0x08 /* 5 */ |
249 | #define M6811_OC5I 0x08 /* 5 */ |
| 251 | #define M6811_IC1I 0x04 /* Input Capture 1 Interrupt */ |
250 | #define M6811_IC1I 0x04 /* Input Capture 1 Interrupt */ |
| 252 | #define M6811_IC2I 0x02 /* 2 */ |
251 | #define M6811_IC2I 0x02 /* 2 */ |
| 253 | #define M6811_IC3I 0x01 /* 3 */ |
252 | #define M6811_IC3I 0x01 /* 3 */ |
| 254 | 253 | ||
| 255 | /* Flags of the TFLG1 register. */ |
254 | /* Flags of the TFLG1 register. */ |
| 256 | #define M6811_OC1F 0x80 /* Output Compare 1 Flag */ |
255 | #define M6811_OC1F 0x80 /* Output Compare 1 Flag */ |
| 257 | #define M6811_OC2F 0x40 /* 2 */ |
256 | #define M6811_OC2F 0x40 /* 2 */ |
| 258 | #define M6811_OC3F 0x20 /* 3 */ |
257 | #define M6811_OC3F 0x20 /* 3 */ |
| 259 | #define M6811_OC4F 0x10 /* 4 */ |
258 | #define M6811_OC4F 0x10 /* 4 */ |
| 260 | #define M6811_OC5F 0x08 /* 5 */ |
259 | #define M6811_OC5F 0x08 /* 5 */ |
| 261 | #define M6811_IC1F 0x04 /* Input Capture 1 Flag */ |
260 | #define M6811_IC1F 0x04 /* Input Capture 1 Flag */ |
| 262 | #define M6811_IC2F 0x02 /* 2 */ |
261 | #define M6811_IC2F 0x02 /* 2 */ |
| 263 | #define M6811_IC3F 0x01 /* 3 */ |
262 | #define M6811_IC3F 0x01 /* 3 */ |
| 264 | 263 | ||
| 265 | /* Flags of Timer Interrupt Mask Register 2 (TMSK2). */ |
264 | /* Flags of Timer Interrupt Mask Register 2 (TMSK2). */ |
| 266 | #define M6811_TOI 0x80 /* Timer Overflow Interrupt Enable */ |
265 | #define M6811_TOI 0x80 /* Timer Overflow Interrupt Enable */ |
| 267 | #define M6811_RTII 0x40 /* RTI Interrupt Enable */ |
266 | #define M6811_RTII 0x40 /* RTI Interrupt Enable */ |
| 268 | #define M6811_PAOVI 0x20 /* Pulse Accumulator Overflow Interrupt En. */ |
267 | #define M6811_PAOVI 0x20 /* Pulse Accumulator Overflow Interrupt En. */ |
| 269 | #define M6811_PAII 0x10 /* Pulse Accumulator Interrupt Enable */ |
268 | #define M6811_PAII 0x10 /* Pulse Accumulator Interrupt Enable */ |
| 270 | #define M6811_PR1 0x02 /* Timer prescaler */ |
269 | #define M6811_PR1 0x02 /* Timer prescaler */ |
| 271 | #define M6811_PR0 0x01 /* Timer prescaler */ |
270 | #define M6811_PR0 0x01 /* Timer prescaler */ |
| 272 | #define M6811_TPR_1 0x00 /* " " prescale div 1 */ |
271 | #define M6811_TPR_1 0x00 /* " " prescale div 1 */ |
| 273 | #define M6811_TPR_4 0x01 /* " " prescale div 4 */ |
272 | #define M6811_TPR_4 0x01 /* " " prescale div 4 */ |
| 274 | #define M6811_TPR_8 0x02 /* " " prescale div 8 */ |
273 | #define M6811_TPR_8 0x02 /* " " prescale div 8 */ |
| 275 | #define M6811_TPR_16 0x03 /* " " prescale div 16 */ |
274 | #define M6811_TPR_16 0x03 /* " " prescale div 16 */ |
| 276 | 275 | ||
| 277 | /* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2). */ |
276 | /* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2). */ |
| 278 | #define M6811_TOF 0x80 /* Timer overflow bit */ |
277 | #define M6811_TOF 0x80 /* Timer overflow bit */ |
| 279 | #define M6811_RTIF 0x40 /* Read time interrupt flag */ |
278 | #define M6811_RTIF 0x40 /* Read time interrupt flag */ |
| 280 | #define M6811_PAOVF 0x20 /* Pulse accumulator overflow Interrupt flag */ |
279 | #define M6811_PAOVF 0x20 /* Pulse accumulator overflow Interrupt flag */ |
| 281 | #define M6811_PAIF 0x10 /* Pulse accumulator Input Edge " " " */ |
280 | #define M6811_PAIF 0x10 /* Pulse accumulator Input Edge " " " */ |
| 282 | 281 | ||
| 283 | /* Flags of Pulse Accumulator Control Register (PACTL). */ |
282 | /* Flags of Pulse Accumulator Control Register (PACTL). */ |
| 284 | #define M6811_DDRA7 0x80 /* Data direction for port A bit 7 */ |
283 | #define M6811_DDRA7 0x80 /* Data direction for port A bit 7 */ |
| 285 | #define M6811_PAEN 0x40 /* Pulse accumulator system enable */ |
284 | #define M6811_PAEN 0x40 /* Pulse accumulator system enable */ |
| 286 | #define M6811_PAMOD 0x20 /* Pulse accumulator mode */ |
285 | #define M6811_PAMOD 0x20 /* Pulse accumulator mode */ |
| 287 | #define M6811_PEDGE 0x10 /* Pulse accumulator edge control */ |
286 | #define M6811_PEDGE 0x10 /* Pulse accumulator edge control */ |
| 288 | #define M6811_RTR1 0x02 /* RTI Interrupt rates select */ |
287 | #define M6811_RTR1 0x02 /* RTI Interrupt rates select */ |
| 289 | #define M6811_RTR0 0x01 /* " " " " */ |
288 | #define M6811_RTR0 0x01 /* " " " " */ |
| 290 | 289 | ||
| 291 | /* Flags of the Options register. */ |
290 | /* Flags of the Options register. */ |
| 292 | #define M6811_ADPU 0x80 /* A/D Powerup */ |
291 | #define M6811_ADPU 0x80 /* A/D Powerup */ |
| 293 | #define M6811_CSEL 0x40 /* A/D/EE Charge pump clock source select */ |
292 | #define M6811_CSEL 0x40 /* A/D/EE Charge pump clock source select */ |
| 294 | #define M6811_IRQE 0x20 /* IRQ Edge/Level sensitive */ |
293 | #define M6811_IRQE 0x20 /* IRQ Edge/Level sensitive */ |
| 295 | #define M6811_DLY 0x10 /* Stop exit turn on delay */ |
294 | #define M6811_DLY 0x10 /* Stop exit turn on delay */ |
| 296 | #define M6811_CME 0x08 /* Clock Monitor enable */ |
295 | #define M6811_CME 0x08 /* Clock Monitor enable */ |
| 297 | #define M6811_CR1 0x02 /* COP timer rate select */ |
296 | #define M6811_CR1 0x02 /* COP timer rate select */ |
| 298 | #define M6811_CR0 0x01 /* COP timer rate select */ |
297 | #define M6811_CR0 0x01 /* COP timer rate select */ |
| 299 | 298 | ||
| 300 | /* Flags of the HPRIO register. */ |
299 | /* Flags of the HPRIO register. */ |
| 301 | #define M6811_RBOOT 0x80 /* Read Bootstrap ROM */ |
300 | #define M6811_RBOOT 0x80 /* Read Bootstrap ROM */ |
| 302 | #define M6811_SMOD 0x40 /* Special Mode */ |
301 | #define M6811_SMOD 0x40 /* Special Mode */ |
| 303 | #define M6811_MDA 0x20 /* Mode Select A */ |
302 | #define M6811_MDA 0x20 /* Mode Select A */ |
| 304 | #define M6811_IRV 0x10 /* Internal Read Visibility */ |
303 | #define M6811_IRV 0x10 /* Internal Read Visibility */ |
| 305 | #define M6811_PSEL3 0x08 /* Priority Select */ |
304 | #define M6811_PSEL3 0x08 /* Priority Select */ |
| 306 | #define M6811_PSEL2 0x04 |
305 | #define M6811_PSEL2 0x04 |
| 307 | #define M6811_PSEL1 0x02 |
306 | #define M6811_PSEL1 0x02 |
| 308 | #define M6811_PSEL0 0x01 |
307 | #define M6811_PSEL0 0x01 |
| 309 | 308 | ||
| 310 | /* Some insns used by gas to turn relative branches into absolute ones. */ |
309 | /* Some insns used by gas to turn relative branches into absolute ones. */ |
| 311 | #define M6811_BRA 0x20 |
310 | #define M6811_BRA 0x20 |
| 312 | #define M6811_JMP 0x7e |
311 | #define M6811_JMP 0x7e |
| 313 | #define M6811_BSR 0x8d |
312 | #define M6811_BSR 0x8d |
| 314 | #define M6811_JSR 0xbd |
313 | #define M6811_JSR 0xbd |
| 315 | #define M6812_JMP 0x06 |
314 | #define M6812_JMP 0x06 |
| 316 | #define M6812_BSR 0x07 |
315 | #define M6812_BSR 0x07 |
| 317 | #define M6812_JSR 0x16 |
316 | #define M6812_JSR 0x16 |
| 318 | 317 | ||
| 319 | /* Instruction code pages. Code page 1 is the default. */ |
318 | /* Instruction code pages. Code page 1 is the default. */ |
| 320 | /*#define M6811_OPCODE_PAGE1 0x00*/ |
319 | /*#define M6811_OPCODE_PAGE1 0x00*/ |
| 321 | #define M6811_OPCODE_PAGE2 0x18 |
320 | #define M6811_OPCODE_PAGE2 0x18 |
| 322 | #define M6811_OPCODE_PAGE3 0x1A |
321 | #define M6811_OPCODE_PAGE3 0x1A |
| 323 | #define M6811_OPCODE_PAGE4 0xCD |
322 | #define M6811_OPCODE_PAGE4 0xCD |
| 324 | 323 | ||
| 325 | 324 | ||
| 326 | /* 68HC11 operands formats as stored in the m6811_opcode table. These |
325 | /* 68HC11 operands formats as stored in the m6811_opcode table. These |
| 327 | flags do not correspond to anything in the 68HC11 or 68HC12. |
326 | flags do not correspond to anything in the 68HC11 or 68HC12. |
| 328 | They are only used by GAS to recognize operands. */ |
327 | They are only used by GAS to recognize operands. */ |
| 329 | #define M6811_OP_NONE 0 /* No operand */ |
328 | #define M6811_OP_NONE 0 /* No operand */ |
| 330 | #define M6811_OP_DIRECT 0x0001 /* Page 0 addressing: * |
329 | #define M6811_OP_DIRECT 0x0001 /* Page 0 addressing: * |
| 331 | #define M6811_OP_IMM8 0x0002 /* 8 bits immediat: # |
330 | #define M6811_OP_IMM8 0x0002 /* 8 bits immediat: # |
| 332 | #define M6811_OP_IMM16 0x0004 /* 16 bits immediat: # |
331 | #define M6811_OP_IMM16 0x0004 /* 16 bits immediat: # |
| 333 | #define M6811_OP_IND16 0x0008 /* Indirect abs: |
332 | #define M6811_OP_IND16 0x0008 /* Indirect abs: |
| 334 | #define M6812_OP_IND16_P2 0x0010 /* Second parameter indirect abs. */ |
333 | #define M6812_OP_IND16_P2 0x0010 /* Second parameter indirect abs. */ |
| 335 | #define M6812_OP_REG 0x0020 /* Register operand 1 */ |
334 | #define M6812_OP_REG 0x0020 /* Register operand 1 */ |
| 336 | #define M6812_OP_REG_2 0x0040 /* Register operand 2 */ |
335 | #define M6812_OP_REG_2 0x0040 /* Register operand 2 */ |
| 337 | 336 | ||
| 338 | #define M6811_OP_IX 0x0080 /* Indirect IX: |
337 | #define M6811_OP_IX 0x0080 /* Indirect IX: |
| 339 | #define M6811_OP_IY 0x0100 /* Indirect IY: |
338 | #define M6811_OP_IY 0x0100 /* Indirect IY: |
| 340 | #define M6812_OP_IDX 0x0200 /* Indirect: N,r N,[+-]r[+-] N:5-bits */ |
339 | #define M6812_OP_IDX 0x0200 /* Indirect: N,r N,[+-]r[+-] N:5-bits */ |
| 341 | #define M6812_OP_IDX_1 0x0400 /* N,r N:9-bits */ |
340 | #define M6812_OP_IDX_1 0x0400 /* N,r N:9-bits */ |
| 342 | #define M6812_OP_IDX_2 0x0800 /* N,r N:16-bits */ |
341 | #define M6812_OP_IDX_2 0x0800 /* N,r N:16-bits */ |
| 343 | #define M6812_OP_D_IDX 0x1000 /* Indirect indexed: [D,r] */ |
342 | #define M6812_OP_D_IDX 0x1000 /* Indirect indexed: [D,r] */ |
| 344 | #define M6812_OP_D_IDX_2 0x2000 /* [N,r] N:16-bits */ |
343 | #define M6812_OP_D_IDX_2 0x2000 /* [N,r] N:16-bits */ |
| 345 | #define M6812_OP_PAGE 0x4000 /* Page number */ |
344 | #define M6812_OP_PAGE 0x4000 /* Page number */ |
| 346 | #define M6811_OP_MASK 0x07FFF |
345 | #define M6811_OP_MASK 0x07FFF |
| 347 | #define M6811_OP_BRANCH 0x00008000 /* Branch, jsr, call */ |
346 | #define M6811_OP_BRANCH 0x00008000 /* Branch, jsr, call */ |
| 348 | #define M6811_OP_BITMASK 0x00010000 /* Bitmask: # |
347 | #define M6811_OP_BITMASK 0x00010000 /* Bitmask: # |
| 349 | #define M6811_OP_JUMP_REL 0x00020000 /* Pc-Relative: |
348 | #define M6811_OP_JUMP_REL 0x00020000 /* Pc-Relative: |
| 350 | #define M6812_OP_JUMP_REL16 0x00040000 /* Pc-relative: |
349 | #define M6812_OP_JUMP_REL16 0x00040000 /* Pc-relative: |
| 351 | #define M6811_OP_PAGE1 0x0000 |
350 | #define M6811_OP_PAGE1 0x0000 |
| 352 | #define M6811_OP_PAGE2 0x00080000 /* Need a page2 opcode before */ |
351 | #define M6811_OP_PAGE2 0x00080000 /* Need a page2 opcode before */ |
| 353 | #define M6811_OP_PAGE3 0x00100000 /* Need a page3 opcode before */ |
352 | #define M6811_OP_PAGE3 0x00100000 /* Need a page3 opcode before */ |
| 354 | #define M6811_OP_PAGE4 0x00200000 /* Need a page4 opcode before */ |
353 | #define M6811_OP_PAGE4 0x00200000 /* Need a page4 opcode before */ |
| 355 | #define M6811_MAX_OPERANDS 3 /* Max operands: brset |
354 | #define M6811_MAX_OPERANDS 3 /* Max operands: brset |
| 356 | 355 | ||
| 357 | #define M6812_ACC_OFFSET 0x00400000 /* A,r B,r D,r */ |
356 | #define M6812_ACC_OFFSET 0x00400000 /* A,r B,r D,r */ |
| 358 | #define M6812_ACC_IND 0x00800000 /* [D,r] */ |
357 | #define M6812_ACC_IND 0x00800000 /* [D,r] */ |
| 359 | #define M6812_PRE_INC 0x01000000 /* n,+r n = -8..8 */ |
358 | #define M6812_PRE_INC 0x01000000 /* n,+r n = -8..8 */ |
| 360 | #define M6812_PRE_DEC 0x02000000 /* n,-r */ |
359 | #define M6812_PRE_DEC 0x02000000 /* n,-r */ |
| 361 | #define M6812_POST_INC 0x04000000 /* n,r+ */ |
360 | #define M6812_POST_INC 0x04000000 /* n,r+ */ |
| 362 | #define M6812_POST_DEC 0x08000000 /* n,r- */ |
361 | #define M6812_POST_DEC 0x08000000 /* n,r- */ |
| 363 | #define M6812_INDEXED_IND 0x10000000 /* [n,r] n = 16-bits */ |
362 | #define M6812_INDEXED_IND 0x10000000 /* [n,r] n = 16-bits */ |
| 364 | #define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */ |
363 | #define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */ |
| 365 | #define M6812_OP_IDX_P2 0x40000000 |
364 | #define M6812_OP_IDX_P2 0x40000000 |
| 366 | 365 | ||
| 367 | /* XGATE defines. |
366 | /* XGATE defines. |
| 368 | These overlap with HC11/12 as above but not used at the same time. */ |
367 | These overlap with HC11/12 as above but not used at the same time. */ |
| 369 | #define M68XG_OP_NONE 0x0001 |
368 | #define M68XG_OP_NONE 0x0001 |
| 370 | #define M68XG_OP_IMM3 0x0002 |
369 | #define M68XG_OP_IMM3 0x0002 |
| 371 | #define M68XG_OP_R 0x0004 |
370 | #define M68XG_OP_R 0x0004 |
| 372 | #define M68XG_OP_R_R 0x0008 |
371 | #define M68XG_OP_R_R 0x0008 |
| 373 | #define M68XG_OP_R_IMM4 0x0010 |
372 | #define M68XG_OP_R_IMM4 0x0010 |
| 374 | #define M68XG_OP_R_R_R 0x0020 |
373 | #define M68XG_OP_R_R_R 0x0020 |
| 375 | #define M68XG_OP_REL9 0x0040 |
374 | #define M68XG_OP_REL9 0x0040 |
| 376 | #define M68XG_OP_REL10 0x0080 |
375 | #define M68XG_OP_REL10 0x0080 |
| 377 | #define M68XG_OP_R_R_OFFS5 0x0100 |
376 | #define M68XG_OP_R_R_OFFS5 0x0100 |
| 378 | #define M68XG_OP_RD_RB_RI 0x0200 |
377 | #define M68XG_OP_RD_RB_RI 0x0200 |
| 379 | #define M68XG_OP_RD_RB_RIp 0x0400 |
378 | #define M68XG_OP_RD_RB_RIp 0x0400 |
| 380 | #define M68XG_OP_RD_RB_mRI 0x0800 |
379 | #define M68XG_OP_RD_RB_mRI 0x0800 |
| 381 | #define M68XG_OP_R_IMM8 0x1000 |
380 | #define M68XG_OP_R_IMM8 0x1000 |
| 382 | #define M68XG_OP_R_IMM16 0x2000 |
381 | #define M68XG_OP_R_IMM16 0x2000 |
| 383 | #define M68XG_OP_REG 0x4000 /* Register operand 1. */ |
382 | #define M68XG_OP_REG 0x4000 /* Register operand 1. */ |
| 384 | #define M68XG_OP_REG_2 0x8000 /* Register operand 2. */ |
383 | #define M68XG_OP_REG_2 0x8000 /* Register operand 2. */ |
| 385 | #define M68XG_MAX_OPERANDS 3 /* Max operands of triadic r1, r2, r3. */ |
384 | #define M68XG_MAX_OPERANDS 3 /* Max operands of triadic r1, r2, r3. */ |
| 386 | 385 | ||
| 387 | /* Markers to identify some instructions. */ |
386 | /* Markers to identify some instructions. */ |
| 388 | #define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */ |
387 | #define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */ |
| 389 | #define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */ |
388 | #define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */ |
| 390 | #define M6812_OP_SEX_MARKER 0x04000000 /* sex r1,r2 */ |
389 | #define M6812_OP_SEX_MARKER 0x04000000 /* sex r1,r2 */ |
| 391 | 390 | ||
| 392 | #define M6812_OP_EQ_MARKER 0x80000000 /* dbeq/ibeq/tbeq */ |
391 | #define M6812_OP_EQ_MARKER 0x80000000 /* dbeq/ibeq/tbeq */ |
| 393 | #define M6812_OP_DBCC_MARKER 0x04000000 /* dbeq/dbne */ |
392 | #define M6812_OP_DBCC_MARKER 0x04000000 /* dbeq/dbne */ |
| 394 | #define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */ |
393 | #define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */ |
| 395 | #define M6812_OP_TBCC_MARKER 0x01000000 |
394 | #define M6812_OP_TBCC_MARKER 0x01000000 |
| 396 | 395 | ||
| 397 | /* XGATE markers. */ |
396 | /* XGATE markers. */ |
| 398 | #define M68XG_OP_B_MARKER 0x04000000 /* bXX rel9 */ |
397 | #define M68XG_OP_B_MARKER 0x04000000 /* bXX rel9 */ |
| 399 | #define M68XG_OP_BRA_MARKER 0x02000000 /* bra rel10 */ |
398 | #define M68XG_OP_BRA_MARKER 0x02000000 /* bra rel10 */ |
| 400 | 399 | ||
| 401 | #define M6812_OP_TRAP_ID 0x80000000 /* trap #N */ |
400 | #define M6812_OP_TRAP_ID 0x80000000 /* trap #N */ |
| 402 | 401 | ||
| 403 | #define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */ |
402 | #define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */ |
| 404 | #define M6811_OP_LOW_ADDR 0x02000000 |
403 | #define M6811_OP_LOW_ADDR 0x02000000 |
| 405 | 404 | ||
| 406 | #define M68HC12_BANK_VIRT 0x010000 |
405 | #define M68HC12_BANK_VIRT 0x010000 |
| 407 | #define M68HC12_BANK_MASK 0x00003fff |
406 | #define M68HC12_BANK_MASK 0x00003fff |
| 408 | #define M68HC12_BANK_BASE 0x00008000 |
407 | #define M68HC12_BANK_BASE 0x00008000 |
| 409 | #define M68HC12_BANK_SHIFT 14 |
408 | #define M68HC12_BANK_SHIFT 14 |
| 410 | #define M68HC12_BANK_PAGE_MASK 0x0ff |
409 | #define M68HC12_BANK_PAGE_MASK 0x0ff |
| 411 | 410 | ||
| 412 | 411 | ||
| 413 | /* CPU identification. */ |
412 | /* CPU identification. */ |
| 414 | #define cpu6811 0x01 |
413 | #define cpu6811 0x01 |
| 415 | #define cpu6812 0x02 |
414 | #define cpu6812 0x02 |
| 416 | #define cpu6812s 0x04 |
415 | #define cpu6812s 0x04 |
| 417 | #define cpu9s12x 0x08 /* 9S12X main cpu. */ |
416 | #define cpu9s12x 0x08 /* 9S12X main cpu. */ |
| 418 | #define cpuxgate 0x10 /* The XGATE module itself. */ |
417 | #define cpuxgate 0x10 /* The XGATE module itself. */ |
| 419 | 418 | ||
| 420 | /* The opcode table is an array of struct m68hc11_opcode. */ |
419 | /* The opcode table is an array of struct m68hc11_opcode. */ |
| 421 | struct m68hc11_opcode |
420 | struct m68hc11_opcode |
| 422 | { |
421 | { |
| 423 | const char * name; /* Op-code name. */ |
422 | const char * name; /* Op-code name. */ |
| 424 | long format; |
423 | long format; |
| 425 | unsigned char size; |
424 | unsigned char size; |
| 426 | unsigned int opcode; |
425 | unsigned int opcode; |
| 427 | unsigned char cycles_low; |
426 | unsigned char cycles_low; |
| 428 | unsigned char cycles_high; |
427 | unsigned char cycles_high; |
| 429 | unsigned char set_flags_mask; |
428 | unsigned char set_flags_mask; |
| 430 | unsigned char clr_flags_mask; |
429 | unsigned char clr_flags_mask; |
| 431 | unsigned char chg_flags_mask; |
430 | unsigned char chg_flags_mask; |
| 432 | unsigned char arch; |
431 | unsigned char arch; |
| 433 | unsigned int xg_mask; /* Mask with zero in register place for xgate. */ |
432 | unsigned int xg_mask; /* Mask with zero in register place for xgate. */ |
| 434 | }; |
433 | }; |
| 435 | 434 | ||
| 436 | /* Alias definition for 68HC12. */ |
435 | /* Alias definition for 68HC12. */ |
| 437 | struct m68hc12_opcode_alias |
436 | struct m68hc12_opcode_alias |
| 438 | { |
437 | { |
| 439 | const char* name; |
438 | const char* name; |
| 440 | const char* translation; |
439 | const char* translation; |
| 441 | unsigned char size; |
440 | unsigned char size; |
| 442 | unsigned char code1; |
441 | unsigned char code1; |
| 443 | unsigned char code2; |
442 | unsigned char code2; |
| 444 | }; |
443 | }; |
| 445 | 444 | ||
| 446 | /* The opcode table. The table contains all the opcodes (all pages). |
445 | /* The opcode table. The table contains all the opcodes (all pages). |
| 447 | You can't rely on the order. */ |
446 | You can't rely on the order. */ |
| 448 | extern const struct m68hc11_opcode m68hc11_opcodes[]; |
447 | extern const struct m68hc11_opcode m68hc11_opcodes[]; |
| 449 | extern const int m68hc11_num_opcodes; |
448 | extern const int m68hc11_num_opcodes; |
| 450 | 449 | ||
| 451 | /* Alias table for 68HC12. It translates some 68HC11 insn which are not |
450 | /* Alias table for 68HC12. It translates some 68HC11 insn which are not |
| 452 | implemented in 68HC12 but have equivalent translations. */ |
451 | implemented in 68HC12 but have equivalent translations. */ |
| 453 | extern const struct m68hc12_opcode_alias m68hc12_alias[]; |
452 | extern const struct m68hc12_opcode_alias m68hc12_alias[]; |
| 454 | extern const int m68hc12_num_alias; |
453 | extern const int m68hc12_num_alias; |
| 455 | 454 | ||
| 456 | #endif /* _OPCODE_M68HC11_H */ |
455 | #endif /* _OPCODE_M68HC11_H */ |