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1 | /* ia64.h -- Header file for ia64 opcode table |
1 | /* ia64.h -- Header file for ia64 opcode table |
2 | Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006, 2010 |
- | |
3 | Free Software Foundation, Inc. |
2 | Copyright (C) 1998-2015 Free Software Foundation, Inc. |
4 | Contributed by David Mosberger-Tang |
3 | Contributed by David Mosberger-Tang |
5 | 4 | ||
6 | This file is part of BFD, the Binary File Descriptor library. |
5 | This file is part of BFD, the Binary File Descriptor library. |
7 | 6 | ||
8 | This program is free software; you can redistribute it and/or modify |
7 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by |
8 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 3 of the License, or |
9 | the Free Software Foundation; either version 3 of the License, or |
11 | (at your option) any later version. |
10 | (at your option) any later version. |
12 | 11 | ||
13 | This program is distributed in the hope that it will be useful, |
12 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
16 | GNU General Public License for more details. |
15 | GNU General Public License for more details. |
17 | 16 | ||
18 | You should have received a copy of the GNU General Public License |
17 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software Foundation, |
18 | along with this program; if not, write to the Free Software Foundation, |
20 | Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
19 | Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
21 | 20 | ||
22 | #ifndef opcode_ia64_h |
21 | #ifndef opcode_ia64_h |
23 | #define opcode_ia64_h |
22 | #define opcode_ia64_h |
24 | 23 | ||
25 | #include |
24 | #include |
26 | 25 | ||
27 | #include "bfd.h" |
26 | #include "bfd.h" |
28 | 27 | ||
29 | 28 | ||
30 | typedef BFD_HOST_U_64_BIT ia64_insn; |
29 | typedef BFD_HOST_U_64_BIT ia64_insn; |
31 | 30 | ||
32 | enum ia64_insn_type |
31 | enum ia64_insn_type |
33 | { |
32 | { |
34 | IA64_TYPE_NIL = 0, /* illegal type */ |
33 | IA64_TYPE_NIL = 0, /* illegal type */ |
35 | IA64_TYPE_A, /* integer alu (I- or M-unit) */ |
34 | IA64_TYPE_A, /* integer alu (I- or M-unit) */ |
36 | IA64_TYPE_I, /* non-alu integer (I-unit) */ |
35 | IA64_TYPE_I, /* non-alu integer (I-unit) */ |
37 | IA64_TYPE_M, /* memory (M-unit) */ |
36 | IA64_TYPE_M, /* memory (M-unit) */ |
38 | IA64_TYPE_B, /* branch (B-unit) */ |
37 | IA64_TYPE_B, /* branch (B-unit) */ |
39 | IA64_TYPE_F, /* floating-point (F-unit) */ |
38 | IA64_TYPE_F, /* floating-point (F-unit) */ |
40 | IA64_TYPE_X, /* long encoding (X-unit) */ |
39 | IA64_TYPE_X, /* long encoding (X-unit) */ |
41 | IA64_TYPE_DYN, /* Dynamic opcode */ |
40 | IA64_TYPE_DYN, /* Dynamic opcode */ |
42 | IA64_NUM_TYPES |
41 | IA64_NUM_TYPES |
43 | }; |
42 | }; |
44 | 43 | ||
45 | enum ia64_unit |
44 | enum ia64_unit |
46 | { |
45 | { |
47 | IA64_UNIT_NIL = 0, /* illegal unit */ |
46 | IA64_UNIT_NIL = 0, /* illegal unit */ |
48 | IA64_UNIT_I, /* integer unit */ |
47 | IA64_UNIT_I, /* integer unit */ |
49 | IA64_UNIT_M, /* memory unit */ |
48 | IA64_UNIT_M, /* memory unit */ |
50 | IA64_UNIT_B, /* branching unit */ |
49 | IA64_UNIT_B, /* branching unit */ |
51 | IA64_UNIT_F, /* floating-point unit */ |
50 | IA64_UNIT_F, /* floating-point unit */ |
52 | IA64_UNIT_L, /* long "unit" */ |
51 | IA64_UNIT_L, /* long "unit" */ |
53 | IA64_UNIT_X, /* may be integer or branch unit */ |
52 | IA64_UNIT_X, /* may be integer or branch unit */ |
54 | IA64_NUM_UNITS |
53 | IA64_NUM_UNITS |
55 | }; |
54 | }; |
56 | 55 | ||
57 | /* Changes to this enumeration must be propagated to the operand table in |
56 | /* Changes to this enumeration must be propagated to the operand table in |
58 | bfd/cpu-ia64-opc.c |
57 | bfd/cpu-ia64-opc.c |
59 | */ |
58 | */ |
60 | enum ia64_opnd |
59 | enum ia64_opnd |
61 | { |
60 | { |
62 | IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ |
61 | IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ |
63 | 62 | ||
64 | /* constants */ |
63 | /* constants */ |
65 | IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ |
64 | IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ |
66 | IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ |
65 | IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ |
67 | IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ |
66 | IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ |
68 | IA64_OPND_C1, /* the constant 1 */ |
67 | IA64_OPND_C1, /* the constant 1 */ |
69 | IA64_OPND_C8, /* the constant 8 */ |
68 | IA64_OPND_C8, /* the constant 8 */ |
70 | IA64_OPND_C16, /* the constant 16 */ |
69 | IA64_OPND_C16, /* the constant 16 */ |
71 | IA64_OPND_GR0, /* gr0 */ |
70 | IA64_OPND_GR0, /* gr0 */ |
72 | IA64_OPND_IP, /* instruction pointer (ip) */ |
71 | IA64_OPND_IP, /* instruction pointer (ip) */ |
73 | IA64_OPND_PR, /* predicate register (pr) */ |
72 | IA64_OPND_PR, /* predicate register (pr) */ |
74 | IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ |
73 | IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ |
75 | IA64_OPND_PSR, /* processor status register (psr) */ |
74 | IA64_OPND_PSR, /* processor status register (psr) */ |
76 | IA64_OPND_PSR_L, /* processor status register L (psr.l) */ |
75 | IA64_OPND_PSR_L, /* processor status register L (psr.l) */ |
77 | IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ |
76 | IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ |
78 | 77 | ||
79 | /* register operands: */ |
78 | /* register operands: */ |
80 | IA64_OPND_AR3, /* third application register # (bits 20-26) */ |
79 | IA64_OPND_AR3, /* third application register # (bits 20-26) */ |
81 | IA64_OPND_B1, /* branch register # (bits 6-8) */ |
80 | IA64_OPND_B1, /* branch register # (bits 6-8) */ |
82 | IA64_OPND_B2, /* branch register # (bits 13-15) */ |
81 | IA64_OPND_B2, /* branch register # (bits 13-15) */ |
83 | IA64_OPND_CR3, /* third control register # (bits 20-26) */ |
82 | IA64_OPND_CR3, /* third control register # (bits 20-26) */ |
84 | IA64_OPND_F1, /* first floating-point register # */ |
83 | IA64_OPND_F1, /* first floating-point register # */ |
85 | IA64_OPND_F2, /* second floating-point register # */ |
84 | IA64_OPND_F2, /* second floating-point register # */ |
86 | IA64_OPND_F3, /* third floating-point register # */ |
85 | IA64_OPND_F3, /* third floating-point register # */ |
87 | IA64_OPND_F4, /* fourth floating-point register # */ |
86 | IA64_OPND_F4, /* fourth floating-point register # */ |
88 | IA64_OPND_P1, /* first predicate # */ |
87 | IA64_OPND_P1, /* first predicate # */ |
89 | IA64_OPND_P2, /* second predicate # */ |
88 | IA64_OPND_P2, /* second predicate # */ |
90 | IA64_OPND_R1, /* first register # */ |
89 | IA64_OPND_R1, /* first register # */ |
91 | IA64_OPND_R2, /* second register # */ |
90 | IA64_OPND_R2, /* second register # */ |
92 | IA64_OPND_R3, /* third register # */ |
91 | IA64_OPND_R3, /* third register # */ |
93 | IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ |
92 | IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ |
94 | IA64_OPND_DAHR3, /* dahr reg # ( bits 23-25) */ |
93 | IA64_OPND_DAHR3, /* dahr reg # ( bits 23-25) */ |
95 | 94 | ||
96 | /* memory operands: */ |
95 | /* memory operands: */ |
97 | IA64_OPND_MR3, /* memory at addr of third register # */ |
96 | IA64_OPND_MR3, /* memory at addr of third register # */ |
98 | 97 | ||
99 | /* indirect operands: */ |
98 | /* indirect operands: */ |
100 | IA64_OPND_CPUID_R3, /* cpuid[reg] */ |
99 | IA64_OPND_CPUID_R3, /* cpuid[reg] */ |
101 | IA64_OPND_DBR_R3, /* dbr[reg] */ |
100 | IA64_OPND_DBR_R3, /* dbr[reg] */ |
102 | IA64_OPND_DTR_R3, /* dtr[reg] */ |
101 | IA64_OPND_DTR_R3, /* dtr[reg] */ |
103 | IA64_OPND_ITR_R3, /* itr[reg] */ |
102 | IA64_OPND_ITR_R3, /* itr[reg] */ |
104 | IA64_OPND_IBR_R3, /* ibr[reg] */ |
103 | IA64_OPND_IBR_R3, /* ibr[reg] */ |
105 | IA64_OPND_MSR_R3, /* msr[reg] */ |
104 | IA64_OPND_MSR_R3, /* msr[reg] */ |
106 | IA64_OPND_PKR_R3, /* pkr[reg] */ |
105 | IA64_OPND_PKR_R3, /* pkr[reg] */ |
107 | IA64_OPND_PMC_R3, /* pmc[reg] */ |
106 | IA64_OPND_PMC_R3, /* pmc[reg] */ |
108 | IA64_OPND_PMD_R3, /* pmd[reg] */ |
107 | IA64_OPND_PMD_R3, /* pmd[reg] */ |
109 | IA64_OPND_DAHR_R3, /* dahr[reg] */ |
108 | IA64_OPND_DAHR_R3, /* dahr[reg] */ |
110 | IA64_OPND_RR_R3, /* rr[reg] */ |
109 | IA64_OPND_RR_R3, /* rr[reg] */ |
111 | 110 | ||
112 | /* immediate operands: */ |
111 | /* immediate operands: */ |
113 | IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ |
112 | IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ |
114 | IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ |
113 | IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ |
115 | IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ |
114 | IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ |
116 | IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ |
115 | IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ |
117 | IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ |
116 | IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ |
118 | IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ |
117 | IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ |
119 | IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ |
118 | IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ |
120 | IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ |
119 | IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ |
121 | IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ |
120 | IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ |
122 | IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ |
121 | IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ |
123 | IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ |
122 | IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ |
124 | IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */ |
123 | IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */ |
125 | IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ |
124 | IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ |
126 | IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ |
125 | IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ |
127 | IA64_OPND_SOF, /* 8-bit stack frame size */ |
126 | IA64_OPND_SOF, /* 8-bit stack frame size */ |
128 | IA64_OPND_SOL, /* 8-bit size of locals */ |
127 | IA64_OPND_SOL, /* 8-bit size of locals */ |
129 | IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ |
128 | IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ |
130 | IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ |
129 | IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ |
131 | IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ |
130 | IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ |
132 | IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ |
131 | IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ |
133 | IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ |
132 | IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ |
134 | IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ |
133 | IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ |
135 | IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ |
134 | IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ |
136 | IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ |
135 | IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ |
137 | IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ |
136 | IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ |
138 | IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ |
137 | IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ |
139 | IA64_OPND_IMMU16, /* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */ |
138 | IA64_OPND_IMMU16, /* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */ |
140 | IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ |
139 | IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ |
141 | IA64_OPND_IMMU19, /* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */ |
140 | IA64_OPND_IMMU19, /* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */ |
142 | IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ |
141 | IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ |
143 | IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ |
142 | IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ |
144 | IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ |
143 | IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ |
145 | IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ |
144 | IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ |
146 | IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ |
145 | IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ |
147 | IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ |
146 | IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ |
148 | IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ |
147 | IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ |
149 | IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ |
148 | IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ |
150 | IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ |
149 | IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ |
151 | IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ |
150 | IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ |
152 | IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ |
151 | IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ |
153 | IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ |
152 | IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ |
154 | IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ |
153 | IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ |
155 | IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ |
154 | IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ |
156 | IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ |
155 | IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ |
157 | IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ |
156 | IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ |
158 | IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ |
157 | IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ |
159 | IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ |
158 | IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ |
160 | IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ |
159 | IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ |
161 | 160 | ||
162 | IA64_OPND_CNT6a, /* 6-bit count (bits 6-11) */ |
161 | IA64_OPND_CNT6a, /* 6-bit count (bits 6-11) */ |
163 | IA64_OPND_STRD5b, /* 5-bit stride (bits 13-17) */ |
162 | IA64_OPND_STRD5b, /* 5-bit stride (bits 13-17) */ |
164 | 163 | ||
165 | IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ |
164 | IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ |
166 | }; |
165 | }; |
167 | 166 | ||
168 | enum ia64_dependency_mode |
167 | enum ia64_dependency_mode |
169 | { |
168 | { |
170 | IA64_DV_RAW, |
169 | IA64_DV_RAW, |
171 | IA64_DV_WAW, |
170 | IA64_DV_WAW, |
172 | IA64_DV_WAR, |
171 | IA64_DV_WAR, |
173 | }; |
172 | }; |
174 | 173 | ||
175 | enum ia64_dependency_semantics |
174 | enum ia64_dependency_semantics |
176 | { |
175 | { |
177 | IA64_DVS_NONE, |
176 | IA64_DVS_NONE, |
178 | IA64_DVS_IMPLIED, |
177 | IA64_DVS_IMPLIED, |
179 | IA64_DVS_IMPLIEDF, |
178 | IA64_DVS_IMPLIEDF, |
180 | IA64_DVS_DATA, |
179 | IA64_DVS_DATA, |
181 | IA64_DVS_INSTR, |
180 | IA64_DVS_INSTR, |
182 | IA64_DVS_SPECIFIC, |
181 | IA64_DVS_SPECIFIC, |
183 | IA64_DVS_STOP, |
182 | IA64_DVS_STOP, |
184 | IA64_DVS_OTHER, |
183 | IA64_DVS_OTHER, |
185 | }; |
184 | }; |
186 | 185 | ||
187 | enum ia64_resource_specifier |
186 | enum ia64_resource_specifier |
188 | { |
187 | { |
189 | IA64_RS_ANY, |
188 | IA64_RS_ANY, |
190 | IA64_RS_AR_K, |
189 | IA64_RS_AR_K, |
191 | IA64_RS_AR_UNAT, |
190 | IA64_RS_AR_UNAT, |
192 | IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ |
191 | IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ |
193 | IA64_RS_ARb, /* 48-63, 112-127 */ |
192 | IA64_RS_ARb, /* 48-63, 112-127 */ |
194 | IA64_RS_BR, |
193 | IA64_RS_BR, |
195 | IA64_RS_CFM, |
194 | IA64_RS_CFM, |
196 | IA64_RS_CPUID, |
195 | IA64_RS_CPUID, |
197 | IA64_RS_CR_IIB, |
196 | IA64_RS_CR_IIB, |
198 | IA64_RS_CR_IRR, |
197 | IA64_RS_CR_IRR, |
199 | IA64_RS_CR_LRR, |
198 | IA64_RS_CR_LRR, |
200 | IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */ |
199 | IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */ |
201 | IA64_RS_DAHR, |
200 | IA64_RS_DAHR, |
202 | IA64_RS_DBR, |
201 | IA64_RS_DBR, |
203 | IA64_RS_FR, |
202 | IA64_RS_FR, |
204 | IA64_RS_FRb, |
203 | IA64_RS_FRb, |
205 | IA64_RS_GR0, |
204 | IA64_RS_GR0, |
206 | IA64_RS_GR, |
205 | IA64_RS_GR, |
207 | IA64_RS_IBR, |
206 | IA64_RS_IBR, |
208 | IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ |
207 | IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ |
209 | IA64_RS_MSR, |
208 | IA64_RS_MSR, |
210 | IA64_RS_PKR, |
209 | IA64_RS_PKR, |
211 | IA64_RS_PMC, |
210 | IA64_RS_PMC, |
212 | IA64_RS_PMD, |
211 | IA64_RS_PMD, |
213 | IA64_RS_PR, /* non-rotating, 1-15 */ |
212 | IA64_RS_PR, /* non-rotating, 1-15 */ |
214 | IA64_RS_PRr, /* rotating, 16-62 */ |
213 | IA64_RS_PRr, /* rotating, 16-62 */ |
215 | IA64_RS_PR63, |
214 | IA64_RS_PR63, |
216 | IA64_RS_RR, |
215 | IA64_RS_RR, |
217 | 216 | ||
218 | IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ |
217 | IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ |
219 | IA64_RS_CRX, /* CRs not in RS_CR */ |
218 | IA64_RS_CRX, /* CRs not in RS_CR */ |
220 | IA64_RS_PSR, /* PSR bits */ |
219 | IA64_RS_PSR, /* PSR bits */ |
221 | IA64_RS_RSE, /* implementation-specific RSE resources */ |
220 | IA64_RS_RSE, /* implementation-specific RSE resources */ |
222 | IA64_RS_AR_FPSR, |
221 | IA64_RS_AR_FPSR, |
223 | 222 | ||
224 | }; |
223 | }; |
225 | 224 | ||
226 | enum ia64_rse_resource |
225 | enum ia64_rse_resource |
227 | { |
226 | { |
228 | IA64_RSE_N_STACKED_PHYS, |
227 | IA64_RSE_N_STACKED_PHYS, |
229 | IA64_RSE_BOF, |
228 | IA64_RSE_BOF, |
230 | IA64_RSE_STORE_REG, |
229 | IA64_RSE_STORE_REG, |
231 | IA64_RSE_LOAD_REG, |
230 | IA64_RSE_LOAD_REG, |
232 | IA64_RSE_BSPLOAD, |
231 | IA64_RSE_BSPLOAD, |
233 | IA64_RSE_RNATBITINDEX, |
232 | IA64_RSE_RNATBITINDEX, |
234 | IA64_RSE_CFLE, |
233 | IA64_RSE_CFLE, |
235 | IA64_RSE_NDIRTY, |
234 | IA64_RSE_NDIRTY, |
236 | }; |
235 | }; |
237 | 236 | ||
238 | /* Information about a given resource dependency */ |
237 | /* Information about a given resource dependency */ |
239 | struct ia64_dependency |
238 | struct ia64_dependency |
240 | { |
239 | { |
241 | /* Name of the resource */ |
240 | /* Name of the resource */ |
242 | const char *name; |
241 | const char *name; |
243 | /* Does this dependency need further specification? */ |
242 | /* Does this dependency need further specification? */ |
244 | enum ia64_resource_specifier specifier; |
243 | enum ia64_resource_specifier specifier; |
245 | /* Mode of dependency */ |
244 | /* Mode of dependency */ |
246 | enum ia64_dependency_mode mode; |
245 | enum ia64_dependency_mode mode; |
247 | /* Dependency semantics */ |
246 | /* Dependency semantics */ |
248 | enum ia64_dependency_semantics semantics; |
247 | enum ia64_dependency_semantics semantics; |
249 | /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ |
248 | /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ |
250 | #define REG_NONE (-1) |
249 | #define REG_NONE (-1) |
251 | int regindex; |
250 | int regindex; |
252 | /* Special info on semantics */ |
251 | /* Special info on semantics */ |
253 | const char *info; |
252 | const char *info; |
254 | }; |
253 | }; |
255 | 254 | ||
256 | /* Two arrays of indexes into the ia64_dependency table. |
255 | /* Two arrays of indexes into the ia64_dependency table. |
257 | chks are dependencies to check for conflicts when an opcode is |
256 | chks are dependencies to check for conflicts when an opcode is |
258 | encountered; regs are dependencies to register (mark as used) when an |
257 | encountered; regs are dependencies to register (mark as used) when an |
259 | opcode is used. chks correspond to readers (RAW) or writers (WAW or |
258 | opcode is used. chks correspond to readers (RAW) or writers (WAW or |
260 | WAR) of a resource, while regs correspond to writers (RAW or WAW) and |
259 | WAR) of a resource, while regs correspond to writers (RAW or WAW) and |
261 | readers (WAR) of a resource. */ |
260 | readers (WAR) of a resource. */ |
262 | struct ia64_opcode_dependency |
261 | struct ia64_opcode_dependency |
263 | { |
262 | { |
264 | int nchks; |
263 | int nchks; |
265 | const unsigned short *chks; |
264 | const unsigned short *chks; |
266 | int nregs; |
265 | int nregs; |
267 | const unsigned short *regs; |
266 | const unsigned short *regs; |
268 | }; |
267 | }; |
269 | 268 | ||
270 | /* encode/extract the note/index for a dependency */ |
269 | /* encode/extract the note/index for a dependency */ |
271 | #define RDEP(N,X) (((N)<<11)|(X)) |
270 | #define RDEP(N,X) (((N)<<11)|(X)) |
272 | #define NOTE(X) (((X)>>11)&0x1F) |
271 | #define NOTE(X) (((X)>>11)&0x1F) |
273 | #define DEP(X) ((X)&0x7FF) |
272 | #define DEP(X) ((X)&0x7FF) |
274 | 273 | ||
275 | /* A template descriptor describes the execution units that are active |
274 | /* A template descriptor describes the execution units that are active |
276 | for each of the three slots. It also specifies the location of |
275 | for each of the three slots. It also specifies the location of |
277 | instruction group boundaries that may be present between two slots. */ |
276 | instruction group boundaries that may be present between two slots. */ |
278 | struct ia64_templ_desc |
277 | struct ia64_templ_desc |
279 | { |
278 | { |
280 | int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ |
279 | int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ |
281 | enum ia64_unit exec_unit[3]; |
280 | enum ia64_unit exec_unit[3]; |
282 | const char *name; |
281 | const char *name; |
283 | }; |
282 | }; |
284 | 283 | ||
285 | /* The opcode table is an array of struct ia64_opcode. */ |
284 | /* The opcode table is an array of struct ia64_opcode. */ |
286 | 285 | ||
287 | struct ia64_opcode |
286 | struct ia64_opcode |
288 | { |
287 | { |
289 | /* The opcode name. */ |
288 | /* The opcode name. */ |
290 | const char *name; |
289 | const char *name; |
291 | 290 | ||
292 | /* The type of the instruction: */ |
291 | /* The type of the instruction: */ |
293 | enum ia64_insn_type type; |
292 | enum ia64_insn_type type; |
294 | 293 | ||
295 | /* Number of output operands: */ |
294 | /* Number of output operands: */ |
296 | int num_outputs; |
295 | int num_outputs; |
297 | 296 | ||
298 | /* The opcode itself. Those bits which will be filled in with |
297 | /* The opcode itself. Those bits which will be filled in with |
299 | operands are zeroes. */ |
298 | operands are zeroes. */ |
300 | ia64_insn opcode; |
299 | ia64_insn opcode; |
301 | 300 | ||
302 | /* The opcode mask. This is used by the disassembler. This is a |
301 | /* The opcode mask. This is used by the disassembler. This is a |
303 | mask containing ones indicating those bits which must match the |
302 | mask containing ones indicating those bits which must match the |
304 | opcode field, and zeroes indicating those bits which need not |
303 | opcode field, and zeroes indicating those bits which need not |
305 | match (and are presumably filled in by operands). */ |
304 | match (and are presumably filled in by operands). */ |
306 | ia64_insn mask; |
305 | ia64_insn mask; |
307 | 306 | ||
308 | /* An array of operand codes. Each code is an index into the |
307 | /* An array of operand codes. Each code is an index into the |
309 | operand table. They appear in the order which the operands must |
308 | operand table. They appear in the order which the operands must |
310 | appear in assembly code, and are terminated by a zero. */ |
309 | appear in assembly code, and are terminated by a zero. */ |
311 | enum ia64_opnd operands[5]; |
310 | enum ia64_opnd operands[5]; |
312 | 311 | ||
313 | /* One bit flags for the opcode. These are primarily used to |
312 | /* One bit flags for the opcode. These are primarily used to |
314 | indicate specific processors and environments support the |
313 | indicate specific processors and environments support the |
315 | instructions. The defined values are listed below. */ |
314 | instructions. The defined values are listed below. */ |
316 | unsigned int flags; |
315 | unsigned int flags; |
317 | 316 | ||
318 | /* Used by ia64_find_next_opcode (). */ |
317 | /* Used by ia64_find_next_opcode (). */ |
319 | short ent_index; |
318 | short ent_index; |
320 | 319 | ||
321 | /* Opcode dependencies. */ |
320 | /* Opcode dependencies. */ |
322 | const struct ia64_opcode_dependency *dependencies; |
321 | const struct ia64_opcode_dependency *dependencies; |
323 | }; |
322 | }; |
324 | 323 | ||
325 | /* Values defined for the flags field of a struct ia64_opcode. */ |
324 | /* Values defined for the flags field of a struct ia64_opcode. */ |
326 | 325 | ||
327 | #define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ |
326 | #define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ |
328 | #define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ |
327 | #define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ |
329 | #define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ |
328 | #define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ |
330 | #define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ |
329 | #define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ |
331 | #define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ |
330 | #define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ |
332 | #define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ |
331 | #define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ |
333 | #define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ |
332 | #define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ |
334 | #define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ |
333 | #define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ |
335 | #define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ |
334 | #define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ |
336 | #define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ |
335 | #define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ |
337 | #define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ |
336 | #define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ |
338 | 337 | ||
339 | /* A macro to extract the major opcode from an instruction. */ |
338 | /* A macro to extract the major opcode from an instruction. */ |
340 | #define IA64_OP(i) (((i) >> 37) & 0xf) |
339 | #define IA64_OP(i) (((i) >> 37) & 0xf) |
341 | 340 | ||
342 | enum ia64_operand_class |
341 | enum ia64_operand_class |
343 | { |
342 | { |
344 | IA64_OPND_CLASS_CST, /* constant */ |
343 | IA64_OPND_CLASS_CST, /* constant */ |
345 | IA64_OPND_CLASS_REG, /* register */ |
344 | IA64_OPND_CLASS_REG, /* register */ |
346 | IA64_OPND_CLASS_IND, /* indirect register */ |
345 | IA64_OPND_CLASS_IND, /* indirect register */ |
347 | IA64_OPND_CLASS_ABS, /* absolute value */ |
346 | IA64_OPND_CLASS_ABS, /* absolute value */ |
348 | IA64_OPND_CLASS_REL, /* IP-relative value */ |
347 | IA64_OPND_CLASS_REL, /* IP-relative value */ |
349 | }; |
348 | }; |
350 | 349 | ||
351 | /* The operands table is an array of struct ia64_operand. */ |
350 | /* The operands table is an array of struct ia64_operand. */ |
352 | 351 | ||
353 | struct ia64_operand |
352 | struct ia64_operand |
354 | { |
353 | { |
355 | enum ia64_operand_class op_class; |
354 | enum ia64_operand_class op_class; |
356 | 355 | ||
357 | /* Set VALUE as the operand bits for the operand of type SELF in the |
356 | /* Set VALUE as the operand bits for the operand of type SELF in the |
358 | instruction pointed to by CODE. If an error occurs, *CODE is not |
357 | instruction pointed to by CODE. If an error occurs, *CODE is not |
359 | modified and the returned string describes the cause of the |
358 | modified and the returned string describes the cause of the |
360 | error. If no error occurs, NULL is returned. */ |
359 | error. If no error occurs, NULL is returned. */ |
361 | const char *(*insert) (const struct ia64_operand *self, ia64_insn value, |
360 | const char *(*insert) (const struct ia64_operand *self, ia64_insn value, |
362 | ia64_insn *code); |
361 | ia64_insn *code); |
363 | 362 | ||
364 | /* Extract the operand bits for an operand of type SELF from |
363 | /* Extract the operand bits for an operand of type SELF from |
365 | instruction CODE store them in *VALUE. If an error occurs, the |
364 | instruction CODE store them in *VALUE. If an error occurs, the |
366 | cause of the error is described by the string returned. If no |
365 | cause of the error is described by the string returned. If no |
367 | error occurs, NULL is returned. */ |
366 | error occurs, NULL is returned. */ |
368 | const char *(*extract) (const struct ia64_operand *self, ia64_insn code, |
367 | const char *(*extract) (const struct ia64_operand *self, ia64_insn code, |
369 | ia64_insn *value); |
368 | ia64_insn *value); |
370 | 369 | ||
371 | /* A string whose meaning depends on the operand class. */ |
370 | /* A string whose meaning depends on the operand class. */ |
372 | 371 | ||
373 | const char *str; |
372 | const char *str; |
374 | 373 | ||
375 | struct bit_field |
374 | struct bit_field |
376 | { |
375 | { |
377 | /* The number of bits in the operand. */ |
376 | /* The number of bits in the operand. */ |
378 | int bits; |
377 | int bits; |
379 | 378 | ||
380 | /* How far the operand is left shifted in the instruction. */ |
379 | /* How far the operand is left shifted in the instruction. */ |
381 | int shift; |
380 | int shift; |
382 | } |
381 | } |
383 | field[4]; /* no operand has more than this many bit-fields */ |
382 | field[4]; /* no operand has more than this many bit-fields */ |
384 | 383 | ||
385 | unsigned int flags; |
384 | unsigned int flags; |
386 | 385 | ||
387 | const char *desc; /* brief description */ |
386 | const char *desc; /* brief description */ |
388 | }; |
387 | }; |
389 | 388 | ||
390 | /* Values defined for the flags field of a struct ia64_operand. */ |
389 | /* Values defined for the flags field of a struct ia64_operand. */ |
391 | 390 | ||
392 | /* Disassemble as signed decimal (instead of hex): */ |
391 | /* Disassemble as signed decimal (instead of hex): */ |
393 | #define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) |
392 | #define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) |
394 | /* Disassemble as unsigned decimal (instead of hex): */ |
393 | /* Disassemble as unsigned decimal (instead of hex): */ |
395 | #define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) |
394 | #define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) |
396 | 395 | ||
397 | extern const struct ia64_templ_desc ia64_templ_desc[16]; |
396 | extern const struct ia64_templ_desc ia64_templ_desc[16]; |
398 | 397 | ||
399 | /* The tables are sorted by major opcode number and are otherwise in |
398 | /* The tables are sorted by major opcode number and are otherwise in |
400 | the order in which the disassembler should consider instructions. */ |
399 | the order in which the disassembler should consider instructions. */ |
401 | extern struct ia64_opcode ia64_opcodes_a[]; |
400 | extern struct ia64_opcode ia64_opcodes_a[]; |
402 | extern struct ia64_opcode ia64_opcodes_i[]; |
401 | extern struct ia64_opcode ia64_opcodes_i[]; |
403 | extern struct ia64_opcode ia64_opcodes_m[]; |
402 | extern struct ia64_opcode ia64_opcodes_m[]; |
404 | extern struct ia64_opcode ia64_opcodes_b[]; |
403 | extern struct ia64_opcode ia64_opcodes_b[]; |
405 | extern struct ia64_opcode ia64_opcodes_f[]; |
404 | extern struct ia64_opcode ia64_opcodes_f[]; |
406 | extern struct ia64_opcode ia64_opcodes_d[]; |
405 | extern struct ia64_opcode ia64_opcodes_d[]; |
407 | 406 | ||
408 | 407 | ||
409 | extern struct ia64_opcode *ia64_find_opcode (const char *); |
408 | extern struct ia64_opcode *ia64_find_opcode (const char *); |
410 | extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *); |
409 | extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *); |
411 | 410 | ||
412 | extern struct ia64_opcode *ia64_dis_opcode (ia64_insn, |
411 | extern struct ia64_opcode *ia64_dis_opcode (ia64_insn, |
413 | enum ia64_insn_type); |
412 | enum ia64_insn_type); |
414 | 413 | ||
415 | extern void ia64_free_opcode (struct ia64_opcode *); |
414 | extern void ia64_free_opcode (struct ia64_opcode *); |
416 | extern const struct ia64_dependency *ia64_find_dependency (int); |
415 | extern const struct ia64_dependency *ia64_find_dependency (int); |
417 | 416 | ||
418 | /* To avoid circular library dependencies, this array is implemented |
417 | /* To avoid circular library dependencies, this array is implemented |
419 | in bfd/cpu-ia64-opc.c: */ |
418 | in bfd/cpu-ia64-opc.c: */ |
420 | extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; |
419 | extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; |
421 | 420 | ||
422 | #endif /* opcode_ia64_h */1) |
421 | #endif /* opcode_ia64_h */1) |
423 | 422 | ||
424 | extern><1) |
423 | extern><1) |
425 | 424 | ||
426 | extern>0) |
425 | extern>0) |
427 | /*><0) |
426 | /*><0) |
428 | /*>10)><10)>9)><9)>8)><8)>7)><7)>6)><6)>5)><5)>4)><4)>3)><3)>2)><2)>1)><1)>0)><0)>11)|(X)) |
427 | /*>10)><10)>9)><9)>8)><8)>7)><7)>6)><6)>5)><5)>4)><4)>3)><3)>2)><2)>1)><1)>0)><0)>11)|(X)) |
429 | #define><11)|(X)) |
428 | #define><11)|(X)) |
430 | #define> |
429 | #define> |