WebSVN – Kolibri OS – Diff – /contrib/toolchain/binutils/include/opcode/d10v.h


/* d10v.h -- Header file for D10V opcode table
 
   Copyright (C) 1996-2015 Free Software Foundation, Inc.
   Written by Martin Hunt (hunt@cygnus.com), Cygnus Support
 
   This file is part of GDB, GAS, and the GNU binutils.
 
   GDB, GAS, and the GNU binutils are free software; you can redistribute
   them and/or modify them under the terms of the GNU General Public
   License as published by the Free Software Foundation; either version 3,
   or (at your option) any later version.
 
   GDB, GAS, and the GNU binutils are distributed in the hope that they
   will be useful, but WITHOUT ANY WARRANTY; without even the implied
   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
   the GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING3.  If not, write to the Free
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */
 
#ifndef D10V_H
#define D10V_H
 
/* Format Specifier */
#define FM00	0
#define FM01	0x40000000
#define FM10	0x80000000
#define FM11	0xC0000000
 
#define NOP 0x5e00
#define OPCODE_DIVS	0x14002800
 
/* The opcode table is an array of struct d10v_opcode.  */
 
struct d10v_opcode
{
  /* The opcode name.  */
  const char *name;
 
  /* the opcode format */
  int format;
 
  /* These numbers were picked so we can do if( i & SHORT_OPCODE) */
#define SHORT_OPCODE 1
#define LONG_OPCODE  8
#define SHORT_2	     1		/* short with 2 operands */
#define SHORT_B	     3		/* short with 8-bit branch */
#define LONG_B	     8		/* long with 16-bit branch */
#define LONG_L       10		/* long with 3 operands */
#define LONG_R       12		/* reserved */
 
  /* just a placeholder for variable-length instructions */
  /* for example, "bra" will be a fake for "bra.s" and bra.l" */
  /* which will immediately follow in the opcode table.  */
#define OPCODE_FAKE  32
 
  /* the number of cycles */
  int cycles;
 
  /* the execution unit(s) used */
  int unit;
#define EITHER	0
#define IU	1
#define MU	2
#define BOTH	3
 
  /* execution type; parallel or sequential */
  /* this field is used to decide if two instructions */
  /* can be executed in parallel */
  int exec_type;
#define PARONLY 1	/* parallel only */
#define SEQ	2	/* must be sequential */
#define PAR	4	/* may be parallel */
#define BRANCH_LINK 8	/* subroutine call.  must be aligned */
#define RMEM     16	/* reads memory */
#define WMEM     32	/* writes memory */
#define RF0      64	/* reads f0 */
#define WF0     128	/* modifies f0 */
#define WCAR    256	/* write Carry */
#define BRANCH  512	/* branch, no link */
#define ALONE  1024	/* short but pack with a NOP if on asm line alone */
 
  /* the opcode */
  long opcode;
 
  /* mask.  if( (i & mask) == opcode ) then match */
  long mask;
 
  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  unsigned char operands[6];
};
 
/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct d10v_opcode d10v_opcodes[];
extern const int d10v_num_opcodes;
 
/* The operands table is an array of struct d10v_operand.  */
struct d10v_operand
{
  /* The number of bits in the operand.  */
  int bits;
 
  /* How far the operand is left shifted in the instruction.  */
  int shift;
 
  /* One bit syntax flags.  */
  int flags;
};
 
/* Elements in the table are retrieved by indexing with values from
   the operands field of the d10v_opcodes table.  */
 
extern const struct d10v_operand d10v_operands[];
 
/* Values defined for the flags field of a struct d10v_operand.  */
 
/* the operand must be an even number */
#define OPERAND_EVEN	(1)
 
/* the operand must be an odd number */
#define OPERAND_ODD	(2)	
 
/* this is the destination register; it will be modified */
/* this is used by the optimizer */
#define OPERAND_DEST	(4)
 
/* number or symbol */
#define OPERAND_NUM	(8)
 
/* address or label */
#define OPERAND_ADDR	(0x10)
 
/* register */
#define OPERAND_REG	(0x20)
 
/* postincrement +  */
#define OPERAND_PLUS	(0x40)
 
/* postdecrement -  */
#define OPERAND_MINUS	(0x80)
 
/* @  */
#define OPERAND_ATSIGN	(0x100)
 
/* @(  */
#define OPERAND_ATPAR	(0x200)
 
/* accumulator 0 */
#define OPERAND_ACC0	(0x400)
 
/* accumulator 1 */
#define OPERAND_ACC1	(0x800)
 
/* f0 / f1 flag register */
#define OPERAND_FFLAG	(0x1000)
 
/* c flag register */
#define OPERAND_CFLAG	(0x2000)
 
/* control register  */
#define OPERAND_CONTROL	(0x4000)
 
/* predecrement mode '@-sp'  */
#define OPERAND_ATMINUS	(0x8000)
 
/* signed number */
#define OPERAND_SIGNED	(0x10000)
 
/* special accumulator shifts need a 4-bit number */
/* 1 <= x <= 16 */
#define OPERAND_SHIFT	(0x20000)
 
/* general purpose register */
#define OPERAND_GPR	(0x40000)
 
/* special imm3 values with range restricted to -2 <= imm3 <= 3 */
/* needed for rac/rachi */
#define RESTRICTED_NUM3	(0x80000)
 
/* Pre-decrement is only supported for SP.  */
#define OPERAND_SP      (0x100000)
 
/* Post-decrement is not supported for SP.  Like OPERAND_EVEN, and
   unlike OPERAND_SP, this flag doesn't prevent the instruction from
   matching, it only fails validation later on.  */
#define OPERAND_NOSP    (0x200000)
 
/* Structure to hold information about predefined registers.  */
struct pd_reg
{
  char *name;		/* name to recognize */
  char *pname;		/* name to print for this register */
  int value;
};
 
extern const struct pd_reg d10v_predefined_registers[];
int d10v_reg_name_cnt (void);
 
/* an expressionS only has one register type, so we fake it */
/* by setting high bits to indicate type */
#define REGISTER_MASK	0xFF
 
#endif /* D10V_H */

Rev 5191	Rev 6324
1	/* d10v.h -- Header file for D10V opcode table	1	/* d10v.h -- Header file for D10V opcode table
2	Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2010	-
3	Free Software Foundation, Inc.	2	Copyright (C) 1996-2015 Free Software Foundation, Inc.
4	Written by Martin Hunt (hunt@cygnus.com), Cygnus Support	3	Written by Martin Hunt (hunt@cygnus.com), Cygnus Support
5		4
6	This file is part of GDB, GAS, and the GNU binutils.	5	This file is part of GDB, GAS, and the GNU binutils.
7		6
8	GDB, GAS, and the GNU binutils are free software; you can redistribute	7	GDB, GAS, and the GNU binutils are free software; you can redistribute
9	them and/or modify them under the terms of the GNU General Public	8	them and/or modify them under the terms of the GNU General Public
10	License as published by the Free Software Foundation; either version 3,	9	License as published by the Free Software Foundation; either version 3,
11	or (at your option) any later version.	10	or (at your option) any later version.
12		11
13	GDB, GAS, and the GNU binutils are distributed in the hope that they	12	GDB, GAS, and the GNU binutils are distributed in the hope that they
14	will be useful, but WITHOUT ANY WARRANTY; without even the implied	13	will be useful, but WITHOUT ANY WARRANTY; without even the implied
15	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See	14	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16	the GNU General Public License for more details.	15	the GNU General Public License for more details.
17		16
18	You should have received a copy of the GNU General Public License	17	You should have received a copy of the GNU General Public License
19	along with this file; see the file COPYING3. If not, write to the Free	18	along with this file; see the file COPYING3. If not, write to the Free
20	Software Foundation, 51 Franklin Street - Fifth Floor, Boston,	19	Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21	MA 02110-1301, USA. */	20	MA 02110-1301, USA. */
22		21
23	#ifndef D10V_H	22	#ifndef D10V_H
24	#define D10V_H	23	#define D10V_H
25		24
26	/* Format Specifier */	25	/* Format Specifier */
27	#define FM00 0	26	#define FM00 0
28	#define FM01 0x40000000	27	#define FM01 0x40000000
29	#define FM10 0x80000000	28	#define FM10 0x80000000
30	#define FM11 0xC0000000	29	#define FM11 0xC0000000
31		30
32	#define NOP 0x5e00	31	#define NOP 0x5e00
33	#define OPCODE_DIVS 0x14002800	32	#define OPCODE_DIVS 0x14002800
34		33
35	/* The opcode table is an array of struct d10v_opcode. */	34	/* The opcode table is an array of struct d10v_opcode. */
36		35
37	struct d10v_opcode	36	struct d10v_opcode
38	{	37	{
39	/* The opcode name. */	38	/* The opcode name. */
40	const char *name;	39	const char *name;
41		40
42	/* the opcode format */	41	/* the opcode format */
43	int format;	42	int format;
44		43
45	/* These numbers were picked so we can do if( i & SHORT_OPCODE) */	44	/* These numbers were picked so we can do if( i & SHORT_OPCODE) */
46	#define SHORT_OPCODE 1	45	#define SHORT_OPCODE 1
47	#define LONG_OPCODE 8	46	#define LONG_OPCODE 8
48	#define SHORT_2 1 /* short with 2 operands */	47	#define SHORT_2 1 /* short with 2 operands */
49	#define SHORT_B 3 /* short with 8-bit branch */	48	#define SHORT_B 3 /* short with 8-bit branch */
50	#define LONG_B 8 /* long with 16-bit branch */	49	#define LONG_B 8 /* long with 16-bit branch */
51	#define LONG_L 10 /* long with 3 operands */	50	#define LONG_L 10 /* long with 3 operands */
52	#define LONG_R 12 /* reserved */	51	#define LONG_R 12 /* reserved */
53		52
54	/* just a placeholder for variable-length instructions */	53	/* just a placeholder for variable-length instructions */
55	/* for example, "bra" will be a fake for "bra.s" and bra.l" */	54	/* for example, "bra" will be a fake for "bra.s" and bra.l" */
56	/* which will immediately follow in the opcode table. */	55	/* which will immediately follow in the opcode table. */
57	#define OPCODE_FAKE 32	56	#define OPCODE_FAKE 32
58		57
59	/* the number of cycles */	58	/* the number of cycles */
60	int cycles;	59	int cycles;
61		60
62	/* the execution unit(s) used */	61	/* the execution unit(s) used */
63	int unit;	62	int unit;
64	#define EITHER 0	63	#define EITHER 0
65	#define IU 1	64	#define IU 1
66	#define MU 2	65	#define MU 2
67	#define BOTH 3	66	#define BOTH 3
68		67
69	/* execution type; parallel or sequential */	68	/* execution type; parallel or sequential */
70	/* this field is used to decide if two instructions */	69	/* this field is used to decide if two instructions */
71	/* can be executed in parallel */	70	/* can be executed in parallel */
72	int exec_type;	71	int exec_type;
73	#define PARONLY 1 /* parallel only */	72	#define PARONLY 1 /* parallel only */
74	#define SEQ 2 /* must be sequential */	73	#define SEQ 2 /* must be sequential */
75	#define PAR 4 /* may be parallel */	74	#define PAR 4 /* may be parallel */
76	#define BRANCH_LINK 8 /* subroutine call. must be aligned */	75	#define BRANCH_LINK 8 /* subroutine call. must be aligned */
77	#define RMEM 16 /* reads memory */	76	#define RMEM 16 /* reads memory */
78	#define WMEM 32 /* writes memory */	77	#define WMEM 32 /* writes memory */
79	#define RF0 64 /* reads f0 */	78	#define RF0 64 /* reads f0 */
80	#define WF0 128 /* modifies f0 */	79	#define WF0 128 /* modifies f0 */
81	#define WCAR 256 /* write Carry */	80	#define WCAR 256 /* write Carry */
82	#define BRANCH 512 /* branch, no link */	81	#define BRANCH 512 /* branch, no link */
83	#define ALONE 1024 /* short but pack with a NOP if on asm line alone */	82	#define ALONE 1024 /* short but pack with a NOP if on asm line alone */
84		83
85	/* the opcode */	84	/* the opcode */
86	long opcode;	85	long opcode;
87		86
88	/* mask. if( (i & mask) == opcode ) then match */	87	/* mask. if( (i & mask) == opcode ) then match */
89	long mask;	88	long mask;
90		89
91	/* An array of operand codes. Each code is an index into the	90	/* An array of operand codes. Each code is an index into the
92	operand table. They appear in the order which the operands must	91	operand table. They appear in the order which the operands must
93	appear in assembly code, and are terminated by a zero. */	92	appear in assembly code, and are terminated by a zero. */
94	unsigned char operands[6];	93	unsigned char operands[6];
95	};	94	};
96		95
97	/* The table itself is sorted by major opcode number, and is otherwise	96	/* The table itself is sorted by major opcode number, and is otherwise
98	in the order in which the disassembler should consider	97	in the order in which the disassembler should consider
99	instructions. */	98	instructions. */
100	extern const struct d10v_opcode d10v_opcodes[];	99	extern const struct d10v_opcode d10v_opcodes[];
101	extern const int d10v_num_opcodes;	100	extern const int d10v_num_opcodes;
102		101
103	/* The operands table is an array of struct d10v_operand. */	102	/* The operands table is an array of struct d10v_operand. */
104	struct d10v_operand	103	struct d10v_operand
105	{	104	{
106	/* The number of bits in the operand. */	105	/* The number of bits in the operand. */
107	int bits;	106	int bits;
108		107
109	/* How far the operand is left shifted in the instruction. */	108	/* How far the operand is left shifted in the instruction. */
110	int shift;	109	int shift;
111		110
112	/* One bit syntax flags. */	111	/* One bit syntax flags. */
113	int flags;	112	int flags;
114	};	113	};
115		114
116	/* Elements in the table are retrieved by indexing with values from	115	/* Elements in the table are retrieved by indexing with values from
117	the operands field of the d10v_opcodes table. */	116	the operands field of the d10v_opcodes table. */
118		117
119	extern const struct d10v_operand d10v_operands[];	118	extern const struct d10v_operand d10v_operands[];
120		119
121	/* Values defined for the flags field of a struct d10v_operand. */	120	/* Values defined for the flags field of a struct d10v_operand. */
122		121
123	/* the operand must be an even number */	122	/* the operand must be an even number */
124	#define OPERAND_EVEN (1)	123	#define OPERAND_EVEN (1)
125		124
126	/* the operand must be an odd number */	125	/* the operand must be an odd number */
127	#define OPERAND_ODD (2)	126	#define OPERAND_ODD (2)
128		127
129	/* this is the destination register; it will be modified */	128	/* this is the destination register; it will be modified */
130	/* this is used by the optimizer */	129	/* this is used by the optimizer */
131	#define OPERAND_DEST (4)	130	#define OPERAND_DEST (4)
132		131
133	/* number or symbol */	132	/* number or symbol */
134	#define OPERAND_NUM (8)	133	#define OPERAND_NUM (8)
135		134
136	/* address or label */	135	/* address or label */
137	#define OPERAND_ADDR (0x10)	136	#define OPERAND_ADDR (0x10)
138		137
139	/* register */	138	/* register */
140	#define OPERAND_REG (0x20)	139	#define OPERAND_REG (0x20)
141		140
142	/* postincrement + */	141	/* postincrement + */
143	#define OPERAND_PLUS (0x40)	142	#define OPERAND_PLUS (0x40)
144		143
145	/* postdecrement - */	144	/* postdecrement - */
146	#define OPERAND_MINUS (0x80)	145	#define OPERAND_MINUS (0x80)
147		146
148	/* @ */	147	/* @ */
149	#define OPERAND_ATSIGN (0x100)	148	#define OPERAND_ATSIGN (0x100)
150		149
151	/* @( */	150	/* @( */
152	#define OPERAND_ATPAR (0x200)	151	#define OPERAND_ATPAR (0x200)
153		152
154	/* accumulator 0 */	153	/* accumulator 0 */
155	#define OPERAND_ACC0 (0x400)	154	#define OPERAND_ACC0 (0x400)
156		155
157	/* accumulator 1 */	156	/* accumulator 1 */
158	#define OPERAND_ACC1 (0x800)	157	#define OPERAND_ACC1 (0x800)
159		158
160	/* f0 / f1 flag register */	159	/* f0 / f1 flag register */
161	#define OPERAND_FFLAG (0x1000)	160	#define OPERAND_FFLAG (0x1000)
162		161
163	/* c flag register */	162	/* c flag register */
164	#define OPERAND_CFLAG (0x2000)	163	#define OPERAND_CFLAG (0x2000)
165		164
166	/* control register */	165	/* control register */
167	#define OPERAND_CONTROL (0x4000)	166	#define OPERAND_CONTROL (0x4000)
168		167
169	/* predecrement mode '@-sp' */	168	/* predecrement mode '@-sp' */
170	#define OPERAND_ATMINUS (0x8000)	169	#define OPERAND_ATMINUS (0x8000)
171		170
172	/* signed number */	171	/* signed number */
173	#define OPERAND_SIGNED (0x10000)	172	#define OPERAND_SIGNED (0x10000)
174		173
175	/* special accumulator shifts need a 4-bit number */	174	/* special accumulator shifts need a 4-bit number */
176	/* 1 <= x <= 16 */	175	/* 1 <= x <= 16 */
177	#define OPERAND_SHIFT (0x20000)	176	#define OPERAND_SHIFT (0x20000)
178		177
179	/* general purpose register */	178	/* general purpose register */
180	#define OPERAND_GPR (0x40000)	179	#define OPERAND_GPR (0x40000)
181		180
182	/* special imm3 values with range restricted to -2 <= imm3 <= 3 */	181	/* special imm3 values with range restricted to -2 <= imm3 <= 3 */
183	/* needed for rac/rachi */	182	/* needed for rac/rachi */
184	#define RESTRICTED_NUM3 (0x80000)	183	#define RESTRICTED_NUM3 (0x80000)
185		184
186	/* Pre-decrement is only supported for SP. */	185	/* Pre-decrement is only supported for SP. */
187	#define OPERAND_SP (0x100000)	186	#define OPERAND_SP (0x100000)
188		187
189	/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and	188	/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and
190	unlike OPERAND_SP, this flag doesn't prevent the instruction from	189	unlike OPERAND_SP, this flag doesn't prevent the instruction from
191	matching, it only fails validation later on. */	190	matching, it only fails validation later on. */
192	#define OPERAND_NOSP (0x200000)	191	#define OPERAND_NOSP (0x200000)
193		192
194	/* Structure to hold information about predefined registers. */	193	/* Structure to hold information about predefined registers. */
195	struct pd_reg	194	struct pd_reg
196	{	195	{
197	char name; / name to recognize */	196	char name; / name to recognize */
198	char pname; / name to print for this register */	197	char pname; / name to print for this register */
199	int value;	198	int value;
200	};	199	};
201		200
202	extern const struct pd_reg d10v_predefined_registers[];	201	extern const struct pd_reg d10v_predefined_registers[];
203	int d10v_reg_name_cnt (void);	202	int d10v_reg_name_cnt (void);
204		203
205	/* an expressionS only has one register type, so we fake it */	204	/* an expressionS only has one register type, so we fake it */
206	/* by setting high bits to indicate type */	205	/* by setting high bits to indicate type */
207	#define REGISTER_MASK 0xFF	206	#define REGISTER_MASK 0xFF
208		207
209	#endif /* D10V_H */	208	#endif /* D10V_H */

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