Rev 5191 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 5191 | Rev 6324 | ||
---|---|---|---|
Line 1... | Line 1... | ||
1 | /* Opcode table for the ARC. |
1 | /* Opcode table for the ARC. |
2 | Copyright 1994, 1995, 1997, 2001, 2002, 2003, 2010 |
- | |
3 | Free Software Foundation, Inc. |
2 | Copyright 1994-2015 Free Software Foundation, Inc. |
- | 3 | ||
4 | Contributed by Doug Evans (dje@cygnus.com). |
4 | Contributed by Claudiu Zissulescu (claziss@synopsys.com) |
Line 5... | Line 5... | ||
5 | 5 | ||
6 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
6 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
Line 7... | Line 7... | ||
7 | the GNU Binutils. |
7 | the GNU Binutils. |
Line 19... | Line 19... | ||
19 | You should have received a copy of the GNU General Public License |
19 | You should have received a copy of the GNU General Public License |
20 | along with GAS or GDB; see the file COPYING3. If not, write to |
20 | along with GAS or GDB; see the file COPYING3. If not, write to |
21 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
21 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
22 | MA 02110-1301, USA. */ |
22 | MA 02110-1301, USA. */ |
Line 23... | Line -... | ||
23 | - | ||
24 | /* List of the various cpu types. |
- | |
25 | The tables currently use bit masks to say whether the instruction or |
- | |
26 | whatever is supported by a particular cpu. This lets us have one entry |
- | |
27 | apply to several cpus. |
- | |
28 | - | ||
29 | The `base' cpu must be 0. The cpu type is treated independently of |
- | |
30 | endianness. The complete `mach' number includes endianness. |
- | |
31 | These values are internal to opcodes/bfd/binutils/gas. */ |
23 | |
32 | #define ARC_MACH_5 0 |
- | |
33 | #define ARC_MACH_6 1 |
- | |
34 | #define ARC_MACH_7 2 |
24 | #ifndef OPCODE_ARC_H |
35 | #define ARC_MACH_8 4 |
- | |
36 | - | ||
37 | /* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ |
- | |
38 | #define ARC_MACH_BIG 16 |
- | |
39 | - | ||
40 | /* Mask of number of bits necessary to record cpu type. */ |
- | |
41 | #define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) |
- | |
42 | - | ||
43 | /* Mask of number of bits necessary to record cpu type + endianness. */ |
- | |
44 | #define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) |
- | |
45 | - | ||
46 | /* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ |
- | |
47 | - | ||
48 | typedef unsigned int arc_insn; |
- | |
49 | - | ||
50 | struct arc_opcode { |
- | |
51 | char *syntax; /* syntax of insn */ |
- | |
52 | unsigned long mask, value; /* recognize insn if (op&mask) == value */ |
- | |
53 | int flags; /* various flag bits */ |
- | |
54 | - | ||
55 | /* Values for `flags'. */ |
- | |
56 | - | ||
57 | /* Return CPU number, given flag bits. */ |
- | |
58 | #define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) |
- | |
59 | - | ||
60 | /* Return MACH number, given flag bits. */ |
- | |
61 | #define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) |
- | |
62 | - | ||
63 | /* First opcode flag bit available after machine mask. */ |
- | |
64 | #define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) |
- | |
65 | - | ||
66 | /* This insn is a conditional branch. */ |
- | |
67 | #define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) |
- | |
68 | #define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) |
- | |
69 | #define SYNTAX_LENGTH (SYNTAX_3OP ) |
- | |
70 | #define SYNTAX_2OP (SYNTAX_3OP << 1) |
- | |
71 | #define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) |
- | |
72 | #define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) |
- | |
73 | #define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) |
- | |
74 | - | ||
75 | #define I(x) (((x) & 31) << 27) |
- | |
76 | #define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) |
- | |
77 | #define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) |
- | |
78 | #define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) |
- | |
79 | #define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ |
- | |
80 | - | ||
81 | /* These values are used to optimize assembly and disassembly. Each insn |
- | |
82 | is on a list of related insns (same first letter for assembly, same |
- | |
83 | insn code for disassembly). */ |
- | |
84 | - | ||
85 | struct arc_opcode *next_asm; /* Next instr to try during assembly. */ |
- | |
86 | struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ |
- | |
87 | - | ||
88 | /* Macros to create the hash values for the lists. */ |
- | |
89 | #define ARC_HASH_OPCODE(string) \ |
- | |
90 | ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) |
- | |
91 | #define ARC_HASH_ICODE(insn) \ |
- | |
92 | ((unsigned int) (insn) >> 27) |
- | |
93 | - | ||
94 | /* Macros to access `next_asm', `next_dis' so users needn't care about the |
- | |
95 | underlying mechanism. */ |
- | |
96 | #define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) |
- | |
97 | #define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) |
- | |
Line 98... | Line -... | ||
98 | }; |
- | |
99 | - | ||
100 | /* this is an "insert at front" linked list per Metaware spec |
- | |
101 | that new definitions override older ones. */ |
- | |
102 | extern struct arc_opcode *arc_ext_opcodes; |
25 | #define OPCODE_ARC_H |
103 | - | ||
104 | struct arc_operand_value { |
26 | |
105 | char *name; /* eg: "eq" */ |
- | |
106 | short value; /* eg: 1 */ |
- | |
107 | unsigned char type; /* index into `arc_operands' */ |
- | |
108 | unsigned char flags; /* various flag bits */ |
- | |
109 | - | ||
110 | /* Values for `flags'. */ |
- | |
111 | - | ||
112 | /* Return CPU number, given flag bits. */ |
- | |
113 | #define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) |
- | |
114 | /* Return MACH number, given flag bits. */ |
- | |
Line -... | Line 27... | ||
- | 27 | #define MAX_INSN_ARGS 6 |
|
- | 28 | #define MAX_INSN_FLGS 3 |
|
- | 29 | ||
- | 30 | /* Instruction Class. */ |
|
- | 31 | typedef enum |
|
- | 32 | { |
|
- | 33 | ARITH, |
|
- | 34 | AUXREG, |
|
- | 35 | BRANCH, |
|
- | 36 | CONTROL, |
|
- | 37 | DSP, |
|
- | 38 | FLOAT, |
|
- | 39 | INVALID, |
|
- | 40 | JUMP, |
|
- | 41 | KERNEL, |
|
- | 42 | LOGICAL, |
|
- | 43 | MEMORY, |
|
- | 44 | } insn_class_t; |
|
- | 45 | ||
- | 46 | /* Instruction Subclass. */ |
|
- | 47 | typedef enum |
|
- | 48 | { |
|
- | 49 | NONE, |
|
- | 50 | CVT, |
|
- | 51 | BTSCN, |
|
- | 52 | CD1, |
|
- | 53 | CD2, |
|
- | 54 | DIV, |
|
- | 55 | DP, |
|
- | 56 | MPY1E, |
|
- | 57 | MPY6E, |
|
- | 58 | MPY7E, |
|
- | 59 | MPY8E, |
|
- | 60 | MPY9E, |
|
- | 61 | SHFT1, |
|
- | 62 | SHFT2, |
|
- | 63 | SWAP, |
|
- | 64 | SP |
|
- | 65 | } insn_subclass_t; |
|
- | 66 | ||
- | 67 | /* Flags class. */ |
|
- | 68 | typedef enum |
|
- | 69 | { |
|
- | 70 | FNONE, |
|
- | 71 | CND, /* Conditional flags. */ |
|
- | 72 | WBM, /* Write-back modes. */ |
|
- | 73 | FLG, /* F Flag. */ |
|
- | 74 | SBP, /* Static branch prediction. */ |
|
- | 75 | DLY, /* Delay slot. */ |
|
- | 76 | DIF, /* Bypass caches. */ |
|
- | 77 | SGX, /* Sign extend modes. */ |
|
- | 78 | SZM /* Data size modes. */ |
|
115 | #define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) |
79 | } flag_class_t; |
- | 80 | ||
- | 81 | /* The opcode table is an array of struct arc_opcode. */ |
|
- | 82 | struct arc_opcode |
|
- | 83 | { |
|
- | 84 | /* The opcode name. */ |
|
116 | }; |
85 | const char *name; |
- | 86 | ||
- | 87 | /* The opcode itself. Those bits which will be filled in with |
|
- | 88 | operands are zeroes. */ |
|
- | 89 | unsigned opcode; |
|
- | 90 | ||
- | 91 | /* The opcode mask. This is used by the disassembler. This is a |
|
- | 92 | mask containing ones indicating those bits which must match the |
|
- | 93 | opcode field, and zeroes indicating those bits which need not |
|
- | 94 | match (and are presumably filled in by operands). */ |
|
- | 95 | unsigned mask; |
|
- | 96 | ||
- | 97 | /* One bit flags for the opcode. These are primarily used to |
|
- | 98 | indicate specific processors and environments support the |
|
- | 99 | instructions. The defined values are listed below. */ |
|
- | 100 | unsigned cpu; |
|
- | 101 | ||
- | 102 | /* The instruction class. This is used by gdb. */ |
|
- | 103 | insn_class_t class; |
|
- | 104 | ||
- | 105 | /* The instruction subclass. */ |
|
- | 106 | insn_subclass_t subclass; |
|
- | 107 | ||
117 | 108 | /* An array of operand codes. Each code is an index into the |
|
- | 109 | operand table. They appear in the order which the operands must |
|
- | 110 | appear in assembly code, and are terminated by a zero. */ |
|
- | 111 | unsigned char operands[MAX_INSN_ARGS + 1]; |
|
- | 112 | ||
- | 113 | /* An array of flag codes. Each code is an index into the flag |
|
118 | struct arc_ext_operand_value { |
114 | table. They appear in the order which the flags must appear in |
Line -... | Line 115... | ||
- | 115 | assembly code, and are terminated by a zero. */ |
|
- | 116 | unsigned char flags[MAX_INSN_FLGS + 1]; |
|
- | 117 | }; |
|
119 | struct arc_ext_operand_value *next; |
118 | |
- | 119 | /* The table itself is sorted by major opcode number, and is otherwise |
|
- | 120 | in the order in which the disassembler should consider |
|
- | 121 | instructions. */ |
|
- | 122 | extern const struct arc_opcode arc_opcodes[]; |
|
- | 123 | extern const unsigned arc_num_opcodes; |
|
- | 124 | ||
- | 125 | /* CPU Availability. */ |
|
- | 126 | #define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */ |
|
- | 127 | #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */ |
|
- | 128 | #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */ |
|
- | 129 | #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */ |
|
- | 130 | ||
- | 131 | /* CPU extensions. */ |
|
- | 132 | #define ARC_EA 0x0001 |
|
- | 133 | #define ARC_CD 0x0001 /* Mutual exclusive with EA. */ |
|
- | 134 | #define ARC_LLOCK 0x0002 |
|
- | 135 | #define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */ |
|
- | 136 | #define ARC_MPY 0x0004 |
|
- | 137 | #define ARC_MULT 0x0004 |
|
- | 138 | ||
- | 139 | /* Floating point support. */ |
|
- | 140 | #define ARC_DPFP 0x0010 |
|
- | 141 | #define ARC_SPFP 0x0020 |
|
- | 142 | #define ARC_FPU 0x0030 |
|
- | 143 | ||
- | 144 | /* NORM & SWAP. */ |
|
- | 145 | #define ARC_SWAP 0x0100 |
|
- | 146 | #define ARC_NORM 0x0200 |
|
- | 147 | #define ARC_BSCAN 0x0200 |
|
- | 148 | ||
- | 149 | /* A7 specific. */ |
|
- | 150 | #define ARC_UIX 0x1000 |
|
- | 151 | #define ARC_TSTAMP 0x1000 |
|
- | 152 | ||
- | 153 | /* A6 specific. */ |
|
- | 154 | #define ARC_VBFDW 0x1000 |
|
- | 155 | #define ARC_BARREL 0x1000 |
|
- | 156 | #define ARC_DSPA 0x1000 |
|
- | 157 | ||
- | 158 | /* EM specific. */ |
|
- | 159 | #define ARC_SHIFT 0x1000 |
|
- | 160 | ||
- | 161 | /* V2 specific. */ |
|
- | 162 | #define ARC_INTR 0x1000 |
|
- | 163 | #define ARC_DIV 0x1000 |
|
- | 164 | ||
- | 165 | /* V1 specific. */ |
|
- | 166 | #define ARC_XMAC 0x1000 |
|
- | 167 | #define ARC_CRC 0x1000 |
|
- | 168 | ||
- | 169 | /* Base architecture -- all cpus. */ |
|
- | 170 | #define ARC_OPCODE_BASE \ |
|
- | 171 | (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ |
|
- | 172 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) |
|
- | 173 | ||
- | 174 | /* A macro to check for short instructions. */ |
|
- | 175 | #define ARC_SHORT(mask) \ |
|
- | 176 | (((mask) & 0xFFFF0000) ? 0 : 1) |
|
- | 177 | ||
- | 178 | /* The operands table is an array of struct arc_operand. */ |
|
Line 120... | Line -... | ||
120 | struct arc_operand_value operand; |
- | |
121 | }; |
179 | struct arc_operand |
122 | 180 | { |
|
Line 123... | Line 181... | ||
123 | extern struct arc_ext_operand_value *arc_ext_operands; |
181 | /* The number of bits in the operand. */ |
124 | 182 | unsigned int bits; |
|
Line 125... | Line -... | ||
125 | struct arc_operand { |
- | |
126 | /* One of the insn format chars. */ |
183 | |
127 | unsigned char fmt; |
184 | /* How far the operand is left shifted in the instruction. */ |
Line 128... | Line 185... | ||
128 | 185 | unsigned int shift; |
|
129 | /* The number of bits in the operand (may be unused for a modifier). */ |
186 | |
Line 130... | Line 187... | ||
130 | unsigned char bits; |
187 | /* The default relocation type for this operand. */ |
- | 188 | signed int default_reloc; |
|
- | 189 | ||
- | 190 | /* One bit syntax flags. */ |
|
- | 191 | unsigned int flags; |
|
Line -... | Line 192... | ||
- | 192 | ||
- | 193 | /* Insertion function. This is used by the assembler. To insert an |
|
- | 194 | operand value into an instruction, check this field. |
|
- | 195 | ||
131 | 196 | If it is NULL, execute |
|
- | 197 | i |= (op & ((1 << o->bits) - 1)) << o->shift; |
|
132 | /* How far the operand is left shifted in the instruction, or |
198 | (i is the instruction which we are filling in, o is a pointer to |
- | 199 | this structure, and op is the opcode value; this assumes twos |
|
Line 133... | Line 200... | ||
133 | the modifier's flag bit (may be unused for a modifier. */ |
200 | complement arithmetic). |
134 | unsigned char shift; |
201 | |
135 | - | ||
Line 136... | Line 202... | ||
136 | /* Various flag bits. */ |
202 | If this field is not NULL, then simply call it with the |
137 | int flags; |
203 | instruction and the operand value. It will return the new value |
138 | 204 | of the instruction. If the ERRMSG argument is not NULL, then if |
|
- | 205 | the operand value is illegal, *ERRMSG will be set to a warning |
|
- | 206 | string (the operand will be inserted in any case). If the |
|
- | 207 | operand value is legal, *ERRMSG will be unchanged (most operands |
|
- | 208 | can accept any value). */ |
|
Line -... | Line 209... | ||
- | 209 | unsigned (*insert) (unsigned instruction, int op, const char **errmsg); |
|
- | 210 | ||
- | 211 | /* Extraction function. This is used by the disassembler. To |
|
- | 212 | extract this operand type from an instruction, check this field. |
|
- | 213 | ||
139 | /* Values for `flags'. */ |
214 | If it is NULL, compute |
- | 215 | op = ((i) >> o->shift) & ((1 << o->bits) - 1); |
|
- | 216 | if ((o->flags & ARC_OPERAND_SIGNED) != 0 |
|
- | 217 | && (op & (1 << (o->bits - 1))) != 0) |
|
- | 218 | op -= 1 << o->bits; |
|
140 | 219 | (i is the instruction, o is a pointer to this structure, and op |
|
- | 220 | is the result; this assumes twos complement arithmetic). |
|
- | 221 | ||
- | 222 | If this field is not NULL, then simply call it with the |
|
- | 223 | instruction value. It will return the value of the operand. If |
|
- | 224 | the INVALID argument is not NULL, *INVALID will be set to |
|
- | 225 | TRUE if this operand type can not actually be extracted from |
|
- | 226 | this operand (i.e., the instruction does not match). If the |
|
- | 227 | operand is valid, *INVALID will not be changed. */ |
|
- | 228 | int (*extract) (unsigned instruction, bfd_boolean *invalid); |
|
- | 229 | }; |
|
- | 230 | ||
- | 231 | /* Elements in the table are retrieved by indexing with values from |
|
- | 232 | the operands field of the arc_opcodes table. */ |
|
141 | /* This operand is a suffix to the opcode. */ |
233 | extern const struct arc_operand arc_operands[]; |
Line 142... | Line 234... | ||
142 | #define ARC_OPERAND_SUFFIX 1 |
234 | extern const unsigned arc_num_operands; |
143 | 235 | extern const unsigned arc_Toperand; |
|
Line 144... | Line 236... | ||
144 | /* This operand is a relative branch displacement. The disassembler |
236 | extern const unsigned arc_NToperand; |
145 | prints these symbolically if possible. */ |
237 | |
Line 146... | Line 238... | ||
146 | #define ARC_OPERAND_RELATIVE_BRANCH 2 |
238 | /* Values defined for the flags field of a struct arc_operand. */ |
147 | 239 | ||
148 | /* This operand is an absolute branch address. The disassembler |
- | |
149 | prints these symbolically if possible. */ |
240 | /* This operand does not actually exist in the assembler input. This |
Line 150... | Line 241... | ||
150 | #define ARC_OPERAND_ABSOLUTE_BRANCH 4 |
241 | is used to support extended mnemonics, for which two operands fields |
151 | - | ||
152 | /* This operand is an address. The disassembler |
- | |
153 | prints these symbolically if possible. */ |
- | |
154 | #define ARC_OPERAND_ADDRESS 8 |
- | |
155 | 242 | are identical. The assembler should call the insert function with |
|
Line 156... | Line 243... | ||
156 | /* This operand is a long immediate value. */ |
243 | any op value. The disassembler should call the extract function, |
157 | #define ARC_OPERAND_LIMM 0x10 |
- | |
158 | 244 | ignore the return value, and check the value placed in the invalid |
|
Line 159... | Line 245... | ||
159 | /* This operand takes signed values. */ |
245 | argument. */ |
160 | #define ARC_OPERAND_SIGNED 0x20 |
246 | #define ARC_OPERAND_FAKE 0x0001 |
Line 161... | Line 247... | ||
161 | 247 | ||
162 | /* This operand takes signed values, but also accepts a full positive |
248 | /* This operand names an integer register. */ |
163 | range of values. That is, if bits is 16, it takes any value from |
249 | #define ARC_OPERAND_IR 0x0002 |
Line 164... | Line 250... | ||
164 | -0x8000 to 0xffff. */ |
250 | |
165 | #define ARC_OPERAND_SIGNOPT 0x40 |
251 | /* This operand takes signed values. */ |
Line 166... | Line 252... | ||
166 | 252 | #define ARC_OPERAND_SIGNED 0x0004 |
|
167 | /* This operand should be regarded as a negative number for the |
253 | |
Line 168... | Line 254... | ||
168 | purposes of overflow checking (i.e., the normal most negative |
254 | /* This operand takes unsigned values. This exists primarily so that |
169 | number is disallowed and one more than the normal most positive |
255 | a flags value of 0 can be treated as end-of-arguments. */ |
170 | number is allowed). This flag will only be set for a signed |
256 | #define ARC_OPERAND_UNSIGNED 0x0008 |
Line 171... | Line 257... | ||
171 | operand. */ |
257 | |
172 | #define ARC_OPERAND_NEGATIVE 0x80 |
258 | /* This operand takes long immediate values. */ |
Line 173... | Line 259... | ||
173 | 259 | #define ARC_OPERAND_LIMM 0x0010 |
|
174 | /* This operand doesn't really exist. The program uses these operands |
260 | |
Line 175... | Line 261... | ||
175 | in special ways. */ |
261 | /* This operand is identical like the previous one. */ |
176 | #define ARC_OPERAND_FAKE 0x100 |
262 | #define ARC_OPERAND_DUPLICATE 0x0020 |
- | 263 | ||
- | 264 | /* This operand is PC relative. Used for internal relocs. */ |
|
- | 265 | #define ARC_OPERAND_PCREL 0x0040 |
|
Line 177... | Line 266... | ||
177 | 266 | ||
178 | /* separate flags operand for j and jl instructions */ |
267 | /* This operand is truncated. The truncation is done accordingly to |
- | 268 | operand alignment attribute. */ |
|
- | 269 | #define ARC_OPERAND_TRUNCATE 0x0080 |
|
- | 270 | ||
Line 179... | Line 271... | ||
179 | #define ARC_OPERAND_JUMPFLAGS 0x200 |
271 | /* This operand is 16bit aligned. */ |
180 | - | ||
181 | /* allow warnings and errors to be issued after call to insert_xxxxxx */ |
272 | #define ARC_OPERAND_ALIGNED16 0x0100 |
182 | #define ARC_OPERAND_WARN 0x400 |
- | |
Line 183... | Line 273... | ||
183 | #define ARC_OPERAND_ERROR 0x800 |
273 | |
184 | 274 | /* This operand is 32bit aligned. */ |
|
Line 185... | Line -... | ||
185 | /* this is a load operand */ |
- | |
186 | #define ARC_OPERAND_LOAD 0x8000 |
- | |
187 | 275 | #define ARC_OPERAND_ALIGNED32 0x0200 |
|
188 | /* this is a store operand */ |
- | |
189 | #define ARC_OPERAND_STORE 0x10000 |
276 | |
Line 190... | Line -... | ||
190 | - | ||
191 | /* Modifier values. */ |
- | |
192 | /* A dot is required before a suffix. Eg: .le */ |
- | |
193 | #define ARC_MOD_DOT 0x1000 |
- | |
194 | 277 | /* This operand can be ignored by matching process if it is not |
|
195 | /* A normal register is allowed (not used, but here for completeness). */ |
278 | present. */ |
- | 279 | #define ARC_OPERAND_IGNORE 0x0400 |
|
Line -... | Line 280... | ||
- | 280 | ||
196 | #define ARC_MOD_REG 0x2000 |
281 | /* Don't check the range when matching. */ |
- | 282 | #define ARC_OPERAND_NCHK 0x0800 |
|
- | 283 | ||
- | 284 | /* Mark the braket possition. */ |
|
- | 285 | #define ARC_OPERAND_BRAKET 0x1000 |
|
- | 286 | ||
- | 287 | /* Mask for selecting the type for typecheck purposes. */ |
|
- | 288 | #define ARC_OPERAND_TYPECHECK_MASK \ |
|
Line 197... | Line 289... | ||
197 | 289 | (ARC_OPERAND_IR | \ |
|
198 | /* An auxiliary register name is expected. */ |
290 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \ |
199 | #define ARC_MOD_AUXREG 0x4000 |
- | |
- | 291 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET) |
|
Line 200... | Line -... | ||
200 | - | ||
201 | /* Sum of all ARC_MOD_XXX bits. */ |
292 | |
Line 202... | Line 293... | ||
202 | #define ARC_MOD_BITS 0x7000 |
293 | /* The flags structure. */ |
203 | - | ||
204 | /* Non-zero if the operand type is really a modifier. */ |
294 | struct arc_flag_operand |
- | 295 | { |
|
205 | #define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) |
296 | /* The flag name. */ |
206 | 297 | const char *name; |
|
207 | /* enforce read/write only register restrictions */ |
- | |
208 | #define ARC_REGISTER_READONLY 0x01 |
- | |
Line 209... | Line 298... | ||
209 | #define ARC_REGISTER_WRITEONLY 0x02 |
298 | |
210 | #define ARC_REGISTER_NOSHORT_CUT 0x04 |
- | |
211 | - | ||
212 | /* Insertion function. This is used by the assembler. To insert an |
- | |
213 | operand value into an instruction, check this field. |
- | |
214 | 299 | /* The flag code. */ |
|
- | 300 | unsigned code; |
|
Line 215... | Line 301... | ||
215 | If it is NULL, execute |
301 | |
216 | i |= (p & ((1 << o->bits) - 1)) << o->shift; |
302 | /* The number of bits in the operand. */ |
Line -... | Line 303... | ||
- | 303 | unsigned int bits; |
|
- | 304 | ||
- | 305 | /* How far the operand is left shifted in the instruction. */ |
|
- | 306 | unsigned int shift; |
|
217 | (I is the instruction which we are filling in, O is a pointer to |
307 | |
- | 308 | /* Available for disassembler. */ |
|
- | 309 | unsigned char favail; |
|
- | 310 | }; |
|
- | 311 | ||
- | 312 | /* The flag operands table. */ |
|
218 | this structure, and OP is the opcode value; this assumes twos |
313 | extern const struct arc_flag_operand arc_flag_operands[]; |
- | 314 | extern const unsigned arc_num_flag_operands; |
|
Line -... | Line 315... | ||
- | 315 | ||
- | 316 | /* The flag's class structure. */ |
|
- | 317 | struct arc_flag_class |
|
- | 318 | { |
|
219 | complement arithmetic). |
319 | /* Flag class. */ |
- | 320 | flag_class_t class; |
|
220 | 321 | ||
221 | If this field is not NULL, then simply call it with the |
322 | /* List of valid flags (codes). */ |
- | 323 | unsigned flags[256]; |
|
- | 324 | }; |
|
- | 325 | ||
- | 326 | extern const struct arc_flag_class arc_flag_classes[]; |
|
- | 327 | ||
- | 328 | /* Structure for special cases. */ |
|
- | 329 | struct arc_flag_special |
|
- | 330 | { |
|
- | 331 | /* Name of special case instruction. */ |
|
- | 332 | const char *name; |
|
- | 333 | ||
222 | instruction and the operand value. It will return the new value |
334 | /* List of flags applicable for special case instruction. */ |
Line 223... | Line 335... | ||
223 | of the instruction. If the ERRMSG argument is not NULL, then if |
335 | unsigned flags[32]; |
- | 336 | }; |
|
- | 337 | ||
- | 338 | extern const struct arc_flag_special arc_flag_special_cases[]; |
|
- | 339 | extern const unsigned arc_num_flag_special; |
|
- | 340 | ||
224 | the operand value is illegal, *ERRMSG will be set to a warning |
341 | /* Relocation equivalence structure. */ |
- | 342 | struct arc_reloc_equiv_tab |
|
Line 225... | Line -... | ||
225 | string (the operand will be inserted in any case). If the |
- | |
226 | operand value is legal, *ERRMSG will be unchanged. |
- | |
227 | - | ||
228 | REG is non-NULL when inserting a register value. */ |
- | |
229 | - | ||
230 | arc_insn (*insert) |
- | |
231 | (arc_insn insn, const struct arc_operand *operand, int mods, |
- | |
232 | const struct arc_operand_value *reg, long value, const char **errmsg); |
- | |
233 | - | ||
234 | /* Extraction function. This is used by the disassembler. To |
- | |
235 | extract this operand type from an instruction, check this field. |
343 | { |
236 | - | ||
237 | If it is NULL, compute |
- | |
238 | op = ((i) >> o->shift) & ((1 << o->bits) - 1); |
- | |
239 | if ((o->flags & ARC_OPERAND_SIGNED) != 0 |
- | |
240 | && (op & (1 << (o->bits - 1))) != 0) |
- | |
241 | op -= 1 << o->bits; |
- | |
242 | (I is the instruction, O is a pointer to this structure, and OP |
- | |
243 | is the result; this assumes twos complement arithmetic). |
- | |
244 | 344 | const char * name; /* String to lookup. */ |
|
245 | If this field is not NULL, then simply call it with the |
- | |
246 | instruction value. It will return the value of the operand. If |
- | |
247 | the INVALID argument is not NULL, *INVALID will be set to |
- | |
Line 248... | Line 345... | ||
248 | non-zero if this operand type can not actually be extracted from |
345 | const char * mnemonic; /* Extra matching condition. */ |
249 | this operand (i.e., the instruction does not match). If the |
346 | unsigned flagcode; /* Extra matching condition. */ |
Line 250... | Line 347... | ||
250 | operand is valid, *INVALID will not be changed. |
347 | signed int oldreloc; /* Old relocation. */ |
251 | 348 | signed int newreloc; /* New relocation. */ |
|
- | 349 | }; |
|
- | 350 | ||
252 | INSN is a pointer to an array of two `arc_insn's. The first element is |
351 | extern const struct arc_reloc_equiv_tab arc_reloc_equiv[]; |
253 | the insn, the second is the limm if present. |
352 | extern const unsigned arc_num_equiv_tab; |
- | 353 | ||
254 | 354 | /* Structure for operand operations for pseudo/alias instructions. */ |
|
255 | Operands that have a printable form like registers and suffixes have |
355 | struct arc_operand_operation |
256 | their struct arc_operand_value pointer stored in OPVAL. */ |
- | |
- | 356 | { |
|
257 | 357 | /* The index for operand from operand array. */ |
|
258 | long (*extract) |
358 | unsigned operand_idx; |
259 | (arc_insn *insn, const struct arc_operand *operand, int mods, |
359 | |
260 | const struct arc_operand_value **opval, int *invalid); |
360 | /* Defines if it needs the operand inserted by the assembler or |
261 | }; |
361 | whether this operand comes from the pseudo instruction's |
262 | 362 | operands. */ |
|
263 | /* Bits that say what version of cpu we have. These should be passed to |
- | |
264 | arc_init_opcode_tables. At present, all there is is the cpu type. */ |
- | |
265 | 363 | unsigned char needs_insert; |
|
266 | /* CPU number, given value passed to `arc_init_opcode_tables'. */ |
- | |
267 | #define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) |
- | |
268 | /* MACH number, given value passed to `arc_init_opcode_tables'. */ |
- | |
269 | #define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) |
364 | |
270 | - | ||
- | 365 | /* Count we have to add to the operand. Use negative number to |
|
- | 366 | subtract from the operand. Also use this number to add to 0 if |
|
271 | /* Special register values: */ |
367 | the operand needs to be inserted (i.e. needs_insert == 1). */ |
272 | #define ARC_REG_SHIMM_UPDATE 61 |
- | |
273 | #define ARC_REG_SHIMM 63 |
- | |
274 | #define ARC_REG_LIMM 62 |
- | |
275 | 368 | int count; |
|
276 | /* Non-zero if REG is a constant marker. */ |
- | |
- | 369 | ||
277 | #define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) |
370 | /* Index of the operand to swap with. To be done AFTER applying |
278 | - | ||
279 | /* Positions and masks of various fields: */ |
- |