WebSVN – Kolibri OS – Diff – /contrib/toolchain/binutils/include/gdb/sim-m32c.h


/* This file defines the interface between the m32c simulator and gdb.
   Copyright (C) 2005-2015 Free Software Foundation, Inc.
 
   This file is part of GDB.
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.
 
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program.  If not, see .  */
 
#ifndef SIM_M32C_H
#define SIM_M32C_H
 
enum m32c_sim_reg {
  m32c_sim_reg_r0_bank0,
  m32c_sim_reg_r1_bank0,
  m32c_sim_reg_r2_bank0,
  m32c_sim_reg_r3_bank0,
  m32c_sim_reg_a0_bank0,
  m32c_sim_reg_a1_bank0,
  m32c_sim_reg_fb_bank0,
  m32c_sim_reg_sb_bank0,
  m32c_sim_reg_r0_bank1,
  m32c_sim_reg_r1_bank1,
  m32c_sim_reg_r2_bank1,
  m32c_sim_reg_r3_bank1,
  m32c_sim_reg_a0_bank1,
  m32c_sim_reg_a1_bank1,
  m32c_sim_reg_fb_bank1,
  m32c_sim_reg_sb_bank1,
  m32c_sim_reg_usp,
  m32c_sim_reg_isp,
  m32c_sim_reg_pc,
  m32c_sim_reg_intb,
  m32c_sim_reg_flg,
  m32c_sim_reg_svf,
  m32c_sim_reg_svp,
  m32c_sim_reg_vct,
  m32c_sim_reg_dmd0,
  m32c_sim_reg_dmd1,
  m32c_sim_reg_dct0,
  m32c_sim_reg_dct1,
  m32c_sim_reg_drc0,
  m32c_sim_reg_drc1,
  m32c_sim_reg_dma0,
  m32c_sim_reg_dma1,
  m32c_sim_reg_dsa0,
  m32c_sim_reg_dsa1,
  m32c_sim_reg_dra0,
  m32c_sim_reg_dra1,
  m32c_sim_reg_num_regs
};
 
#endif /* SIM_M32C_H */

Rev 5191	Rev 6324
1	/* This file defines the interface between the m32c simulator and gdb.	1	/* This file defines the interface between the m32c simulator and gdb.
2	Copyright (C) 2005-2013 Free Software Foundation, Inc.	2	Copyright (C) 2005-2015 Free Software Foundation, Inc.
3		3
4	This file is part of GDB.	4	This file is part of GDB.
5		5
6	This program is free software; you can redistribute it and/or modify	6	This program is free software; you can redistribute it and/or modify
7	it under the terms of the GNU General Public License as published by	7	it under the terms of the GNU General Public License as published by
8	the Free Software Foundation; either version 3 of the License, or	8	the Free Software Foundation; either version 3 of the License, or
9	(at your option) any later version.	9	(at your option) any later version.
10		10
11	This program is distributed in the hope that it will be useful,	11	This program is distributed in the hope that it will be useful,
12	but WITHOUT ANY WARRANTY; without even the implied warranty of	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	GNU General Public License for more details.	14	GNU General Public License for more details.
15		15
16	You should have received a copy of the GNU General Public License	16	You should have received a copy of the GNU General Public License
17	along with this program. If not, see . */	17	along with this program. If not, see . */
18		18
19	#ifndef SIM_M32C_H	19	#ifndef SIM_M32C_H
20	#define SIM_M32C_H	20	#define SIM_M32C_H
21		21
22	enum m32c_sim_reg {	22	enum m32c_sim_reg {
23	m32c_sim_reg_r0_bank0,	23	m32c_sim_reg_r0_bank0,
24	m32c_sim_reg_r1_bank0,	24	m32c_sim_reg_r1_bank0,
25	m32c_sim_reg_r2_bank0,	25	m32c_sim_reg_r2_bank0,
26	m32c_sim_reg_r3_bank0,	26	m32c_sim_reg_r3_bank0,
27	m32c_sim_reg_a0_bank0,	27	m32c_sim_reg_a0_bank0,
28	m32c_sim_reg_a1_bank0,	28	m32c_sim_reg_a1_bank0,
29	m32c_sim_reg_fb_bank0,	29	m32c_sim_reg_fb_bank0,
30	m32c_sim_reg_sb_bank0,	30	m32c_sim_reg_sb_bank0,
31	m32c_sim_reg_r0_bank1,	31	m32c_sim_reg_r0_bank1,
32	m32c_sim_reg_r1_bank1,	32	m32c_sim_reg_r1_bank1,
33	m32c_sim_reg_r2_bank1,	33	m32c_sim_reg_r2_bank1,
34	m32c_sim_reg_r3_bank1,	34	m32c_sim_reg_r3_bank1,
35	m32c_sim_reg_a0_bank1,	35	m32c_sim_reg_a0_bank1,
36	m32c_sim_reg_a1_bank1,	36	m32c_sim_reg_a1_bank1,
37	m32c_sim_reg_fb_bank1,	37	m32c_sim_reg_fb_bank1,
38	m32c_sim_reg_sb_bank1,	38	m32c_sim_reg_sb_bank1,
39	m32c_sim_reg_usp,	39	m32c_sim_reg_usp,
40	m32c_sim_reg_isp,	40	m32c_sim_reg_isp,
41	m32c_sim_reg_pc,	41	m32c_sim_reg_pc,
42	m32c_sim_reg_intb,	42	m32c_sim_reg_intb,
43	m32c_sim_reg_flg,	43	m32c_sim_reg_flg,
44	m32c_sim_reg_svf,	44	m32c_sim_reg_svf,
45	m32c_sim_reg_svp,	45	m32c_sim_reg_svp,
46	m32c_sim_reg_vct,	46	m32c_sim_reg_vct,
47	m32c_sim_reg_dmd0,	47	m32c_sim_reg_dmd0,
48	m32c_sim_reg_dmd1,	48	m32c_sim_reg_dmd1,
49	m32c_sim_reg_dct0,	49	m32c_sim_reg_dct0,
50	m32c_sim_reg_dct1,	50	m32c_sim_reg_dct1,
51	m32c_sim_reg_drc0,	51	m32c_sim_reg_drc0,
52	m32c_sim_reg_drc1,	52	m32c_sim_reg_drc1,
53	m32c_sim_reg_dma0,	53	m32c_sim_reg_dma0,
54	m32c_sim_reg_dma1,	54	m32c_sim_reg_dma1,
55	m32c_sim_reg_dsa0,	55	m32c_sim_reg_dsa0,
56	m32c_sim_reg_dsa1,	56	m32c_sim_reg_dsa1,
57	m32c_sim_reg_dra0,	57	m32c_sim_reg_dra0,
58	m32c_sim_reg_dra1,	58	m32c_sim_reg_dra1,
59	m32c_sim_reg_num_regs	59	m32c_sim_reg_num_regs
60	};	60	};
61		61
62	#endif /* SIM_M32C_H */	62	#endif /* SIM_M32C_H */

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(root)/contrib/toolchain/binutils/include/gdb/sim-m32c.h – Rev 5191 → 6324