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/* SPARC ELF support for BFD. |
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/* SPARC ELF support for BFD. |
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2008, 2010, |
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2011 |
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Free Software Foundation, Inc. |
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Copyright (C) 1996-2015 Free Software Foundation, Inc. |
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By Doug Evans, Cygnus Support, . |
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By Doug Evans, Cygnus Support, . |
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This file is part of BFD, the Binary File Descriptor library. |
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This file is part of BFD, the Binary File Descriptor library. |
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/* Object attribute tags. */ |
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/* Object attribute tags. */ |
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enum |
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enum |
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{ |
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{ |
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/* 0-3 are generic. */ |
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/* 0-3 are generic. */ |
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Tag_GNU_Sparc_HWCAPS = 4, |
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Tag_GNU_Sparc_HWCAPS = 4, |
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Tag_GNU_Sparc_HWCAPS2 = 8 |
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}; |
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}; |
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/* Generally speaking the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_* |
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values match the AV_SPARC_* and AV2_SPARC_* bits respectively. |
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However Solaris 11 introduced a backwards-incompatible change |
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deprecating the RANDOM, TRANS and ASI_CACHE_SPARING bits in the |
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AT_SUNW_CAP_HW1 flags, reusing the bits for the unrelated hwcaps |
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FJATHHPC, FJDES and FJAES respectively. In GNU/Linux we opted to |
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keep the old hwcaps in Tag_GNU_Sparc_HWCAPS and allocate bits for |
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FJATHHPC, FJDES and JFAES in Tag_GNU_Sparc_HWCAPS2. */ |
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/* These values match the AV_SPARC_* hwcap bits defined under Solaris. */ |
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#define ELF_SPARC_HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */ |
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#define ELF_SPARC_HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */ |
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#define ELF_SPARC_HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */ |
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#define ELF_SPARC_HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */ |
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#define ELF_SPARC_HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */ |
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#define ELF_SPARC_HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */ |
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#define ELF_SPARC_HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */ |
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#define ELF_SPARC_HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */ |
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#define ELF_SPARC_HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */ |
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#define ELF_SPARC_HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */ |
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#define ELF_SPARC_HWCAP_PAUSE 0x08000000 /* Pause insn */ |
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#define ELF_SPARC_HWCAP_PAUSE 0x08000000 /* Pause insn */ |
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#define ELF_SPARC_HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */ |
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#define ELF_SPARC_HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */ |
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#define ELF_SPARC_HWCAP_CRC32C 0x20000000 /* CRC32C insn */ |
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#define ELF_SPARC_HWCAP_CRC32C 0x20000000 /* CRC32C insn */ |
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#define ELF_SPARC_HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */ |
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#define ELF_SPARC_HWCAP2_VIS3B 0x00000002 /* Subset of VIS3 present on sparc64 X+ */ |
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#define ELF_SPARC_HWCAP2_ADP 0x00000004 /* Application Data Protection */ |
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#define ELF_SPARC_HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */ |
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#define ELF_SPARC_HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */ |
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#define ELF_SPARC_HWCAP2_XMPMUL 0x00000020 /* XOR multiple precision multiply */ |
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#define ELF_SPARC_HWCAP2_XMONT 0x00000040 /* XOR Montgomery mult/sqr instructions */ |
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#define ELF_SPARC_HWCAP2_NSEC \ |
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0x00000080 /* pause insn with support for nsec timings */ |
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#define ELF_SPARC_HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */ |
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#define ELF_SPARC_HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */ |
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#define ELF_SPARC_HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */ |
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