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Rev 5068 Rev 6110
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#define PCI_CHIP_CHERRYVIEW_0		0x22b0
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#define PCI_CHIP_CHERRYVIEW_0		0x22b0
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#define PCI_CHIP_CHERRYVIEW_1		0x22b1
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#define PCI_CHIP_CHERRYVIEW_1		0x22b1
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#define PCI_CHIP_CHERRYVIEW_2		0x22b2
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#define PCI_CHIP_CHERRYVIEW_2		0x22b2
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#define PCI_CHIP_CHERRYVIEW_3		0x22b3
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#define PCI_CHIP_CHERRYVIEW_3		0x22b3
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#define PCI_CHIP_SKYLAKE_DT_GT1		0x1902
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#define PCI_CHIP_SKYLAKE_ULT_GT1	0x1906
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#define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A /* Reserved */
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#define PCI_CHIP_SKYLAKE_ULX_GT1	0x190E /* Reserved */
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#define PCI_CHIP_SKYLAKE_DT_GT2		0x1912
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#define PCI_CHIP_SKYLAKE_FUSED0_GT2	0x1913 /* Reserved */
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#define PCI_CHIP_SKYLAKE_FUSED1_GT2	0x1915 /* Reserved */
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#define PCI_CHIP_SKYLAKE_ULT_GT2	0x1916
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#define PCI_CHIP_SKYLAKE_FUSED2_GT2	0x1917 /* Reserved */
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#define PCI_CHIP_SKYLAKE_SRV_GT2	0x191A /* Reserved */
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#define PCI_CHIP_SKYLAKE_HALO_GT2	0x191B
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#define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
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#define PCI_CHIP_SKYLAKE_ULX_GT2	0x191E
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#define PCI_CHIP_SKYLAKE_MOBILE_GT2	0x1921 /* Reserved */
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#define PCI_CHIP_SKYLAKE_GT3		0x1926
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#define PCI_CHIP_SKYLAKE_HALO_GT3	0x192B /* Reserved */
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#define PCI_CHIP_SKYLAKE_SRV_GT4	0x192A
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#define PCI_CHIP_SKYLAKE_DT_GT4		0x1932
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#define PCI_CHIP_SKYLAKE_SRV_GT4X	0x193A
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#define PCI_CHIP_SKYLAKE_H_GT4		0x193B
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#define PCI_CHIP_SKYLAKE_WKS_GT4	0x193D
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#define PCI_CHIP_BROXTON_0		0x0A84
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#define PCI_CHIP_BROXTON_1		0x1A84
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#define PCI_CHIP_BROXTON_2		0x5A84
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#define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \
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#define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \
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				 (devid) == PCI_CHIP_I915_GM || \
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				 (devid) == PCI_CHIP_I915_GM || \
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				 (devid) == PCI_CHIP_I945_GM || \
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				 (devid) == PCI_CHIP_I945_GM || \
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				 (devid) == PCI_CHIP_I945_GME || \
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				 (devid) == PCI_CHIP_I945_GME || \
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				 (devid) == PCI_CHIP_CHERRYVIEW_3)
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				 (devid) == PCI_CHIP_CHERRYVIEW_3)
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#define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
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#define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
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				 IS_CHERRYVIEW(devid))
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#define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
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#define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2)
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#define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_GT3	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3)
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#define IS_SKL_GT4(devid)	((devid) == PCI_CHIP_SKYLAKE_SRV_GT4	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_DT_GT4	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_H_GT4	|| \
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				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT4)
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#define IS_SKYLAKE(devid)	(IS_SKL_GT1(devid) || \
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				 IS_SKL_GT2(devid) || \
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				 IS_SKL_GT3(devid) || \
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				 IS_SKL_GT4(devid))
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#define IS_BROXTON(devid)	((devid) == PCI_CHIP_BROXTON_0	|| \
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				 (devid) == PCI_CHIP_BROXTON_1	|| \
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				 (devid) == PCI_CHIP_BROXTON_2)
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#define IS_GEN9(devid)		(IS_SKYLAKE(devid) || \
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				 IS_CHERRYVIEW(devid))
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				 IS_BROXTON(devid))
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#define IS_9XX(dev)		(IS_GEN3(dev) || \
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#define IS_9XX(dev)		(IS_GEN3(dev) || \
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				 IS_GEN4(dev) || \
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				 IS_GEN4(dev) || \
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				 IS_GEN5(dev) || \
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				 IS_GEN5(dev) || \
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				 IS_GEN6(dev) || \
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				 IS_GEN6(dev) || \
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				 IS_GEN7(dev) || \
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				 IS_GEN7(dev) || \
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				 IS_GEN8(dev) || \