Rev 5068 | Rev 5374 | Go to most recent revision | Only display areas with differences | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 5068 | Rev 5368 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
3 | * All Rights Reserved. |
3 | * All Rights Reserved. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the |
6 | * copy of this software and associated documentation files (the |
7 | * "Software"), to deal in the Software without restriction, including |
7 | * "Software"), to deal in the Software without restriction, including |
8 | * without limitation the rights to use, copy, modify, merge, publish, |
8 | * without limitation the rights to use, copy, modify, merge, publish, |
9 | * distribute, sub license, and/or sell copies of the Software, and to |
9 | * distribute, sub license, and/or sell copies of the Software, and to |
10 | * permit persons to whom the Software is furnished to do so, subject to |
10 | * permit persons to whom the Software is furnished to do so, subject to |
11 | * the following conditions: |
11 | * the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice (including the |
13 | * The above copyright notice and this permission notice (including the |
14 | * next paragraph) shall be included in all copies or substantial portions |
14 | * next paragraph) shall be included in all copies or substantial portions |
15 | * of the Software. |
15 | * of the Software. |
16 | * |
16 | * |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
24 | * |
24 | * |
25 | */ |
25 | */ |
26 | 26 | ||
27 | #ifndef _I915_DRM_H_ |
27 | #ifndef _I915_DRM_H_ |
28 | #define _I915_DRM_H_ |
28 | #define _I915_DRM_H_ |
29 | 29 | ||
30 | #include "drm.h" |
30 | #include "drm.h" |
31 | 31 | ||
32 | /* Please note that modifications to all structs defined here are |
32 | /* Please note that modifications to all structs defined here are |
33 | * subject to backwards-compatibility constraints. |
33 | * subject to backwards-compatibility constraints. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | /** |
36 | /** |
37 | * DOC: uevents generated by i915 on it's device node |
37 | * DOC: uevents generated by i915 on it's device node |
38 | * |
38 | * |
39 | * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch |
39 | * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch |
40 | * event from the gpu l3 cache. Additional information supplied is ROW, |
40 | * event from the gpu l3 cache. Additional information supplied is ROW, |
41 | * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep |
41 | * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep |
42 | * track of these events and if a specific cache-line seems to have a |
42 | * track of these events and if a specific cache-line seems to have a |
43 | * persistent error remap it with the l3 remapping tool supplied in |
43 | * persistent error remap it with the l3 remapping tool supplied in |
44 | * intel-gpu-tools. The value supplied with the event is always 1. |
44 | * intel-gpu-tools. The value supplied with the event is always 1. |
45 | * |
45 | * |
46 | * I915_ERROR_UEVENT - Generated upon error detection, currently only via |
46 | * I915_ERROR_UEVENT - Generated upon error detection, currently only via |
47 | * hangcheck. The error detection event is a good indicator of when things |
47 | * hangcheck. The error detection event is a good indicator of when things |
48 | * began to go badly. The value supplied with the event is a 1 upon error |
48 | * began to go badly. The value supplied with the event is a 1 upon error |
49 | * detection, and a 0 upon reset completion, signifying no more error |
49 | * detection, and a 0 upon reset completion, signifying no more error |
50 | * exists. NOTE: Disabling hangcheck or reset via module parameter will |
50 | * exists. NOTE: Disabling hangcheck or reset via module parameter will |
51 | * cause the related events to not be seen. |
51 | * cause the related events to not be seen. |
52 | * |
52 | * |
53 | * I915_RESET_UEVENT - Event is generated just before an attempt to reset the |
53 | * I915_RESET_UEVENT - Event is generated just before an attempt to reset the |
54 | * the GPU. The value supplied with the event is always 1. NOTE: Disable |
54 | * the GPU. The value supplied with the event is always 1. NOTE: Disable |
55 | * reset via module parameter will cause this event to not be seen. |
55 | * reset via module parameter will cause this event to not be seen. |
56 | */ |
56 | */ |
57 | #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" |
57 | #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" |
58 | #define I915_ERROR_UEVENT "ERROR" |
58 | #define I915_ERROR_UEVENT "ERROR" |
59 | #define I915_RESET_UEVENT "RESET" |
59 | #define I915_RESET_UEVENT "RESET" |
60 | 60 | ||
61 | /* Each region is a minimum of 16k, and there are at most 255 of them. |
61 | /* Each region is a minimum of 16k, and there are at most 255 of them. |
62 | */ |
62 | */ |
63 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use |
63 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use |
64 | * of chars for next/prev indices */ |
64 | * of chars for next/prev indices */ |
65 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 |
65 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 |
66 | 66 | ||
67 | typedef struct _drm_i915_init { |
67 | typedef struct _drm_i915_init { |
68 | enum { |
68 | enum { |
69 | I915_INIT_DMA = 0x01, |
69 | I915_INIT_DMA = 0x01, |
70 | I915_CLEANUP_DMA = 0x02, |
70 | I915_CLEANUP_DMA = 0x02, |
71 | I915_RESUME_DMA = 0x03 |
71 | I915_RESUME_DMA = 0x03 |
72 | } func; |
72 | } func; |
73 | unsigned int mmio_offset; |
73 | unsigned int mmio_offset; |
74 | int sarea_priv_offset; |
74 | int sarea_priv_offset; |
75 | unsigned int ring_start; |
75 | unsigned int ring_start; |
76 | unsigned int ring_end; |
76 | unsigned int ring_end; |
77 | unsigned int ring_size; |
77 | unsigned int ring_size; |
78 | unsigned int front_offset; |
78 | unsigned int front_offset; |
79 | unsigned int back_offset; |
79 | unsigned int back_offset; |
80 | unsigned int depth_offset; |
80 | unsigned int depth_offset; |
81 | unsigned int w; |
81 | unsigned int w; |
82 | unsigned int h; |
82 | unsigned int h; |
83 | unsigned int pitch; |
83 | unsigned int pitch; |
84 | unsigned int pitch_bits; |
84 | unsigned int pitch_bits; |
85 | unsigned int back_pitch; |
85 | unsigned int back_pitch; |
86 | unsigned int depth_pitch; |
86 | unsigned int depth_pitch; |
87 | unsigned int cpp; |
87 | unsigned int cpp; |
88 | unsigned int chipset; |
88 | unsigned int chipset; |
89 | } drm_i915_init_t; |
89 | } drm_i915_init_t; |
90 | 90 | ||
91 | typedef struct _drm_i915_sarea { |
91 | typedef struct _drm_i915_sarea { |
92 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; |
92 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; |
93 | int last_upload; /* last time texture was uploaded */ |
93 | int last_upload; /* last time texture was uploaded */ |
94 | int last_enqueue; /* last time a buffer was enqueued */ |
94 | int last_enqueue; /* last time a buffer was enqueued */ |
95 | int last_dispatch; /* age of the most recently dispatched buffer */ |
95 | int last_dispatch; /* age of the most recently dispatched buffer */ |
96 | int ctxOwner; /* last context to upload state */ |
96 | int ctxOwner; /* last context to upload state */ |
97 | int texAge; |
97 | int texAge; |
98 | int pf_enabled; /* is pageflipping allowed? */ |
98 | int pf_enabled; /* is pageflipping allowed? */ |
99 | int pf_active; |
99 | int pf_active; |
100 | int pf_current_page; /* which buffer is being displayed? */ |
100 | int pf_current_page; /* which buffer is being displayed? */ |
101 | int perf_boxes; /* performance boxes to be displayed */ |
101 | int perf_boxes; /* performance boxes to be displayed */ |
102 | int width, height; /* screen size in pixels */ |
102 | int width, height; /* screen size in pixels */ |
103 | 103 | ||
104 | drm_handle_t front_handle; |
104 | drm_handle_t front_handle; |
105 | int front_offset; |
105 | int front_offset; |
106 | int front_size; |
106 | int front_size; |
107 | 107 | ||
108 | drm_handle_t back_handle; |
108 | drm_handle_t back_handle; |
109 | int back_offset; |
109 | int back_offset; |
110 | int back_size; |
110 | int back_size; |
111 | 111 | ||
112 | drm_handle_t depth_handle; |
112 | drm_handle_t depth_handle; |
113 | int depth_offset; |
113 | int depth_offset; |
114 | int depth_size; |
114 | int depth_size; |
115 | 115 | ||
116 | drm_handle_t tex_handle; |
116 | drm_handle_t tex_handle; |
117 | int tex_offset; |
117 | int tex_offset; |
118 | int tex_size; |
118 | int tex_size; |
119 | int log_tex_granularity; |
119 | int log_tex_granularity; |
120 | int pitch; |
120 | int pitch; |
121 | int rotation; /* 0, 90, 180 or 270 */ |
121 | int rotation; /* 0, 90, 180 or 270 */ |
122 | int rotated_offset; |
122 | int rotated_offset; |
123 | int rotated_size; |
123 | int rotated_size; |
124 | int rotated_pitch; |
124 | int rotated_pitch; |
125 | int virtualX, virtualY; |
125 | int virtualX, virtualY; |
126 | 126 | ||
127 | unsigned int front_tiled; |
127 | unsigned int front_tiled; |
128 | unsigned int back_tiled; |
128 | unsigned int back_tiled; |
129 | unsigned int depth_tiled; |
129 | unsigned int depth_tiled; |
130 | unsigned int rotated_tiled; |
130 | unsigned int rotated_tiled; |
131 | unsigned int rotated2_tiled; |
131 | unsigned int rotated2_tiled; |
132 | 132 | ||
133 | int pipeA_x; |
133 | int pipeA_x; |
134 | int pipeA_y; |
134 | int pipeA_y; |
135 | int pipeA_w; |
135 | int pipeA_w; |
136 | int pipeA_h; |
136 | int pipeA_h; |
137 | int pipeB_x; |
137 | int pipeB_x; |
138 | int pipeB_y; |
138 | int pipeB_y; |
139 | int pipeB_w; |
139 | int pipeB_w; |
140 | int pipeB_h; |
140 | int pipeB_h; |
141 | 141 | ||
142 | /* fill out some space for old userspace triple buffer */ |
142 | /* fill out some space for old userspace triple buffer */ |
143 | drm_handle_t unused_handle; |
143 | drm_handle_t unused_handle; |
144 | __u32 unused1, unused2, unused3; |
144 | __u32 unused1, unused2, unused3; |
145 | 145 | ||
146 | /* buffer object handles for static buffers. May change |
146 | /* buffer object handles for static buffers. May change |
147 | * over the lifetime of the client. |
147 | * over the lifetime of the client. |
148 | */ |
148 | */ |
149 | __u32 front_bo_handle; |
149 | __u32 front_bo_handle; |
150 | __u32 back_bo_handle; |
150 | __u32 back_bo_handle; |
151 | __u32 unused_bo_handle; |
151 | __u32 unused_bo_handle; |
152 | __u32 depth_bo_handle; |
152 | __u32 depth_bo_handle; |
153 | 153 | ||
154 | } drm_i915_sarea_t; |
154 | } drm_i915_sarea_t; |
155 | 155 | ||
156 | /* due to userspace building against these headers we need some compat here */ |
156 | /* due to userspace building against these headers we need some compat here */ |
157 | #define planeA_x pipeA_x |
157 | #define planeA_x pipeA_x |
158 | #define planeA_y pipeA_y |
158 | #define planeA_y pipeA_y |
159 | #define planeA_w pipeA_w |
159 | #define planeA_w pipeA_w |
160 | #define planeA_h pipeA_h |
160 | #define planeA_h pipeA_h |
161 | #define planeB_x pipeB_x |
161 | #define planeB_x pipeB_x |
162 | #define planeB_y pipeB_y |
162 | #define planeB_y pipeB_y |
163 | #define planeB_w pipeB_w |
163 | #define planeB_w pipeB_w |
164 | #define planeB_h pipeB_h |
164 | #define planeB_h pipeB_h |
165 | 165 | ||
166 | /* Flags for perf_boxes |
166 | /* Flags for perf_boxes |
167 | */ |
167 | */ |
168 | #define I915_BOX_RING_EMPTY 0x1 |
168 | #define I915_BOX_RING_EMPTY 0x1 |
169 | #define I915_BOX_FLIP 0x2 |
169 | #define I915_BOX_FLIP 0x2 |
170 | #define I915_BOX_WAIT 0x4 |
170 | #define I915_BOX_WAIT 0x4 |
171 | #define I915_BOX_TEXTURE_LOAD 0x8 |
171 | #define I915_BOX_TEXTURE_LOAD 0x8 |
172 | #define I915_BOX_LOST_CONTEXT 0x10 |
172 | #define I915_BOX_LOST_CONTEXT 0x10 |
173 | 173 | ||
174 | /* I915 specific ioctls |
174 | /* I915 specific ioctls |
175 | * The device specific ioctl range is 0x40 to 0x79. |
175 | * The device specific ioctl range is 0x40 to 0x79. |
176 | */ |
176 | */ |
177 | #define DRM_I915_INIT 0x00 |
177 | #define DRM_I915_INIT 0x00 |
178 | #define DRM_I915_FLUSH 0x01 |
178 | #define DRM_I915_FLUSH 0x01 |
179 | #define DRM_I915_FLIP 0x02 |
179 | #define DRM_I915_FLIP 0x02 |
180 | #define DRM_I915_BATCHBUFFER 0x03 |
180 | #define DRM_I915_BATCHBUFFER 0x03 |
181 | #define DRM_I915_IRQ_EMIT 0x04 |
181 | #define DRM_I915_IRQ_EMIT 0x04 |
182 | #define DRM_I915_IRQ_WAIT 0x05 |
182 | #define DRM_I915_IRQ_WAIT 0x05 |
183 | #define DRM_I915_GETPARAM 0x06 |
183 | #define DRM_I915_GETPARAM 0x06 |
184 | #define DRM_I915_SETPARAM 0x07 |
184 | #define DRM_I915_SETPARAM 0x07 |
185 | #define DRM_I915_ALLOC 0x08 |
185 | #define DRM_I915_ALLOC 0x08 |
186 | #define DRM_I915_FREE 0x09 |
186 | #define DRM_I915_FREE 0x09 |
187 | #define DRM_I915_INIT_HEAP 0x0a |
187 | #define DRM_I915_INIT_HEAP 0x0a |
188 | #define DRM_I915_CMDBUFFER 0x0b |
188 | #define DRM_I915_CMDBUFFER 0x0b |
189 | #define DRM_I915_DESTROY_HEAP 0x0c |
189 | #define DRM_I915_DESTROY_HEAP 0x0c |
190 | #define DRM_I915_SET_VBLANK_PIPE 0x0d |
190 | #define DRM_I915_SET_VBLANK_PIPE 0x0d |
191 | #define DRM_I915_GET_VBLANK_PIPE 0x0e |
191 | #define DRM_I915_GET_VBLANK_PIPE 0x0e |
192 | #define DRM_I915_VBLANK_SWAP 0x0f |
192 | #define DRM_I915_VBLANK_SWAP 0x0f |
193 | #define DRM_I915_HWS_ADDR 0x11 |
193 | #define DRM_I915_HWS_ADDR 0x11 |
194 | #define DRM_I915_GEM_INIT 0x13 |
194 | #define DRM_I915_GEM_INIT 0x13 |
195 | #define DRM_I915_GEM_EXECBUFFER 0x14 |
195 | #define DRM_I915_GEM_EXECBUFFER 0x14 |
196 | #define DRM_I915_GEM_PIN 0x15 |
196 | #define DRM_I915_GEM_PIN 0x15 |
197 | #define DRM_I915_GEM_UNPIN 0x16 |
197 | #define DRM_I915_GEM_UNPIN 0x16 |
198 | #define DRM_I915_GEM_BUSY 0x17 |
198 | #define DRM_I915_GEM_BUSY 0x17 |
199 | #define DRM_I915_GEM_THROTTLE 0x18 |
199 | #define DRM_I915_GEM_THROTTLE 0x18 |
200 | #define DRM_I915_GEM_ENTERVT 0x19 |
200 | #define DRM_I915_GEM_ENTERVT 0x19 |
201 | #define DRM_I915_GEM_LEAVEVT 0x1a |
201 | #define DRM_I915_GEM_LEAVEVT 0x1a |
202 | #define DRM_I915_GEM_CREATE 0x1b |
202 | #define DRM_I915_GEM_CREATE 0x1b |
203 | #define DRM_I915_GEM_PREAD 0x1c |
203 | #define DRM_I915_GEM_PREAD 0x1c |
204 | #define DRM_I915_GEM_PWRITE 0x1d |
204 | #define DRM_I915_GEM_PWRITE 0x1d |
205 | #define DRM_I915_GEM_MMAP 0x1e |
205 | #define DRM_I915_GEM_MMAP 0x1e |
206 | #define DRM_I915_GEM_SET_DOMAIN 0x1f |
206 | #define DRM_I915_GEM_SET_DOMAIN 0x1f |
207 | #define DRM_I915_GEM_SW_FINISH 0x20 |
207 | #define DRM_I915_GEM_SW_FINISH 0x20 |
208 | #define DRM_I915_GEM_SET_TILING 0x21 |
208 | #define DRM_I915_GEM_SET_TILING 0x21 |
209 | #define DRM_I915_GEM_GET_TILING 0x22 |
209 | #define DRM_I915_GEM_GET_TILING 0x22 |
210 | #define DRM_I915_GEM_GET_APERTURE 0x23 |
210 | #define DRM_I915_GEM_GET_APERTURE 0x23 |
211 | #define DRM_I915_GEM_MMAP_GTT 0x24 |
211 | #define DRM_I915_GEM_MMAP_GTT 0x24 |
212 | #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 |
212 | #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 |
213 | #define DRM_I915_GEM_MADVISE 0x26 |
213 | #define DRM_I915_GEM_MADVISE 0x26 |
214 | #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 |
214 | #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 |
215 | #define DRM_I915_OVERLAY_ATTRS 0x28 |
215 | #define DRM_I915_OVERLAY_ATTRS 0x28 |
216 | #define DRM_I915_GEM_EXECBUFFER2 0x29 |
216 | #define DRM_I915_GEM_EXECBUFFER2 0x29 |
217 | #define DRM_I915_GET_SPRITE_COLORKEY 0x2a |
217 | #define DRM_I915_GET_SPRITE_COLORKEY 0x2a |
218 | #define DRM_I915_SET_SPRITE_COLORKEY 0x2b |
218 | #define DRM_I915_SET_SPRITE_COLORKEY 0x2b |
219 | #define DRM_I915_GEM_WAIT 0x2c |
219 | #define DRM_I915_GEM_WAIT 0x2c |
220 | #define DRM_I915_GEM_CONTEXT_CREATE 0x2d |
220 | #define DRM_I915_GEM_CONTEXT_CREATE 0x2d |
221 | #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e |
221 | #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e |
222 | #define DRM_I915_GEM_SET_CACHING 0x2f |
222 | #define DRM_I915_GEM_SET_CACHING 0x2f |
223 | #define DRM_I915_GEM_GET_CACHING 0x30 |
223 | #define DRM_I915_GEM_GET_CACHING 0x30 |
224 | #define DRM_I915_REG_READ 0x31 |
224 | #define DRM_I915_REG_READ 0x31 |
225 | #define DRM_I915_GET_RESET_STATS 0x32 |
225 | #define DRM_I915_GET_RESET_STATS 0x32 |
226 | #define DRM_I915_GEM_USERPTR 0x33 |
226 | #define DRM_I915_GEM_USERPTR 0x33 |
227 | 227 | ||
228 | #define DRM_IOCTL_I915_INIT |
228 | #define DRM_IOCTL_I915_INIT |
229 | #define DRM_IOCTL_I915_FLUSH |
229 | #define DRM_IOCTL_I915_FLUSH |
230 | #define DRM_IOCTL_I915_FLIP |
230 | #define DRM_IOCTL_I915_FLIP |
231 | #define DRM_IOCTL_I915_BATCHBUFFER |
231 | #define DRM_IOCTL_I915_BATCHBUFFER |
232 | #define DRM_IOCTL_I915_IRQ_EMIT |
232 | #define DRM_IOCTL_I915_IRQ_EMIT |
233 | #define DRM_IOCTL_I915_IRQ_WAIT |
233 | #define DRM_IOCTL_I915_IRQ_WAIT |
234 | #define DRM_IOCTL_I915_GETPARAM SRV_I915_GET_PARAM |
234 | #define DRM_IOCTL_I915_GETPARAM SRV_I915_GET_PARAM |
235 | #define DRM_IOCTL_I915_SETPARAM |
235 | #define DRM_IOCTL_I915_SETPARAM |
236 | #define DRM_IOCTL_I915_ALLOC |
236 | #define DRM_IOCTL_I915_ALLOC |
237 | #define DRM_IOCTL_I915_FREE |
237 | #define DRM_IOCTL_I915_FREE |
238 | #define DRM_IOCTL_I915_INIT_HEAP |
238 | #define DRM_IOCTL_I915_INIT_HEAP |
239 | #define DRM_IOCTL_I915_CMDBUFFER |
239 | #define DRM_IOCTL_I915_CMDBUFFER |
240 | #define DRM_IOCTL_I915_DESTROY_HEAP |
240 | #define DRM_IOCTL_I915_DESTROY_HEAP |
241 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE |
241 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE |
242 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE |
242 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE |
243 | #define DRM_IOCTL_I915_VBLANK_SWAP |
243 | #define DRM_IOCTL_I915_VBLANK_SWAP |
244 | #define DRM_IOCTL_I915_HWS_ADDR |
244 | #define DRM_IOCTL_I915_HWS_ADDR |
245 | #define DRM_IOCTL_I915_GEM_INIT |
245 | #define DRM_IOCTL_I915_GEM_INIT |
246 | #define DRM_IOCTL_I915_GEM_EXECBUFFER |
246 | #define DRM_IOCTL_I915_GEM_EXECBUFFER |
247 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2 SRV_I915_GEM_EXECBUFFER2 |
247 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2 SRV_I915_GEM_EXECBUFFER2 |
248 | #define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN |
248 | #define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN |
249 | #define DRM_IOCTL_I915_GEM_UNPIN SRV_I915_GEM_UNPIN |
249 | #define DRM_IOCTL_I915_GEM_UNPIN SRV_I915_GEM_UNPIN |
250 | #define DRM_IOCTL_I915_GEM_BUSY SRV_I915_GEM_BUSY |
250 | #define DRM_IOCTL_I915_GEM_BUSY SRV_I915_GEM_BUSY |
251 | #define DRM_IOCTL_I915_GEM_SET_CACHEING SRV_I915_GEM_SET_CACHING |
251 | #define DRM_IOCTL_I915_GEM_SET_CACHEING SRV_I915_GEM_SET_CACHING |
252 | #define DRM_IOCTL_I915_GEM_GET_CACHEING |
252 | #define DRM_IOCTL_I915_GEM_GET_CACHEING SRV_I915_GEM_GET_CACHING |
253 | #define DRM_IOCTL_I915_GEM_THROTTLE SRV_I915_GEM_THROTTLE |
253 | #define DRM_IOCTL_I915_GEM_THROTTLE SRV_I915_GEM_THROTTLE |
254 | #define DRM_IOCTL_I915_GEM_ENTERVT |
254 | #define DRM_IOCTL_I915_GEM_ENTERVT |
255 | #define DRM_IOCTL_I915_GEM_LEAVEVT |
255 | #define DRM_IOCTL_I915_GEM_LEAVEVT |
256 | #define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE |
256 | #define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE |
257 | #define DRM_IOCTL_I915_GEM_PREAD |
257 | #define DRM_IOCTL_I915_GEM_PREAD |
258 | #define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE |
258 | #define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE |
259 | #define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP |
259 | #define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP |
260 | #define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT |
260 | #define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT |
261 | #define DRM_IOCTL_I915_GEM_SET_DOMAIN SRV_I915_GEM_SET_DOMAIN |
261 | #define DRM_IOCTL_I915_GEM_SET_DOMAIN SRV_I915_GEM_SET_DOMAIN |
262 | #define DRM_IOCTL_I915_GEM_SW_FINISH |
262 | #define DRM_IOCTL_I915_GEM_SW_FINISH |
263 | #define DRM_IOCTL_I915_GEM_SET_TILING SRV_I915_GEM_SET_TILING |
263 | #define DRM_IOCTL_I915_GEM_SET_TILING SRV_I915_GEM_SET_TILING |
264 | #define DRM_IOCTL_I915_GEM_GET_TILING SRV_I915_GEM_GET_TILING |
264 | #define DRM_IOCTL_I915_GEM_GET_TILING SRV_I915_GEM_GET_TILING |
265 | #define DRM_IOCTL_I915_GEM_GET_APERTURE SRV_I915_GEM_GET_APERTURE |
265 | #define DRM_IOCTL_I915_GEM_GET_APERTURE SRV_I915_GEM_GET_APERTURE |
266 | #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID |
266 | #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID |
267 | #define DRM_IOCTL_I915_GEM_MADVISE |
267 | #define DRM_IOCTL_I915_GEM_MADVISE |
268 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE |
268 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE |
269 | #define DRM_IOCTL_I915_OVERLAY_ATTRS |
269 | #define DRM_IOCTL_I915_OVERLAY_ATTRS |
270 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY |
270 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY |
271 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY |
271 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY |
272 | #define DRM_IOCTL_I915_GEM_WAIT SRV_I915_GEM_WAIT |
272 | #define DRM_IOCTL_I915_GEM_WAIT SRV_I915_GEM_WAIT |
273 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE SRV_I915_GEM_CONTEXT_CREATE |
273 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE SRV_I915_GEM_CONTEXT_CREATE |
274 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY SRV_I915_GEM_CONTEXT_DESTROY |
274 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY SRV_I915_GEM_CONTEXT_DESTROY |
275 | #define DRM_IOCTL_I915_REG_READ SRV_I915_REG_READ |
275 | #define DRM_IOCTL_I915_REG_READ SRV_I915_REG_READ |
276 | 276 | ||
277 | 277 | ||
278 | /* Allow drivers to submit batchbuffers directly to hardware, relying |
278 | /* Allow drivers to submit batchbuffers directly to hardware, relying |
279 | * on the security mechanisms provided by hardware. |
279 | * on the security mechanisms provided by hardware. |
280 | */ |
280 | */ |
281 | typedef struct drm_i915_batchbuffer { |
281 | typedef struct drm_i915_batchbuffer { |
282 | int start; /* agp offset */ |
282 | int start; /* agp offset */ |
283 | int used; /* nr bytes in use */ |
283 | int used; /* nr bytes in use */ |
284 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
284 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
285 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
285 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
286 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
286 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
287 | struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ |
287 | struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ |
288 | } drm_i915_batchbuffer_t; |
288 | } drm_i915_batchbuffer_t; |
289 | 289 | ||
290 | /* As above, but pass a pointer to userspace buffer which can be |
290 | /* As above, but pass a pointer to userspace buffer which can be |
291 | * validated by the kernel prior to sending to hardware. |
291 | * validated by the kernel prior to sending to hardware. |
292 | */ |
292 | */ |
293 | typedef struct _drm_i915_cmdbuffer { |
293 | typedef struct _drm_i915_cmdbuffer { |
294 | char *buf; /* pointer to userspace command buffer */ |
294 | char *buf; /* pointer to userspace command buffer */ |
295 | int sz; /* nr bytes in buf */ |
295 | int sz; /* nr bytes in buf */ |
296 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
296 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
297 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
297 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
298 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
298 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
299 | struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ |
299 | struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ |
300 | } drm_i915_cmdbuffer_t; |
300 | } drm_i915_cmdbuffer_t; |
301 | 301 | ||
302 | /* Userspace can request & wait on irq's: |
302 | /* Userspace can request & wait on irq's: |
303 | */ |
303 | */ |
304 | typedef struct drm_i915_irq_emit { |
304 | typedef struct drm_i915_irq_emit { |
305 | int *irq_seq; |
305 | int *irq_seq; |
306 | } drm_i915_irq_emit_t; |
306 | } drm_i915_irq_emit_t; |
307 | 307 | ||
308 | typedef struct drm_i915_irq_wait { |
308 | typedef struct drm_i915_irq_wait { |
309 | int irq_seq; |
309 | int irq_seq; |
310 | } drm_i915_irq_wait_t; |
310 | } drm_i915_irq_wait_t; |
311 | 311 | ||
312 | /* Ioctl to query kernel params: |
312 | /* Ioctl to query kernel params: |
313 | */ |
313 | */ |
314 | #define I915_PARAM_IRQ_ACTIVE 1 |
314 | #define I915_PARAM_IRQ_ACTIVE 1 |
315 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 |
315 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 |
316 | #define I915_PARAM_LAST_DISPATCH 3 |
316 | #define I915_PARAM_LAST_DISPATCH 3 |
317 | #define I915_PARAM_CHIPSET_ID 4 |
317 | #define I915_PARAM_CHIPSET_ID 4 |
318 | #define I915_PARAM_HAS_GEM 5 |
318 | #define I915_PARAM_HAS_GEM 5 |
319 | #define I915_PARAM_NUM_FENCES_AVAIL 6 |
319 | #define I915_PARAM_NUM_FENCES_AVAIL 6 |
320 | #define I915_PARAM_HAS_OVERLAY 7 |
320 | #define I915_PARAM_HAS_OVERLAY 7 |
321 | #define I915_PARAM_HAS_PAGEFLIPPING 8 |
321 | #define I915_PARAM_HAS_PAGEFLIPPING 8 |
322 | #define I915_PARAM_HAS_EXECBUF2 9 |
322 | #define I915_PARAM_HAS_EXECBUF2 9 |
323 | #define I915_PARAM_HAS_BSD 10 |
323 | #define I915_PARAM_HAS_BSD 10 |
324 | #define I915_PARAM_HAS_BLT 11 |
324 | #define I915_PARAM_HAS_BLT 11 |
325 | #define I915_PARAM_HAS_RELAXED_FENCING 12 |
325 | #define I915_PARAM_HAS_RELAXED_FENCING 12 |
326 | #define I915_PARAM_HAS_COHERENT_RINGS 13 |
326 | #define I915_PARAM_HAS_COHERENT_RINGS 13 |
327 | #define I915_PARAM_HAS_EXEC_CONSTANTS 14 |
327 | #define I915_PARAM_HAS_EXEC_CONSTANTS 14 |
328 | #define I915_PARAM_HAS_RELAXED_DELTA 15 |
328 | #define I915_PARAM_HAS_RELAXED_DELTA 15 |
329 | #define I915_PARAM_HAS_GEN7_SOL_RESET 16 |
329 | #define I915_PARAM_HAS_GEN7_SOL_RESET 16 |
330 | #define I915_PARAM_HAS_LLC 17 |
330 | #define I915_PARAM_HAS_LLC 17 |
331 | #define I915_PARAM_HAS_ALIASING_PPGTT 18 |
331 | #define I915_PARAM_HAS_ALIASING_PPGTT 18 |
332 | #define I915_PARAM_HAS_WAIT_TIMEOUT 19 |
332 | #define I915_PARAM_HAS_WAIT_TIMEOUT 19 |
333 | #define I915_PARAM_HAS_SEMAPHORES 20 |
333 | #define I915_PARAM_HAS_SEMAPHORES 20 |
334 | #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 |
334 | #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 |
335 | #define I915_PARAM_HAS_VEBOX 22 |
335 | #define I915_PARAM_HAS_VEBOX 22 |
336 | #define I915_PARAM_HAS_SECURE_BATCHES 23 |
336 | #define I915_PARAM_HAS_SECURE_BATCHES 23 |
337 | #define I915_PARAM_HAS_PINNED_BATCHES 24 |
337 | #define I915_PARAM_HAS_PINNED_BATCHES 24 |
338 | #define I915_PARAM_HAS_EXEC_NO_RELOC 25 |
338 | #define I915_PARAM_HAS_EXEC_NO_RELOC 25 |
339 | #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 |
339 | #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 |
340 | #define I915_PARAM_HAS_WT 27 |
340 | #define I915_PARAM_HAS_WT 27 |
341 | #define I915_PARAM_CMD_PARSER_VERSION 28 |
341 | #define I915_PARAM_CMD_PARSER_VERSION 28 |
- | 342 | #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 |
|
342 | 343 | ||
343 | typedef struct drm_i915_getparam { |
344 | typedef struct drm_i915_getparam { |
344 | int param; |
345 | int param; |
345 | int *value; |
346 | int *value; |
346 | } drm_i915_getparam_t; |
347 | } drm_i915_getparam_t; |
347 | 348 | ||
348 | /* Ioctl to set kernel params: |
349 | /* Ioctl to set kernel params: |
349 | */ |
350 | */ |
350 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 |
351 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 |
351 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 |
352 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 |
352 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 |
353 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 |
353 | #define I915_SETPARAM_NUM_USED_FENCES 4 |
354 | #define I915_SETPARAM_NUM_USED_FENCES 4 |
354 | 355 | ||
355 | typedef struct drm_i915_setparam { |
356 | typedef struct drm_i915_setparam { |
356 | int param; |
357 | int param; |
357 | int value; |
358 | int value; |
358 | } drm_i915_setparam_t; |
359 | } drm_i915_setparam_t; |
359 | 360 | ||
360 | /* A memory manager for regions of shared memory: |
361 | /* A memory manager for regions of shared memory: |
361 | */ |
362 | */ |
362 | #define I915_MEM_REGION_AGP 1 |
363 | #define I915_MEM_REGION_AGP 1 |
363 | 364 | ||
364 | typedef struct drm_i915_mem_alloc { |
365 | typedef struct drm_i915_mem_alloc { |
365 | int region; |
366 | int region; |
366 | int alignment; |
367 | int alignment; |
367 | int size; |
368 | int size; |
368 | int *region_offset; /* offset from start of fb or agp */ |
369 | int *region_offset; /* offset from start of fb or agp */ |
369 | } drm_i915_mem_alloc_t; |
370 | } drm_i915_mem_alloc_t; |
370 | 371 | ||
371 | typedef struct drm_i915_mem_free { |
372 | typedef struct drm_i915_mem_free { |
372 | int region; |
373 | int region; |
373 | int region_offset; |
374 | int region_offset; |
374 | } drm_i915_mem_free_t; |
375 | } drm_i915_mem_free_t; |
375 | 376 | ||
376 | typedef struct drm_i915_mem_init_heap { |
377 | typedef struct drm_i915_mem_init_heap { |
377 | int region; |
378 | int region; |
378 | int size; |
379 | int size; |
379 | int start; |
380 | int start; |
380 | } drm_i915_mem_init_heap_t; |
381 | } drm_i915_mem_init_heap_t; |
381 | 382 | ||
382 | /* Allow memory manager to be torn down and re-initialized (eg on |
383 | /* Allow memory manager to be torn down and re-initialized (eg on |
383 | * rotate): |
384 | * rotate): |
384 | */ |
385 | */ |
385 | typedef struct drm_i915_mem_destroy_heap { |
386 | typedef struct drm_i915_mem_destroy_heap { |
386 | int region; |
387 | int region; |
387 | } drm_i915_mem_destroy_heap_t; |
388 | } drm_i915_mem_destroy_heap_t; |
388 | 389 | ||
389 | /* Allow X server to configure which pipes to monitor for vblank signals |
390 | /* Allow X server to configure which pipes to monitor for vblank signals |
390 | */ |
391 | */ |
391 | #define DRM_I915_VBLANK_PIPE_A 1 |
392 | #define DRM_I915_VBLANK_PIPE_A 1 |
392 | #define DRM_I915_VBLANK_PIPE_B 2 |
393 | #define DRM_I915_VBLANK_PIPE_B 2 |
393 | 394 | ||
394 | typedef struct drm_i915_vblank_pipe { |
395 | typedef struct drm_i915_vblank_pipe { |
395 | int pipe; |
396 | int pipe; |
396 | } drm_i915_vblank_pipe_t; |
397 | } drm_i915_vblank_pipe_t; |
397 | 398 | ||
398 | /* Schedule buffer swap at given vertical blank: |
399 | /* Schedule buffer swap at given vertical blank: |
399 | */ |
400 | */ |
400 | typedef struct drm_i915_vblank_swap { |
401 | typedef struct drm_i915_vblank_swap { |
401 | drm_drawable_t drawable; |
402 | drm_drawable_t drawable; |
402 | enum drm_vblank_seq_type seqtype; |
403 | enum drm_vblank_seq_type seqtype; |
403 | unsigned int sequence; |
404 | unsigned int sequence; |
404 | } drm_i915_vblank_swap_t; |
405 | } drm_i915_vblank_swap_t; |
405 | 406 | ||
406 | typedef struct drm_i915_hws_addr { |
407 | typedef struct drm_i915_hws_addr { |
407 | __u64 addr; |
408 | __u64 addr; |
408 | } drm_i915_hws_addr_t; |
409 | } drm_i915_hws_addr_t; |
409 | 410 | ||
410 | struct drm_i915_gem_init { |
411 | struct drm_i915_gem_init { |
411 | /** |
412 | /** |
412 | * Beginning offset in the GTT to be managed by the DRM memory |
413 | * Beginning offset in the GTT to be managed by the DRM memory |
413 | * manager. |
414 | * manager. |
414 | */ |
415 | */ |
415 | __u64 gtt_start; |
416 | __u64 gtt_start; |
416 | /** |
417 | /** |
417 | * Ending offset in the GTT to be managed by the DRM memory |
418 | * Ending offset in the GTT to be managed by the DRM memory |
418 | * manager. |
419 | * manager. |
419 | */ |
420 | */ |
420 | __u64 gtt_end; |
421 | __u64 gtt_end; |
421 | }; |
422 | }; |
422 | 423 | ||
423 | struct drm_i915_gem_create { |
424 | struct drm_i915_gem_create { |
424 | /** |
425 | /** |
425 | * Requested size for the object. |
426 | * Requested size for the object. |
426 | * |
427 | * |
427 | * The (page-aligned) allocated size for the object will be returned. |
428 | * The (page-aligned) allocated size for the object will be returned. |
428 | */ |
429 | */ |
429 | __u64 size; |
430 | __u64 size; |
430 | /** |
431 | /** |
431 | * Returned handle for the object. |
432 | * Returned handle for the object. |
432 | * |
433 | * |
433 | * Object handles are nonzero. |
434 | * Object handles are nonzero. |
434 | */ |
435 | */ |
435 | __u32 handle; |
436 | __u32 handle; |
436 | __u32 pad; |
437 | __u32 pad; |
437 | }; |
438 | }; |
438 | 439 | ||
439 | struct drm_i915_gem_pread { |
440 | struct drm_i915_gem_pread { |
440 | /** Handle for the object being read. */ |
441 | /** Handle for the object being read. */ |
441 | __u32 handle; |
442 | __u32 handle; |
442 | __u32 pad; |
443 | __u32 pad; |
443 | /** Offset into the object to read from */ |
444 | /** Offset into the object to read from */ |
444 | __u64 offset; |
445 | __u64 offset; |
445 | /** Length of data to read */ |
446 | /** Length of data to read */ |
446 | __u64 size; |
447 | __u64 size; |
447 | /** |
448 | /** |
448 | * Pointer to write the data into. |
449 | * Pointer to write the data into. |
449 | * |
450 | * |
450 | * This is a fixed-size type for 32/64 compatibility. |
451 | * This is a fixed-size type for 32/64 compatibility. |
451 | */ |
452 | */ |
452 | __u64 data_ptr; |
453 | __u64 data_ptr; |
453 | }; |
454 | }; |
454 | 455 | ||
455 | struct drm_i915_gem_pwrite { |
456 | struct drm_i915_gem_pwrite { |
456 | /** Handle for the object being written to. */ |
457 | /** Handle for the object being written to. */ |
457 | __u32 handle; |
458 | __u32 handle; |
458 | __u32 pad; |
459 | __u32 pad; |
459 | /** Offset into the object to write to */ |
460 | /** Offset into the object to write to */ |
460 | __u64 offset; |
461 | __u64 offset; |
461 | /** Length of data to write */ |
462 | /** Length of data to write */ |
462 | __u64 size; |
463 | __u64 size; |
463 | /** |
464 | /** |
464 | * Pointer to read the data from. |
465 | * Pointer to read the data from. |
465 | * |
466 | * |
466 | * This is a fixed-size type for 32/64 compatibility. |
467 | * This is a fixed-size type for 32/64 compatibility. |
467 | */ |
468 | */ |
468 | __u64 data_ptr; |
469 | __u64 data_ptr; |
469 | }; |
470 | }; |
470 | 471 | ||
471 | struct drm_i915_gem_mmap { |
472 | struct drm_i915_gem_mmap { |
472 | /** Handle for the object being mapped. */ |
473 | /** Handle for the object being mapped. */ |
473 | __u32 handle; |
474 | __u32 handle; |
474 | __u32 pad; |
475 | __u32 pad; |
475 | /** Offset in the object to map. */ |
476 | /** Offset in the object to map. */ |
476 | __u64 offset; |
477 | __u64 offset; |
477 | /** |
478 | /** |
478 | * Length of data to map. |
479 | * Length of data to map. |
479 | * |
480 | * |
480 | * The value will be page-aligned. |
481 | * The value will be page-aligned. |
481 | */ |
482 | */ |
482 | __u64 size; |
483 | __u64 size; |
483 | /** |
484 | /** |
484 | * Returned pointer the data was mapped at. |
485 | * Returned pointer the data was mapped at. |
485 | * |
486 | * |
486 | * This is a fixed-size type for 32/64 compatibility. |
487 | * This is a fixed-size type for 32/64 compatibility. |
487 | */ |
488 | */ |
488 | __u64 addr_ptr; |
489 | __u64 addr_ptr; |
489 | }; |
490 | }; |
490 | 491 | ||
491 | struct drm_i915_gem_mmap_gtt { |
492 | struct drm_i915_gem_mmap_gtt { |
492 | /** Handle for the object being mapped. */ |
493 | /** Handle for the object being mapped. */ |
493 | __u32 handle; |
494 | __u32 handle; |
494 | __u32 pad; |
495 | __u32 pad; |
495 | /** |
496 | /** |
496 | * Fake offset to use for subsequent mmap call |
497 | * Fake offset to use for subsequent mmap call |
497 | * |
498 | * |
498 | * This is a fixed-size type for 32/64 compatibility. |
499 | * This is a fixed-size type for 32/64 compatibility. |
499 | */ |
500 | */ |
500 | __u64 offset; |
501 | __u64 offset; |
501 | }; |
502 | }; |
502 | 503 | ||
503 | struct drm_i915_gem_set_domain { |
504 | struct drm_i915_gem_set_domain { |
504 | /** Handle for the object */ |
505 | /** Handle for the object */ |
505 | __u32 handle; |
506 | __u32 handle; |
506 | 507 | ||
507 | /** New read domains */ |
508 | /** New read domains */ |
508 | __u32 read_domains; |
509 | __u32 read_domains; |
509 | 510 | ||
510 | /** New write domain */ |
511 | /** New write domain */ |
511 | __u32 write_domain; |
512 | __u32 write_domain; |
512 | }; |
513 | }; |
513 | 514 | ||
514 | struct drm_i915_gem_sw_finish { |
515 | struct drm_i915_gem_sw_finish { |
515 | /** Handle for the object */ |
516 | /** Handle for the object */ |
516 | __u32 handle; |
517 | __u32 handle; |
517 | }; |
518 | }; |
518 | 519 | ||
519 | struct drm_i915_gem_relocation_entry { |
520 | struct drm_i915_gem_relocation_entry { |
520 | /** |
521 | /** |
521 | * Handle of the buffer being pointed to by this relocation entry. |
522 | * Handle of the buffer being pointed to by this relocation entry. |
522 | * |
523 | * |
523 | * It's appealing to make this be an index into the mm_validate_entry |
524 | * It's appealing to make this be an index into the mm_validate_entry |
524 | * list to refer to the buffer, but this allows the driver to create |
525 | * list to refer to the buffer, but this allows the driver to create |
525 | * a relocation list for state buffers and not re-write it per |
526 | * a relocation list for state buffers and not re-write it per |
526 | * exec using the buffer. |
527 | * exec using the buffer. |
527 | */ |
528 | */ |
528 | __u32 target_handle; |
529 | __u32 target_handle; |
529 | 530 | ||
530 | /** |
531 | /** |
531 | * Value to be added to the offset of the target buffer to make up |
532 | * Value to be added to the offset of the target buffer to make up |
532 | * the relocation entry. |
533 | * the relocation entry. |
533 | */ |
534 | */ |
534 | __u32 delta; |
535 | __u32 delta; |
535 | 536 | ||
536 | /** Offset in the buffer the relocation entry will be written into */ |
537 | /** Offset in the buffer the relocation entry will be written into */ |
537 | __u64 offset; |
538 | __u64 offset; |
538 | 539 | ||
539 | /** |
540 | /** |
540 | * Offset value of the target buffer that the relocation entry was last |
541 | * Offset value of the target buffer that the relocation entry was last |
541 | * written as. |
542 | * written as. |
542 | * |
543 | * |
543 | * If the buffer has the same offset as last time, we can skip syncing |
544 | * If the buffer has the same offset as last time, we can skip syncing |
544 | * and writing the relocation. This value is written back out by |
545 | * and writing the relocation. This value is written back out by |
545 | * the execbuffer ioctl when the relocation is written. |
546 | * the execbuffer ioctl when the relocation is written. |
546 | */ |
547 | */ |
547 | __u64 presumed_offset; |
548 | __u64 presumed_offset; |
548 | 549 | ||
549 | /** |
550 | /** |
550 | * Target memory domains read by this operation. |
551 | * Target memory domains read by this operation. |
551 | */ |
552 | */ |
552 | __u32 read_domains; |
553 | __u32 read_domains; |
553 | 554 | ||
554 | /** |
555 | /** |
555 | * Target memory domains written by this operation. |
556 | * Target memory domains written by this operation. |
556 | * |
557 | * |
557 | * Note that only one domain may be written by the whole |
558 | * Note that only one domain may be written by the whole |
558 | * execbuffer operation, so that where there are conflicts, |
559 | * execbuffer operation, so that where there are conflicts, |
559 | * the application will get -EINVAL back. |
560 | * the application will get -EINVAL back. |
560 | */ |
561 | */ |
561 | __u32 write_domain; |
562 | __u32 write_domain; |
562 | }; |
563 | }; |
563 | 564 | ||
564 | /** @{ |
565 | /** @{ |
565 | * Intel memory domains |
566 | * Intel memory domains |
566 | * |
567 | * |
567 | * Most of these just align with the various caches in |
568 | * Most of these just align with the various caches in |
568 | * the system and are used to flush and invalidate as |
569 | * the system and are used to flush and invalidate as |
569 | * objects end up cached in different domains. |
570 | * objects end up cached in different domains. |
570 | */ |
571 | */ |
571 | /** CPU cache */ |
572 | /** CPU cache */ |
572 | #define I915_GEM_DOMAIN_CPU 0x00000001 |
573 | #define I915_GEM_DOMAIN_CPU 0x00000001 |
573 | /** Render cache, used by 2D and 3D drawing */ |
574 | /** Render cache, used by 2D and 3D drawing */ |
574 | #define I915_GEM_DOMAIN_RENDER 0x00000002 |
575 | #define I915_GEM_DOMAIN_RENDER 0x00000002 |
575 | /** Sampler cache, used by texture engine */ |
576 | /** Sampler cache, used by texture engine */ |
576 | #define I915_GEM_DOMAIN_SAMPLER 0x00000004 |
577 | #define I915_GEM_DOMAIN_SAMPLER 0x00000004 |
577 | /** Command queue, used to load batch buffers */ |
578 | /** Command queue, used to load batch buffers */ |
578 | #define I915_GEM_DOMAIN_COMMAND 0x00000008 |
579 | #define I915_GEM_DOMAIN_COMMAND 0x00000008 |
579 | /** Instruction cache, used by shader programs */ |
580 | /** Instruction cache, used by shader programs */ |
580 | #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 |
581 | #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 |
581 | /** Vertex address cache */ |
582 | /** Vertex address cache */ |
582 | #define I915_GEM_DOMAIN_VERTEX 0x00000020 |
583 | #define I915_GEM_DOMAIN_VERTEX 0x00000020 |
583 | /** GTT domain - aperture and scanout */ |
584 | /** GTT domain - aperture and scanout */ |
584 | #define I915_GEM_DOMAIN_GTT 0x00000040 |
585 | #define I915_GEM_DOMAIN_GTT 0x00000040 |
585 | /** @} */ |
586 | /** @} */ |
586 | 587 | ||
587 | struct drm_i915_gem_exec_object { |
588 | struct drm_i915_gem_exec_object { |
588 | /** |
589 | /** |
589 | * User's handle for a buffer to be bound into the GTT for this |
590 | * User's handle for a buffer to be bound into the GTT for this |
590 | * operation. |
591 | * operation. |
591 | */ |
592 | */ |
592 | __u32 handle; |
593 | __u32 handle; |
593 | 594 | ||
594 | /** Number of relocations to be performed on this buffer */ |
595 | /** Number of relocations to be performed on this buffer */ |
595 | __u32 relocation_count; |
596 | __u32 relocation_count; |
596 | /** |
597 | /** |
597 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
598 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
598 | * the relocations to be performed in this buffer. |
599 | * the relocations to be performed in this buffer. |
599 | */ |
600 | */ |
600 | __u64 relocs_ptr; |
601 | __u64 relocs_ptr; |
601 | 602 | ||
602 | /** Required alignment in graphics aperture */ |
603 | /** Required alignment in graphics aperture */ |
603 | __u64 alignment; |
604 | __u64 alignment; |
604 | 605 | ||
605 | /** |
606 | /** |
606 | * Returned value of the updated offset of the object, for future |
607 | * Returned value of the updated offset of the object, for future |
607 | * presumed_offset writes. |
608 | * presumed_offset writes. |
608 | */ |
609 | */ |
609 | __u64 offset; |
610 | __u64 offset; |
610 | }; |
611 | }; |
611 | 612 | ||
612 | struct drm_i915_gem_execbuffer { |
613 | struct drm_i915_gem_execbuffer { |
613 | /** |
614 | /** |
614 | * List of buffers to be validated with their relocations to be |
615 | * List of buffers to be validated with their relocations to be |
615 | * performend on them. |
616 | * performend on them. |
616 | * |
617 | * |
617 | * This is a pointer to an array of struct drm_i915_gem_validate_entry. |
618 | * This is a pointer to an array of struct drm_i915_gem_validate_entry. |
618 | * |
619 | * |
619 | * These buffers must be listed in an order such that all relocations |
620 | * These buffers must be listed in an order such that all relocations |
620 | * a buffer is performing refer to buffers that have already appeared |
621 | * a buffer is performing refer to buffers that have already appeared |
621 | * in the validate list. |
622 | * in the validate list. |
622 | */ |
623 | */ |
623 | __u64 buffers_ptr; |
624 | __u64 buffers_ptr; |
624 | __u32 buffer_count; |
625 | __u32 buffer_count; |
625 | 626 | ||
626 | /** Offset in the batchbuffer to start execution from. */ |
627 | /** Offset in the batchbuffer to start execution from. */ |
627 | __u32 batch_start_offset; |
628 | __u32 batch_start_offset; |
628 | /** Bytes used in batchbuffer from batch_start_offset */ |
629 | /** Bytes used in batchbuffer from batch_start_offset */ |
629 | __u32 batch_len; |
630 | __u32 batch_len; |
630 | __u32 DR1; |
631 | __u32 DR1; |
631 | __u32 DR4; |
632 | __u32 DR4; |
632 | __u32 num_cliprects; |
633 | __u32 num_cliprects; |
633 | /** This is a struct drm_clip_rect *cliprects */ |
634 | /** This is a struct drm_clip_rect *cliprects */ |
634 | __u64 cliprects_ptr; |
635 | __u64 cliprects_ptr; |
635 | }; |
636 | }; |
636 | 637 | ||
637 | struct drm_i915_gem_exec_object2 { |
638 | struct drm_i915_gem_exec_object2 { |
638 | /** |
639 | /** |
639 | * User's handle for a buffer to be bound into the GTT for this |
640 | * User's handle for a buffer to be bound into the GTT for this |
640 | * operation. |
641 | * operation. |
641 | */ |
642 | */ |
642 | __u32 handle; |
643 | __u32 handle; |
643 | 644 | ||
644 | /** Number of relocations to be performed on this buffer */ |
645 | /** Number of relocations to be performed on this buffer */ |
645 | __u32 relocation_count; |
646 | __u32 relocation_count; |
646 | /** |
647 | /** |
647 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
648 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
648 | * the relocations to be performed in this buffer. |
649 | * the relocations to be performed in this buffer. |
649 | */ |
650 | */ |
650 | __u64 relocs_ptr; |
651 | __u64 relocs_ptr; |
651 | 652 | ||
652 | /** Required alignment in graphics aperture */ |
653 | /** Required alignment in graphics aperture */ |
653 | __u64 alignment; |
654 | __u64 alignment; |
654 | 655 | ||
655 | /** |
656 | /** |
656 | * Returned value of the updated offset of the object, for future |
657 | * Returned value of the updated offset of the object, for future |
657 | * presumed_offset writes. |
658 | * presumed_offset writes. |
658 | */ |
659 | */ |
659 | __u64 offset; |
660 | __u64 offset; |
660 | 661 | ||
661 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
662 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
662 | #define EXEC_OBJECT_NEEDS_GTT (1<<1) |
663 | #define EXEC_OBJECT_NEEDS_GTT (1<<1) |
663 | #define EXEC_OBJECT_WRITE (1<<2) |
664 | #define EXEC_OBJECT_WRITE (1<<2) |
664 | #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) |
665 | #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) |
665 | __u64 flags; |
666 | __u64 flags; |
666 | 667 | ||
667 | __u64 rsvd1; |
668 | __u64 rsvd1; |
668 | __u64 rsvd2; |
669 | __u64 rsvd2; |
669 | }; |
670 | }; |
670 | 671 | ||
671 | struct drm_i915_gem_execbuffer2 { |
672 | struct drm_i915_gem_execbuffer2 { |
672 | /** |
673 | /** |
673 | * List of gem_exec_object2 structs |
674 | * List of gem_exec_object2 structs |
674 | */ |
675 | */ |
675 | __u64 buffers_ptr; |
676 | __u64 buffers_ptr; |
676 | __u32 buffer_count; |
677 | __u32 buffer_count; |
677 | 678 | ||
678 | /** Offset in the batchbuffer to start execution from. */ |
679 | /** Offset in the batchbuffer to start execution from. */ |
679 | __u32 batch_start_offset; |
680 | __u32 batch_start_offset; |
680 | /** Bytes used in batchbuffer from batch_start_offset */ |
681 | /** Bytes used in batchbuffer from batch_start_offset */ |
681 | __u32 batch_len; |
682 | __u32 batch_len; |
682 | __u32 DR1; |
683 | __u32 DR1; |
683 | __u32 DR4; |
684 | __u32 DR4; |
684 | __u32 num_cliprects; |
685 | __u32 num_cliprects; |
685 | /** This is a struct drm_clip_rect *cliprects */ |
686 | /** This is a struct drm_clip_rect *cliprects */ |
686 | __u64 cliprects_ptr; |
687 | __u64 cliprects_ptr; |
687 | #define I915_EXEC_RING_MASK (7<<0) |
688 | #define I915_EXEC_RING_MASK (7<<0) |
688 | #define I915_EXEC_DEFAULT (0<<0) |
689 | #define I915_EXEC_DEFAULT (0<<0) |
689 | #define I915_EXEC_RENDER (1<<0) |
690 | #define I915_EXEC_RENDER (1<<0) |
690 | #define I915_EXEC_BSD (2<<0) |
691 | #define I915_EXEC_BSD (2<<0) |
691 | #define I915_EXEC_BLT (3<<0) |
692 | #define I915_EXEC_BLT (3<<0) |
692 | #define I915_EXEC_VEBOX (4<<0) |
693 | #define I915_EXEC_VEBOX (4<<0) |
693 | 694 | ||
694 | /* Used for switching the constants addressing mode on gen4+ RENDER ring. |
695 | /* Used for switching the constants addressing mode on gen4+ RENDER ring. |
695 | * Gen6+ only supports relative addressing to dynamic state (default) and |
696 | * Gen6+ only supports relative addressing to dynamic state (default) and |
696 | * absolute addressing. |
697 | * absolute addressing. |
697 | * |
698 | * |
698 | * These flags are ignored for the BSD and BLT rings. |
699 | * These flags are ignored for the BSD and BLT rings. |
699 | */ |
700 | */ |
700 | #define I915_EXEC_CONSTANTS_MASK (3<<6) |
701 | #define I915_EXEC_CONSTANTS_MASK (3<<6) |
701 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
702 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
702 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
703 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
703 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
704 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
704 | __u64 flags; |
705 | __u64 flags; |
705 | __u64 rsvd1; /* now used for context info */ |
706 | __u64 rsvd1; /* now used for context info */ |
706 | __u64 rsvd2; |
707 | __u64 rsvd2; |
707 | }; |
708 | }; |
708 | 709 | ||
709 | /** Resets the SO write offset registers for transform feedback on gen7. */ |
710 | /** Resets the SO write offset registers for transform feedback on gen7. */ |
710 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) |
711 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) |
711 | 712 | ||
712 | /** Request a privileged ("secure") batch buffer. Note only available for |
713 | /** Request a privileged ("secure") batch buffer. Note only available for |
713 | * DRM_ROOT_ONLY | DRM_MASTER processes. |
714 | * DRM_ROOT_ONLY | DRM_MASTER processes. |
714 | */ |
715 | */ |
715 | #define I915_EXEC_SECURE (1<<9) |
716 | #define I915_EXEC_SECURE (1<<9) |
716 | 717 | ||
717 | /** Inform the kernel that the batch is and will always be pinned. This |
718 | /** Inform the kernel that the batch is and will always be pinned. This |
718 | * negates the requirement for a workaround to be performed to avoid |
719 | * negates the requirement for a workaround to be performed to avoid |
719 | * an incoherent CS (such as can be found on 830/845). If this flag is |
720 | * an incoherent CS (such as can be found on 830/845). If this flag is |
720 | * not passed, the kernel will endeavour to make sure the batch is |
721 | * not passed, the kernel will endeavour to make sure the batch is |
721 | * coherent with the CS before execution. If this flag is passed, |
722 | * coherent with the CS before execution. If this flag is passed, |
722 | * userspace assumes the responsibility for ensuring the same. |
723 | * userspace assumes the responsibility for ensuring the same. |
723 | */ |
724 | */ |
724 | #define I915_EXEC_IS_PINNED (1<<10) |
725 | #define I915_EXEC_IS_PINNED (1<<10) |
725 | 726 | ||
726 | /** Provide a hint to the kernel that the command stream and auxiliary |
727 | /** Provide a hint to the kernel that the command stream and auxiliary |
727 | * state buffers already holds the correct presumed addresses and so the |
728 | * state buffers already holds the correct presumed addresses and so the |
728 | * relocation process may be skipped if no buffers need to be moved in |
729 | * relocation process may be skipped if no buffers need to be moved in |
729 | * preparation for the execbuffer. |
730 | * preparation for the execbuffer. |
730 | */ |
731 | */ |
731 | #define I915_EXEC_NO_RELOC (1<<11) |
732 | #define I915_EXEC_NO_RELOC (1<<11) |
732 | 733 | ||
733 | /** Use the reloc.handle as an index into the exec object array rather |
734 | /** Use the reloc.handle as an index into the exec object array rather |
734 | * than as the per-file handle. |
735 | * than as the per-file handle. |
735 | */ |
736 | */ |
736 | #define I915_EXEC_HANDLE_LUT (1<<12) |
737 | #define I915_EXEC_HANDLE_LUT (1<<12) |
737 | 738 | ||
738 | #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) |
739 | #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) |
739 | 740 | ||
740 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
741 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
741 | #define i915_execbuffer2_set_context_id(eb2, context) \ |
742 | #define i915_execbuffer2_set_context_id(eb2, context) \ |
742 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
743 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
743 | #define i915_execbuffer2_get_context_id(eb2) \ |
744 | #define i915_execbuffer2_get_context_id(eb2) \ |
744 | ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) |
745 | ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) |
745 | 746 | ||
746 | struct drm_i915_gem_pin { |
747 | struct drm_i915_gem_pin { |
747 | /** Handle of the buffer to be pinned. */ |
748 | /** Handle of the buffer to be pinned. */ |
748 | __u32 handle; |
749 | __u32 handle; |
749 | __u32 pad; |
750 | __u32 pad; |
750 | 751 | ||
751 | /** alignment required within the aperture */ |
752 | /** alignment required within the aperture */ |
752 | __u64 alignment; |
753 | __u64 alignment; |
753 | 754 | ||
754 | /** Returned GTT offset of the buffer. */ |
755 | /** Returned GTT offset of the buffer. */ |
755 | __u64 offset; |
756 | __u64 offset; |
756 | }; |
757 | }; |
757 | 758 | ||
758 | struct drm_i915_gem_unpin { |
759 | struct drm_i915_gem_unpin { |
759 | /** Handle of the buffer to be unpinned. */ |
760 | /** Handle of the buffer to be unpinned. */ |
760 | __u32 handle; |
761 | __u32 handle; |
761 | __u32 pad; |
762 | __u32 pad; |
762 | }; |
763 | }; |
763 | 764 | ||
764 | struct drm_i915_gem_busy { |
765 | struct drm_i915_gem_busy { |
765 | /** Handle of the buffer to check for busy */ |
766 | /** Handle of the buffer to check for busy */ |
766 | __u32 handle; |
767 | __u32 handle; |
767 | 768 | ||
768 | /** Return busy status (1 if busy, 0 if idle). |
769 | /** Return busy status (1 if busy, 0 if idle). |
769 | * The high word is used to indicate on which rings the object |
770 | * The high word is used to indicate on which rings the object |
770 | * currently resides: |
771 | * currently resides: |
771 | * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) |
772 | * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) |
772 | */ |
773 | */ |
773 | __u32 busy; |
774 | __u32 busy; |
774 | }; |
775 | }; |
775 | 776 | ||
776 | /** |
777 | /** |
777 | * I915_CACHING_NONE |
778 | * I915_CACHING_NONE |
778 | * |
779 | * |
779 | * GPU access is not coherent with cpu caches. Default for machines without an |
780 | * GPU access is not coherent with cpu caches. Default for machines without an |
780 | * LLC. |
781 | * LLC. |
781 | */ |
782 | */ |
782 | #define I915_CACHING_NONE 0 |
783 | #define I915_CACHING_NONE 0 |
783 | /** |
784 | /** |
784 | * I915_CACHING_CACHED |
785 | * I915_CACHING_CACHED |
785 | * |
786 | * |
786 | * GPU access is coherent with cpu caches and furthermore the data is cached in |
787 | * GPU access is coherent with cpu caches and furthermore the data is cached in |
787 | * last-level caches shared between cpu cores and the gpu GT. Default on |
788 | * last-level caches shared between cpu cores and the gpu GT. Default on |
788 | * machines with HAS_LLC. |
789 | * machines with HAS_LLC. |
789 | */ |
790 | */ |
790 | #define I915_CACHING_CACHED 1 |
791 | #define I915_CACHING_CACHED 1 |
791 | /** |
792 | /** |
792 | * I915_CACHING_DISPLAY |
793 | * I915_CACHING_DISPLAY |
793 | * |
794 | * |
794 | * Special GPU caching mode which is coherent with the scanout engines. |
795 | * Special GPU caching mode which is coherent with the scanout engines. |
795 | * Transparently falls back to I915_CACHING_NONE on platforms where no special |
796 | * Transparently falls back to I915_CACHING_NONE on platforms where no special |
796 | * cache mode (like write-through or gfdt flushing) is available. The kernel |
797 | * cache mode (like write-through or gfdt flushing) is available. The kernel |
797 | * automatically sets this mode when using a buffer as a scanout target. |
798 | * automatically sets this mode when using a buffer as a scanout target. |
798 | * Userspace can manually set this mode to avoid a costly stall and clflush in |
799 | * Userspace can manually set this mode to avoid a costly stall and clflush in |
799 | * the hotpath of drawing the first frame. |
800 | * the hotpath of drawing the first frame. |
800 | */ |
801 | */ |
801 | #define I915_CACHING_DISPLAY 2 |
802 | #define I915_CACHING_DISPLAY 2 |
802 | 803 | ||
803 | struct drm_i915_gem_caching { |
804 | struct drm_i915_gem_caching { |
804 | /** |
805 | /** |
805 | * Handle of the buffer to set/get the caching level of. */ |
806 | * Handle of the buffer to set/get the caching level of. */ |
806 | __u32 handle; |
807 | __u32 handle; |
807 | 808 | ||
808 | /** |
809 | /** |
809 | * Cacheing level to apply or return value |
810 | * Cacheing level to apply or return value |
810 | * |
811 | * |
811 | * bits0-15 are for generic caching control (i.e. the above defined |
812 | * bits0-15 are for generic caching control (i.e. the above defined |
812 | * values). bits16-31 are reserved for platform-specific variations |
813 | * values). bits16-31 are reserved for platform-specific variations |
813 | * (e.g. l3$ caching on gen7). */ |
814 | * (e.g. l3$ caching on gen7). */ |
814 | __u32 caching; |
815 | __u32 caching; |
815 | }; |
816 | }; |
816 | 817 | ||
817 | #define I915_TILING_NONE 0 |
818 | #define I915_TILING_NONE 0 |
818 | #define I915_TILING_X 1 |
819 | #define I915_TILING_X 1 |
819 | #define I915_TILING_Y 2 |
820 | #define I915_TILING_Y 2 |
820 | 821 | ||
821 | #define I915_BIT_6_SWIZZLE_NONE 0 |
822 | #define I915_BIT_6_SWIZZLE_NONE 0 |
822 | #define I915_BIT_6_SWIZZLE_9 1 |
823 | #define I915_BIT_6_SWIZZLE_9 1 |
823 | #define I915_BIT_6_SWIZZLE_9_10 2 |
824 | #define I915_BIT_6_SWIZZLE_9_10 2 |
824 | #define I915_BIT_6_SWIZZLE_9_11 3 |
825 | #define I915_BIT_6_SWIZZLE_9_11 3 |
825 | #define I915_BIT_6_SWIZZLE_9_10_11 4 |
826 | #define I915_BIT_6_SWIZZLE_9_10_11 4 |
826 | /* Not seen by userland */ |
827 | /* Not seen by userland */ |
827 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 |
828 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 |
828 | /* Seen by userland. */ |
829 | /* Seen by userland. */ |
829 | #define I915_BIT_6_SWIZZLE_9_17 6 |
830 | #define I915_BIT_6_SWIZZLE_9_17 6 |
830 | #define I915_BIT_6_SWIZZLE_9_10_17 7 |
831 | #define I915_BIT_6_SWIZZLE_9_10_17 7 |
831 | 832 | ||
832 | struct drm_i915_gem_set_tiling { |
833 | struct drm_i915_gem_set_tiling { |
833 | /** Handle of the buffer to have its tiling state updated */ |
834 | /** Handle of the buffer to have its tiling state updated */ |
834 | __u32 handle; |
835 | __u32 handle; |
835 | 836 | ||
836 | /** |
837 | /** |
837 | * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
838 | * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
838 | * I915_TILING_Y). |
839 | * I915_TILING_Y). |
839 | * |
840 | * |
840 | * This value is to be set on request, and will be updated by the |
841 | * This value is to be set on request, and will be updated by the |
841 | * kernel on successful return with the actual chosen tiling layout. |
842 | * kernel on successful return with the actual chosen tiling layout. |
842 | * |
843 | * |
843 | * The tiling mode may be demoted to I915_TILING_NONE when the system |
844 | * The tiling mode may be demoted to I915_TILING_NONE when the system |
844 | * has bit 6 swizzling that can't be managed correctly by GEM. |
845 | * has bit 6 swizzling that can't be managed correctly by GEM. |
845 | * |
846 | * |
846 | * Buffer contents become undefined when changing tiling_mode. |
847 | * Buffer contents become undefined when changing tiling_mode. |
847 | */ |
848 | */ |
848 | __u32 tiling_mode; |
849 | __u32 tiling_mode; |
849 | 850 | ||
850 | /** |
851 | /** |
851 | * Stride in bytes for the object when in I915_TILING_X or |
852 | * Stride in bytes for the object when in I915_TILING_X or |
852 | * I915_TILING_Y. |
853 | * I915_TILING_Y. |
853 | */ |
854 | */ |
854 | __u32 stride; |
855 | __u32 stride; |
855 | 856 | ||
856 | /** |
857 | /** |
857 | * Returned address bit 6 swizzling required for CPU access through |
858 | * Returned address bit 6 swizzling required for CPU access through |
858 | * mmap mapping. |
859 | * mmap mapping. |
859 | */ |
860 | */ |
860 | __u32 swizzle_mode; |
861 | __u32 swizzle_mode; |
861 | }; |
862 | }; |
862 | 863 | ||
863 | struct drm_i915_gem_get_tiling { |
864 | struct drm_i915_gem_get_tiling { |
864 | /** Handle of the buffer to get tiling state for. */ |
865 | /** Handle of the buffer to get tiling state for. */ |
865 | __u32 handle; |
866 | __u32 handle; |
866 | 867 | ||
867 | /** |
868 | /** |
868 | * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
869 | * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
869 | * I915_TILING_Y). |
870 | * I915_TILING_Y). |
870 | */ |
871 | */ |
871 | __u32 tiling_mode; |
872 | __u32 tiling_mode; |
872 | 873 | ||
873 | /** |
874 | /** |
874 | * Returned address bit 6 swizzling required for CPU access through |
875 | * Returned address bit 6 swizzling required for CPU access through |
875 | * mmap mapping. |
876 | * mmap mapping. |
876 | */ |
877 | */ |
877 | __u32 swizzle_mode; |
878 | __u32 swizzle_mode; |
- | 879 | ||
- | 880 | /** |
|
- | 881 | * Returned address bit 6 swizzling required for CPU access through |
|
- | 882 | * mmap mapping whilst bound. |
|
- | 883 | */ |
|
- | 884 | __u32 phys_swizzle_mode; |
|
878 | }; |
885 | }; |
879 | 886 | ||
880 | struct drm_i915_gem_get_aperture { |
887 | struct drm_i915_gem_get_aperture { |
881 | /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ |
888 | /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ |
882 | __u64 aper_size; |
889 | __u64 aper_size; |
883 | 890 | ||
884 | /** |
891 | /** |
885 | * Available space in the aperture used by i915_gem_execbuffer, in |
892 | * Available space in the aperture used by i915_gem_execbuffer, in |
886 | * bytes |
893 | * bytes |
887 | */ |
894 | */ |
888 | __u64 aper_available_size; |
895 | __u64 aper_available_size; |
889 | }; |
896 | }; |
890 | 897 | ||
891 | struct drm_i915_get_pipe_from_crtc_id { |
898 | struct drm_i915_get_pipe_from_crtc_id { |
892 | /** ID of CRTC being requested **/ |
899 | /** ID of CRTC being requested **/ |
893 | __u32 crtc_id; |
900 | __u32 crtc_id; |
894 | 901 | ||
895 | /** pipe of requested CRTC **/ |
902 | /** pipe of requested CRTC **/ |
896 | __u32 pipe; |
903 | __u32 pipe; |
897 | }; |
904 | }; |
898 | 905 | ||
899 | #define I915_MADV_WILLNEED 0 |
906 | #define I915_MADV_WILLNEED 0 |
900 | #define I915_MADV_DONTNEED 1 |
907 | #define I915_MADV_DONTNEED 1 |
901 | #define __I915_MADV_PURGED 2 /* internal state */ |
908 | #define __I915_MADV_PURGED 2 /* internal state */ |
902 | 909 | ||
903 | struct drm_i915_gem_madvise { |
910 | struct drm_i915_gem_madvise { |
904 | /** Handle of the buffer to change the backing store advice */ |
911 | /** Handle of the buffer to change the backing store advice */ |
905 | __u32 handle; |
912 | __u32 handle; |
906 | 913 | ||
907 | /* Advice: either the buffer will be needed again in the near future, |
914 | /* Advice: either the buffer will be needed again in the near future, |
908 | * or wont be and could be discarded under memory pressure. |
915 | * or wont be and could be discarded under memory pressure. |
909 | */ |
916 | */ |
910 | __u32 madv; |
917 | __u32 madv; |
911 | 918 | ||
912 | /** Whether the backing store still exists. */ |
919 | /** Whether the backing store still exists. */ |
913 | __u32 retained; |
920 | __u32 retained; |
914 | }; |
921 | }; |
915 | 922 | ||
916 | /* flags */ |
923 | /* flags */ |
917 | #define I915_OVERLAY_TYPE_MASK 0xff |
924 | #define I915_OVERLAY_TYPE_MASK 0xff |
918 | #define I915_OVERLAY_YUV_PLANAR 0x01 |
925 | #define I915_OVERLAY_YUV_PLANAR 0x01 |
919 | #define I915_OVERLAY_YUV_PACKED 0x02 |
926 | #define I915_OVERLAY_YUV_PACKED 0x02 |
920 | #define I915_OVERLAY_RGB 0x03 |
927 | #define I915_OVERLAY_RGB 0x03 |
921 | 928 | ||
922 | #define I915_OVERLAY_DEPTH_MASK 0xff00 |
929 | #define I915_OVERLAY_DEPTH_MASK 0xff00 |
923 | #define I915_OVERLAY_RGB24 0x1000 |
930 | #define I915_OVERLAY_RGB24 0x1000 |
924 | #define I915_OVERLAY_RGB16 0x2000 |
931 | #define I915_OVERLAY_RGB16 0x2000 |
925 | #define I915_OVERLAY_RGB15 0x3000 |
932 | #define I915_OVERLAY_RGB15 0x3000 |
926 | #define I915_OVERLAY_YUV422 0x0100 |
933 | #define I915_OVERLAY_YUV422 0x0100 |
927 | #define I915_OVERLAY_YUV411 0x0200 |
934 | #define I915_OVERLAY_YUV411 0x0200 |
928 | #define I915_OVERLAY_YUV420 0x0300 |
935 | #define I915_OVERLAY_YUV420 0x0300 |
929 | #define I915_OVERLAY_YUV410 0x0400 |
936 | #define I915_OVERLAY_YUV410 0x0400 |
930 | 937 | ||
931 | #define I915_OVERLAY_SWAP_MASK 0xff0000 |
938 | #define I915_OVERLAY_SWAP_MASK 0xff0000 |
932 | #define I915_OVERLAY_NO_SWAP 0x000000 |
939 | #define I915_OVERLAY_NO_SWAP 0x000000 |
933 | #define I915_OVERLAY_UV_SWAP 0x010000 |
940 | #define I915_OVERLAY_UV_SWAP 0x010000 |
934 | #define I915_OVERLAY_Y_SWAP 0x020000 |
941 | #define I915_OVERLAY_Y_SWAP 0x020000 |
935 | #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 |
942 | #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 |
936 | 943 | ||
937 | #define I915_OVERLAY_FLAGS_MASK 0xff000000 |
944 | #define I915_OVERLAY_FLAGS_MASK 0xff000000 |
938 | #define I915_OVERLAY_ENABLE 0x01000000 |
945 | #define I915_OVERLAY_ENABLE 0x01000000 |
939 | 946 | ||
940 | struct drm_intel_overlay_put_image { |
947 | struct drm_intel_overlay_put_image { |
941 | /* various flags and src format description */ |
948 | /* various flags and src format description */ |
942 | __u32 flags; |
949 | __u32 flags; |
943 | /* source picture description */ |
950 | /* source picture description */ |
944 | __u32 bo_handle; |
951 | __u32 bo_handle; |
945 | /* stride values and offsets are in bytes, buffer relative */ |
952 | /* stride values and offsets are in bytes, buffer relative */ |
946 | __u16 stride_Y; /* stride for packed formats */ |
953 | __u16 stride_Y; /* stride for packed formats */ |
947 | __u16 stride_UV; |
954 | __u16 stride_UV; |
948 | __u32 offset_Y; /* offset for packet formats */ |
955 | __u32 offset_Y; /* offset for packet formats */ |
949 | __u32 offset_U; |
956 | __u32 offset_U; |
950 | __u32 offset_V; |
957 | __u32 offset_V; |
951 | /* in pixels */ |
958 | /* in pixels */ |
952 | __u16 src_width; |
959 | __u16 src_width; |
953 | __u16 src_height; |
960 | __u16 src_height; |
954 | /* to compensate the scaling factors for partially covered surfaces */ |
961 | /* to compensate the scaling factors for partially covered surfaces */ |
955 | __u16 src_scan_width; |
962 | __u16 src_scan_width; |
956 | __u16 src_scan_height; |
963 | __u16 src_scan_height; |
957 | /* output crtc description */ |
964 | /* output crtc description */ |
958 | __u32 crtc_id; |
965 | __u32 crtc_id; |
959 | __u16 dst_x; |
966 | __u16 dst_x; |
960 | __u16 dst_y; |
967 | __u16 dst_y; |
961 | __u16 dst_width; |
968 | __u16 dst_width; |
962 | __u16 dst_height; |
969 | __u16 dst_height; |
963 | }; |
970 | }; |
964 | 971 | ||
965 | /* flags */ |
972 | /* flags */ |
966 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
973 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
967 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
974 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
968 | struct drm_intel_overlay_attrs { |
975 | struct drm_intel_overlay_attrs { |
969 | __u32 flags; |
976 | __u32 flags; |
970 | __u32 color_key; |
977 | __u32 color_key; |
971 | __s32 brightness; |
978 | __s32 brightness; |
972 | __u32 contrast; |
979 | __u32 contrast; |
973 | __u32 saturation; |
980 | __u32 saturation; |
974 | __u32 gamma0; |
981 | __u32 gamma0; |
975 | __u32 gamma1; |
982 | __u32 gamma1; |
976 | __u32 gamma2; |
983 | __u32 gamma2; |
977 | __u32 gamma3; |
984 | __u32 gamma3; |
978 | __u32 gamma4; |
985 | __u32 gamma4; |
979 | __u32 gamma5; |
986 | __u32 gamma5; |
980 | }; |
987 | }; |
981 | 988 | ||
982 | /* |
989 | /* |
983 | * Intel sprite handling |
990 | * Intel sprite handling |
984 | * |
991 | * |
985 | * Color keying works with a min/mask/max tuple. Both source and destination |
992 | * Color keying works with a min/mask/max tuple. Both source and destination |
986 | * color keying is allowed. |
993 | * color keying is allowed. |
987 | * |
994 | * |
988 | * Source keying: |
995 | * Source keying: |
989 | * Sprite pixels within the min & max values, masked against the color channels |
996 | * Sprite pixels within the min & max values, masked against the color channels |
990 | * specified in the mask field, will be transparent. All other pixels will |
997 | * specified in the mask field, will be transparent. All other pixels will |
991 | * be displayed on top of the primary plane. For RGB surfaces, only the min |
998 | * be displayed on top of the primary plane. For RGB surfaces, only the min |
992 | * and mask fields will be used; ranged compares are not allowed. |
999 | * and mask fields will be used; ranged compares are not allowed. |
993 | * |
1000 | * |
994 | * Destination keying: |
1001 | * Destination keying: |
995 | * Primary plane pixels that match the min value, masked against the color |
1002 | * Primary plane pixels that match the min value, masked against the color |
996 | * channels specified in the mask field, will be replaced by corresponding |
1003 | * channels specified in the mask field, will be replaced by corresponding |
997 | * pixels from the sprite plane. |
1004 | * pixels from the sprite plane. |
998 | * |
1005 | * |
999 | * Note that source & destination keying are exclusive; only one can be |
1006 | * Note that source & destination keying are exclusive; only one can be |
1000 | * active on a given plane. |
1007 | * active on a given plane. |
1001 | */ |
1008 | */ |
1002 | 1009 | ||
1003 | #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ |
1010 | #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ |
1004 | #define I915_SET_COLORKEY_DESTINATION (1<<1) |
1011 | #define I915_SET_COLORKEY_DESTINATION (1<<1) |
1005 | #define I915_SET_COLORKEY_SOURCE (1<<2) |
1012 | #define I915_SET_COLORKEY_SOURCE (1<<2) |
1006 | struct drm_intel_sprite_colorkey { |
1013 | struct drm_intel_sprite_colorkey { |
1007 | __u32 plane_id; |
1014 | __u32 plane_id; |
1008 | __u32 min_value; |
1015 | __u32 min_value; |
1009 | __u32 channel_mask; |
1016 | __u32 channel_mask; |
1010 | __u32 max_value; |
1017 | __u32 max_value; |
1011 | __u32 flags; |
1018 | __u32 flags; |
1012 | }; |
1019 | }; |
1013 | 1020 | ||
1014 | struct drm_i915_gem_wait { |
1021 | struct drm_i915_gem_wait { |
1015 | /** Handle of BO we shall wait on */ |
1022 | /** Handle of BO we shall wait on */ |
1016 | __u32 bo_handle; |
1023 | __u32 bo_handle; |
1017 | __u32 flags; |
1024 | __u32 flags; |
1018 | /** Number of nanoseconds to wait, Returns time remaining. */ |
1025 | /** Number of nanoseconds to wait, Returns time remaining. */ |
1019 | __s64 timeout_ns; |
1026 | __s64 timeout_ns; |
1020 | }; |
1027 | }; |
1021 | 1028 | ||
1022 | struct drm_i915_gem_context_create { |
1029 | struct drm_i915_gem_context_create { |
1023 | /* output: id of new context*/ |
1030 | /* output: id of new context*/ |
1024 | __u32 ctx_id; |
1031 | __u32 ctx_id; |
1025 | __u32 pad; |
1032 | __u32 pad; |
1026 | }; |
1033 | }; |
1027 | 1034 | ||
1028 | struct drm_i915_gem_context_destroy { |
1035 | struct drm_i915_gem_context_destroy { |
1029 | __u32 ctx_id; |
1036 | __u32 ctx_id; |
1030 | __u32 pad; |
1037 | __u32 pad; |
1031 | }; |
1038 | }; |
1032 | 1039 | ||
1033 | struct drm_i915_reg_read { |
1040 | struct drm_i915_reg_read { |
1034 | __u64 offset; |
1041 | __u64 offset; |
1035 | __u64 val; /* Return value */ |
1042 | __u64 val; /* Return value */ |
1036 | }; |
1043 | }; |
1037 | 1044 | ||
1038 | struct drm_i915_reset_stats { |
1045 | struct drm_i915_reset_stats { |
1039 | __u32 ctx_id; |
1046 | __u32 ctx_id; |
1040 | __u32 flags; |
1047 | __u32 flags; |
1041 | 1048 | ||
1042 | /* All resets since boot/module reload, for all contexts */ |
1049 | /* All resets since boot/module reload, for all contexts */ |
1043 | __u32 reset_count; |
1050 | __u32 reset_count; |
1044 | 1051 | ||
1045 | /* Number of batches lost when active in GPU, for this context */ |
1052 | /* Number of batches lost when active in GPU, for this context */ |
1046 | __u32 batch_active; |
1053 | __u32 batch_active; |
1047 | 1054 | ||
1048 | /* Number of batches lost pending for execution, for this context */ |
1055 | /* Number of batches lost pending for execution, for this context */ |
1049 | __u32 batch_pending; |
1056 | __u32 batch_pending; |
1050 | 1057 | ||
1051 | __u32 pad; |
1058 | __u32 pad; |
1052 | }; |
1059 | }; |
1053 | 1060 | ||
1054 | struct drm_i915_gem_userptr { |
1061 | struct drm_i915_gem_userptr { |
1055 | __u64 user_ptr; |
1062 | __u64 user_ptr; |
1056 | __u64 user_size; |
1063 | __u64 user_size; |
1057 | __u32 flags; |
1064 | __u32 flags; |
1058 | #define I915_USERPTR_READ_ONLY 0x1 |
1065 | #define I915_USERPTR_READ_ONLY 0x1 |
1059 | #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 |
1066 | #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 |
1060 | /** |
1067 | /** |
1061 | * Returned handle for the object. |
1068 | * Returned handle for the object. |
1062 | * |
1069 | * |
1063 | * Object handles are nonzero. |
1070 | * Object handles are nonzero. |
1064 | */ |
1071 | */ |
1065 | __u32 handle; |
1072 | __u32 handle; |
1066 | }; |
1073 | }; |
1067 | 1074 | ||
1068 | struct drm_i915_mask { |
1075 | struct drm_i915_mask { |
1069 | __u32 handle; |
1076 | __u32 handle; |
1070 | __u32 width; |
1077 | __u32 width; |
1071 | __u32 height; |
1078 | __u32 height; |
1072 | __u32 bo_size; |
1079 | __u32 bo_size; |
1073 | __u32 bo_pitch; |
1080 | __u32 bo_pitch; |
1074 | __u32 bo_map; |
1081 | __u32 bo_map; |
1075 | }; |
1082 | }; |
1076 | 1083 | ||
1077 | struct drm_i915_fb_info { |
1084 | struct drm_i915_fb_info { |
1078 | __u32 name; |
1085 | __u32 name; |
1079 | __u32 width; |
1086 | __u32 width; |
1080 | __u32 height; |
1087 | __u32 height; |
1081 | __u32 pitch; |
1088 | __u32 pitch; |
1082 | __u32 tiling; |
1089 | __u32 tiling; |
1083 | __u32 crtc; |
1090 | __u32 crtc; |
1084 | __u32 pipe; |
1091 | __u32 pipe; |
1085 | }; |
1092 | }; |
1086 | 1093 | ||
1087 | struct drm_i915_mask_update { |
1094 | struct drm_i915_mask_update { |
1088 | __u32 handle; |
1095 | __u32 handle; |
1089 | __u32 dx; |
1096 | __u32 dx; |
1090 | __u32 dy; |
1097 | __u32 dy; |
1091 | __u32 width; |
1098 | __u32 width; |
1092 | __u32 height; |
1099 | __u32 height; |
1093 | __u32 bo_pitch; |
1100 | __u32 bo_pitch; |
1094 | __u32 bo_map; |
1101 | __u32 bo_map; |
1095 | }; |
1102 | }; |
1096 | 1103 | ||
1097 | #endif /* _I915_DRM_H_ */2) |
1104 | #endif /* _I915_DRM_H_ */2) |
1098 | struct><2) |
1105 | struct><2) |
1099 | struct>1) |
1106 | struct>1) |
1100 | #define><1) |
1107 | #define><1) |
1101 | #define>0)><0)>1) |
1108 | #define>0)><0)>1) |
1102 | struct><1) |
1109 | struct><1) |
1103 | struct>0) |
1110 | struct>0) |
1104 | #define><0) |
1111 | #define><0) |
1105 | #define>1) |
1112 | #define>1) |
1106 | 1113 | ||
1107 | #define><1) |
1114 | #define><1) |
1108 | 1115 | ||
1109 | #define>12) |
1116 | #define>12) |
1110 | 1117 | ||
1111 | #define><12) |
1118 | #define><12) |
1112 | 1119 | ||
1113 | #define>11) |
1120 | #define>11) |
1114 | 1121 | ||
1115 | /**><11) |
1122 | /**><11) |
1116 | 1123 | ||
1117 | /**>10) |
1124 | /**>10) |
1118 | 1125 | ||
1119 | /**><10) |
1126 | /**><10) |
1120 | 1127 | ||
1121 | /**>9) |
1128 | /**>9) |
1122 | 1129 | ||
1123 | /**><9) |
1130 | /**><9) |
1124 | 1131 | ||
1125 | /**>8) |
1132 | /**>8) |
1126 | 1133 | ||
1127 | /**><8) |
1134 | /**><8) |
1128 | 1135 | ||
1129 | /**>6)><6)>6) |
1136 | /**>6)><6)>6) |
1130 | #define><6) |
1137 | #define><6) |
1131 | #define>6)><6)>6) |
1138 | #define>6)><6)>6) |
1132 | #define><6) |
1139 | #define><6) |
1133 | #define>0) |
1140 | #define>0) |
1134 | 1141 | ||
1135 | /*><0) |
1142 | /*><0) |
1136 | 1143 | ||
1137 | /*>0) |
1144 | /*>0) |
1138 | #define><0) |
1145 | #define><0) |
1139 | #define>0) |
1146 | #define>0) |
1140 | #define><0) |
1147 | #define><0) |
1141 | #define>0) |
1148 | #define>0) |
1142 | #define><0) |
1149 | #define><0) |
1143 | #define>0) |
1150 | #define>0) |
1144 | #define><0) |
1151 | #define><0) |
1145 | #define>0) |
1152 | #define>0) |
1146 | #define><0) |
1153 | #define><0) |
1147 | #define>1) |
1154 | #define>1) |
1148 | ><1) |
1155 | ><1) |
1149 | >2) |
1156 | >2) |
1150 | #define><2) |
1157 | #define><2) |
1151 | #define>1) |
1158 | #define>1) |
1152 | #define><1) |
1159 | #define><1) |
1153 | #define>0) |
1160 | #define>0) |
1154 | #define><0) |
1161 | #define><0) |
1155 | #define> |
1162 | #define> |