WebSVN – Kolibri OS – Diff – /contrib/sdk/sources/libdrm/include/drm/i915_drm.h


/*
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */
 
#ifndef _I915_DRM_H_
#define _I915_DRM_H_
 
#include "drm.h"
 
/* Please note that modifications to all structs defined here are
 * subject to backwards-compatibility constraints.
 */
 
 
/* Each region is a minimum of 16k, and there are at most 255 of them.
 */
#define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
				 * of chars for next/prev indices */
#define I915_LOG_MIN_TEX_REGION_SIZE 14
 
typedef struct _drm_i915_init {
	enum {
		I915_INIT_DMA = 0x01,
		I915_CLEANUP_DMA = 0x02,
		I915_RESUME_DMA = 0x03
	} func;
	unsigned int mmio_offset;
	int sarea_priv_offset;
	unsigned int ring_start;
	unsigned int ring_end;
	unsigned int ring_size;
	unsigned int front_offset;
	unsigned int back_offset;
	unsigned int depth_offset;
	unsigned int w;
	unsigned int h;
	unsigned int pitch;
	unsigned int pitch_bits;
	unsigned int back_pitch;
	unsigned int depth_pitch;
	unsigned int cpp;
	unsigned int chipset;
} drm_i915_init_t;
 
typedef struct _drm_i915_sarea {
	struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
	int last_upload;	/* last time texture was uploaded */
	int last_enqueue;	/* last time a buffer was enqueued */
	int last_dispatch;	/* age of the most recently dispatched buffer */
	int ctxOwner;		/* last context to upload state */
	int texAge;
	int pf_enabled;		/* is pageflipping allowed? */
	int pf_active;
	int pf_current_page;	/* which buffer is being displayed? */
	int perf_boxes;		/* performance boxes to be displayed */
	int width, height;      /* screen size in pixels */
 
	drm_handle_t front_handle;
	int front_offset;
	int front_size;
 
	drm_handle_t back_handle;
	int back_offset;
	int back_size;
 
	drm_handle_t depth_handle;
	int depth_offset;
	int depth_size;
 
	drm_handle_t tex_handle;
	int tex_offset;
	int tex_size;
	int log_tex_granularity;
	int pitch;
	int rotation;           /* 0, 90, 180 or 270 */
	int rotated_offset;
	int rotated_size;
	int rotated_pitch;
	int virtualX, virtualY;
 
	unsigned int front_tiled;
	unsigned int back_tiled;
	unsigned int depth_tiled;
	unsigned int rotated_tiled;
	unsigned int rotated2_tiled;
 
	int pipeA_x;
	int pipeA_y;
	int pipeA_w;
	int pipeA_h;
	int pipeB_x;
	int pipeB_y;
	int pipeB_w;
	int pipeB_h;
 
	/* fill out some space for old userspace triple buffer */
	drm_handle_t unused_handle;
	__u32 unused1, unused2, unused3;
 
	/* buffer object handles for static buffers. May change
	 * over the lifetime of the client.
	 */
	__u32 front_bo_handle;
	__u32 back_bo_handle;
	__u32 unused_bo_handle;
	__u32 depth_bo_handle;
 
} drm_i915_sarea_t;
 
/* due to userspace building against these headers we need some compat here */
#define planeA_x pipeA_x
#define planeA_y pipeA_y
#define planeA_w pipeA_w
#define planeA_h pipeA_h
#define planeB_x pipeB_x
#define planeB_y pipeB_y
#define planeB_w pipeB_w
#define planeB_h pipeB_h
 
/* Flags for perf_boxes
 */
#define I915_BOX_RING_EMPTY    		0x1
#define I915_BOX_FLIP          		0x2
#define I915_BOX_WAIT          		0x4
#define I915_BOX_TEXTURE_LOAD  		0x8
#define I915_BOX_LOST_CONTEXT  		0x10
 
/* I915 specific ioctls
 * The device specific ioctl range is 0x40 to 0x79.
 */
#define DRM_I915_INIT			0x00
#define DRM_I915_FLUSH			0x01
#define DRM_I915_FLIP			0x02
#define DRM_I915_BATCHBUFFER		0x03
#define DRM_I915_IRQ_EMIT		0x04
#define DRM_I915_IRQ_WAIT		0x05
#define DRM_I915_GETPARAM		0x06
#define DRM_I915_SETPARAM		0x07
#define DRM_I915_ALLOC			0x08
#define DRM_I915_FREE			0x09
#define DRM_I915_INIT_HEAP		0x0a
#define DRM_I915_CMDBUFFER		0x0b
#define DRM_I915_DESTROY_HEAP		0x0c
#define DRM_I915_SET_VBLANK_PIPE	0x0d
#define DRM_I915_GET_VBLANK_PIPE	0x0e
#define DRM_I915_VBLANK_SWAP		0x0f
#define DRM_I915_HWS_ADDR		0x11
#define DRM_I915_GEM_INIT		0x13
#define DRM_I915_GEM_EXECBUFFER		0x14
#define DRM_I915_GEM_PIN		0x15
#define DRM_I915_GEM_UNPIN		0x16
#define DRM_I915_GEM_BUSY		0x17
#define DRM_I915_GEM_THROTTLE		0x18
#define DRM_I915_GEM_ENTERVT		0x19
#define DRM_I915_GEM_LEAVEVT		0x1a
#define DRM_I915_GEM_CREATE		0x1b
#define DRM_I915_GEM_PREAD		0x1c
#define DRM_I915_GEM_PWRITE		0x1d
#define DRM_I915_GEM_MMAP		0x1e
#define DRM_I915_GEM_SET_DOMAIN		0x1f
#define DRM_I915_GEM_SW_FINISH		0x20
#define DRM_I915_GEM_SET_TILING		0x21
#define DRM_I915_GEM_GET_TILING		0x22
#define DRM_I915_GEM_GET_APERTURE 	0x23
#define DRM_I915_GEM_MMAP_GTT		0x24
#define DRM_I915_GET_PIPE_FROM_CRTC_ID	0x25
#define DRM_I915_GEM_MADVISE		0x26
#define DRM_I915_OVERLAY_PUT_IMAGE	0x27
#define DRM_I915_OVERLAY_ATTRS		0x28
#define DRM_I915_GEM_EXECBUFFER2	0x29
#define DRM_I915_GET_SPRITE_COLORKEY	0x2a
#define DRM_I915_SET_SPRITE_COLORKEY	0x2b
#define DRM_I915_GEM_WAIT		0x2c
#define DRM_I915_GEM_CONTEXT_CREATE	0x2d
#define DRM_I915_GEM_CONTEXT_DESTROY	0x2e
#define DRM_I915_GEM_SET_CACHEING	0x2f
#define DRM_I915_GEM_GET_CACHEING	0x30
#define DRM_I915_REG_READ		0x31
#define DRM_I915_GET_RESET_STATS	0x32
 
#define DRM_IOCTL_I915_INIT
#define DRM_IOCTL_I915_FLUSH
#define DRM_IOCTL_I915_FLIP
#define DRM_IOCTL_I915_BATCHBUFFER
#define DRM_IOCTL_I915_IRQ_EMIT
#define DRM_IOCTL_I915_IRQ_WAIT
#define DRM_IOCTL_I915_GETPARAM                SRV_I915_GET_PARAM
#define DRM_IOCTL_I915_SETPARAM
#define DRM_IOCTL_I915_ALLOC
#define DRM_IOCTL_I915_FREE
#define DRM_IOCTL_I915_INIT_HEAP
#define DRM_IOCTL_I915_CMDBUFFER
#define DRM_IOCTL_I915_DESTROY_HEAP
#define DRM_IOCTL_I915_SET_VBLANK_PIPE
#define DRM_IOCTL_I915_GET_VBLANK_PIPE
#define DRM_IOCTL_I915_VBLANK_SWAP
#define DRM_IOCTL_I915_HWS_ADDR
#define DRM_IOCTL_I915_GEM_INIT
#define DRM_IOCTL_I915_GEM_EXECBUFFER
#define DRM_IOCTL_I915_GEM_EXECBUFFER2          SRV_I915_GEM_EXECBUFFER2
#define DRM_IOCTL_I915_GEM_PIN                  SRV_I915_GEM_PIN
#define DRM_IOCTL_I915_GEM_UNPIN                SRV_I915_GEM_UNPIN
#define DRM_IOCTL_I915_GEM_BUSY                 SRV_I915_GEM_BUSY
#define DRM_IOCTL_I915_GEM_SET_CACHEING         SRV_I915_GEM_SET_CACHING
#define DRM_IOCTL_I915_GEM_GET_CACHEING
#define DRM_IOCTL_I915_GEM_THROTTLE             SRV_I915_GEM_THROTTLE
#define DRM_IOCTL_I915_GEM_ENTERVT
#define DRM_IOCTL_I915_GEM_LEAVEVT
#define DRM_IOCTL_I915_GEM_CREATE               SRV_I915_GEM_CREATE
#define DRM_IOCTL_I915_GEM_PREAD
#define DRM_IOCTL_I915_GEM_PWRITE               SRV_I915_GEM_PWRITE
#define DRM_IOCTL_I915_GEM_MMAP                 SRV_I915_GEM_MMAP
#define DRM_IOCTL_I915_GEM_MMAP_GTT             SRV_I915_GEM_MMAP_GTT
#define DRM_IOCTL_I915_GEM_SET_DOMAIN           SRV_I915_GEM_SET_DOMAIN
#define DRM_IOCTL_I915_GEM_SW_FINISH
#define DRM_IOCTL_I915_GEM_SET_TILING           SRV_I915_GEM_SET_TILING
#define DRM_IOCTL_I915_GEM_GET_TILING           SRV_I915_GEM_GET_TILING
#define DRM_IOCTL_I915_GEM_GET_APERTURE         SRV_I915_GEM_GET_APERTURE
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID
#define DRM_IOCTL_I915_GEM_MADVISE
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE
#define DRM_IOCTL_I915_OVERLAY_ATTRS
#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY
#define DRM_IOCTL_I915_GEM_WAIT                 SRV_I915_GEM_WAIT
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE       SRV_I915_GEM_CONTEXT_CREATE
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY      SRV_I915_GEM_CONTEXT_DESTROY
#define DRM_IOCTL_I915_REG_READ                 SRV_I915_REG_READ
 
 
/* Allow drivers to submit batchbuffers directly to hardware, relying
 * on the security mechanisms provided by hardware.
 */
typedef struct drm_i915_batchbuffer {
	int start;		/* agp offset */
	int used;		/* nr bytes in use */
	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
	int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO */
	int num_cliprects;	/* mulitpass with multiple cliprects? */
	struct drm_clip_rect *cliprects;	/* pointer to userspace cliprects */
} drm_i915_batchbuffer_t;
 
/* As above, but pass a pointer to userspace buffer which can be
 * validated by the kernel prior to sending to hardware.
 */
typedef struct _drm_i915_cmdbuffer {
	char *buf;	/* pointer to userspace command buffer */
	int sz;			/* nr bytes in buf */
	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
	int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO */
	int num_cliprects;	/* mulitpass with multiple cliprects? */
	struct drm_clip_rect *cliprects;	/* pointer to userspace cliprects */
} drm_i915_cmdbuffer_t;
 
/* Userspace can request & wait on irq's:
 */
typedef struct drm_i915_irq_emit {
	int *irq_seq;
} drm_i915_irq_emit_t;
 
typedef struct drm_i915_irq_wait {
	int irq_seq;
} drm_i915_irq_wait_t;
 
/* Ioctl to query kernel params:
 */
#define I915_PARAM_IRQ_ACTIVE            1
#define I915_PARAM_ALLOW_BATCHBUFFER     2
#define I915_PARAM_LAST_DISPATCH         3
#define I915_PARAM_CHIPSET_ID            4
#define I915_PARAM_HAS_GEM               5
#define I915_PARAM_NUM_FENCES_AVAIL      6
#define I915_PARAM_HAS_OVERLAY           7
#define I915_PARAM_HAS_PAGEFLIPPING	 8
#define I915_PARAM_HAS_EXECBUF2          9
#define I915_PARAM_HAS_BSD		 10
#define I915_PARAM_HAS_BLT		 11
#define I915_PARAM_HAS_RELAXED_FENCING	 12
#define I915_PARAM_HAS_COHERENT_RINGS	 13
#define I915_PARAM_HAS_EXEC_CONSTANTS	 14
#define I915_PARAM_HAS_RELAXED_DELTA	 15
#define I915_PARAM_HAS_GEN7_SOL_RESET	 16
#define I915_PARAM_HAS_LLC     	 	 17
#define I915_PARAM_HAS_ALIASING_PPGTT	 18
#define I915_PARAM_HAS_WAIT_TIMEOUT	 19
#define I915_PARAM_HAS_VEBOX            22
 
typedef struct drm_i915_getparam {
	int param;
	int *value;
} drm_i915_getparam_t;
 
/* Ioctl to set kernel params:
 */
#define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
#define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
#define I915_SETPARAM_NUM_USED_FENCES                     4
 
typedef struct drm_i915_setparam {
	int param;
	int value;
} drm_i915_setparam_t;
 
/* A memory manager for regions of shared memory:
 */
#define I915_MEM_REGION_AGP 1
 
typedef struct drm_i915_mem_alloc {
	int region;
	int alignment;
	int size;
	int *region_offset;	/* offset from start of fb or agp */
} drm_i915_mem_alloc_t;
 
typedef struct drm_i915_mem_free {
	int region;
	int region_offset;
} drm_i915_mem_free_t;
 
typedef struct drm_i915_mem_init_heap {
	int region;
	int size;
	int start;
} drm_i915_mem_init_heap_t;
 
/* Allow memory manager to be torn down and re-initialized (eg on
 * rotate):
 */
typedef struct drm_i915_mem_destroy_heap {
	int region;
} drm_i915_mem_destroy_heap_t;
 
/* Allow X server to configure which pipes to monitor for vblank signals
 */
#define	DRM_I915_VBLANK_PIPE_A	1
#define	DRM_I915_VBLANK_PIPE_B	2
 
typedef struct drm_i915_vblank_pipe {
	int pipe;
} drm_i915_vblank_pipe_t;
 
/* Schedule buffer swap at given vertical blank:
 */
typedef struct drm_i915_vblank_swap {
	drm_drawable_t drawable;
	enum drm_vblank_seq_type seqtype;
	unsigned int sequence;
} drm_i915_vblank_swap_t;
 
typedef struct drm_i915_hws_addr {
	__u64 addr;
} drm_i915_hws_addr_t;
 
struct drm_i915_gem_init {
	/**
	 * Beginning offset in the GTT to be managed by the DRM memory
	 * manager.
	 */
	__u64 gtt_start;
	/**
	 * Ending offset in the GTT to be managed by the DRM memory
	 * manager.
	 */
	__u64 gtt_end;
};
 
struct drm_i915_gem_create {
	/**
	 * Requested size for the object.
	 *
	 * The (page-aligned) allocated size for the object will be returned.
	 */
	__u64 size;
	/**
	 * Returned handle for the object.
	 *
	 * Object handles are nonzero.
	 */
	__u32 handle;
	__u32 pad;
};
 
struct drm_i915_gem_pread {
	/** Handle for the object being read. */
	__u32 handle;
	__u32 pad;
	/** Offset into the object to read from */
	__u64 offset;
	/** Length of data to read */
	__u64 size;
	/**
	 * Pointer to write the data into.
	 *
	 * This is a fixed-size type for 32/64 compatibility.
	 */
	__u64 data_ptr;
};
 
struct drm_i915_gem_pwrite {
	/** Handle for the object being written to. */
	__u32 handle;
	__u32 pad;
	/** Offset into the object to write to */
	__u64 offset;
	/** Length of data to write */
	__u64 size;
	/**
	 * Pointer to read the data from.
	 *
	 * This is a fixed-size type for 32/64 compatibility.
	 */
	__u64 data_ptr;
};
 
struct drm_i915_gem_mmap {
	/** Handle for the object being mapped. */
	__u32 handle;
	__u32 pad;
	/** Offset in the object to map. */
	__u64 offset;
	/**
	 * Length of data to map.
	 *
	 * The value will be page-aligned.
	 */
	__u64 size;
	/**
	 * Returned pointer the data was mapped at.
	 *
	 * This is a fixed-size type for 32/64 compatibility.
	 */
	__u64 addr_ptr;
};
 
struct drm_i915_gem_mmap_gtt {
	/** Handle for the object being mapped. */
	__u32 handle;
	__u32 pad;
	/**
	 * Fake offset to use for subsequent mmap call
	 *
	 * This is a fixed-size type for 32/64 compatibility.
	 */
	__u64 offset;
};
 
struct drm_i915_gem_set_domain {
	/** Handle for the object */
	__u32 handle;
 
	/** New read domains */
	__u32 read_domains;
 
	/** New write domain */
	__u32 write_domain;
};
 
struct drm_i915_gem_sw_finish {
	/** Handle for the object */
	__u32 handle;
};
 
struct drm_i915_gem_relocation_entry {
	/**
	 * Handle of the buffer being pointed to by this relocation entry.
	 *
	 * It's appealing to make this be an index into the mm_validate_entry
	 * list to refer to the buffer, but this allows the driver to create
	 * a relocation list for state buffers and not re-write it per
	 * exec using the buffer.
	 */
	__u32 target_handle;
 
	/**
	 * Value to be added to the offset of the target buffer to make up
	 * the relocation entry.
	 */
	__u32 delta;
 
	/** Offset in the buffer the relocation entry will be written into */
	__u64 offset;
 
	/**
	 * Offset value of the target buffer that the relocation entry was last
	 * written as.
	 *
	 * If the buffer has the same offset as last time, we can skip syncing
	 * and writing the relocation.  This value is written back out by
	 * the execbuffer ioctl when the relocation is written.
	 */
	__u64 presumed_offset;
 
	/**
	 * Target memory domains read by this operation.
	 */
	__u32 read_domains;
 
	/**
	 * Target memory domains written by this operation.
	 *
	 * Note that only one domain may be written by the whole
	 * execbuffer operation, so that where there are conflicts,
	 * the application will get -EINVAL back.
	 */
	__u32 write_domain;
};
 
/** @{
 * Intel memory domains
 *
 * Most of these just align with the various caches in
 * the system and are used to flush and invalidate as
 * objects end up cached in different domains.
 */
/** CPU cache */
#define I915_GEM_DOMAIN_CPU		0x00000001
/** Render cache, used by 2D and 3D drawing */
#define I915_GEM_DOMAIN_RENDER		0x00000002
/** Sampler cache, used by texture engine */
#define I915_GEM_DOMAIN_SAMPLER		0x00000004
/** Command queue, used to load batch buffers */
#define I915_GEM_DOMAIN_COMMAND		0x00000008
/** Instruction cache, used by shader programs */
#define I915_GEM_DOMAIN_INSTRUCTION	0x00000010
/** Vertex address cache */
#define I915_GEM_DOMAIN_VERTEX		0x00000020
/** GTT domain - aperture and scanout */
#define I915_GEM_DOMAIN_GTT		0x00000040
/** @} */
 
struct drm_i915_gem_exec_object {
	/**
	 * User's handle for a buffer to be bound into the GTT for this
	 * operation.
	 */
	__u32 handle;
 
	/** Number of relocations to be performed on this buffer */
	__u32 relocation_count;
	/**
	 * Pointer to array of struct drm_i915_gem_relocation_entry containing
	 * the relocations to be performed in this buffer.
	 */
	__u64 relocs_ptr;
 
	/** Required alignment in graphics aperture */
	__u64 alignment;
 
	/**
	 * Returned value of the updated offset of the object, for future
	 * presumed_offset writes.
	 */
	__u64 offset;
};
 
struct drm_i915_gem_execbuffer {
	/**
	 * List of buffers to be validated with their relocations to be
	 * performend on them.
	 *
	 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
	 *
	 * These buffers must be listed in an order such that all relocations
	 * a buffer is performing refer to buffers that have already appeared
	 * in the validate list.
	 */
	__u64 buffers_ptr;
	__u32 buffer_count;
 
	/** Offset in the batchbuffer to start execution from. */
	__u32 batch_start_offset;
	/** Bytes used in batchbuffer from batch_start_offset */
	__u32 batch_len;
	__u32 DR1;
	__u32 DR4;
	__u32 num_cliprects;
	/** This is a struct drm_clip_rect *cliprects */
	__u64 cliprects_ptr;
};
 
struct drm_i915_gem_exec_object2 {
	/**
	 * User's handle for a buffer to be bound into the GTT for this
	 * operation.
	 */
	__u32 handle;
 
	/** Number of relocations to be performed on this buffer */
	__u32 relocation_count;
	/**
	 * Pointer to array of struct drm_i915_gem_relocation_entry containing
	 * the relocations to be performed in this buffer.
	 */
	__u64 relocs_ptr;
 
	/** Required alignment in graphics aperture */
	__u64 alignment;
 
	/**
	 * Returned value of the updated offset of the object, for future
	 * presumed_offset writes.
	 */
	__u64 offset;
 
#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
	__u64 flags;
	__u64 rsvd1;
	__u64 rsvd2;
};
 
struct drm_i915_gem_execbuffer2 {
	/**
	 * List of gem_exec_object2 structs
	 */
	__u64 buffers_ptr;
	__u32 buffer_count;
 
	/** Offset in the batchbuffer to start execution from. */
	__u32 batch_start_offset;
	/** Bytes used in batchbuffer from batch_start_offset */
	__u32 batch_len;
	__u32 DR1;
	__u32 DR4;
	__u32 num_cliprects;
	/** This is a struct drm_clip_rect *cliprects */
	__u64 cliprects_ptr;
#define I915_EXEC_RING_MASK              (7<<0)
#define I915_EXEC_DEFAULT                (0<<0)
#define I915_EXEC_RENDER                 (1<<0)
#define I915_EXEC_BSD                    (2<<0)
#define I915_EXEC_BLT                    (3<<0)
#define I915_EXEC_VEBOX                  (4<<0)
 
/* Used for switching the constants addressing mode on gen4+ RENDER ring.
 * Gen6+ only supports relative addressing to dynamic state (default) and
 * absolute addressing.
 *
 * These flags are ignored for the BSD and BLT rings.
 */
#define I915_EXEC_CONSTANTS_MASK 	(3<<6)
#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
#define I915_EXEC_CONSTANTS_ABSOLUTE 	(1<<6)
#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
	__u64 flags;
	__u64 rsvd1; /* now used for context info */
	__u64 rsvd2;
};
 
/** Resets the SO write offset registers for transform feedback on gen7. */
#define I915_EXEC_GEN7_SOL_RESET	(1<<8)
 
#define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
#define i915_execbuffer2_set_context_id(eb2, context) \
	(eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
#define i915_execbuffer2_get_context_id(eb2) \
	((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
 
struct drm_i915_gem_pin {
	/** Handle of the buffer to be pinned. */
	__u32 handle;
	__u32 pad;
 
	/** alignment required within the aperture */
	__u64 alignment;
 
	/** Returned GTT offset of the buffer. */
	__u64 offset;
};
 
struct drm_i915_gem_unpin {
	/** Handle of the buffer to be unpinned. */
	__u32 handle;
	__u32 pad;
};
 
struct drm_i915_gem_busy {
	/** Handle of the buffer to check for busy */
	__u32 handle;
 
	/** Return busy status (1 if busy, 0 if idle).
	 * The high word is used to indicate on which rings the object
	 * currently resides:
	 *  16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
	 */
	__u32 busy;
};
 
#define I915_CACHEING_NONE		0
#define I915_CACHEING_CACHED		1
 
struct drm_i915_gem_cacheing {
	/**
	 * Handle of the buffer to set/get the cacheing level of. */
	__u32 handle;
 
	/**
	 * Cacheing level to apply or return value
	 *
	 * bits0-15 are for generic cacheing control (i.e. the above defined
	 * values). bits16-31 are reserved for platform-specific variations
	 * (e.g. l3$ caching on gen7). */
	__u32 cacheing;
};
 
#define I915_TILING_NONE	0
#define I915_TILING_X		1
#define I915_TILING_Y		2
 
#define I915_BIT_6_SWIZZLE_NONE		0
#define I915_BIT_6_SWIZZLE_9		1
#define I915_BIT_6_SWIZZLE_9_10		2
#define I915_BIT_6_SWIZZLE_9_11		3
#define I915_BIT_6_SWIZZLE_9_10_11	4
/* Not seen by userland */
#define I915_BIT_6_SWIZZLE_UNKNOWN	5
/* Seen by userland. */
#define I915_BIT_6_SWIZZLE_9_17		6
#define I915_BIT_6_SWIZZLE_9_10_17	7
 
struct drm_i915_gem_set_tiling {
	/** Handle of the buffer to have its tiling state updated */
	__u32 handle;
 
	/**
	 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
	 * I915_TILING_Y).
	 *
	 * This value is to be set on request, and will be updated by the
	 * kernel on successful return with the actual chosen tiling layout.
	 *
	 * The tiling mode may be demoted to I915_TILING_NONE when the system
	 * has bit 6 swizzling that can't be managed correctly by GEM.
	 *
	 * Buffer contents become undefined when changing tiling_mode.
	 */
	__u32 tiling_mode;
 
	/**
	 * Stride in bytes for the object when in I915_TILING_X or
	 * I915_TILING_Y.
	 */
	__u32 stride;
 
	/**
	 * Returned address bit 6 swizzling required for CPU access through
	 * mmap mapping.
	 */
	__u32 swizzle_mode;
};
 
struct drm_i915_gem_get_tiling {
	/** Handle of the buffer to get tiling state for. */
	__u32 handle;
 
	/**
	 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
	 * I915_TILING_Y).
	 */
	__u32 tiling_mode;
 
	/**
	 * Returned address bit 6 swizzling required for CPU access through
	 * mmap mapping.
	 */
	__u32 swizzle_mode;
};
 
struct drm_i915_gem_get_aperture {
	/** Total size of the aperture used by i915_gem_execbuffer, in bytes */
	__u64 aper_size;
 
	/**
	 * Available space in the aperture used by i915_gem_execbuffer, in
	 * bytes
	 */
	__u64 aper_available_size;
};
 
struct drm_i915_get_pipe_from_crtc_id {
	/** ID of CRTC being requested **/
	__u32 crtc_id;
 
	/** pipe of requested CRTC **/
	__u32 pipe;
};
 
#define I915_MADV_WILLNEED 0
#define I915_MADV_DONTNEED 1
#define __I915_MADV_PURGED 2 /* internal state */
 
struct drm_i915_gem_madvise {
	/** Handle of the buffer to change the backing store advice */
	__u32 handle;
 
	/* Advice: either the buffer will be needed again in the near future,
	 *         or wont be and could be discarded under memory pressure.
	 */
	__u32 madv;
 
	/** Whether the backing store still exists. */
	__u32 retained;
};
 
/* flags */
#define I915_OVERLAY_TYPE_MASK 		0xff
#define I915_OVERLAY_YUV_PLANAR 	0x01
#define I915_OVERLAY_YUV_PACKED 	0x02
#define I915_OVERLAY_RGB		0x03
 
#define I915_OVERLAY_DEPTH_MASK		0xff00
#define I915_OVERLAY_RGB24		0x1000
#define I915_OVERLAY_RGB16		0x2000
#define I915_OVERLAY_RGB15		0x3000
#define I915_OVERLAY_YUV422		0x0100
#define I915_OVERLAY_YUV411		0x0200
#define I915_OVERLAY_YUV420		0x0300
#define I915_OVERLAY_YUV410		0x0400
 
#define I915_OVERLAY_SWAP_MASK		0xff0000
#define I915_OVERLAY_NO_SWAP		0x000000
#define I915_OVERLAY_UV_SWAP		0x010000
#define I915_OVERLAY_Y_SWAP		0x020000
#define I915_OVERLAY_Y_AND_UV_SWAP	0x030000
 
#define I915_OVERLAY_FLAGS_MASK		0xff000000
#define I915_OVERLAY_ENABLE		0x01000000
 
struct drm_intel_overlay_put_image {
	/* various flags and src format description */
	__u32 flags;
	/* source picture description */
	__u32 bo_handle;
	/* stride values and offsets are in bytes, buffer relative */
	__u16 stride_Y; /* stride for packed formats */
	__u16 stride_UV;
	__u32 offset_Y; /* offset for packet formats */
	__u32 offset_U;
	__u32 offset_V;
	/* in pixels */
	__u16 src_width;
	__u16 src_height;
	/* to compensate the scaling factors for partially covered surfaces */
	__u16 src_scan_width;
	__u16 src_scan_height;
	/* output crtc description */
	__u32 crtc_id;
	__u16 dst_x;
	__u16 dst_y;
	__u16 dst_width;
	__u16 dst_height;
};
 
/* flags */
#define I915_OVERLAY_UPDATE_ATTRS	(1<<0)
#define I915_OVERLAY_UPDATE_GAMMA	(1<<1)
struct drm_intel_overlay_attrs {
	__u32 flags;
	__u32 color_key;
	__s32 brightness;
	__u32 contrast;
	__u32 saturation;
	__u32 gamma0;
	__u32 gamma1;
	__u32 gamma2;
	__u32 gamma3;
	__u32 gamma4;
	__u32 gamma5;
};
 
/*
 * Intel sprite handling
 *
 * Color keying works with a min/mask/max tuple.  Both source and destination
 * color keying is allowed.
 *
 * Source keying:
 * Sprite pixels within the min & max values, masked against the color channels
 * specified in the mask field, will be transparent.  All other pixels will
 * be displayed on top of the primary plane.  For RGB surfaces, only the min
 * and mask fields will be used; ranged compares are not allowed.
 *
 * Destination keying:
 * Primary plane pixels that match the min value, masked against the color
 * channels specified in the mask field, will be replaced by corresponding
 * pixels from the sprite plane.
 *
 * Note that source & destination keying are exclusive; only one can be
 * active on a given plane.
 */
 
#define I915_SET_COLORKEY_NONE		(1<<0) /* disable color key matching */
#define I915_SET_COLORKEY_DESTINATION	(1<<1)
#define I915_SET_COLORKEY_SOURCE	(1<<2)
struct drm_intel_sprite_colorkey {
	__u32 plane_id;
	__u32 min_value;
	__u32 channel_mask;
	__u32 max_value;
	__u32 flags;
};
 
struct drm_i915_gem_wait {
	/** Handle of BO we shall wait on */
	__u32 bo_handle;
	__u32 flags;
	/** Number of nanoseconds to wait, Returns time remaining. */
	__s64 timeout_ns;
};
 
struct drm_i915_gem_context_create {
	/*  output: id of new context*/
	__u32 ctx_id;
	__u32 pad;
};
 
struct drm_i915_gem_context_destroy {
	__u32 ctx_id;
	__u32 pad;
};
 
struct drm_i915_reg_read {
	__u64 offset;
	__u64 val; /* Return value */
};
 
struct drm_i915_reset_stats {
	__u32 ctx_id;
	__u32 flags;
 
	/* All resets since boot/module reload, for all contexts */
	__u32 reset_count;
 
	/* Number of batches lost when active in GPU, for this context */
	__u32 batch_active;
 
	/* Number of batches lost pending for execution, for this context */
	__u32 batch_pending;
 
	__u32 pad;
};
 
 
 
 
 
 
 
 
 
 
struct drm_i915_fb_info {
    __u32 name;
    __u32 width;
    __u32 height;
    __u32 pitch;
    __u32 tiling;
    __u32 crtc;
    __u32 pipe;
};
 
struct drm_i915_mask_update {
    __u32 handle;
    __u32 dx;
    __u32 dy;
    __u32 width;
    __u32 height;
    __u32 bo_pitch;
    __u32 bo_map;
};
 
#endif				/* _I915_DRM_H_ */
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Rev 4502	Rev 4768
1	/*	1	/*
2	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.	2	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3	* All Rights Reserved.	3	* All Rights Reserved.
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a	5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the	6	* copy of this software and associated documentation files (the
7	* "Software"), to deal in the Software without restriction, including	7	* "Software"), to deal in the Software without restriction, including
8	* without limitation the rights to use, copy, modify, merge, publish,	8	* without limitation the rights to use, copy, modify, merge, publish,
9	* distribute, sub license, and/or sell copies of the Software, and to	9	* distribute, sub license, and/or sell copies of the Software, and to
10	* permit persons to whom the Software is furnished to do so, subject to	10	* permit persons to whom the Software is furnished to do so, subject to
11	* the following conditions:	11	* the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice (including the	13	* The above copyright notice and this permission notice (including the
14	* next paragraph) shall be included in all copies or substantial portions	14	* next paragraph) shall be included in all copies or substantial portions
15	* of the Software.	15	* of the Software.
16	*	16	*
17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF	18	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR	20	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,	21	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE	22	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.	23	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24	*	24	*
25	*/	25	*/
26		26
27	#ifndef _I915_DRM_H_	27	#ifndef _I915_DRM_H_
28	#define _I915_DRM_H_	28	#define _I915_DRM_H_
29		29
30	#include "drm.h"	30	#include "drm.h"
31		31
32	/* Please note that modifications to all structs defined here are	32	/* Please note that modifications to all structs defined here are
33	* subject to backwards-compatibility constraints.	33	* subject to backwards-compatibility constraints.
34	*/	34	*/
35		35
36		36
37	/* Each region is a minimum of 16k, and there are at most 255 of them.	37	/* Each region is a minimum of 16k, and there are at most 255 of them.
38	*/	38	*/
39	#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use	39	#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
40	* of chars for next/prev indices */	40	* of chars for next/prev indices */
41	#define I915_LOG_MIN_TEX_REGION_SIZE 14	41	#define I915_LOG_MIN_TEX_REGION_SIZE 14
42		42
43	typedef struct _drm_i915_init {	43	typedef struct _drm_i915_init {
44	enum {	44	enum {
45	I915_INIT_DMA = 0x01,	45	I915_INIT_DMA = 0x01,
46	I915_CLEANUP_DMA = 0x02,	46	I915_CLEANUP_DMA = 0x02,
47	I915_RESUME_DMA = 0x03	47	I915_RESUME_DMA = 0x03
48	} func;	48	} func;
49	unsigned int mmio_offset;	49	unsigned int mmio_offset;
50	int sarea_priv_offset;	50	int sarea_priv_offset;
51	unsigned int ring_start;	51	unsigned int ring_start;
52	unsigned int ring_end;	52	unsigned int ring_end;
53	unsigned int ring_size;	53	unsigned int ring_size;
54	unsigned int front_offset;	54	unsigned int front_offset;
55	unsigned int back_offset;	55	unsigned int back_offset;
56	unsigned int depth_offset;	56	unsigned int depth_offset;
57	unsigned int w;	57	unsigned int w;
58	unsigned int h;	58	unsigned int h;
59	unsigned int pitch;	59	unsigned int pitch;
60	unsigned int pitch_bits;	60	unsigned int pitch_bits;
61	unsigned int back_pitch;	61	unsigned int back_pitch;
62	unsigned int depth_pitch;	62	unsigned int depth_pitch;
63	unsigned int cpp;	63	unsigned int cpp;
64	unsigned int chipset;	64	unsigned int chipset;
65	} drm_i915_init_t;	65	} drm_i915_init_t;
66		66
67	typedef struct _drm_i915_sarea {	67	typedef struct _drm_i915_sarea {
68	struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];	68	struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
69	int last_upload; /* last time texture was uploaded */	69	int last_upload; /* last time texture was uploaded */
70	int last_enqueue; /* last time a buffer was enqueued */	70	int last_enqueue; /* last time a buffer was enqueued */
71	int last_dispatch; /* age of the most recently dispatched buffer */	71	int last_dispatch; /* age of the most recently dispatched buffer */
72	int ctxOwner; /* last context to upload state */	72	int ctxOwner; /* last context to upload state */
73	int texAge;	73	int texAge;
74	int pf_enabled; /* is pageflipping allowed? */	74	int pf_enabled; /* is pageflipping allowed? */
75	int pf_active;	75	int pf_active;
76	int pf_current_page; /* which buffer is being displayed? */	76	int pf_current_page; /* which buffer is being displayed? */
77	int perf_boxes; /* performance boxes to be displayed */	77	int perf_boxes; /* performance boxes to be displayed */
78	int width, height; /* screen size in pixels */	78	int width, height; /* screen size in pixels */
79		79
80	drm_handle_t front_handle;	80	drm_handle_t front_handle;
81	int front_offset;	81	int front_offset;
82	int front_size;	82	int front_size;
83		83
84	drm_handle_t back_handle;	84	drm_handle_t back_handle;
85	int back_offset;	85	int back_offset;
86	int back_size;	86	int back_size;
87		87
88	drm_handle_t depth_handle;	88	drm_handle_t depth_handle;
89	int depth_offset;	89	int depth_offset;
90	int depth_size;	90	int depth_size;
91		91
92	drm_handle_t tex_handle;	92	drm_handle_t tex_handle;
93	int tex_offset;	93	int tex_offset;
94	int tex_size;	94	int tex_size;
95	int log_tex_granularity;	95	int log_tex_granularity;
96	int pitch;	96	int pitch;
97	int rotation; /* 0, 90, 180 or 270 */	97	int rotation; /* 0, 90, 180 or 270 */
98	int rotated_offset;	98	int rotated_offset;
99	int rotated_size;	99	int rotated_size;
100	int rotated_pitch;	100	int rotated_pitch;
101	int virtualX, virtualY;	101	int virtualX, virtualY;
102		102
103	unsigned int front_tiled;	103	unsigned int front_tiled;
104	unsigned int back_tiled;	104	unsigned int back_tiled;
105	unsigned int depth_tiled;	105	unsigned int depth_tiled;
106	unsigned int rotated_tiled;	106	unsigned int rotated_tiled;
107	unsigned int rotated2_tiled;	107	unsigned int rotated2_tiled;
108		108
109	int pipeA_x;	109	int pipeA_x;
110	int pipeA_y;	110	int pipeA_y;
111	int pipeA_w;	111	int pipeA_w;
112	int pipeA_h;	112	int pipeA_h;
113	int pipeB_x;	113	int pipeB_x;
114	int pipeB_y;	114	int pipeB_y;
115	int pipeB_w;	115	int pipeB_w;
116	int pipeB_h;	116	int pipeB_h;
117		117
118	/* fill out some space for old userspace triple buffer */	118	/* fill out some space for old userspace triple buffer */
119	drm_handle_t unused_handle;	119	drm_handle_t unused_handle;
120	__u32 unused1, unused2, unused3;	120	__u32 unused1, unused2, unused3;
121		121
122	/* buffer object handles for static buffers. May change	122	/* buffer object handles for static buffers. May change
123	* over the lifetime of the client.	123	* over the lifetime of the client.
124	*/	124	*/
125	__u32 front_bo_handle;	125	__u32 front_bo_handle;
126	__u32 back_bo_handle;	126	__u32 back_bo_handle;
127	__u32 unused_bo_handle;	127	__u32 unused_bo_handle;
128	__u32 depth_bo_handle;	128	__u32 depth_bo_handle;
129		129
130	} drm_i915_sarea_t;	130	} drm_i915_sarea_t;
131		131
132	/* due to userspace building against these headers we need some compat here */	132	/* due to userspace building against these headers we need some compat here */
133	#define planeA_x pipeA_x	133	#define planeA_x pipeA_x
134	#define planeA_y pipeA_y	134	#define planeA_y pipeA_y
135	#define planeA_w pipeA_w	135	#define planeA_w pipeA_w
136	#define planeA_h pipeA_h	136	#define planeA_h pipeA_h
137	#define planeB_x pipeB_x	137	#define planeB_x pipeB_x
138	#define planeB_y pipeB_y	138	#define planeB_y pipeB_y
139	#define planeB_w pipeB_w	139	#define planeB_w pipeB_w
140	#define planeB_h pipeB_h	140	#define planeB_h pipeB_h
141		141
142	/* Flags for perf_boxes	142	/* Flags for perf_boxes
143	*/	143	*/
144	#define I915_BOX_RING_EMPTY 0x1	144	#define I915_BOX_RING_EMPTY 0x1
145	#define I915_BOX_FLIP 0x2	145	#define I915_BOX_FLIP 0x2
146	#define I915_BOX_WAIT 0x4	146	#define I915_BOX_WAIT 0x4
147	#define I915_BOX_TEXTURE_LOAD 0x8	147	#define I915_BOX_TEXTURE_LOAD 0x8
148	#define I915_BOX_LOST_CONTEXT 0x10	148	#define I915_BOX_LOST_CONTEXT 0x10
149		149
150	/* I915 specific ioctls	150	/* I915 specific ioctls
151	* The device specific ioctl range is 0x40 to 0x79.	151	* The device specific ioctl range is 0x40 to 0x79.
152	*/	152	*/
153	#define DRM_I915_INIT 0x00	153	#define DRM_I915_INIT 0x00
154	#define DRM_I915_FLUSH 0x01	154	#define DRM_I915_FLUSH 0x01
155	#define DRM_I915_FLIP 0x02	155	#define DRM_I915_FLIP 0x02
156	#define DRM_I915_BATCHBUFFER 0x03	156	#define DRM_I915_BATCHBUFFER 0x03
157	#define DRM_I915_IRQ_EMIT 0x04	157	#define DRM_I915_IRQ_EMIT 0x04
158	#define DRM_I915_IRQ_WAIT 0x05	158	#define DRM_I915_IRQ_WAIT 0x05
159	#define DRM_I915_GETPARAM 0x06	159	#define DRM_I915_GETPARAM 0x06
160	#define DRM_I915_SETPARAM 0x07	160	#define DRM_I915_SETPARAM 0x07
161	#define DRM_I915_ALLOC 0x08	161	#define DRM_I915_ALLOC 0x08
162	#define DRM_I915_FREE 0x09	162	#define DRM_I915_FREE 0x09
163	#define DRM_I915_INIT_HEAP 0x0a	163	#define DRM_I915_INIT_HEAP 0x0a
164	#define DRM_I915_CMDBUFFER 0x0b	164	#define DRM_I915_CMDBUFFER 0x0b
165	#define DRM_I915_DESTROY_HEAP 0x0c	165	#define DRM_I915_DESTROY_HEAP 0x0c
166	#define DRM_I915_SET_VBLANK_PIPE 0x0d	166	#define DRM_I915_SET_VBLANK_PIPE 0x0d
167	#define DRM_I915_GET_VBLANK_PIPE 0x0e	167	#define DRM_I915_GET_VBLANK_PIPE 0x0e
168	#define DRM_I915_VBLANK_SWAP 0x0f	168	#define DRM_I915_VBLANK_SWAP 0x0f
169	#define DRM_I915_HWS_ADDR 0x11	169	#define DRM_I915_HWS_ADDR 0x11
170	#define DRM_I915_GEM_INIT 0x13	170	#define DRM_I915_GEM_INIT 0x13
171	#define DRM_I915_GEM_EXECBUFFER 0x14	171	#define DRM_I915_GEM_EXECBUFFER 0x14
172	#define DRM_I915_GEM_PIN 0x15	172	#define DRM_I915_GEM_PIN 0x15
173	#define DRM_I915_GEM_UNPIN 0x16	173	#define DRM_I915_GEM_UNPIN 0x16
174	#define DRM_I915_GEM_BUSY 0x17	174	#define DRM_I915_GEM_BUSY 0x17
175	#define DRM_I915_GEM_THROTTLE 0x18	175	#define DRM_I915_GEM_THROTTLE 0x18
176	#define DRM_I915_GEM_ENTERVT 0x19	176	#define DRM_I915_GEM_ENTERVT 0x19
177	#define DRM_I915_GEM_LEAVEVT 0x1a	177	#define DRM_I915_GEM_LEAVEVT 0x1a
178	#define DRM_I915_GEM_CREATE 0x1b	178	#define DRM_I915_GEM_CREATE 0x1b
179	#define DRM_I915_GEM_PREAD 0x1c	179	#define DRM_I915_GEM_PREAD 0x1c
180	#define DRM_I915_GEM_PWRITE 0x1d	180	#define DRM_I915_GEM_PWRITE 0x1d
181	#define DRM_I915_GEM_MMAP 0x1e	181	#define DRM_I915_GEM_MMAP 0x1e
182	#define DRM_I915_GEM_SET_DOMAIN 0x1f	182	#define DRM_I915_GEM_SET_DOMAIN 0x1f
183	#define DRM_I915_GEM_SW_FINISH 0x20	183	#define DRM_I915_GEM_SW_FINISH 0x20
184	#define DRM_I915_GEM_SET_TILING 0x21	184	#define DRM_I915_GEM_SET_TILING 0x21
185	#define DRM_I915_GEM_GET_TILING 0x22	185	#define DRM_I915_GEM_GET_TILING 0x22
186	#define DRM_I915_GEM_GET_APERTURE 0x23	186	#define DRM_I915_GEM_GET_APERTURE 0x23
187	#define DRM_I915_GEM_MMAP_GTT 0x24	187	#define DRM_I915_GEM_MMAP_GTT 0x24
188	#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25	188	#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
189	#define DRM_I915_GEM_MADVISE 0x26	189	#define DRM_I915_GEM_MADVISE 0x26
190	#define DRM_I915_OVERLAY_PUT_IMAGE 0x27	190	#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
191	#define DRM_I915_OVERLAY_ATTRS 0x28	191	#define DRM_I915_OVERLAY_ATTRS 0x28
192	#define DRM_I915_GEM_EXECBUFFER2 0x29	192	#define DRM_I915_GEM_EXECBUFFER2 0x29
193	#define DRM_I915_GET_SPRITE_COLORKEY 0x2a	193	#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
194	#define DRM_I915_SET_SPRITE_COLORKEY 0x2b	194	#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
195	#define DRM_I915_GEM_WAIT 0x2c	195	#define DRM_I915_GEM_WAIT 0x2c
196	#define DRM_I915_GEM_CONTEXT_CREATE 0x2d	196	#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
197	#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e	197	#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
198	#define DRM_I915_GEM_SET_CACHEING 0x2f	198	#define DRM_I915_GEM_SET_CACHEING 0x2f
199	#define DRM_I915_GEM_GET_CACHEING 0x30	199	#define DRM_I915_GEM_GET_CACHEING 0x30
200	#define DRM_I915_REG_READ 0x31	200	#define DRM_I915_REG_READ 0x31
201	#define DRM_I915_GET_RESET_STATS 0x32	201	#define DRM_I915_GET_RESET_STATS 0x32
202		202
203	#define DRM_IOCTL_I915_INIT	203	#define DRM_IOCTL_I915_INIT
204	#define DRM_IOCTL_I915_FLUSH	204	#define DRM_IOCTL_I915_FLUSH
205	#define DRM_IOCTL_I915_FLIP	205	#define DRM_IOCTL_I915_FLIP
206	#define DRM_IOCTL_I915_BATCHBUFFER	206	#define DRM_IOCTL_I915_BATCHBUFFER
207	#define DRM_IOCTL_I915_IRQ_EMIT	207	#define DRM_IOCTL_I915_IRQ_EMIT
208	#define DRM_IOCTL_I915_IRQ_WAIT	208	#define DRM_IOCTL_I915_IRQ_WAIT
209	#define DRM_IOCTL_I915_GETPARAM SRV_I915_GET_PARAM	209	#define DRM_IOCTL_I915_GETPARAM SRV_I915_GET_PARAM
210	#define DRM_IOCTL_I915_SETPARAM	210	#define DRM_IOCTL_I915_SETPARAM
211	#define DRM_IOCTL_I915_ALLOC	211	#define DRM_IOCTL_I915_ALLOC
212	#define DRM_IOCTL_I915_FREE	212	#define DRM_IOCTL_I915_FREE
213	#define DRM_IOCTL_I915_INIT_HEAP	213	#define DRM_IOCTL_I915_INIT_HEAP
214	#define DRM_IOCTL_I915_CMDBUFFER	214	#define DRM_IOCTL_I915_CMDBUFFER
215	#define DRM_IOCTL_I915_DESTROY_HEAP	215	#define DRM_IOCTL_I915_DESTROY_HEAP
216	#define DRM_IOCTL_I915_SET_VBLANK_PIPE	216	#define DRM_IOCTL_I915_SET_VBLANK_PIPE
217	#define DRM_IOCTL_I915_GET_VBLANK_PIPE	217	#define DRM_IOCTL_I915_GET_VBLANK_PIPE
218	#define DRM_IOCTL_I915_VBLANK_SWAP	218	#define DRM_IOCTL_I915_VBLANK_SWAP
219	#define DRM_IOCTL_I915_HWS_ADDR	219	#define DRM_IOCTL_I915_HWS_ADDR
220	#define DRM_IOCTL_I915_GEM_INIT	220	#define DRM_IOCTL_I915_GEM_INIT
221	#define DRM_IOCTL_I915_GEM_EXECBUFFER	221	#define DRM_IOCTL_I915_GEM_EXECBUFFER
222	#define DRM_IOCTL_I915_GEM_EXECBUFFER2 SRV_I915_GEM_EXECBUFFER2	222	#define DRM_IOCTL_I915_GEM_EXECBUFFER2 SRV_I915_GEM_EXECBUFFER2
223	#define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN	223	#define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN
224	#define DRM_IOCTL_I915_GEM_UNPIN SRV_I915_GEM_UNPIN	224	#define DRM_IOCTL_I915_GEM_UNPIN SRV_I915_GEM_UNPIN
225	#define DRM_IOCTL_I915_GEM_BUSY SRV_I915_GEM_BUSY	225	#define DRM_IOCTL_I915_GEM_BUSY SRV_I915_GEM_BUSY
226	#define DRM_IOCTL_I915_GEM_SET_CACHEING SRV_I915_GEM_SET_CACHING	226	#define DRM_IOCTL_I915_GEM_SET_CACHEING SRV_I915_GEM_SET_CACHING
227	#define DRM_IOCTL_I915_GEM_GET_CACHEING	227	#define DRM_IOCTL_I915_GEM_GET_CACHEING
228	#define DRM_IOCTL_I915_GEM_THROTTLE SRV_I915_GEM_THROTTLE	228	#define DRM_IOCTL_I915_GEM_THROTTLE SRV_I915_GEM_THROTTLE
229	#define DRM_IOCTL_I915_GEM_ENTERVT	229	#define DRM_IOCTL_I915_GEM_ENTERVT
230	#define DRM_IOCTL_I915_GEM_LEAVEVT	230	#define DRM_IOCTL_I915_GEM_LEAVEVT
231	#define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE	231	#define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE
232	#define DRM_IOCTL_I915_GEM_PREAD	232	#define DRM_IOCTL_I915_GEM_PREAD
233	#define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE	233	#define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE
234	#define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP	234	#define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP
235	#define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT	235	#define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT
236	#define DRM_IOCTL_I915_GEM_SET_DOMAIN SRV_I915_GEM_SET_DOMAIN	236	#define DRM_IOCTL_I915_GEM_SET_DOMAIN SRV_I915_GEM_SET_DOMAIN
237	#define DRM_IOCTL_I915_GEM_SW_FINISH	237	#define DRM_IOCTL_I915_GEM_SW_FINISH
238	#define DRM_IOCTL_I915_GEM_SET_TILING SRV_I915_GEM_SET_TILING	238	#define DRM_IOCTL_I915_GEM_SET_TILING SRV_I915_GEM_SET_TILING
239	#define DRM_IOCTL_I915_GEM_GET_TILING SRV_I915_GEM_GET_TILING	239	#define DRM_IOCTL_I915_GEM_GET_TILING SRV_I915_GEM_GET_TILING
240	#define DRM_IOCTL_I915_GEM_GET_APERTURE SRV_I915_GEM_GET_APERTURE	240	#define DRM_IOCTL_I915_GEM_GET_APERTURE SRV_I915_GEM_GET_APERTURE
241	#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID	241	#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID
242	#define DRM_IOCTL_I915_GEM_MADVISE	242	#define DRM_IOCTL_I915_GEM_MADVISE
243	#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE	243	#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE
244	#define DRM_IOCTL_I915_OVERLAY_ATTRS	244	#define DRM_IOCTL_I915_OVERLAY_ATTRS
245	#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY	245	#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY
246	#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY	246	#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY
247	#define DRM_IOCTL_I915_GEM_WAIT SRV_I915_GEM_WAIT	247	#define DRM_IOCTL_I915_GEM_WAIT SRV_I915_GEM_WAIT
248	#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE SRV_I915_GEM_CONTEXT_CREATE	248	#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE SRV_I915_GEM_CONTEXT_CREATE
249	#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY SRV_I915_GEM_CONTEXT_DESTROY	249	#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY SRV_I915_GEM_CONTEXT_DESTROY
250	#define DRM_IOCTL_I915_REG_READ SRV_I915_REG_READ	250	#define DRM_IOCTL_I915_REG_READ SRV_I915_REG_READ
251		251
252		252
253	/* Allow drivers to submit batchbuffers directly to hardware, relying	253	/* Allow drivers to submit batchbuffers directly to hardware, relying
254	* on the security mechanisms provided by hardware.	254	* on the security mechanisms provided by hardware.
255	*/	255	*/
256	typedef struct drm_i915_batchbuffer {	256	typedef struct drm_i915_batchbuffer {
257	int start; /* agp offset */	257	int start; /* agp offset */
258	int used; /* nr bytes in use */	258	int used; /* nr bytes in use */
259	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */	259	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
260	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */	260	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
261	int num_cliprects; /* mulitpass with multiple cliprects? */	261	int num_cliprects; /* mulitpass with multiple cliprects? */
262	struct drm_clip_rect cliprects; / pointer to userspace cliprects */	262	struct drm_clip_rect cliprects; / pointer to userspace cliprects */
263	} drm_i915_batchbuffer_t;	263	} drm_i915_batchbuffer_t;
264		264
265	/* As above, but pass a pointer to userspace buffer which can be	265	/* As above, but pass a pointer to userspace buffer which can be
266	* validated by the kernel prior to sending to hardware.	266	* validated by the kernel prior to sending to hardware.
267	*/	267	*/
268	typedef struct _drm_i915_cmdbuffer {	268	typedef struct _drm_i915_cmdbuffer {
269	char buf; / pointer to userspace command buffer */	269	char buf; / pointer to userspace command buffer */
270	int sz; /* nr bytes in buf */	270	int sz; /* nr bytes in buf */
271	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */	271	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
272	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */	272	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
273	int num_cliprects; /* mulitpass with multiple cliprects? */	273	int num_cliprects; /* mulitpass with multiple cliprects? */
274	struct drm_clip_rect cliprects; / pointer to userspace cliprects */	274	struct drm_clip_rect cliprects; / pointer to userspace cliprects */
275	} drm_i915_cmdbuffer_t;	275	} drm_i915_cmdbuffer_t;
276		276
277	/* Userspace can request & wait on irq's:	277	/* Userspace can request & wait on irq's:
278	*/	278	*/
279	typedef struct drm_i915_irq_emit {	279	typedef struct drm_i915_irq_emit {
280	int *irq_seq;	280	int *irq_seq;
281	} drm_i915_irq_emit_t;	281	} drm_i915_irq_emit_t;
282		282
283	typedef struct drm_i915_irq_wait {	283	typedef struct drm_i915_irq_wait {
284	int irq_seq;	284	int irq_seq;
285	} drm_i915_irq_wait_t;	285	} drm_i915_irq_wait_t;
286		286
287	/* Ioctl to query kernel params:	287	/* Ioctl to query kernel params:
288	*/	288	*/
289	#define I915_PARAM_IRQ_ACTIVE 1	289	#define I915_PARAM_IRQ_ACTIVE 1
290	#define I915_PARAM_ALLOW_BATCHBUFFER 2	290	#define I915_PARAM_ALLOW_BATCHBUFFER 2
291	#define I915_PARAM_LAST_DISPATCH 3	291	#define I915_PARAM_LAST_DISPATCH 3
292	#define I915_PARAM_CHIPSET_ID 4	292	#define I915_PARAM_CHIPSET_ID 4
293	#define I915_PARAM_HAS_GEM 5	293	#define I915_PARAM_HAS_GEM 5
294	#define I915_PARAM_NUM_FENCES_AVAIL 6	294	#define I915_PARAM_NUM_FENCES_AVAIL 6
295	#define I915_PARAM_HAS_OVERLAY 7	295	#define I915_PARAM_HAS_OVERLAY 7
296	#define I915_PARAM_HAS_PAGEFLIPPING 8	296	#define I915_PARAM_HAS_PAGEFLIPPING 8
297	#define I915_PARAM_HAS_EXECBUF2 9	297	#define I915_PARAM_HAS_EXECBUF2 9
298	#define I915_PARAM_HAS_BSD 10	298	#define I915_PARAM_HAS_BSD 10
299	#define I915_PARAM_HAS_BLT 11	299	#define I915_PARAM_HAS_BLT 11
300	#define I915_PARAM_HAS_RELAXED_FENCING 12	300	#define I915_PARAM_HAS_RELAXED_FENCING 12
301	#define I915_PARAM_HAS_COHERENT_RINGS 13	301	#define I915_PARAM_HAS_COHERENT_RINGS 13
302	#define I915_PARAM_HAS_EXEC_CONSTANTS 14	302	#define I915_PARAM_HAS_EXEC_CONSTANTS 14
303	#define I915_PARAM_HAS_RELAXED_DELTA 15	303	#define I915_PARAM_HAS_RELAXED_DELTA 15
304	#define I915_PARAM_HAS_GEN7_SOL_RESET 16	304	#define I915_PARAM_HAS_GEN7_SOL_RESET 16
305	#define I915_PARAM_HAS_LLC 17	305	#define I915_PARAM_HAS_LLC 17
306	#define I915_PARAM_HAS_ALIASING_PPGTT 18	306	#define I915_PARAM_HAS_ALIASING_PPGTT 18
307	#define I915_PARAM_HAS_WAIT_TIMEOUT 19	307	#define I915_PARAM_HAS_WAIT_TIMEOUT 19
308	#define I915_PARAM_HAS_VEBOX 22	308	#define I915_PARAM_HAS_VEBOX 22
309		309
310	typedef struct drm_i915_getparam {	310	typedef struct drm_i915_getparam {
311	int param;	311	int param;
312	int *value;	312	int *value;
313	} drm_i915_getparam_t;	313	} drm_i915_getparam_t;
314		314
315	/* Ioctl to set kernel params:	315	/* Ioctl to set kernel params:
316	*/	316	*/
317	#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1	317	#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
318	#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2	318	#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
319	#define I915_SETPARAM_ALLOW_BATCHBUFFER 3	319	#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
320	#define I915_SETPARAM_NUM_USED_FENCES 4	320	#define I915_SETPARAM_NUM_USED_FENCES 4
321		321
322	typedef struct drm_i915_setparam {	322	typedef struct drm_i915_setparam {
323	int param;	323	int param;
324	int value;	324	int value;
325	} drm_i915_setparam_t;	325	} drm_i915_setparam_t;
326		326
327	/* A memory manager for regions of shared memory:	327	/* A memory manager for regions of shared memory:
328	*/	328	*/
329	#define I915_MEM_REGION_AGP 1	329	#define I915_MEM_REGION_AGP 1
330		330
331	typedef struct drm_i915_mem_alloc {	331	typedef struct drm_i915_mem_alloc {
332	int region;	332	int region;
333	int alignment;	333	int alignment;
334	int size;	334	int size;
335	int region_offset; / offset from start of fb or agp */	335	int region_offset; / offset from start of fb or agp */
336	} drm_i915_mem_alloc_t;	336	} drm_i915_mem_alloc_t;
337		337
338	typedef struct drm_i915_mem_free {	338	typedef struct drm_i915_mem_free {
339	int region;	339	int region;
340	int region_offset;	340	int region_offset;
341	} drm_i915_mem_free_t;	341	} drm_i915_mem_free_t;
342		342
343	typedef struct drm_i915_mem_init_heap {	343	typedef struct drm_i915_mem_init_heap {
344	int region;	344	int region;
345	int size;	345	int size;
346	int start;	346	int start;
347	} drm_i915_mem_init_heap_t;	347	} drm_i915_mem_init_heap_t;
348		348
349	/* Allow memory manager to be torn down and re-initialized (eg on	349	/* Allow memory manager to be torn down and re-initialized (eg on
350	* rotate):	350	* rotate):
351	*/	351	*/
352	typedef struct drm_i915_mem_destroy_heap {	352	typedef struct drm_i915_mem_destroy_heap {
353	int region;	353	int region;
354	} drm_i915_mem_destroy_heap_t;	354	} drm_i915_mem_destroy_heap_t;
355		355
356	/* Allow X server to configure which pipes to monitor for vblank signals	356	/* Allow X server to configure which pipes to monitor for vblank signals
357	*/	357	*/
358	#define DRM_I915_VBLANK_PIPE_A 1	358	#define DRM_I915_VBLANK_PIPE_A 1
359	#define DRM_I915_VBLANK_PIPE_B 2	359	#define DRM_I915_VBLANK_PIPE_B 2
360		360
361	typedef struct drm_i915_vblank_pipe {	361	typedef struct drm_i915_vblank_pipe {
362	int pipe;	362	int pipe;
363	} drm_i915_vblank_pipe_t;	363	} drm_i915_vblank_pipe_t;
364		364
365	/* Schedule buffer swap at given vertical blank:	365	/* Schedule buffer swap at given vertical blank:
366	*/	366	*/
367	typedef struct drm_i915_vblank_swap {	367	typedef struct drm_i915_vblank_swap {
368	drm_drawable_t drawable;	368	drm_drawable_t drawable;
369	enum drm_vblank_seq_type seqtype;	369	enum drm_vblank_seq_type seqtype;
370	unsigned int sequence;	370	unsigned int sequence;
371	} drm_i915_vblank_swap_t;	371	} drm_i915_vblank_swap_t;
372		372
373	typedef struct drm_i915_hws_addr {	373	typedef struct drm_i915_hws_addr {
374	__u64 addr;	374	__u64 addr;
375	} drm_i915_hws_addr_t;	375	} drm_i915_hws_addr_t;
376		376
377	struct drm_i915_gem_init {	377	struct drm_i915_gem_init {
378	/**	378	/**
379	* Beginning offset in the GTT to be managed by the DRM memory	379	* Beginning offset in the GTT to be managed by the DRM memory
380	* manager.	380	* manager.
381	*/	381	*/
382	__u64 gtt_start;	382	__u64 gtt_start;
383	/**	383	/**
384	* Ending offset in the GTT to be managed by the DRM memory	384	* Ending offset in the GTT to be managed by the DRM memory
385	* manager.	385	* manager.
386	*/	386	*/
387	__u64 gtt_end;	387	__u64 gtt_end;
388	};	388	};
389		389
390	struct drm_i915_gem_create {	390	struct drm_i915_gem_create {
391	/**	391	/**
392	* Requested size for the object.	392	* Requested size for the object.
393	*	393	*
394	* The (page-aligned) allocated size for the object will be returned.	394	* The (page-aligned) allocated size for the object will be returned.
395	*/	395	*/
396	__u64 size;	396	__u64 size;
397	/**	397	/**
398	* Returned handle for the object.	398	* Returned handle for the object.
399	*	399	*
400	* Object handles are nonzero.	400	* Object handles are nonzero.
401	*/	401	*/
402	__u32 handle;	402	__u32 handle;
403	__u32 pad;	403	__u32 pad;
404	};	404	};
405		405
406	struct drm_i915_gem_pread {	406	struct drm_i915_gem_pread {
407	/** Handle for the object being read. */	407	/** Handle for the object being read. */
408	__u32 handle;	408	__u32 handle;
409	__u32 pad;	409	__u32 pad;
410	/** Offset into the object to read from */	410	/** Offset into the object to read from */
411	__u64 offset;	411	__u64 offset;
412	/** Length of data to read */	412	/** Length of data to read */
413	__u64 size;	413	__u64 size;
414	/**	414	/**
415	* Pointer to write the data into.	415	* Pointer to write the data into.
416	*	416	*
417	* This is a fixed-size type for 32/64 compatibility.	417	* This is a fixed-size type for 32/64 compatibility.
418	*/	418	*/
419	__u64 data_ptr;	419	__u64 data_ptr;
420	};	420	};
421		421
422	struct drm_i915_gem_pwrite {	422	struct drm_i915_gem_pwrite {
423	/** Handle for the object being written to. */	423	/** Handle for the object being written to. */
424	__u32 handle;	424	__u32 handle;
425	__u32 pad;	425	__u32 pad;
426	/** Offset into the object to write to */	426	/** Offset into the object to write to */
427	__u64 offset;	427	__u64 offset;
428	/** Length of data to write */	428	/** Length of data to write */
429	__u64 size;	429	__u64 size;
430	/**	430	/**
431	* Pointer to read the data from.	431	* Pointer to read the data from.
432	*	432	*
433	* This is a fixed-size type for 32/64 compatibility.	433	* This is a fixed-size type for 32/64 compatibility.
434	*/	434	*/
435	__u64 data_ptr;	435	__u64 data_ptr;
436	};	436	};
437		437
438	struct drm_i915_gem_mmap {	438	struct drm_i915_gem_mmap {
439	/** Handle for the object being mapped. */	439	/** Handle for the object being mapped. */
440	__u32 handle;	440	__u32 handle;
441	__u32 pad;	441	__u32 pad;
442	/** Offset in the object to map. */	442	/** Offset in the object to map. */
443	__u64 offset;	443	__u64 offset;
444	/**	444	/**
445	* Length of data to map.	445	* Length of data to map.
446	*	446	*
447	* The value will be page-aligned.	447	* The value will be page-aligned.
448	*/	448	*/
449	__u64 size;	449	__u64 size;
450	/**	450	/**
451	* Returned pointer the data was mapped at.	451	* Returned pointer the data was mapped at.
452	*	452	*
453	* This is a fixed-size type for 32/64 compatibility.	453	* This is a fixed-size type for 32/64 compatibility.
454	*/	454	*/
455	__u64 addr_ptr;	455	__u64 addr_ptr;
456	};	456	};
457		457
458	struct drm_i915_gem_mmap_gtt {	458	struct drm_i915_gem_mmap_gtt {
459	/** Handle for the object being mapped. */	459	/** Handle for the object being mapped. */
460	__u32 handle;	460	__u32 handle;
461	__u32 pad;	461	__u32 pad;
462	/**	462	/**
463	* Fake offset to use for subsequent mmap call	463	* Fake offset to use for subsequent mmap call
464	*	464	*
465	* This is a fixed-size type for 32/64 compatibility.	465	* This is a fixed-size type for 32/64 compatibility.
466	*/	466	*/
467	__u64 offset;	467	__u64 offset;
468	};	468	};
469		469
470	struct drm_i915_gem_set_domain {	470	struct drm_i915_gem_set_domain {
471	/** Handle for the object */	471	/** Handle for the object */
472	__u32 handle;	472	__u32 handle;
473		473
474	/** New read domains */	474	/** New read domains */
475	__u32 read_domains;	475	__u32 read_domains;
476		476
477	/** New write domain */	477	/** New write domain */
478	__u32 write_domain;	478	__u32 write_domain;
479	};	479	};
480		480
481	struct drm_i915_gem_sw_finish {	481	struct drm_i915_gem_sw_finish {
482	/** Handle for the object */	482	/** Handle for the object */
483	__u32 handle;	483	__u32 handle;
484	};	484	};
485		485
486	struct drm_i915_gem_relocation_entry {	486	struct drm_i915_gem_relocation_entry {
487	/**	487	/**
488	* Handle of the buffer being pointed to by this relocation entry.	488	* Handle of the buffer being pointed to by this relocation entry.
489	*	489	*
490	* It's appealing to make this be an index into the mm_validate_entry	490	* It's appealing to make this be an index into the mm_validate_entry
491	* list to refer to the buffer, but this allows the driver to create	491	* list to refer to the buffer, but this allows the driver to create
492	* a relocation list for state buffers and not re-write it per	492	* a relocation list for state buffers and not re-write it per
493	* exec using the buffer.	493	* exec using the buffer.
494	*/	494	*/
495	__u32 target_handle;	495	__u32 target_handle;
496		496
497	/**	497	/**
498	* Value to be added to the offset of the target buffer to make up	498	* Value to be added to the offset of the target buffer to make up
499	* the relocation entry.	499	* the relocation entry.
500	*/	500	*/

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(root)/contrib/sdk/sources/libdrm/include/drm/i915_drm.h – Rev 4502 → 4768