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Rev 4358 Rev 4401
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      if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
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      if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
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         nv50->state.rt_serialize = TRUE;
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         nv50->state.rt_serialize = TRUE;
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      mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
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      mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
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      mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING;
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      mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
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      /* only register for writing, otherwise we'd always serialize here */
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      /* only register for writing, otherwise we'd always serialize here */
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      BCTX_REFN(nv50->bufctx_3d, FB, &mt->base, WR);
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      BCTX_REFN(nv50->bufctx_3d, FB, &mt->base, WR);
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      if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
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      if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
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         nv50->state.rt_serialize = TRUE;
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         nv50->state.rt_serialize = TRUE;
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      mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
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      mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
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      mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING;
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      mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
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      BCTX_REFN(nv50->bufctx_3d, FB, &mt->base, WR);
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      BCTX_REFN(nv50->bufctx_3d, FB, &mt->base, WR);
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   } else {
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   } else {
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      BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
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      BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);