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6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
7 | http://0x04.net/cgit/index.cgi/rules-ng-ng |
7 | http://0x04.net/cgit/index.cgi/rules-ng-ng |
8 | git clone git://0x04.net/rules-ng-ng |
8 | git clone git://0x04.net/rules-ng-ng |
Line 9... | Line 9... | ||
9 | 9 | ||
10 | The rules-ng-ng source files this header was generated from are: |
10 | The rules-ng-ng source files this header was generated from are: |
11 | - /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml ( 42578 bytes, from 2013-06-02 13:10:46) |
11 | - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) |
- | 12 | - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) |
|
12 | - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) |
13 | - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) |
13 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 3094 bytes, from 2013-05-05 18:29:22) |
14 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) |
- | 15 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) |
|
Line 14... | Line 16... | ||
14 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) |
16 | - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05) |
15 | 17 | ||
Line 16... | Line 18... | ||
16 | Copyright (C) 2013 by the following authors: |
18 | Copyright (C) 2013 by the following authors: |
Line 111... | Line 113... | ||
111 | enum adreno_rb_depth_format { |
113 | enum adreno_rb_depth_format { |
112 | DEPTHX_16 = 0, |
114 | DEPTHX_16 = 0, |
113 | DEPTHX_24_8 = 1, |
115 | DEPTHX_24_8 = 1, |
114 | }; |
116 | }; |
Line -... | Line 117... | ||
- | 117 | ||
- | 118 | enum adreno_mmu_clnt_beh { |
|
- | 119 | BEH_NEVR = 0, |
|
- | 120 | BEH_TRAN_RNG = 1, |
|
- | 121 | BEH_TRAN_FLT = 2, |
|
- | 122 | }; |
|
- | 123 | ||
- | 124 | #define REG_AXXX_MH_MMU_CONFIG 0x00000040 |
|
- | 125 | #define AXXX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 |
|
- | 126 | #define AXXX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 |
|
- | 127 | #define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 |
|
- | 128 | #define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 |
|
- | 129 | static inline uint32_t AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
|
- | 130 | { |
|
- | 131 | return ((val) << AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; |
|
- | 132 | } |
|
- | 133 | #define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 |
|
- | 134 | #define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 |
|
- | 135 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
|
- | 136 | { |
|
- | 137 | return ((val) << AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; |
|
- | 138 | } |
|
- | 139 | #define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 |
|
- | 140 | #define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 |
|
- | 141 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
|
- | 142 | { |
|
- | 143 | return ((val) << AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; |
|
- | 144 | } |
|
- | 145 | #define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 |
|
- | 146 | #define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 |
|
- | 147 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
|
- | 148 | { |
|
- | 149 | return ((val) << AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; |
|
- | 150 | } |
|
- | 151 | #define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 |
|
- | 152 | #define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 |
|
- | 153 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
|
- | 154 | { |
|
- | 155 | return ((val) << AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; |
|
- | 156 | } |
|
- | 157 | #define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 |
|
- | 158 | #define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 |
|
- | 159 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
|
- | 160 | { |
|
- | 161 | return ((val) << AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; |
|
- | 162 | } |
|
- | 163 | #define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 |
|
- | 164 | #define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 |
|
- | 165 | static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
|
- | 166 | { |
|
- | 167 | return ((val) << AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; |
|
- | 168 | } |
|
- | 169 | #define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 |
|
- | 170 | #define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 |
|
- | 171 | static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
|
- | 172 | { |
|
- | 173 | return ((val) << AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; |
|
- | 174 | } |
|
- | 175 | #define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 |
|
- | 176 | #define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 |
|
- | 177 | static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
|
- | 178 | { |
|
- | 179 | return ((val) << AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; |
|
- | 180 | } |
|
- | 181 | #define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 |
|
- | 182 | #define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 |
|
- | 183 | static inline uint32_t AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
|
- | 184 | { |
|
- | 185 | return ((val) << AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; |
|
- | 186 | } |
|
- | 187 | #define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 |
|
- | 188 | #define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 |
|
- | 189 | static inline uint32_t AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
|
- | 190 | { |
|
- | 191 | return ((val) << AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; |
|
- | 192 | } |
|
- | 193 | ||
- | 194 | #define REG_AXXX_MH_MMU_VA_RANGE 0x00000041 |
|
- | 195 | ||
- | 196 | #define REG_AXXX_MH_MMU_PT_BASE 0x00000042 |
|
- | 197 | ||
- | 198 | #define REG_AXXX_MH_MMU_PAGE_FAULT 0x00000043 |
|
- | 199 | ||
- | 200 | #define REG_AXXX_MH_MMU_TRAN_ERROR 0x00000044 |
|
- | 201 | ||
- | 202 | #define REG_AXXX_MH_MMU_INVALIDATE 0x00000045 |
|
- | 203 | ||
- | 204 | #define REG_AXXX_MH_MMU_MPU_BASE 0x00000046 |
|
- | 205 | ||
- | 206 | #define REG_AXXX_MH_MMU_MPU_END 0x00000047 |
|
- | 207 | ||
- | 208 | #define REG_AXXX_CP_RB_BASE 0x000001c0 |
|
- | 209 | ||
- | 210 | #define REG_AXXX_CP_RB_CNTL 0x000001c1 |
|
- | 211 | #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f |
|
- | 212 | #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 |
|
- | 213 | static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) |
|
- | 214 | { |
|
- | 215 | return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; |
|
- | 216 | } |
|
- | 217 | #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 |
|
- | 218 | #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 |
|
- | 219 | static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) |
|
- | 220 | { |
|
- | 221 | return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; |
|
- | 222 | } |
|
- | 223 | #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 |
|
- | 224 | #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 |
|
- | 225 | static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) |
|
- | 226 | { |
|
- | 227 | return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; |
|
- | 228 | } |
|
- | 229 | #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 |
|
- | 230 | #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 |
|
- | 231 | #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 |
|
- | 232 | ||
- | 233 | #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 |
|
- | 234 | #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 |
|
- | 235 | #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 |
|
- | 236 | static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) |
|
- | 237 | { |
|
- | 238 | return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; |
|
- | 239 | } |
|
- | 240 | #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc |
|
- | 241 | #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 |
|
- | 242 | static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) |
|
- | 243 | { |
|
- | 244 | return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; |
|
- | 245 | } |
|
- | 246 | ||
- | 247 | #define REG_AXXX_CP_RB_RPTR 0x000001c4 |
|
- | 248 | ||
- | 249 | #define REG_AXXX_CP_RB_WPTR 0x000001c5 |
|
- | 250 | ||
- | 251 | #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 |
|
- | 252 | ||
- | 253 | #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 |
|
- | 254 | ||
- | 255 | #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 |
|
- | 256 | ||
- | 257 | #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 |
|
- | 258 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f |
|
- | 259 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 |
|
- | 260 | static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) |
|
- | 261 | { |
|
- | 262 | return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; |
|
- | 263 | } |
|
- | 264 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 |
|
- | 265 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 |
|
- | 266 | static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) |
|
- | 267 | { |
|
- | 268 | return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; |
|
- | 269 | } |
|
- | 270 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 |
|
- | 271 | #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 |
|
- | 272 | static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) |
|
- | 273 | { |
|
- | 274 | return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; |
|
- | 275 | } |
|
- | 276 | ||
- | 277 | #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 |
|
- | 278 | ||
- | 279 | #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 |
|
- | 280 | #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f |
|
- | 281 | #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 |
|
- | 282 | static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) |
|
- | 283 | { |
|
- | 284 | return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; |
|
- | 285 | } |
|
- | 286 | #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 |
|
- | 287 | #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 |
|
- | 288 | static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) |
|
- | 289 | { |
|
- | 290 | return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; |
|
- | 291 | } |
|
- | 292 | #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 |
|
- | 293 | #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 |
|
- | 294 | static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) |
|
- | 295 | { |
|
- | 296 | return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; |
|
- | 297 | } |
|
- | 298 | ||
- | 299 | #define REG_AXXX_CP_STQ_AVAIL 0x000001d8 |
|
- | 300 | #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f |
|
- | 301 | #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 |
|
- | 302 | static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) |
|
- | 303 | { |
|
- | 304 | return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; |
|
- | 305 | } |
|
- | 306 | ||
- | 307 | #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 |
|
- | 308 | #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f |
|
- | 309 | #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 |
|
- | 310 | static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) |
|
- | 311 | { |
|
- | 312 | return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; |
|
- | 313 | } |
|
- | 314 | ||
- | 315 | #define REG_AXXX_SCRATCH_UMSK 0x000001dc |
|
- | 316 | #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff |
|
- | 317 | #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 |
|
- | 318 | static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) |
|
- | 319 | { |
|
- | 320 | return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; |
|
- | 321 | } |
|
- | 322 | #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 |
|
- | 323 | #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 |
|
- | 324 | static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) |
|
- | 325 | { |
|
- | 326 | return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; |
|
- | 327 | } |
|
- | 328 | ||
- | 329 | #define REG_AXXX_SCRATCH_ADDR 0x000001dd |
|
- | 330 | ||
- | 331 | #define REG_AXXX_CP_ME_RDADDR 0x000001ea |
|
- | 332 | ||
- | 333 | #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec |
|
- | 334 | ||
- | 335 | #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed |
|
- | 336 | ||
- | 337 | #define REG_AXXX_CP_INT_CNTL 0x000001f2 |
|
- | 338 | ||
- | 339 | #define REG_AXXX_CP_INT_STATUS 0x000001f3 |
|
- | 340 | ||
- | 341 | #define REG_AXXX_CP_INT_ACK 0x000001f4 |
|
- | 342 | ||
- | 343 | #define REG_AXXX_CP_ME_CNTL 0x000001f6 |
|
- | 344 | ||
- | 345 | #define REG_AXXX_CP_ME_STATUS 0x000001f7 |
|
- | 346 | ||
- | 347 | #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 |
|
- | 348 | ||
- | 349 | #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 |
|
- | 350 | ||
- | 351 | #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa |
|
- | 352 | ||
- | 353 | #define REG_AXXX_CP_DEBUG 0x000001fc |
|
- | 354 | #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 |
|
- | 355 | #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 |
|
- | 356 | #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 |
|
- | 357 | #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 |
|
- | 358 | #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 |
|
- | 359 | #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 |
|
- | 360 | #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 |
|
- | 361 | #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 |
|
- | 362 | ||
- | 363 | #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd |
|
- | 364 | #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f |
|
- | 365 | #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 |
|
- | 366 | static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) |
|
- | 367 | { |
|
- | 368 | return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; |
|
- | 369 | } |
|
- | 370 | #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 |
|
- | 371 | #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 |
|
- | 372 | static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) |
|
- | 373 | { |
|
- | 374 | return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; |
|
- | 375 | } |
|
- | 376 | ||
- | 377 | #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe |
|
- | 378 | #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f |
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- | 379 | #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 |
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- | 380 | static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) |
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- | 381 | { |
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- | 382 | return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; |
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- | 383 | } |
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- | 384 | #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 |
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- | 385 | #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 |
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- | 386 | static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) |
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- | 387 | { |
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- | 388 | return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; |
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- | 389 | } |
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- | 390 | ||
- | 391 | #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff |
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- | 392 | #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f |
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- | 393 | #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 |
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- | 394 | static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) |
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- | 395 | { |
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- | 396 | return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; |
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- | 397 | } |
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- | 398 | #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 |
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- | 399 | #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 |
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- | 400 | static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) |
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- | 401 | { |
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- | 402 | return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; |
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- | 403 | } |
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- | 404 | ||
- | 405 | #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 |
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- | 406 | ||
- | 407 | #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 |
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- | 408 | ||
- | 409 | #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a |
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- | 410 | ||
- | 411 | #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b |
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- | 412 | ||
- | 413 | #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c |
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- | 414 | ||
- | 415 | #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d |
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- | 416 | ||
- | 417 | #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e |
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- | 418 | ||
- | 419 | #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f |
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- | 420 | ||
- | 421 | #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a |
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- | 422 | ||
- | 423 | #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b |
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- | 424 | ||
- | 425 | #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c |
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- | 426 | ||
- | 427 | #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d |
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- | 428 | ||
- | 429 | #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e |
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Line 115... | Line 430... | ||
115 | 430 |