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Rev 4358 Rev 4401
Line 87... Line 87...
87 
				A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
 87 
				A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
88 
				A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
 88 
				A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
89 
		if (bin_w || (i >= nr_bufs)) {
 89 
		if (bin_w || (i >= nr_bufs)) {
90 
			OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
 90 
			OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
91 
		} else {
 91 
		} else {
92 
			OUT_RELOCS(ring, res->bo, 0, 0, -1);
 92 
			OUT_RELOCW(ring, res->bo, 0, 0, -1);
93 
		}
 93 
		}
Line 94... Line 94...
94 
 
 94 
 
95 
		OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
 95 
		OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
96 
		OUT_RING(ring, A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(format));
 96 
		OUT_RING(ring, A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(format));
Line 114... Line 114...
114 
 
 114 
 
115 
	OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
 115 
	OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
116 
	OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 116 
	OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
117 
			A3XX_RB_COPY_CONTROL_MODE(mode) |
 117 
			A3XX_RB_COPY_CONTROL_MODE(mode) |
118 
			A3XX_RB_COPY_CONTROL_GMEM_BASE(base));
 118 
			A3XX_RB_COPY_CONTROL_GMEM_BASE(base));
119 
	OUT_RELOCS(ring, rsc->bo, 0, 0, -1);    /* RB_COPY_DEST_BASE */
 119 
	OUT_RELOCW(ring, rsc->bo, 0, 0, -1);    /* RB_COPY_DEST_BASE */
120 
	OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(rsc->pitch * rsc->cpp));
 120 
	OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(rsc->pitch * rsc->cpp));
121 
	OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
 121 
	OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
122 
			A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(psurf->format)) |
 122 
			A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(psurf->format)) |
123 
			A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 123 
			A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
Line 166... Line 166...
166 
	OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 166 
	OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
Line 167... Line 167...
167 
 
 167 
 
168 
	OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 168 
	OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
Line -... Line 169...
- 
 
 169 
	OUT_RING(ring, 0x00000000);   /* GRAS_CL_CLIP_CNTL */
- 
 
 170 
 
- 
 
 171 
	OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
- 
 
 172 
	OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
- 
 
 173 
	OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
- 
 
 174 
	OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
- 
 
 175 
	OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
- 
 
 176 
	OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
169 
	OUT_RING(ring, 0x00000000);   /* GRAS_CL_CLIP_CNTL */
 177 
	OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
170 
 
 178 
 
171 
	OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 179 
	OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
Line 172... Line 180...
172 
	OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 180 
	OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
Line 204... Line 212...
204 
	fd3_emit_vertex_bufs(ring, &ctx->solid_prog, (struct fd3_vertex_buf[]) {
 212 
	fd3_emit_vertex_bufs(ring, &ctx->solid_prog, (struct fd3_vertex_buf[]) {
205 
			{ .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
 213 
			{ .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
206 
		}, 1);
 214 
		}, 1);
Line 207... Line 215...
207 
 
 215 
 
208 
	if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 216 
	if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
- 
 
 217 
		uint32_t base = 0;
- 
 
 218 
		if (pfb->cbufs[0]) {
209 
		uint32_t base = depth_base(&ctx->gmem) *
 219 
			struct fd_resource *rsc =
- 
 
 220 
					fd_resource(pfb->cbufs[0]->texture);
- 
 
 221 
			base = depth_base(&ctx->gmem) * rsc->cpp;
210 
				fd_resource(pfb->cbufs[0]->texture)->cpp;
 222 
		}
211 
		emit_gmem2mem_surf(ring, RB_COPY_DEPTH_STENCIL, base, pfb->zsbuf);
 223 
		emit_gmem2mem_surf(ring, RB_COPY_DEPTH_STENCIL, base, pfb->zsbuf);
Line 212... Line 224...
212 
	}
 224 
	}
213 
 
 225 
 
Line 258... Line 270...
258 
	x1 = ((float)xoff + bin_w) / ((float)pfb->width);
 270 
	x1 = ((float)xoff + bin_w) / ((float)pfb->width);
259 
	y0 = ((float)yoff) / ((float)pfb->height);
 271 
	y0 = ((float)yoff) / ((float)pfb->height);
260 
	y1 = ((float)yoff + bin_h) / ((float)pfb->height);
 272 
	y1 = ((float)yoff + bin_h) / ((float)pfb->height);
Line 261... Line 273...
261 
 
 273 
 
262 
	OUT_PKT3(ring, CP_MEM_WRITE, 5);
 274 
	OUT_PKT3(ring, CP_MEM_WRITE, 5);
263 
	OUT_RELOC(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0);
 275 
	OUT_RELOC(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
264 
	OUT_RING(ring, fui(x0));
 276 
	OUT_RING(ring, fui(x0));
265 
	OUT_RING(ring, fui(y0));
 277 
	OUT_RING(ring, fui(y0));
266 
	OUT_RING(ring, fui(x1));
 278 
	OUT_RING(ring, fui(x1));
Line 381... Line 393...
381 
	OUT_PKT0(ring, REG_A3XX_VSC_PIPE(0), 3);
 393 
	OUT_PKT0(ring, REG_A3XX_VSC_PIPE(0), 3);
382 
	OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(0) |
 394 
	OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(0) |
383 
			A3XX_VSC_PIPE_CONFIG_Y(0) |
 395 
			A3XX_VSC_PIPE_CONFIG_Y(0) |
384 
			A3XX_VSC_PIPE_CONFIG_W(gmem->nbins_x) |
 396 
			A3XX_VSC_PIPE_CONFIG_W(gmem->nbins_x) |
385 
			A3XX_VSC_PIPE_CONFIG_H(gmem->nbins_y));
 397 
			A3XX_VSC_PIPE_CONFIG_H(gmem->nbins_y));
386 
	OUT_RELOC(ring, bo, 0, 0);              /* VSC_PIPE[0].DATA_ADDRESS */
 398 
	OUT_RELOC(ring, bo, 0, 0, 0);           /* VSC_PIPE[0].DATA_ADDRESS */
387 
	OUT_RING(ring, fd_bo_size(bo) - 32);    /* VSC_PIPE[0].DATA_LENGTH */
 399 
	OUT_RING(ring, fd_bo_size(bo) - 32);    /* VSC_PIPE[0].DATA_LENGTH */
Line 388... Line 400...
388 
 
 400 
 
389 
	for (i = 1; i < 8; i++) {
 401 
	for (i = 1; i < 8; i++) {
390 
		OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
 402 
		OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
Line 400... Line 412...
400 
/* for rendering directly to system memory: */
 412 
/* for rendering directly to system memory: */
401 
static void
 413 
static void
402 
fd3_emit_sysmem_prep(struct fd_context *ctx)
 414 
fd3_emit_sysmem_prep(struct fd_context *ctx)
403 
{
 415 
{
404 
	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 416 
	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
405 
	struct fd_resource *rsc = fd_resource(pfb->cbufs[0]->texture);
 - 
 
406 
	struct fd_ringbuffer *ring = ctx->ring;
 417 
	struct fd_ringbuffer *ring = ctx->ring;
- 
 
 418 
	uint32_t pitch = 0;
- 
 
 419 
 
- 
 
 420 
	if (pfb->cbufs[0])
- 
 
 421 
		pitch = fd_resource(pfb->cbufs[0]->texture)->pitch;
Line 407... Line 422...
407 
 
 422 
 
Line 408... Line 423...
408 
	fd3_emit_restore(ctx);
 423 
	fd3_emit_restore(ctx);
409 
 
 424 
 
410 
	OUT_PKT0(ring, REG_A3XX_RB_WINDOW_SIZE, 1);
 425 
	OUT_PKT0(ring, REG_A3XX_RB_WINDOW_SIZE, 1);
Line 411... Line 426...
411 
	OUT_RING(ring, A3XX_RB_WINDOW_SIZE_WIDTH(pfb->width) |
 426 
	OUT_RING(ring, A3XX_RB_WINDOW_SIZE_WIDTH(pfb->width) |
Line 412... Line 427...
412 
			A3XX_RB_WINDOW_SIZE_HEIGHT(pfb->height));
 427 
			A3XX_RB_WINDOW_SIZE_HEIGHT(pfb->height));
413 
 
 428 
 
Line 414... Line 429...
414 
	emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
 429 
	emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
415 
 
 430 
 
416 
	fd3_emit_rbrc_tile_state(ring,
 431 
	fd3_emit_rbrc_tile_state(ring,
417 
			A3XX_RB_RENDER_CONTROL_BIN_WIDTH(rsc->pitch));
 432 
			A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));