WebSVN – Kolibri OS – Diff – /contrib/sdk/sources/Mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.c



			CP_LOAD_STATE_0_STATE_BLOCK(sb) |
			CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
	if (prsc) {
		struct fd_bo *bo = fd_resource(prsc)->bo;
		OUT_RELOC(ring, bo, offset,
				CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
	} else {
		OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
				CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
		dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
	}

	OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
			CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
	for (i = 0; i < tex->num_textures; i++) {
		struct fd3_pipe_sampler_view *view =
				fd3_pipe_sampler_view(tex->textures[i]);
		OUT_RELOC(ring, view->tex_resource->bo, 0, 0, 0);
		/* I think each entry is a ptr to mipmap level.. for now, just
		 * pad w/ null's until I get around to actually implementing
		 * mipmap support..
		 */
		for (j = 1; j < BASETABLE_SZ; j++) {

			CP_LOAD_STATE_0_NUM_UNIT(1));
	OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
			CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
	OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(psurf->format)) |
			0x40000000 | // XXX
			fd3_tex_swiz(psurf->format,  PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
					PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
	OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
			A3XX_TEX_CONST_1_WIDTH(psurf->width) |
			A3XX_TEX_CONST_1_HEIGHT(psurf->height));
	OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(rsc->pitch * rsc->cpp) |
			A3XX_TEX_CONST_2_INDX(0));
	OUT_RING(ring, 0x00000000);

			CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
			CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
			CP_LOAD_STATE_0_NUM_UNIT(1));
	OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
			CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
	OUT_RELOC(ring, rsc->bo, 0, 0, 0);
}

 
void
fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,

		OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
				A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vbufs[i].stride) |
				COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
				A3XX_VFD_FETCH_INSTR_0_INDEXCODE(i) |
				A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
		OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 0, 0);

 
		OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(i), 1);
		OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
				A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |

	OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
	OUT_RING(ring, 0x00007fff);

 
	OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_CTRL_REG, 3);
	OUT_RING(ring, 0x08000001);                  /* SP_VS_PVT_MEM_CTRL_REG */
	OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */

	OUT_RING(ring, 0x00000000);                  /* SP_VS_PVT_MEM_SIZE_REG */
 
	OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_CTRL_REG, 3);
	OUT_RING(ring, 0x08000001);                  /* SP_FS_PVT_MEM_CTRL_REG */

	OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
	OUT_RING(ring, 0x00000000);                  /* SP_FS_PVT_MEM_SIZE_REG */

	OUT_RING(ring, 0x00000003);        /* UNKNOWN_0EE0 */

 
	OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);

	OUT_RING(ring, 0x00000001);        /* UNKNOWN_0C3D */
 

	OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
	OUT_RING(ring, 0x00000000);        /* HLSQ_PERFCOUNTER0_SELECT */
 
	OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);

 
	OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 1);

	OUT_RING(ring, 0x00000001);        /* UCHE_CACHE_MODE_CONTROL_REG */
 

	OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
	OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */

 

Subversion Repositories Kolibri OS

(root)/contrib/sdk/sources/Mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.c – Rev 4358 → 4401

Rev 4358		Rev 4401
Line 79...		Line 79...
79	CP_LOAD_STATE_0_STATE_BLOCK(sb) \|	79	CP_LOAD_STATE_0_STATE_BLOCK(sb) \|
80	CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));	80	CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
81	if (prsc) {	81	if (prsc) {
82	struct fd_bo *bo = fd_resource(prsc)->bo;	82	struct fd_bo *bo = fd_resource(prsc)->bo;
83	OUT_RELOC(ring, bo, offset,	83	OUT_RELOC(ring, bo, offset,
84	CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));	84	CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
85	} else {	85	} else {
86	OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) \|	86	OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) \|
87	CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));	87	CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
88	dwords = (uint32_t )&((uint8_t )dwords)[offset];	88	dwords = (uint32_t )&((uint8_t )dwords)[offset];
89	}	89	}
Line 210...		Line 210...
210	OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) \|	210	OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) \|
211	CP_LOAD_STATE_1_EXT_SRC_ADDR(0));	211	CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
212	for (i = 0; i < tex->num_textures; i++) {	212	for (i = 0; i < tex->num_textures; i++) {
213	struct fd3_pipe_sampler_view *view =	213	struct fd3_pipe_sampler_view *view =
214	fd3_pipe_sampler_view(tex->textures[i]);	214	fd3_pipe_sampler_view(tex->textures[i]);
215	OUT_RELOC(ring, view->tex_resource->bo, 0, 0);	215	OUT_RELOC(ring, view->tex_resource->bo, 0, 0, 0);
216	/* I think each entry is a ptr to mipmap level.. for now, just	216	/* I think each entry is a ptr to mipmap level.. for now, just
217	* pad w/ null's until I get around to actually implementing	217	* pad w/ null's until I get around to actually implementing
218	* mipmap support..	218	* mipmap support..
219	*/	219	*/
220	for (j = 1; j < BASETABLE_SZ; j++) {	220	for (j = 1; j < BASETABLE_SZ; j++) {
Line 277...		Line 277...
277	CP_LOAD_STATE_0_NUM_UNIT(1));	277	CP_LOAD_STATE_0_NUM_UNIT(1));
278	OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) \|	278	OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) \|
279	CP_LOAD_STATE_1_EXT_SRC_ADDR(0));	279	CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
280	OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(psurf->format)) \|	280	OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(psurf->format)) \|
281	0x40000000 \| // XXX	281	0x40000000 \| // XXX
282	fd3_tex_swiz(psurf->format, PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_GREEN,	282	fd3_tex_swiz(psurf->format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
283	PIPE_SWIZZLE_RED, PIPE_SWIZZLE_ALPHA));	283	PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
284	OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(fd3_pipe2fetchsize(psurf->format)) \|	284	OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) \|
285	A3XX_TEX_CONST_1_WIDTH(psurf->width) \|	285	A3XX_TEX_CONST_1_WIDTH(psurf->width) \|
286	A3XX_TEX_CONST_1_HEIGHT(psurf->height));	286	A3XX_TEX_CONST_1_HEIGHT(psurf->height));
287	OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(rsc->pitch * rsc->cpp) \|	287	OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(rsc->pitch * rsc->cpp) \|
288	A3XX_TEX_CONST_2_INDX(0));	288	A3XX_TEX_CONST_2_INDX(0));
289	OUT_RING(ring, 0x00000000);	289	OUT_RING(ring, 0x00000000);
Line 294...		Line 294...
294	CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) \|	294	CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) \|
295	CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) \|	295	CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) \|
296	CP_LOAD_STATE_0_NUM_UNIT(1));	296	CP_LOAD_STATE_0_NUM_UNIT(1));
297	OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) \|	297	OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) \|
298	CP_LOAD_STATE_1_EXT_SRC_ADDR(0));	298	CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
299	OUT_RELOC(ring, rsc->bo, 0, 0);	299	OUT_RELOC(ring, rsc->bo, 0, 0, 0);
300	}	300	}
Line 301...		Line 301...
301		301
302	void	302	void
303	fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,	303	fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,
Line 320...		Line 320...
320	OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) \|	320	OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) \|
321	A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vbufs[i].stride) \|	321	A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vbufs[i].stride) \|
322	COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) \|	322	COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) \|
323	A3XX_VFD_FETCH_INSTR_0_INDEXCODE(i) \|	323	A3XX_VFD_FETCH_INSTR_0_INDEXCODE(i) \|
324	A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));	324	A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
325	OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 0);	325	OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 0, 0);
Line 326...		Line 326...
326		326
327	OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(i), 1);	327	OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(i), 1);
328	OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL \|	328	OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL \|
329	A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) \|	329	A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) \|
Line 479...		Line 479...
479	OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);	479	OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
480	OUT_RING(ring, 0x00007fff);	480	OUT_RING(ring, 0x00007fff);
Line 481...		Line 481...
481		481
482	OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_CTRL_REG, 3);	482	OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_CTRL_REG, 3);
483	OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */	483	OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
484	OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0, 0); /* SP_VS_PVT_MEM_ADDR_REG */	484	OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
Line 485...		Line 485...
485	OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */	485	OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
486		486
487	OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_CTRL_REG, 3);	487	OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_CTRL_REG, 3);
488	OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */	488	OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
Line 489...		Line 489...
489	OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0, 0); /* SP_FS_PVT_MEM_ADDR_REG */	489	OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
490	OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */	490	OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
Line 534...		Line 534...
534	OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */	534	OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
Line 535...		Line 535...
535		535
536	OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);	536	OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
Line 537...		Line 537...
537	OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */	537	OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
538		538
Line 539...		Line 539...
539	OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E00, 1);	539	OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
540	OUT_RING(ring, 0x00000000); /* UNKNOWN_0E00 */	540	OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
541		541
542	OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);	542	OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
Line 547...		Line 547...
547		547
548	OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 1);	548	OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 1);
Line 549...		Line 549...
549	OUT_RING(ring, 0x00000001); /* UCHE_CACHE_MODE_CONTROL_REG */	549	OUT_RING(ring, 0x00000001); /* UCHE_CACHE_MODE_CONTROL_REG */
550		550
Line 551...		Line 551...
551	OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);	551	OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
552	OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0); /* VSC_SIZE_ADDRESS */	552	OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
Line 553...		Line 553...
553		553