WebSVN – Kolibri OS – Diff – /contrib/sdk/sources/Mesa/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c

 	if (reg->flags & IR3_REG_HALF)
 		num += MAX_REG;
 	return num;
+}
+static void regmask_set(regmask_t regmask, struct ir3_register *reg,
-static void regmask_set(regmask_t regmask, struct ir3_register *reg)
+		unsigned wrmask)
+{
+	unsigned i;
+	for (i = 0; i < 4; i++) {
-{
+		if (wrmask & (1 << i)) {
-	unsigned idx = regmask_idx(reg);
+			unsigned idx = regmask_idx(reg) + i;
-	regmask[idx / 8] |= 1 << (idx % 8);
+			regmask[idx / 8] |= 1 << (idx % 8);
+		}
+	}
+}
 static unsigned regmask_get(regmask_t regmask, struct ir3_register *reg)
+{
 	/* last input dst (for setting (ei) flag): */
 	struct ir3_register *last_input;
 	unsigned next_inloc;
+	unsigned num_internal_temps;
-	unsigned num_internal_temps;
+	struct tgsi_src_register internal_temps[6];
 	/* track registers which need to synchronize w/ "complex alu" cat3
 	 * instruction pipeline:
 	/* used when dst is same as one of the src, to avoid overwriting a
 	 * src element before the remaining scalar instructions that make
 	 * up the vector operation
 	 */
 	struct tgsi_dst_register tmp_dst;
-	struct tgsi_src_register tmp_src;
+	struct tgsi_src_register *tmp_src;
 };
+static void vectorize(struct fd3_compile_context *ctx,
+		struct ir3_instruction *instr, struct tgsi_dst_register *dst,
+		int nsrcs, ...);
+static void create_mov(struct fd3_compile_context *ctx,
+		struct tgsi_dst_register *dst, struct tgsi_src_register *src);
 static unsigned
 compile_init(struct fd3_compile_context *ctx, struct fd3_shader_stateobj *so,
 		const struct tgsi_token *tokens)
+{
 	tgsi_scan_shader(tokens, &ctx->info);
 	/* Immediates go after constants: */
 	ctx->base_reg[TGSI_FILE_CONSTANT]  = 0;
 	ctx->base_reg[TGSI_FILE_IMMEDIATE] =
-			ctx->info.file_count[TGSI_FILE_CONSTANT];
+			ctx->info.file_max[TGSI_FILE_CONSTANT] + 1;
 	/* Temporaries after outputs after inputs: */
 	ctx->base_reg[TGSI_FILE_INPUT]     = 0;
 	ctx->base_reg[TGSI_FILE_OUTPUT]    =
-			ctx->info.file_count[TGSI_FILE_INPUT];
+			ctx->info.file_max[TGSI_FILE_INPUT] + 1;
 	ctx->base_reg[TGSI_FILE_TEMPORARY] =
-			ctx->info.file_count[TGSI_FILE_INPUT] +
+			ctx->info.file_max[TGSI_FILE_INPUT] + 1 +
-			ctx->info.file_count[TGSI_FILE_OUTPUT];
+			ctx->info.file_max[TGSI_FILE_OUTPUT] + 1;
 	so->first_immediate = ctx->base_reg[TGSI_FILE_IMMEDIATE];
-	ctx->immediate_idx = 4 * (ctx->info.file_count[TGSI_FILE_CONSTANT] +
+	ctx->immediate_idx = 4 * (ctx->info.file_max[TGSI_FILE_CONSTANT] + 1 +
-			ctx->info.file_count[TGSI_FILE_IMMEDIATE]);
+			ctx->info.file_max[TGSI_FILE_IMMEDIATE] + 1);
 	return ret;
+}
+static void
+compile_error(struct fd3_compile_context *ctx, const char *format, ...)
+{
+	va_list ap;
+	va_start(ap, format);
+	_debug_vprintf(format, ap);
+	va_end(ap);
+	tgsi_dump(ctx->tokens, 0);
+	assert(0);
+}
+#define compile_assert(ctx, cond) do { \
+		if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
+	} while (0)
 static void
 compile_free(struct fd3_compile_context *ctx)
+{
 	opc_t opc;
 	opc_t hopc;    /* opc to use for half_precision mode, if different */
 	unsigned arg;
 };
+static unsigned
+src_flags(struct fd3_compile_context *ctx, struct ir3_register *reg)
+{
+	unsigned flags = 0;
+	if (regmask_get(ctx->needs_ss, reg)) {
+		flags |= IR3_INSTR_SS;
+		memset(ctx->needs_ss, 0, sizeof(ctx->needs_ss));
+	}
+	if (regmask_get(ctx->needs_sy, reg)) {
+		flags |= IR3_INSTR_SY;
+		memset(ctx->needs_sy, 0, sizeof(ctx->needs_sy));
+	}
+	return flags;
+}
 static struct ir3_register *
 add_dst_reg(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
 		const struct tgsi_dst_register *dst, unsigned chan)
+{
 	case TGSI_FILE_OUTPUT:
 	case TGSI_FILE_TEMPORARY:
 		num = dst->Index + ctx->base_reg[dst->File];
 		break;
 	default:
-		DBG("unsupported dst register file: %s",
+		compile_error(ctx, "unsupported dst register file: %s\n",
 			tgsi_file_name(dst->File));
-		assert(0);
 		break;
+	}
 	if (ctx->so->half_precision)
 		 */
 	case TGSI_FILE_CONSTANT:
 		flags |= IR3_REG_CONST;
 		num = src->Index + ctx->base_reg[src->File];
 		break;
+	case TGSI_FILE_OUTPUT:
+		/* NOTE: we should only end up w/ OUTPUT file for things like
+		 * clamp()'ing saturated dst instructions
+		 */
 	case TGSI_FILE_INPUT:
 	case TGSI_FILE_TEMPORARY:
 		num = src->Index + ctx->base_reg[src->File];
 		break;
 	default:
-		DBG("unsupported src register file: %s",
+		compile_error(ctx, "unsupported src register file: %s\n",
 			tgsi_file_name(src->File));
-		assert(0);
 		break;
+	}
 	if (src->Absolute)
 	if (ctx->so->half_precision)
 		flags |= IR3_REG_HALF;
-	reg = ir3_reg_create(instr, regid(num, chan), flags);
+	reg = ir3_reg_create(instr, regid(num, chan), flags);
-	if (regmask_get(ctx->needs_ss, reg)) {
-		instr->flags |= IR3_INSTR_SS;
-		memset(ctx->needs_ss, 0, sizeof(ctx->needs_ss));
-	}
-	if (regmask_get(ctx->needs_sy, reg)) {
-		instr->flags |= IR3_INSTR_SY;
 		memset(ctx->needs_sy, 0, sizeof(ctx->needs_sy));
 	instr->flags |= src_flags(ctx, reg);
+}
 /* Get internal-temp src/dst to use for a sequence of instructions
  * generated by a single TGSI op.
  */
-static void
+static struct tgsi_src_register *
 get_internal_temp(struct fd3_compile_context *ctx,
-		struct tgsi_dst_register *tmp_dst,
-		struct tgsi_src_register *tmp_src)
+		struct tgsi_dst_register *tmp_dst)
+{
 	struct tgsi_src_register *tmp_src;
 	int n;
 	tmp_dst->File      = TGSI_FILE_TEMPORARY;
 	tmp_dst->WriteMask = TGSI_WRITEMASK_XYZW;
 	tmp_dst->Indirect  = 0;
 	tmp_dst->Dimension = 0;
+	/* assign next temporary: */
+	n = ctx->num_internal_temps++;
-	/* assign next temporary: */
+	compile_assert(ctx, n < ARRAY_SIZE(ctx->internal_temps));
+	tmp_src = &ctx->internal_temps[n];
-	n = ctx->num_internal_temps++;
+	tmp_dst->Index = ctx->info.file_max[TGSI_FILE_TEMPORARY] + n + 1;
-	tmp_dst->Index = ctx->info.file_count[TGSI_FILE_TEMPORARY] + n;
+	src_from_dst(tmp_src, tmp_dst);
-	src_from_dst(tmp_src, tmp_dst);
+	return tmp_src;
+}
-/* same as get_internal_temp, but w/ src.xxxx (for instructions that
- * replicate their results)
+/* same as get_internal_temp, but w/ src.xxxx (for instructions that
+ * replicate their results)
  */
-static void
+static struct tgsi_src_register *
 get_internal_temp_repl(struct fd3_compile_context *ctx,
+		struct tgsi_dst_register *tmp_dst)
+{
+	struct tgsi_src_register *tmp_src =
+			get_internal_temp(ctx, tmp_dst);
+	tmp_src->SwizzleX = tmp_src->SwizzleY =
+		tmp_src->SwizzleZ = tmp_src->SwizzleW = TGSI_SWIZZLE_X;
+	return tmp_src;
+}
+static inline bool
+is_const(struct tgsi_src_register *src)
+{
+	return (src->File == TGSI_FILE_CONSTANT) ||
+			(src->File == TGSI_FILE_IMMEDIATE);
+}
+static type_t
+get_ftype(struct fd3_compile_context *ctx)
+{
+	return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
+}
+static type_t
+get_utype(struct fd3_compile_context *ctx)
+{
+	return ctx->so->half_precision ? TYPE_U16 : TYPE_U32;
+}
+static unsigned
+src_swiz(struct tgsi_src_register *src, int chan)
+{
+	switch (chan) {
+	case 0: return src->SwizzleX;
+	case 1: return src->SwizzleY;
+	case 2: return src->SwizzleZ;
+	case 3: return src->SwizzleW;
+	}
+	assert(0);
+	return 0;
+}
+/* for instructions that cannot take a const register as src, if needed
+ * generate a move to temporary gpr:
+ */
+static struct tgsi_src_register *
+get_unconst(struct fd3_compile_context *ctx, struct tgsi_src_register *src)
+{
+	struct tgsi_dst_register tmp_dst;
+	struct tgsi_src_register *tmp_src;
+	compile_assert(ctx, is_const(src));
 		struct tgsi_dst_register *tmp_dst,
-		struct tgsi_src_register *tmp_src)
+	tmp_src = get_internal_temp(ctx, &tmp_dst);
-	get_internal_temp(ctx, tmp_dst, tmp_src);
+	create_mov(ctx, &tmp_dst, src);
 	reg->SwizzleY  = swiz2tgsi[swiz];
 	reg->SwizzleZ  = swiz2tgsi[swiz];
 	reg->SwizzleW  = swiz2tgsi[swiz];
+}
-static type_t
-get_type(struct fd3_compile_context *ctx)
-{
-	return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
-}
-static unsigned
-src_swiz(struct tgsi_src_register *src, int chan)
-{
-	switch (chan) {
-	case 0: return src->SwizzleX;
-	case 1: return src->SwizzleY;
-	case 2: return src->SwizzleZ;
-	case 3: return src->SwizzleW;
-	}
-	assert(0);
-	return 0;
-}
 static void
 create_mov(struct fd3_compile_context *ctx, struct tgsi_dst_register *dst,
 		struct tgsi_src_register *src)
 {
-	type_t type_mov = get_type(ctx);
+	type_t type_mov = get_ftype(ctx);
 	unsigned i;
 	for (i = 0; i < 4; i++) {
 			add_src_reg(ctx, instr, src, src_swiz(src, i));
 		} else {
 			ir3_instr_create(ctx->ir, 0, OPC_NOP);
+		}
+	}
+}
+static void
+create_clamp(struct fd3_compile_context *ctx, struct tgsi_dst_register *dst,
+		struct tgsi_src_register *minval, struct tgsi_src_register *maxval)
+{
+	struct ir3_instruction *instr;
+	struct tgsi_src_register src;
+	src_from_dst(&src, dst);
+	instr = ir3_instr_create(ctx->ir, 2, OPC_MAX_F);
+	vectorize(ctx, instr, dst, 2, &src, 0, minval, 0);
+	instr = ir3_instr_create(ctx->ir, 2, OPC_MIN_F);
+	vectorize(ctx, instr, dst, 2, &src, 0, maxval, 0);
+}
+static void
+create_clamp_imm(struct fd3_compile_context *ctx,
+		struct tgsi_dst_register *dst,
+		uint32_t minval, uint32_t maxval)
+{
+	struct tgsi_src_register minconst, maxconst;
+	get_immediate(ctx, &minconst, minval);
+	get_immediate(ctx, &maxconst, maxval);
 	create_clamp(ctx, dst, &minconst, &maxconst);
+}
 static struct tgsi_dst_register *
 get_dst(struct fd3_compile_context *ctx, struct tgsi_full_instruction *inst)
+{
 	struct tgsi_dst_register *dst = &inst->Dst[0].Register;
 	unsigned i;
 	for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
 		struct tgsi_src_register *src = &inst->Src[i].Register;
 		if ((src->File == dst->File) && (src->Index == dst->Index)) {
-			get_internal_temp(ctx, &ctx->tmp_dst, &ctx->tmp_src);
+			ctx->tmp_src = get_internal_temp(ctx, &ctx->tmp_dst);
 			ctx->tmp_dst.WriteMask = dst->WriteMask;
 			dst = &ctx->tmp_dst;
 			break;
 put_dst(struct fd3_compile_context *ctx, struct tgsi_full_instruction *inst,
 		struct tgsi_dst_register *dst)
+{
 	/* if necessary, add mov back into original dst: */
 	if (dst != &inst->Dst[0].Register) {
-		create_mov(ctx, &inst->Dst[0].Register, &ctx->tmp_src);
+		create_mov(ctx, &inst->Dst[0].Register, ctx->tmp_src);
+	}
+}
 /* helper to generate the necessary repeat and/or additional instructions
 						va_arg(ap, struct tgsi_src_register *);
 				(void)va_arg(ap, unsigned);
 				cur->regs[j+1]->num =
 					regid(cur->regs[j+1]->num >> 2,
 						src_swiz(src, i));
+				cur->flags |= src_flags(ctx, cur->regs[j+1]);
+			}
 			va_end(ap);
+		}
+	}
 /*
  * Handlers for TGSI instructions which do not have a 1:1 mapping to
  * native instructions:
  */
+static inline void
+get_swiz(unsigned *swiz, struct tgsi_src_register *src)
+{
+	swiz[0] = src->SwizzleX;
+	swiz[1] = src->SwizzleY;
+	swiz[2] = src->SwizzleZ;
+	swiz[3] = src->SwizzleW;
+}
 static void
 trans_dotp(const struct instr_translater *t,
 		struct fd3_compile_context *ctx,
 		struct tgsi_full_instruction *inst)
+{
 	struct ir3_instruction *instr;
 	struct tgsi_dst_register tmp_dst;
-	struct tgsi_src_register tmp_src;
+	struct tgsi_src_register *tmp_src;
 	struct tgsi_dst_register *dst  = &inst->Dst[0].Register;
 	struct tgsi_src_register *src0 = &inst->Src[0].Register;
 	struct tgsi_src_register *src1 = &inst->Src[1].Register;
-	unsigned swiz0[] = { src0->SwizzleX, src0->SwizzleY, src0->SwizzleZ, src0->SwizzleW };
+	unsigned swiz0[4];
-	unsigned swiz1[] = { src1->SwizzleX, src1->SwizzleY, src1->SwizzleZ, src1->SwizzleW };
+	unsigned swiz1[4];
 	opc_t opc_mad    = ctx->so->half_precision ? OPC_MAD_F16 : OPC_MAD_F32;
 	unsigned n = t->arg;     /* number of components */
-	unsigned i;
-	get_internal_temp_repl(ctx, &tmp_dst, &tmp_src);
-	/* Blob compiler never seems to use a const in src1 position for
-	 * mad.*, although there does seem (according to disassembler
-	 * hidden in libllvm-a3xx.so) to be a bit to indicate that src1
-	 * is a const.  Not sure if this is a hw bug, or simply that the
-	 * disassembler lies.
-	 */
-	if ((src1->File == TGSI_FILE_IMMEDIATE) ||
-			(src1->File == TGSI_FILE_CONSTANT)) {
+	unsigned i, swapped = 0;
-		/* the mov to tmp unswizzles src1, so now we have tmp.xyzw:
-		 */
-		for (i = 0; i < 4; i++)
-			swiz1[i] = i;
 	tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
+	/* in particular, can't handle const for src1 for cat3/mad:
-		/* the first mul.f will clobber tmp.x, but that is ok
+	 */
+	if (is_const(src1)) {
+		if (!is_const(src0)) {
-		 * because after that point we no longer need tmp.x:
+			struct tgsi_src_register *tmp;
+			tmp = src0;
+			src0 = src1;
+			src1 = tmp;
+			swapped = 1;
-		 */
+		} else {
+			src0 = get_unconst(ctx, src0);
+		}
+	}
 		create_mov(ctx, &tmp_dst, src1);
-		src1 = &tmp_src;
+	get_swiz(swiz0, src0);
 	get_swiz(swiz1, src1);
 		instr = ir3_instr_create(ctx->ir, 3, opc_mad);
 		add_dst_reg(ctx, instr, &tmp_dst, 0);
 		add_src_reg(ctx, instr, src0, swiz0[i]);
 		add_src_reg(ctx, instr, src1, swiz1[i]);
-		add_src_reg(ctx, instr, &tmp_src, 0);
+		add_src_reg(ctx, instr, tmp_src, 0);
+	}
 	/* DPH(a,b) = (a.x * b.x) + (a.y * b.y) + (a.z * b.z) + b.w */
 	if (t->tgsi_opc == TGSI_OPCODE_DPH) {
-		ir3_instr_create(ctx->ir, 0, OPC_NOP);
+		ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 1;
+		instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
+		add_dst_reg(ctx, instr, &tmp_dst, 0);
 		if (swapped)
-		instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
+			add_src_reg(ctx, instr, src0, swiz0[i]);
-		add_dst_reg(ctx, instr, &tmp_dst, 0);
+		else
-		add_src_reg(ctx, instr, src1, swiz1[i]);
+			add_src_reg(ctx, instr, src1, swiz1[i]);
-		add_src_reg(ctx, instr, &tmp_src, 0);
+		add_src_reg(ctx, instr, tmp_src, 0);
-		n++;
-	}
-	ir3_instr_create(ctx->ir, 0, OPC_NOP);
-	/* pad out to multiple of 4 scalar instructions: */
+		n++;
 	for (i = 2 * n; i % 4; i++) {
 		ir3_instr_create(ctx->ir, 0, OPC_NOP);
 	ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 2;
-	create_mov(ctx, dst, &tmp_src);
+	create_mov(ctx, dst, tmp_src);
+}
 /* LRP(a,b,c) = (a * b) + ((1 - a) * c) */
 static void
 trans_lrp(const struct instr_translater *t,
+		struct fd3_compile_context *ctx,
+		struct tgsi_full_instruction *inst)
+{
+	struct ir3_instruction *instr;
+	struct tgsi_dst_register tmp_dst1, tmp_dst2;
-		struct fd3_compile_context *ctx,
+	struct tgsi_src_register *tmp_src1, *tmp_src2;
-		struct tgsi_full_instruction *inst)
+	struct tgsi_src_register tmp_const;
 	struct tgsi_src_register *src0 = &inst->Src[0].Register;
-	struct ir3_instruction *instr;
+	struct tgsi_src_register *src1 = &inst->Src[1].Register;
 	struct tgsi_dst_register tmp_dst1, tmp_dst2;
-	struct tgsi_src_register tmp_src1, tmp_src2;
+	if (is_const(src0) && is_const(src1))
-	struct tgsi_src_register tmp_const;
-	get_internal_temp(ctx, &tmp_dst1, &tmp_src1);
+		src0 = get_unconst(ctx, src0);
 	get_internal_temp(ctx, &tmp_dst2, &tmp_src2);
+	tmp_src1 = get_internal_temp(ctx, &tmp_dst1);
-	get_immediate(ctx, &tmp_const, fui(1.0));
+	tmp_src2 = get_internal_temp(ctx, &tmp_dst2);
 	/* tmp1 = (a * b) */
-	instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
+	get_immediate(ctx, &tmp_const, fui(1.0));
 	vectorize(ctx, instr, &tmp_dst1, 2,
-			&inst->Src[0].Register, 0,
+	/* tmp1 = (a * b) */
-			&inst->Src[1].Register, 0);
+	instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
 	vectorize(ctx, instr, &tmp_dst1, 2, src0, 0, src1, 0);
 	/* tmp2 = (1 - a) */
-	instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
+	/* tmp2 = (1 - a) */
-	vectorize(ctx, instr, &tmp_dst2, 2,
+	instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
-			&tmp_const, 0,
+	vectorize(ctx, instr, &tmp_dst2, 2, &tmp_const, 0,
-			&inst->Src[0].Register, IR3_REG_NEGATE);
+			src0, IR3_REG_NEGATE);
 	/* tmp2 = tmp2 * c */
 	instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
 	vectorize(ctx, instr, &tmp_dst2, 2,
-			&tmp_src2, 0,
+			tmp_src2, 0,
 			&inst->Src[2].Register, 0);
 	/* dst = tmp1 + tmp2 */
 	instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
 	vectorize(ctx, instr, &inst->Dst[0].Register, 2,
-			&tmp_src1, 0,
+			tmp_src1, 0,
-			&tmp_src2, 0);
+			tmp_src2, 0);
+}
 /* FRC(x) = x - FLOOR(x) */
 static void
 trans_frac(const struct instr_translater *t,
 		struct fd3_compile_context *ctx,
 		struct tgsi_full_instruction *inst)
+{
 	struct ir3_instruction *instr;
 	struct tgsi_dst_register tmp_dst;
-	struct tgsi_src_register tmp_src;
+	struct tgsi_src_register *tmp_src;
 		struct tgsi_full_instruction *inst)
+{
 	struct ir3_instruction *instr;
 	struct ir3_register *r;
 	struct tgsi_dst_register tmp_dst;
-	struct tgsi_src_register tmp_src;
+	struct tgsi_src_register *tmp_src;
 	struct tgsi_dst_register *dst  = &inst->Dst[0].Register;
 	struct tgsi_src_register *src0 = &inst->Src[0].Register;
 	struct tgsi_src_register *src1 = &inst->Src[1].Register;
-	get_internal_temp_repl(ctx, &tmp_dst, &tmp_src);
+	tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
 	/* log2 Rtmp, Rsrc0 */
 	ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
 	instr = ir3_instr_create(ctx->ir, 4, OPC_LOG2);
 	r = add_dst_reg(ctx, instr, &tmp_dst, 0);
 	add_src_reg(ctx, instr, src0, src0->SwizzleX);
-	regmask_set(ctx->needs_ss, r);
+	regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_X);
 	/* mul.f Rtmp, Rtmp, Rsrc1 */
 	instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
 	add_dst_reg(ctx, instr, &tmp_dst, 0);
-	add_src_reg(ctx, instr, &tmp_src, 0);
+	add_src_reg(ctx, instr, tmp_src, 0);
 	add_src_reg(ctx, instr, src1, src1->SwizzleX);
 	ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
 	/* exp2 Rdst, Rtmp */
 	instr = ir3_instr_create(ctx->ir, 4, OPC_EXP2);
 	r = add_dst_reg(ctx, instr, &tmp_dst, 0);
-	add_src_reg(ctx, instr, &tmp_src, 0);
+	add_src_reg(ctx, instr, tmp_src, 0);
-	regmask_set(ctx->needs_ss, r);
+	regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_X);
-	create_mov(ctx, dst, &tmp_src);
+	create_mov(ctx, dst, tmp_src);
+}
 /* texture fetch/sample instructions: */
 static void
 trans_samp(const struct instr_translater *t,
 		struct fd3_compile_context *ctx,
 		struct tgsi_full_instruction *inst)
-{
-	struct ir3_register *r;
 	struct ir3_instruction *instr;
-	struct tgsi_dst_register tmp_dst;
+	struct ir3_register *r;
-	struct tgsi_src_register tmp_src;
+	struct ir3_instruction *instr;
 	struct tgsi_src_register *coord = &inst->Src[0].Register;
 	struct tgsi_src_register *samp  = &inst->Src[1].Register;
 				(int8_t[4]){ 0,  1,  3, -1 } :  /* 2D */
 				(int8_t[4]){ 0,  1,  2,  3 };   /* 3D */
 		flags |= IR3_INSTR_P;
 		break;
 	default:
-		assert(0);
+		compile_assert(ctx, 0);
 		break;
+	}
 	if (tex == TGSI_TEXTURE_3D)
 	 * might need to emit some mov instructions to shuffle things
 	 * around:
 	 */
 	for (i = 1; (i < 4) && (order[i] >= 0); i++) {
 		if (src_swiz(coord, i) != (src_swiz(coord, 0) + order[i])) {
+			struct tgsi_dst_register tmp_dst;
+			struct tgsi_src_register *tmp_src;
-			type_t type_mov = get_type(ctx);
+			type_t type_mov = get_ftype(ctx);
 			/* need to move things around: */
-			get_internal_temp(ctx, &tmp_dst, &tmp_src);
+			tmp_src = get_internal_temp(ctx, &tmp_dst);
 			for (j = 0; (j < 4) && (order[j] >= 0); j++) {
 				instr = ir3_instr_create(ctx->ir, 1, 0);
 				instr->cat1.src_type = type_mov;
 				instr->cat1.dst_type = type_mov;
 				add_dst_reg(ctx, instr, &tmp_dst, j);
 				add_src_reg(ctx, instr, coord,
 						src_swiz(coord, order[j]));
+			}
-			coord = &tmp_src;
+			coord = tmp_src;
 			if (j < 4)
 				ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 4 - j - 1;
 			break;
+		}
+	}
 	instr = ir3_instr_create(ctx->ir, 5, t->opc);
-	instr->cat5.type = get_type(ctx);
+	instr->cat5.type = get_ftype(ctx);
 	instr->cat5.samp = samp->Index;
 	instr->cat5.tex  = samp->Index;
+	instr->flags |= flags;
+	r = add_dst_reg(ctx, instr, &inst->Dst[0].Register, 0);
+	r->wrmask = inst->Dst[0].Register.WriteMask;
+	add_src_reg(ctx, instr, coord, coord->SwizzleX);
+	regmask_set(ctx->needs_sy, r, r->wrmask);
+}
+/*
+ * SEQ(a,b) = (a == b) ? 1.0 : 0.0
+ *   cmps.f.eq tmp0, b, a
+ *   cov.u16f16 dst, tmp0
+ *
+ * SNE(a,b) = (a != b) ? 1.0 : 0.0
+ *   cmps.f.eq tmp0, b, a
+ *   add.s tmp0, tmp0, -1
+ *   sel.f16 dst, {0.0}, tmp0, {1.0}
+ *
+ * SGE(a,b) = (a >= b) ? 1.0 : 0.0
+ *   cmps.f.ge tmp0, a, b
+ *   cov.u16f16 dst, tmp0
+ *
+ * SLE(a,b) = (a <= b) ? 1.0 : 0.0
+ *   cmps.f.ge tmp0, b, a
+ *   cov.u16f16 dst, tmp0
+ *
-	instr->flags |= flags;
+ * SGT(a,b) = (a > b)  ? 1.0 : 0.0
+ *   cmps.f.ge tmp0, b, a
+ *   add.s tmp0, tmp0, -1
+ *   sel.f16 dst, {0.0}, tmp0, {1.0}
+ *
  * SLT(a,b) = (a < b)  ? 1.0 : 0.0
-	r = add_dst_reg(ctx, instr, &inst->Dst[0].Register, 0);
+ *   cmps.f.ge tmp0, a, b
-	r->wrmask = inst->Dst[0].Register.WriteMask;
+ *   add.s tmp0, tmp0, -1
  *   sel.f16 dst, {0.0}, tmp0, {1.0}
 	add_src_reg(ctx, instr, coord, coord->SwizzleX);
  * CMP(a,b,c) = (a < 0.0) ? b : c
-	regmask_set(ctx->needs_sy, r);
+ *   cmps.f.ge tmp0, a, {0.0}
-}
+ *   add.s tmp0, tmp0, -1
+ *   sel.f16 dst, c, tmp0, b
-/* CMP(a,b,c) = (a < 0) ? b : c */
+ */
 static void
+trans_cmp(const struct instr_translater *t,
+		struct fd3_compile_context *ctx,
-trans_cmp(const struct instr_translater *t,
+		struct tgsi_full_instruction *inst)
+{
+	struct ir3_instruction *instr;
+	struct tgsi_dst_register tmp_dst;
+	struct tgsi_src_register *tmp_src;
+	struct tgsi_src_register constval0, constval1;
+	/* final instruction for CMP() uses orig src1 and src2: */
+	struct tgsi_dst_register *dst = get_dst(ctx, inst);
+	struct tgsi_src_register *a0, *a1;
+	unsigned condition;
+	tmp_src = get_internal_temp(ctx, &tmp_dst);
+	switch (t->tgsi_opc) {
+	case TGSI_OPCODE_SEQ:
+	case TGSI_OPCODE_SNE:
+		a0 = &inst->Src[1].Register;  /* b */
+		a1 = &inst->Src[0].Register;  /* a */
+		condition = IR3_COND_EQ;
+		break;
+	case TGSI_OPCODE_SGE:
+	case TGSI_OPCODE_SLT:
+		a0 = &inst->Src[0].Register;  /* a */
+		a1 = &inst->Src[1].Register;  /* b */
+		condition = IR3_COND_GE;
+		break;
+	case TGSI_OPCODE_SLE:
+	case TGSI_OPCODE_SGT:
+		a0 = &inst->Src[1].Register;  /* b */
+		a1 = &inst->Src[0].Register;  /* a */
+		condition = IR3_COND_GE;
+		break;
+	case TGSI_OPCODE_CMP:
+		get_immediate(ctx, &constval0, fui(0.0));
-		struct fd3_compile_context *ctx,
+		a0 = &inst->Src[0].Register;  /* a */
-		struct tgsi_full_instruction *inst)
+		a1 = &constval0;              /* {0.0} */
-{
+		condition = IR3_COND_GE;
-	struct ir3_instruction *instr;
-	struct tgsi_dst_register tmp_dst;
+		break;
-	struct tgsi_src_register tmp_src;
-	struct tgsi_src_register constval;
+	default:
+		compile_assert(ctx, 0);
+		return;
+	}
+	if (is_const(a0) && is_const(a1))
+		a0 = get_unconst(ctx, a0);
+	/* cmps.f.ge tmp, a0, a1 */
+	instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
+	instr->cat2.condition = condition;
+	vectorize(ctx, instr, &tmp_dst, 2, a0, 0, a1, 0);
+	switch (t->tgsi_opc) {
-	/* final instruction uses original src1 and src2, so we need get_dst() */
+	case TGSI_OPCODE_SEQ:
-	struct tgsi_dst_register *dst = get_dst(ctx, inst);
+	case TGSI_OPCODE_SGE:
 	case TGSI_OPCODE_SLE:
-	get_internal_temp(ctx, &tmp_dst, &tmp_src);
+		/* cov.u16f16 dst, tmp0 */
+		instr = ir3_instr_create(ctx->ir, 1, 0);
-	/* cmps.f.ge tmp, src0, 0.0 */
+		instr->cat1.src_type = get_utype(ctx);
+		instr->cat1.dst_type = get_ftype(ctx);
-	instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
+		vectorize(ctx, instr, dst, 1, tmp_src, 0);
-	instr->cat2.condition = IR3_COND_GE;
+		break;
-	get_immediate(ctx, &constval, fui(0.0));
+	case TGSI_OPCODE_SNE:
-	vectorize(ctx, instr, &tmp_dst, 2,
+	case TGSI_OPCODE_SGT:
-			&inst->Src[0].Register, 0,
+	case TGSI_OPCODE_SLT:
-			&constval, 0);
+	case TGSI_OPCODE_CMP:
 		/* add.s tmp, tmp, -1 */
+		instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
+		instr->repeat = 3;
+		add_dst_reg(ctx, instr, &tmp_dst, 0);
+		add_src_reg(ctx, instr, tmp_src, 0)->flags |= IR3_REG_R;
+		ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
+		if (t->tgsi_opc == TGSI_OPCODE_CMP) {
+			/* sel.{f32,f16} dst, src2, tmp, src1 */
+			instr = ir3_instr_create(ctx->ir, 3,
+					ctx->so->half_precision ? OPC_SEL_F16 : OPC_SEL_F32);
+			vectorize(ctx, instr, dst, 3,
+					&inst->Src[2].Register, 0,
-	/* add.s tmp, tmp, -1 */
+					tmp_src, 0,
-	instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
+					&inst->Src[1].Register, 0);
-	instr->repeat = 3;
+		} else {
 	struct tgsi_src_register *src = &inst->Src[0].Register;
 	struct tgsi_src_register constval;
+	get_immediate(ctx, &constval, fui(0.0));
+	if (is_const(src))
-	get_immediate(ctx, &constval, fui(0.0));
+		src = get_unconst(ctx, src);
-	instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
-	ir3_reg_create(instr, regid(REG_P0, 0), 0);
+	instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
+	ir3_reg_create(instr, regid(REG_P0, 0), 0);
-	add_src_reg(ctx, instr, &constval, constval.SwizzleX);
+	add_src_reg(ctx, instr, src, src->SwizzleX);
-	add_src_reg(ctx, instr, src, src->SwizzleX);
+	add_src_reg(ctx, instr, &constval, constval.SwizzleX);
 	instr->cat2.condition = IR3_COND_EQ;
 instr_cat2(const struct instr_translater *t,
 		struct fd3_compile_context *ctx,
 		struct tgsi_full_instruction *inst)
+{
 	struct tgsi_dst_register *dst = get_dst(ctx, inst);
+	struct tgsi_src_register *src0 = &inst->Src[0].Register;
+	struct tgsi_src_register *src1 = &inst->Src[1].Register;
 	struct ir3_instruction *instr;
 	unsigned src0_flags = 0;
-	instr = ir3_instr_create(ctx->ir, 2, t->opc);
-	switch (t->tgsi_opc) {
-	case TGSI_OPCODE_SLT:
-	case TGSI_OPCODE_SGE:
-		instr->cat2.condition = t->arg;
-		break;
+	switch (t->tgsi_opc) {
 	case TGSI_OPCODE_ABS:
 		src0_flags = IR3_REG_ABS;
 		break;
 	case OPC_NOT_B:
 	case OPC_BFREV_B:
 	case OPC_SETRM:
 	case OPC_CBITS_B:
 		/* these only have one src reg */
-		vectorize(ctx, instr, dst, 1,
+		instr = ir3_instr_create(ctx->ir, 2, t->opc);
-				&inst->Src[0].Register, src0_flags);
+		vectorize(ctx, instr, dst, 1, src0, src0_flags);
 		break;
 	default:
-		vectorize(ctx, instr, dst, 2,
+		if (is_const(src0) && is_const(src1))
-				&inst->Src[0].Register, src0_flags,
+			src0 = get_unconst(ctx, src0);
-				&inst->Src[1].Register, 0);
+		instr = ir3_instr_create(ctx->ir, 2, t->opc);
+		vectorize(ctx, instr, dst, 2, src0, src0_flags, src1, 0);
 		break;
+	}
 	put_dst(ctx, inst, dst);
+}
+static bool is_mad(opc_t opc)
+{
+	switch (opc) {
+	case OPC_MAD_U16:
+	case OPC_MADSH_U16:
+	case OPC_MAD_S16:
+	case OPC_MADSH_M16:
+	case OPC_MAD_U24:
+	case OPC_MAD_S24:
+	case OPC_MAD_F16:
+	case OPC_MAD_F32:
+		return true;
+	default:
+		return false;
+	}
+}
 static void
 instr_cat3(const struct instr_translater *t,
 		struct fd3_compile_context *ctx,
 		struct tgsi_full_instruction *inst)
+{
 	struct tgsi_dst_register *dst = get_dst(ctx, inst);
-	struct tgsi_dst_register *dst = get_dst(ctx, inst);
-	struct tgsi_src_register *src1 = &inst->Src[1].Register;
-	struct tgsi_dst_register tmp_dst;
+	struct tgsi_src_register *src0 = &inst->Src[0].Register;
-	struct tgsi_src_register tmp_src;
+	struct tgsi_src_register *src1 = &inst->Src[1].Register;
 	struct ir3_instruction *instr;
-	/* Blob compiler never seems to use a const in src1 position..
-	 * although there does seem (according to disassembler hidden
-	 * in libllvm-a3xx.so) to be a bit to indicate that src1 is a
-	 * const.  Not sure if this is a hw bug, or simply that the
+	/* in particular, can't handle const for src1 for cat3..
-	 * disassembler lies.
+	 * for mad, we can swap first two src's if needed:
 	 */
+	if (is_const(src1)) {
-	if ((src1->File == TGSI_FILE_CONSTANT) ||
+		if (is_mad(t->opc) && !is_const(src0)) {
-			(src1->File == TGSI_FILE_IMMEDIATE)) {
+			struct tgsi_src_register *tmp;
+			tmp = src0;
+			src0 = src1;
+			src1 = tmp;
-		get_internal_temp(ctx, &tmp_dst, &tmp_src);
+		} else {
-		create_mov(ctx, &tmp_dst, src1);
+			src0 = get_unconst(ctx, src0);
 		src1 = &tmp_src;
 	}
-	instr = ir3_instr_create(ctx->ir, 3,
 			ctx->so->half_precision ? t->hopc : t->opc);
-	vectorize(ctx, instr, dst, 3,
+	instr = ir3_instr_create(ctx->ir, 3,
-			&inst->Src[0].Register, 0,
+			ctx->so->half_precision ? t->hopc : t->opc);
-			src1, 0,
+	vectorize(ctx, instr, dst, 3, src0, 0, src1, 0,
 			&inst->Src[2].Register, 0);
 	put_dst(ctx, inst, dst);
+}
 static void
+instr_cat4(const struct instr_translater *t,
-instr_cat4(const struct instr_translater *t,
+		struct fd3_compile_context *ctx,
+		struct tgsi_full_instruction *inst)
+{
+	struct tgsi_dst_register *dst = get_dst(ctx, inst);
+	struct tgsi_src_register *src = &inst->Src[0].Register;
-		struct fd3_compile_context *ctx,
+	struct ir3_instruction *instr;
 		struct tgsi_full_instruction *inst)
-{
+	/* seems like blob compiler avoids const as src.. */
-	struct tgsi_dst_register *dst = get_dst(ctx, inst);
-	struct ir3_instruction *instr;
+	if (is_const(src))
+		src = get_unconst(ctx, src);
 	ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
 	instr = ir3_instr_create(ctx->ir, 4, t->opc);
 	INSTR(DP3,          trans_dotp, .arg = 3),
 	INSTR(DP4,          trans_dotp, .arg = 4),
 	INSTR(DPH,          trans_dotp, .arg = 3),   /* almost like DP3 */
 	INSTR(MIN,          instr_cat2, .opc = OPC_MIN_F),
 	INSTR(MAX,          instr_cat2, .opc = OPC_MAX_F),
-	INSTR(SLT,          instr_cat2, .opc = OPC_CMPS_F, .arg = IR3_COND_LT),
-	INSTR(SGE,          instr_cat2, .opc = OPC_CMPS_F, .arg = IR3_COND_GE),
 	INSTR(MAD,          instr_cat3, .opc = OPC_MAD_F32, .hopc = OPC_MAD_F16),
 	INSTR(LRP,          trans_lrp),
 	INSTR(FRC,          trans_frac),
 	INSTR(FLR,          instr_cat2, .opc = OPC_FLOOR_F),
+	INSTR(ARL,          instr_cat2, .opc = OPC_FLOOR_F),
 	INSTR(EX2,          instr_cat4, .opc = OPC_EXP2),
 	INSTR(LG2,          instr_cat4, .opc = OPC_LOG2),
 	INSTR(POW,          trans_pow),
 	INSTR(ABS,          instr_cat2, .opc = OPC_ABSNEG_F),
 	INSTR(COS,          instr_cat4, .opc = OPC_SIN),
 	INSTR(SIN,          instr_cat4, .opc = OPC_COS),
 	INSTR(TEX,          trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TEX),
 	INSTR(TXP,          trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TXP),
+	INSTR(SGT,          trans_cmp),
+	INSTR(SLT,          trans_cmp),
+	INSTR(SGE,          trans_cmp),
+	INSTR(SLE,          trans_cmp),
+	INSTR(SNE,          trans_cmp),
+	INSTR(SEQ,          trans_cmp),
 	INSTR(CMP,          trans_cmp),
 	INSTR(IF,           trans_if),
 	INSTR(ELSE,         trans_else),
 	INSTR(ENDIF,        trans_endif),
 	INSTR(END,          instr_cat0, .opc = OPC_END),
 	struct fd3_shader_stateobj *so = ctx->so;
 	unsigned base = ctx->base_reg[TGSI_FILE_OUTPUT];
 	unsigned name = decl->Semantic.Name;
 	unsigned i;
-	assert(decl->Declaration.Semantic);  // TODO is this ever not true?
+	compile_assert(ctx, decl->Declaration.Semantic);  // TODO is this ever not true?
 	DBG("decl out[%d] -> r%d", name, decl->Range.First + base);   // XXX
 		case TGSI_SEMANTIC_TEXCOORD:
 			for (i = decl->Range.First; i <= decl->Range.Last; i++)
 				so->outputs[so->outputs_count++].regid = regid(i + base, 0);
 			break;
 		default:
-			DBG("unknown VS semantic name: %s",
+			compile_error(ctx, "unknown VS semantic name: %s\n",
 					tgsi_semantic_names[name]);
-			assert(0);
+		}
 	} else {
 		switch (name) {
 		case TGSI_SEMANTIC_COLOR:
 			so->color_regid = regid(decl->Range.First + base, 0);
 			break;
 		default:
-			DBG("unknown VS semantic name: %s",
+			compile_error(ctx, "unknown VS semantic name: %s\n",
 					tgsi_semantic_names[name]);
-			assert(0);
+		}
+	}
+}
 			if (t->fxn) {
 				t->fxn(t, ctx, inst);
 				ctx->num_internal_temps = 0;
 			} else {
-				debug_printf("unknown TGSI opc: %s\n",
+				compile_error(ctx, "unknown TGSI opc: %s\n",
+						tgsi_get_opcode_name(opc));
+			}
+			switch (inst->Instruction.Saturate) {
+			case TGSI_SAT_ZERO_ONE:
+				create_clamp_imm(ctx, &inst->Dst[0].Register,
+						fui(0.0), fui(1.0));
+				break;
+			case TGSI_SAT_MINUS_PLUS_ONE:
-						tgsi_get_opcode_name(opc));
+				create_clamp_imm(ctx, &inst->Dst[0].Register,
-				tgsi_dump(ctx->tokens, 0);
+						fui(-1.0), fui(1.0));
-				assert(0);
+				break;
+			}
 			break;
 	assert(!so->ir);
+	so->ir = ir3_shader_create();
-	so->ir = ir3_shader_create();
+	assert(so->ir);
 	so->color_regid = regid(63,0);

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(root)/contrib/sdk/sources/Mesa/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c – Rev 4358 → 4401