Rev 4358 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 4358 | Rev 4401 | ||
|---|---|---|---|
| Line 6... | Line 6... | ||
| 6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
| 7 | http://0x04.net/cgit/index.cgi/rules-ng-ng |
7 | http://0x04.net/cgit/index.cgi/rules-ng-ng |
| 8 | git clone git://0x04.net/rules-ng-ng |
8 | git clone git://0x04.net/rules-ng-ng |
| Line 9... | Line 9... | ||
| 9 | 9 | ||
| 10 | The rules-ng-ng source files this header was generated from are: |
10 | The rules-ng-ng source files this header was generated from are: |
| 11 | - /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml ( 42578 bytes, from 2013-06-02 13:10:46) |
11 | - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) |
| - | 12 | - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) |
|
| 12 | - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) |
13 | - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) |
| 13 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 3094 bytes, from 2013-05-05 18:29:22) |
14 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) |
| - | 15 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) |
|
| Line 14... | Line 16... | ||
| 14 | - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) |
16 | - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05) |
| 15 | 17 | ||
| Line 16... | Line 18... | ||
| 16 | Copyright (C) 2013 by the following authors: |
18 | Copyright (C) 2013 by the following authors: |
| Line 128... | Line 130... | ||
| 128 | enum a3xx_tex_fmt { |
130 | enum a3xx_tex_fmt { |
| 129 | TFMT_NORM_USHORT_565 = 4, |
131 | TFMT_NORM_USHORT_565 = 4, |
| 130 | TFMT_NORM_USHORT_5551 = 6, |
132 | TFMT_NORM_USHORT_5551 = 6, |
| 131 | TFMT_NORM_USHORT_4444 = 7, |
133 | TFMT_NORM_USHORT_4444 = 7, |
| 132 | TFMT_NORM_UINT_X8Z24 = 10, |
134 | TFMT_NORM_UINT_X8Z24 = 10, |
| - | 135 | TFMT_NORM_UINT_NV12_UV_TILED = 17, |
|
| - | 136 | TFMT_NORM_UINT_NV12_Y_TILED = 19, |
|
| - | 137 | TFMT_NORM_UINT_NV12_UV = 21, |
|
| - | 138 | TFMT_NORM_UINT_NV12_Y = 23, |
|
| - | 139 | TFMT_NORM_UINT_I420_Y = 24, |
|
| - | 140 | TFMT_NORM_UINT_I420_U = 26, |
|
| - | 141 | TFMT_NORM_UINT_I420_V = 27, |
|
| 133 | TFMT_NORM_UINT_2_10_10_10 = 41, |
142 | TFMT_NORM_UINT_2_10_10_10 = 41, |
| 134 | TFMT_NORM_UINT_A8 = 44, |
143 | TFMT_NORM_UINT_A8 = 44, |
| 135 | TFMT_NORM_UINT_L8_A8 = 47, |
144 | TFMT_NORM_UINT_L8_A8 = 47, |
| 136 | TFMT_NORM_UINT_8 = 48, |
145 | TFMT_NORM_UINT_8 = 48, |
| 137 | TFMT_NORM_UINT_8_8 = 49, |
146 | TFMT_NORM_UINT_8_8 = 49, |
| Line 205... | Line 214... | ||
| 205 | A3XX_TEX_W = 3, |
214 | A3XX_TEX_W = 3, |
| 206 | A3XX_TEX_ZERO = 4, |
215 | A3XX_TEX_ZERO = 4, |
| 207 | A3XX_TEX_ONE = 5, |
216 | A3XX_TEX_ONE = 5, |
| 208 | }; |
217 | }; |
| Line -... | Line 218... | ||
| - | 218 | ||
| - | 219 | enum a3xx_tex_type { |
|
| - | 220 | A3XX_TEX_1D = 0, |
|
| - | 221 | A3XX_TEX_2D = 1, |
|
| - | 222 | A3XX_TEX_CUBE = 2, |
|
| - | 223 | A3XX_TEX_3D = 3, |
|
| - | 224 | }; |
|
| - | 225 | ||
| - | 226 | #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 |
|
| - | 227 | #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 |
|
| - | 228 | #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 |
|
| - | 229 | #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 |
|
| - | 230 | #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 |
|
| - | 231 | #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 |
|
| - | 232 | #define A3XX_INT0_VFD_ERROR 0x00000040 |
|
| - | 233 | #define A3XX_INT0_CP_SW_INT 0x00000080 |
|
| - | 234 | #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 |
|
| - | 235 | #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 |
|
| - | 236 | #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 |
|
| - | 237 | #define A3XX_INT0_CP_HW_FAULT 0x00000800 |
|
| - | 238 | #define A3XX_INT0_CP_DMA 0x00001000 |
|
| - | 239 | #define A3XX_INT0_CP_IB2_INT 0x00002000 |
|
| - | 240 | #define A3XX_INT0_CP_IB1_INT 0x00004000 |
|
| - | 241 | #define A3XX_INT0_CP_RB_INT 0x00008000 |
|
| - | 242 | #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 |
|
| - | 243 | #define A3XX_INT0_CP_RB_DONE_TS 0x00020000 |
|
| - | 244 | #define A3XX_INT0_CP_VS_DONE_TS 0x00040000 |
|
| - | 245 | #define A3XX_INT0_CP_PS_DONE_TS 0x00080000 |
|
| - | 246 | #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 |
|
| - | 247 | #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 |
|
| - | 248 | #define A3XX_INT0_MISC_HANG_DETECT 0x01000000 |
|
| 209 | 249 | #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 |
|
| Line 210... | Line 250... | ||
| 210 | #define REG_A3XX_RBBM_HW_VERSION 0x00000000 |
250 | #define REG_A3XX_RBBM_HW_VERSION 0x00000000 |
| Line 211... | Line 251... | ||
| 211 | 251 | ||
| Line 228... | Line 268... | ||
| 228 | #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 |
268 | #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 |
| Line 229... | Line 269... | ||
| 229 | 269 | ||
| Line 230... | Line 270... | ||
| 230 | #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e |
270 | #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e |
| - | 271 | ||
| - | 272 | #define REG_A3XX_RBBM_STATUS 0x00000030 |
|
| - | 273 | #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 |
|
| - | 274 | #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 |
|
| - | 275 | #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 |
|
| - | 276 | #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 |
|
| - | 277 | #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 |
|
| - | 278 | #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 |
|
| - | 279 | #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 |
|
| - | 280 | #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 |
|
| - | 281 | #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 |
|
| - | 282 | #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 |
|
| - | 283 | #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 |
|
| - | 284 | #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 |
|
| - | 285 | #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 |
|
| - | 286 | #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 |
|
| - | 287 | #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 |
|
| - | 288 | #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 |
|
| - | 289 | #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 |
|
| - | 290 | #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 |
|
| - | 291 | #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 |
|
| Line 231... | Line 292... | ||
| 231 | 292 | #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 |
|
| Line 232... | Line 293... | ||
| 232 | #define REG_A3XX_RBBM_STATUS 0x00000030 |
293 | #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 |
| Line 249... | Line 310... | ||
| 249 | 310 | ||
| Line 250... | Line 311... | ||
| 250 | #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 |
311 | #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 |
| Line -... | Line 312... | ||
| - | 312 | ||
| - | 313 | #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 |
|
| - | 314 | ||
| - | 315 | #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 |
|
| - | 316 | ||
| - | 317 | #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 |
|
| - | 318 | ||
| - | 319 | #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 |
|
| - | 320 | ||
| - | 321 | #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 |
|
| - | 322 | ||
| - | 323 | #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 |
|
| 251 | 324 | ||
| Line -... | Line 325... | ||
| - | 325 | #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 |
|
| - | 326 | ||
| - | 327 | #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 |
|
| - | 328 | ||
| - | 329 | #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 |
|
| - | 330 | ||
| - | 331 | #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 |
|
| - | 332 | ||
| - | 333 | #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 |
|
| - | 334 | ||
| - | 335 | #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 |
|
| - | 336 | ||
| - | 337 | #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 |
|
| - | 338 | ||
| - | 339 | #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 |
|
| - | 340 | ||
| - | 341 | #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 |
|
| - | 342 | ||
| - | 343 | #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 |
|
| - | 344 | ||
| - | 345 | #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 |
|
| - | 346 | ||
| - | 347 | #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 |
|
| - | 348 | ||
| - | 349 | #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a |
|
| - | 350 | ||
| - | 351 | #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b |
|
| - | 352 | ||
| - | 353 | #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c |
|
| - | 354 | ||
| - | 355 | #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d |
|
| - | 356 | ||
| - | 357 | #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e |
|
| - | 358 | ||
| - | 359 | #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f |
|
| - | 360 | ||
| - | 361 | #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 |
|
| - | 362 | ||
| - | 363 | #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 |
|
| - | 364 | ||
| - | 365 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 |
|
| - | 366 | ||
| - | 367 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 |
|
| - | 368 | ||
| - | 369 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 |
|
| - | 370 | ||
| - | 371 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 |
|
| - | 372 | ||
| - | 373 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 |
|
| - | 374 | ||
| - | 375 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 |
|
| - | 376 | ||
| - | 377 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 |
|
| - | 378 | ||
| - | 379 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 |
|
| - | 380 | ||
| - | 381 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa |
|
| - | 382 | ||
| - | 383 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab |
|
| - | 384 | ||
| - | 385 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac |
|
| - | 386 | ||
| - | 387 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad |
|
| - | 388 | ||
| - | 389 | #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae |
|
| - | 390 | ||
| - | 391 | #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af |
|
| - | 392 | ||
| - | 393 | #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 |
|
| - | 394 | ||
| - | 395 | #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 |
|
| - | 396 | ||
| - | 397 | #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 |
|
| - | 398 | ||
| - | 399 | #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 |
|
| - | 400 | ||
| - | 401 | #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 |
|
| - | 402 | ||
| - | 403 | #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 |
|
| - | 404 | ||
| - | 405 | #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 |
|
| - | 406 | ||
| - | 407 | #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 |
|
| - | 408 | ||
| - | 409 | #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 |
|
| - | 410 | ||
| - | 411 | #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 |
|
| - | 412 | ||
| - | 413 | #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba |
|
| - | 414 | ||
| - | 415 | #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb |
|
| - | 416 | ||
| - | 417 | #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc |
|
| - | 418 | ||
| - | 419 | #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd |
|
| - | 420 | ||
| - | 421 | #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be |
|
| - | 422 | ||
| - | 423 | #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf |
|
| - | 424 | ||
| - | 425 | #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 |
|
| - | 426 | ||
| - | 427 | #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 |
|
| - | 428 | ||
| - | 429 | #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 |
|
| - | 430 | ||
| - | 431 | #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 |
|
| - | 432 | ||
| - | 433 | #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 |
|
| - | 434 | ||
| - | 435 | #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 |
|
| - | 436 | ||
| - | 437 | #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 |
|
| - | 438 | ||
| - | 439 | #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 |
|
| - | 440 | ||
| - | 441 | #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 |
|
| - | 442 | ||
| - | 443 | #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 |
|
| - | 444 | ||
| - | 445 | #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca |
|
| - | 446 | ||
| - | 447 | #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb |
|
| - | 448 | ||
| - | 449 | #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc |
|
| - | 450 | ||
| - | 451 | #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd |
|
| - | 452 | ||
| - | 453 | #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce |
|
| - | 454 | ||
| - | 455 | #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf |
|
| - | 456 | ||
| - | 457 | #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 |
|
| - | 458 | ||
| - | 459 | #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 |
|
| - | 460 | ||
| - | 461 | #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 |
|
| - | 462 | ||
| - | 463 | #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 |
|
| - | 464 | ||
| - | 465 | #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 |
|
| - | 466 | ||
| - | 467 | #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 |
|
| - | 468 | ||
| - | 469 | #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 |
|
| - | 470 | ||
| - | 471 | #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 |
|
| - | 472 | ||
| - | 473 | #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 |
|
| - | 474 | ||
| - | 475 | #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 |
|
| - | 476 | ||
| - | 477 | #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da |
|
| - | 478 | ||
| - | 479 | #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db |
|
| - | 480 | ||
| - | 481 | #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc |
|
| - | 482 | ||
| - | 483 | #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd |
|
| - | 484 | ||
| 252 | #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 |
485 | #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de |
| Line 253... | Line 486... | ||
| 253 | 486 | ||
| Line -... | Line 487... | ||
| - | 487 | #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df |
|
| - | 488 | ||
| - | 489 | #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 |
|
| - | 490 | ||
| - | 491 | #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 |
|
| - | 492 | ||
| - | 493 | #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 |
|
| - | 494 | ||
| - | 495 | #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 |
|
| - | 496 | ||
| - | 497 | #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 |
|
| - | 498 | ||
| 254 | #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 |
499 | #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 |
| Line 255... | Line 500... | ||
| 255 | 500 | ||
| Line 256... | Line 501... | ||
| 256 | #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 |
501 | #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea |
| Line 257... | Line -... | ||
| 257 | - | ||
| 258 | #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 |
- | |
| 259 | 502 | ||
| Line 260... | Line 503... | ||
| 260 | #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec |
503 | #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb |
| Line 261... | Line 504... | ||
| 261 | 504 | ||
| Line 285... | Line 528... | ||
| 285 | 528 | ||
| Line 286... | Line 529... | ||
| 286 | #define REG_A3XX_CP_MEQ_ADDR 0x000001da |
529 | #define REG_A3XX_CP_MEQ_ADDR 0x000001da |
| Line -... | Line 530... | ||
| - | 530 | ||
| - | 531 | #define REG_A3XX_CP_MEQ_DATA 0x000001db |
|
| 287 | 532 | ||
| Line 288... | Line 533... | ||
| 288 | #define REG_A3XX_CP_MEQ_DATA 0x000001db |
533 | #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 |
| Line 289... | Line 534... | ||
| 289 | 534 | ||
| Line 290... | Line 535... | ||
| 290 | #define REG_A3XX_CP_HW_FAULT 0x0000045c |
535 | #define REG_A3XX_CP_HW_FAULT 0x0000045c |
| Line 291... | Line 536... | ||
| 291 | 536 | ||
| Line 292... | Line 537... | ||
| 292 | #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e |
537 | #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e |
| Line 293... | Line -... | ||
| 293 | - | ||
| 294 | #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f |
- | |
| 295 | - | ||
| 296 | #define REG_A3XX_CP_PROTECT(i0) (0x00000460 + 0x1*(i0)) |
- | |
| 297 | 538 | ||
| 298 | #define REG_A3XX_CP_PROTECT_REG(i0) (0x00000460 + 0x1*(i0)) |
539 | #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f |
| 299 | 540 | ||
| 300 | #define REG_A3XX_CP_AHB_FAULT 0x0000054d |
541 | static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } |
| 301 | 542 | ||
| Line 526... | Line 767... | ||
| 526 | return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; |
767 | return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; |
| 527 | } |
768 | } |
| Line 528... | Line 769... | ||
| 528 | 769 | ||
| Line 529... | Line 770... | ||
| 529 | #define REG_A3XX_UNKNOWN_20C3 0x000020c3 |
770 | #define REG_A3XX_UNKNOWN_20C3 0x000020c3 |
| Line 530... | Line 771... | ||
| 530 | 771 | ||
| 531 | #define REG_A3XX_RB_MRT(i0) (0x000020c4 + 0x4*(i0)) |
772 | static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } |
| 532 | 773 | ||
| 533 | #define REG_A3XX_RB_MRT_CONTROL(i0) (0x000020c4 + 0x4*(i0)) |
774 | static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } |
| 534 | #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 |
775 | #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 |
| 535 | #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 |
776 | #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 |
| Line 551... | Line 792... | ||
| 551 | static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) |
792 | static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) |
| 552 | { |
793 | { |
| 553 | return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; |
794 | return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; |
| 554 | } |
795 | } |
| Line 555... | Line 796... | ||
| 555 | 796 | ||
| 556 | #define REG_A3XX_RB_MRT_BUF_INFO(i0) (0x000020c5 + 0x4*(i0)) |
797 | static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } |
| 557 | #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f |
798 | #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f |
| 558 | #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 |
799 | #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 |
| 559 | static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) |
800 | static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) |
| 560 | { |
801 | { |
| Line 577... | Line 818... | ||
| 577 | static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) |
818 | static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) |
| 578 | { |
819 | { |
| 579 | return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; |
820 | return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; |
| 580 | } |
821 | } |
| Line 581... | Line 822... | ||
| 581 | 822 | ||
| 582 | #define REG_A3XX_RB_MRT_BUF_BASE(i0) (0x000020c6 + 0x4*(i0)) |
823 | static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } |
| 583 | #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 |
824 | #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 |
| 584 | #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 |
825 | #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 |
| 585 | static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) |
826 | static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) |
| 586 | { |
827 | { |
| 587 | return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; |
828 | return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; |
| Line 588... | Line 829... | ||
| 588 | } |
829 | } |
| 589 | 830 | ||
| 590 | #define REG_A3XX_RB_MRT_BLEND_CONTROL(i0) (0x000020c7 + 0x4*(i0)) |
831 | static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } |
| 591 | #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f |
832 | #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f |
| 592 | #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 |
833 | #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 |
| 593 | static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) |
834 | static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) |
| Line 625... | Line 866... | ||
| 625 | return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; |
866 | return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; |
| 626 | } |
867 | } |
| 627 | #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 |
868 | #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 |
| Line 628... | Line 869... | ||
| 628 | 869 | ||
| - | 870 | #define REG_A3XX_RB_BLEND_RED 0x000020e4 |
|
| - | 871 | #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff |
|
| - | 872 | #define A3XX_RB_BLEND_RED_UINT__SHIFT 0 |
|
| - | 873 | static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) |
|
| - | 874 | { |
|
| - | 875 | return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; |
|
| - | 876 | } |
|
| - | 877 | #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 |
|
| - | 878 | #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 |
|
| - | 879 | static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) |
|
| - | 880 | { |
|
| - | 881 | return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; |
|
| Line 629... | Line 882... | ||
| 629 | #define REG_A3XX_RB_BLEND_RED 0x000020e4 |
882 | } |
| - | 883 | ||
| - | 884 | #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 |
|
| - | 885 | #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff |
|
| - | 886 | #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 |
|
| - | 887 | static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) |
|
| - | 888 | { |
|
| - | 889 | return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; |
|
| - | 890 | } |
|
| - | 891 | #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 |
|
| - | 892 | #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 |
|
| - | 893 | static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) |
|
| - | 894 | { |
|
| Line 630... | Line 895... | ||
| 630 | 895 | return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; |
|
| - | 896 | } |
|
| - | 897 | ||
| - | 898 | #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 |
|
| - | 899 | #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff |
|
| - | 900 | #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 |
|
| - | 901 | static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) |
|
| - | 902 | { |
|
| - | 903 | return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; |
|
| - | 904 | } |
|
| - | 905 | #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 |
|
| - | 906 | #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 |
|
| - | 907 | static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) |
|
| Line 631... | Line 908... | ||
| 631 | #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 |
908 | { |
| - | 909 | return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; |
|
| - | 910 | } |
|
| - | 911 | ||
| - | 912 | #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 |
|
| - | 913 | #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff |
|
| - | 914 | #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 |
|
| - | 915 | static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) |
|
| - | 916 | { |
|
| - | 917 | return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; |
|
| - | 918 | } |
|
| - | 919 | #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 |
|
| - | 920 | #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 |
|
| Line 632... | Line 921... | ||
| 632 | 921 | static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) |
|
| Line 633... | Line 922... | ||
| 633 | #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 |
922 | { |
| Line 1061... | Line 1350... | ||
| 1061 | 1350 | ||
| Line 1062... | Line 1351... | ||
| 1062 | #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 |
1351 | #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 |
| Line 1063... | Line 1352... | ||
| 1063 | 1352 | ||
| Line 1064... | Line 1353... | ||
| 1064 | #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 |
1353 | #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 |
| 1065 | 1354 | ||
| 1066 | #define REG_A3XX_VFD_FETCH(i0) (0x00002246 + 0x2*(i0)) |
1355 | static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } |
| 1067 | 1356 | ||
| 1068 | #define REG_A3XX_VFD_FETCH_INSTR_0(i0) (0x00002246 + 0x2*(i0)) |
1357 | static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } |
| 1069 | #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f |
1358 | #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f |
| Line 1090... | Line 1379... | ||
| 1090 | static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) |
1379 | static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) |
| 1091 | { |
1380 | { |
| 1092 | return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; |
1381 | return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; |
| 1093 | } |
1382 | } |
| Line 1094... | Line 1383... | ||
| 1094 | 1383 | ||
| Line 1095... | Line 1384... | ||
| 1095 | #define REG_A3XX_VFD_FETCH_INSTR_1(i0) (0x00002247 + 0x2*(i0)) |
1384 | static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } |
| Line 1096... | Line 1385... | ||
| 1096 | 1385 | ||
| 1097 | #define REG_A3XX_VFD_DECODE(i0) (0x00002266 + 0x1*(i0)) |
1386 | static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } |
| 1098 | 1387 | ||
| 1099 | #define REG_A3XX_VFD_DECODE_INSTR(i0) (0x00002266 + 0x1*(i0)) |
1388 | static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } |
| 1100 | #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f |
1389 | #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f |
| 1101 | #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 |
1390 | #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 |
| Line 1171... | Line 1460... | ||
| 1171 | static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) |
1460 | static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) |
| 1172 | { |
1461 | { |
| 1173 | return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; |
1462 | return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; |
| 1174 | } |
1463 | } |
| Line 1175... | Line 1464... | ||
| 1175 | 1464 | ||
| Line 1176... | Line 1465... | ||
| 1176 | #define REG_A3XX_VPC_VARYING_INTERP(i0) (0x00002282 + 0x1*(i0)) |
1465 | static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } |
| Line 1177... | Line 1466... | ||
| 1177 | 1466 | ||
| Line 1178... | Line 1467... | ||
| 1178 | #define REG_A3XX_VPC_VARYING_INTERP_MODE(i0) (0x00002282 + 0x1*(i0)) |
1467 | static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } |
| Line 1179... | Line 1468... | ||
| 1179 | 1468 | ||
| Line 1180... | Line 1469... | ||
| 1180 | #define REG_A3XX_VPC_VARYING_PS_REPL(i0) (0x00002286 + 0x1*(i0)) |
1469 | static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } |
| Line 1291... | Line 1580... | ||
| 1291 | static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) |
1580 | static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) |
| 1292 | { |
1581 | { |
| 1293 | return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; |
1582 | return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; |
| 1294 | } |
1583 | } |
| Line 1295... | Line 1584... | ||
| 1295 | 1584 | ||
| Line 1296... | Line 1585... | ||
| 1296 | #define REG_A3XX_SP_VS_OUT(i0) (0x000022c7 + 0x1*(i0)) |
1585 | static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } |
| 1297 | 1586 | ||
| 1298 | #define REG_A3XX_SP_VS_OUT_REG(i0) (0x000022c7 + 0x1*(i0)) |
1587 | static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } |
| 1299 | #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff |
1588 | #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff |
| 1300 | #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 |
1589 | #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 |
| 1301 | static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) |
1590 | static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) |
| Line 1319... | Line 1608... | ||
| 1319 | static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) |
1608 | static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) |
| 1320 | { |
1609 | { |
| 1321 | return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; |
1610 | return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; |
| 1322 | } |
1611 | } |
| Line 1323... | Line 1612... | ||
| 1323 | 1612 | ||
| Line 1324... | Line 1613... | ||
| 1324 | #define REG_A3XX_SP_VS_VPC_DST(i0) (0x000022d0 + 0x1*(i0)) |
1613 | static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } |
| 1325 | 1614 | ||
| 1326 | #define REG_A3XX_SP_VS_VPC_DST_REG(i0) (0x000022d0 + 0x1*(i0)) |
1615 | static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } |
| 1327 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff |
1616 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff |
| 1328 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 |
1617 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 |
| 1329 | static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) |
1618 | static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) |
| Line 1478... | Line 1767... | ||
| 1478 | 1767 | ||
| Line 1479... | Line 1768... | ||
| 1479 | #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 |
1768 | #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 |
| Line 1480... | Line 1769... | ||
| 1480 | 1769 | ||
| Line 1481... | Line 1770... | ||
| 1481 | #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec |
1770 | #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec |
| 1482 | 1771 | ||
| 1483 | #define REG_A3XX_SP_FS_MRT(i0) (0x000022f0 + 0x1*(i0)) |
1772 | static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } |
| 1484 | 1773 | ||
| 1485 | #define REG_A3XX_SP_FS_MRT_REG(i0) (0x000022f0 + 0x1*(i0)) |
1774 | static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } |
| 1486 | #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff |
1775 | #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff |
| 1487 | #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 |
1776 | #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 |
| 1488 | static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) |
1777 | static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) |
| Line 1489... | Line 1778... | ||
| 1489 | { |
1778 | { |
| Line 1490... | Line 1779... | ||
| 1490 | return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; |
1779 | return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; |
| 1491 | } |
1780 | } |
| 1492 | #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 |
1781 | #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 |
| 1493 | 1782 | ||
| 1494 | #define REG_A3XX_SP_FS_IMAGE_OUTPUT(i0) (0x000022f4 + 0x1*(i0)) |
1783 | static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } |
| 1495 | 1784 | ||
| Line 1605... | Line 1894... | ||
| 1605 | return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; |
1894 | return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; |
| 1606 | } |
1895 | } |
| Line 1607... | Line 1896... | ||
| 1607 | 1896 | ||
| Line 1608... | Line 1897... | ||
| 1608 | #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 |
1897 | #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 |
| Line 1609... | Line 1898... | ||
| 1609 | 1898 | ||
| 1610 | #define REG_A3XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0)) |
1899 | static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } |
| 1611 | 1900 | ||
| 1612 | #define REG_A3XX_VSC_PIPE_CONFIG(i0) (0x00000c06 + 0x3*(i0)) |
1901 | static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } |
| 1613 | #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff |
1902 | #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff |
| 1614 | #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 |
1903 | #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 |
| Line 1633... | Line 1922... | ||
| 1633 | static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) |
1922 | static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) |
| 1634 | { |
1923 | { |
| 1635 | return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; |
1924 | return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; |
| 1636 | } |
1925 | } |
| Line 1637... | Line 1926... | ||
| 1637 | 1926 | ||
| Line 1638... | Line 1927... | ||
| 1638 | #define REG_A3XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000c07 + 0x3*(i0)) |
1927 | static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } |
| Line 1639... | Line 1928... | ||
| 1639 | 1928 | ||
| Line -... | Line 1929... | ||
| - | 1929 | static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } |
|
| - | 1930 | ||
| - | 1931 | #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d |
|
| - | 1932 | ||
| - | 1933 | #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 |
|
| - | 1934 | ||
| - | 1935 | #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 |
|
| - | 1936 | ||
| 1640 | #define REG_A3XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c08 + 0x3*(i0)) |
1937 | #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a |
| Line 1641... | Line 1938... | ||
| 1641 | 1938 | ||
| - | 1939 | #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b |
|
| - | 1940 | ||
| Line 1642... | Line 1941... | ||
| 1642 | #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d |
1941 | #define REG_A3XX_UNKNOWN_0C81 0x00000c81 |
| Line 1643... | Line 1942... | ||
| 1643 | 1942 | ||
| Line 1644... | Line 1943... | ||
| 1644 | #define REG_A3XX_UNKNOWN_0C81 0x00000c81 |
1943 | #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 |
| Line -... | Line 1944... | ||
| - | 1944 | ||
| - | 1945 | #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 |
|
| - | 1946 | ||
| - | 1947 | #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a |
|
| - | 1948 | ||
| - | 1949 | #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b |
|
| 1645 | 1950 | ||
| Line 1646... | Line 1951... | ||
| 1646 | #define REG_A3XX_GRAS_CL_USER_PLANE(i0) (0x00000ca0 + 0x4*(i0)) |
1951 | static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } |
| Line -... | Line 1952... | ||
| - | 1952 | ||
| - | 1953 | static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } |
|
| - | 1954 | ||
| - | 1955 | static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } |
|
| 1647 | 1956 | ||
| 1648 | #define REG_A3XX_GRAS_CL_USER_PLANE_X(i0) (0x00000ca0 + 0x4*(i0)) |
1957 | static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } |
| 1649 | 1958 | ||
| 1650 | #define REG_A3XX_GRAS_CL_USER_PLANE_Y(i0) (0x00000ca1 + 0x4*(i0)) |
1959 | static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } |
| 1651 | 1960 | ||
| Line 1667... | Line 1976... | ||
| 1667 | static inline uint32_t A3XX_RB_WINDOW_SIZE_HEIGHT(uint32_t val) |
1976 | static inline uint32_t A3XX_RB_WINDOW_SIZE_HEIGHT(uint32_t val) |
| 1668 | { |
1977 | { |
| 1669 | return ((val) << A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT) & A3XX_RB_WINDOW_SIZE_HEIGHT__MASK; |
1978 | return ((val) << A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT) & A3XX_RB_WINDOW_SIZE_HEIGHT__MASK; |
| 1670 | } |
1979 | } |
| Line 1671... | Line 1980... | ||
| 1671 | 1980 | ||
| - | 1981 | #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 |
|
| - | 1982 | ||
| - | 1983 | #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 |
|
| - | 1984 | ||
| - | 1985 | #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 |
|
| - | 1986 | ||
| - | 1987 | #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 |
|
| - | 1988 | ||
| - | 1989 | #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 |
|
| - | 1990 | ||
| Line 1672... | Line 1991... | ||
| 1672 | #define REG_A3XX_UNKNOWN_0E00 0x00000e00 |
1991 | #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 |
| Line 1673... | Line 1992... | ||
| 1673 | 1992 | ||
| Line -... | Line 1993... | ||
| - | 1993 | #define REG_A3XX_UNKNOWN_0E43 0x00000e43 |
|
| - | 1994 | ||
| 1674 | #define REG_A3XX_UNKNOWN_0E43 0x00000e43 |
1995 | #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 |
| Line 1675... | Line 1996... | ||
| 1675 | 1996 | ||
| Line -... | Line 1997... | ||
| - | 1997 | #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 |
|
| - | 1998 | ||
| - | 1999 | #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 |
|
| - | 2000 | ||
| 1676 | #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 |
2001 | #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 |
| Line -... | Line 2002... | ||
| - | 2002 | ||
| - | 2003 | #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 |
|
| - | 2004 | ||
| - | 2005 | #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 |
|
| - | 2006 | ||
| - | 2007 | #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 |
|
| - | 2008 | ||
| - | 2009 | #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 |
|
| - | 2010 | ||
| - | 2011 | #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 |
|
| - | 2012 | ||
| - | 2013 | #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 |
|
| 1677 | 2014 | ||
| 1678 | #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 |
2015 | #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 |
| 1679 | 2016 | ||
| 1680 | #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 |
2017 | #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 |
| 1681 | 2018 | ||
| Line 1722... | Line 2059... | ||
| 1722 | 2059 | ||
| Line 1723... | Line 2060... | ||
| 1723 | #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 |
2060 | #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 |
| Line -... | Line 2061... | ||
| - | 2061 | ||
| - | 2062 | #define REG_A3XX_UNKNOWN_0F03 0x00000f03 |
|
| - | 2063 | ||
| - | 2064 | #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 |
|
| - | 2065 | ||
| - | 2066 | #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 |
|
| - | 2067 | ||
| - | 2068 | #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 |
|
| - | 2069 | ||
| - | 2070 | #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 |
|
| - | 2071 | ||
| - | 2072 | #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 |
|
| 1724 | 2073 | ||
| 1725 | #define REG_A3XX_UNKNOWN_0F03 0x00000f03 |
2074 | #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 |
| 1726 | 2075 | ||
| 1727 | #define REG_A3XX_TEX_SAMP_0 0x00000000 |
2076 | #define REG_A3XX_TEX_SAMP_0 0x00000000 |
| 1728 | #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c |
2077 | #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c |
| Line 1789... | Line 2138... | ||
| 1789 | #define A3XX_TEX_CONST_0_FMT__SHIFT 22 |
2138 | #define A3XX_TEX_CONST_0_FMT__SHIFT 22 |
| 1790 | static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) |
2139 | static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) |
| 1791 | { |
2140 | { |
| 1792 | return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; |
2141 | return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; |
| 1793 | } |
2142 | } |
| - | 2143 | #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 |
|
| - | 2144 | #define A3XX_TEX_CONST_0_TYPE__SHIFT 30 |
|
| - | 2145 | static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) |
|
| - | 2146 | { |
|
| - | 2147 | return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; |
|
| - | 2148 | } |
|
| Line 1794... | Line 2149... | ||
| 1794 | 2149 | ||
| 1795 | #define REG_A3XX_TEX_CONST_1 0x00000001 |
2150 | #define REG_A3XX_TEX_CONST_1 0x00000001 |
| 1796 | #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff |
2151 | #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff |
| 1797 | #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 |
2152 | #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 |