Subversion Repositories Kolibri OS

Rev

Rev 4358 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 4358 Rev 4401
Line 6... Line 6...
6 
This file was generated by the rules-ng-ng headergen tool in this git repository:
 6 
This file was generated by the rules-ng-ng headergen tool in this git repository:
7 
http://0x04.net/cgit/index.cgi/rules-ng-ng
 7 
http://0x04.net/cgit/index.cgi/rules-ng-ng
8 
git clone git://0x04.net/rules-ng-ng
 8 
git clone git://0x04.net/rules-ng-ng
Line 9... Line 9...
9 
 
 9 
 
10 
The rules-ng-ng source files this header was generated from are:
 10 
The rules-ng-ng source files this header was generated from are:
11 
- /home/robclark/src/freedreno/envytools/rnndb/a2xx.xml                (  30127 bytes, from 2013-05-05 18:29:35)
 11 
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
- 
 
 12 
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
12 
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
 13 
- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  30005 bytes, from 2013-07-19 21:30:48)
13 
- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   3094 bytes, from 2013-05-05 18:29:22)
 14 
- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
- 
 
 15 
- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)
Line 14... Line 16...
14 
- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)
 16 
- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51415 bytes, from 2013-08-03 14:26:05)
15 
 
 17 
 
Line 16... Line 18...
16 
Copyright (C) 2013 by the following authors:
 18 
Copyright (C) 2013 by the following authors:
Line 234... Line 236...
234 
 
 236 
 
Line 235... Line 237...
235 
#define REG_A2XX_CP_PFP_UCODE_ADDR				0x000000c0
 237 
#define REG_A2XX_CP_PFP_UCODE_ADDR				0x000000c0
Line 236... Line -...
236 
 
 - 
 
237 
#define REG_A2XX_CP_PFP_UCODE_DATA				0x000000c1
 - 
 
238 
 
 - 
 
239 
#define REG_A2XX_CP_RB_BASE					0x000001c0
 - 
 
240 
 
 - 
 
241 
#define REG_A2XX_CP_RB_CNTL					0x000001c1
 - 
 
242 
 
 - 
 
243 
#define REG_A2XX_CP_RB_RPTR_ADDR				0x000001c3
 - 
 
244 
 
 - 
 
245 
#define REG_A2XX_CP_RB_RPTR					0x000001c4
 - 
 
246 
 
 - 
 
247 
#define REG_A2XX_CP_RB_WPTR					0x000001c5
 - 
 
248 
 
 - 
 
249 
#define REG_A2XX_CP_RB_WPTR_DELAY				0x000001c6
 - 
 
250 
 
 - 
 
251 
#define REG_A2XX_CP_RB_RPTR_WR					0x000001c7
 - 
 
252 
 
 - 
 
253 
#define REG_A2XX_CP_RB_WPTR_BASE				0x000001c8
 - 
 
254 
 
 - 
 
255 
#define REG_A2XX_CP_QUEUE_THRESHOLDS				0x000001d5
 - 
 
256 
 
 - 
 
257 
#define REG_A2XX_SCRATCH_UMSK					0x000001dc
 - 
 
258 
 
 - 
 
259 
#define REG_A2XX_SCRATCH_ADDR					0x000001dd
 - 
 
260 
 
 - 
 
261 
#define REG_A2XX_CP_STATE_DEBUG_INDEX				0x000001ec
 - 
 
262 
 
 - 
 
263 
#define REG_A2XX_CP_STATE_DEBUG_DATA				0x000001ed
 - 
 
264 
 
 - 
 
265 
#define REG_A2XX_CP_INT_CNTL					0x000001f2
 - 
 
266 
 
 - 
 
267 
#define REG_A2XX_CP_INT_STATUS					0x000001f3
 - 
 
268 
 
 - 
 
269 
#define REG_A2XX_CP_INT_ACK					0x000001f4
 - 
 
270 
 
 - 
 
271 
#define REG_A2XX_CP_ME_CNTL					0x000001f6
 - 
 
272 
 
 - 
 
273 
#define REG_A2XX_CP_ME_STATUS					0x000001f7
 - 
 
274 
 
 - 
 
275 
#define REG_A2XX_CP_ME_RAM_WADDR				0x000001f8
 - 
 
276 
 
 - 
 
277 
#define REG_A2XX_CP_ME_RAM_RADDR				0x000001f9
 - 
 
278 
 
 - 
 
279 
#define REG_A2XX_CP_ME_RAM_DATA					0x000001fa
 - 
 
280 
 
 - 
 
281 
#define REG_A2XX_CP_DEBUG					0x000001fc
 - 
 
282 
 
 - 
 
283 
#define REG_A2XX_CP_CSQ_RB_STAT					0x000001fd
 - 
 
284 
 
 - 
 
285 
#define REG_A2XX_CP_CSQ_IB1_STAT				0x000001fe
 - 
 
286 
 
 238 
 
Line 287... Line 239...
287 
#define REG_A2XX_CP_CSQ_IB2_STAT				0x000001ff
 239 
#define REG_A2XX_CP_PFP_UCODE_DATA				0x000000c1
Line 288... Line 240...
288 
 
 240 
 
Line 336... Line 288...
336 
 
 288 
 
Line 337... Line 289...
337 
#define REG_A2XX_CP_IB2_BUFSZ					0x0000045b
 289 
#define REG_A2XX_CP_IB2_BUFSZ					0x0000045b
Line 338... Line -...
338 
 
 - 
 
339 
#define REG_A2XX_CP_STAT					0x0000047f
 - 
 
340 
 
 - 
 
341 
#define REG_A2XX_SCRATCH_REG0					0x00000578
 - 
 
342 
 
 290 
 
- 
 
 291 
#define REG_A2XX_CP_STAT					0x0000047f
- 
 
 292 
 
- 
 
 293 
#define REG_A2XX_RBBM_STATUS					0x000005d0
- 
 
 294 
#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK			0x0000001f
- 
 
 295 
#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT			0
- 
 
 296 
static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
- 
 
 297 
{
- 
 
 298 
	return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK;
- 
 
 299 
}
- 
 
 300 
#define A2XX_RBBM_STATUS_TC_BUSY				0x00000020
- 
 
 301 
#define A2XX_RBBM_STATUS_HIRQ_PENDING				0x00000100
- 
 
 302 
#define A2XX_RBBM_STATUS_CPRQ_PENDING				0x00000200
- 
 
 303 
#define A2XX_RBBM_STATUS_CFRQ_PENDING				0x00000400
- 
 
 304 
#define A2XX_RBBM_STATUS_PFRQ_PENDING				0x00000800
- 
 
 305 
#define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA			0x00001000
- 
 
 306 
#define A2XX_RBBM_STATUS_RBBM_WU_BUSY				0x00004000
- 
 
 307 
#define A2XX_RBBM_STATUS_CP_NRT_BUSY				0x00010000
- 
 
 308 
#define A2XX_RBBM_STATUS_MH_BUSY				0x00040000
- 
 
 309 
#define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY			0x00080000
- 
 
 310 
#define A2XX_RBBM_STATUS_SX_BUSY				0x00200000
- 
 
 311 
#define A2XX_RBBM_STATUS_TPC_BUSY				0x00400000
- 
 
 312 
#define A2XX_RBBM_STATUS_SC_CNTX_BUSY				0x01000000
- 
 
 313 
#define A2XX_RBBM_STATUS_PA_BUSY				0x02000000
- 
 
 314 
#define A2XX_RBBM_STATUS_VGT_BUSY				0x04000000
- 
 
 315 
#define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY				0x08000000
Line 343... Line 316...
343 
#define REG_A2XX_SCRATCH_REG2					0x0000057a
 316 
#define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY				0x10000000
344 
 
 317 
#define A2XX_RBBM_STATUS_RB_CNTX_BUSY				0x40000000
345 
#define REG_A2XX_RBBM_STATUS					0x000005d0
 318 
#define A2XX_RBBM_STATUS_GUI_ACTIVE				0x80000000
346 
 
 319 
 
Line 356... Line 329...
356 
static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
 329 
static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
357 
{
 330 
{
358 
	return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
 331 
	return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
359 
}
 332 
}
Line 360... Line 333...
360 
 
 333 
 
Line 361... Line 334...
361 
#define REG_A2XX_VSC_PIPE(i0)				       (0x00000c06 + 0x3*(i0))
 334 
static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
Line 362... Line 335...
362 
 
 335 
 
Line 363... Line 336...
363 
#define REG_A2XX_VSC_PIPE_CONFIG(i0)			       (0x00000c06 + 0x3*(i0))
 336 
static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
Line 364... Line 337...
364 
 
 337 
 
Line 365... Line 338...
365 
#define REG_A2XX_VSC_PIPE_DATA_ADDRESS(i0)		       (0x00000c07 + 0x3*(i0))
 338 
static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }