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Line 40... Line 40...
40
#include "sna_render_inline.h"
40
#include "sna_render_inline.h"
41
//#include "sna_video.h"
41
//#include "sna_video.h"
Line 42... Line 42...
42
 
42
 
43
#include "brw/brw.h"
43
#include "brw/brw.h"
-
 
44
#include "gen5_render.h"
44
#include "gen5_render.h"
45
#include "gen4_common.h"
45
#include "gen4_source.h"
46
#include "gen4_source.h"
Line 46... Line 47...
46
#include "gen4_vertex.h"
47
#include "gen4_vertex.h"
47
 
48
 
Line 717... Line 718...
717
static void
718
static void
718
gen5_align_vertex(struct sna *sna, const struct sna_composite_op *op)
719
gen5_align_vertex(struct sna *sna, const struct sna_composite_op *op)
719
{
720
{
720
	assert(op->floats_per_rect == 3*op->floats_per_vertex);
721
	assert(op->floats_per_rect == 3*op->floats_per_vertex);
721
	if (op->floats_per_vertex != sna->render_state.gen5.floats_per_vertex) {
722
	if (op->floats_per_vertex != sna->render_state.gen5.floats_per_vertex) {
722
		if (sna->render.vertex_size - sna->render.vertex_used < 2*op->floats_per_rect)
-
 
723
			gen4_vertex_finish(sna);
-
 
724
 
-
 
725
		DBG(("aligning vertex: was %d, now %d floats per vertex, %d->%d\n",
723
		DBG(("aligning vertex: was %d, now %d floats per vertex\n",
726
		     sna->render_state.gen5.floats_per_vertex,
724
		     sna->render_state.gen5.floats_per_vertex,
727
		     op->floats_per_vertex,
725
		     op->floats_per_vertex));
728
		     sna->render.vertex_index,
726
		gen4_vertex_align(sna, op);
729
		     (sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex));
-
 
730
		sna->render.vertex_index = (sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex;
-
 
731
		sna->render.vertex_used = sna->render.vertex_index * op->floats_per_vertex;
-
 
732
		sna->render_state.gen5.floats_per_vertex = op->floats_per_vertex;
727
		sna->render_state.gen5.floats_per_vertex = op->floats_per_vertex;
733
	}
728
	}
734
}
729
}
Line 735... Line 730...
735
 
730
 
Line 940... Line 935...
940
}
935
}
Line 941... Line 936...
941
 
936
 
942
inline static void
937
inline static void
943
gen5_emit_pipe_flush(struct sna *sna)
938
gen5_emit_pipe_flush(struct sna *sna)
-
 
939
{
944
{
940
#if 0
945
	OUT_BATCH(GEN5_PIPE_CONTROL | (4 - 2));
941
	OUT_BATCH(GEN5_PIPE_CONTROL | (4 - 2));
946
	OUT_BATCH(GEN5_PIPE_CONTROL_WC_FLUSH);
942
	OUT_BATCH(GEN5_PIPE_CONTROL_WC_FLUSH);
947
	OUT_BATCH(0);
943
	OUT_BATCH(0);
-
 
944
	OUT_BATCH(0);
-
 
945
#else
-
 
946
	OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
948
	OUT_BATCH(0);
947
#endif
Line 949... Line 948...
949
}
948
}
950
 
949
 
951
static void
950
static void
Line 1309... Line 1308...
1309
	tmp.floats_per_rect = 9;
1308
	tmp.floats_per_rect = 9;
1310
	tmp.priv = frame;
1309
	tmp.priv = frame;
Line 1311... Line 1310...
1311
 
1310
 
1312
	if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL)) {
1311
	if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL)) {
1313
		kgem_submit(&sna->kgem);
1312
		kgem_submit(&sna->kgem);
-
 
1313
		if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL))
1314
		assert(kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL));
1314
			return false;
Line 1315... Line -...
1315
	}
-
 
1316
 
1315
	}
-
 
1316
 
Line 1317... Line 1317...
1317
	gen5_video_bind_surfaces(sna, &tmp);
1317
	gen5_align_vertex(sna, &tmp);
1318
	gen5_align_vertex(sna, &tmp);
1318
	gen5_video_bind_surfaces(sna, &tmp);
1319
 
1319
 
1320
	/* Set up the offset for translating from the given region (in screen
1320
	/* Set up the offset for translating from the given region (in screen
Line 1450... Line 1450...
1450
		DBG(("%s: unhandled blend op %d\n", __FUNCTION__, op));
1450
		DBG(("%s: unhandled blend op %d\n", __FUNCTION__, op));
1451
		return false;
1451
		return false;
1452
	}
1452
	}
Line 1453... Line 1453...
1453
 
1453
 
1454
	if (mask == NULL &&
-
 
1455
	    try_blt(sna, dst, src, width, height) &&
1454
	if (mask == NULL &&
1456
	    sna_blt_composite(sna, op,
1455
	    sna_blt_composite(sna, op,
1457
			      src, dst,
1456
			      src, dst,
1458
			      src_x, src_y,
1457
			      src_x, src_y,
1459
			      dst_x, dst_y,
1458
			      dst_x, dst_y,
Line 1575... Line 1574...
1575
		if (!kgem_check_bo(&sna->kgem,
1574
		if (!kgem_check_bo(&sna->kgem,
1576
				   tmp->dst.bo, tmp->src.bo, tmp->mask.bo, NULL))
1575
				   tmp->dst.bo, tmp->src.bo, tmp->mask.bo, NULL))
1577
			goto cleanup_mask;
1576
			goto cleanup_mask;
1578
	}
1577
	}
Line 1579... Line -...
1579
 
-
 
1580
	gen5_bind_surfaces(sna, tmp);
1578
 
-
 
1579
	gen5_align_vertex(sna, tmp);
1581
	gen5_align_vertex(sna, tmp);
1580
	gen5_bind_surfaces(sna, tmp);
Line 1582... Line 1581...
1582
	return true;
1581
	return true;
1583
 
1582
 
1584
cleanup_mask:
1583
cleanup_mask:
Line 1804... Line 1803...
1804
				   tmp->base.dst.bo, tmp->base.src.bo,
1803
				   tmp->base.dst.bo, tmp->base.src.bo,
1805
				   NULL))
1804
				   NULL))
1806
			goto cleanup_src;
1805
			goto cleanup_src;
1807
	}
1806
	}
Line 1808... Line -...
1808
 
-
 
1809
	gen5_bind_surfaces(sna, &tmp->base);
1807
 
-
 
1808
	gen5_align_vertex(sna, &tmp->base);
1810
	gen5_align_vertex(sna, &tmp->base);
1809
	gen5_bind_surfaces(sna, &tmp->base);
Line 1811... Line 1810...
1811
	return true;
1810
	return true;
1812
 
1811
 
1813
cleanup_src:
1812
cleanup_src:
Line 1950... Line 1949...
1950
 
1949
 
1951
	if (!kgem_check_bo(&sna->kgem, dst_bo, src_bo, NULL)) {
1950
	if (!kgem_check_bo(&sna->kgem, dst_bo, src_bo, NULL)) {
1952
		kgem_submit(&sna->kgem);
1951
		kgem_submit(&sna->kgem);
1953
		if (!kgem_check_bo(&sna->kgem, dst_bo, src_bo, NULL)) {
1952
		if (!kgem_check_bo(&sna->kgem, dst_bo, src_bo, NULL)) {
-
 
1953
			DBG(("%s: aperture check failed\n", __FUNCTION__));
-
 
1954
			kgem_bo_destroy(&sna->kgem, tmp.src.bo);
-
 
1955
			if (tmp.redirect.real_bo)
1954
			DBG(("%s: aperture check failed\n", __FUNCTION__));
1956
				kgem_bo_destroy(&sna->kgem, tmp.dst.bo);
1955
			goto fallback_tiled_src;
1957
			goto fallback_blt;
1956
		}
1958
		}
Line 1957... Line 1959...
1957
	}
1959
	}
1958
 
1960
 
1959
	dst_dx += tmp.dst.x;
1961
	dst_dx += tmp.dst.x;
Line 1960... Line 1962...
1960
	dst_dy += tmp.dst.y;
1962
	dst_dy += tmp.dst.y;
1961
	tmp.dst.x = tmp.dst.y = 0;
1963
	tmp.dst.x = tmp.dst.y = 0;
Line 1962... Line -...
1962
 
-
 
1963
	src_dx += tmp.src.offset[0];
1964
 
-
 
1965
	src_dx += tmp.src.offset[0];
Line 1964... Line 1966...
1964
	src_dy += tmp.src.offset[1];
1966
	src_dy += tmp.src.offset[1];
1965
 
1967
 
Line 1966... Line 1968...
1966
	gen5_copy_bind_surfaces(sna, &tmp);
1968
	gen5_align_vertex(sna, &tmp);
Line 1997... Line 1999...
1997
	gen4_vertex_flush(sna);
1999
	gen4_vertex_flush(sna);
1998
	sna_render_composite_redirect_done(sna, &tmp);
2000
	sna_render_composite_redirect_done(sna, &tmp);
1999
	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
2001
	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
2000
	return true;
2002
	return true;
Line 2001... Line -...
2001
 
-
 
2002
fallback_tiled_src:
-
 
2003
	kgem_bo_destroy(&sna->kgem, tmp.src.bo);
2003
 
2004
fallback_tiled_dst:
2004
fallback_tiled_dst:
2005
	if (tmp.redirect.real_bo)
2005
	if (tmp.redirect.real_bo)
2006
		kgem_bo_destroy(&sna->kgem, tmp.dst.bo);
2006
		kgem_bo_destroy(&sna->kgem, tmp.dst.bo);
2007
fallback_tiled:
2007
fallback_tiled:
Line 2019... Line 2019...
2019
				     dst, dst_bo, dst_dx, dst_dy,
2019
				     dst, dst_bo, dst_dx, dst_dy,
2020
				     box, n);
2020
				     box, n);
2021
}
2021
}
Line 2022... Line 2022...
2022
 
2022
 
2023
#endif
-
 
2024
 
-
 
2025
static void
-
 
2026
gen5_render_flush(struct sna *sna)
-
 
2027
{
-
 
2028
	gen4_vertex_close(sna);
-
 
2029
 
-
 
2030
	assert(sna->render.vb_id == 0);
-
 
2031
	assert(sna->render.vertex_offset == 0);
-
 
2032
}
-
 
2033
 
2023
#endif
2034
static void
2024
static void
2035
gen5_render_context_switch(struct kgem *kgem,
2025
gen5_render_context_switch(struct kgem *kgem,
2036
			   int new_mode)
2026
			   int new_mode)
2037
{
2027
{
Line 2058... Line 2048...
2058
		DBG(("%s: GPU idle, flushing\n", __FUNCTION__));
2048
		DBG(("%s: GPU idle, flushing\n", __FUNCTION__));
2059
		_kgem_submit(kgem);
2049
		_kgem_submit(kgem);
2060
	}
2050
	}
2061
}
2051
}
Line 2062... Line -...
2062
 
-
 
2063
static void
-
 
2064
discard_vbo(struct sna *sna)
-
 
2065
{
-
 
2066
	kgem_bo_destroy(&sna->kgem, sna->render.vbo);
-
 
2067
	sna->render.vbo = NULL;
-
 
2068
	sna->render.vertices = sna->render.vertex_data;
-
 
2069
	sna->render.vertex_size = ARRAY_SIZE(sna->render.vertex_data);
-
 
2070
	sna->render.vertex_used = 0;
-
 
2071
	sna->render.vertex_index = 0;
-
 
2072
}
-
 
2073
 
-
 
2074
static void
-
 
2075
gen5_render_retire(struct kgem *kgem)
-
 
2076
{
-
 
2077
	struct sna *sna;
-
 
2078
 
-
 
2079
	sna = container_of(kgem, struct sna, kgem);
-
 
2080
	if (kgem->nbatch == 0 && sna->render.vbo && !kgem_bo_is_busy(sna->render.vbo)) {
-
 
2081
		DBG(("%s: resetting idle vbo\n", __FUNCTION__));
-
 
2082
		sna->render.vertex_used = 0;
-
 
2083
		sna->render.vertex_index = 0;
-
 
2084
	}
-
 
2085
}
-
 
2086
 
-
 
2087
static void
-
 
2088
gen5_render_expire(struct kgem *kgem)
-
 
2089
{
-
 
2090
	struct sna *sna;
-
 
2091
 
-
 
2092
	sna = container_of(kgem, struct sna, kgem);
-
 
2093
	if (sna->render.vbo && !sna->render.vertex_used) {
-
 
2094
		DBG(("%s: discarding vbo\n", __FUNCTION__));
-
 
2095
		discard_vbo(sna);
-
 
2096
	}
-
 
2097
}
-
 
2098
 
2052
 
2099
static void gen5_render_reset(struct sna *sna)
2053
static void gen5_render_reset(struct sna *sna)
2100
{
2054
{
2101
	sna->render_state.gen5.needs_invariant = true;
2055
	sna->render_state.gen5.needs_invariant = true;
2102
	sna->render_state.gen5.ve_id = -1;
2056
	sna->render_state.gen5.ve_id = -1;
Line 2105... Line 2059...
2105
 
2059
 
2106
	sna->render_state.gen5.drawrect_offset = -1;
2060
	sna->render_state.gen5.drawrect_offset = -1;
2107
	sna->render_state.gen5.drawrect_limit = -1;
2061
	sna->render_state.gen5.drawrect_limit = -1;
Line 2108... Line -...
2108
	sna->render_state.gen5.surface_table = -1;
-
 
2109
 
2062
	sna->render_state.gen5.surface_table = -1;
2110
	if (sna->render.vbo &&
2063
 
2111
	    !kgem_bo_is_mappable(&sna->kgem, sna->render.vbo)) {
2064
	if (sna->render.vbo && !kgem_bo_can_map(&sna->kgem, sna->render.vbo)) {
2112
		DBG(("%s: discarding unmappable vbo\n", __FUNCTION__));
2065
		DBG(("%s: discarding unmappable vbo\n", __FUNCTION__));
Line 2113... Line 2066...
2113
		discard_vbo(sna);
2066
		discard_vbo(sna);
Line 2349... Line 2302...
2349
{
2302
{
2350
	if (!gen5_render_setup(sna))
2303
	if (!gen5_render_setup(sna))
2351
		return backend;
2304
		return backend;
Line 2352... Line 2305...
2352
 
2305
 
2353
	sna->kgem.context_switch = gen5_render_context_switch;
2306
	sna->kgem.context_switch = gen5_render_context_switch;
2354
	sna->kgem.retire = gen5_render_retire;
2307
	sna->kgem.retire = gen4_render_retire;
Line 2355... Line 2308...
2355
	sna->kgem.expire = gen5_render_expire;
2308
	sna->kgem.expire = gen4_render_expire;
2356
 
2309
 
2357
#if 0
2310
#if 0
2358
#if !NO_COMPOSITE
2311
#if !NO_COMPOSITE
2359
	sna->render.composite = gen5_render_composite;
2312
	sna->render.composite = gen5_render_composite;
2360
	sna->render.prefer_gpu |= PREFER_GPU_RENDER;
2313
	sna->render.prefer_gpu |= PREFER_GPU_RENDER;
2361
#endif
2314
#endif
2362
#if !NO_COMPOSITE_SPANS
2315
#if !NO_COMPOSITE_SPANS
2363
	sna->render.check_composite_spans = gen5_check_composite_spans;
2316
	sna->render.check_composite_spans = gen5_check_composite_spans;
2364
	sna->render.composite_spans = gen5_render_composite_spans;
2317
	sna->render.composite_spans = gen5_render_composite_spans;
2365
	if (sna->PciInfo->device_id == 0x0044)
2318
	if (intel_get_device_id(sna->scrn) == 0x0044)
2366
		sna->render.prefer_gpu |= PREFER_GPU_SPANS;
2319
		sna->render.prefer_gpu |= PREFER_GPU_SPANS;
Line 2367... Line 2320...
2367
#endif
2320
#endif
Line 2376... Line 2329...
2376
#endif
2329
#endif
Line 2377... Line 2330...
2377
 
2330
 
2378
    sna->render.blit_tex = gen5_blit_tex;
2331
    sna->render.blit_tex = gen5_blit_tex;
Line 2379... Line 2332...
2379
    sna->render.caps = HW_BIT_BLIT | HW_TEX_BLIT;
2332
    sna->render.caps = HW_BIT_BLIT | HW_TEX_BLIT;
2380
 
2333
 
2381
	sna->render.flush = gen5_render_flush;
2334
	sna->render.flush = gen4_render_flush;
Line 2382... Line 2335...
2382
	sna->render.reset = gen5_render_reset;
2335
	sna->render.reset = gen5_render_reset;
2383
	sna->render.fini = gen5_render_fini;
2336
	sna->render.fini = gen5_render_fini;
Line 2464... Line 2417...
2464
	if (!kgem_check_bo(&sna->kgem,
2417
	if (!kgem_check_bo(&sna->kgem,
2465
			   tmp->dst.bo, tmp->src.bo, tmp->mask.bo, NULL)) {
2418
			   tmp->dst.bo, tmp->src.bo, tmp->mask.bo, NULL)) {
2466
		kgem_submit(&sna->kgem);
2419
		kgem_submit(&sna->kgem);
2467
	}
2420
	}
Line 2468... Line -...
2468
 
-
 
2469
	gen5_bind_surfaces(sna, tmp);
2421
 
2470
	gen5_align_vertex(sna, tmp);
2422
	gen5_align_vertex(sna, tmp);
Line -... Line 2423...
-
 
2423
	gen5_bind_surfaces(sna, tmp);
2471
	return true;
2424