WebSVN – Kolibri OS – Diff – /programs/system/drivers/ati2d/r500.inc

 #	define RADEON_ISYNC_CPSCRATCH_IDLEGUI	(1 << 5)
 #define R5XX_LOOP_COUNT 2000000
-#include "microcode.h"
 #define RADEON_CLOCK_CNTL_DATA              0x000c
 #define RADEON_CLOCK_CNTL_INDEX             0x0008
 #       define R300_DISABLE_MC_MCLKA        (1 << 21)
 #       define R300_DISABLE_MC_MCLKB        (1 << 21)
-void RADEONPllErrataAfterData()
-{
-    /* This function is required to workaround a hardware bug in some (all?)
-     * revisions of the R300.  This workaround should be called after every
-     * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
-     * may not be correct.
-     */
-    if (rhd.ChipFamily <= CHIP_FAMILY_RV380)
-    {
-        u32_t save, tmp;
-	save = INREG(RADEON_CLOCK_CNTL_INDEX);
-	tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
-	OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
-	tmp = INREG(RADEON_CLOCK_CNTL_DATA);
-	OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
-    }
-}
-/* Read PLL register */
-u32_t RADEONINPLL(int addr)
-{
-    u32_t       data;
-    OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
-    //RADEONPllErrataAfterIndex();
-    data = INREG(RADEON_CLOCK_CNTL_DATA);
-    RADEONPllErrataAfterData();
-    return data;
-};
-/* Write PLL information */
-void RADEONOUTPLL(int addr, u32_t data)
-{
-    OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) |
-				      RADEON_PLL_WR_EN));
-//    RADEONPllErrataAfterIndex(info);
-    OUTREG(RADEON_CLOCK_CNTL_DATA, data);
-    RADEONPllErrataAfterData();
-}
-static Bool
-R5xxFIFOWaitLocal(u32_t required)             //R100-R500
-{
-  int i;
-  for (i = 0; i < R5XX_LOOP_COUNT; i++)
-    if (required <= (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK))
-	    return TRUE;
-  dbgprintf("%s: Timeout 0x%08X.\n", __func__,
-         (unsigned int) INREG(R5XX_RBBM_STATUS));
   return FALSE;
     return FALSE;
+}
-static void
-R5xx2DReset()
-{
-    u32_t save, tmp;
-    u32_t       clock_cntl_index;
-    u32_t       mclk_cntl;
-      /* The following RBBM_SOFT_RESET sequence can help un-wedge
-       * an R300 after the command processor got stuck. */
-    save = INREG(R5XX_RBBM_SOFT_RESET);
-    tmp = save | R5XX_SOFT_RESET_CP |
-      R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_SE |
-      R5XX_SOFT_RESET_RE | R5XX_SOFT_RESET_PP |
-      R5XX_SOFT_RESET_E2 | R5XX_SOFT_RESET_RB;
-    OUTREG(R5XX_RBBM_SOFT_RESET, tmp);
-    INREG(R5XX_RBBM_SOFT_RESET);
-    tmp &= ~(R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI |
-         R5XX_SOFT_RESET_SE | R5XX_SOFT_RESET_RE |
-         R5XX_SOFT_RESET_PP | R5XX_SOFT_RESET_E2 |
-         R5XX_SOFT_RESET_RB);
-    OUTREG(R5XX_RBBM_SOFT_RESET, tmp);
-    INREG(R5XX_RBBM_SOFT_RESET);
-    OUTREG(R5XX_RBBM_SOFT_RESET, save);
-    INREG(R5XX_RBBM_SOFT_RESET);
-    R5xx2DFlush();
-#if 0
-    clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
-    RADEONPllErrataAfterIndex(info);
-    mclk_cntl = RADEONINPLL(RADEON_MCLK_CNTL);
-    RADEONOUTPLL(RADEON_MCLK_CNTL, (mclk_cntl |
-			      RADEON_FORCEON_MCLKA |
-			      RADEON_FORCEON_MCLKB |
-			      RADEON_FORCEON_YCLKA |
-			      RADEON_FORCEON_YCLKB |
-			      RADEON_FORCEON_MC |
-			      RADEON_FORCEON_AIC));
-#endif
-      /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
-       * unexpected behaviour on some machines.  Here we use
-       * R5XX_HOST_PATH_CNTL to reset it. */
-    save = INREG(R5XX_HOST_PATH_CNTL);
-    tmp = INREG(R5XX_RBBM_SOFT_RESET);
-    tmp |= R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_E2;
-    OUTREG(R5XX_RBBM_SOFT_RESET, tmp);
-    INREG(R5XX_RBBM_SOFT_RESET);
-    OUTREG(R5XX_RBBM_SOFT_RESET, 0);
-    MASKREG(R5XX_RB2D_DSTCACHE_MODE,
-	       R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE,
-	       R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE);
-    OUTREG(R5XX_HOST_PATH_CNTL, save | R5XX_HDP_SOFT_RESET);
-    INREG(R5XX_HOST_PATH_CNTL);
-    OUTREG(R5XX_HOST_PATH_CNTL, save);
-#if 0
-    OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
-    RADEONPllErrataAfterIndex(info);
-    RADEONOUTPLL(RADEON_MCLK_CNTL, mclk_cntl);
-#endif
 void
     MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);
     OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl);
+    R5xxFIFOWaitLocal(3);
+    OUTREG(R5XX_SC_TOP_LEFT, 0);
+    OUTREG(R5XX_SC_BOTTOM_RIGHT,
-    R5xxFIFOWaitLocal(1);
+           RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
     OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT,
+           RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
            R5XX_DEFAULT_SC_RIGHT_MAX | R5XX_DEFAULT_SC_BOTTOM_MAX);
     R5xxFIFOWaitLocal(1);
-    OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control |
+//    OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control |
+//           R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR);
-           R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR);
+    OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM);
     R5xxFIFOWaitLocal(5);
     OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF);
 void R5xxFIFOWait(u32_t required)
+{
     if (!R5xxFIFOWaitLocal(required)) {
-      R5xx2DReset();
+ //     R5xx2DReset();
       R5xx2DSetup();
+    }
+}
 void R5xx2DIdle()
+{
     if (!R5xx2DIdleLocal()) {
-      R5xx2DReset();
+  //    R5xx2DReset();
       R5xx2DSetup();
+    }
-}
-static void load_microcode()
-{
-  u32_t ifl;
-  int i;
-  ifl = safe_cli();
-  OUTREG(RADEON_CP_ME_RAM_ADDR,0);
-  R5xx2DIdleLocal();
-  switch(rhd.ChipFamily)
-  {
-    case CHIP_FAMILY_R300:
-    case CHIP_FAMILY_R350:
-    case CHIP_FAMILY_RV350:
-      dbgprintf("Loading R300 microcode\n");
-      for (i = 0; i < 256; i++)
-      {
-        OUTREG(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
-        OUTREG(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
-      }
-      break;
-/*
-    case RHD_RV505:
-    case RHD_RV515:
-    case RHD_RV516:
-    case RHD_R520:
-    case RHD_RV530:
-    case RHD_RV535:
-    case RHD_RV550:
-    case RHD_RV560:
-    case RHD_RV570:
-    case RHD_R580:
-      dbgprintf("Loading R500 microcode\n");
-      for (i = 0; i < 256; i++)
-      {
-        OUTREG(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
-        OUTREG(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
-      }
-*/
-  }
   safe_sti(ifl);
 };
     clip.ymin = 0;
     clip.xmax = rhd.displayWidth  - 1;
     clip.ymax = rhd.displayHeight - 1;
-    dbgprintf("width  %d \n", rhd.displayWidth);
+    dbgprintf("screen width  %d height %d\n",
-    dbgprintf("height %d \n", rhd.displayHeight);
+               rhd.displayWidth, rhd.displayHeight);
+    rhd.gui_control = ((6 << RADEON_GMC_DST_DATATYPE_SHIFT)
-    rhd.gui_control = (R5XX_DATATYPE_ARGB8888 << R5XX_GMC_DST_DATATYPE_SHIFT) |
+                      | RADEON_GMC_CLR_CMP_CNTL_DIS
-                       R5XX_GMC_CLR_CMP_CNTL_DIS | R5XX_GMC_DST_PITCH_OFFSET_CNTL;
+                      | RADEON_GMC_DST_PITCH_OFFSET_CNTL);
     dbgprintf("gui_control %x \n", rhd.gui_control);
+    rhd.surface_cntl = 0;
+//    rhd.dst_pitch_offset = ((screenpitch / 64) << 22) | (rhd.fbLocation >> 10);
-    rhd.surface_cntl = 0;
+    rhd.dst_pitch_offset = (((rhd.displayWidth * 4 / 64)<< 22) |
-    rhd.dst_pitch_offset = ((screenpitch / 64) << 22) | (rhd.fbLocation >> 10);
+                               (rhd.fbLocation  >> 10));
     dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset);
     dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset);
     scr_pixmap.width  = rhd.displayWidth;
+    scr_pixmap.height = rhd.displayHeight;
+    scr_pixmap.format = PICT_a8r8g8b8;
+    scr_pixmap.pitch  = screenpitch;
-    scr_pixmap.height = rhd.displayHeight;
-    scr_pixmap.format = PICT_a8r8g8b8;
-    scr_pixmap.pitch  = screenpitch;
-    scr_pixmap.local  = (void*)rhd.fbLocation;
-    scr_pixmap.pitch_offset =  rhd.dst_pitch_offset;
-    scr_pixmap.mapped = (void*)0;
-    MASKREG(R5XX_GB_TILE_CONFIG, 0, R5XX_ENABLE_TILING);
+    scr_pixmap.local  = (void*)rhd.fbLocation;
-    OUTREG (R5XX_WAIT_UNTIL, R5XX_WAIT_2D_IDLECLEAN | R5XX_WAIT_3D_IDLECLEAN);
-    MASKREG(R5XX_DST_PIPE_CONFIG, R5XX_PIPE_AUTO_CONFIG, R5XX_PIPE_AUTO_CONFIG);
-    MASKREG(R5XX_RB2D_DSTCACHE_MODE,
+    scr_pixmap.pitch_offset =  rhd.dst_pitch_offset;
-            R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE,
-            R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE);
-    R5xx2DReset();
-    R5xx2DSetup();
-    MASKREG( RADEON_AIC_CNTL,0, RADEON_PCIGART_TRANSLATE_EN);
-  //  load_microcode();
- //   rhd.ring_base = CreateRingBuffer(0x8000, PG_SW | PG_NOCACHE);
- //   dbgprintf("create cp ring buffer %x\n", rhd.ring_base);
- //   base = GetPgAddr(rhd.ring_base);
- //   OUTREG(RADEON_CP_RB_BASE, base);
- //   dbgprintf("ring base %x\n", base);
- //   OUTREG(RADEON_CP_RB_WPTR_DELAY, 0);
- //   rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR);
- //   OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp);
+    scr_pixmap.mapped = (void*)0;
- //   OUTREG(RADEON_CP_RB_RPTR_ADDR, 0); // ring buffer read pointer no update
+    R5xxFIFOWaitLocal(2);
- //   OUTREG(RADEON_CP_RB_CNTL, RADEON_RB_NO_UPDATE | 12);
+    OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);
+    OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset);
- //   OUTREG(RADEON_SCRATCH_UMSK, 0);          // no scratch update
     R5xxFIFOWaitLocal(1);

Subversion Repositories Kolibri OS

(root)/programs/system/drivers/ati2d/r500.inc – Rev 881 → 883