Rev 812 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 812 | Rev 813 | ||
|---|---|---|---|
| Line 5... | Line 5... | ||
| 5 | #define FINISH_ACCEL() COMMIT_RING() |
5 | #define FINISH_ACCEL() COMMIT_RING() |
| 6 | 6 | ||
| Line 7... | Line 7... | ||
| 7 | #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) |
7 | #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) |
| Line -... | Line 8... | ||
| - | 8 | ||
| - | 9 | #define RADEON_SWITCH_TO_3D() \ |
|
| - | 10 | do { \ |
|
| - | 11 | u32_t wait_until = 0; \ |
|
| - | 12 | BEGIN_ACCEL(1); \ |
|
| - | 13 | wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ |
|
| - | 14 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ |
|
| - | 15 | FINISH_ACCEL(); \ |
|
| - | 16 | } while (0); |
|
| - | 17 | ||
| 8 | 18 | ||
| - | 19 | struct blendinfo { |
|
| - | 20 | Bool dst_alpha; |
|
| - | 21 | Bool src_alpha; |
|
| - | 22 | u32_t blend_cntl; |
|
| - | 23 | }; |
|
| - | 24 | ||
| - | 25 | static struct blendinfo RadeonBlendOp[] = { |
|
| - | 26 | /* 0 - Clear */ |
|
| - | 27 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO}, |
|
| - | 28 | /* 1 - Src */ |
|
| - | 29 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO}, |
|
| - | 30 | /* 2 - Dst */ |
|
| - | 31 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE}, |
|
| - | 32 | /* 3 - Over */ |
|
| - | 33 | {0, 1, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
|
| - | 34 | /* 4 - OverReverse */ |
|
| - | 35 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE}, |
|
| - | 36 | /* 5 - In */ |
|
| 9 | #define IS_R300_3D 0 |
37 | {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
| - | 38 | /* 6 - InReverse */ |
|
| - | 39 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
|
| - | 40 | /* 7 - Out */ |
|
| - | 41 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
|
| - | 42 | /* 8 - OutReverse */ |
|
| - | 43 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
|
| - | 44 | /* 9 - Atop */ |
|
| - | 45 | {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
|
| - | 46 | /* 10- AtopReverse */ |
|
| - | 47 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
|
| - | 48 | /* 11 - Xor */ |
|
| - | 49 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
|
| - | 50 | /* 12 - Add */ |
|
| - | 51 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE}, |
|
| Line 10... | Line 52... | ||
| 10 | #define IS_R500_3D 1 |
52 | }; |
| 11 | 53 | ||
| 12 | 54 | ||
| Line 19... | Line 61... | ||
| 19 | u32 *ring, write; |
61 | u32 *ring, write; |
| Line 20... | Line 62... | ||
| 20 | 62 | ||
| Line 21... | Line 63... | ||
| 21 | // info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; |
63 | // info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; |
| - | 64 | ||
| Line 22... | Line 65... | ||
| 22 | 65 | if (IS_R300_3D || IS_R500_3D) |
|
| 23 | if (IS_R300_3D || IS_R500_3D) { |
66 | { |
| 24 | 67 | ||
| 25 | BEGIN_ACCEL(3); |
68 | BEGIN_ACCEL(3); |
| 26 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
69 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
| Line -... | Line 70... | ||
| - | 70 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
|
| - | 71 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
|
| - | 72 | FINISH_ACCEL(); |
|
| - | 73 | ||
| - | 74 | if ( IS_R500_3D) |
|
| - | 75 | { |
|
| - | 76 | u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
|
| - | 77 | ||
| - | 78 | rhdPtr->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
|
| - | 79 | RADEONOUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
|
| 27 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
80 | } |
| Line 28... | Line 81... | ||
| 28 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
81 | |
| 29 | FINISH_ACCEL(); |
82 | dbgprintf("Pipes count %d\n", rhdPtr->num_gb_pipes ); |
| 30 | 83 | ||
| Line 626... | Line 679... | ||
| 626 | } |
679 | } |
| 627 | 680 | ||
| Line 628... | Line 681... | ||
| 628 | } |
681 | } |
| Line -... | Line 682... | ||
| - | 682 | ||
| - | 683 | static Bool R300TextureSetup(int w, int h, int unit) |
|
| - | 684 | { |
|
| - | 685 | //RINFO_FROM_SCREEN(pPix->drawable.pScreen); |
|
| - | 686 | u32_t txfilter, txformat0, txformat1, txoffset, txpitch; |
|
| - | 687 | // int w = pPict->pDrawable->width; |
|
| - | 688 | // int h = pPict->pDrawable->height; |
|
| - | 689 | int i, pixel_shift; |
|
| - | 690 | ||
| - | 691 | //ACCEL_PREAMBLE(); |
|
| - | 692 | ||
| - | 693 | //TRACE; |
|
| - | 694 | ||
| - | 695 | //txpitch = exaGetPixmapPitch(pPix); |
|
| - | 696 | txpitch = rhd.displayWidth * 4; |
|
| - | 697 | ||
| - | 698 | // txoffset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset; |
|
| - | 699 | txoffset = rhd.FbIntAddress + rhd.FbScanoutStart; |
|
| - | 700 | ||
| - | 701 | if ((txoffset & 0x1f) != 0) |
|
| - | 702 | dbgprintf("Bad texture offset 0x%x\n", (int)txoffset); |
|
| - | 703 | if ((txpitch & 0x1f) != 0) |
|
| - | 704 | dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch); |
|
| - | 705 | ||
| - | 706 | /* TXPITCH = pixels (texels) per line - 1 */ |
|
| - | 707 | pixel_shift = 32 >> 4; |
|
| - | 708 | txpitch >>= pixel_shift; |
|
| - | 709 | txpitch -= 1; |
|
| - | 710 | ||
| - | 711 | // if (RADEONPixmapIsColortiled(pPix)) |
|
| - | 712 | // txoffset |= R300_MACRO_TILE; |
|
| - | 713 | ||
| - | 714 | // for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++) |
|
| - | 715 | // { |
|
| - | 716 | // if (R300TexFormats[i].fmt == pPict->format) |
|
| - | 717 | // break; |
|
| - | 718 | // } |
|
| - | 719 | ||
| - | 720 | //txformat1 = R300TexFormats[i].card_fmt; |
|
| - | 721 | txformat1 = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); |
|
| - | 722 | ||
| - | 723 | txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | |
|
| - | 724 | (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT)); |
|
| - | 725 | ||
| - | 726 | if (IS_R500_3D && ((w - 1) & 0x800)) |
|
| - | 727 | txpitch |= R500_TXWIDTH_11; |
|
| - | 728 | ||
| - | 729 | if (IS_R500_3D && ((h - 1) & 0x800)) |
|
| - | 730 | txpitch |= R500_TXHEIGHT_11; |
|
| - | 731 | ||
| - | 732 | /* Use TXPITCH instead of TXWIDTH for address computations: we could |
|
| - | 733 | * omit this if there is no padding, but there is no apparent advantage |
|
| - | 734 | * in doing so. |
|
| - | 735 | */ |
|
| - | 736 | txformat0 |= R300_TXPITCH_EN; |
|
| - | 737 | ||
| - | 738 | // info->texW[unit] = w; |
|
| - | 739 | // info->texH[unit] = h; |
|
| - | 740 | ||
| - | 741 | // if (pPict->repeat && !(unit == 0 && need_src_tile_x)) |
|
| - | 742 | // txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP); |
|
| - | 743 | // else |
|
| - | 744 | txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL); |
|
| - | 745 | ||
| - | 746 | // if (pPict->repeat && !(unit == 0 && need_src_tile_y)) |
|
| - | 747 | // txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP); |
|
| - | 748 | // else |
|
| - | 749 | txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); |
|
| - | 750 | ||
| - | 751 | txfilter |= (unit << R300_TX_ID_SHIFT); |
|
| - | 752 | ||
| - | 753 | // switch (pPict->filter) { |
|
| - | 754 | // case PictFilterNearest: |
|
| - | 755 | txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST); |
|
| - | 756 | // break; |
|
| - | 757 | // case PictFilterBilinear: |
|
| - | 758 | // txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR); |
|
| - | 759 | // break; |
|
| - | 760 | // default: |
|
| - | 761 | // RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); |
|
| - | 762 | // } |
|
| - | 763 | ||
| - | 764 | { |
|
| - | 765 | u32_t *ring, write; |
|
| - | 766 | ||
| - | 767 | BEGIN_ACCEL(7); |
|
| - | 768 | OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter); |
|
| - | 769 | OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0); |
|
| - | 770 | OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0); |
|
| - | 771 | OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1); |
|
| - | 772 | OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch); |
|
| - | 773 | OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset); |
|
| - | 774 | // if (!pPict->repeat) |
|
| - | 775 | OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); |
|
| - | 776 | FINISH_ACCEL(); |
|
| - | 777 | } |
|
| - | 778 | // if (pPict->transform != 0) { |
|
| - | 779 | // is_transform[unit] = TRUE; |
|
| - | 780 | // transform[unit] = pPict->transform; |
|
| - | 781 | // } else { |
|
| - | 782 | // is_transform[unit] = FALSE; |
|
| - | 783 | // } |
|
| - | 784 | ||
| - | 785 | return TRUE; |
|
| - | 786 | } |
|
| - | 787 | ||
| - | 788 | static u32_t RADEONGetBlendCntl(int op, u32_t dst_format) |
|
| - | 789 | { |
|
| - | 790 | u32_t sblend, dblend; |
|
| - | 791 | ||
| - | 792 | sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK; |
|
| Line -... | Line 793... | ||
| - | 793 | dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK; |
|
| - | 794 | ||
| - | 795 | /* If there's no dst alpha channel, adjust the blend op so that we'll treat |
|
| - | 796 | * it as always 1. |
|
| - | 797 | */ |
|
| - | 798 | if (PICT_FORMAT_A(dst_format) == 0 && RadeonBlendOp[op].dst_alpha) { |
|
| - | 799 | if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA) |
|
| - | 800 | sblend = RADEON_SRC_BLEND_GL_ONE; |
|
| - | 801 | else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) |
|
| - | 802 | sblend = RADEON_SRC_BLEND_GL_ZERO; |
|
| - | 803 | } |
|
| - | 804 | ||
| - | 805 | return sblend | dblend; |
|
| - | 806 | } |
|
| - | 807 | ||
| - | 808 | static Bool R300PrepareComposite(int op, int srcX, int srcY, |
|
| - | 809 | int dstX, int dstY, |
|
| - | 810 | int w, int h) |
|
| - | 811 | { |
|
| - | 812 | // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
|
| - | 813 | u32_t dst_format, dst_offset, dst_pitch; |
|
| - | 814 | u32_t txenable, colorpitch; |
|
| - | 815 | u32_t blendcntl; |
|
| - | 816 | int pixel_shift; |
|
| - | 817 | u32_t *ring, write; |
|
| - | 818 | ||
| - | 819 | //ACCEL_PREAMBLE(); |
|
| - | 820 | ||
| - | 821 | //TRACE; |
|
| - | 822 | ||
| - | 823 | //if (!info->XInited3D) |
|
| - | 824 | // RADEONInit3DEngine(pScrn); |
|
| - | 825 | ||
| - | 826 | //if (!R300GetDestFormat(pDstPicture, &dst_format)) |
|
| - | 827 | // return FALSE; |
|
| - | 828 | dst_format = R300_COLORFORMAT_ARGB8888; |
|
| - | 829 | ||
| - | 830 | pixel_shift = 32 >> 4; |
|
| - | 831 | ||
| - | 832 | //dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; |
|
| - | 833 | dst_offset = rhd.FbIntAddress + rhd.FbScanoutStart; |
|
| - | 834 | ||
| - | 835 | //dst_pitch = exaGetPixmapPitch(pDst); |
|
| - | 836 | dst_pitch = rhd.displayWidth * 4; |
|
| - | 837 | colorpitch = dst_pitch >> pixel_shift; |
|
| - | 838 | ||
| - | 839 | // if (RADEONPixmapIsColortiled(pDst)) |
|
| - | 840 | // colorpitch |= R300_COLORTILE; |
|
| - | 841 | ||
| - | 842 | colorpitch |= dst_format; |
|
| - | 843 | ||
| - | 844 | if ((dst_offset & 0x0f) != 0) |
|
| - | 845 | dbgprintf("Bad destination offset 0x%x\n", (int)dst_offset); |
|
| - | 846 | if (((dst_pitch >> pixel_shift) & 0x7) != 0) |
|
| - | 847 | dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch); |
|
| - | 848 | ||
| - | 849 | // if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE)) |
|
| - | 850 | // return FALSE; |
|
| - | 851 | ||
| - | 852 | if (!R300TextureSetup(w, h, 0)) |
|
| - | 853 | return FALSE; |
|
| - | 854 | ||
| - | 855 | txenable = R300_TEX_0_ENABLE; |
|
| - | 856 | ||
| - | 857 | // RADEON_SWITCH_TO_3D(); |
|
| - | 858 | ||
| - | 859 | /* setup the VAP */ |
|
| - | 860 | BEGIN_ACCEL(7); |
|
| - | 861 | ||
| - | 862 | /* These registers define the number, type, and location of data submitted |
|
| - | 863 | * to the PVS unit of GA input (when PVS is disabled) |
|
| - | 864 | * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is |
|
| - | 865 | * enabled. This memory provides the imputs to the vertex shader program |
|
| - | 866 | * and ordering is not important. When PVS/TCL is disabled, this field maps |
|
| - | 867 | * directly to the GA input memory and the order is signifigant. In |
|
| - | 868 | * PVS_BYPASS mode the order is as follows: |
|
| - | 869 | * Position |
|
| - | 870 | * Point Size |
|
| - | 871 | * Color 0-3 |
|
| - | 872 | * Textures 0-7 |
|
| - | 873 | * Fog |
|
| - | 874 | */ |
|
| - | 875 | ||
| - | 876 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, |
|
| - | 877 | ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | |
|
| - | 878 | (0 << R300_SKIP_DWORDS_0_SHIFT) | |
|
| - | 879 | (0 << R300_DST_VEC_LOC_0_SHIFT) | |
|
| - | 880 | R300_SIGNED_0 | |
|
| - | 881 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | |
|
| - | 882 | (0 << R300_SKIP_DWORDS_1_SHIFT) | |
|
| - | 883 | (6 << R300_DST_VEC_LOC_1_SHIFT) | |
|
| - | 884 | R300_LAST_VEC_1 | |
|
| - | 885 | R300_SIGNED_1)); |
|
| - | 886 | ||
| - | 887 | /* load the vertex shader |
|
| - | 888 | * We pre-load vertex programs in RADEONInit3DEngine(): |
|
| - | 889 | * - exa no mask |
|
| - | 890 | * - exa mask |
|
| - | 891 | * - Xv |
|
| - | 892 | * Here we select the offset of the vertex program we want to use |
|
| - | 893 | */ |
|
| - | 894 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, |
|
| - | 895 | ((3 << R300_PVS_FIRST_INST_SHIFT) | |
|
| - | 896 | (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | |
|
| - | 897 | (4 << R300_PVS_LAST_INST_SHIFT))); |
|
| - | 898 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, |
|
| - | 899 | (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); |
|
| - | 900 | ||
| - | 901 | /* Position and one or two sets of 2 texture coordinates */ |
|
| - | 902 | OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); |
|
| - | 903 | OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); |
|
| - | 904 | ||
| - | 905 | OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); |
|
| - | 906 | OUT_ACCEL_REG(R300_TX_ENABLE, txenable); |
|
| - | 907 | FINISH_ACCEL(); |
|
| - | 908 | ||
| - | 909 | /* setup pixel shader */ |
|
| - | 910 | if (IS_R300_3D) { |
|
| - | 911 | } else { |
|
| - | 912 | u32_t output_fmt; |
|
| - | 913 | u32_t src_color, src_alpha; |
|
| - | 914 | u32_t mask_color, mask_alpha; |
|
| - | 915 | ||
| - | 916 | if (PICT_FORMAT_RGB(PICT_a8r8g8b8) == 0) |
|
| - | 917 | src_color = (R500_ALU_RGB_R_SWIZ_A_0 | |
|
| - | 918 | R500_ALU_RGB_G_SWIZ_A_0 | |
|
| - | 919 | R500_ALU_RGB_B_SWIZ_A_0); |
|
| - | 920 | else |
|
| - | 921 | src_color = (R500_ALU_RGB_R_SWIZ_A_R | |
|
| - | 922 | R500_ALU_RGB_G_SWIZ_A_G | |
|
| - | 923 | R500_ALU_RGB_B_SWIZ_A_B); |
|
| - | 924 | ||
| - | 925 | if (PICT_FORMAT_A(PICT_a8r8g8b8) == 0) |
|
| - | 926 | src_alpha = R500_ALPHA_SWIZ_A_1; |
|
| - | 927 | else |
|
| - | 928 | src_alpha = R500_ALPHA_SWIZ_A_A; |
|
| - | 929 | ||
| - | 930 | mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | |
|
| - | 931 | R500_ALU_RGB_G_SWIZ_B_1 | |
|
| - | 932 | R500_ALU_RGB_B_SWIZ_B_1); |
|
| - | 933 | mask_alpha = R500_ALPHA_SWIZ_B_1; |
|
| - | 934 | ||
| - | 935 | /* shader output swizzling */ |
|
| - | 936 | output_fmt = (R300_OUT_FMT_C4_8 | |
|
| - | 937 | R300_OUT_FMT_C0_SEL_BLUE | |
|
| - | 938 | R300_OUT_FMT_C1_SEL_GREEN | |
|
| - | 939 | R300_OUT_FMT_C2_SEL_RED | |
|
| - | 940 | R300_OUT_FMT_C3_SEL_ALPHA); |
|
| - | 941 | ||
| - | 942 | BEGIN_ACCEL(6); |
|
| - | 943 | OUT_ACCEL_REG(R300_RS_COUNT, |
|
| - | 944 | ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | |
|
| - | 945 | R300_RS_COUNT_HIRES_EN)); |
|
| - | 946 | ||
| - | 947 | OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); |
|
| - | 948 | ||
| - | 949 | OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | |
|
| - | 950 | R500_US_CODE_END_ADDR(1))); |
|
| - | 951 | OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | |
|
| - | 952 | R500_US_CODE_RANGE_SIZE(1))); |
|
| - | 953 | OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); |
|
| - | 954 | ||
| - | 955 | OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); |
|
| - | 956 | FINISH_ACCEL(); |
|
| - | 957 | ||
| - | 958 | BEGIN_ACCEL(13); |
|
| - | 959 | OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); |
|
| - | 960 | /* tex inst for src texture */ |
|
| - | 961 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | |
|
| - | 962 | R500_INST_TEX_SEM_WAIT | |
|
| - | 963 | R500_INST_RGB_WMASK_R | |
|
| - | 964 | R500_INST_RGB_WMASK_G | |
|
| - | 965 | R500_INST_RGB_WMASK_B | |
|
| - | 966 | R500_INST_ALPHA_WMASK | |
|
| - | 967 | R500_INST_RGB_CLAMP | |
|
| - | 968 | R500_INST_ALPHA_CLAMP)); |
|
| - | 969 | ||
| - | 970 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | |
|
| - | 971 | R500_TEX_INST_LD | |
|
| - | 972 | R500_TEX_SEM_ACQUIRE | |
|
| - | 973 | R500_TEX_IGNORE_UNCOVERED)); |
|
| - | 974 | ||
| - | 975 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | |
|
| - | 976 | R500_TEX_SRC_S_SWIZ_R | |
|
| - | 977 | R500_TEX_SRC_T_SWIZ_G | |
|
| - | 978 | R500_TEX_DST_ADDR(0) | |
|
| - | 979 | R500_TEX_DST_R_SWIZ_R | |
|
| - | 980 | R500_TEX_DST_G_SWIZ_G | |
|
| - | 981 | R500_TEX_DST_B_SWIZ_B | |
|
| - | 982 | R500_TEX_DST_A_SWIZ_A)); |
|
| - | 983 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | |
|
| - | 984 | R500_DX_S_SWIZ_R | |
|
| - | 985 | R500_DX_T_SWIZ_R | |
|
| - | 986 | R500_DX_R_SWIZ_R | |
|
| - | 987 | R500_DX_Q_SWIZ_R | |
|
| - | 988 | R500_DY_ADDR(0) | |
|
| - | 989 | R500_DY_S_SWIZ_R | |
|
| - | 990 | R500_DY_T_SWIZ_R | |
|
| - | 991 | R500_DY_R_SWIZ_R | |
|
| - | 992 | R500_DY_Q_SWIZ_R)); |
|
| - | 993 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
|
| - | 994 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
|
| - | 995 | ||
| - | 996 | /* ALU inst */ |
|
| - | 997 | /* *_OMASK* - output component write mask */ |
|
| - | 998 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | |
|
| - | 999 | R500_INST_TEX_SEM_WAIT | |
|
| - | 1000 | R500_INST_LAST | |
|
| - | 1001 | R500_INST_RGB_OMASK_R | |
|
| - | 1002 | R500_INST_RGB_OMASK_G | |
|
| - | 1003 | R500_INST_RGB_OMASK_B | |
|
| - | 1004 | R500_INST_ALPHA_OMASK | |
|
| - | 1005 | R500_INST_RGB_CLAMP | |
|
| - | 1006 | R500_INST_ALPHA_CLAMP)); |
|
| - | 1007 | /* ALU inst |
|
| - | 1008 | * temp addresses for texture inputs |
|
| - | 1009 | * RGB_ADDR0 is src tex (temp 0) |
|
| - | 1010 | * RGB_ADDR1 is mask tex (temp 1) |
|
| - | 1011 | */ |
|
| - | 1012 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | |
|
| - | 1013 | R500_RGB_ADDR1(1) | |
|
| - | 1014 | R500_RGB_ADDR2(0))); |
|
| - | 1015 | /* ALU inst |
|
| - | 1016 | * temp addresses for texture inputs |
|
| - | 1017 | * ALPHA_ADDR0 is src tex (temp 0) |
|
| - | 1018 | * ALPHA_ADDR1 is mask tex (temp 1) |
|
| - | 1019 | */ |
|
| - | 1020 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | |
|
| - | 1021 | R500_ALPHA_ADDR1(1) | |
|
| - | 1022 | R500_ALPHA_ADDR2(0))); |
|
| - | 1023 | ||
| - | 1024 | /* R500_ALU_RGB_TARGET - RGB render target */ |
|
| - | 1025 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | |
|
| - | 1026 | src_color | |
|
| - | 1027 | R500_ALU_RGB_SEL_B_SRC1 | |
|
| - | 1028 | mask_color | |
|
| - | 1029 | R500_ALU_RGB_TARGET(0))); |
|
| - | 1030 | ||
| - | 1031 | /* R500_ALPHA_RGB_TARGET - alpha render target */ |
|
| - | 1032 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | |
|
| - | 1033 | R500_ALPHA_ADDRD(0) | |
|
| - | 1034 | R500_ALPHA_SEL_A_SRC0 | |
|
| - | 1035 | src_alpha | |
|
| - | 1036 | R500_ALPHA_SEL_B_SRC1 | |
|
| - | 1037 | mask_alpha | |
|
| - | 1038 | R500_ALPHA_TARGET(0))); |
|
| - | 1039 | ||
| - | 1040 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | |
|
| - | 1041 | R500_ALU_RGBA_ADDRD(0) | |
|
| - | 1042 | R500_ALU_RGBA_R_SWIZ_0 | |
|
| - | 1043 | R500_ALU_RGBA_G_SWIZ_0 | |
|
| - | 1044 | R500_ALU_RGBA_B_SWIZ_0 | |
|
| - | 1045 | R500_ALU_RGBA_A_SWIZ_0)); |
|
| - | 1046 | FINISH_ACCEL(); |
|
| - | 1047 | } |
|
| - | 1048 | ||
| - | 1049 | BEGIN_ACCEL(3); |
|
| - | 1050 | ||
| - | 1051 | OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); |
|
| - | 1052 | OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); |
|
| - | 1053 | ||
| - | 1054 | blendcntl = RADEONGetBlendCntl(op, PICT_a8r8g8b8); |
|
| - | 1055 | OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE); |
|
| - | 1056 | ||
| - | 1057 | FINISH_ACCEL(); |
|
| - | 1058 | ||
| - | 1059 | return TRUE; |
|
| - | 1060 | } |
|
| - | 1061 | ||
| - | 1062 | ||
| - | 1063 | ||
| - | 1064 | ||
| - | 1065 | ||
| - | 1066 | ||
| - | 1067 | #define VTX_COUNT 4 |
|
| - | 1068 | ||
| - | 1069 | static __inline__ u32_t F_TO_DW(float val) |
|
| - | 1070 | { |
|
| - | 1071 | union { |
|
| - | 1072 | float f; |
|
| - | 1073 | u32_t l; |
|
| - | 1074 | } tmp; |
|
| - | 1075 | tmp.f = val; |
|
| - | 1076 | return tmp.l; |
|
| - | 1077 | } |
|
| - | 1078 | ||
| - | 1079 | #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) |
|
| - | 1080 | ||
| - | 1081 | #define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ |
|
| - | 1082 | do { \ |
|
| - | 1083 | OUT_RING_F(_dstX); \ |
|
| - | 1084 | OUT_RING_F(_dstY); \ |
|
| - | 1085 | OUT_RING_F(_srcX); \ |
|
| - | 1086 | OUT_RING_F(_srcY); \ |
|
| - | 1087 | } while (0) |
|
| - | 1088 | ||
| - | 1089 | ||
| - | 1090 | ||
| - | 1091 | static void RadeonCompositeTile(int srcX, int srcY, |
|
| - | 1092 | int dstX, int dstY, |
|
| - | 1093 | int w, int h) |
|
| - | 1094 | { |
|
| - | 1095 | // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
|
| - | 1096 | int vtx_count; |
|
| - | 1097 | xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; |
|
| - | 1098 | xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; |
|
| - | 1099 | ||
| - | 1100 | u32 *ring, write; |
|
| - | 1101 | ||
| - | 1102 | ||
| - | 1103 | // ACCEL_PREAMBLE(); |
|
| - | 1104 | ||
| - | 1105 | // ENTER_DRAW(0); |
|
| - | 1106 | ||
| - | 1107 | /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", |
|
| - | 1108 | srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ |
|
| - | 1109 | ||
| - | 1110 | srcTopLeft.x = IntToxFixed(srcX); |
|
| - | 1111 | srcTopLeft.y = IntToxFixed(srcY); |
|
| - | 1112 | srcTopRight.x = IntToxFixed(srcX + w); |
|
| - | 1113 | srcTopRight.y = IntToxFixed(srcY); |
|
| - | 1114 | srcBottomLeft.x = IntToxFixed(srcX); |
|
| - | 1115 | srcBottomLeft.y = IntToxFixed(srcY + h); |
|
| - | 1116 | srcBottomRight.x = IntToxFixed(srcX + w); |
|
| - | 1117 | srcBottomRight.y = IntToxFixed(srcY + h); |
|
| - | 1118 | ||
| - | 1119 | /* |
|
| - | 1120 | if (is_transform[0]) { |
|
| - | 1121 | transformPoint(transform[0], &srcTopLeft); |
|
| - | 1122 | transformPoint(transform[0], &srcTopRight); |
|
| - | 1123 | transformPoint(transform[0], &srcBottomLeft); |
|
| - | 1124 | transformPoint(transform[0], &srcBottomRight); |
|
| - | 1125 | } |
|
| - | 1126 | if (is_transform[1]) { |
|
| - | 1127 | transformPoint(transform[1], &maskTopLeft); |
|
| - | 1128 | transformPoint(transform[1], &maskTopRight); |
|
| - | 1129 | transformPoint(transform[1], &maskBottomLeft); |
|
| - | 1130 | transformPoint(transform[1], &maskBottomRight); |
|
| - | 1131 | } |
|
| - | 1132 | */ |
|
| - | 1133 | vtx_count = VTX_COUNT; |
|
| - | 1134 | ||
| - | 1135 | BEGIN_ACCEL(1); |
|
| - | 1136 | OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); |
|
| - | 1137 | FINISH_ACCEL(); |
|
| - | 1138 | ||
| - | 1139 | BEGIN_RING(4 * vtx_count + 4); |
|
| - | 1140 | ||
| - | 1141 | OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, |
|
| - | 1142 | 4 * vtx_count)); |
|
| - | 1143 | OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | |
|
| - | 1144 | RADEON_CP_VC_CNTL_PRIM_WALK_RING | |
|
| - | 1145 | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); |
|
| - | 1146 | ||
| - | 1147 | ||
| - | 1148 | VTX_OUT((float)dstX, (float)dstY, |
|
| - | 1149 | xFixedToFloat(srcTopLeft.x) / w, // info->texW[0], |
|
| - | 1150 | xFixedToFloat(srcTopLeft.y) / h); // info->texH[0]); |
|
| - | 1151 | ||
| - | 1152 | VTX_OUT((float)dstX, (float)(dstY + h), |
|
| - | 1153 | xFixedToFloat(srcBottomLeft.x) / w, // info->texW[0], |
|
| - | 1154 | xFixedToFloat(srcBottomLeft.y) / h); // info->texH[0]); |
|
| - | 1155 | ||
| - | 1156 | VTX_OUT((float)(dstX + w), (float)(dstY + h), |
|
| - | 1157 | xFixedToFloat(srcBottomRight.x) / w, // info->texW[0], |
|
| - | 1158 | xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]); |
|
| - | 1159 | ||
| - | 1160 | VTX_OUT((float)(dstX + w), (float)dstY, |
|
| - | 1161 | xFixedToFloat(srcTopRight.x) / w, // info->texW[0], |
|
| - | 1162 | xFixedToFloat(srcTopRight.y) / h); // info->texH[0]); |
|
| - | 1163 | ||
| - | 1164 | /* flushing is pipelined, free/finish is not */ |
|
| - | 1165 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); |
|
| - | 1166 | ||
| - | 1167 | // OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); |
|
| - | 1168 | ||
| - | 1169 | COMMIT_RING(); |
|
| - | 1170 | ||
| - | 1171 | // LEAVE_DRAW(0); |
|
| - | 1172 | } |
|
| - | 1173 | #undef VTX_OUT |
|
| - | 1174 | #undef VTX_OUT_MASK |
|
| - | 1175 | ||
| - | 1176 | ||
| - | 1177 | int RadeonComposite( blit_t *blit) |
|
| - | 1178 | { |
|
| - | 1179 | int tileSrcY, tileMaskY, tileDstY; |
|
| - | 1180 | int remainingHeight; |
|
| - | 1181 | ||
| - | 1182 | R300PrepareComposite(3, blit->src_x, blit->src_y, |
|
| - | 1183 | blit->dst_x, blit->dst_y, |
|
| - | 1184 | blit->w, blit->h); |
|
| - | 1185 | ||
| - | 1186 | // if (!need_src_tile_x && !need_src_tile_y) { |
|
| - | 1187 | RadeonCompositeTile( blit->src_x, blit->src_y, |
|
| - | 1188 | blit->dst_x, blit->dst_y, |
|
| - | 1189 | blit->w, blit->h); |
|
| - | 1190 | return 0; |
|
| - | 1191 | // } |
|
| - | 1192 | ||
| - | 1193 | /* Tiling logic borrowed from exaFillRegionTiled */ |
|
| - | 1194 | ||
| - | 1195 | #if 0 |
|
| - | 1196 | modulus(srcY, src_tile_height, tileSrcY); |
|
| - | 1197 | tileMaskY = maskY; |
|
| - | 1198 | tileDstY = dstY; |
|
| - | 1199 | ||
| - | 1200 | remainingHeight = height; |
|
| - | 1201 | while (remainingHeight > 0) { |
|
| - | 1202 | int remainingWidth = width; |
|
| - | 1203 | int tileSrcX, tileMaskX, tileDstX; |
|
| - | 1204 | int h = src_tile_height - tileSrcY; |
|
| - | 1205 | ||
| - | 1206 | if (h > remainingHeight) |
|
| - | 1207 | h = remainingHeight; |
|
| - | 1208 | remainingHeight -= h; |
|
| - | 1209 | ||
| - | 1210 | modulus(srcX, src_tile_width, tileSrcX); |
|
| - | 1211 | tileMaskX = maskX; |
|
| - | 1212 | tileDstX = dstX; |
|
| - | 1213 | ||
| - | 1214 | while (remainingWidth > 0) { |
|
| - | 1215 | int w = src_tile_width - tileSrcX; |
|
| - | 1216 | if (w > remainingWidth) |
|
| - | 1217 | w = remainingWidth; |
|
| - | 1218 | remainingWidth -= w; |
|
| - | 1219 | ||
| - | 1220 | FUNC_NAME(RadeonCompositeTile)(pDst, |
|
| - | 1221 | tileSrcX, tileSrcY, |
|
| - | 1222 | tileMaskX, tileMaskY, |
|
| - | 1223 | tileDstX, tileDstY, |
|
| - | 1224 | w, h); |
|
| - | 1225 | ||
| - | 1226 | tileSrcX = 0; |
|
| - | 1227 | tileMaskX += w; |
|
| - | 1228 | tileDstX += w; |
|
| - | 1229 | } |
|
| - | 1230 | tileSrcY = 0; |
|
| - | 1231 | tileMaskY += h; |
|
| - | 1232 | tileDstY += h; |
|
| - | 1233 | } |
|