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Line 270... | Line 270... | ||
270 | else |
270 | else |
271 | if (hsrc eqtype 0) & (~lsrc eqtype 0) |
271 | if (hsrc eqtype 0) & (~lsrc eqtype 0) |
272 | mov dest, (hsrc) shl 16 |
272 | mov dest, (hsrc) shl 16 |
273 | add dest, lsrc |
273 | add dest, lsrc |
274 | else |
274 | else |
275 | movi dest, hsrc |
275 | mov dest, hsrc |
276 | shl dest, 16 |
276 | shl dest, 16 |
277 | add dest, lsrc |
277 | add dest, lsrc |
278 | end if |
278 | end if |
279 | end if |
279 | end if |
280 | } |
280 | } |
Line 281... | Line 281... | ||
281 | 281 | ||
282 | macro __mov reg,a,b { ; mike.dld |
282 | macro __mov reg,a,b { ; mike.dld |
283 | if (~a eq)&(~b eq) |
283 | if (~a eq)&(~b eq) |
284 | mpack reg,a,b |
284 | mpack reg,a,b |
285 | else if (~a eq)&(b eq) |
285 | else if (~a eq)&(b eq) |
286 | movi reg,a |
286 | mov reg,a |
287 | end if |
287 | end if |
Line 288... | Line 288... | ||
288 | } |
288 | } |