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Rev 3653 Rev 3656
Line 18... Line 18...
18 
USB_PID_SETUP = 2Dh
 18 
USB_PID_SETUP = 2Dh
19 
USB_PID_IN    = 69h
 19 
USB_PID_IN    = 69h
20 
USB_PID_OUT   = 0E1h
 20 
USB_PID_OUT   = 0E1h
21 
; UHCI does not support an interrupt on root hub status change. We must poll
 21 
; UHCI does not support an interrupt on root hub status change. We must poll
22 
; the controller periodically. This is the period in timer ticks (10ms).
 22 
; the controller periodically. This is the period in timer ticks (10ms).
23 
; We use the value 100 ms: it is valid value for USB hub poll rate (1-255 ms),
 23 
; We use the value 100 ticks: it is small enough to be responsible to connect
24 
; small enough to be responsible to connect events and large enough to not
 24 
; events and large enough to not load CPU too often.
25 
; load CPU too often.
 - 
 
26 
UHCI_POLL_INTERVAL = 100
 25 
UHCI_POLL_INTERVAL = 100
27 
; the following constant is an invalid encoding for length fields in
 26 
; the following constant is an invalid encoding for length fields in
28 
; uhci_gtd; it is used to check whether an inactive TD has been
 27 
; uhci_gtd; it is used to check whether an inactive TD has been
29 
; completed (actual length of the transfer is valid) or not processed at all
 28 
; completed (actual length of the transfer is valid) or not processed at all
30 
; (actual length of the transfer is UHCI_INVALID_LENGTH).
 29 
; (actual length of the transfer is UHCI_INVALID_LENGTH).
Line 1716... Line 1715...
1716 
        pop     [ecx+uhci_gtd.OrigBufferInfo-sizeof.uhci_gtd]
 1715 
        pop     [ecx+uhci_gtd.OrigBufferInfo-sizeof.uhci_gtd]
1717 
; 5b. Store physical address of the next TD.
 1716 
; 5b. Store physical address of the next TD.
1718 
        push    eax
 1717 
        push    eax
1719 
        sub     eax, sizeof.uhci_gtd
 1718 
        sub     eax, sizeof.uhci_gtd
1720 
        call    get_phys_addr
 1719 
        call    get_phys_addr
1721 
; use Depth traversal unless this is the first TD in the transfer stage;
 1720 
; for Control/Bulk pipes, use Depth traversal unless this is the first TD
- 
 
 1721 
; in the transfer stage;
1722 
; uhci_insert_transfer will set Depth traversal for the first TD and clear
 1722 
; uhci_insert_transfer will set Depth traversal for the first TD and clear
1723 
; it in the last TD
 1723 
; it in the last TD
- 
 
 1724 
        test    [ebx+usb_pipe.Type], 1
- 
 
 1725 
        jnz     @f
1724 
        cmp     ecx, [ebx+usb_pipe.LastTD]
 1726 
        cmp     ecx, [ebx+usb_pipe.LastTD]
1725 
        jz      @f
 1727 
        jz      @f
1726 
        or      eax, 4
 1728 
        or      eax, 4
1727 
@@:
 1729 
@@:
1728 
        mov     [ecx+uhci_gtd.NextTD-sizeof.uhci_gtd], eax
 1730 
        mov     [ecx+uhci_gtd.NextTD-sizeof.uhci_gtd], eax
Line 1776... Line 1778...
1776 
;       DEBUGF 1,'K : uhci_insert_transfer: eax=%x, ecx=%x, [esp+4]=%x\n',eax,ecx,[esp+4]
 1778 
;       DEBUGF 1,'K : uhci_insert_transfer: eax=%x, ecx=%x, [esp+4]=%x\n',eax,ecx,[esp+4]
1777 
        and     byte [eax+uhci_gtd.ControlStatus+2-sizeof.uhci_gtd], not (1 shl (23-16))  ; clear Active bit
 1779 
        and     byte [eax+uhci_gtd.ControlStatus+2-sizeof.uhci_gtd], not (1 shl (23-16))  ; clear Active bit
1778 
        or      byte [ecx+uhci_gtd.ControlStatus+3-sizeof.uhci_gtd], 1 shl (24-24)        ; set InterruptOnComplete bit
 1780 
        or      byte [ecx+uhci_gtd.ControlStatus+3-sizeof.uhci_gtd], 1 shl (24-24)        ; set InterruptOnComplete bit
1779 
        mov     eax, [esp+4]
 1781 
        mov     eax, [esp+4]
1780 
        or      byte [eax+uhci_gtd.ControlStatus+2-sizeof.uhci_gtd], 1 shl (23-16)        ; set Active bit
 1782 
        or      byte [eax+uhci_gtd.ControlStatus+2-sizeof.uhci_gtd], 1 shl (23-16)        ; set Active bit
- 
 
 1783 
        test    [ebx+usb_pipe.Type], 1
- 
 
 1784 
        jnz     @f
1781 
        or      byte [eax+uhci_gtd.NextTD-sizeof.uhci_gtd], 4     ; set Depth bit
 1785 
        or      byte [eax+uhci_gtd.NextTD-sizeof.uhci_gtd], 4     ; set Depth bit
- 
 
 1786 
@@:
1782 
        ret
 1787 
        ret
1783 
endp
 1788 
endp
Line 1784... Line 1789...
1784 
 
 1789 
 
1785 
; Free all memory associated with one TD.
 1790 
; Free all memory associated with one TD.