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| Rev 3197 | Rev 3198 | ||
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| 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| 2 | ;; ;; |
2 | ;; ;; |
| 3 | ;; Copyright (C) KolibriOS team 2004-2013. All rights reserved. ;; |
3 | ;; Copyright (C) KolibriOS team 2004-2013. All rights reserved. ;; |
| 4 | ;; Distributed under terms of the GNU General Public License ;; |
4 | ;; Distributed under terms of the GNU General Public License ;; |
| 5 | ;; ;; |
5 | ;; ;; |
| 6 | ;; PCnet driver for KolibriOS ;; |
6 | ;; AMD PCnet driver for KolibriOS ;; |
| 7 | ;; ;; |
7 | ;; ;; |
| 8 | ;; By hidnplayr & clevermouse ;; |
8 | ;; By hidnplayr & clevermouse ;; |
| 9 | ;; ;; |
9 | ;; ;; |
| 10 | ;; Based on the PCnet32 driver for MenuetOS, by Jarek Pelczar ;; |
10 | ;; Based on the PCnet32 driver for MenuetOS, by Jarek Pelczar ;; |
| 11 | ;; ;; |
11 | ;; ;; |
| Line 23... | Line 23... | ||
| 23 | __DEBUG_LEVEL__ = 1 |
23 | __DEBUG_LEVEL__ = 1 |
| Line 24... | Line 24... | ||
| 24 | 24 | ||
| 25 | MAX_DEVICES = 4 |
25 | MAX_DEVICES = 4 |
| Line -... | Line 26... | ||
| - | 26 | MAX_ETH_FRAME_SIZE = 1514 |
|
| - | 27 | ||
| - | 28 | TX_RING_SIZE = 4 |
|
| 26 | MAX_ETH_FRAME_SIZE = 1514 |
29 | RX_RING_SIZE = 4 |
| 27 | 30 | ||
| 28 | include 'proc32.inc' |
31 | include 'proc32.inc' |
| 29 | include 'imports.inc' |
32 | include 'imports.inc' |
| Line 30... | Line -... | ||
| 30 | include 'fdo.inc' |
- | |
| 31 | include 'netdrv.inc' |
33 | include 'fdo.inc' |
| 32 | 34 | include 'netdrv.inc' |
|
| 33 | 35 | ||
| Line -... | Line 36... | ||
| - | 36 | public START |
|
| - | 37 | public service_proc |
|
| - | 38 | public version |
|
| - | 39 | ||
| - | 40 | ||
| - | 41 | PORT_AUI = 0x00 |
|
| - | 42 | PORT_10BT = 0x01 |
|
| - | 43 | PORT_GPSI = 0x02 |
|
| - | 44 | PORT_MII = 0x03 |
|
| - | 45 | PORT_PORTSEL = 0x03 |
|
| - | 46 | PORT_ASEL = 0x04 |
|
| - | 47 | PORT_100 = 0x40 |
|
| - | 48 | PORT_FD = 0x80 |
|
| - | 49 | ||
| - | 50 | DMA_MASK = 0xffffffff |
|
| - | 51 | ||
| - | 52 | LOG_TX_BUFFERS = 2 ; FIXME |
|
| - | 53 | LOG_RX_BUFFERS = 2 |
|
| - | 54 | ||
| - | 55 | TX_RING_MOD_MASK = (TX_RING_SIZE-1) |
|
| - | 56 | TX_RING_LEN_BITS = (LOG_TX_BUFFERS shl 12) |
|
| - | 57 | ||
| - | 58 | RX_RING_MOD_MASK = (RX_RING_SIZE-1) |
|
| - | 59 | RX_RING_LEN_BITS = (LOG_RX_BUFFERS shl 4) |
|
| - | 60 | ||
| - | 61 | PKT_BUF_SZ = 1544 |
|
| - | 62 | ||
| - | 63 | WIO_RDP = 0x10 |
|
| - | 64 | WIO_RAP = 0x12 |
|
| - | 65 | WIO_RESET = 0x14 |
|
| - | 66 | WIO_BDP = 0x16 |
|
| - | 67 | ||
| - | 68 | DWIO_RDP = 0x10 |
|
| - | 69 | DWIO_RAP = 0x14 |
|
| - | 70 | DWIO_RESET = 0x18 |
|
| - | 71 | DWIO_BDP = 0x1C |
|
| - | 72 | ||
| - | 73 | ; CSR registers |
|
| - | 74 | ||
| - | 75 | CSR_CSR = 0x00 |
|
| - | 76 | CSR_IAB0 = 0x01 |
|
| - | 77 | CSR_IAB1 = 0x02 |
|
| - | 78 | CSR_IMR = 0x03 |
|
| - | 79 | CSR_TFEAT = 0x04 |
|
| - | 80 | CSR_EXTCTL1 = 0x05 |
|
| - | 81 | CSR_DTBLLEN = 0x06 |
|
| - | 82 | CSR_EXTCTL2 = 0x07 |
|
| - | 83 | CSR_MAR0 = 0x08 |
|
| - | 84 | CSR_MAR1 = 0x09 |
|
| - | 85 | CSR_MAR2 = 0x0A |
|
| - | 86 | CSR_MAR3 = 0x0B |
|
| - | 87 | CSR_PAR0 = 0x0C |
|
| - | 88 | CSR_PAR1 = 0x0D |
|
| - | 89 | CSR_PAR2 = 0x0E |
|
| - | 90 | CSR_MODE = 0x0F |
|
| - | 91 | CSR_RXADDR0 = 0x18 |
|
| - | 92 | CSR_RXADDR1 = 0x19 |
|
| - | 93 | CSR_TXADDR0 = 0x1E |
|
| - | 94 | CSR_TXADDR1 = 0x1F |
|
| - | 95 | CSR_TXPOLL = 0x2F |
|
| - | 96 | CSR_RXPOLL = 0x31 |
|
| - | 97 | CSR_RXRINGLEN = 0x4C |
|
| - | 98 | CSR_TXRINGLEN = 0x4E |
|
| - | 99 | CSR_DMACTL = 0x50 |
|
| - | 100 | CSR_BUSTIMER = 0x52 |
|
| - | 101 | CSR_MEMERRTIMEO = 0x64 |
|
| - | 102 | CSR_ONNOWMISC = 0x74 |
|
| - | 103 | CSR_ADVFEAT = 0x7A |
|
| - | 104 | CSR_MACCFG = 0x7D |
|
| - | 105 | CSR_CHIPID0 = 0x58 |
|
| - | 106 | CSR_CHIPID1 = 0x59 |
|
| - | 107 | ||
| - | 108 | ; Control and Status Register (CSR0) |
|
| - | 109 | ||
| - | 110 | CSR_INIT = 1 shl 0 |
|
| - | 111 | CSR_START = 1 shl 1 |
|
| - | 112 | CSR_STOP = 1 shl 2 |
|
| - | 113 | CSR_TX = 1 shl 3 |
|
| - | 114 | CSR_TXON = 1 shl 4 |
|
| - | 115 | CSR_RXON = 1 shl 5 |
|
| - | 116 | CSR_INTEN = 1 shl 6 |
|
| - | 117 | CSR_INTR = 1 shl 7 |
|
| - | 118 | CSR_IDONE = 1 shl 8 |
|
| - | 119 | CSR_TINT = 1 shl 9 |
|
| - | 120 | CSR_RINT = 1 shl 10 |
|
| - | 121 | CSR_MERR = 1 shl 11 |
|
| - | 122 | CSR_MISS = 1 shl 12 |
|
| - | 123 | CSR_CERR = 1 shl 13 |
|
| - | 124 | ||
| - | 125 | ; Interrupt masks and deferral control (CSR3) |
|
| - | 126 | ||
| - | 127 | IMR_BSWAP = 0x0004 |
|
| - | 128 | IMR_ENMBA = 0x0008 ; enable modified backoff alg |
|
| - | 129 | IMR_DXMT2PD = 0x0010 |
|
| - | 130 | IMR_LAPPEN = 0x0020 ; lookahead packet processing enb |
|
| - | 131 | IMR_DXSUFLO = 0x0040 ; disable TX stop on underflow |
|
| - | 132 | IMR_IDONE = 0x0100 |
|
| - | 133 | IMR_TINT = 0x0200 |
|
| - | 134 | IMR_RINT = 0x0400 |
|
| - | 135 | IMR_MERR = 0x0800 |
|
| - | 136 | IMR_MISS = 0x1000 |
|
| - | 137 | ||
| - | 138 | IMR = IMR_IDONE ; IMR_TINT + IMR_RINT + IMR_MERR + IMR_MISS ;+ IMR_IDONE |
|
| - | 139 | ||
| - | 140 | ; Test and features control (CSR4) |
|
| - | 141 | ||
| - | 142 | TFEAT_TXSTRTMASK = 0x0004 |
|
| - | 143 | TFEAT_TXSTRT = 0x0008 |
|
| - | 144 | TFEAT_RXCCOFLOWM = 0x0010 ; Rx collision counter oflow |
|
| - | 145 | TFEAT_RXCCOFLOW = 0x0020 |
|
| - | 146 | TFEAT_UINT = 0x0040 |
|
| - | 147 | TFEAT_UINTREQ = 0x0080 |
|
| - | 148 | TFEAT_MISSOFLOWM = 0x0100 |
|
| - | 149 | TFEAT_MISSOFLOW = 0x0200 |
|
| - | 150 | TFEAT_STRIP_FCS = 0x0400 |
|
| - | 151 | TFEAT_PAD_TX = 0x0800 |
|
| - | 152 | TFEAT_TXDPOLL = 0x1000 |
|
| - | 153 | TFEAT_DMAPLUS = 0x4000 |
|
| - | 154 | ||
| - | 155 | ; Extended control and interrupt 1 (CSR5) |
|
| - | 156 | ||
| - | 157 | EXTCTL1_SPND = 0x0001 ; suspend |
|
| - | 158 | EXTCTL1_MPMODE = 0x0002 ; magic packet mode |
|
| - | 159 | EXTCTL1_MPENB = 0x0004 ; magic packet enable |
|
| - | 160 | EXTCTL1_MPINTEN = 0x0008 ; magic packet interrupt enable |
|
| - | 161 | EXTCTL1_MPINT = 0x0010 ; magic packet interrupt |
|
| - | 162 | EXTCTL1_MPPLBA = 0x0020 ; magic packet phys. logical bcast |
|
| - | 163 | EXTCTL1_EXDEFEN = 0x0040 ; excessive deferral interrupt enb. |
|
| - | 164 | EXTCTL1_EXDEF = 0x0080 ; excessive deferral interrupt |
|
| - | 165 | EXTCTL1_SINTEN = 0x0400 ; system interrupt enable |
|
| - | 166 | EXTCTL1_SINT = 0x0800 ; system interrupt |
|
| - | 167 | EXTCTL1_LTINTEN = 0x4000 ; last TX interrupt enb |
|
| - | 168 | EXTCTL1_TXOKINTD = 0x8000 ; TX OK interrupt disable |
|
| - | 169 | ||
| - | 170 | ; RX/TX descriptor len (CSR6) |
|
| - | 171 | ||
| - | 172 | DTBLLEN_RLEN = 0x0F00 |
|
| - | 173 | DTBLLEN_TLEN = 0xF000 |
|
| - | 174 | ||
| - | 175 | ; Extended control and interrupt 2 (CSR7) |
|
| - | 176 | ||
| - | 177 | EXTCTL2_MIIPDTINTE = 0x0001 |
|
| - | 178 | EXTCTL2_MIIPDTINT = 0x0002 |
|
| - | 179 | EXTCTL2_MCCIINTE = 0x0004 |
|
| - | 180 | EXTCTL2_MCCIINT = 0x0008 |
|
| - | 181 | EXTCTL2_MCCINTE = 0x0010 |
|
| - | 182 | EXTCTL2_MCCINT = 0x0020 |
|
| - | 183 | EXTCTL2_MAPINTE = 0x0040 |
|
| - | 184 | EXTCTL2_MAPINT = 0x0080 |
|
| - | 185 | EXTCTL2_MREINTE = 0x0100 |
|
| - | 186 | EXTCTL2_MREINT = 0x0200 |
|
| - | 187 | EXTCTL2_STINTE = 0x0400 |
|
| - | 188 | EXTCTL2_STINT = 0x0800 |
|
| - | 189 | EXTCTL2_RXDPOLL = 0x1000 |
|
| - | 190 | EXTCTL2_RDMD = 0x2000 |
|
| - | 191 | EXTCTL2_RXFRTG = 0x4000 |
|
| - | 192 | EXTCTL2_FASTSPNDE = 0x8000 |
|
| - | 193 | ||
| - | 194 | ; Mode (CSR15) |
|
| - | 195 | ||
| - | 196 | MODE_RXD = 0x0001 ; RX disable |
|
| - | 197 | MODE_TXD = 0x0002 ; TX disable |
|
| - | 198 | MODE_LOOP = 0x0004 ; loopback enable |
|
| - | 199 | MODE_TXCRCD = 0x0008 |
|
| - | 200 | MODE_FORCECOLL = 0x0010 |
|
| - | 201 | MODE_RETRYD = 0x0020 |
|
| - | 202 | MODE_INTLOOP = 0x0040 |
|
| - | 203 | MODE_PORTSEL = 0x0180 |
|
| - | 204 | MODE_RXVPAD = 0x2000 |
|
| - | 205 | MODE_RXNOBROAD = 0x4000 |
|
| - | 206 | MODE_PROMISC = 0x8000 |
|
| - | 207 | ||
| - | 208 | ; BCR (Bus Control Registers) |
|
| - | 209 | ||
| - | 210 | BCR_MMRA = 0x00 ; Master Mode Read Active |
|
| - | 211 | BCR_MMW = 0x01 ; Master Mode Write Active |
|
| - | 212 | BCR_MISCCFG = 0x02 |
|
| - | 213 | BCR_LED0 = 0x04 |
|
| - | 214 | BCR_LED1 = 0x05 |
|
| - | 215 | BCR_LED2 = 0x06 |
|
| - | 216 | BCR_LED3 = 0x07 |
|
| - | 217 | BCR_DUPLEX = 0x09 |
|
| - | 218 | BCR_BUSCTL = 0x12 |
|
| - | 219 | BCR_EECTL = 0x13 |
|
| - | 220 | BCR_SSTYLE = 0x14 |
|
| - | 221 | BCR_PCILAT = 0x16 |
|
| - | 222 | BCR_PCISUBVENID = 0x17 |
|
| - | 223 | BCR_PCISUBSYSID = 0x18 |
|
| - | 224 | BCR_SRAMSIZE = 0x19 |
|
| - | 225 | BCR_SRAMBOUND = 0x1A |
|
| - | 226 | BCR_SRAMCTL = 0x1B |
|
| - | 227 | BCR_MIICTL = 0x20 |
|
| - | 228 | BCR_MIIADDR = 0x21 |
|
| - | 229 | BCR_MIIDATA = 0x22 |
|
| - | 230 | BCR_PCIVENID = 0x23 |
|
| - | 231 | BCR_PCIPCAP = 0x24 |
|
| - | 232 | BCR_DATA0 = 0x25 |
|
| - | 233 | BCR_DATA1 = 0x26 |
|
| - | 234 | BCR_DATA2 = 0x27 |
|
| - | 235 | BCR_DATA3 = 0x28 |
|
| - | 236 | BCR_DATA4 = 0x29 |
|
| - | 237 | BCR_DATA5 = 0x2A |
|
| - | 238 | BCR_DATA6 = 0x2B |
|
| - | 239 | BCR_DATA7 = 0x2C |
|
| - | 240 | BCR_ONNOWPAT0 = 0x2D |
|
| - | 241 | BCR_ONNOWPAT1 = 0x2E |
|
| - | 242 | BCR_ONNOWPAT2 = 0x2F |
|
| - | 243 | BCR_PHYSEL = 0x31 |
|
| - | 244 | ||
| - | 245 | ; RX status register |
|
| - | 246 | ||
| - | 247 | RXSTAT_BPE = 0x0080 ; bus parity error |
|
| - | 248 | RXSTAT_ENP = 0x0100 ; end of packet |
|
| - | 249 | RXSTAT_STP = 0x0200 ; start of packet |
|
| - | 250 | RXSTAT_BUFF = 0x0400 ; buffer error |
|
| - | 251 | RXSTAT_CRC = 0x0800 ; CRC error |
|
| - | 252 | RXSTAT_OFLOW = 0x1000 ; rx overrun |
|
| - | 253 | RXSTAT_FRAM = 0x2000 ; framing error |
|
| - | 254 | RXSTAT_ERR = 0x4000 ; error summary |
|
| - | 255 | RXSTAT_OWN = 0x8000 |
|
| - | 256 | ||
| - | 257 | ; TX status register |
|
| - | 258 | ||
| - | 259 | TXSTAT_TRC = 0x0000000F ; transmit retries |
|
| - | 260 | TXSTAT_RTRY = 0x04000000 ; retry |
|
| - | 261 | TXSTAT_LCAR = 0x08000000 ; lost carrier |
|
| - | 262 | TXSTAT_LCOL = 0x10000000 ; late collision |
|
| - | 263 | TXSTAT_EXDEF = 0x20000000 ; excessive deferrals |
|
| - | 264 | TXSTAT_UFLOW = 0x40000000 ; transmit underrun |
|
| - | 265 | TXSTAT_BUFF = 0x80000000 ; buffer error |
|
| - | 266 | ||
| - | 267 | TXCTL_OWN = 0x8000 |
|
| - | 268 | TXCTL_ERR = 0x4000 ; error summary |
|
| - | 269 | TXCTL_ADD_FCS = 0x2000 ; add FCS to pkt |
|
| - | 270 | TXCTL_MORE_LTINT = 0x1000 |
|
| - | 271 | TXCTL_ONE = 0x0800 |
|
| - | 272 | TXCTL_DEF = 0x0400 |
|
| - | 273 | TXCTL_STP = 0x0200 |
|
| - | 274 | TXCTL_ENP = 0x0100 |
|
| - | 275 | TXCTL_BPE = 0x0080 |
|
| 34 | public START |
276 | |
| Line 35... | Line 277... | ||
| 35 | public service_proc |
277 | TXCTL_MBO = 0x0000F000 |
| Line 36... | Line 278... | ||
| 36 | public version |
278 | TXCTL_BUFSZ = 0x00000FFF |
| Line 37... | Line 279... | ||
| 37 | 279 | ||
| Line -... | Line 280... | ||
| - | 280 | ||
| 38 | 281 | virtual at ebx |
|
| 39 | virtual at ebx |
282 | |
| 40 | 283 | device: |
|
| 41 | device: |
284 | |
| 42 | 285 | ETH_DEVICE |
|
| 43 | ETH_DEVICE |
286 | |
| 44 | 287 | ; device specific |
|
| 45 | ; device specific |
288 | |
| Line -... | Line 289... | ||
| - | 289 | rb 0x100-(($ - device) and 0xff) ; align 256 |
|
| - | 290 | .private: |
|
| - | 291 | .mode_ dw ? |
|
| - | 292 | .tlen_rlen dw ? |
|
| - | 293 | .phys_addr dp ? |
|
| - | 294 | .reserved dw ? |
|
| 46 | 295 | .filter dq ? |
|
| 47 | .private: |
296 | .rx_ring_phys dd ? |
| 48 | .mode_ dw ? |
- | |
| 49 | .tlen_rlen dw ? |
297 | .tx_ring_phys dd ? |
| 50 | .phys_addr dp ? |
- | |
| 51 | .reserved dw ? |
298 | |
| 52 | .filter dq ? |
299 | rb 0x100-(($ - device) and 0xff) ; align 256 |
| 53 | .rx_ring_phys dd ? |
300 | .rx_ring rb RX_RING_SIZE * descriptor.size |
| 54 | .tx_ring_phys dd ? |
301 | |
| 55 | 302 | rb 0x100-(($ - device) and 0xff) ; align 256 |
|
| 56 | .cur_rx db ? |
303 | .tx_ring rb TX_RING_SIZE * descriptor.size |
| 57 | .cur_tx db ? |
304 | |
| 58 | .dirty_rx dd ? |
305 | .cur_rx db ? |
| Line 59... | Line -... | ||
| 59 | .dirty_tx dd ? |
- | |
| 60 | .tx_full db ? |
- | |
| 61 | .options dd ? |
- | |
| 62 | .full_duplex db ? |
306 | .cur_tx db ? |
| 63 | .chip_version dd ? |
307 | .last_tx db ? |
| 64 | .mii db ? |
308 | .options dd ? |
| 65 | .ltint db ? |
309 | .full_duplex db ? |
| Line 66... | Line -... | ||
| 66 | .dxsuflo db ? |
- | |
| 67 | .fset db ? |
310 | .chip_version dw ? |
| 68 | .fdx db ? |
311 | .mii db ? |
| 69 | 312 | .ltint db ? |
|
| 70 | .rx_buffer dd ? |
313 | .dxsuflo db ? |
| 71 | .tx_buffer dd ? |
314 | .fset db ? |
| 72 | 315 | .fdx db ? |
|
| 73 | .io_addr dd ? |
316 | |
| Line 74... | Line 317... | ||
| 74 | .irq_line db ? |
317 | .io_addr dd ? |
| Line 75... | Line 318... | ||
| 75 | .pci_bus db ? |
318 | .irq_line db ? |
| Line 76... | Line 319... | ||
| 76 | .pci_dev db ? |
319 | .pci_bus db ? |
| 77 | 320 | .pci_dev db ? |
|
| 78 | 321 | ||
| 79 | .access_read_csr dd ? |
322 | .read_csr dd ? |
| 80 | .access_write_csr dd ? |
323 | .write_csr dd ? |
| 81 | .access_read_bcr dd ? |
324 | .read_bcr dd ? |
| 82 | .access_write_bcr dd ? |
325 | .write_bcr dd ? |
| Line 83... | Line 326... | ||
| 83 | .access_read_rap dd ? |
326 | .read_rap dd ? |
| 84 | .access_write_rap dd ? |
327 | .write_rap dd ? |
| Line 85... | Line 328... | ||
| 85 | .access_reset dd ? |
328 | .sw_reset dd ? |
| 86 | 329 | ||
| 87 | device_size = $ - device |
330 | device_size = $ - device |
| Line 88... | Line -... | ||
| 88 | - | ||
| 89 | end virtual |
- | |
| 90 | - | ||
| 91 | struc buf_head { |
- | |
| 92 | .base dd ? |
- | |
| 93 | .length dw ? |
- | |
| 94 | .status dw ? |
- | |
| 95 | .msg_length dw ? |
- | |
| 96 | .misc dw ? |
- | |
| 97 | .reserved dd ? |
- | |
| 98 | - | ||
| 99 | .size: |
- | |
| 100 | } |
- | |
| 101 | - | ||
| 102 | virtual at 0 |
- | |
| 103 | buf_head buf_head |
- | |
| 104 | end virtual |
- | |
| 105 | - | ||
| 106 | PCNET_PORT_AUI = 0x00 |
- | |
| 107 | PCNET_PORT_10BT = 0x01 |
- | |
| 108 | PCNET_PORT_GPSI = 0x02 |
- | |
| 109 | PCNET_PORT_MII = 0x03 |
- | |
| 110 | PCNET_PORT_PORTSEL = 0x03 |
- | |
| 111 | PCNET_PORT_ASEL = 0x04 |
- | |
| 112 | PCNET_PORT_100 = 0x40 |
- | |
| 113 | PCNET_PORT_FD = 0x80 |
- | |
| 114 | - | ||
| 115 | PCNET_DMA_MASK = 0xffffffff |
- | |
| 116 | - | ||
| 117 | PCNET_LOG_TX_BUFFERS = 2 |
- | |
| 118 | PCNET_LOG_RX_BUFFERS = 2 |
- | |
| 119 | - | ||
| 120 | PCNET_TX_RING_SIZE = 4 |
- | |
| 121 | PCNET_TX_RING_MOD_MASK = (PCNET_TX_RING_SIZE-1) |
- | |
| 122 | PCNET_TX_RING_LEN_BITS = (PCNET_LOG_TX_BUFFERS shl 12) |
- | |
| 123 | - | ||
| 124 | PCNET_RX_RING_SIZE = 4 |
- | |
| 125 | PCNET_RX_RING_MOD_MASK = (PCNET_RX_RING_SIZE-1) |
- | |
| 126 | PCNET_RX_RING_LEN_BITS = (PCNET_LOG_RX_BUFFERS shl 4) |
- | |
| 127 | - | ||
| 128 | PCNET_PKT_BUF_SZ = 1544 |
- | |
| 129 | PCNET_PKT_BUF_SZ_NEG = 0xf9f8 |
- | |
| 130 | - | ||
| 131 | PCNET_WIO_RDP = 0x10 |
- | |
| 132 | PCNET_WIO_RAP = 0x12 |
- | |
| 133 | PCNET_WIO_RESET = 0x14 |
- | |
| 134 | PCNET_WIO_BDP = 0x16 |
- | |
| 135 | PCNET_DWIO_RDP = 0x10 |
- | |
| 136 | PCNET_DWIO_RAP = 0x14 |
- | |
| 137 | PCNET_DWIO_RESET = 0x18 |
- | |
| 138 | PCNET_DWIO_BDP = 0x1C |
- | |
| 139 | PCNET_TOTAL_SIZE = 0x20 |
- | |
| 140 | - | ||
| 141 | ; CSR registers |
- | |
| 142 | - | ||
| 143 | PCNET_CSR_CSR = 0x00 |
- | |
| 144 | PCNET_CSR_IAB0 = 0x01 |
- | |
| 145 | PCNET_CSR_IAB1 = 0x02 |
- | |
| 146 | PCNET_CSR_IMR = 0x03 |
- | |
| 147 | PCNET_CSR_TFEAT = 0x04 |
- | |
| 148 | PCNET_CSR_EXTCTL1 = 0x05 |
- | |
| 149 | PCNET_CSR_DTBLLEN = 0x06 |
- | |
| 150 | PCNET_CSR_EXTCTL2 = 0x07 |
- | |
| 151 | PCNET_CSR_MAR0 = 0x08 |
- | |
| 152 | PCNET_CSR_MAR1 = 0x09 |
- | |
| 153 | PCNET_CSR_MAR2 = 0x0A |
- | |
| 154 | PCNET_CSR_MAR3 = 0x0B |
- | |
| 155 | PCNET_CSR_PAR0 = 0x0C |
- | |
| 156 | PCNET_CSR_PAR1 = 0x0D |
- | |
| 157 | PCNET_CSR_PAR2 = 0x0E |
- | |
| 158 | PCNET_CSR_MODE = 0x0F |
- | |
| 159 | PCNET_CSR_RXADDR0 = 0x18 |
- | |
| 160 | PCNET_CSR_RXADDR1 = 0x19 |
- | |
| 161 | PCNET_CSR_TXADDR0 = 0x1E |
- | |
| 162 | PCNET_CSR_TXADDR1 = 0x1F |
- | |
| 163 | PCNET_CSR_TXPOLL = 0x2F |
- | |
| 164 | PCNET_CSR_RXPOLL = 0x31 |
- | |
| 165 | PCNET_CSR_RXRINGLEN = 0x4C |
- | |
| 166 | PCNET_CSR_TXRINGLEN = 0x4E |
- | |
| 167 | PCNET_CSR_DMACTL = 0x50 |
- | |
| 168 | PCNET_CSR_BUSTIMER = 0x52 |
- | |
| 169 | PCNET_CSR_MEMERRTIMEO = 0x64 |
- | |
| 170 | PCNET_CSR_ONNOWMISC = 0x74 |
- | |
| 171 | PCNET_CSR_ADVFEAT = 0x7A |
- | |
| 172 | PCNET_CSR_MACCFG = 0x7D |
- | |
| 173 | PCNET_CSR_CHIPID0 = 0x58 |
- | |
| 174 | PCNET_CSR_CHIPID1 = 0x59 |
- | |
| 175 | - | ||
| 176 | ; Control and Status Register (CSR0) |
- | |
| 177 | - | ||
| 178 | PCNET_CSR_INIT = 1 shl 0 |
- | |
| 179 | PCNET_CSR_START = 1 shl 1 |
- | |
| 180 | PCNET_CSR_STOP = 1 shl 2 |
- | |
| 181 | PCNET_CSR_TX = 1 shl 3 |
- | |
| 182 | PCNET_CSR_TXON = 1 shl 4 |
- | |
| 183 | PCNET_CSR_RXON = 1 shl 5 |
- | |
| 184 | PCNET_CSR_INTEN = 1 shl 6 |
- | |
| 185 | PCNET_CSR_INTR = 1 shl 7 |
- | |
| 186 | PCNET_CSR_IDONE = 1 shl 8 |
- | |
| 187 | PCNET_CSR_TINT = 1 shl 9 |
- | |
| 188 | PCNET_CSR_RINT = 1 shl 10 |
- | |
| 189 | PCNET_CSR_MERR = 1 shl 11 |
- | |
| 190 | PCNET_CSR_MISS = 1 shl 12 |
- | |
| 191 | PCNET_CSR_CERR = 1 shl 13 |
- | |
| 192 | - | ||
| 193 | ; Interrupt masks and deferral control (CSR3) |
- | |
| 194 | - | ||
| 195 | PCNET_IMR_BSWAP = 0x0004 |
- | |
| 196 | PCNET_IMR_ENMBA = 0x0008 ; enable modified backoff alg |
- | |
| 197 | PCNET_IMR_DXMT2PD = 0x0010 |
- | |
| 198 | PCNET_IMR_LAPPEN = 0x0020 ; lookahead packet processing enb |
- | |
| 199 | PCNET_IMR_DXSUFLO = 0x0040 ; disable TX stop on underflow |
- | |
| 200 | PCNET_IMR_IDONE = 0x0100 |
- | |
| 201 | PCNET_IMR_TINT = 0x0200 |
- | |
| 202 | PCNET_IMR_RINT = 0x0400 |
- | |
| 203 | PCNET_IMR_MERR = 0x0800 |
- | |
| 204 | PCNET_IMR_MISS = 0x1000 |
- | |
| 205 | - | ||
| 206 | PCNET_IMR = PCNET_IMR_TINT+PCNET_IMR_RINT+PCNET_IMR_IDONE+PCNET_IMR_MERR+PCNET_IMR_MISS |
- | |
| 207 | - | ||
| 208 | ; Test and features control (CSR4) |
- | |
| 209 | - | ||
| 210 | PCNET_TFEAT_TXSTRTMASK = 0x0004 |
- | |
| 211 | PCNET_TFEAT_TXSTRT = 0x0008 |
- | |
| 212 | PCNET_TFEAT_RXCCOFLOWM = 0x0010 ; Rx collision counter oflow |
- | |
| 213 | PCNET_TFEAT_RXCCOFLOW = 0x0020 |
- | |
| 214 | PCNET_TFEAT_UINT = 0x0040 |
- | |
| 215 | PCNET_TFEAT_UINTREQ = 0x0080 |
- | |
| 216 | PCNET_TFEAT_MISSOFLOWM = 0x0100 |
- | |
| 217 | PCNET_TFEAT_MISSOFLOW = 0x0200 |
- | |
| 218 | PCNET_TFEAT_STRIP_FCS = 0x0400 |
- | |
| 219 | PCNET_TFEAT_PAD_TX = 0x0800 |
- | |
| 220 | PCNET_TFEAT_TXDPOLL = 0x1000 |
- | |
| 221 | PCNET_TFEAT_DMAPLUS = 0x4000 |
- | |
| 222 | - | ||
| 223 | ; Extended control and interrupt 1 (CSR5) |
- | |
| 224 | - | ||
| 225 | PCNET_EXTCTL1_SPND = 0x0001 ; suspend |
- | |
| 226 | PCNET_EXTCTL1_MPMODE = 0x0002 ; magic packet mode |
- | |
| 227 | PCNET_EXTCTL1_MPENB = 0x0004 ; magic packet enable |
- | |
| 228 | PCNET_EXTCTL1_MPINTEN = 0x0008 ; magic packet interrupt enable |
- | |
| 229 | PCNET_EXTCTL1_MPINT = 0x0010 ; magic packet interrupt |
- | |
| 230 | PCNET_EXTCTL1_MPPLBA = 0x0020 ; magic packet phys. logical bcast |
- | |
| 231 | PCNET_EXTCTL1_EXDEFEN = 0x0040 ; excessive deferral interrupt enb. |
- | |
| 232 | PCNET_EXTCTL1_EXDEF = 0x0080 ; excessive deferral interrupt |
- | |
| 233 | PCNET_EXTCTL1_SINTEN = 0x0400 ; system interrupt enable |
- | |
| 234 | PCNET_EXTCTL1_SINT = 0x0800 ; system interrupt |
- | |
| 235 | PCNET_EXTCTL1_LTINTEN = 0x4000 ; last TX interrupt enb |
- | |
| 236 | PCNET_EXTCTL1_TXOKINTD = 0x8000 ; TX OK interrupt disable |
- | |
| 237 | - | ||
| 238 | ; RX/TX descriptor len (CSR6) |
- | |
| 239 | - | ||
| 240 | PCNET_DTBLLEN_RLEN = 0x0F00 |
- | |
| 241 | PCNET_DTBLLEN_TLEN = 0xF000 |
- | |
| 242 | - | ||
| 243 | ; Extended control and interrupt 2 (CSR7) |
- | |
| 244 | - | ||
| 245 | PCNET_EXTCTL2_MIIPDTINTE = 0x0001 |
- | |
| 246 | PCNET_EXTCTL2_MIIPDTINT = 0x0002 |
- | |
| 247 | PCNET_EXTCTL2_MCCIINTE = 0x0004 |
- | |
| 248 | PCNET_EXTCTL2_MCCIINT = 0x0008 |
- | |
| 249 | PCNET_EXTCTL2_MCCINTE = 0x0010 |
- | |
| 250 | PCNET_EXTCTL2_MCCINT = 0x0020 |
- | |
| 251 | PCNET_EXTCTL2_MAPINTE = 0x0040 |
- | |
| 252 | PCNET_EXTCTL2_MAPINT = 0x0080 |
- | |
| 253 | PCNET_EXTCTL2_MREINTE = 0x0100 |
- | |
| 254 | PCNET_EXTCTL2_MREINT = 0x0200 |
- | |
| 255 | PCNET_EXTCTL2_STINTE = 0x0400 |
- | |
| 256 | PCNET_EXTCTL2_STINT = 0x0800 |
- | |
| 257 | PCNET_EXTCTL2_RXDPOLL = 0x1000 |
- | |
| 258 | PCNET_EXTCTL2_RDMD = 0x2000 |
- | |
| 259 | PCNET_EXTCTL2_RXFRTG = 0x4000 |
- | |
| 260 | PCNET_EXTCTL2_FASTSPNDE = 0x8000 |
- | |
| 261 | - | ||
| 262 | ; Mode (CSR15) |
- | |
| 263 | - | ||
| 264 | PCNET_MODE_RXD = 0x0001 ; RX disable |
- | |
| 265 | PCNET_MODE_TXD = 0x0002 ; TX disable |
- | |
| 266 | PCNET_MODE_LOOP = 0x0004 ; loopback enable |
- | |
| 267 | PCNET_MODE_TXCRCD = 0x0008 |
- | |
| 268 | PCNET_MODE_FORCECOLL = 0x0010 |
- | |
| 269 | PCNET_MODE_RETRYD = 0x0020 |
- | |
| 270 | PCNET_MODE_INTLOOP = 0x0040 |
- | |
| 271 | PCNET_MODE_PORTSEL = 0x0180 |
- | |
| 272 | PCNET_MODE_RXVPAD = 0x2000 |
- | |
| 273 | PCNET_MODE_RXNOBROAD = 0x4000 |
- | |
| 274 | PCNET_MODE_PROMISC = 0x8000 |
- | |
| 275 | - | ||
| 276 | ; BCR (Bus Control Registers) |
- | |
| 277 | - | ||
| 278 | PCNET_BCR_MMRA = 0x00 ; Master Mode Read Active |
- | |
| 279 | PCNET_BCR_MMW = 0x01 ; Master Mode Write Active |
- | |
| 280 | PCNET_BCR_MISCCFG = 0x02 |
- | |
| 281 | PCNET_BCR_LED0 = 0x04 |
- | |
| 282 | PCNET_BCR_LED1 = 0x05 |
- | |
| 283 | PCNET_BCR_LED2 = 0x06 |
- | |
| 284 | PCNET_BCR_LED3 = 0x07 |
- | |
| 285 | PCNET_BCR_DUPLEX = 0x09 |
- | |
| 286 | PCNET_BCR_BUSCTL = 0x12 |
- | |
| 287 | PCNET_BCR_EECTL = 0x13 |
- | |
| 288 | PCNET_BCR_SSTYLE = 0x14 |
- | |
| 289 | PCNET_BCR_PCILAT = 0x16 |
- | |
| 290 | PCNET_BCR_PCISUBVENID = 0x17 |
- | |
| 291 | PCNET_BCR_PCISUBSYSID = 0x18 |
- | |
| 292 | PCNET_BCR_SRAMSIZE = 0x19 |
- | |
| 293 | PCNET_BCR_SRAMBOUND = 0x1A |
- | |
| 294 | PCNET_BCR_SRAMCTL = 0x1B |
- | |
| 295 | PCNET_BCR_MIICTL = 0x20 |
- | |
| 296 | PCNET_BCR_MIIADDR = 0x21 |
- | |
| 297 | PCNET_BCR_MIIDATA = 0x22 |
- | |
| 298 | PCNET_BCR_PCIVENID = 0x23 |
- | |
| 299 | PCNET_BCR_PCIPCAP = 0x24 |
- | |
| 300 | PCNET_BCR_DATA0 = 0x25 |
- | |
| 301 | PCNET_BCR_DATA1 = 0x26 |
- | |
| 302 | PCNET_BCR_DATA2 = 0x27 |
- | |
| 303 | PCNET_BCR_DATA3 = 0x28 |
- | |
| 304 | PCNET_BCR_DATA4 = 0x29 |
- | |
| 305 | PCNET_BCR_DATA5 = 0x2A |
- | |
| 306 | PCNET_BCR_DATA6 = 0x2B |
- | |
| 307 | PCNET_BCR_DATA7 = 0x2C |
- | |
| 308 | PCNET_BCR_ONNOWPAT0 = 0x2D |
- | |
| 309 | PCNET_BCR_ONNOWPAT1 = 0x2E |
- | |
| 310 | PCNET_BCR_ONNOWPAT2 = 0x2F |
- | |
| 311 | PCNET_BCR_PHYSEL = 0x31 |
- | |
| 312 | - | ||
| 313 | ; RX status register |
- | |
| 314 | - | ||
| 315 | PCNET_RXSTAT_BPE = 0x0080 ; bus parity error |
- | |
| 316 | PCNET_RXSTAT_ENP = 0x0100 ; end of packet |
- | |
| 317 | PCNET_RXSTAT_STP = 0x0200 ; start of packet |
- | |
| 318 | PCNET_RXSTAT_BUFF = 0x0400 ; buffer error |
- | |
| 319 | PCNET_RXSTAT_CRC = 0x0800 ; CRC error |
- | |
| 320 | PCNET_RXSTAT_OFLOW = 0x1000 ; rx overrun |
- | |
| 321 | PCNET_RXSTAT_FRAM = 0x2000 ; framing error |
- | |
| 322 | PCNET_RXSTAT_ERR = 0x4000 ; error summary |
- | |
| 323 | PCNET_RXSTAT_OWN = 0x8000 |
- | |
| 324 | - | ||
| 325 | ; TX status register |
- | |
| 326 | - | ||
| 327 | PCNET_TXSTAT_TRC = 0x0000000F ; transmit retries |
- | |
| 328 | PCNET_TXSTAT_RTRY = 0x04000000 ; retry |
- | |
| Line 329... | Line 331... | ||
| 329 | PCNET_TXSTAT_LCAR = 0x08000000 ; lost carrier |
331 | |
| Line 463... | Line 465... | ||
| 463 | find_irq [device.pci_bus], [device.pci_dev], [device.irq_line] |
465 | find_irq [device.pci_bus], [device.pci_dev], [device.irq_line] |
| Line 464... | Line 466... | ||
| 464 | 466 | ||
| 465 | DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\ |
467 | DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\ |
| Line 466... | Line -... | ||
| 466 | [device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:4 |
- | |
| 467 | - | ||
| 468 | allocate_and_clear [device.tx_buffer], PCNET_RX_RING_SIZE * (PCNET_PKT_BUF_SZ + buf_head.size), .err |
- | |
| 469 | allocate_and_clear [device.rx_buffer], PCNET_TX_RING_SIZE * (PCNET_PKT_BUF_SZ + buf_head.size), .err |
468 | [device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:4 |
| 470 | 469 | ||
| 471 | ; Ok, the eth_device structure is ready, let's probe the device |
470 | ; Ok, the eth_device structure is ready, let's probe the device |
| 472 | ; Because initialization fires IRQ, IRQ handler must be aware of this device |
471 | ; Because initialization fires IRQ, IRQ handler must be aware of this device |
| 473 | mov eax, [devices] ; Add the device structure to our device list |
472 | mov eax, [devices] ; Add the device structure to our device list |
| Line 501... | Line 500... | ||
| 501 | ; todo: reset device into virgin state |
500 | ; todo: reset device into virgin state |
| Line 502... | Line 501... | ||
| 502 | 501 | ||
| 503 | dec [devices] |
502 | dec [devices] |
| 504 | .err: |
503 | .err: |
| 505 | DEBUGF 1,"Error, removing all data !\n" |
- | |
| 506 | stdcall KernelFree, [device.rx_buffer] |
- | |
| 507 | stdcall KernelFree, [device.tx_buffer] |
504 | DEBUGF 1,"Error, removing all data !\n" |
| Line 508... | Line 505... | ||
| 508 | stdcall KernelFree, ebx |
505 | stdcall KernelFree, ebx |
| 509 | 506 | ||
| 510 | .fail: |
507 | .fail: |
| Line 542... | Line 539... | ||
| 542 | ;; |
539 | ;; |
| 543 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
540 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| Line 544... | Line 541... | ||
| 544 | 541 | ||
| 545 | align 4 |
542 | align 4 |
| - | 543 | probe: |
|
| 546 | probe: |
544 | |
| Line 547... | Line 545... | ||
| 547 | mov edx, [device.io_addr] |
545 | mov edx, [device.io_addr] |
| Line 548... | Line 546... | ||
| 548 | 546 | ||
| Line 553... | Line 551... | ||
| 553 | cmp eax, 4 |
551 | cmp eax, 4 |
| 554 | jne .try_dwio |
552 | jne .try_dwio |
| Line 555... | Line 553... | ||
| 555 | 553 | ||
| 556 | ; Try Word I/O |
554 | ; Try Word I/O |
| 557 | mov ax , 88 |
555 | mov ax, 88 |
| 558 | add edx, PCNET_WIO_RAP |
556 | add edx, WIO_RAP |
| 559 | out dx , ax |
557 | out dx, ax |
| 560 | nop |
558 | nop |
| 561 | nop |
559 | nop |
| 562 | in ax , dx |
560 | in ax, dx |
| 563 | sub edx, PCNET_WIO_RAP |
561 | sub edx, WIO_RAP |
| 564 | cmp ax , 88 |
562 | cmp ax, 88 |
| Line 565... | Line 563... | ||
| 565 | jne .try_dwio |
563 | jne .try_dwio |
| Line 575... | Line 573... | ||
| 575 | call dwio_read_csr |
573 | call dwio_read_csr |
| 576 | cmp eax, 4 |
574 | cmp eax, 4 |
| 577 | jne .no_dev |
575 | jne .no_dev |
| Line 578... | Line 576... | ||
| 578 | 576 | ||
| 579 | ; Try Dword I/O |
577 | ; Try Dword I/O |
| 580 | add edx, PCNET_DWIO_RAP |
578 | add edx, DWIO_RAP |
| 581 | mov eax, 88 |
579 | mov eax, 88 |
| 582 | out dx , eax |
580 | out dx, eax |
| 583 | nop |
581 | nop |
| 584 | nop |
582 | nop |
| 585 | in eax, dx |
583 | in eax, dx |
| 586 | sub edx, PCNET_DWIO_RAP |
584 | sub edx, DWIO_RAP |
| 587 | and eax, 0xffff |
585 | and eax, 0xffff |
| 588 | cmp eax, 88 |
586 | cmp eax, 88 |
| Line 589... | Line 587... | ||
| 589 | jne .no_dev |
587 | jne .no_dev |
| Line 594... | Line 592... | ||
| 594 | 592 | ||
| 595 | .no_dev: |
593 | .no_dev: |
| 596 | DEBUGF 1,"PCnet device not found!\n" |
594 | DEBUGF 1,"PCnet device not found!\n" |
| 597 | mov eax, 1 |
595 | mov eax, 1 |
| - | 596 | ret |
|
| 598 | ret |
597 | |
| - | 598 | .L1: |
|
| - | 599 | mov ecx, CSR_CHIPID0 |
|
| Line 599... | Line -... | ||
| 599 | .L1: |
- | |
| 600 | - | ||
| 601 | mov ecx, PCNET_CSR_CHIPID0 |
600 | call [device.read_csr] |
| - | 601 | ||
| Line 602... | Line -... | ||
| 602 | call [device.access_read_csr] |
- | |
| 603 | mov esi, eax |
- | |
| 604 | - | ||
| 605 | mov ecx, PCNET_CSR_CHIPID1 |
- | |
| 606 | call [device.access_read_csr] |
- | |
| 607 | shl eax, 16 |
- | |
| 608 | or eax, esi |
602 | mov esi, eax |
| 609 | 603 | shr esi, 12 |
|
| 610 | mov ecx, eax |
604 | |
| Line -... | Line 605... | ||
| - | 605 | and ax, 0xfff |
|
| - | 606 | cmp ax, 3 |
|
| 611 | and ecx, 0xfff |
607 | jne .no_dev |
| 612 | cmp ecx, 3 |
608 | |
| 613 | jne .no_dev |
609 | mov ecx, CSR_CHIPID1 |
| Line 614... | Line -... | ||
| 614 | - | ||
| 615 | shr eax, 12 |
610 | call [device.read_csr] |
| 616 | and eax, 0xffff |
611 | shl eax, 4 |
| 617 | mov [device.chip_version], eax |
612 | or eax, esi |
| 618 | 613 | mov [device.chip_version], ax |
|
| 619 | DEBUGF 1,"chip version ok\n" |
614 | |
| Line 620... | Line 615... | ||
| 620 | mov [device.fdx], 0 |
615 | mov [device.fdx], 0 |
| 621 | mov [device.mii], 0 |
616 | mov [device.mii], 0 |
| 622 | mov [device.fset], 0 |
617 | mov [device.fset], 0 |
| 623 | mov [device.dxsuflo], 0 |
618 | mov [device.dxsuflo], 0 |
| Line 624... | Line 619... | ||
| 624 | mov [device.ltint], 0 |
619 | mov [device.ltint], 0 |
| Line 625... | Line 620... | ||
| 625 | 620 | ||
| 626 | cmp eax, 0x2420 |
621 | cmp ax, 0x2420 |
| 627 | je .L2 |
622 | je .L2 |
| 628 | cmp eax, 0x2430 |
623 | cmp ax, 0x2430 |
| 629 | je .L2 |
624 | je .L2 |
| 630 | 625 | ||
| 631 | mov [device.fdx], 1 |
626 | mov [device.fdx], 1 |
| 632 | 627 | ||
| 633 | cmp eax, 0x2621 |
628 | cmp ax, 0x2621 |
| 634 | je .L4 |
629 | je .L4 |
| 635 | cmp eax, 0x2623 |
630 | cmp ax, 0x2623 |
| 636 | je .L5 |
631 | je .L5 |
| Line 637... | Line 632... | ||
| 637 | cmp eax, 0x2624 |
632 | cmp ax, 0x2624 |
| 638 | je .L6 |
633 | je .L6 |
| 639 | cmp eax, 0x2625 |
634 | cmp ax, 0x2625 |
| Line 671... | Line 666... | ||
| 671 | mov [device.mii], 1 |
666 | mov [device.mii], 1 |
| 672 | jmp .L10 |
667 | jmp .L10 |
| 673 | .L8: |
668 | .L8: |
| 674 | mov [device.name], device_l8 |
669 | mov [device.name], device_l8 |
| 675 | ; mov [device.fdx], 1 |
670 | ; mov [device.fdx], 1 |
| 676 | mov ecx, PCNET_CSR_RXPOLL |
671 | mov ecx, CSR_RXPOLL |
| 677 | call dword [device.access_read_bcr] |
672 | call dword [device.read_bcr] |
| 678 | call dword [device.access_write_bcr] |
673 | call dword [device.write_bcr] |
| 679 | jmp .L10 |
674 | jmp .L10 |
| 680 | .L9: |
675 | .L9: |
| 681 | mov [device.name], device_l9 |
676 | mov [device.name], device_l9 |
| 682 | ; mov [device.fdx], 1 |
677 | ; mov [device.fdx], 1 |
| 683 | mov [device.mii], 1 |
678 | mov [device.mii], 1 |
| 684 | .L10: |
679 | .L10: |
| 685 | DEBUGF 1,"device name: %s\n",[device.name] |
680 | DEBUGF 1,"device name: %s\n", [device.name] |
| Line 686... | Line 681... | ||
| 686 | 681 | ||
| 687 | cmp [device.fset], 1 |
682 | cmp [device.fset], 1 |
| 688 | jne .L11 |
683 | jne .L11 |
| 689 | mov ecx, PCNET_BCR_BUSCTL |
684 | mov ecx, BCR_BUSCTL |
| 690 | call [device.access_read_bcr] |
685 | call [device.read_bcr] |
| 691 | or eax, 0x800 |
686 | or eax, 0x800 |
| Line 692... | Line 687... | ||
| 692 | call [device.access_write_bcr] |
687 | call [device.write_bcr] |
| 693 | 688 | ||
| 694 | mov ecx, PCNET_CSR_DMACTL |
689 | mov ecx, CSR_DMACTL |
| 695 | call [device.access_read_csr] |
690 | call [device.read_csr] |
| 696 | ; and eax, 0xc00 |
691 | ; and eax, 0xc00 |
| 697 | ; or eax, 0xc00 |
692 | ; or eax, 0xc00 |
| Line 698... | Line 693... | ||
| 698 | mov eax, 0xc00 |
693 | mov eax, 0xc00 |
| 699 | call [device.access_write_csr] |
694 | call [device.write_csr] |
| 700 | 695 | ||
| Line 701... | Line 696... | ||
| 701 | mov [device.dxsuflo],1 |
696 | mov [device.dxsuflo],1 |
| Line 702... | Line -... | ||
| 702 | mov [device.ltint],1 |
- | |
| 703 | .L11: |
697 | mov [device.ltint],1 |
| 704 | 698 | .L11: |
|
| 705 | make_bus_master [device.pci_bus], [device.pci_dev] |
699 | |
| Line 706... | Line 700... | ||
| 706 | 700 | make_bus_master [device.pci_bus], [device.pci_dev] |
|
| 707 | mov eax, PCNET_PORT_ASEL |
701 | |
| Line 708... | Line -... | ||
| 708 | mov [device.options], eax |
- | |
| 709 | mov [device.mode_], word 0x0003 |
- | |
| 710 | mov [device.tlen_rlen], word (PCNET_TX_RING_LEN_BITS or PCNET_RX_RING_LEN_BITS) |
- | |
| 711 | - | ||
| 712 | mov dword [device.filter], 0 |
702 | mov [device.options], PORT_ASEL |
| 713 | mov dword [device.filter+4], 0 |
703 | mov [device.mode_], MODE_RXD + MODE_TXD ; disable receive and transmit |
| Line 714... | Line 704... | ||
| 714 | 704 | mov [device.tlen_rlen], (TX_RING_LEN_BITS or RX_RING_LEN_BITS) |
|
| Line 730... | Line 720... | ||
| 730 | ; or eax, -1 |
720 | ; or eax, -1 |
| 731 | ; ret |
721 | ; ret |
| 732 | @@: |
722 | @@: |
| Line 733... | Line 723... | ||
| 733 | 723 | ||
| - | 724 | mov edx, [device.io_addr] |
|
| 734 | mov edx, [device.io_addr] |
725 | |
| Line 735... | Line 726... | ||
| 735 | call [device.access_reset] |
726 | call [device.sw_reset] |
| 736 | 727 | ||
| 737 | ; Switch pcnet32 to 32bit mode |
728 | ; Switch pcnet32 to 32bit mode |
| 738 | mov ecx, PCNET_BCR_SSTYLE |
729 | mov ecx, BCR_SSTYLE |
| Line 739... | Line 730... | ||
| 739 | mov eax, 2 |
730 | mov eax, 2 |
| 740 | call [device.access_write_bcr] |
731 | call [device.write_bcr] |
| 741 | 732 | ||
| 742 | ; set/reset autoselect bit |
733 | ; set/reset autoselect bit |
| 743 | mov ecx, PCNET_BCR_MISCCFG |
734 | mov ecx, BCR_MISCCFG |
| 744 | call [device.access_read_bcr] |
735 | call [device.read_bcr] |
| 745 | and eax,not 2 |
736 | and eax, not 2 |
| 746 | test [device.options], PCNET_PORT_ASEL |
737 | test [device.options], PORT_ASEL |
| 747 | jz .L1 |
738 | jz @f |
| 748 | or eax, 2 |
- | |
| Line 749... | Line 739... | ||
| 749 | .L1: |
739 | or eax, 2 |
| 750 | call [device.access_write_bcr] |
740 | @@: |
| 751 | 741 | call [device.write_bcr] |
|
| 752 | 742 | ||
| 753 | ; Handle full duplex setting |
743 | ; Handle full duplex setting |
| 754 | cmp byte [device.full_duplex], 0 |
744 | cmp byte [device.full_duplex], 0 |
| 755 | je .L2 |
745 | je .duplex_ok |
| 756 | mov ecx, PCNET_BCR_DUPLEX |
746 | mov ecx, BCR_DUPLEX |
| 757 | call [device.access_read_bcr] |
747 | call [device.read_bcr] |
| 758 | and eax, not 3 |
748 | and eax, not 3 |
| 759 | test [device.options], PCNET_PORT_FD |
749 | test [device.options], PORT_FD |
| 760 | jz .L3 |
750 | jz @f |
| 761 | or eax, 1 |
751 | or eax, 1 |
| 762 | cmp [device.options], PCNET_PORT_FD or PCNET_PORT_AUI |
752 | cmp [device.options], PORT_FD or PORT_AUI |
| 763 | jne .L4 |
753 | jne .set_duplex |
| 764 | or eax, 2 |
754 | or eax, 2 |
| 765 | jmp .L4 |
755 | jmp .set_duplex |
| 766 | .L3: |
756 | @@: |
| 767 | test [device.options], PCNET_PORT_ASEL |
757 | test [device.options], PORT_ASEL |
| 768 | jz .L4 |
758 | jz .set_duplex |
| 769 | cmp [device.chip_version], 0x2627 |
759 | cmp [device.chip_version], 0x2627 |
| 770 | jne .L4 |
760 | jne .set_duplex |
| 771 | or eax, 3 |
761 | or eax, 3 |
| 772 | .L4: |
- | |
| Line 773... | Line 762... | ||
| 773 | mov ecx, PCNET_BCR_DUPLEX |
762 | .set_duplex: |
| 774 | call [device.access_write_bcr] |
763 | mov ecx, BCR_DUPLEX |
| 775 | .L2: |
764 | call [device.write_bcr] |
| 776 | 765 | .duplex_ok: |
|
| 777 | 766 | ||
| 778 | ; set/reset GPSI bit in test register |
767 | ; set/reset GPSI bit in test register |
| 779 | mov ecx, 124 |
768 | mov ecx, 124 |
| 780 | call [device.access_read_csr] |
769 | call [device.read_csr] |
| 781 | mov ecx, [device.options] |
770 | mov ecx, [device.options] |
| 782 | and ecx, PCNET_PORT_PORTSEL |
771 | and ecx, PORT_PORTSEL |
| 783 | cmp ecx, PCNET_PORT_GPSI |
772 | cmp ecx, PORT_GPSI |
| 784 | jne .L5 |
773 | jne @f |
| 785 | or eax, 0x10 |
774 | or eax, 0x10 |
| 786 | .L5: |
775 | @@: |
| 787 | call [device.access_write_csr] |
776 | call [device.write_csr] |
| 788 | cmp [device.mii], 0 |
777 | cmp [device.mii], 0 |
| 789 | je .L6 |
778 | je .L6 |
| 790 | test [device.options], PCNET_PORT_ASEL |
779 | test [device.options], PORT_ASEL |
| 791 | jnz .L6 |
780 | jnz .L6 |
| 792 | mov ecx, PCNET_BCR_MIICTL |
781 | mov ecx, BCR_MIICTL |
| 793 | call [device.access_read_bcr] |
782 | call [device.read_bcr] |
| 794 | and eax,not 0x38 |
783 | and eax, not 0x38 |
| 795 | test [device.options], PCNET_PORT_FD |
784 | test [device.options], PORT_FD |
| 796 | jz .L7 |
785 | jz @f |
| 797 | or eax, 0x10 |
786 | or eax, 0x10 |
| 798 | .L7: |
787 | @@: |
| 799 | test [device.options], PCNET_PORT_100 |
788 | test [device.options], PORT_100 |
| 800 | jz .L8 |
789 | jz @f |
| 801 | or eax, 0x08 |
790 | or eax, 0x08 |
| 802 | .L8: |
791 | @@: |
| 803 | call [device.access_write_bcr] |
792 | call [device.write_bcr] |
| 804 | jmp .L9 |
793 | jmp .L9 |
| 805 | .L6: |
794 | .L6: |
| 806 | test [device.options], PCNET_PORT_ASEL |
795 | test [device.options], PORT_ASEL |
| 807 | jz .L9 |
796 | jz .L9 |
| 808 | mov ecx, PCNET_BCR_MIICTL |
797 | mov ecx, BCR_MIICTL |
| 809 | DEBUGF 1,"ASEL, enable auto-negotiation\n" |
798 | DEBUGF 1,"ASEL, enable auto-negotiation\n" |
| 810 | call [device.access_read_bcr] |
799 | call [device.read_bcr] |
| 811 | and eax, not 0x98 |
800 | and eax, not 0x98 |
| 812 | or eax, 0x20 |
801 | or eax, 0x20 |
| 813 | call [device.access_write_bcr] |
802 | call [device.write_bcr] |
| 814 | .L9: |
803 | .L9: |
| 815 | cmp [device.ltint],0 |
804 | cmp [device.ltint], 0 |
| 816 | je .L10 |
805 | je @f |
| 817 | mov ecx,5 |
806 | mov ecx, 5 |
| 818 | call [device.access_read_csr] |
807 | call [device.read_csr] |
| 819 | or eax,(1 shl 14) |
808 | or eax, (1 shl 14) |
| 820 | call [device.access_write_csr] |
809 | call [device.write_csr] |
| 821 | .L10: |
810 | @@: |
| 822 | mov eax,[device.options] |
811 | mov eax, [device.options] |
| Line 833... | Line 822... | ||
| 833 | movsd |
822 | movsd |
| 834 | movsw |
823 | movsw |
| Line 835... | Line 824... | ||
| 835 | 824 | ||
| Line -... | Line 825... | ||
| - | 825 | call init_ring |
|
| - | 826 | ||
| 836 | call init_ring |
827 | mov edx, [device.io_addr] ; init ring destroys edx |
| 837 | 828 | ||
| 838 | lea eax, [device.private] |
- | |
| 839 | GetRealAddr |
829 | lea eax, [device.private] |
| 840 | 830 | GetRealAddr |
|
| 841 | push eax |
831 | push eax |
| 842 | and eax, 0xffff |
832 | and eax, 0xffff |
| 843 | mov ecx, 1 |
833 | mov ecx, 1 |
| 844 | call [device.access_write_csr] |
834 | call [device.write_csr] |
| 845 | pop eax |
835 | pop eax |
| 846 | shr eax,16 |
836 | shr eax, 16 |
| Line 847... | Line 837... | ||
| 847 | mov ecx,2 |
837 | mov ecx, 2 |
| 848 | call [device.access_write_csr] |
838 | call [device.write_csr] |
| 849 | 839 | ||
| 850 | mov ecx,4 |
- | |
| 851 | mov eax,0x0915 |
- | |
| 852 | call [device.access_write_csr] |
- | |
| 853 | - | ||
| Line 854... | Line 840... | ||
| 854 | mov ecx,0 |
840 | mov ecx, 4 |
| 855 | mov eax,1 |
841 | mov eax, 0x0915 |
| 856 | call [device.access_write_csr] |
842 | call [device.write_csr] |
| 857 | - | ||
| 858 | mov [device.tx_full],0 |
843 | |
| Line 859... | Line -... | ||
| 859 | mov [device.cur_rx],0 |
- | |
| 860 | mov [device.cur_tx],0 |
- | |
| 861 | mov [device.dirty_rx],0 |
844 | ; Set the interrupt mask |
| 862 | mov [device.dirty_tx],0 |
845 | mov ecx, CSR_IMR |
| 863 | - | ||
| 864 | mov ecx,100 |
846 | mov eax, IMR |
| 865 | .L11: |
847 | call [device.write_csr] |
| 866 | push ecx |
- | |
| 867 | xor ecx,ecx |
- | |
| 868 | call [device.access_read_csr] |
- | |
| Line 869... | Line 848... | ||
| 869 | pop ecx |
848 | |
| 870 | test ax,0x100 |
849 | ; Initialise the device |
| - | 850 | xor ecx, ecx |
|
| 871 | jnz .L12 |
851 | mov eax, CSR_INIT |
| 872 | loop .L11 |
852 | call [device.write_csr] |
| - | 853 | ||
| Line 873... | Line 854... | ||
| 873 | .L12: |
854 | mov esi, 100 |
| - | 855 | ; xor ecx, ecx |
|
| 874 | 856 | @@: |
|
| - | 857 | call [device.read_csr] |
|
| Line -... | Line 858... | ||
| - | 858 | test ax, CSR_IDONE |
|
| 875 | DEBUGF 1,"hardware reset\n" |
859 | jnz @f |
| 876 | xor ecx, ecx |
860 | |
| 877 | mov eax, 0x0002 |
861 | dec esi |
| Line 878... | Line 862... | ||
| 878 | call [device.access_write_csr] |
862 | jnz @r |
| 879 | 863 | DEBUGF 1,"Initialize timeout!\n" |
|
| Line 880... | Line 864... | ||
| 880 | xor ecx, ecx |
864 | @@: |
| 881 | call [device.access_read_csr] |
865 | |
| 882 | 866 | ; Start the device and enable interrupts |
|
| Line 883... | Line 867... | ||
| 883 | xor ecx, ecx |
867 | xor ecx, ecx |
| 884 | mov eax, PCNET_CSR_INTEN or PCNET_CSR_START |
868 | mov eax, CSR_START + CSR_INTEN |
| Line 885... | Line 869... | ||
| 885 | call [device.access_write_csr] |
869 | call [device.write_csr] |
| - | 870 | ||
| 886 | 871 | ; Set the mtu, kernel will be able to send now |
|
| 887 | ; Set the mtu, kernel will be able to send now |
872 | mov [device.mtu], 1514 |
| 888 | mov [device.mtu], 1514 |
873 | |
| 889 | 874 | DEBUGF 1,"reset complete\n" |
|
| 890 | DEBUGF 1,"PCNET reset complete\n" |
875 | xor eax, eax |
| 891 | xor eax, eax |
876 | ret |
| - | 877 | ||
| - | 878 | ||
| - | 879 | align 4 |
|
| 892 | ret |
880 | init_ring: |
| - | 881 | ||
| 893 | 882 | DEBUGF 1,"init ring\n" |
|
| 894 | 883 | ||
| 895 | align 4 |
884 | lea edi, [device.rx_ring] |
| 896 | init_ring: |
885 | mov eax, edi |
| 897 | 886 | GetRealAddr |
|
| 898 | mov ecx, PCNET_RX_RING_SIZE |
887 | mov [device.rx_ring_phys], eax |
| 899 | mov edi, [device.rx_buffer] |
888 | mov ecx, RX_RING_SIZE |
| Line 900... | Line -... | ||
| 900 | mov eax, edi |
- | |
| 901 | GetRealAddr |
889 | .rx_init: |
| 902 | mov [device.rx_ring_phys], eax |
890 | push ecx |
| 903 | add eax, PCNET_RX_RING_SIZE * buf_head.size |
891 | stdcall KernelAlloc, PKT_BUF_SZ |
| 904 | .rx_init: |
892 | pop ecx |
| 905 | mov [edi + buf_head.base], eax |
893 | mov [edi + descriptor.virtual], eax |
| 906 | mov [edi + buf_head.length], PCNET_PKT_BUF_SZ_NEG |
894 | GetRealAddr |
| 907 | mov [edi + buf_head.status], 0x8000 |
895 | mov [edi + descriptor.base], eax |
| 908 | and dword [edi + buf_head.msg_length], 0 |
- | |
| 909 | and dword [edi + buf_head.reserved], 0 |
- | |
| 910 | add eax, PCNET_PKT_BUF_SZ |
- | |
| 911 | add edi, buf_head.size |
896 | mov [edi + descriptor.length], - PKT_BUF_SZ |
| 912 | loop .rx_init |
897 | mov [edi + descriptor.status], RXSTAT_OWN |
| 913 | 898 | mov dword [edi + descriptor.msg_length], 0 ; also clears misc field |
|
| Line 914... | Line 899... | ||
| 914 | mov ecx, PCNET_TX_RING_SIZE |
899 | add edi, descriptor.size |
| - | 900 | dec ecx |
|
| - | 901 | jnz .rx_init |
|
| - | 902 | ||
| - | 903 | lea edi, [device.tx_ring] |
|
| Line 915... | Line 904... | ||
| 915 | mov edi, [device.tx_buffer] |
904 | mov eax, edi |
| Line 956... | Line 945... | ||
| 956 | ja .nospace ; packet is too long |
945 | ja .nospace ; packet is too long |
| 957 | cmp dword [esp+8], 60 |
946 | cmp dword [esp+8], 60 |
| 958 | jb .nospace ; packet is too short |
947 | jb .nospace ; packet is too short |
| Line 959... | Line 948... | ||
| 959 | 948 | ||
| - | 949 | ; check descriptor |
|
| 960 | ; check descriptor |
950 | lea edi, [device.tx_ring] |
| 961 | movzx eax, [device.cur_tx] |
- | |
| 962 | imul edi, eax, PCNET_PKT_BUF_SZ |
951 | movzx eax, [device.cur_tx] |
| 963 | shl eax, 4 |
- | |
| 964 | add eax, [device.tx_buffer] |
952 | shl eax, 4 |
| 965 | add edi, [device.tx_buffer] |
- | |
| Line 966... | Line 953... | ||
| 966 | add edi, PCNET_TX_RING_SIZE * buf_head.size |
953 | add edi, eax |
| 967 | 954 | ||
| 968 | test byte [eax + buf_head.status + 1], 80h |
955 | test [edi + descriptor.status], TXCTL_OWN |
| 969 | jnz .nospace |
956 | jnz .nospace |
| 970 | ; descriptor is free, copy data |
957 | ; descriptor is free, use it |
| 971 | mov esi, [esp+4] |
- | |
| 972 | mov ecx, [esp+8] |
- | |
| 973 | mov edx, ecx |
- | |
| 974 | shr ecx, 2 |
958 | mov eax, [esp+4] |
| 975 | and edx, 3 |
959 | mov [edi + descriptor.virtual], eax |
| 976 | rep movsd |
- | |
| 977 | mov ecx, edx |
960 | GetRealAddr |
| 978 | rep movsb |
961 | mov [edi + descriptor.base], eax |
| 979 | ; set length |
962 | ; set length |
| 980 | mov ecx, [esp+8] |
963 | mov eax, [esp+8] |
| 981 | neg ecx |
964 | neg eax |
| 982 | mov [eax + buf_head.length], cx |
965 | mov [edi + descriptor.length], ax |
| Line 983... | Line 966... | ||
| 983 | ; put to transfer queue |
966 | ; put to transfer queue |
| 984 | mov [eax + buf_head.status], 0x8300 |
967 | mov [edi + descriptor.status], TXCTL_OWN + TXCTL_STP + TXCTL_ENP |
| 985 | 968 | ||
| 986 | ; trigger an immediate send |
969 | ; trigger an immediate send |
| 987 | mov edx, [device.io_addr] |
970 | mov edx, [device.io_addr] |
| 988 | xor ecx, ecx ; CSR0 |
971 | xor ecx, ecx ; CSR0 |
| Line 989... | Line 972... | ||
| 989 | call [device.access_read_csr] |
972 | call [device.read_csr] |
| 990 | or eax, PCNET_CSR_TX |
973 | or eax, CSR_TX |
| 991 | call [device.access_write_csr] |
974 | call [device.write_csr] |
| 992 | 975 | ||
| Line 993... | Line 976... | ||
| 993 | ; get next descriptor 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, ... |
976 | ; get next descriptor 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, ... |
| 994 | inc [device.cur_tx] |
977 | inc [device.cur_tx] |
| 995 | and [device.cur_tx], 3 |
978 | and [device.cur_tx], TX_RING_SIZE - 1 |
| 996 | DEBUGF 2," - Packet Sent! " |
979 | DEBUGF 2," - Packet Sent! " |
| 997 | 980 | ||
| Line 998... | Line 981... | ||
| 998 | ; Update stats |
981 | ; Update stats |
| 999 | inc [device.packets_tx] |
982 | inc [device.packets_tx] |
| 1000 | mov eax, [esp+8] |
- | |
| 1001 | add dword [device.bytes_tx], eax |
983 | mov eax, [esp+8] |
| 1002 | adc dword [device.bytes_tx + 4], 0 |
984 | add dword [device.bytes_tx], eax |
| Line 1003... | Line 985... | ||
| 1003 | 985 | adc dword [device.bytes_tx + 4], 0 |
|
| 1004 | .finish: |
986 | |
| Line 1033... | Line 1015... | ||
| 1033 | jz .nothing |
1015 | jz .nothing |
| 1034 | mov esi, device_list |
1016 | mov esi, device_list |
| 1035 | .nextdevice: |
1017 | .nextdevice: |
| 1036 | mov ebx, [esi] |
1018 | mov ebx, [esi] |
| Line 1037... | Line 1019... | ||
| 1037 | 1019 | ||
| 1038 | mov edx, [device.io_addr] ; get IRQ reason |
1020 | mov edx, [device.io_addr] |
| 1039 | push ecx |
1021 | push ecx |
| 1040 | xor ecx, ecx ; CSR0 |
1022 | xor ecx, ecx ; CSR0 |
| - | 1023 | call [device.read_csr] ; get IRQ reason |
|
| 1041 | call [device.access_read_csr] |
1024 | call [device.write_csr] ; write it back to ACK |
| 1042 | pop ecx |
1025 | pop ecx |
| 1043 | test al, al |
1026 | test ax, ax |
| 1044 | js .got_it |
1027 | jnz .got_it |
| 1045 | .continue: |
1028 | .continue: |
| 1046 | add esi, 4 |
1029 | add esi, 4 |
| 1047 | dec ecx |
1030 | dec ecx |
| 1048 | jnz .nextdevice |
1031 | jnz .nextdevice |
| 1049 | .nothing: |
1032 | .nothing: |
| Line 1050... | Line 1033... | ||
| 1050 | ret ; If no device was found, abort (The irq was probably for a device, not registered to this driver |
1033 | ret ; If no device was found, abort (The int was probably for a device, not registered to this driver) |
| - | 1034 | ||
| Line 1051... | Line -... | ||
| 1051 | - | ||
| 1052 | .got_it: |
- | |
| 1053 | - | ||
| 1054 | DEBUGF 1,"Device: %x Status: %x ", ebx, eax:2 |
- | |
| 1055 | - | ||
| 1056 | ;------------------------------------------------------- |
- | |
| 1057 | ; Possible reasons: |
- | |
| 1058 | ; initialization done - ignore |
- | |
| 1059 | ; transmit done - ignore |
- | |
| 1060 | ; packet received - handle |
- | |
| 1061 | ; Clear ALL IRQ reasons. |
1035 | .got_it: |
| 1062 | ; N.B. One who wants to handle more than one reason must be ready |
- | |
| 1063 | ; to two or more reasons in one IRQ. |
- | |
| 1064 | xor ecx, ecx |
- | |
| 1065 | call [device.access_write_csr] |
1036 | DEBUGF 1,"Device: %x status: %x\n", ebx, eax:2 |
| 1066 | ; Received packet ok? |
1037 | |
| Line 1067... | Line 1038... | ||
| 1067 | 1038 | push ax |
|
| 1068 | test ax, PCNET_CSR_RINT |
1039 | test ax, CSR_RINT |
| 1069 | jz @f |
1040 | jz .not_receive |
| 1070 | 1041 | ||
| 1071 | push ebx |
- | |
| 1072 | .receiver_test_loop: |
1042 | push ebx |
| 1073 | pop ebx |
- | |
| 1074 | movzx eax, [device.cur_rx] |
1043 | .rx_loop: |
| 1075 | ; and eax, PCNET_RX_RING_MOD_MASK |
- | |
| 1076 | mov edi, eax |
- | |
| 1077 | - | ||
| 1078 | imul esi, eax, PCNET_PKT_BUF_SZ ; |
- | |
| 1079 | add esi, [device.rx_buffer] ; esi now points to rx buffer |
1044 | pop ebx |
| Line 1080... | Line 1045... | ||
| 1080 | add esi, PCNET_RX_RING_SIZE * buf_head.size |
1045 | movzx eax, [device.cur_rx] |
| - | 1046 | shl eax, 4 |
|
| Line 1081... | Line 1047... | ||
| 1081 | 1047 | lea edi, [device.rx_ring] |
|
| 1082 | shl edi, 4 ; desc * 16 (16 is size of one ring entry) |
1048 | add edi, eax ; edi now points to current rx ring entry |
| Line 1083... | Line 1049... | ||
| 1083 | add edi, [device.rx_buffer] ; edi now points to current rx ring entry |
1049 | |
| 1084 | 1050 | mov ax, [edi + descriptor.status] |
|
| Line 1085... | Line 1051... | ||
| 1085 | mov cx , [edi + buf_head.status] |
1051 | DEBUGF 1,"RX packet status: %x\n", eax:4 |
| 1086 | 1052 | ||
| Line 1087... | Line 1053... | ||
| 1087 | test cx , PCNET_RXSTAT_OWN ; If this bit is set, the controller OWN's the packet, if not, we do |
1053 | test ax, RXSTAT_OWN ; If this bit is set, the controller OWN's the packet, if not, we do |
| 1088 | jnz .abort |
1054 | jnz .not_receive |
| Line -... | Line 1055... | ||
| - | 1055 | ||
| 1089 | 1056 | test ax, RXSTAT_ENP |
|
| - | 1057 | jz .not_receive |
|
| 1090 | test cx , PCNET_RXSTAT_ENP |
1058 | |
| 1091 | jz .abort |
- | |
| 1092 | 1059 | test ax, RXSTAT_STP |
|
| 1093 | test cx , PCNET_RXSTAT_STP |
1060 | jz .not_receive |
| Line 1094... | Line 1061... | ||
| 1094 | jz .abort |
1061 | |
| 1095 | 1062 | movzx ecx, [edi + descriptor.msg_length] ; get packet length in ecx |
|
| 1096 | movzx ecx, [edi + buf_head.msg_length] ; get packet length in ecx |
1063 | sub ecx, 4 ; |
| 1097 | sub ecx, 4 ; |
1064 | |
| 1098 | - | ||
| 1099 | push ecx |
- | |
| 1100 | stdcall KernelAlloc, ecx ; Allocate a buffer to put packet into |
- | |
| 1101 | pop ecx |
- | |
| 1102 | test eax, eax ; Test if we allocated succesfully |
- | |
| Line 1103... | Line 1065... | ||
| 1103 | jz .abort ; |
1065 | ; Set pointers for ETH_input |
| 1104 | - | ||
| 1105 | ; Update stats |
1066 | push ebx |
| 1106 | add dword [device.bytes_rx], ecx |
- | |
| 1107 | adc dword [device.bytes_rx + 4], 0 |
1067 | |
| 1108 | inc dword [device.packets_rx] |
1068 | push .rx_loop ; return address |
| 1109 | 1069 | push ecx ; packet size |
|
| 1110 | push ebx |
- | |
| Line 1111... | Line 1070... | ||
| 1111 | push .receiver_test_loop ; |
1070 | push [edi + descriptor.virtual] ; packet address |
| 1112 | push ecx ; for eth_receiver |
1071 | |
| Line 1113... | Line 1072... | ||
| 1113 | push eax ; |
1072 | ; Update stats |
| 1114 | 1073 | add dword [device.bytes_rx], ecx |
|
| Line 1115... | Line 1074... | ||
| 1115 | xchg edi, eax |
1074 | adc dword [device.bytes_rx + 4], 0 |
| Line 1116... | Line 1075... | ||
| 1116 | push ecx |
1075 | inc [device.packets_rx] |
| - | 1076 | ||
| Line -... | Line 1077... | ||
| - | 1077 | ; now allocate a new buffer |
|
| - | 1078 | stdcall KernelAlloc, PKT_BUF_SZ ; Allocate a buffer for the next packet |
|
| - | 1079 | mov [edi + descriptor.virtual], eax ; set virtual address |
|
| 1117 | shr ecx, 2 |
1080 | GetRealAddr |
| - | 1081 | mov [edi + descriptor.base], eax ; and real address |
|
| - | 1082 | ||
| - | 1083 | ; mov word [edi + descriptor.length], - PKT_BUF_SZ |
|
| - | 1084 | mov [edi + descriptor.status], RXSTAT_OWN ; give it back to PCnet controller |
|
| - | 1085 | ||
| - | 1086 | inc [device.cur_rx] ; set next receive descriptor |
|
| - | 1087 | and [device.cur_rx], RX_RING_SIZE - 1 |
|
| - | 1088 | ||
| - | 1089 | jmp Eth_input |
|
| - | 1090 | ||
| - | 1091 | .not_receive: |
|
| - | 1092 | pop ax |
|
| - | 1093 | ||
| - | 1094 | test ax, CSR_TINT |
|
| - | 1095 | jz .not_transmit |
|
| - | 1096 | ||
| - | 1097 | .tx_loop: |
|
| - | 1098 | lea edi, [device.tx_ring] |
|
| - | 1099 | movzx eax, [device.last_tx] |
|
| - | 1100 | shl eax, 4 |
|
| - | 1101 | add edi, eax |
|
| - | 1102 | ||
| - | 1103 | test [edi + descriptor.status], TXCTL_OWN |
|
| Line 1118... | Line 1104... | ||
| 1118 | cld |
1104 | jnz .not_transmit |
| Line 1151... | Line 1137... | ||
| 1151 | 1137 | ||
| 1152 | mov edx, [device.io_addr] |
1138 | mov edx, [device.io_addr] |
| 1153 | add dx, 2 |
1139 | add dx, 2 |
| Line 1154... | Line 1140... | ||
| 1154 | xor eax, eax |
1140 | xor eax, eax |
| 1155 | 1141 | ||
| 1156 | mov ecx, PCNET_CSR_PAR0 |
1142 | mov ecx, CSR_PAR0 |
| 1157 | @@: |
1143 | @@: |
| 1158 | pop ax |
1144 | pop ax |
| 1159 | call [device.access_write_csr] |
1145 | call [device.write_csr] |
| 1160 | DEBUGF 1,"." |
1146 | DEBUGF 1,"." |
| 1161 | inc ecx |
1147 | inc ecx |
| Line 1162... | Line 1148... | ||
| 1162 | cmp ecx, PCNET_CSR_PAR2 |
1148 | cmp ecx, CSR_PAR2 |
| Line 1163... | Line 1149... | ||
| 1163 | jb @r |
1149 | jb @r |
| Line 1201... | Line 1187... | ||
| 1201 | align 4 |
1187 | align 4 |
| 1202 | switch_to_wio: |
1188 | switch_to_wio: |
| Line 1203... | Line 1189... | ||
| 1203 | 1189 | ||
| Line 1204... | Line 1190... | ||
| 1204 | DEBUGF 1,"Switching to 16-bit mode\n" |
1190 | DEBUGF 1,"Switching to 16-bit mode\n" |
| 1205 | 1191 | ||
| 1206 | mov [device.access_read_csr], wio_read_csr |
1192 | mov [device.read_csr], wio_read_csr |
| 1207 | mov [device.access_write_csr], wio_write_csr |
1193 | mov [device.write_csr], wio_write_csr |
| 1208 | mov [device.access_read_bcr], wio_read_bcr |
1194 | mov [device.read_bcr], wio_read_bcr |
| 1209 | mov [device.access_write_bcr], wio_write_bcr |
1195 | mov [device.write_bcr], wio_write_bcr |
| 1210 | mov [device.access_read_rap], wio_read_rap |
1196 | mov [device.read_rap], wio_read_rap |
| Line 1211... | Line 1197... | ||
| 1211 | mov [device.access_write_rap], wio_write_rap |
1197 | mov [device.write_rap], wio_write_rap |
| Line 1212... | Line 1198... | ||
| 1212 | mov [device.access_reset], wio_reset |
1198 | mov [device.sw_reset], wio_reset |
| 1213 | 1199 | ||
| Line 1214... | Line 1200... | ||
| 1214 | ret |
1200 | ret |
| Line 1215... | Line 1201... | ||
| 1215 | 1201 | ||
| 1216 | align 4 |
1202 | align 4 |
| 1217 | switch_to_dwio: |
1203 | switch_to_dwio: |
| 1218 | 1204 | ||
| 1219 | DEBUGF 1,"Switching to 32-bit mode\n" |
1205 | DEBUGF 1,"Switching to 32-bit mode\n" |
| 1220 | 1206 | ||
| 1221 | mov [device.access_read_csr], dwio_read_csr |
1207 | mov [device.read_csr], dwio_read_csr |
| Line 1222... | Line 1208... | ||
| 1222 | mov [device.access_write_csr], dwio_write_csr |
1208 | mov [device.write_csr], dwio_write_csr |
| Line 1223... | Line 1209... | ||
| 1223 | mov [device.access_read_bcr], dwio_read_bcr |
1209 | mov [device.read_bcr], dwio_read_bcr |
| 1224 | mov [device.access_write_bcr], dwio_write_bcr |
1210 | mov [device.write_bcr], dwio_write_bcr |
| 1225 | mov [device.access_read_rap], dwio_read_rap |
1211 | mov [device.read_rap], dwio_read_rap |
| 1226 | mov [device.access_write_rap], dwio_write_rap |
1212 | mov [device.write_rap], dwio_write_rap |
| 1227 | mov [device.access_reset], dwio_reset |
1213 | mov [device.sw_reset], dwio_reset |
| Line 1228... | Line 1214... | ||
| 1228 | 1214 | ||
| 1229 | ret |
1215 | ret |
| 1230 | 1216 | ||
| 1231 | 1217 | ||
| 1232 | ; ecx - index |
1218 | ; ecx - index |
| 1233 | ; return: |
1219 | ; return: |
| 1234 | ; eax - data |
1220 | ; eax - data |
| Line 1235... | Line 1221... | ||
| 1235 | align 4 |
1221 | align 4 |
| Line 1236... | Line 1222... | ||
| 1236 | wio_read_csr: |
1222 | wio_read_csr: |
| 1237 | 1223 | ||
| 1238 | add edx, PCNET_WIO_RAP |
1224 | add edx, WIO_RAP |
| 1239 | mov ax , cx |
1225 | mov ax, cx |
| Line 1240... | Line 1226... | ||
| 1240 | out dx , ax |
1226 | out dx, ax |
| 1241 | add edx, PCNET_WIO_RDP - PCNET_WIO_RAP |
1227 | add edx, WIO_RDP - WIO_RAP |
| 1242 | in ax , dx |
1228 | in ax, dx |
| 1243 | and eax, 0xffff |
1229 | and eax, 0xffff |
| 1244 | sub edx, PCNET_WIO_RDP |
1230 | sub edx, WIO_RDP |
| 1245 | 1231 | ||
| 1246 | ret |
1232 | ret |
| Line 1247... | Line 1233... | ||
| 1247 | 1233 | ||
| Line 1248... | Line 1234... | ||
| 1248 | 1234 | ||
| 1249 | ; eax - data |
1235 | ; eax - data |
| 1250 | ; ecx - index |
1236 | ; ecx - index |
| 1251 | align 4 |
1237 | align 4 |
| 1252 | wio_write_csr: |
1238 | wio_write_csr: |
| Line 1253... | Line 1239... | ||
| 1253 | 1239 | ||
| 1254 | add edx, PCNET_WIO_RAP |
1240 | add edx, WIO_RAP |
| 1255 | xchg eax, ecx |
1241 | xchg eax, ecx |
| 1256 | out dx , ax |
1242 | out dx, ax |
| 1257 | xchg eax, ecx |
1243 | xchg eax, ecx |
| 1258 | add edx, PCNET_WIO_RDP - PCNET_WIO_RAP |
1244 | add edx, WIO_RDP - WIO_RAP |
| 1259 | out dx , ax |
1245 | out dx, ax |
| Line 1260... | Line 1246... | ||
| 1260 | sub edx, PCNET_WIO_RDP |
1246 | sub edx, WIO_RDP |
| Line 1261... | Line 1247... | ||
| 1261 | 1247 | ||
| 1262 | ret |
1248 | ret |
| 1263 | 1249 | ||
| 1264 | 1250 | ||
| Line 1265... | Line 1251... | ||
| 1265 | ; ecx - index |
1251 | ; ecx - index |
| 1266 | ; return: |
1252 | ; return: |
| 1267 | ; eax - data |
1253 | ; eax - data |
| 1268 | align 4 |
1254 | align 4 |
| 1269 | wio_read_bcr: |
1255 | wio_read_bcr: |
| 1270 | 1256 | ||
| 1271 | add edx, PCNET_WIO_RAP |
1257 | add edx, WIO_RAP |
| Line 1272... | Line 1258... | ||
| 1272 | mov ax , cx |
1258 | mov ax, cx |
| Line 1273... | Line 1259... | ||
| 1273 | out dx , ax |
1259 | out dx, ax |
| 1274 | add edx, PCNET_WIO_BDP - PCNET_WIO_RAP |
1260 | add edx, WIO_BDP - WIO_RAP |
| Line 1275... | Line 1261... | ||
| 1275 | in ax , dx |
1261 | in ax, dx |
| 1276 | and eax, 0xffff |
1262 | and eax, 0xffff |
| 1277 | sub edx, PCNET_WIO_BDP |
1263 | sub edx, WIO_BDP |
| 1278 | 1264 | ||
| Line 1279... | Line 1265... | ||
| 1279 | ret |
1265 | ret |
| Line 1280... | Line 1266... | ||
| 1280 | 1266 | ||
| 1281 | 1267 | ||
| 1282 | ; eax - data |
1268 | ; eax - data |
| Line 1283... | Line 1269... | ||
| 1283 | ; ecx - index |
1269 | ; ecx - index |
| 1284 | align 4 |
1270 | align 4 |
| 1285 | wio_write_bcr: |
1271 | wio_write_bcr: |
| Line 1286... | Line 1272... | ||
| 1286 | 1272 | ||
| Line 1287... | Line 1273... | ||
| 1287 | add edx, PCNET_WIO_RAP |
1273 | add edx, WIO_RAP |
| 1288 | xchg eax, ecx |
1274 | xchg eax, ecx |
| Line 1289... | Line 1275... | ||
| 1289 | out dx , ax |
1275 | out dx, ax |
| 1290 | xchg eax, ecx |
1276 | xchg eax, ecx |
| 1291 | add edx, PCNET_WIO_BDP - PCNET_WIO_RAP |
1277 | add edx, WIO_BDP - WIO_RAP |
| 1292 | out dx , ax |
1278 | out dx, ax |
| 1293 | sub edx, PCNET_WIO_BDP |
1279 | sub edx, WIO_BDP |
| Line 1294... | Line 1280... | ||
| 1294 | 1280 | ||
| Line 1331... | Line 1317... | ||
| 1331 | ; return: |
1317 | ; return: |
| 1332 | ; eax - data |
1318 | ; eax - data |
| 1333 | align 4 |
1319 | align 4 |
| 1334 | dwio_read_csr: |
1320 | dwio_read_csr: |
| Line 1335... | Line 1321... | ||
| 1335 | 1321 | ||
| 1336 | add edx, PCNET_DWIO_RAP |
1322 | add edx, DWIO_RAP |
| 1337 | mov eax, ecx |
1323 | mov eax, ecx |
| 1338 | out dx , eax |
1324 | out dx, eax |
| 1339 | add edx, PCNET_DWIO_RDP - PCNET_DWIO_RAP |
1325 | add edx, DWIO_RDP - DWIO_RAP |
| 1340 | in eax, dx |
1326 | in eax, dx |
| 1341 | and eax, 0xffff |
1327 | and eax, 0xffff |
| Line 1342... | Line 1328... | ||
| 1342 | sub edx, PCNET_DWIO_RDP |
1328 | sub edx, DWIO_RDP |
| Line 1343... | Line 1329... | ||
| 1343 | 1329 | ||
| 1344 | ret |
1330 | ret |
| 1345 | 1331 | ||
| 1346 | 1332 | ||
| Line 1347... | Line 1333... | ||
| 1347 | ; ecx - index |
1333 | ; ecx - index |
| 1348 | ; eax - data |
1334 | ; eax - data |
| 1349 | align 4 |
1335 | align 4 |
| 1350 | dwio_write_csr: |
1336 | dwio_write_csr: |
| 1351 | 1337 | ||
| 1352 | add edx, PCNET_DWIO_RAP |
1338 | add edx, DWIO_RAP |
| 1353 | xchg eax, ecx |
1339 | xchg eax, ecx |
| Line 1354... | Line 1340... | ||
| 1354 | out dx , eax |
1340 | out dx, eax |
| Line 1355... | Line 1341... | ||
| 1355 | add edx, PCNET_DWIO_RDP - PCNET_DWIO_RAP |
1341 | add edx, DWIO_RDP - DWIO_RAP |
| 1356 | xchg eax, ecx |
1342 | xchg eax, ecx |
| 1357 | out dx , eax |
1343 | out dx, eax |
| 1358 | sub edx, PCNET_DWIO_RDP |
1344 | sub edx, DWIO_RDP |
| 1359 | 1345 | ||
| Line 1360... | Line 1346... | ||
| 1360 | ret |
1346 | ret |
| 1361 | 1347 | ||
| 1362 | ; ecx - index |
1348 | ; ecx - index |
| 1363 | ; return: |
1349 | ; return: |
| 1364 | ; eax - data |
1350 | ; eax - data |
| 1365 | align 4 |
1351 | align 4 |
| 1366 | dwio_read_bcr: |
1352 | dwio_read_bcr: |
| Line 1367... | Line 1353... | ||
| 1367 | 1353 | ||
| Line 1368... | Line 1354... | ||
| 1368 | add edx, PCNET_DWIO_RAP |
1354 | add edx, DWIO_RAP |
| 1369 | mov eax, ecx |
1355 | mov eax, ecx |
| 1370 | out dx , eax |
1356 | out dx, eax |
| 1371 | add edx, PCNET_DWIO_BDP - PCNET_DWIO_RAP |
1357 | add edx, DWIO_BDP - DWIO_RAP |
| Line 1372... | Line 1358... | ||
| 1372 | in eax, dx |
1358 | in eax, dx |
| 1373 | and eax, 0xffff |
1359 | and eax, 0xffff |
| 1374 | sub edx, PCNET_DWIO_BDP |
1360 | sub edx, DWIO_BDP |
| 1375 | 1361 | ||
| 1376 | ret |
1362 | ret |
| 1377 | 1363 | ||
| 1378 | 1364 | ||
| Line 1379... | Line 1365... | ||
| 1379 | ; ecx - index |
1365 | ; ecx - index |
| Line 1380... | Line 1366... | ||
| 1380 | ; eax - data |
1366 | ; eax - data |
| 1381 | align 4 |
1367 | align 4 |
| Line 1382... | Line 1368... | ||
| 1382 | dwio_write_bcr: |
1368 | dwio_write_bcr: |
| 1383 | 1369 | ||
| 1384 | add edx, PCNET_DWIO_RAP |
1370 | add edx, DWIO_RAP |
| 1385 | xchg eax, ecx |
1371 | xchg eax, ecx |
| Line 1386... | Line 1372... | ||
| 1386 | out dx , eax |
1372 | out dx, eax |
| Line 1387... | Line 1373... | ||
| 1387 | add edx, PCNET_DWIO_BDP - PCNET_DWIO_RAP |
1373 | add edx, DWIO_BDP - DWIO_RAP |
| 1388 | xchg eax, ecx |
1374 | xchg eax, ecx |
| 1389 | out dx , eax |
1375 | out dx, eax |
| Line 1390... | Line 1376... | ||
| 1390 | sub edx, PCNET_DWIO_BDP |
1376 | sub edx, DWIO_BDP |
| 1391 | 1377 | ||
| 1392 | ret |
1378 | ret |
| Line 1393... | Line 1379... | ||
| 1393 | 1379 | ||
| Line 1394... | Line 1380... | ||
| 1394 | align 4 |
1380 | align 4 |
| 1395 | dwio_read_rap: |
1381 | dwio_read_rap: |
| Line 1396... | Line 1382... | ||
| 1396 | 1382 | ||
| 1397 | add edx, PCNET_DWIO_RAP |
1383 | add edx, DWIO_RAP |
| 1398 | in eax, dx |
1384 | in eax, dx |
| 1399 | and eax, 0xffff |
1385 | and eax, 0xffff |
| 1400 | sub edx, PCNET_DWIO_RAP |
1386 | sub edx, DWIO_RAP |
| Line 1401... | Line 1387... | ||
| 1401 | 1387 | ||
| Line 1440... | Line 1426... | ||
| 1440 | device_l7 db "PCnet/FAST III 79C973",0 |
1426 | device_l7 db "PCnet/FAST III 79C973",0 |
| 1441 | device_l8 db "PCnet/Home 79C978",0 |
1427 | device_l8 db "PCnet/Home 79C978",0 |
| 1442 | device_l9 db "PCnet/FAST III 79C975",0 |
1428 | device_l9 db "PCnet/FAST III 79C975",0 |
| Line 1443... | Line 1429... | ||
| 1443 | 1429 | ||
| 1444 | options_mapping: |
1430 | options_mapping: |
| 1445 | dd PCNET_PORT_ASEL ; 0 Auto-select |
1431 | dd PORT_ASEL ; 0 Auto-select |
| 1446 | dd PCNET_PORT_AUI ; 1 BNC/AUI |
1432 | dd PORT_AUI ; 1 BNC/AUI |
| 1447 | dd PCNET_PORT_AUI ; 2 AUI/BNC |
1433 | dd PORT_AUI ; 2 AUI/BNC |
| 1448 | dd PCNET_PORT_ASEL ; 3 not supported |
1434 | dd PORT_ASEL ; 3 not supported |
| 1449 | dd PCNET_PORT_10BT or PCNET_PORT_FD ; 4 10baseT-FD |
1435 | dd PORT_10BT or PORT_FD ; 4 10baseT-FD |
| 1450 | dd PCNET_PORT_ASEL ; 5 not supported |
1436 | dd PORT_ASEL ; 5 not supported |
| 1451 | dd PCNET_PORT_ASEL ; 6 not supported |
1437 | dd PORT_ASEL ; 6 not supported |
| 1452 | dd PCNET_PORT_ASEL ; 7 not supported |
1438 | dd PORT_ASEL ; 7 not supported |
| 1453 | dd PCNET_PORT_ASEL ; 8 not supported |
1439 | dd PORT_ASEL ; 8 not supported |
| 1454 | dd PCNET_PORT_MII ; 9 MII 10baseT |
1440 | dd PORT_MII ; 9 MII 10baseT |
| 1455 | dd PCNET_PORT_MII or PCNET_PORT_FD ; 10 MII 10baseT-FD |
1441 | dd PORT_MII or PORT_FD ; 10 MII 10baseT-FD |
| 1456 | dd PCNET_PORT_MII ; 11 MII (autosel) |
1442 | dd PORT_MII ; 11 MII (autosel) |
| 1457 | dd PCNET_PORT_10BT ; 12 10BaseT |
1443 | dd PORT_10BT ; 12 10BaseT |
| 1458 | dd PCNET_PORT_MII or PCNET_PORT_100 ; 13 MII 100BaseTx |
1444 | dd PORT_MII or PORT_100 ; 13 MII 100BaseTx |
| 1459 | dd PCNET_PORT_MII or PCNET_PORT_100 or PCNET_PORT_FD ; 14 MII 100BaseTx-FD |
1445 | dd PORT_MII or PORT_100 or PORT_FD ; 14 MII 100BaseTx-FD |
| Line 1460... | Line 1446... | ||
| 1460 | dd PCNET_PORT_ASEL ; 15 not supported |
1446 | dd PORT_ASEL ; 15 not supported |
| Line 1461... | Line 1447... | ||
| 1461 | 1447 | ||