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Rev 1893 Rev 2852
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;;                                                                 ;;
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;;                                                                 ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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format MS COFF
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format MS COFF
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	API_VERSION		equ 0x01000100
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        API_VERSION             =   0x01000100
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	DRIVER_VERSION		equ 5
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        DRIVER_VERSION          =   5
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	MAX_DEVICES		equ 16
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        MAX_DEVICES             =   16
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	DEBUG			equ 1
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        DEBUG                   =   1
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	__DEBUG__		equ 1
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        __DEBUG__               =   1
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	__DEBUG_LEVEL__ 	equ 2
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        __DEBUG_LEVEL__         =   2
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	W_MAX_TIMEOUT		equ 0x0FFF	; max time out delay time
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        W_MAX_TIMEOUT           =   0x0FFF      ; max time out delay time
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	TX_TIMEOUT		equ 6000	; Time before concluding the transmitter is hung, in ms
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        TX_TIMEOUT              =   6000        ; Time before concluding the transmitter is hung, in ms
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	TX_RING_SIZE		equ 4		; RING sizes must be a power of 2
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        TX_RING_SIZE            =   4           ; RING sizes must be a power of 2
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	RX_RING_SIZE		equ 4
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        RX_RING_SIZE            =   4
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	RX_BUF_LEN_IDX		equ 3		; 0==8K, 1==16K, 2==32K, 3==64K
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        RX_BUF_LEN_IDX          =   3           ; 0==8K, 1==16K, 2==32K, 3==64K
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public service_proc
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public service_proc
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public version
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public version
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; Operational parameters that usually are not changed.
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; Operational parameters that usually are not changed.
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PHY1_ADDR	equ 1	    ;For MAC1
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PHY1_ADDR       =   1       ;For MAC1
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PHY2_ADDR	equ 3	    ;For MAC2
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PHY2_ADDR       =   3       ;For MAC2
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PHY_MODE	equ 0x3100  ;PHY CHIP Register 0
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PHY_MODE        =   0x3100  ;PHY CHIP Register 0
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PHY_CAP 	equ 0x01E1  ;PHY CHIP Register 4
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PHY_CAP         =   0x01E1  ;PHY CHIP Register 4
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;**************************************************************************
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;**************************************************************************
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; RDC R6040 Register Definitions
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; RDC R6040 Register Definitions
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;**************************************************************************
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;**************************************************************************
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MCR0		equ 0x00    ;Control register 0
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MCR0            =   0x00    ;Control register 0
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MCR1		equ 0x01    ;Control register 1
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MCR1            =   0x01    ;Control register 1
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MAC_RST 	equ 0x0001  ;Reset the MAC
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MAC_RST         =   0x0001  ;Reset the MAC
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MBCR		equ 0x08    ;Bus control
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MBCR            =   0x08    ;Bus control
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MT_ICR		equ 0x0C    ;TX interrupt control
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MT_ICR          =   0x0C    ;TX interrupt control
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MR_ICR		equ 0x10    ;RX interrupt control
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MR_ICR          =   0x10    ;RX interrupt control
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MTPR		equ 0x14    ;TX poll command register
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MTPR            =   0x14    ;TX poll command register
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MR_BSR		equ 0x18    ;RX buffer size
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MR_BSR          =   0x18    ;RX buffer size
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MR_DCR		equ 0x1A    ;RX descriptor control
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MR_DCR          =   0x1A    ;RX descriptor control
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MLSR		equ 0x1C    ;Last status
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MLSR            =   0x1C    ;Last status
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MMDIO		equ 0x20    ;MDIO control register
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MMDIO           =   0x20    ;MDIO control register
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MDIO_WRITE	equ 0x4000  ;MDIO write
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MDIO_WRITE      =   0x4000  ;MDIO write
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MDIO_READ	equ 0x2000  ;MDIO read
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MDIO_READ       =   0x2000  ;MDIO read
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MMRD		equ 0x24    ;MDIO read data register
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MMRD            =   0x24    ;MDIO read data register
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MMWD		equ 0x28    ;MDIO write data register
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MMWD            =   0x28    ;MDIO write data register
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MTD_SA0 	equ 0x2C    ;TX descriptor start address 0
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MTD_SA0         =   0x2C    ;TX descriptor start address 0
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MTD_SA1 	equ 0x30    ;TX descriptor start address 1
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MTD_SA1         =   0x30    ;TX descriptor start address 1
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MRD_SA0 	equ 0x34    ;RX descriptor start address 0
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MRD_SA0         =   0x34    ;RX descriptor start address 0
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MRD_SA1 	equ 0x38    ;RX descriptor start address 1
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MRD_SA1         =   0x38    ;RX descriptor start address 1
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MISR		equ 0x3C    ;Status register
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MISR            =   0x3C    ;Status register
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MIER		equ 0x40    ;INT enable register
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MIER            =   0x40    ;INT enable register
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MSK_INT 	equ 0x0000  ;Mask off interrupts
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MSK_INT         =   0x0000  ;Mask off interrupts
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RX_FINISH	equ 0x0001  ;RX finished
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RX_FINISH       =   0x0001  ;RX finished
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RX_NO_DESC	equ 0x0002  ;No RX descriptor available
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RX_NO_DESC      =   0x0002  ;No RX descriptor available
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RX_FIFO_FULL	equ 0x0004  ;RX FIFO full
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RX_FIFO_FULL    =   0x0004  ;RX FIFO full
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RX_EARLY	equ 0x0008  ;RX early
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RX_EARLY        =   0x0008  ;RX early
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TX_FINISH	equ 0x0010  ;TX finished
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TX_FINISH       =   0x0010  ;TX finished
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TX_EARLY	equ 0x0080  ;TX early
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TX_EARLY        =   0x0080  ;TX early
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EVENT_OVRFL	equ 0x0100  ;Event counter overflow
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EVENT_OVRFL     =   0x0100  ;Event counter overflow
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LINK_CHANGED	equ 0x0200  ;PHY link changed
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LINK_CHANGED    =   0x0200  ;PHY link changed
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ME_CISR 	equ 0x44    ;Event counter INT status
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ME_CISR         =   0x44    ;Event counter INT status
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ME_CIER 	equ 0x48    ;Event counter INT enable
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ME_CIER         =   0x48    ;Event counter INT enable
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MR_CNT		equ 0x50    ;Successfully received packet counter
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MR_CNT          =   0x50    ;Successfully received packet counter
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ME_CNT0 	equ 0x52    ;Event counter 0
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ME_CNT0         =   0x52    ;Event counter 0
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ME_CNT1 	equ 0x54    ;Event counter 1
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ME_CNT1         =   0x54    ;Event counter 1
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ME_CNT2 	equ 0x56    ;Event counter 2
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ME_CNT2         =   0x56    ;Event counter 2
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ME_CNT3 	equ 0x58    ;Event counter 3
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ME_CNT3         =   0x58    ;Event counter 3
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MT_CNT		equ 0x5A    ;Successfully transmit packet counter
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MT_CNT          =   0x5A    ;Successfully transmit packet counter
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ME_CNT4 	equ 0x5C    ;Event counter 4
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ME_CNT4         =   0x5C    ;Event counter 4
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MP_CNT		equ 0x5E    ;Pause frame counter register
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MP_CNT          =   0x5E    ;Pause frame counter register
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MAR0		equ 0x60    ;Hash table 0
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MAR0            =   0x60    ;Hash table 0
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MAR1		equ 0x62    ;Hash table 1
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MAR1            =   0x62    ;Hash table 1
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MAR2		equ 0x64    ;Hash table 2
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MAR2            =   0x64    ;Hash table 2
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MAR3		equ 0x66    ;Hash table 3
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MAR3            =   0x66    ;Hash table 3
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MID_0L		equ 0x68    ;Multicast address MID0 Low
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MID_0L          =   0x68    ;Multicast address MID0 Low
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MID_0M		equ 0x6A    ;Multicast address MID0 Medium
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MID_0M          =   0x6A    ;Multicast address MID0 Medium
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MID_0H		equ 0x6C    ;Multicast address MID0 High
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MID_0H          =   0x6C    ;Multicast address MID0 High
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MID_1L		equ 0x70    ;MID1 Low
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MID_1L          =   0x70    ;MID1 Low
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MID_1M		equ 0x72    ;MID1 Medium
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MID_1M          =   0x72    ;MID1 Medium
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MID_1H		equ 0x74    ;MID1 High
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MID_1H          =   0x74    ;MID1 High
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MID_2L		equ 0x78    ;MID2 Low
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MID_2L          =   0x78    ;MID2 Low
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MID_2M		equ 0x7A    ;MID2 Medium
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MID_2M          =   0x7A    ;MID2 Medium
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MID_2H		equ 0x7C    ;MID2 High
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MID_2H          =   0x7C    ;MID2 High
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MID_3L		equ 0x80    ;MID3 Low
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MID_3L          =   0x80    ;MID3 Low
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MID_3M		equ 0x82    ;MID3 Medium
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MID_3M          =   0x82    ;MID3 Medium
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MID_3H		equ 0x84    ;MID3 High
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MID_3H          =   0x84    ;MID3 High
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PHY_CC		equ 0x88    ;PHY status change configuration register
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PHY_CC          =   0x88    ;PHY status change configuration register
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PHY_ST		equ 0x8A    ;PHY status register
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PHY_ST          =   0x8A    ;PHY status register
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MAC_SM		equ 0xAC    ;MAC status machine
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MAC_SM          =   0xAC    ;MAC status machine
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MAC_ID		equ 0xBE    ;Identifier register
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MAC_ID          =   0xBE    ;Identifier register
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MAX_BUF_SIZE	equ 0x600   ;1536
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MAX_BUF_SIZE    =   0x600   ;1536
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MBCR_DEFAULT	equ 0x012A  ;MAC Bus Control Register
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MBCR_DEFAULT    =   0x012A  ;MAC Bus Control Register
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MCAST_MAX	equ 3	    ;Max number multicast addresses to filter
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MCAST_MAX       =   3       ;Max number multicast addresses to filter
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;Descriptor status
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;Descriptor status
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DSC_OWNER_MAC	equ 0x8000  ;MAC is the owner of this descriptor
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DSC_OWNER_MAC   =   0x8000  ;MAC is the owner of this descriptor
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DSC_RX_OK	equ 0x4000  ;RX was successfull
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DSC_RX_OK       =   0x4000  ;RX was successfull
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DSC_RX_ERR	equ 0x0800  ;RX PHY error
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DSC_RX_ERR      =   0x0800  ;RX PHY error
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DSC_RX_ERR_DRI	equ 0x0400  ;RX dribble packet
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DSC_RX_ERR_DRI  =   0x0400  ;RX dribble packet
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DSC_RX_ERR_BUF	equ 0x0200  ;RX length exceeds buffer size
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DSC_RX_ERR_BUF  =   0x0200  ;RX length exceeds buffer size
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DSC_RX_ERR_LONG equ 0x0100  ;RX length > maximum packet length
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DSC_RX_ERR_LONG =   0x0100  ;RX length > maximum packet length
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DSC_RX_ERR_RUNT equ 0x0080  ;RX packet length < 64 byte
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DSC_RX_ERR_RUNT =   0x0080  ;RX packet length < 64 byte
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DSC_RX_ERR_CRC	equ 0x0040  ;RX CRC error
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DSC_RX_ERR_CRC  =   0x0040  ;RX CRC error
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DSC_RX_BCAST	equ 0x0020  ;RX broadcast (no error)
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DSC_RX_BCAST    =   0x0020  ;RX broadcast (no error)
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DSC_RX_MCAST	equ 0x0010  ;RX multicast (no error)
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DSC_RX_MCAST    =   0x0010  ;RX multicast (no error)
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DSC_RX_MCH_HIT	equ 0x0008  ;RX multicast hit in hash table (no error)
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DSC_RX_MCH_HIT  =   0x0008  ;RX multicast hit in hash table (no error)
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DSC_RX_MIDH_HIT equ 0x0004  ;RX MID table hit (no error)
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DSC_RX_MIDH_HIT =   0x0004  ;RX MID table hit (no error)
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DSC_RX_IDX_MID_MASK  equ 3  ;RX mask for the index of matched MIDx
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DSC_RX_IDX_MID_MASK  =   3  ;RX mask for the index of matched MIDx
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;PHY settings
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;PHY settings
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ICPLUS_PHY_ID	equ 0x0243
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ICPLUS_PHY_ID   =   0x0243
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RX_INTS 	equ RX_FIFO_FULL or RX_NO_DESC or RX_FINISH
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RX_INTS         =   RX_FIFO_FULL or RX_NO_DESC or RX_FINISH