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23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
- | 28 | //#include |
|
28 | //#include |
29 | //#include |
29 | #include "drmP.h" |
30 | #include "drmP.h" |
30 | #include "radeon.h" |
31 | #include "radeon.h" |
31 | #include "radeon_drm.h" |
32 | #include "radeon_drm.h" |
32 | #include "rv770d.h" |
33 | #include "rv770d.h" |
33 | #include "atom.h" |
34 | #include "atom.h" |
34 | #include "avivod.h" |
35 | #include "avivod.h" |
Line 35... | Line -... | ||
35 | - | ||
36 | #include |
- | |
37 | - | ||
38 | 36 | ||
39 | #define R700_PFP_UCODE_SIZE 848 |
37 | #define R700_PFP_UCODE_SIZE 848 |
Line 40... | Line 38... | ||
40 | #define R700_PM4_UCODE_SIZE 1360 |
38 | #define R700_PM4_UCODE_SIZE 1360 |
41 | 39 | ||
Line 92... | Line 90... | ||
92 | } |
90 | } |
Line 93... | Line 91... | ||
93 | 91 | ||
94 | void rv770_pcie_gart_disable(struct radeon_device *rdev) |
92 | void rv770_pcie_gart_disable(struct radeon_device *rdev) |
95 | { |
93 | { |
96 | u32 tmp; |
94 | u32 tmp; |
Line 97... | Line 95... | ||
97 | int i; |
95 | int i, r; |
98 | 96 | ||
99 | /* Disable all tables */ |
97 | /* Disable all tables */ |
Line 230... | Line 228... | ||
230 | void r700_cp_stop(struct radeon_device *rdev) |
228 | void r700_cp_stop(struct radeon_device *rdev) |
231 | { |
229 | { |
232 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
230 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
233 | } |
231 | } |
Line 234... | Line 232... | ||
234 | 232 | ||
235 | 233 | #if 0 |
|
236 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
234 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
237 | { |
235 | { |
238 | const __be32 *fw_data; |
236 | const __be32 *fw_data; |
Line 265... | Line 263... | ||
265 | WREG32(CP_ME_RAM_WADDR, 0); |
263 | WREG32(CP_ME_RAM_WADDR, 0); |
266 | WREG32(CP_ME_RAM_RADDR, 0); |
264 | WREG32(CP_ME_RAM_RADDR, 0); |
267 | return 0; |
265 | return 0; |
268 | } |
266 | } |
Line -... | Line 267... | ||
- | 267 | ||
Line 269... | Line 268... | ||
269 | 268 | #endif |
|
270 | 269 | ||
271 | /* |
270 | /* |
272 | * Core functions |
271 | * Core functions |
Line 775... | Line 774... | ||
775 | int rv770_mc_init(struct radeon_device *rdev) |
774 | int rv770_mc_init(struct radeon_device *rdev) |
776 | { |
775 | { |
777 | fixed20_12 a; |
776 | fixed20_12 a; |
778 | u32 tmp; |
777 | u32 tmp; |
779 | int chansize, numchan; |
778 | int chansize, numchan; |
780 | int r; |
- | |
Line 781... | Line 779... | ||
781 | 779 | ||
782 | /* Get VRAM informations */ |
780 | /* Get VRAM informations */ |
783 | rdev->mc.vram_is_ddr = true; |
781 | rdev->mc.vram_is_ddr = true; |
784 | tmp = RREG32(MC_ARB_RAMCFG); |
782 | tmp = RREG32(MC_ARB_RAMCFG); |
Line 818... | Line 816... | ||
818 | 816 | ||
819 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) |
817 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) |
Line 820... | Line 818... | ||
820 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
818 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
821 | - | ||
822 | if (rdev->flags & RADEON_IS_AGP) { |
- | |
823 | r = radeon_agp_init(rdev); |
- | |
824 | if (r) |
819 | |
825 | return r; |
820 | if (rdev->flags & RADEON_IS_AGP) { |
826 | /* gtt_size is setup by radeon_agp_init */ |
821 | /* gtt_size is setup by radeon_agp_init */ |
827 | rdev->mc.gtt_location = rdev->mc.agp_base; |
822 | rdev->mc.gtt_location = rdev->mc.agp_base; |
828 | tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; |
823 | tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; |
Line 933... | Line 928... | ||
933 | } |
928 | } |
934 | r = radeon_atombios_init(rdev); |
929 | r = radeon_atombios_init(rdev); |
935 | if (r) |
930 | if (r) |
936 | return r; |
931 | return r; |
937 | /* Post card if necessary */ |
932 | /* Post card if necessary */ |
938 | if (!r600_card_posted(rdev) && rdev->bios) { |
933 | if (!r600_card_posted(rdev)) { |
- | 934 | if (!rdev->bios) { |
|
- | 935 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
|
- | 936 | return -EINVAL; |
|
- | 937 | } |
|
939 | DRM_INFO("GPU not posted. posting now...\n"); |
938 | DRM_INFO("GPU not posted. posting now...\n"); |
940 | atom_asic_init(rdev->mode_info.atom_context); |
939 | atom_asic_init(rdev->mode_info.atom_context); |
941 | } |
940 | } |
942 | /* Initialize scratch registers */ |
941 | /* Initialize scratch registers */ |
943 | r600_scratch_init(rdev); |
942 | r600_scratch_init(rdev); |
Line 952... | Line 951... | ||
952 | radeon_pm_init(rdev); |
951 | radeon_pm_init(rdev); |
953 | /* Fence driver */ |
952 | /* Fence driver */ |
954 | // r = radeon_fence_driver_init(rdev); |
953 | // r = radeon_fence_driver_init(rdev); |
955 | // if (r) |
954 | // if (r) |
956 | // return r; |
955 | // return r; |
- | 956 | if (rdev->flags & RADEON_IS_AGP) { |
|
- | 957 | r = radeon_agp_init(rdev); |
|
- | 958 | if (r) |
|
- | 959 | radeon_agp_disable(rdev); |
|
- | 960 | } |
|
957 | r = rv770_mc_init(rdev); |
961 | r = rv770_mc_init(rdev); |
958 | if (r) |
962 | if (r) |
959 | return r; |
963 | return r; |
960 | /* Memory manager */ |
964 | /* Memory manager */ |
961 | r = radeon_object_init(rdev); |
965 | r = radeon_bo_init(rdev); |
962 | if (r) |
966 | if (r) |
963 | return r; |
967 | return r; |
964 | // rdev->cp.ring_obj = NULL; |
- | |
965 | // r600_ring_init(rdev, 1024 * 1024); |
- | |
Line 966... | Line 968... | ||
966 | 968 | ||
967 | // if (!rdev->me_fw || !rdev->pfp_fw) { |
969 | // if (!rdev->me_fw || !rdev->pfp_fw) { |
968 | // r = r600_cp_init_microcode(rdev); |
970 | // r = r600_cp_init_microcode(rdev); |
969 | // if (r) { |
971 | // if (r) { |