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Rev 1404 | Rev 1430 | ||
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Line 66... | Line 66... | ||
66 | } |
66 | } |
Line 67... | Line 67... | ||
67 | 67 | ||
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
Line -... | Line 69... | ||
- | 69 | } |
|
- | 70 | ||
- | 71 | static void evergreen_crtc_load_lut(struct drm_crtc *crtc) |
|
- | 72 | { |
|
- | 73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
|
- | 74 | struct drm_device *dev = crtc->dev; |
|
- | 75 | struct radeon_device *rdev = dev->dev_private; |
|
- | 76 | int i; |
|
- | 77 | ||
- | 78 | DRM_DEBUG("%d\n", radeon_crtc->crtc_id); |
|
- | 79 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
|
- | 80 | ||
- | 81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
|
- | 82 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
|
- | 83 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
|
- | 84 | ||
- | 85 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
|
- | 86 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
|
- | 87 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
|
- | 88 | ||
- | 89 | WREG32(EVERGREEN_DC_LUT_RW_MODE, radeon_crtc->crtc_id); |
|
- | 90 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007); |
|
- | 91 | ||
- | 92 | WREG32(EVERGREEN_DC_LUT_RW_INDEX, 0); |
|
- | 93 | for (i = 0; i < 256; i++) { |
|
- | 94 | WREG32(EVERGREEN_DC_LUT_30_COLOR, |
|
- | 95 | (radeon_crtc->lut_r[i] << 20) | |
|
- | 96 | (radeon_crtc->lut_g[i] << 10) | |
|
- | 97 | (radeon_crtc->lut_b[i] << 0)); |
|
- | 98 | } |
|
69 | } |
99 | } |
70 | 100 | ||
71 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
101 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
72 | { |
102 | { |
73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
103 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Line 98... | Line 128... | ||
98 | struct radeon_device *rdev = dev->dev_private; |
128 | struct radeon_device *rdev = dev->dev_private; |
Line 99... | Line 129... | ||
99 | 129 | ||
100 | if (!crtc->enabled) |
130 | if (!crtc->enabled) |
Line -... | Line 131... | ||
- | 131 | return; |
|
- | 132 | ||
101 | return; |
133 | if (ASIC_IS_DCE4(rdev)) |
102 | 134 | evergreen_crtc_load_lut(crtc); |
|
103 | if (ASIC_IS_AVIVO(rdev)) |
135 | else if (ASIC_IS_AVIVO(rdev)) |
104 | avivo_crtc_load_lut(crtc); |
136 | avivo_crtc_load_lut(crtc); |
105 | else |
137 | else |
Line 359... | Line 391... | ||
359 | return ret; |
391 | return ret; |
360 | } |
392 | } |
Line 361... | Line 393... | ||
361 | 393 | ||
362 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
394 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
- | 395 | { |
|
- | 396 | struct drm_device *dev = radeon_connector->base.dev; |
|
363 | { |
397 | struct radeon_device *rdev = dev->dev_private; |
Line 364... | Line 398... | ||
364 | int ret = 0; |
398 | int ret = 0; |
365 | 399 | ||
366 | if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
400 | if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
Line 371... | Line 405... | ||
371 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); |
405 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); |
372 | } |
406 | } |
373 | if (!radeon_connector->ddc_bus) |
407 | if (!radeon_connector->ddc_bus) |
374 | return -1; |
408 | return -1; |
375 | if (!radeon_connector->edid) { |
409 | if (!radeon_connector->edid) { |
376 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); |
- | |
377 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
410 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
378 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); |
- | |
379 | } |
411 | } |
380 | - | ||
- | 412 | /* some servers provide a hardcoded edid in rom for KVMs */ |
|
- | 413 | if (!radeon_connector->edid) |
|
- | 414 | radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev); |
|
381 | if (radeon_connector->edid) { |
415 | if (radeon_connector->edid) { |
382 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
416 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
383 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
417 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
384 | return ret; |
418 | return ret; |
385 | } |
419 | } |
Line 393... | Line 427... | ||
393 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
427 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
394 | int ret = 0; |
428 | int ret = 0; |
Line 395... | Line 429... | ||
395 | 429 | ||
396 | if (!radeon_connector->ddc_bus) |
430 | if (!radeon_connector->ddc_bus) |
397 | return -1; |
- | |
398 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); |
431 | return -1; |
399 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
- | |
400 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); |
432 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
401 | if (edid) { |
433 | if (edid) { |
402 | kfree(edid); |
434 | kfree(edid); |
403 | } |
435 | } |
404 | return ret; |
436 | return ret; |
Line 412... | Line 444... | ||
412 | 444 | ||
413 | mod = do_div(n, d); |
445 | mod = do_div(n, d); |
414 | return n; |
446 | return n; |
Line 415... | Line 447... | ||
415 | } |
447 | } |
416 | 448 | ||
417 | void radeon_compute_pll(struct radeon_pll *pll, |
449 | static void radeon_compute_pll_legacy(struct radeon_pll *pll, |
418 | uint64_t freq, |
450 | uint64_t freq, |
419 | uint32_t *dot_clock_p, |
451 | uint32_t *dot_clock_p, |
420 | uint32_t *fb_div_p, |
452 | uint32_t *fb_div_p, |
Line 578... | Line 610... | ||
578 | *frac_fb_div_p = best_frac_feedback_div; |
610 | *frac_fb_div_p = best_frac_feedback_div; |
579 | *ref_div_p = best_ref_div; |
611 | *ref_div_p = best_ref_div; |
580 | *post_div_p = best_post_div; |
612 | *post_div_p = best_post_div; |
581 | } |
613 | } |
Line -... | Line 614... | ||
- | 614 | ||
- | 615 | static bool |
|
- | 616 | calc_fb_div(struct radeon_pll *pll, |
|
- | 617 | uint32_t freq, |
|
- | 618 | uint32_t post_div, |
|
- | 619 | uint32_t ref_div, |
|
- | 620 | uint32_t *fb_div, |
|
- | 621 | uint32_t *fb_div_frac) |
|
- | 622 | { |
|
- | 623 | fixed20_12 feedback_divider, a, b; |
|
- | 624 | u32 vco_freq; |
|
- | 625 | ||
- | 626 | vco_freq = freq * post_div; |
|
- | 627 | /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */ |
|
- | 628 | a.full = rfixed_const(pll->reference_freq); |
|
- | 629 | feedback_divider.full = rfixed_const(vco_freq); |
|
- | 630 | feedback_divider.full = rfixed_div(feedback_divider, a); |
|
- | 631 | a.full = rfixed_const(ref_div); |
|
- | 632 | feedback_divider.full = rfixed_mul(feedback_divider, a); |
|
- | 633 | ||
- | 634 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
|
- | 635 | /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */ |
|
- | 636 | a.full = rfixed_const(10); |
|
- | 637 | feedback_divider.full = rfixed_mul(feedback_divider, a); |
|
- | 638 | feedback_divider.full += rfixed_const_half(0); |
|
- | 639 | feedback_divider.full = rfixed_floor(feedback_divider); |
|
- | 640 | feedback_divider.full = rfixed_div(feedback_divider, a); |
|
- | 641 | ||
- | 642 | /* *fb_div = floor(feedback_divider); */ |
|
- | 643 | a.full = rfixed_floor(feedback_divider); |
|
- | 644 | *fb_div = rfixed_trunc(a); |
|
- | 645 | /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */ |
|
- | 646 | a.full = rfixed_const(10); |
|
- | 647 | b.full = rfixed_mul(feedback_divider, a); |
|
- | 648 | ||
- | 649 | feedback_divider.full = rfixed_floor(feedback_divider); |
|
- | 650 | feedback_divider.full = rfixed_mul(feedback_divider, a); |
|
- | 651 | feedback_divider.full = b.full - feedback_divider.full; |
|
- | 652 | *fb_div_frac = rfixed_trunc(feedback_divider); |
|
- | 653 | } else { |
|
- | 654 | /* *fb_div = floor(feedback_divider + 0.5); */ |
|
- | 655 | feedback_divider.full += rfixed_const_half(0); |
|
- | 656 | feedback_divider.full = rfixed_floor(feedback_divider); |
|
- | 657 | ||
- | 658 | *fb_div = rfixed_trunc(feedback_divider); |
|
- | 659 | *fb_div_frac = 0; |
|
- | 660 | } |
|
- | 661 | ||
- | 662 | if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div)) |
|
- | 663 | return false; |
|
- | 664 | else |
|
- | 665 | return true; |
|
- | 666 | } |
|
- | 667 | ||
- | 668 | static bool |
|
- | 669 | calc_fb_ref_div(struct radeon_pll *pll, |
|
- | 670 | uint32_t freq, |
|
- | 671 | uint32_t post_div, |
|
- | 672 | uint32_t *fb_div, |
|
- | 673 | uint32_t *fb_div_frac, |
|
- | 674 | uint32_t *ref_div) |
|
- | 675 | { |
|
- | 676 | fixed20_12 ffreq, max_error, error, pll_out, a; |
|
- | 677 | u32 vco; |
|
- | 678 | ||
- | 679 | ffreq.full = rfixed_const(freq); |
|
- | 680 | /* max_error = ffreq * 0.0025; */ |
|
- | 681 | a.full = rfixed_const(400); |
|
- | 682 | max_error.full = rfixed_div(ffreq, a); |
|
- | 683 | ||
- | 684 | for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) { |
|
- | 685 | if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) { |
|
- | 686 | vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac)); |
|
- | 687 | vco = vco / ((*ref_div) * 10); |
|
- | 688 | ||
- | 689 | if ((vco < pll->pll_out_min) || (vco > pll->pll_out_max)) |
|
- | 690 | continue; |
|
- | 691 | ||
- | 692 | /* pll_out = vco / post_div; */ |
|
- | 693 | a.full = rfixed_const(post_div); |
|
- | 694 | pll_out.full = rfixed_const(vco); |
|
- | 695 | pll_out.full = rfixed_div(pll_out, a); |
|
- | 696 | ||
- | 697 | if (pll_out.full >= ffreq.full) { |
|
- | 698 | error.full = pll_out.full - ffreq.full; |
|
- | 699 | if (error.full <= max_error.full) |
|
- | 700 | return true; |
|
- | 701 | } |
|
- | 702 | } |
|
- | 703 | } |
|
- | 704 | return false; |
|
- | 705 | } |
|
582 | 706 | ||
583 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
707 | static void radeon_compute_pll_new(struct radeon_pll *pll, |
584 | uint64_t freq, |
708 | uint64_t freq, |
585 | uint32_t *dot_clock_p, |
709 | uint32_t *dot_clock_p, |
586 | uint32_t *fb_div_p, |
710 | uint32_t *fb_div_p, |
587 | uint32_t *frac_fb_div_p, |
711 | uint32_t *frac_fb_div_p, |
588 | uint32_t *ref_div_p, |
712 | uint32_t *ref_div_p, |
589 | uint32_t *post_div_p) |
713 | uint32_t *post_div_p) |
590 | { |
714 | { |
591 | fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq; |
- | |
592 | fixed20_12 pll_out_max, pll_out_min; |
- | |
593 | fixed20_12 pll_in_max, pll_in_min; |
- | |
594 | fixed20_12 reference_freq; |
715 | u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0; |
595 | fixed20_12 error, ffreq, a, b; |
- | |
596 | - | ||
597 | pll_out_max.full = rfixed_const(pll->pll_out_max); |
- | |
598 | pll_out_min.full = rfixed_const(pll->pll_out_min); |
- | |
599 | pll_in_max.full = rfixed_const(pll->pll_in_max); |
- | |
600 | pll_in_min.full = rfixed_const(pll->pll_in_min); |
- | |
601 | reference_freq.full = rfixed_const(pll->reference_freq); |
- | |
602 | do_div(freq, 10); |
- | |
603 | ffreq.full = rfixed_const(freq); |
- | |
604 | error.full = rfixed_const(100 * 100); |
- | |
605 | - | ||
606 | /* max p */ |
- | |
607 | p.full = rfixed_div(pll_out_max, ffreq); |
- | |
608 | p.full = rfixed_floor(p); |
- | |
609 | - | ||
610 | /* min m */ |
- | |
611 | m.full = rfixed_div(reference_freq, pll_in_max); |
- | |
612 | m.full = rfixed_ceil(m); |
- | |
613 | - | ||
614 | while (1) { |
- | |
615 | n.full = rfixed_div(ffreq, reference_freq); |
- | |
616 | n.full = rfixed_mul(n, m); |
- | |
617 | n.full = rfixed_mul(n, p); |
- | |
618 | - | ||
619 | f_vco.full = rfixed_div(n, m); |
- | |
Line 620... | Line -... | ||
620 | f_vco.full = rfixed_mul(f_vco, reference_freq); |
- | |
621 | - | ||
622 | f_pclk.full = rfixed_div(f_vco, p); |
- | |
623 | - | ||
624 | if (f_pclk.full > ffreq.full) |
- | |
625 | error.full = f_pclk.full - ffreq.full; |
- | |
626 | else |
- | |
627 | error.full = ffreq.full - f_pclk.full; |
- | |
628 | error.full = rfixed_div(error, f_pclk); |
- | |
629 | a.full = rfixed_const(100 * 100); |
- | |
630 | error.full = rfixed_mul(error, a); |
716 | u32 best_freq = 0, vco_frequency; |
631 | 717 | ||
632 | a.full = rfixed_mul(m, p); |
- | |
Line -... | Line 718... | ||
- | 718 | /* freq = freq / 10; */ |
|
- | 719 | do_div(freq, 10); |
|
- | 720 | ||
- | 721 | if (pll->flags & RADEON_PLL_USE_POST_DIV) { |
|
- | 722 | post_div = pll->post_div; |
|
- | 723 | if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div)) |
|
- | 724 | goto done; |
|
- | 725 | ||
- | 726 | vco_frequency = freq * post_div; |
|
- | 727 | if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) |
|
- | 728 | goto done; |
|
- | 729 | ||
- | 730 | if (pll->flags & RADEON_PLL_USE_REF_DIV) { |
|
- | 731 | ref_div = pll->reference_div; |
|
- | 732 | if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) |
|
- | 733 | goto done; |
|
- | 734 | if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac)) |
|
- | 735 | goto done; |
|
- | 736 | } |
|
633 | a.full = rfixed_div(n, a); |
737 | } else { |
- | 738 | for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) { |
|
- | 739 | if (pll->flags & RADEON_PLL_LEGACY) { |
|
- | 740 | if ((post_div == 5) || |
|
- | 741 | (post_div == 7) || |
|
- | 742 | (post_div == 9) || |
|
634 | best_freq.full = rfixed_mul(reference_freq, a); |
743 | (post_div == 10) || |
Line 635... | Line -... | ||
635 | - | ||
636 | if (rfixed_trunc(error) < 25) |
- | |
637 | break; |
744 | (post_div == 11)) |
638 | - | ||
639 | a.full = rfixed_const(1); |
745 | continue; |
Line 640... | Line -... | ||
640 | m.full = m.full + a.full; |
- | |
641 | a.full = rfixed_div(reference_freq, m); |
- | |
642 | if (a.full >= pll_in_min.full) |
- | |
643 | continue; |
746 | } |
644 | - | ||
645 | m.full = rfixed_div(reference_freq, pll_in_max); |
747 | |
646 | m.full = rfixed_ceil(m); |
748 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
- | 749 | continue; |
|
- | 750 | ||
- | 751 | vco_frequency = freq * post_div; |
|
- | 752 | if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) |
|
- | 753 | continue; |
|
- | 754 | if (pll->flags & RADEON_PLL_USE_REF_DIV) { |
|
647 | a.full= rfixed_const(1); |
755 | ref_div = pll->reference_div; |
648 | p.full = p.full - a.full; |
756 | if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) |
649 | a.full = rfixed_mul(p, ffreq); |
757 | goto done; |
650 | if (a.full >= pll_out_min.full) |
758 | if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac)) |
651 | continue; |
759 | break; |
- | 760 | } else { |
|
Line -... | Line 761... | ||
- | 761 | if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div)) |
|
- | 762 | break; |
|
- | 763 | } |
|
- | 764 | } |
|
- | 765 | } |
|
652 | else { |
766 | |
- | 767 | best_freq = pll->reference_freq * 10 * fb_div; |
|
- | 768 | best_freq += pll->reference_freq * fb_div_frac; |
|
653 | DRM_ERROR("Unable to find pll dividers\n"); |
769 | best_freq = best_freq / (ref_div * post_div); |
- | 770 | ||
- | 771 | done: |
|
- | 772 | if (best_freq == 0) |
|
- | 773 | DRM_ERROR("Couldn't find valid PLL dividers\n"); |
|
Line 654... | Line -... | ||
654 | break; |
- | |
655 | } |
774 | |
656 | } |
- | |
657 | 775 | *dot_clock_p = best_freq / 10; |
|
658 | a.full = rfixed_const(10); |
- | |
659 | b.full = rfixed_mul(n, a); |
- | |
660 | - | ||
661 | frac_n.full = rfixed_floor(n); |
- | |
662 | frac_n.full = rfixed_mul(frac_n, a); |
- | |
Line -... | Line 776... | ||
- | 776 | *fb_div_p = fb_div; |
|
- | 777 | *frac_fb_div_p = fb_div_frac; |
|
- | 778 | *ref_div_p = ref_div; |
|
- | 779 | *post_div_p = post_div; |
|
- | 780 | ||
- | 781 | DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); |
|
- | 782 | } |
|
- | 783 | ||
- | 784 | void radeon_compute_pll(struct radeon_pll *pll, |
|
- | 785 | uint64_t freq, |
|
- | 786 | uint32_t *dot_clock_p, |
|
663 | frac_n.full = b.full - frac_n.full; |
787 | uint32_t *fb_div_p, |
- | 788 | uint32_t *frac_fb_div_p, |
|
- | 789 | uint32_t *ref_div_p, |
|
- | 790 | uint32_t *post_div_p) |
|
- | 791 | { |
|
- | 792 | switch (pll->algo) { |
|
- | 793 | case PLL_ALGO_NEW: |
|
- | 794 | radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p, |
|
664 | 795 | frac_fb_div_p, ref_div_p, post_div_p); |
|
Line 665... | Line 796... | ||
665 | *dot_clock_p = rfixed_trunc(best_freq); |
796 | break; |
666 | *fb_div_p = rfixed_trunc(n); |
797 | case PLL_ALGO_LEGACY: |
667 | *frac_fb_div_p = rfixed_trunc(frac_n); |
798 | default: |
Line 817... | Line 948... | ||
817 | return 0; |
948 | return 0; |
818 | } |
949 | } |
Line 819... | Line 950... | ||
819 | 950 | ||
820 | int radeon_modeset_init(struct radeon_device *rdev) |
951 | int radeon_modeset_init(struct radeon_device *rdev) |
821 | { |
952 | { |
822 | int num_crtc = 2, i; |
953 | int i; |
Line 823... | Line 954... | ||
823 | int ret; |
954 | int ret; |
824 | 955 | ||
Line 840... | Line 971... | ||
840 | ret = radeon_modeset_create_props(rdev); |
971 | ret = radeon_modeset_create_props(rdev); |
841 | if (ret) { |
972 | if (ret) { |
842 | return ret; |
973 | return ret; |
843 | } |
974 | } |
Line -... | Line 975... | ||
- | 975 | ||
- | 976 | /* check combios for a valid hardcoded EDID - Sun servers */ |
|
- | 977 | if (!rdev->is_atom_bios) { |
|
- | 978 | /* check for hardcoded EDID in BIOS */ |
|
- | 979 | radeon_combios_check_hardcoded_edid(rdev); |
|
- | 980 | } |
|
844 | 981 | ||
845 | if (rdev->flags & RADEON_SINGLE_CRTC) |
982 | if (rdev->flags & RADEON_SINGLE_CRTC) |
- | 983 | rdev->num_crtc = 1; |
|
- | 984 | else { |
|
- | 985 | if (ASIC_IS_DCE4(rdev)) |
|
- | 986 | rdev->num_crtc = 6; |
|
- | 987 | else |
|
- | 988 | rdev->num_crtc = 2; |
|
Line 846... | Line 989... | ||
846 | num_crtc = 1; |
989 | } |
847 | 990 | ||
848 | /* allocate crtcs */ |
991 | /* allocate crtcs */ |
849 | for (i = 0; i < num_crtc; i++) { |
992 | for (i = 0; i < rdev->num_crtc; i++) { |
Line 850... | Line 993... | ||
850 | radeon_crtc_init(rdev->ddev, i); |
993 | radeon_crtc_init(rdev->ddev, i); |
851 | } |
994 | } |
Line 861... | Line 1004... | ||
861 | return 0; |
1004 | return 0; |
862 | } |
1005 | } |
Line 863... | Line 1006... | ||
863 | 1006 | ||
864 | void radeon_modeset_fini(struct radeon_device *rdev) |
1007 | void radeon_modeset_fini(struct radeon_device *rdev) |
- | 1008 | { |
|
- | 1009 | kfree(rdev->mode_info.bios_hardcoded_edid); |
|
865 | { |
1010 | |
866 | if (rdev->mode_info.mode_config_initialized) { |
1011 | if (rdev->mode_info.mode_config_initialized) { |
867 | radeon_hpd_fini(rdev); |
1012 | radeon_hpd_fini(rdev); |
868 | drm_mode_config_cleanup(rdev->ddev); |
1013 | drm_mode_config_cleanup(rdev->ddev); |
869 | rdev->mode_info.mode_config_initialized = false; |
1014 | rdev->mode_info.mode_config_initialized = false; |