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Rev 3031 | Rev 3243 | ||
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Line 46... | Line 46... | ||
46 | struct drm_device *dev = plane->dev; |
46 | struct drm_device *dev = plane->dev; |
47 | struct drm_i915_private *dev_priv = dev->dev_private; |
47 | struct drm_i915_private *dev_priv = dev->dev_private; |
48 | struct intel_plane *intel_plane = to_intel_plane(plane); |
48 | struct intel_plane *intel_plane = to_intel_plane(plane); |
49 | int pipe = intel_plane->pipe; |
49 | int pipe = intel_plane->pipe; |
50 | u32 sprctl, sprscale = 0; |
50 | u32 sprctl, sprscale = 0; |
51 | int pixel_size; |
51 | unsigned long sprsurf_offset, linear_offset; |
- | 52 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
|
Line 52... | Line 53... | ||
52 | 53 | ||
Line 53... | Line 54... | ||
53 | sprctl = I915_READ(SPRCTL(pipe)); |
54 | sprctl = I915_READ(SPRCTL(pipe)); |
54 | 55 | ||
Line 59... | Line 60... | ||
59 | sprctl &= ~SPRITE_TILED; |
60 | sprctl &= ~SPRITE_TILED; |
Line 60... | Line 61... | ||
60 | 61 | ||
61 | switch (fb->pixel_format) { |
62 | switch (fb->pixel_format) { |
62 | case DRM_FORMAT_XBGR8888: |
63 | case DRM_FORMAT_XBGR8888: |
63 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
- | |
64 | pixel_size = 4; |
64 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
65 | break; |
65 | break; |
66 | case DRM_FORMAT_XRGB8888: |
66 | case DRM_FORMAT_XRGB8888: |
67 | sprctl |= SPRITE_FORMAT_RGBX888; |
- | |
68 | pixel_size = 4; |
67 | sprctl |= SPRITE_FORMAT_RGBX888; |
69 | break; |
68 | break; |
70 | case DRM_FORMAT_YUYV: |
69 | case DRM_FORMAT_YUYV: |
71 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; |
- | |
72 | pixel_size = 2; |
70 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; |
73 | break; |
71 | break; |
74 | case DRM_FORMAT_YVYU: |
72 | case DRM_FORMAT_YVYU: |
75 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; |
- | |
76 | pixel_size = 2; |
73 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; |
77 | break; |
74 | break; |
78 | case DRM_FORMAT_UYVY: |
75 | case DRM_FORMAT_UYVY: |
79 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; |
- | |
80 | pixel_size = 2; |
76 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; |
81 | break; |
77 | break; |
82 | case DRM_FORMAT_VYUY: |
78 | case DRM_FORMAT_VYUY: |
83 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; |
- | |
84 | pixel_size = 2; |
79 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; |
85 | break; |
80 | break; |
86 | default: |
- | |
87 | DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n"); |
- | |
88 | sprctl |= SPRITE_FORMAT_RGBX888; |
- | |
89 | pixel_size = 4; |
81 | default: |
90 | break; |
82 | BUG(); |
Line 91... | Line 83... | ||
91 | } |
83 | } |
92 | 84 | ||
Line 125... | Line 117... | ||
125 | } |
117 | } |
126 | } |
118 | } |
Line 127... | Line 119... | ||
127 | 119 | ||
128 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
120 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
- | 121 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
|
- | 122 | ||
- | 123 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
|
- | 124 | sprsurf_offset = |
|
- | 125 | intel_gen4_compute_offset_xtiled(&x, &y, |
|
- | 126 | pixel_size, fb->pitches[0]); |
|
- | 127 | linear_offset -= sprsurf_offset; |
|
- | 128 | ||
- | 129 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
|
- | 130 | * register */ |
|
- | 131 | if (IS_HASWELL(dev)) |
|
129 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
132 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
130 | if (obj->tiling_mode != I915_TILING_NONE) { |
133 | else if (obj->tiling_mode != I915_TILING_NONE) |
131 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
134 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
132 | } else { |
135 | else |
Line 133... | Line -... | ||
133 | unsigned long offset; |
- | |
134 | - | ||
135 | offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
- | |
136 | I915_WRITE(SPRLINOFF(pipe), offset); |
136 | I915_WRITE(SPRLINOFF(pipe), linear_offset); |
- | 137 | ||
137 | } |
138 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
138 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
139 | if (intel_plane->can_scale) |
139 | I915_WRITE(SPRSCALE(pipe), sprscale); |
140 | I915_WRITE(SPRSCALE(pipe), sprscale); |
140 | I915_WRITE(SPRCTL(pipe), sprctl); |
141 | I915_WRITE(SPRCTL(pipe), sprctl); |
141 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset); |
142 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); |
Line 142... | Line 143... | ||
142 | POSTING_READ(SPRSURF(pipe)); |
143 | POSTING_READ(SPRSURF(pipe)); |
143 | } |
144 | } |
Line 150... | Line 151... | ||
150 | struct intel_plane *intel_plane = to_intel_plane(plane); |
151 | struct intel_plane *intel_plane = to_intel_plane(plane); |
151 | int pipe = intel_plane->pipe; |
152 | int pipe = intel_plane->pipe; |
Line 152... | Line 153... | ||
152 | 153 | ||
153 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
154 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
- | 155 | /* Can't leave the scaler enabled... */ |
|
154 | /* Can't leave the scaler enabled... */ |
156 | if (intel_plane->can_scale) |
155 | I915_WRITE(SPRSCALE(pipe), 0); |
157 | I915_WRITE(SPRSCALE(pipe), 0); |
156 | /* Activate double buffered register update */ |
158 | /* Activate double buffered register update */ |
157 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
159 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
Line 223... | Line 225... | ||
223 | uint32_t src_w, uint32_t src_h) |
225 | uint32_t src_w, uint32_t src_h) |
224 | { |
226 | { |
225 | struct drm_device *dev = plane->dev; |
227 | struct drm_device *dev = plane->dev; |
226 | struct drm_i915_private *dev_priv = dev->dev_private; |
228 | struct drm_i915_private *dev_priv = dev->dev_private; |
227 | struct intel_plane *intel_plane = to_intel_plane(plane); |
229 | struct intel_plane *intel_plane = to_intel_plane(plane); |
228 | int pipe = intel_plane->pipe, pixel_size; |
230 | int pipe = intel_plane->pipe; |
- | 231 | unsigned long dvssurf_offset, linear_offset; |
|
229 | u32 dvscntr, dvsscale; |
232 | u32 dvscntr, dvsscale; |
- | 233 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
|
Line 230... | Line 234... | ||
230 | 234 | ||
Line 231... | Line 235... | ||
231 | dvscntr = I915_READ(DVSCNTR(pipe)); |
235 | dvscntr = I915_READ(DVSCNTR(pipe)); |
232 | 236 | ||
Line 237... | Line 241... | ||
237 | dvscntr &= ~DVS_TILED; |
241 | dvscntr &= ~DVS_TILED; |
Line 238... | Line 242... | ||
238 | 242 | ||
239 | switch (fb->pixel_format) { |
243 | switch (fb->pixel_format) { |
240 | case DRM_FORMAT_XBGR8888: |
244 | case DRM_FORMAT_XBGR8888: |
241 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
- | |
242 | pixel_size = 4; |
245 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
243 | break; |
246 | break; |
244 | case DRM_FORMAT_XRGB8888: |
247 | case DRM_FORMAT_XRGB8888: |
245 | dvscntr |= DVS_FORMAT_RGBX888; |
- | |
246 | pixel_size = 4; |
248 | dvscntr |= DVS_FORMAT_RGBX888; |
247 | break; |
249 | break; |
248 | case DRM_FORMAT_YUYV: |
250 | case DRM_FORMAT_YUYV: |
249 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; |
- | |
250 | pixel_size = 2; |
251 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; |
251 | break; |
252 | break; |
252 | case DRM_FORMAT_YVYU: |
253 | case DRM_FORMAT_YVYU: |
253 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; |
- | |
254 | pixel_size = 2; |
254 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; |
255 | break; |
255 | break; |
256 | case DRM_FORMAT_UYVY: |
256 | case DRM_FORMAT_UYVY: |
257 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; |
- | |
258 | pixel_size = 2; |
257 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; |
259 | break; |
258 | break; |
260 | case DRM_FORMAT_VYUY: |
259 | case DRM_FORMAT_VYUY: |
261 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; |
- | |
262 | pixel_size = 2; |
260 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; |
263 | break; |
261 | break; |
264 | default: |
- | |
265 | DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n"); |
- | |
266 | dvscntr |= DVS_FORMAT_RGBX888; |
- | |
267 | pixel_size = 4; |
262 | default: |
268 | break; |
263 | BUG(); |
Line 269... | Line 264... | ||
269 | } |
264 | } |
270 | 265 | ||
Line 287... | Line 282... | ||
287 | if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) |
282 | if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) |
288 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
283 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
Line 289... | Line 284... | ||
289 | 284 | ||
290 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
285 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
- | 286 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
|
- | 287 | ||
- | 288 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
|
- | 289 | dvssurf_offset = |
|
- | 290 | intel_gen4_compute_offset_xtiled(&x, &y, |
|
- | 291 | pixel_size, fb->pitches[0]); |
|
- | 292 | linear_offset -= dvssurf_offset; |
|
291 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
293 | |
292 | if (obj->tiling_mode != I915_TILING_NONE) { |
294 | if (obj->tiling_mode != I915_TILING_NONE) |
293 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
295 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
294 | } else { |
296 | else |
Line 295... | Line -... | ||
295 | unsigned long offset; |
- | |
296 | - | ||
297 | offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
- | |
298 | I915_WRITE(DVSLINOFF(pipe), offset); |
297 | I915_WRITE(DVSLINOFF(pipe), linear_offset); |
299 | } |
298 | |
300 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
299 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
301 | I915_WRITE(DVSSCALE(pipe), dvsscale); |
300 | I915_WRITE(DVSSCALE(pipe), dvsscale); |
302 | I915_WRITE(DVSCNTR(pipe), dvscntr); |
301 | I915_WRITE(DVSCNTR(pipe), dvscntr); |
303 | I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset); |
302 | I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset); |
Line 304... | Line 303... | ||
304 | POSTING_READ(DVSSURF(pipe)); |
303 | POSTING_READ(DVSSURF(pipe)); |
305 | } |
304 | } |
Line 420... | Line 419... | ||
420 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
419 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
421 | struct intel_plane *intel_plane = to_intel_plane(plane); |
420 | struct intel_plane *intel_plane = to_intel_plane(plane); |
422 | struct intel_framebuffer *intel_fb; |
421 | struct intel_framebuffer *intel_fb; |
423 | struct drm_i915_gem_object *obj, *old_obj; |
422 | struct drm_i915_gem_object *obj, *old_obj; |
424 | int pipe = intel_plane->pipe; |
423 | int pipe = intel_plane->pipe; |
- | 424 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
|
- | 425 | pipe); |
|
425 | int ret = 0; |
426 | int ret = 0; |
426 | int x = src_x >> 16, y = src_y >> 16; |
427 | int x = src_x >> 16, y = src_y >> 16; |
427 | int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay; |
428 | int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay; |
428 | bool disable_primary = false; |
429 | bool disable_primary = false; |
Line 434... | Line 435... | ||
434 | 435 | ||
435 | src_w = src_w >> 16; |
436 | src_w = src_w >> 16; |
Line 436... | Line 437... | ||
436 | src_h = src_h >> 16; |
437 | src_h = src_h >> 16; |
437 | 438 | ||
438 | /* Pipe must be running... */ |
439 | /* Pipe must be running... */ |
Line 439... | Line 440... | ||
439 | if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE)) |
440 | if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) |
440 | return -EINVAL; |
441 | return -EINVAL; |
Line 441... | Line 442... | ||
441 | 442 | ||
442 | if (crtc_x >= primary_w || crtc_y >= primary_h) |
443 | if (crtc_x >= primary_w || crtc_y >= primary_h) |
443 | return -EINVAL; |
444 | return -EINVAL; |
Line -... | Line 445... | ||
- | 445 | ||
- | 446 | /* Don't modify another pipe's plane */ |
|
- | 447 | if (intel_plane->pipe != intel_crtc->pipe) |
|
- | 448 | return -EINVAL; |
|
- | 449 | ||
- | 450 | /* Sprite planes can be linear or x-tiled surfaces */ |
|
- | 451 | switch (obj->tiling_mode) { |
|
- | 452 | case I915_TILING_NONE: |
|
- | 453 | case I915_TILING_X: |
|
444 | 454 | break; |
|
445 | /* Don't modify another pipe's plane */ |
455 | default: |
446 | if (intel_plane->pipe != intel_crtc->pipe) |
456 | return -EINVAL; |
447 | return -EINVAL; |
457 | } |
448 | 458 | ||
Line 471... | Line 481... | ||
471 | 481 | ||
472 | if (!crtc_w || !crtc_h) /* Again, nothing to display */ |
482 | if (!crtc_w || !crtc_h) /* Again, nothing to display */ |
Line 473... | Line 483... | ||
473 | goto out; |
483 | goto out; |
- | 484 | ||
- | 485 | /* |
|
- | 486 | * We may not have a scaler, eg. HSW does not have it any more |
|
- | 487 | */ |
|
- | 488 | if (!intel_plane->can_scale && (crtc_w != src_w || crtc_h != src_h)) |
|
- | 489 | return -EINVAL; |
|
474 | 490 | ||
475 | /* |
491 | /* |
476 | * We can take a larger source and scale it down, but |
492 | * We can take a larger source and scale it down, but |
477 | * only so much... 16x is the max on SNB. |
493 | * only so much... 16x is the max on SNB. |
478 | */ |
494 | */ |
Line 568... | Line 584... | ||
568 | struct drm_mode_object *obj; |
584 | struct drm_mode_object *obj; |
569 | struct drm_plane *plane; |
585 | struct drm_plane *plane; |
570 | struct intel_plane *intel_plane; |
586 | struct intel_plane *intel_plane; |
571 | int ret = 0; |
587 | int ret = 0; |
Line 572... | Line -... | ||
572 | - | ||
573 | // if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
- | |
Line 574... | Line 588... | ||
574 | // return -ENODEV; |
588 | |
575 | 589 | ||
576 | /* Make sure we don't try to enable both src & dest simultaneously */ |
590 | /* Make sure we don't try to enable both src & dest simultaneously */ |
Line 601... | Line 615... | ||
601 | struct drm_mode_object *obj; |
615 | struct drm_mode_object *obj; |
602 | struct drm_plane *plane; |
616 | struct drm_plane *plane; |
603 | struct intel_plane *intel_plane; |
617 | struct intel_plane *intel_plane; |
604 | int ret = 0; |
618 | int ret = 0; |
Line 605... | Line -... | ||
605 | - | ||
606 | // if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
- | |
Line 607... | Line 619... | ||
607 | // return -ENODEV; |
619 | |
Line 608... | Line 620... | ||
608 | 620 | ||
609 | mutex_lock(&dev->mode_config.mutex); |
621 | mutex_lock(&dev->mode_config.mutex); |
Line 663... | Line 675... | ||
663 | return -ENOMEM; |
675 | return -ENOMEM; |
Line 664... | Line 676... | ||
664 | 676 | ||
665 | switch (INTEL_INFO(dev)->gen) { |
677 | switch (INTEL_INFO(dev)->gen) { |
666 | case 5: |
678 | case 5: |
- | 679 | case 6: |
|
667 | case 6: |
680 | intel_plane->can_scale = true; |
668 | intel_plane->max_downscale = 16; |
681 | intel_plane->max_downscale = 16; |
669 | intel_plane->update_plane = ilk_update_plane; |
682 | intel_plane->update_plane = ilk_update_plane; |
670 | intel_plane->disable_plane = ilk_disable_plane; |
683 | intel_plane->disable_plane = ilk_disable_plane; |
671 | intel_plane->update_colorkey = ilk_update_colorkey; |
684 | intel_plane->update_colorkey = ilk_update_colorkey; |
Line 679... | Line 692... | ||
679 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); |
692 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); |
680 | } |
693 | } |
681 | break; |
694 | break; |
Line 682... | Line 695... | ||
682 | 695 | ||
- | 696 | case 7: |
|
- | 697 | if (IS_HASWELL(dev) || IS_VALLEYVIEW(dev)) |
|
- | 698 | intel_plane->can_scale = false; |
|
- | 699 | else |
|
683 | case 7: |
700 | intel_plane->can_scale = true; |
684 | intel_plane->max_downscale = 2; |
701 | intel_plane->max_downscale = 2; |
685 | intel_plane->update_plane = ivb_update_plane; |
702 | intel_plane->update_plane = ivb_update_plane; |
686 | intel_plane->disable_plane = ivb_disable_plane; |
703 | intel_plane->disable_plane = ivb_disable_plane; |
687 | intel_plane->update_colorkey = ivb_update_colorkey; |
704 | intel_plane->update_colorkey = ivb_update_colorkey; |