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Line 34... | Line 34... | ||
34 | #include |
34 | #include |
35 | #include "intel_drv.h" |
35 | #include "intel_drv.h" |
36 | #include |
36 | #include |
37 | #include "i915_drv.h" |
37 | #include "i915_drv.h" |
Line 38... | Line -... | ||
38 | - | ||
39 | #define DP_RECEIVER_CAP_SIZE 0xf |
- | |
40 | #define DP_LINK_STATUS_SIZE 6 |
38 | |
Line 41... | Line 39... | ||
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
42 | 40 | ||
43 | /** |
41 | /** |
Line 47... | Line 45... | ||
47 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
45 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
48 | * will return true, and false otherwise. |
46 | * will return true, and false otherwise. |
49 | */ |
47 | */ |
50 | static bool is_edp(struct intel_dp *intel_dp) |
48 | static bool is_edp(struct intel_dp *intel_dp) |
51 | { |
49 | { |
- | 50 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 51 | ||
52 | return intel_dp->base.type == INTEL_OUTPUT_EDP; |
52 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
53 | } |
53 | } |
Line 54... | Line 54... | ||
54 | 54 | ||
55 | /** |
55 | /** |
56 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? |
56 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? |
Line 74... | Line 74... | ||
74 | static bool is_cpu_edp(struct intel_dp *intel_dp) |
74 | static bool is_cpu_edp(struct intel_dp *intel_dp) |
75 | { |
75 | { |
76 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); |
76 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); |
77 | } |
77 | } |
Line 78... | Line 78... | ||
78 | 78 | ||
79 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
79 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
- | 80 | { |
|
- | 81 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
80 | { |
82 | |
81 | return container_of(encoder, struct intel_dp, base.base); |
83 | return intel_dig_port->base.base.dev; |
Line 82... | Line 84... | ||
82 | } |
84 | } |
83 | 85 | ||
84 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
86 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
85 | { |
- | |
86 | return container_of(intel_attached_encoder(connector), |
87 | { |
Line 87... | Line 88... | ||
87 | struct intel_dp, base); |
88 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
88 | } |
89 | } |
89 | 90 | ||
Line 104... | Line 105... | ||
104 | intel_dp = enc_to_intel_dp(encoder); |
105 | intel_dp = enc_to_intel_dp(encoder); |
Line 105... | Line 106... | ||
105 | 106 | ||
106 | return is_pch_edp(intel_dp); |
107 | return is_pch_edp(intel_dp); |
Line 107... | Line -... | ||
107 | } |
- | |
108 | - | ||
109 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
108 | } |
Line 110... | Line 109... | ||
110 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
109 | |
111 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
110 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
112 | 111 | ||
113 | void |
112 | void |
114 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
113 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
Line 115... | Line 114... | ||
115 | int *lane_num, int *link_bw) |
114 | int *lane_num, int *link_bw) |
116 | { |
- | |
117 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
- | |
118 | 115 | { |
|
119 | *lane_num = intel_dp->lane_count; |
- | |
120 | if (intel_dp->link_bw == DP_LINK_BW_1_62) |
116 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Line 121... | Line 117... | ||
121 | *link_bw = 162000; |
117 | |
122 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
118 | *lane_num = intel_dp->lane_count; |
123 | *link_bw = 270000; |
119 | *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
124 | } |
120 | } |
125 | 121 | ||
- | 122 | int |
|
Line 126... | Line 123... | ||
126 | int |
123 | intel_edp_target_clock(struct intel_encoder *intel_encoder, |
127 | intel_edp_target_clock(struct intel_encoder *intel_encoder, |
124 | struct drm_display_mode *mode) |
128 | struct drm_display_mode *mode) |
125 | { |
129 | { |
126 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
130 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
127 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Line 131... | Line 128... | ||
131 | 128 | ||
132 | if (intel_dp->panel_fixed_mode) |
- | |
133 | return intel_dp->panel_fixed_mode->clock; |
- | |
134 | else |
- | |
135 | return mode->clock; |
- | |
136 | } |
- | |
137 | - | ||
138 | static int |
- | |
139 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
- | |
140 | { |
- | |
141 | int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; |
- | |
142 | switch (max_lane_count) { |
- | |
143 | case 1: case 2: case 4: |
- | |
144 | break; |
- | |
145 | default: |
129 | if (intel_connector->panel.fixed_mode) |
146 | max_lane_count = 4; |
130 | return intel_connector->panel.fixed_mode->clock; |
147 | } |
131 | else |
Line 148... | Line 132... | ||
148 | return max_lane_count; |
132 | return mode->clock; |
Line 206... | Line 190... | ||
206 | intel_dp_adjust_dithering(struct intel_dp *intel_dp, |
190 | intel_dp_adjust_dithering(struct intel_dp *intel_dp, |
207 | struct drm_display_mode *mode, |
191 | struct drm_display_mode *mode, |
208 | bool adjust_mode) |
192 | bool adjust_mode) |
209 | { |
193 | { |
210 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
194 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
211 | int max_lanes = intel_dp_max_lane_count(intel_dp); |
195 | int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); |
212 | int max_rate, mode_rate; |
196 | int max_rate, mode_rate; |
Line 213... | Line 197... | ||
213 | 197 | ||
214 | mode_rate = intel_dp_link_required(mode->clock, 24); |
198 | mode_rate = intel_dp_link_required(mode->clock, 24); |
Line 232... | Line 216... | ||
232 | static int |
216 | static int |
233 | intel_dp_mode_valid(struct drm_connector *connector, |
217 | intel_dp_mode_valid(struct drm_connector *connector, |
234 | struct drm_display_mode *mode) |
218 | struct drm_display_mode *mode) |
235 | { |
219 | { |
236 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
220 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
- | 221 | struct intel_connector *intel_connector = to_intel_connector(connector); |
|
- | 222 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
|
Line 237... | Line 223... | ||
237 | 223 | ||
238 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
224 | if (is_edp(intel_dp) && fixed_mode) { |
239 | if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) |
225 | if (mode->hdisplay > fixed_mode->hdisplay) |
Line 240... | Line 226... | ||
240 | return MODE_PANEL; |
226 | return MODE_PANEL; |
241 | 227 | ||
242 | if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) |
228 | if (mode->vdisplay > fixed_mode->vdisplay) |
Line 243... | Line 229... | ||
243 | return MODE_PANEL; |
229 | return MODE_PANEL; |
244 | } |
230 | } |
Line 283... | Line 269... | ||
283 | intel_hrawclk(struct drm_device *dev) |
269 | intel_hrawclk(struct drm_device *dev) |
284 | { |
270 | { |
285 | struct drm_i915_private *dev_priv = dev->dev_private; |
271 | struct drm_i915_private *dev_priv = dev->dev_private; |
286 | uint32_t clkcfg; |
272 | uint32_t clkcfg; |
Line -... | Line 273... | ||
- | 273 | ||
- | 274 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
|
- | 275 | if (IS_VALLEYVIEW(dev)) |
|
- | 276 | return 200; |
|
287 | 277 | ||
288 | clkcfg = I915_READ(CLKCFG); |
278 | clkcfg = I915_READ(CLKCFG); |
289 | switch (clkcfg & CLKCFG_FSB_MASK) { |
279 | switch (clkcfg & CLKCFG_FSB_MASK) { |
290 | case CLKCFG_FSB_400: |
280 | case CLKCFG_FSB_400: |
291 | return 100; |
281 | return 100; |
Line 308... | Line 298... | ||
308 | } |
298 | } |
309 | } |
299 | } |
Line 310... | Line 300... | ||
310 | 300 | ||
311 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
301 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
312 | { |
302 | { |
313 | struct drm_device *dev = intel_dp->base.base.dev; |
303 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Line 314... | Line 304... | ||
314 | struct drm_i915_private *dev_priv = dev->dev_private; |
304 | struct drm_i915_private *dev_priv = dev->dev_private; |
315 | 305 | ||
Line 316... | Line 306... | ||
316 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; |
306 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; |
317 | } |
307 | } |
318 | 308 | ||
319 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) |
309 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) |
Line 320... | Line 310... | ||
320 | { |
310 | { |
321 | struct drm_device *dev = intel_dp->base.base.dev; |
311 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Line 322... | Line 312... | ||
322 | struct drm_i915_private *dev_priv = dev->dev_private; |
312 | struct drm_i915_private *dev_priv = dev->dev_private; |
323 | 313 | ||
324 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; |
314 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; |
325 | } |
315 | } |
326 | 316 | ||
Line 327... | Line 317... | ||
327 | static void |
317 | static void |
328 | intel_dp_check_edp(struct intel_dp *intel_dp) |
318 | intel_dp_check_edp(struct intel_dp *intel_dp) |
329 | { |
319 | { |
Line 344... | Line 334... | ||
344 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
334 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
345 | uint8_t *send, int send_bytes, |
335 | uint8_t *send, int send_bytes, |
346 | uint8_t *recv, int recv_size) |
336 | uint8_t *recv, int recv_size) |
347 | { |
337 | { |
348 | uint32_t output_reg = intel_dp->output_reg; |
338 | uint32_t output_reg = intel_dp->output_reg; |
- | 339 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
349 | struct drm_device *dev = intel_dp->base.base.dev; |
340 | struct drm_device *dev = intel_dig_port->base.base.dev; |
350 | struct drm_i915_private *dev_priv = dev->dev_private; |
341 | struct drm_i915_private *dev_priv = dev->dev_private; |
351 | uint32_t ch_ctl = output_reg + 0x10; |
342 | uint32_t ch_ctl = output_reg + 0x10; |
352 | uint32_t ch_data = ch_ctl + 4; |
343 | uint32_t ch_data = ch_ctl + 4; |
353 | int i; |
344 | int i; |
354 | int recv_bytes; |
345 | int recv_bytes; |
355 | uint32_t status; |
346 | uint32_t status; |
356 | uint32_t aux_clock_divider; |
347 | uint32_t aux_clock_divider; |
357 | int try, precharge; |
348 | int try, precharge; |
Line -... | Line 349... | ||
- | 349 | ||
- | 350 | if (IS_HASWELL(dev)) { |
|
- | 351 | switch (intel_dig_port->port) { |
|
- | 352 | case PORT_A: |
|
- | 353 | ch_ctl = DPA_AUX_CH_CTL; |
|
- | 354 | ch_data = DPA_AUX_CH_DATA1; |
|
- | 355 | break; |
|
- | 356 | case PORT_B: |
|
- | 357 | ch_ctl = PCH_DPB_AUX_CH_CTL; |
|
- | 358 | ch_data = PCH_DPB_AUX_CH_DATA1; |
|
- | 359 | break; |
|
- | 360 | case PORT_C: |
|
- | 361 | ch_ctl = PCH_DPC_AUX_CH_CTL; |
|
- | 362 | ch_data = PCH_DPC_AUX_CH_DATA1; |
|
- | 363 | break; |
|
- | 364 | case PORT_D: |
|
- | 365 | ch_ctl = PCH_DPD_AUX_CH_CTL; |
|
- | 366 | ch_data = PCH_DPD_AUX_CH_DATA1; |
|
- | 367 | break; |
|
- | 368 | default: |
|
- | 369 | BUG(); |
|
- | 370 | } |
|
- | 371 | } |
|
358 | 372 | ||
359 | intel_dp_check_edp(intel_dp); |
373 | intel_dp_check_edp(intel_dp); |
360 | /* The clock divider is based off the hrawclk, |
374 | /* The clock divider is based off the hrawclk, |
361 | * and would like to run at 2MHz. So, take the |
375 | * and would like to run at 2MHz. So, take the |
362 | * hrawclk value and divide by 2 and use that |
376 | * hrawclk value and divide by 2 and use that |
363 | * |
377 | * |
364 | * Note that PCH attached eDP panels should use a 125MHz input |
378 | * Note that PCH attached eDP panels should use a 125MHz input |
365 | * clock divider. |
379 | * clock divider. |
366 | */ |
380 | */ |
- | 381 | if (is_cpu_edp(intel_dp)) { |
|
- | 382 | if (IS_HASWELL(dev)) |
|
- | 383 | aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; |
|
- | 384 | else if (IS_VALLEYVIEW(dev)) |
|
367 | if (is_cpu_edp(intel_dp)) { |
385 | aux_clock_divider = 100; |
368 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
386 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
369 | aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ |
387 | aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ |
370 | else |
388 | else |
371 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ |
389 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ |
372 | } else if (HAS_PCH_SPLIT(dev)) |
390 | } else if (HAS_PCH_SPLIT(dev)) |
373 | aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */ |
391 | aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
374 | else |
392 | else |
Line 375... | Line 393... | ||
375 | aux_clock_divider = intel_hrawclk(dev) / 2; |
393 | aux_clock_divider = intel_hrawclk(dev) / 2; |
376 | 394 | ||
Line 640... | Line 658... | ||
640 | 658 | ||
641 | DRM_ERROR("too many retries, giving up\n"); |
659 | DRM_ERROR("too many retries, giving up\n"); |
642 | return -EREMOTEIO; |
660 | return -EREMOTEIO; |
Line 643... | Line -... | ||
643 | } |
- | |
644 | - | ||
645 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
- | |
646 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
661 | } |
647 | 662 | ||
648 | static int |
663 | static int |
649 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
664 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
650 | struct intel_connector *intel_connector, const char *name) |
665 | struct intel_connector *intel_connector, const char *name) |
Line 668... | Line 683... | ||
668 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
683 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
669 | ironlake_edp_panel_vdd_off(intel_dp, false); |
684 | ironlake_edp_panel_vdd_off(intel_dp, false); |
670 | return ret; |
685 | return ret; |
671 | } |
686 | } |
Line 672... | Line 687... | ||
672 | 687 | ||
673 | static bool |
688 | bool |
674 | intel_dp_mode_fixup(struct drm_encoder *encoder, |
689 | intel_dp_mode_fixup(struct drm_encoder *encoder, |
675 | const struct drm_display_mode *mode, |
690 | const struct drm_display_mode *mode, |
676 | struct drm_display_mode *adjusted_mode) |
691 | struct drm_display_mode *adjusted_mode) |
677 | { |
692 | { |
678 | struct drm_device *dev = encoder->dev; |
693 | struct drm_device *dev = encoder->dev; |
- | 694 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
|
679 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
695 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
680 | int lane_count, clock; |
696 | int lane_count, clock; |
681 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
697 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
682 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
698 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
683 | int bpp, mode_rate; |
699 | int bpp, mode_rate; |
Line 684... | Line 700... | ||
684 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
700 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
685 | 701 | ||
- | 702 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
|
686 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
703 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
- | 704 | adjusted_mode); |
|
687 | intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); |
705 | intel_pch_panel_fitting(dev, |
688 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, |
706 | intel_connector->panel.fitting_mode, |
Line 689... | Line 707... | ||
689 | mode, adjusted_mode); |
707 | mode, adjusted_mode); |
690 | } |
708 | } |
Line 760... | Line 778... | ||
760 | void |
778 | void |
761 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
779 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
762 | struct drm_display_mode *adjusted_mode) |
780 | struct drm_display_mode *adjusted_mode) |
763 | { |
781 | { |
764 | struct drm_device *dev = crtc->dev; |
782 | struct drm_device *dev = crtc->dev; |
765 | struct intel_encoder *encoder; |
783 | struct intel_encoder *intel_encoder; |
- | 784 | struct intel_dp *intel_dp; |
|
766 | struct drm_i915_private *dev_priv = dev->dev_private; |
785 | struct drm_i915_private *dev_priv = dev->dev_private; |
767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
786 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
768 | int lane_count = 4; |
787 | int lane_count = 4; |
769 | struct intel_dp_m_n m_n; |
788 | struct intel_dp_m_n m_n; |
770 | int pipe = intel_crtc->pipe; |
789 | int pipe = intel_crtc->pipe; |
- | 790 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
|
Line 771... | Line 791... | ||
771 | 791 | ||
772 | /* |
792 | /* |
773 | * Find the lane count in the intel_encoder private |
793 | * Find the lane count in the intel_encoder private |
774 | */ |
794 | */ |
775 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
795 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
Line 776... | Line 796... | ||
776 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
796 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
777 | 797 | ||
778 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || |
798 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
779 | intel_dp->base.type == INTEL_OUTPUT_EDP) |
799 | intel_encoder->type == INTEL_OUTPUT_EDP) |
780 | { |
800 | { |
781 | lane_count = intel_dp->lane_count; |
801 | lane_count = intel_dp->lane_count; |
782 | break; |
802 | break; |
Line 789... | Line 809... | ||
789 | * set up for 8-bits of R/G/B, or 3 bytes total. |
809 | * set up for 8-bits of R/G/B, or 3 bytes total. |
790 | */ |
810 | */ |
791 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
811 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
792 | mode->clock, adjusted_mode->clock, &m_n); |
812 | mode->clock, adjusted_mode->clock, &m_n); |
Line 793... | Line 813... | ||
793 | 813 | ||
794 | if (HAS_PCH_SPLIT(dev)) { |
814 | if (IS_HASWELL(dev)) { |
795 | I915_WRITE(TRANSDATA_M1(pipe), |
815 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), |
- | 816 | TU_SIZE(m_n.tu) | m_n.gmch_m); |
|
- | 817 | I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); |
|
- | 818 | I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m); |
|
796 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
819 | I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n); |
- | 820 | } else if (HAS_PCH_SPLIT(dev)) { |
|
797 | m_n.gmch_m); |
821 | I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
798 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); |
822 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); |
799 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); |
823 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); |
- | 824 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); |
|
- | 825 | } else if (IS_VALLEYVIEW(dev)) { |
|
- | 826 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
|
- | 827 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); |
|
- | 828 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); |
|
800 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); |
829 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); |
801 | } else { |
830 | } else { |
802 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
- | |
803 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
831 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
804 | m_n.gmch_m); |
832 | TU_SIZE(m_n.tu) | m_n.gmch_m); |
805 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); |
833 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); |
806 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); |
834 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); |
807 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); |
835 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); |
808 | } |
836 | } |
Line -... | Line 837... | ||
- | 837 | } |
|
- | 838 | ||
- | 839 | void intel_dp_init_link_config(struct intel_dp *intel_dp) |
|
- | 840 | { |
|
- | 841 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
|
- | 842 | intel_dp->link_configuration[0] = intel_dp->link_bw; |
|
- | 843 | intel_dp->link_configuration[1] = intel_dp->lane_count; |
|
- | 844 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
|
- | 845 | /* |
|
- | 846 | * Check for DPCD version > 1.1 and enhanced framing support |
|
- | 847 | */ |
|
- | 848 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
|
- | 849 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
|
- | 850 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
|
- | 851 | } |
|
809 | } |
852 | } |
810 | 853 | ||
811 | static void |
854 | static void |
812 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
855 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
813 | struct drm_display_mode *adjusted_mode) |
856 | struct drm_display_mode *adjusted_mode) |
814 | { |
857 | { |
815 | struct drm_device *dev = encoder->dev; |
858 | struct drm_device *dev = encoder->dev; |
816 | struct drm_i915_private *dev_priv = dev->dev_private; |
859 | struct drm_i915_private *dev_priv = dev->dev_private; |
817 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
860 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Line 818... | Line 861... | ||
818 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
861 | struct drm_crtc *crtc = encoder->crtc; |
819 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
820 | 863 | ||
Line 858... | Line 901... | ||
858 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
901 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
859 | pipe_name(intel_crtc->pipe)); |
902 | pipe_name(intel_crtc->pipe)); |
860 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
903 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
861 | intel_write_eld(encoder, adjusted_mode); |
904 | intel_write_eld(encoder, adjusted_mode); |
862 | } |
905 | } |
863 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
- | |
864 | intel_dp->link_configuration[0] = intel_dp->link_bw; |
- | |
865 | intel_dp->link_configuration[1] = intel_dp->lane_count; |
- | |
866 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
- | |
867 | /* |
906 | |
868 | * Check for DPCD version > 1.1 and enhanced framing support |
- | |
869 | */ |
- | |
870 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
907 | intel_dp_init_link_config(intel_dp); |
871 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
- | |
872 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
- | |
873 | } |
- | |
Line 874... | Line 908... | ||
874 | 908 | ||
Line 875... | Line 909... | ||
875 | /* Split out the IBX/CPU vs CPT settings */ |
909 | /* Split out the IBX/CPU vs CPT settings */ |
876 | 910 | ||
877 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { |
911 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
878 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
912 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
879 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
913 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
880 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
914 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
Line 929... | Line 963... | ||
929 | 963 | ||
930 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, |
964 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, |
931 | u32 mask, |
965 | u32 mask, |
932 | u32 value) |
966 | u32 value) |
933 | { |
967 | { |
934 | struct drm_device *dev = intel_dp->base.base.dev; |
968 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Line 935... | Line 969... | ||
935 | struct drm_i915_private *dev_priv = dev->dev_private; |
969 | struct drm_i915_private *dev_priv = dev->dev_private; |
936 | 970 | ||
937 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
971 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
Line 976... | Line 1010... | ||
976 | control &= ~PANEL_UNLOCK_MASK; |
1010 | control &= ~PANEL_UNLOCK_MASK; |
977 | control |= PANEL_UNLOCK_REGS; |
1011 | control |= PANEL_UNLOCK_REGS; |
978 | return control; |
1012 | return control; |
979 | } |
1013 | } |
Line 980... | Line 1014... | ||
980 | 1014 | ||
981 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1015 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
982 | { |
1016 | { |
983 | struct drm_device *dev = intel_dp->base.base.dev; |
1017 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
984 | struct drm_i915_private *dev_priv = dev->dev_private; |
1018 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 985... | Line 1019... | ||
985 | u32 pp; |
1019 | u32 pp; |
986 | 1020 | ||
Line 1017... | Line 1051... | ||
1017 | } |
1051 | } |
1018 | } |
1052 | } |
Line 1019... | Line 1053... | ||
1019 | 1053 | ||
1020 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1054 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1021 | { |
1055 | { |
1022 | struct drm_device *dev = intel_dp->base.base.dev; |
1056 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1023 | struct drm_i915_private *dev_priv = dev->dev_private; |
1057 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1024... | Line 1058... | ||
1024 | u32 pp; |
1058 | u32 pp; |
1025 | 1059 | ||
Line 1035... | Line 1069... | ||
1035 | 1069 | ||
1036 | msleep(intel_dp->panel_power_down_delay); |
1070 | msleep(intel_dp->panel_power_down_delay); |
1037 | } |
1071 | } |
Line -... | Line 1072... | ||
- | 1072 | } |
|
- | 1073 | ||
- | 1074 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
|
- | 1075 | { |
|
- | 1076 | // struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
|
- | 1077 | // struct intel_dp, panel_vdd_work); |
|
- | 1078 | // struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1079 | // |
|
- | 1080 | // mutex_lock(&dev->mode_config.mutex); |
|
- | 1081 | // ironlake_panel_vdd_off_sync(intel_dp); |
|
Line 1038... | Line 1082... | ||
1038 | } |
1082 | // mutex_unlock(&dev->mode_config.mutex); |
1039 | 1083 | } |
|
1040 | 1084 | ||
1041 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
1085 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
Line 1042... | Line 1086... | ||
1042 | { |
1086 | { |
Line 1059... | Line 1103... | ||
1059 | // schedule_delayed_work(&intel_dp->panel_vdd_work, |
1103 | // schedule_delayed_work(&intel_dp->panel_vdd_work, |
1060 | // msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
1104 | // msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
1061 | } |
1105 | } |
1062 | } |
1106 | } |
Line 1063... | Line 1107... | ||
1063 | 1107 | ||
1064 | static void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
1108 | void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
1065 | { |
1109 | { |
1066 | struct drm_device *dev = intel_dp->base.base.dev; |
1110 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1067 | struct drm_i915_private *dev_priv = dev->dev_private; |
1111 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1068... | Line 1112... | ||
1068 | u32 pp; |
1112 | u32 pp; |
1069 | 1113 | ||
Line 1101... | Line 1145... | ||
1101 | I915_WRITE(PCH_PP_CONTROL, pp); |
1145 | I915_WRITE(PCH_PP_CONTROL, pp); |
1102 | POSTING_READ(PCH_PP_CONTROL); |
1146 | POSTING_READ(PCH_PP_CONTROL); |
1103 | } |
1147 | } |
1104 | } |
1148 | } |
Line 1105... | Line 1149... | ||
1105 | 1149 | ||
1106 | static void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
1150 | void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
1107 | { |
1151 | { |
1108 | struct drm_device *dev = intel_dp->base.base.dev; |
1152 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1109 | struct drm_i915_private *dev_priv = dev->dev_private; |
1153 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1110... | Line 1154... | ||
1110 | u32 pp; |
1154 | u32 pp; |
1111 | 1155 | ||
Line 1126... | Line 1170... | ||
1126 | intel_dp->want_panel_vdd = false; |
1170 | intel_dp->want_panel_vdd = false; |
Line 1127... | Line 1171... | ||
1127 | 1171 | ||
1128 | ironlake_wait_panel_off(intel_dp); |
1172 | ironlake_wait_panel_off(intel_dp); |
Line 1129... | Line 1173... | ||
1129 | } |
1173 | } |
1130 | 1174 | ||
- | 1175 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
|
1131 | static void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
1176 | { |
1132 | { |
1177 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | 1178 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
1133 | struct drm_device *dev = intel_dp->base.base.dev; |
1179 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1134... | Line 1180... | ||
1134 | struct drm_i915_private *dev_priv = dev->dev_private; |
1180 | int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe; |
1135 | u32 pp; |
1181 | u32 pp; |
Line 1147... | Line 1193... | ||
1147 | msleep(intel_dp->backlight_on_delay); |
1193 | msleep(intel_dp->backlight_on_delay); |
1148 | pp = ironlake_get_pp_control(dev_priv); |
1194 | pp = ironlake_get_pp_control(dev_priv); |
1149 | pp |= EDP_BLC_ENABLE; |
1195 | pp |= EDP_BLC_ENABLE; |
1150 | I915_WRITE(PCH_PP_CONTROL, pp); |
1196 | I915_WRITE(PCH_PP_CONTROL, pp); |
1151 | POSTING_READ(PCH_PP_CONTROL); |
1197 | POSTING_READ(PCH_PP_CONTROL); |
- | 1198 | ||
- | 1199 | intel_panel_enable_backlight(dev, pipe); |
|
1152 | } |
1200 | } |
Line 1153... | Line 1201... | ||
1153 | 1201 | ||
1154 | static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
1202 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
1155 | { |
1203 | { |
1156 | struct drm_device *dev = intel_dp->base.base.dev; |
1204 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1157 | struct drm_i915_private *dev_priv = dev->dev_private; |
1205 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1158... | Line 1206... | ||
1158 | u32 pp; |
1206 | u32 pp; |
1159 | 1207 | ||
Line -... | Line 1208... | ||
- | 1208 | if (!is_edp(intel_dp)) |
|
- | 1209 | return; |
|
1160 | if (!is_edp(intel_dp)) |
1210 | |
1161 | return; |
1211 | intel_panel_disable_backlight(dev); |
1162 | 1212 | ||
1163 | DRM_DEBUG_KMS("\n"); |
1213 | DRM_DEBUG_KMS("\n"); |
1164 | pp = ironlake_get_pp_control(dev_priv); |
1214 | pp = ironlake_get_pp_control(dev_priv); |
1165 | pp &= ~EDP_BLC_ENABLE; |
1215 | pp &= ~EDP_BLC_ENABLE; |
1166 | I915_WRITE(PCH_PP_CONTROL, pp); |
1216 | I915_WRITE(PCH_PP_CONTROL, pp); |
Line 1167... | Line 1217... | ||
1167 | POSTING_READ(PCH_PP_CONTROL); |
1217 | POSTING_READ(PCH_PP_CONTROL); |
1168 | msleep(intel_dp->backlight_off_delay); |
1218 | msleep(intel_dp->backlight_off_delay); |
1169 | } |
1219 | } |
1170 | 1220 | ||
- | 1221 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
|
1171 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
1222 | { |
1172 | { |
1223 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Line 1173... | Line 1224... | ||
1173 | struct drm_device *dev = intel_dp->base.base.dev; |
1224 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
1174 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1225 | struct drm_device *dev = crtc->dev; |
Line 1193... | Line 1244... | ||
1193 | udelay(200); |
1244 | udelay(200); |
1194 | } |
1245 | } |
Line 1195... | Line 1246... | ||
1195 | 1246 | ||
1196 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
1247 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
1197 | { |
1248 | { |
1198 | struct drm_device *dev = intel_dp->base.base.dev; |
1249 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | 1250 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
|
1199 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1251 | struct drm_device *dev = crtc->dev; |
1200 | struct drm_i915_private *dev_priv = dev->dev_private; |
1252 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 1201... | Line 1253... | ||
1201 | u32 dpa_ctl; |
1253 | u32 dpa_ctl; |
1202 | 1254 | ||
Line 1216... | Line 1268... | ||
1216 | POSTING_READ(DP_A); |
1268 | POSTING_READ(DP_A); |
1217 | udelay(200); |
1269 | udelay(200); |
1218 | } |
1270 | } |
Line 1219... | Line 1271... | ||
1219 | 1271 | ||
1220 | /* If the sink supports it, try to set the power state appropriately */ |
1272 | /* If the sink supports it, try to set the power state appropriately */ |
1221 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
1273 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
1222 | { |
1274 | { |
Line 1223... | Line 1275... | ||
1223 | int ret, i; |
1275 | int ret, i; |
1224 | 1276 | ||
Line 1286... | Line 1338... | ||
1286 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
1338 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
1287 | *pipe = i; |
1339 | *pipe = i; |
1288 | return true; |
1340 | return true; |
1289 | } |
1341 | } |
1290 | } |
1342 | } |
1291 | } |
- | |
Line 1292... | Line 1343... | ||
1292 | 1343 | ||
- | 1344 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
|
- | 1345 | intel_dp->output_reg); |
|
Line 1293... | Line 1346... | ||
1293 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg); |
1346 | } |
1294 | 1347 | ||
Line 1295... | Line 1348... | ||
1295 | return true; |
1348 | return true; |
Line 1384... | Line 1437... | ||
1384 | DP_LANE0_1_STATUS, |
1437 | DP_LANE0_1_STATUS, |
1385 | link_status, |
1438 | link_status, |
1386 | DP_LINK_STATUS_SIZE); |
1439 | DP_LINK_STATUS_SIZE); |
1387 | } |
1440 | } |
Line 1388... | Line -... | ||
1388 | - | ||
1389 | static uint8_t |
- | |
1390 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], |
- | |
1391 | int r) |
- | |
1392 | { |
- | |
1393 | return link_status[r - DP_LANE0_1_STATUS]; |
- | |
1394 | } |
- | |
1395 | - | ||
1396 | static uint8_t |
- | |
1397 | intel_get_adjust_request_voltage(uint8_t adjust_request[2], |
- | |
1398 | int lane) |
- | |
1399 | { |
- | |
1400 | int s = ((lane & 1) ? |
- | |
1401 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : |
- | |
1402 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); |
- | |
1403 | uint8_t l = adjust_request[lane>>1]; |
- | |
1404 | - | ||
1405 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; |
- | |
1406 | } |
- | |
1407 | - | ||
1408 | static uint8_t |
- | |
1409 | intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2], |
- | |
1410 | int lane) |
- | |
1411 | { |
- | |
1412 | int s = ((lane & 1) ? |
- | |
1413 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : |
- | |
1414 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); |
- | |
1415 | uint8_t l = adjust_request[lane>>1]; |
- | |
1416 | - | ||
1417 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; |
- | |
1418 | } |
- | |
1419 | - | ||
1420 | 1441 | ||
1421 | #if 0 |
1442 | #if 0 |
1422 | static char *voltage_names[] = { |
1443 | static char *voltage_names[] = { |
1423 | "0.4V", "0.6V", "0.8V", "1.2V" |
1444 | "0.4V", "0.6V", "0.8V", "1.2V" |
1424 | }; |
1445 | }; |
Line 1436... | Line 1457... | ||
1436 | */ |
1457 | */ |
Line 1437... | Line 1458... | ||
1437 | 1458 | ||
1438 | static uint8_t |
1459 | static uint8_t |
1439 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
1460 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
1440 | { |
1461 | { |
Line 1441... | Line 1462... | ||
1441 | struct drm_device *dev = intel_dp->base.base.dev; |
1462 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1442 | 1463 | ||
1443 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) |
1464 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) |
1444 | return DP_TRAIN_VOLTAGE_SWING_800; |
1465 | return DP_TRAIN_VOLTAGE_SWING_800; |
Line 1449... | Line 1470... | ||
1449 | } |
1470 | } |
Line 1450... | Line 1471... | ||
1450 | 1471 | ||
1451 | static uint8_t |
1472 | static uint8_t |
1452 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
1473 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
1453 | { |
1474 | { |
Line -... | Line 1475... | ||
- | 1475 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1476 | ||
- | 1477 | if (IS_HASWELL(dev)) { |
|
- | 1478 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 1479 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 1480 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
|
- | 1481 | case DP_TRAIN_VOLTAGE_SWING_600: |
|
- | 1482 | return DP_TRAIN_PRE_EMPHASIS_6; |
|
- | 1483 | case DP_TRAIN_VOLTAGE_SWING_800: |
|
- | 1484 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
|
- | 1485 | case DP_TRAIN_VOLTAGE_SWING_1200: |
|
- | 1486 | default: |
|
1454 | struct drm_device *dev = intel_dp->base.base.dev; |
1487 | return DP_TRAIN_PRE_EMPHASIS_0; |
1455 | 1488 | } |
|
1456 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { |
1489 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
1457 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1490 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1458 | case DP_TRAIN_VOLTAGE_SWING_400: |
1491 | case DP_TRAIN_VOLTAGE_SWING_400: |
1459 | return DP_TRAIN_PRE_EMPHASIS_6; |
1492 | return DP_TRAIN_PRE_EMPHASIS_6; |
Line 1482... | Line 1515... | ||
1482 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
1515 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
1483 | { |
1516 | { |
1484 | uint8_t v = 0; |
1517 | uint8_t v = 0; |
1485 | uint8_t p = 0; |
1518 | uint8_t p = 0; |
1486 | int lane; |
1519 | int lane; |
1487 | uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS); |
- | |
1488 | uint8_t voltage_max; |
1520 | uint8_t voltage_max; |
1489 | uint8_t preemph_max; |
1521 | uint8_t preemph_max; |
Line 1490... | Line 1522... | ||
1490 | 1522 | ||
1491 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1523 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1492 | uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane); |
1524 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
Line 1493... | Line 1525... | ||
1493 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane); |
1525 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
1494 | 1526 | ||
1495 | if (this_v > v) |
1527 | if (this_v > v) |
1496 | v = this_v; |
1528 | v = this_v; |
Line 1605... | Line 1637... | ||
1605 | "0x%x\n", signal_levels); |
1637 | "0x%x\n", signal_levels); |
1606 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
1638 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
1607 | } |
1639 | } |
1608 | } |
1640 | } |
Line 1609... | Line -... | ||
1609 | - | ||
1610 | static uint8_t |
- | |
1611 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], |
- | |
1612 | int lane) |
- | |
1613 | { |
- | |
1614 | int s = (lane & 1) * 4; |
- | |
1615 | uint8_t l = link_status[lane>>1]; |
- | |
1616 | - | ||
1617 | return (l >> s) & 0xf; |
- | |
1618 | } |
- | |
1619 | 1641 | ||
1620 | /* Check for clock recovery is done on all channels */ |
1642 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
1621 | static bool |
1643 | static uint32_t |
1622 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) |
1644 | intel_dp_signal_levels_hsw(uint8_t train_set) |
- | 1645 | { |
|
- | 1646 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
|
1623 | { |
1647 | DP_TRAIN_PRE_EMPHASIS_MASK); |
- | 1648 | switch (signal_levels) { |
|
1624 | int lane; |
1649 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
1625 | uint8_t lane_status; |
- | |
1626 | 1650 | return DDI_BUF_EMP_400MV_0DB_HSW; |
|
1627 | for (lane = 0; lane < lane_count; lane++) { |
1651 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1628 | lane_status = intel_get_lane_status(link_status, lane); |
1652 | return DDI_BUF_EMP_400MV_3_5DB_HSW; |
1629 | if ((lane_status & DP_LANE_CR_DONE) == 0) |
1653 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
1630 | return false; |
- | |
- | 1654 | return DDI_BUF_EMP_400MV_6DB_HSW; |
|
1631 | } |
1655 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: |
1632 | return true; |
- | |
Line 1633... | Line 1656... | ||
1633 | } |
1656 | return DDI_BUF_EMP_400MV_9_5DB_HSW; |
1634 | 1657 | ||
1635 | /* Check to see if channel eq is done on all channels */ |
1658 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1636 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ |
1659 | return DDI_BUF_EMP_600MV_0DB_HSW; |
1637 | DP_LANE_CHANNEL_EQ_DONE|\ |
- | |
1638 | DP_LANE_SYMBOL_LOCKED) |
1660 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1639 | static bool |
- | |
1640 | intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
- | |
1641 | { |
1661 | return DDI_BUF_EMP_600MV_3_5DB_HSW; |
1642 | uint8_t lane_align; |
- | |
Line 1643... | Line 1662... | ||
1643 | uint8_t lane_status; |
1662 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1644 | int lane; |
1663 | return DDI_BUF_EMP_600MV_6DB_HSW; |
- | 1664 | ||
1645 | 1665 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
|
1646 | lane_align = intel_dp_link_status(link_status, |
1666 | return DDI_BUF_EMP_800MV_0DB_HSW; |
1647 | DP_LANE_ALIGN_STATUS_UPDATED); |
- | |
1648 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) |
1667 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1649 | return false; |
1668 | return DDI_BUF_EMP_800MV_3_5DB_HSW; |
1650 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1669 | default: |
1651 | lane_status = intel_get_lane_status(link_status, lane); |
1670 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1652 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
- | |
1653 | return false; |
1671 | "0x%x\n", signal_levels); |
Line 1654... | Line 1672... | ||
1654 | } |
1672 | return DDI_BUF_EMP_400MV_0DB_HSW; |
1655 | return true; |
1673 | } |
1656 | } |
1674 | } |
1657 | 1675 | ||
1658 | static bool |
1676 | static bool |
- | 1677 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
|
1659 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
1678 | uint32_t dp_reg_value, |
1660 | uint32_t dp_reg_value, |
1679 | uint8_t dp_train_pat) |
- | 1680 | { |
|
1661 | uint8_t dp_train_pat) |
1681 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | 1682 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
Line -... | Line 1683... | ||
- | 1683 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1684 | enum port port = intel_dig_port->port; |
|
- | 1685 | int ret; |
|
- | 1686 | uint32_t temp; |
|
- | 1687 | ||
- | 1688 | if (IS_HASWELL(dev)) { |
|
- | 1689 | temp = I915_READ(DP_TP_CTL(port)); |
|
- | 1690 | ||
- | 1691 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
|
- | 1692 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
|
- | 1693 | else |
|
- | 1694 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
|
- | 1695 | ||
- | 1696 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
|
- | 1697 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
|
- | 1698 | case DP_TRAINING_PATTERN_DISABLE: |
|
- | 1699 | temp |= DP_TP_CTL_LINK_TRAIN_IDLE; |
|
- | 1700 | I915_WRITE(DP_TP_CTL(port), temp); |
|
- | 1701 | ||
- | 1702 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & |
|
- | 1703 | DP_TP_STATUS_IDLE_DONE), 1)) |
|
- | 1704 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
|
- | 1705 | ||
- | 1706 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
|
- | 1707 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
|
- | 1708 | ||
- | 1709 | break; |
|
- | 1710 | case DP_TRAINING_PATTERN_1: |
|
- | 1711 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
|
- | 1712 | break; |
|
- | 1713 | case DP_TRAINING_PATTERN_2: |
|
- | 1714 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
|
- | 1715 | break; |
|
- | 1716 | case DP_TRAINING_PATTERN_3: |
|
- | 1717 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
|
1662 | { |
1718 | break; |
1663 | struct drm_device *dev = intel_dp->base.base.dev; |
1719 | } |
Line 1664... | Line 1720... | ||
1664 | struct drm_i915_private *dev_priv = dev->dev_private; |
1720 | I915_WRITE(DP_TP_CTL(port), temp); |
1665 | int ret; |
1721 | |
1666 | 1722 | } else if (HAS_PCH_CPT(dev) && |
|
Line 1722... | Line 1778... | ||
1722 | 1778 | ||
1723 | return true; |
1779 | return true; |
Line 1724... | Line 1780... | ||
1724 | } |
1780 | } |
1725 | 1781 | ||
1726 | /* Enable corresponding port and start training pattern 1 */ |
1782 | /* Enable corresponding port and start training pattern 1 */ |
1727 | static void |
1783 | void |
- | 1784 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
|
1728 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
1785 | { |
1729 | { |
1786 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
1730 | struct drm_device *dev = intel_dp->base.base.dev; |
1787 | struct drm_device *dev = encoder->dev; |
1731 | int i; |
1788 | int i; |
1732 | uint8_t voltage; |
1789 | uint8_t voltage; |
1733 | bool clock_recovery = false; |
1790 | bool clock_recovery = false; |
Line -... | Line 1791... | ||
- | 1791 | int voltage_tries, loop_tries; |
|
- | 1792 | uint32_t DP = intel_dp->DP; |
|
- | 1793 | ||
1734 | int voltage_tries, loop_tries; |
1794 | if (IS_HASWELL(dev)) |
1735 | uint32_t DP = intel_dp->DP; |
1795 | intel_ddi_prepare_link_retrain(encoder); |
1736 | 1796 | ||
1737 | /* Write the link configuration data */ |
1797 | /* Write the link configuration data */ |
Line 1749... | Line 1809... | ||
1749 | for (;;) { |
1809 | for (;;) { |
1750 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
1810 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
1751 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
1811 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
1752 | uint32_t signal_levels; |
1812 | uint32_t signal_levels; |
Line 1753... | Line -... | ||
1753 | - | ||
- | 1813 | ||
- | 1814 | if (IS_HASWELL(dev)) { |
|
- | 1815 | signal_levels = intel_dp_signal_levels_hsw( |
|
- | 1816 | intel_dp->train_set[0]); |
|
1754 | 1817 | DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; |
|
1755 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { |
1818 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
1756 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); |
1819 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); |
1757 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; |
1820 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; |
1758 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
1821 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
1759 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
1822 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
1760 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1823 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1761 | } else { |
1824 | } else { |
1762 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
- | |
1763 | DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels); |
1825 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
1764 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1826 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
- | 1827 | } |
|
- | 1828 | DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", |
|
Line -... | Line 1829... | ||
- | 1829 | signal_levels); |
|
1765 | } |
1830 | |
1766 | 1831 | /* Set training pattern 1 */ |
|
1767 | if (!intel_dp_set_link_train(intel_dp, DP, |
1832 | if (!intel_dp_set_link_train(intel_dp, DP, |
1768 | DP_TRAINING_PATTERN_1 | |
1833 | DP_TRAINING_PATTERN_1 | |
1769 | DP_LINK_SCRAMBLING_DISABLE)) |
- | |
Line 1770... | Line 1834... | ||
1770 | break; |
1834 | DP_LINK_SCRAMBLING_DISABLE)) |
1771 | /* Set training pattern 1 */ |
1835 | break; |
1772 | 1836 | ||
1773 | udelay(100); |
1837 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
1774 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
1838 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
Line 1775... | Line 1839... | ||
1775 | DRM_ERROR("failed to get link status\n"); |
1839 | DRM_ERROR("failed to get link status\n"); |
1776 | break; |
1840 | break; |
1777 | } |
1841 | } |
1778 | 1842 | ||
1779 | if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
1843 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
Line 1813... | Line 1877... | ||
1813 | } |
1877 | } |
Line 1814... | Line 1878... | ||
1814 | 1878 | ||
1815 | intel_dp->DP = DP; |
1879 | intel_dp->DP = DP; |
Line 1816... | Line 1880... | ||
1816 | } |
1880 | } |
1817 | 1881 | ||
1818 | static void |
1882 | void |
1819 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
1883 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
1820 | { |
1884 | { |
1821 | struct drm_device *dev = intel_dp->base.base.dev; |
1885 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1822 | bool channel_eq = false; |
1886 | bool channel_eq = false; |
Line 1823... | Line 1887... | ||
1823 | int tries, cr_tries; |
1887 | int tries, cr_tries; |
Line 1836... | Line 1900... | ||
1836 | DRM_ERROR("failed to train DP, aborting\n"); |
1900 | DRM_ERROR("failed to train DP, aborting\n"); |
1837 | intel_dp_link_down(intel_dp); |
1901 | intel_dp_link_down(intel_dp); |
1838 | break; |
1902 | break; |
1839 | } |
1903 | } |
Line -... | Line 1904... | ||
- | 1904 | ||
- | 1905 | if (IS_HASWELL(dev)) { |
|
- | 1906 | signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]); |
|
1840 | 1907 | DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; |
|
1841 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { |
1908 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
1842 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); |
1909 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); |
1843 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; |
1910 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; |
1844 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
1911 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
1845 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
1912 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
Line 1853... | Line 1920... | ||
1853 | if (!intel_dp_set_link_train(intel_dp, DP, |
1920 | if (!intel_dp_set_link_train(intel_dp, DP, |
1854 | DP_TRAINING_PATTERN_2 | |
1921 | DP_TRAINING_PATTERN_2 | |
1855 | DP_LINK_SCRAMBLING_DISABLE)) |
1922 | DP_LINK_SCRAMBLING_DISABLE)) |
1856 | break; |
1923 | break; |
Line 1857... | Line 1924... | ||
1857 | 1924 | ||
1858 | udelay(400); |
1925 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
1859 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
1926 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
Line 1860... | Line 1927... | ||
1860 | break; |
1927 | break; |
1861 | 1928 | ||
1862 | /* Make sure clock is still ok */ |
1929 | /* Make sure clock is still ok */ |
1863 | if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
1930 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
1864 | intel_dp_start_link_train(intel_dp); |
1931 | intel_dp_start_link_train(intel_dp); |
1865 | cr_tries++; |
1932 | cr_tries++; |
Line 1866... | Line 1933... | ||
1866 | continue; |
1933 | continue; |
1867 | } |
1934 | } |
1868 | 1935 | ||
1869 | if (intel_channel_eq_ok(intel_dp, link_status)) { |
1936 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
Line 1870... | Line 1937... | ||
1870 | channel_eq = true; |
1937 | channel_eq = true; |
Line 1883... | Line 1950... | ||
1883 | /* Compute new intel_dp->train_set as requested by target */ |
1950 | /* Compute new intel_dp->train_set as requested by target */ |
1884 | intel_get_adjust_train(intel_dp, link_status); |
1951 | intel_get_adjust_train(intel_dp, link_status); |
1885 | ++tries; |
1952 | ++tries; |
1886 | } |
1953 | } |
Line -... | Line 1954... | ||
- | 1954 | ||
- | 1955 | if (channel_eq) |
|
- | 1956 | DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n"); |
|
1887 | 1957 | ||
1888 | intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE); |
1958 | intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE); |
Line 1889... | Line 1959... | ||
1889 | } |
1959 | } |
1890 | 1960 | ||
1891 | static void |
1961 | static void |
- | 1962 | intel_dp_link_down(struct intel_dp *intel_dp) |
|
1892 | intel_dp_link_down(struct intel_dp *intel_dp) |
1963 | { |
1893 | { |
1964 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1894 | struct drm_device *dev = intel_dp->base.base.dev; |
1965 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Line -... | Line 1966... | ||
- | 1966 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1967 | uint32_t DP = intel_dp->DP; |
|
- | 1968 | ||
- | 1969 | /* |
|
- | 1970 | * DDI code has a strict mode set sequence and we should try to respect |
|
- | 1971 | * it, otherwise we might hang the machine in many different ways. So we |
|
- | 1972 | * really should be disabling the port only on a complete crtc_disable |
|
- | 1973 | * sequence. This function is just called under two conditions on DDI |
|
- | 1974 | * code: |
|
- | 1975 | * - Link train failed while doing crtc_enable, and on this case we |
|
- | 1976 | * really should respect the mode set sequence and wait for a |
|
- | 1977 | * crtc_disable. |
|
- | 1978 | * - Someone turned the monitor off and intel_dp_check_link_status |
|
- | 1979 | * called us. We don't need to disable the whole port on this case, so |
|
- | 1980 | * when someone turns the monitor on again, |
|
- | 1981 | * intel_ddi_prepare_link_retrain will take care of redoing the link |
|
- | 1982 | * train. |
|
- | 1983 | */ |
|
1895 | struct drm_i915_private *dev_priv = dev->dev_private; |
1984 | if (IS_HASWELL(dev)) |
1896 | uint32_t DP = intel_dp->DP; |
1985 | return; |
Line 1897... | Line 1986... | ||
1897 | 1986 | ||
Line 1911... | Line 2000... | ||
1911 | 2000 | ||
Line 1912... | Line 2001... | ||
1912 | msleep(17); |
2001 | msleep(17); |
1913 | 2002 | ||
1914 | if (HAS_PCH_IBX(dev) && |
2003 | if (HAS_PCH_IBX(dev) && |
Line 1915... | Line 2004... | ||
1915 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
2004 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
1916 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
2005 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
1917 | 2006 | ||
1918 | /* Hardware workaround: leaving our transcoder select |
2007 | /* Hardware workaround: leaving our transcoder select |
Line 2012... | Line 2101... | ||
2012 | 2101 | ||
2013 | static void |
2102 | static void |
2014 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
2103 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
2015 | { |
2104 | { |
2016 | /* NAK by default */ |
2105 | /* NAK by default */ |
2017 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK); |
2106 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
Line 2018... | Line 2107... | ||
2018 | } |
2107 | } |
2019 | 2108 | ||
2020 | /* |
2109 | /* |
Line 2024... | Line 2113... | ||
2024 | * 2. Configure link according to Receiver Capabilities |
2113 | * 2. Configure link according to Receiver Capabilities |
2025 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
2114 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
2026 | * 4. Check link status on receipt of hot-plug interrupt |
2115 | * 4. Check link status on receipt of hot-plug interrupt |
2027 | */ |
2116 | */ |
Line 2028... | Line 2117... | ||
2028 | 2117 | ||
2029 | static void |
2118 | void |
2030 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
2119 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
- | 2120 | { |
|
2031 | { |
2121 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
2032 | u8 sink_irq_vector; |
2122 | u8 sink_irq_vector; |
Line 2033... | Line 2123... | ||
2033 | u8 link_status[DP_LINK_STATUS_SIZE]; |
2123 | u8 link_status[DP_LINK_STATUS_SIZE]; |
2034 | 2124 | ||
Line 2035... | Line 2125... | ||
2035 | if (!intel_dp->base.connectors_active) |
2125 | if (!intel_encoder->connectors_active) |
2036 | return; |
2126 | return; |
Line 2037... | Line 2127... | ||
2037 | 2127 | ||
2038 | if (WARN_ON(!intel_dp->base.base.crtc)) |
2128 | if (WARN_ON(!intel_encoder->base.crtc)) |
2039 | return; |
2129 | return; |
Line 2062... | Line 2152... | ||
2062 | intel_dp_handle_test_request(intel_dp); |
2152 | intel_dp_handle_test_request(intel_dp); |
2063 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
2153 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
2064 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
2154 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
2065 | } |
2155 | } |
Line 2066... | Line 2156... | ||
2066 | 2156 | ||
2067 | if (!intel_channel_eq_ok(intel_dp, link_status)) { |
2157 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
2068 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
2158 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
2069 | drm_get_encoder_name(&intel_dp->base.base)); |
2159 | drm_get_encoder_name(&intel_encoder->base)); |
2070 | intel_dp_start_link_train(intel_dp); |
2160 | intel_dp_start_link_train(intel_dp); |
2071 | intel_dp_complete_link_train(intel_dp); |
2161 | intel_dp_complete_link_train(intel_dp); |
2072 | } |
2162 | } |
Line 2113... | Line 2203... | ||
2113 | } |
2203 | } |
Line 2114... | Line 2204... | ||
2114 | 2204 | ||
2115 | static enum drm_connector_status |
2205 | static enum drm_connector_status |
2116 | ironlake_dp_detect(struct intel_dp *intel_dp) |
2206 | ironlake_dp_detect(struct intel_dp *intel_dp) |
- | 2207 | { |
|
2117 | { |
2208 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Line 2118... | Line 2209... | ||
2118 | enum drm_connector_status status; |
2209 | enum drm_connector_status status; |
2119 | 2210 | ||
2120 | /* Can't disconnect eDP, but you can close the lid... */ |
2211 | /* Can't disconnect eDP, but you can close the lid... */ |
2121 | if (is_edp(intel_dp)) { |
2212 | if (is_edp(intel_dp)) { |
2122 | status = intel_panel_detect(intel_dp->base.base.dev); |
2213 | status = intel_panel_detect(dev); |
2123 | if (status == connector_status_unknown) |
2214 | if (status == connector_status_unknown) |
2124 | status = connector_status_connected; |
2215 | status = connector_status_connected; |
Line 2129... | Line 2220... | ||
2129 | } |
2220 | } |
Line 2130... | Line 2221... | ||
2130 | 2221 | ||
2131 | static enum drm_connector_status |
2222 | static enum drm_connector_status |
2132 | g4x_dp_detect(struct intel_dp *intel_dp) |
2223 | g4x_dp_detect(struct intel_dp *intel_dp) |
2133 | { |
2224 | { |
2134 | struct drm_device *dev = intel_dp->base.base.dev; |
2225 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2135 | struct drm_i915_private *dev_priv = dev->dev_private; |
2226 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 2136... | Line 2227... | ||
2136 | uint32_t bit; |
2227 | uint32_t bit; |
2137 | 2228 | ||
Line 2156... | Line 2247... | ||
2156 | } |
2247 | } |
Line 2157... | Line 2248... | ||
2157 | 2248 | ||
2158 | static struct edid * |
2249 | static struct edid * |
2159 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
2250 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
2160 | { |
2251 | { |
- | 2252 | struct intel_connector *intel_connector = to_intel_connector(connector); |
|
- | 2253 | ||
- | 2254 | /* use cached edid if we have one */ |
|
2161 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2255 | if (intel_connector->edid) { |
2162 | struct edid *edid; |
2256 | struct edid *edid; |
Line 2163... | Line 2257... | ||
2163 | int size; |
2257 | int size; |
2164 | 2258 | ||
2165 | if (is_edp(intel_dp)) { |
2259 | /* invalid edid */ |
Line 2166... | Line 2260... | ||
2166 | if (!intel_dp->edid) |
2260 | if (IS_ERR(intel_connector->edid)) |
2167 | return NULL; |
2261 | return NULL; |
2168 | 2262 | ||
2169 | size = (intel_dp->edid->extensions + 1) * EDID_LENGTH; |
2263 | size = (intel_connector->edid->extensions + 1) * EDID_LENGTH; |
Line 2170... | Line 2264... | ||
2170 | edid = kmalloc(size, GFP_KERNEL); |
2264 | edid = kmalloc(size, GFP_KERNEL); |
2171 | if (!edid) |
2265 | if (!edid) |
2172 | return NULL; |
2266 | return NULL; |
Line 2173... | Line 2267... | ||
2173 | 2267 | ||
2174 | memcpy(edid, intel_dp->edid, size); |
- | |
2175 | return edid; |
2268 | memcpy(edid, intel_connector->edid, size); |
Line 2176... | Line 2269... | ||
2176 | } |
2269 | return edid; |
2177 | 2270 | } |
|
2178 | edid = drm_get_edid(connector, adapter); |
2271 | |
2179 | return edid; |
2272 | return drm_get_edid(connector, adapter); |
2180 | } |
- | |
Line 2181... | Line 2273... | ||
2181 | 2273 | } |
|
2182 | static int |
2274 | |
2183 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
2275 | static int |
2184 | { |
2276 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
2185 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2277 | { |
- | 2278 | struct intel_connector *intel_connector = to_intel_connector(connector); |
|
2186 | int ret; |
2279 | |
2187 | 2280 | /* use cached edid if we have one */ |
|
2188 | if (is_edp(intel_dp)) { |
2281 | if (intel_connector->edid) { |
Line 2189... | Line 2282... | ||
2189 | drm_mode_connector_update_edid_property(connector, |
2282 | /* invalid edid */ |
2190 | intel_dp->edid); |
- | |
2191 | ret = drm_add_edid_modes(connector, intel_dp->edid); |
2283 | if (IS_ERR(intel_connector->edid)) |
Line 2192... | Line 2284... | ||
2192 | drm_edid_to_eld(connector, |
2284 | return 0; |
2193 | intel_dp->edid); |
2285 | |
Line 2207... | Line 2299... | ||
2207 | */ |
2299 | */ |
2208 | static enum drm_connector_status |
2300 | static enum drm_connector_status |
2209 | intel_dp_detect(struct drm_connector *connector, bool force) |
2301 | intel_dp_detect(struct drm_connector *connector, bool force) |
2210 | { |
2302 | { |
2211 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2303 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
- | 2304 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 2305 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
2212 | struct drm_device *dev = intel_dp->base.base.dev; |
2306 | struct drm_device *dev = connector->dev; |
2213 | enum drm_connector_status status; |
2307 | enum drm_connector_status status; |
2214 | struct edid *edid = NULL; |
2308 | struct edid *edid = NULL; |
- | 2309 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
|
Line 2215... | Line 2310... | ||
2215 | 2310 | ||
Line 2216... | Line 2311... | ||
2216 | intel_dp->has_audio = false; |
2311 | intel_dp->has_audio = false; |
2217 | 2312 | ||
2218 | if (HAS_PCH_SPLIT(dev)) |
2313 | if (HAS_PCH_SPLIT(dev)) |
2219 | status = ironlake_dp_detect(intel_dp); |
2314 | status = ironlake_dp_detect(intel_dp); |
Line 2220... | Line -... | ||
2220 | else |
- | |
2221 | status = g4x_dp_detect(intel_dp); |
2315 | else |
2222 | 2316 | status = g4x_dp_detect(intel_dp); |
|
2223 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
2317 | |
Line 2224... | Line 2318... | ||
2224 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], |
2318 | // hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
2225 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], |
2319 | // 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
Line 2226... | Line 2320... | ||
2226 | intel_dp->dpcd[6], intel_dp->dpcd[7]); |
2320 | // DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
Line 2227... | Line -... | ||
2227 | - | ||
2228 | if (status != connector_status_connected) |
2321 | |
2229 | return status; |
2322 | if (status != connector_status_connected) |
2230 | 2323 | return status; |
|
2231 | intel_dp_probe_oui(intel_dp); |
2324 | |
2232 | 2325 | intel_dp_probe_oui(intel_dp); |
|
2233 | /* |
2326 | |
2234 | if (intel_dp->force_audio) { |
2327 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
2235 | intel_dp->has_audio = intel_dp->force_audio > 0; |
2328 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
2236 | } else { |
2329 | } else { |
2237 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
2330 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
- | 2331 | if (edid) { |
|
- | 2332 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
|
2238 | if (edid) { |
2333 | kfree(edid); |
2239 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
2334 | } |
Line 2240... | Line 2335... | ||
2240 | kfree(edid); |
2335 | } |
2241 | } |
2336 | |
2242 | } |
2337 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
2243 | */ |
2338 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
2244 | return connector_status_connected; |
2339 | return connector_status_connected; |
2245 | } |
2340 | } |
Line 2246... | Line 2341... | ||
2246 | 2341 | ||
2247 | static int intel_dp_get_modes(struct drm_connector *connector) |
2342 | static int intel_dp_get_modes(struct drm_connector *connector) |
Line 2248... | Line 2343... | ||
2248 | { |
2343 | { |
2249 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2344 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2250 | struct drm_device *dev = intel_dp->base.base.dev; |
- | |
2251 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
2252 | int ret; |
- | |
2253 | - | ||
2254 | /* We should parse the EDID data and find out if it has an audio sink |
- | |
2255 | */ |
- | |
2256 | - | ||
2257 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
- | |
2258 | if (ret) { |
- | |
2259 | if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { |
- | |
2260 | struct drm_display_mode *newmode; |
- | |
2261 | list_for_each_entry(newmode, &connector->probed_modes, |
2345 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2262 | head) { |
- | |
Line 2263... | Line 2346... | ||
2263 | if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { |
2346 | struct drm_device *dev = connector->dev; |
2264 | intel_dp->panel_fixed_mode = |
- | |
2265 | drm_mode_duplicate(dev, newmode); |
- | |
2266 | break; |
- | |
2267 | } |
- | |
2268 | } |
- | |
2269 | } |
- | |
2270 | return ret; |
- | |
2271 | } |
- | |
2272 | - | ||
2273 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ |
- | |
2274 | if (is_edp(intel_dp)) { |
2347 | int ret; |
2275 | /* initialize panel mode from VBT if available for eDP */ |
2348 | |
- | 2349 | /* We should parse the EDID data and find out if it has an audio sink |
|
2276 | if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { |
2350 | */ |
- | 2351 | ||
2277 | intel_dp->panel_fixed_mode = |
2352 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
2278 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
2353 | if (ret) |
2279 | if (intel_dp->panel_fixed_mode) { |
2354 | return ret; |
2280 | intel_dp->panel_fixed_mode->type |= |
2355 | |
2281 | DRM_MODE_TYPE_PREFERRED; |
2356 | /* if eDP has no EDID, fall back to fixed mode */ |
2282 | } |
2357 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
Line -... | Line 2358... | ||
- | 2358 | struct drm_display_mode *mode; |
|
- | 2359 | mode = drm_mode_duplicate(dev, |
|
- | 2360 | intel_connector->panel.fixed_mode); |
|
- | 2361 | if (mode) { |
|
- | 2362 | drm_mode_probed_add(connector, mode); |
|
- | 2363 | return 1; |
|
Line -... | Line 2364... | ||
- | 2364 | } |
|
- | 2365 | } |
|
- | 2366 | return 0; |
|
- | 2367 | } |
|
- | 2368 | ||
Line -... | Line 2369... | ||
- | 2369 | static bool |
|
2283 | } |
2370 | intel_dp_detect_audio(struct drm_connector *connector) |
Line 2284... | Line 2371... | ||
2284 | if (intel_dp->panel_fixed_mode) { |
2371 | { |
2285 | struct drm_display_mode *mode; |
2372 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2286 | mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); |
2373 | struct edid *edid; |
2287 | drm_mode_probed_add(connector, mode); |
2374 | bool has_audio = false; |
2288 | return 1; |
2375 | |
2289 | } |
2376 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
- | 2377 | if (edid) { |
|
2290 | } |
2378 | has_audio = drm_detect_monitor_audio(edid); |
- | 2379 | kfree(edid); |
|
2291 | return 0; |
2380 | } |
Line 2292... | Line 2381... | ||
2292 | } |
2381 | |
2293 | 2382 | return has_audio; |
|
2294 | 2383 | } |
|
2295 | 2384 | ||
2296 | 2385 | static int |
|
2297 | 2386 | intel_dp_set_property(struct drm_connector *connector, |
|
Line 2336... | Line 2425... | ||
2336 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; |
2425 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; |
2337 | goto done; |
2426 | goto done; |
2338 | } |
2427 | } |
2339 | #endif |
2428 | #endif |
Line -... | Line 2429... | ||
- | 2429 | ||
- | 2430 | if (is_edp(intel_dp) && |
|
- | 2431 | property == connector->dev->mode_config.scaling_mode_property) { |
|
- | 2432 | if (val == DRM_MODE_SCALE_NONE) { |
|
- | 2433 | DRM_DEBUG_KMS("no scaling not supported\n"); |
|
- | 2434 | return -EINVAL; |
|
- | 2435 | } |
|
- | 2436 | ||
- | 2437 | if (intel_connector->panel.fitting_mode == val) { |
|
- | 2438 | /* the eDP scaling property is not changed */ |
|
- | 2439 | return 0; |
|
- | 2440 | } |
|
- | 2441 | intel_connector->panel.fitting_mode = val; |
|
- | 2442 | ||
- | 2443 | goto done; |
|
- | 2444 | } |
|
2340 | 2445 | ||
Line 2341... | Line 2446... | ||
2341 | return -EINVAL; |
2446 | return -EINVAL; |
2342 | 2447 | ||
2343 | done: |
2448 | done: |
2344 | if (intel_dp->base.base.crtc) { |
2449 | if (intel_encoder->base.crtc) { |
2345 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
2450 | struct drm_crtc *crtc = intel_encoder->base.crtc; |
2346 | intel_set_mode(crtc, &crtc->mode, |
2451 | intel_set_mode(crtc, &crtc->mode, |
Line 2347... | Line 2452... | ||
2347 | crtc->x, crtc->y, crtc->fb); |
2452 | crtc->x, crtc->y, crtc->fb); |
Line 2353... | Line 2458... | ||
2353 | static void |
2458 | static void |
2354 | intel_dp_destroy(struct drm_connector *connector) |
2459 | intel_dp_destroy(struct drm_connector *connector) |
2355 | { |
2460 | { |
2356 | struct drm_device *dev = connector->dev; |
2461 | struct drm_device *dev = connector->dev; |
2357 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2462 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
- | 2463 | struct intel_connector *intel_connector = to_intel_connector(connector); |
|
Line -... | Line 2464... | ||
- | 2464 | ||
- | 2465 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
|
- | 2466 | kfree(intel_connector->edid); |
|
2358 | 2467 | ||
2359 | if (is_edp(intel_dp)) |
2468 | if (is_edp(intel_dp)) { |
- | 2469 | intel_panel_destroy_backlight(dev); |
|
- | 2470 | intel_panel_fini(&intel_connector->panel); |
|
Line 2360... | Line 2471... | ||
2360 | intel_panel_destroy_backlight(dev); |
2471 | } |
2361 | 2472 | ||
2362 | drm_sysfs_connector_remove(connector); |
2473 | drm_sysfs_connector_remove(connector); |
2363 | drm_connector_cleanup(connector); |
2474 | drm_connector_cleanup(connector); |
Line 2364... | Line 2475... | ||
2364 | kfree(connector); |
2475 | kfree(connector); |
2365 | } |
2476 | } |
- | 2477 | ||
2366 | 2478 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
|
Line 2367... | Line 2479... | ||
2367 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2479 | { |
2368 | { |
2480 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
2369 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2481 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
2370 | 2482 | ||
2371 | // i2c_del_adapter(&intel_dp->adapter); |
2483 | i2c_del_adapter(&intel_dp->adapter); |
2372 | drm_encoder_cleanup(encoder); |
2484 | drm_encoder_cleanup(encoder); |
2373 | if (is_edp(intel_dp)) { |
2485 | if (is_edp(intel_dp)) { |
2374 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
2486 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Line 2375... | Line 2487... | ||
2375 | ironlake_panel_vdd_off_sync(intel_dp); |
2487 | ironlake_panel_vdd_off_sync(intel_dp); |
2376 | } |
2488 | } |
2377 | kfree(intel_dp); |
2489 | kfree(intel_dig_port); |
Line 2402... | Line 2514... | ||
2402 | }; |
2514 | }; |
Line 2403... | Line 2515... | ||
2403 | 2515 | ||
2404 | static void |
2516 | static void |
2405 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
2517 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
2406 | { |
2518 | { |
Line 2407... | Line 2519... | ||
2407 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
2519 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
2408 | 2520 | ||
Line 2409... | Line 2521... | ||
2409 | intel_dp_check_link_status(intel_dp); |
2521 | intel_dp_check_link_status(intel_dp); |
2410 | } |
2522 | } |
2411 | 2523 | ||
2412 | /* Return which DP Port should be selected for Transcoder DP control */ |
2524 | /* Return which DP Port should be selected for Transcoder DP control */ |
2413 | int |
2525 | int |
2414 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
2526 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
- | 2527 | { |
|
Line 2415... | Line 2528... | ||
2415 | { |
2528 | struct drm_device *dev = crtc->dev; |
2416 | struct drm_device *dev = crtc->dev; |
2529 | struct intel_encoder *intel_encoder; |
Line 2417... | Line 2530... | ||
2417 | struct intel_encoder *encoder; |
2530 | struct intel_dp *intel_dp; |
2418 | 2531 | ||
2419 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
2532 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
2420 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2533 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Line 2421... | Line 2534... | ||
2421 | 2534 | ||
2422 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || |
2535 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
Line 2448... | Line 2561... | ||
2448 | } |
2561 | } |
Line 2449... | Line 2562... | ||
2449 | 2562 | ||
2450 | static void |
2563 | static void |
2451 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
2564 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
- | 2565 | { |
|
- | 2566 | struct intel_connector *intel_connector = to_intel_connector(connector); |
|
2452 | { |
2567 | |
2453 | intel_attach_force_audio_property(connector); |
2568 | intel_attach_force_audio_property(connector); |
- | 2569 | intel_attach_broadcast_rgb_property(connector); |
|
- | 2570 | ||
- | 2571 | if (is_edp(intel_dp)) { |
|
- | 2572 | drm_mode_create_scaling_mode_property(connector->dev); |
|
- | 2573 | drm_object_attach_property( |
|
- | 2574 | &connector->base, |
|
- | 2575 | connector->dev->mode_config.scaling_mode_property, |
|
- | 2576 | DRM_MODE_SCALE_ASPECT); |
|
- | 2577 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
|
2454 | intel_attach_broadcast_rgb_property(connector); |
2578 | } |
Line 2455... | Line 2579... | ||
2455 | } |
2579 | } |
2456 | 2580 | ||
- | 2581 | static void |
|
- | 2582 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
|
2457 | void |
2583 | struct intel_dp *intel_dp, |
2458 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
2584 | struct edp_power_seq *out) |
2459 | { |
2585 | { |
- | 2586 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2587 | struct edp_power_seq cur, vbt, spec, final; |
|
- | 2588 | u32 pp_on, pp_off, pp_div, pp; |
|
- | 2589 | ||
- | 2590 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
|
- | 2591 | * the very first thing. */ |
|
- | 2592 | pp = ironlake_get_pp_control(dev_priv); |
|
- | 2593 | I915_WRITE(PCH_PP_CONTROL, pp); |
|
- | 2594 | ||
- | 2595 | pp_on = I915_READ(PCH_PP_ON_DELAYS); |
|
- | 2596 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
|
- | 2597 | pp_div = I915_READ(PCH_PP_DIVISOR); |
|
- | 2598 | ||
- | 2599 | /* Pull timing values out of registers */ |
|
- | 2600 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
|
- | 2601 | PANEL_POWER_UP_DELAY_SHIFT; |
|
- | 2602 | ||
- | 2603 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
|
- | 2604 | PANEL_LIGHT_ON_DELAY_SHIFT; |
|
- | 2605 | ||
- | 2606 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
|
- | 2607 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
|
- | 2608 | ||
- | 2609 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
|
- | 2610 | PANEL_POWER_DOWN_DELAY_SHIFT; |
|
- | 2611 | ||
- | 2612 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
|
- | 2613 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
|
- | 2614 | ||
- | 2615 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
|
- | 2616 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
|
- | 2617 | ||
- | 2618 | vbt = dev_priv->edp.pps; |
|
- | 2619 | ||
- | 2620 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
|
- | 2621 | * our hw here, which are all in 100usec. */ |
|
- | 2622 | spec.t1_t3 = 210 * 10; |
|
- | 2623 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
|
- | 2624 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
|
- | 2625 | spec.t10 = 500 * 10; |
|
- | 2626 | /* This one is special and actually in units of 100ms, but zero |
|
- | 2627 | * based in the hw (so we need to add 100 ms). But the sw vbt |
|
- | 2628 | * table multiplies it with 1000 to make it in units of 100usec, |
|
- | 2629 | * too. */ |
|
- | 2630 | spec.t11_t12 = (510 + 100) * 10; |
|
- | 2631 | ||
- | 2632 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
|
- | 2633 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
|
- | 2634 | ||
- | 2635 | /* Use the max of the register settings and vbt. If both are |
|
- | 2636 | * unset, fall back to the spec limits. */ |
|
- | 2637 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ |
|
- | 2638 | spec.field : \ |
|
- | 2639 | max(cur.field, vbt.field)) |
|
- | 2640 | assign_final(t1_t3); |
|
- | 2641 | assign_final(t8); |
|
- | 2642 | assign_final(t9); |
|
- | 2643 | assign_final(t10); |
|
- | 2644 | assign_final(t11_t12); |
|
- | 2645 | #undef assign_final |
|
- | 2646 | ||
- | 2647 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) |
|
- | 2648 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
|
- | 2649 | intel_dp->backlight_on_delay = get_delay(t8); |
|
- | 2650 | intel_dp->backlight_off_delay = get_delay(t9); |
|
- | 2651 | intel_dp->panel_power_down_delay = get_delay(t10); |
|
- | 2652 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
|
- | 2653 | #undef get_delay |
|
- | 2654 | ||
- | 2655 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
|
- | 2656 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
|
- | 2657 | intel_dp->panel_power_cycle_delay); |
|
- | 2658 | ||
- | 2659 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
|
- | 2660 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
|
- | 2661 | ||
- | 2662 | if (out) |
|
- | 2663 | *out = final; |
|
- | 2664 | } |
|
- | 2665 | ||
2460 | struct drm_i915_private *dev_priv = dev->dev_private; |
2666 | static void |
- | 2667 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
|
- | 2668 | struct intel_dp *intel_dp, |
|
- | 2669 | struct edp_power_seq *seq) |
|
- | 2670 | { |
|
- | 2671 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2672 | u32 pp_on, pp_off, pp_div; |
|
- | 2673 | ||
- | 2674 | /* And finally store the new values in the power sequencer. */ |
|
- | 2675 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
|
- | 2676 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
|
- | 2677 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
|
- | 2678 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
|
- | 2679 | /* Compute the divisor for the pp clock, simply match the Bspec |
|
- | 2680 | * formula. */ |
|
- | 2681 | pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1) |
|
- | 2682 | << PP_REFERENCE_DIVIDER_SHIFT; |
|
- | 2683 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
|
- | 2684 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
|
- | 2685 | ||
- | 2686 | /* Haswell doesn't have any port selection bits for the panel |
|
- | 2687 | * power sequencer any more. */ |
|
- | 2688 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
|
- | 2689 | if (is_cpu_edp(intel_dp)) |
|
- | 2690 | pp_on |= PANEL_POWER_PORT_DP_A; |
|
- | 2691 | else |
|
- | 2692 | pp_on |= PANEL_POWER_PORT_DP_D; |
|
- | 2693 | } |
|
- | 2694 | ||
- | 2695 | I915_WRITE(PCH_PP_ON_DELAYS, pp_on); |
|
- | 2696 | I915_WRITE(PCH_PP_OFF_DELAYS, pp_off); |
|
- | 2697 | I915_WRITE(PCH_PP_DIVISOR, pp_div); |
|
- | 2698 | ||
- | 2699 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
|
- | 2700 | I915_READ(PCH_PP_ON_DELAYS), |
|
- | 2701 | I915_READ(PCH_PP_OFF_DELAYS), |
|
- | 2702 | I915_READ(PCH_PP_DIVISOR)); |
|
- | 2703 | } |
|
- | 2704 | ||
2461 | struct drm_connector *connector; |
2705 | void |
- | 2706 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
|
2462 | struct intel_dp *intel_dp; |
2707 | struct intel_connector *intel_connector) |
- | 2708 | { |
|
- | 2709 | struct drm_connector *connector = &intel_connector->base; |
|
- | 2710 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
|
- | 2711 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
- | 2712 | struct drm_device *dev = intel_encoder->base.dev; |
|
- | 2713 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2714 | struct drm_display_mode *fixed_mode = NULL; |
|
2463 | struct intel_encoder *intel_encoder; |
2715 | struct edp_power_seq power_seq = { 0 }; |
2464 | struct intel_connector *intel_connector; |
2716 | enum port port = intel_dig_port->port; |
Line 2465... | Line -... | ||
2465 | const char *name = NULL; |
- | |
2466 | int type; |
- | |
2467 | - | ||
2468 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
- | |
2469 | if (!intel_dp) |
- | |
2470 | return; |
- | |
2471 | 2717 | const char *name = NULL; |
|
2472 | intel_dp->output_reg = output_reg; |
2718 | int type; |
- | 2719 | ||
Line 2473... | Line -... | ||
2473 | intel_dp->port = port; |
- | |
2474 | /* Preserve the current hw state. */ |
- | |
2475 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
- | |
2476 | - | ||
2477 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
- | |
2478 | if (!intel_connector) { |
- | |
2479 | kfree(intel_dp); |
- | |
2480 | return; |
2720 | /* Preserve the current hw state. */ |
2481 | } |
2721 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
2482 | intel_encoder = &intel_dp->base; |
2722 | intel_dp->attached_connector = intel_connector; |
Line -... | Line 2723... | ||
- | 2723 | ||
- | 2724 | if (HAS_PCH_SPLIT(dev) && port == PORT_D) |
|
- | 2725 | if (intel_dpd_is_edp(dev)) |
|
- | 2726 | intel_dp->is_pch_edp = true; |
|
- | 2727 | ||
- | 2728 | /* |
|
- | 2729 | * FIXME : We need to initialize built-in panels before external panels. |
|
2483 | 2730 | * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup |
|
2484 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
2731 | */ |
2485 | if (intel_dpd_is_edp(dev)) |
2732 | if (IS_VALLEYVIEW(dev) && port == PORT_C) { |
2486 | intel_dp->is_pch_edp = true; |
2733 | type = DRM_MODE_CONNECTOR_eDP; |
- | 2734 | intel_encoder->type = INTEL_OUTPUT_EDP; |
|
- | 2735 | } else if (port == PORT_A || is_pch_edp(intel_dp)) { |
|
- | 2736 | type = DRM_MODE_CONNECTOR_eDP; |
|
- | 2737 | intel_encoder->type = INTEL_OUTPUT_EDP; |
|
2487 | 2738 | } else { |
|
2488 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
- | |
2489 | type = DRM_MODE_CONNECTOR_eDP; |
2739 | /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for |
Line 2490... | Line -... | ||
2490 | intel_encoder->type = INTEL_OUTPUT_EDP; |
- | |
2491 | } else { |
2740 | * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't |
2492 | type = DRM_MODE_CONNECTOR_DisplayPort; |
2741 | * rewrite it. |
Line 2493... | Line 2742... | ||
2493 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
2742 | */ |
2494 | } |
- | |
2495 | - | ||
2496 | connector = &intel_connector->base; |
- | |
2497 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
- | |
2498 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
- | |
2499 | - | ||
2500 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
- | |
2501 | - | ||
2502 | intel_encoder->cloneable = false; |
2743 | type = DRM_MODE_CONNECTOR_DisplayPort; |
2503 | 2744 | } |
|
Line 2504... | Line 2745... | ||
2504 | // INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
2745 | |
2505 | // ironlake_panel_vdd_work); |
2746 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
2506 | - | ||
Line 2507... | Line 2747... | ||
2507 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
2747 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
2508 | 2748 | ||
Line 2509... | Line 2749... | ||
2509 | connector->interlace_allowed = true; |
2749 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
2510 | connector->doublescan_allowed = 0; |
- | |
2511 | - | ||
2512 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
- | |
2513 | DRM_MODE_ENCODER_TMDS); |
2750 | connector->interlace_allowed = true; |
- | 2751 | connector->doublescan_allowed = 0; |
|
2514 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
2752 | |
Line -... | Line 2753... | ||
- | 2753 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
|
2515 | 2754 | ironlake_panel_vdd_work); |
|
2516 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
2755 | |
2517 | drm_sysfs_connector_add(connector); |
2756 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
2518 | 2757 | drm_sysfs_connector_add(connector); |
|
2519 | intel_encoder->enable = intel_enable_dp; |
2758 | |
Line 2543... | Line 2782... | ||
2543 | default: |
2782 | default: |
2544 | WARN(1, "Invalid port %c\n", port_name(port)); |
2783 | WARN(1, "Invalid port %c\n", port_name(port)); |
2545 | break; |
2784 | break; |
2546 | } |
2785 | } |
Line 2547... | Line -... | ||
2547 | - | ||
2548 | /* Cache some DPCD data in the eDP case */ |
2786 | |
2549 | if (is_edp(intel_dp)) { |
- | |
2550 | struct edp_power_seq cur, vbt; |
- | |
2551 | u32 pp_on, pp_off, pp_div; |
- | |
2552 | - | ||
2553 | pp_on = I915_READ(PCH_PP_ON_DELAYS); |
- | |
2554 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
- | |
2555 | pp_div = I915_READ(PCH_PP_DIVISOR); |
- | |
2556 | - | ||
2557 | if (!pp_on || !pp_off || !pp_div) { |
- | |
2558 | DRM_INFO("bad panel power sequencing delays, disabling panel\n"); |
- | |
2559 | intel_dp_encoder_destroy(&intel_dp->base.base); |
- | |
2560 | intel_dp_destroy(&intel_connector->base); |
- | |
2561 | return; |
- | |
2562 | } |
- | |
2563 | - | ||
2564 | /* Pull timing values out of registers */ |
- | |
2565 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
- | |
2566 | PANEL_POWER_UP_DELAY_SHIFT; |
- | |
2567 | - | ||
2568 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
- | |
2569 | PANEL_LIGHT_ON_DELAY_SHIFT; |
- | |
2570 | - | ||
2571 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
- | |
2572 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
- | |
2573 | - | ||
2574 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
- | |
2575 | PANEL_POWER_DOWN_DELAY_SHIFT; |
- | |
2576 | - | ||
2577 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
- | |
2578 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
- | |
2579 | - | ||
2580 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
- | |
2581 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
- | |
2582 | - | ||
2583 | vbt = dev_priv->edp.pps; |
- | |
2584 | - | ||
2585 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
- | |
2586 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
- | |
2587 | - | ||
2588 | #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) |
- | |
2589 | - | ||
2590 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
- | |
2591 | intel_dp->backlight_on_delay = get_delay(t8); |
- | |
2592 | intel_dp->backlight_off_delay = get_delay(t9); |
- | |
2593 | intel_dp->panel_power_down_delay = get_delay(t10); |
2787 | if (is_edp(intel_dp)) |
2594 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
- | |
2595 | - | ||
2596 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
- | |
2597 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
- | |
2598 | intel_dp->panel_power_cycle_delay); |
- | |
2599 | - | ||
2600 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
- | |
2601 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
- | |
Line 2602... | Line 2788... | ||
2602 | } |
2788 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
Line -... | Line 2789... | ||
- | 2789 | ||
2603 | 2790 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
|
2604 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
2791 | |
- | 2792 | /* Cache DPCD and EDID for edp. */ |
|
2605 | 2793 | if (is_edp(intel_dp)) { |
|
Line 2606... | Line 2794... | ||
2606 | if (is_edp(intel_dp)) { |
2794 | bool ret; |
2607 | bool ret; |
2795 | struct drm_display_mode *scan; |
2608 | struct edid *edid; |
2796 | struct edid *edid; |
Line 2617... | Line 2805... | ||
2617 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
2805 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
2618 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2806 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2619 | } else { |
2807 | } else { |
2620 | /* if this fails, presume the device is a ghost */ |
2808 | /* if this fails, presume the device is a ghost */ |
2621 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
2809 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
2622 | intel_dp_encoder_destroy(&intel_dp->base.base); |
2810 | intel_dp_encoder_destroy(&intel_encoder->base); |
2623 | intel_dp_destroy(&intel_connector->base); |
2811 | intel_dp_destroy(connector); |
2624 | return; |
2812 | return; |
2625 | } |
2813 | } |
Line -... | Line 2814... | ||
- | 2814 | ||
- | 2815 | /* We now know it's not a ghost, init power sequence regs. */ |
|
- | 2816 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
|
- | 2817 | &power_seq); |
|
2626 | 2818 | ||
2627 | ironlake_edp_panel_vdd_on(intel_dp); |
2819 | ironlake_edp_panel_vdd_on(intel_dp); |
2628 | edid = drm_get_edid(connector, &intel_dp->adapter); |
2820 | edid = drm_get_edid(connector, &intel_dp->adapter); |
2629 | if (edid) { |
- | |
2630 | drm_mode_connector_update_edid_property(connector, |
- | |
2631 | edid); |
2821 | if (edid) { |
2632 | intel_dp->edid_mode_count = |
2822 | if (drm_add_edid_modes(connector, edid)) { |
2633 | drm_add_edid_modes(connector, edid); |
2823 | drm_mode_connector_update_edid_property(connector, edid); |
- | 2824 | drm_edid_to_eld(connector, edid); |
|
2634 | drm_edid_to_eld(connector, edid); |
2825 | } else { |
- | 2826 | kfree(edid); |
|
2635 | intel_dp->edid = edid; |
2827 | edid = ERR_PTR(-EINVAL); |
- | 2828 | } |
|
2636 | } |
2829 | } else { |
2637 | ironlake_edp_panel_vdd_off(intel_dp, false); |
2830 | edid = ERR_PTR(-ENOENT); |
- | 2831 | } |
|
Line -... | Line 2832... | ||
- | 2832 | intel_connector->edid = edid; |
|
- | 2833 | ||
- | 2834 | /* prefer fixed mode from EDID if available */ |
|
- | 2835 | list_for_each_entry(scan, &connector->probed_modes, head) { |
|
- | 2836 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
|
- | 2837 | fixed_mode = drm_mode_duplicate(dev, scan); |
|
- | 2838 | break; |
|
- | 2839 | } |
|
- | 2840 | } |
|
- | 2841 | ||
- | 2842 | /* fallback to VBT if available for eDP */ |
|
- | 2843 | if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) { |
|
- | 2844 | fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
|
- | 2845 | if (fixed_mode) |
|
- | 2846 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
|
2638 | } |
2847 | } |
- | 2848 | ||
Line 2639... | Line 2849... | ||
2639 | 2849 | ironlake_edp_panel_vdd_off(intel_dp, false); |
|
2640 | intel_encoder->hot_plug = intel_dp_hot_plug; |
2850 | } |
2641 | 2851 | ||
2642 | if (is_edp(intel_dp)) { |
2852 | if (is_edp(intel_dp)) { |
Line 2643... | Line 2853... | ||
2643 | dev_priv->int_edp_connector = connector; |
2853 | intel_panel_init(&intel_connector->panel, fixed_mode); |
Line 2644... | Line 2854... | ||
2644 | intel_panel_setup_backlight(dev); |
2854 | intel_panel_setup_backlight(connector); |
Line 2653... | Line 2863... | ||
2653 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
2863 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
2654 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
2864 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
2655 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
2865 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
2656 | } |
2866 | } |
2657 | }><>><>><>>>>>>>><>><>>>>>>><>><>><>=>=><=>=>=>>>><>><>><>>><>>><>>><>><>><>>>>>><>>> |
2867 | } |
- | 2868 | ||
- | 2869 | void |
|
- | 2870 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
|
- | 2871 | { |
|
- | 2872 | struct intel_digital_port *intel_dig_port; |
|
- | 2873 | struct intel_encoder *intel_encoder; |
|
- | 2874 | struct drm_encoder *encoder; |
|
- | 2875 | struct intel_connector *intel_connector; |
|
- | 2876 | ||
- | 2877 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); |
|
- | 2878 | if (!intel_dig_port) |
|
- | 2879 | return; |
|
- | 2880 | ||
- | 2881 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
|
- | 2882 | if (!intel_connector) { |
|
- | 2883 | kfree(intel_dig_port); |
|
- | 2884 | return; |
|
- | 2885 | } |
|
- | 2886 | ||
- | 2887 | intel_encoder = &intel_dig_port->base; |
|
- | 2888 | encoder = &intel_encoder->base; |
|
- | 2889 | ||
- | 2890 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
|
- | 2891 | DRM_MODE_ENCODER_TMDS); |
|
- | 2892 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
|
- | 2893 | ||
- | 2894 | intel_encoder->enable = intel_enable_dp; |
|
- | 2895 | intel_encoder->pre_enable = intel_pre_enable_dp; |
|
- | 2896 | intel_encoder->disable = intel_disable_dp; |
|
- | 2897 | intel_encoder->post_disable = intel_post_disable_dp; |
|
- | 2898 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
|
- | 2899 | ||
- | 2900 | intel_dig_port->port = port; |
|
- | 2901 | intel_dig_port->dp.output_reg = output_reg; |
|
- | 2902 | ||
- | 2903 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
|
- | 2904 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
|
- | 2905 | intel_encoder->cloneable = false; |
|
- | 2906 | intel_encoder->hot_plug = intel_dp_hot_plug; |
|
- | 2907 | ||
- | 2908 | intel_dp_init_connector(intel_dig_port, intel_connector); |
|
- | 2909 | }><>><>><>><>><>><>><>><>><>>>>>>>>>>><>=>=><=>=>=>>>><>><>><>>><>>><>>><>><>><>>>>>><>>> |