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Rev 6935 | Rev 6937 | ||
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Line 42... | Line 42... | ||
42 | #include |
42 | #include |
43 | #include |
43 | #include |
44 | #include |
44 | #include |
45 | #include |
45 | #include |
46 | #include |
46 | #include |
- | 47 | #include |
|
- | 48 | #include |
|
Line 47... | Line 49... | ||
47 | 49 | ||
48 | /* Primary plane formats for gen <= 3 */ |
50 | /* Primary plane formats for gen <= 3 */ |
49 | static const uint32_t i8xx_primary_formats[] = { |
51 | static const uint32_t i8xx_primary_formats[] = { |
50 | DRM_FORMAT_C8, |
52 | DRM_FORMAT_C8, |
Line 184... | Line 186... | ||
184 | { |
186 | { |
185 | struct drm_i915_private *dev_priv = dev->dev_private; |
187 | struct drm_i915_private *dev_priv = dev->dev_private; |
186 | uint32_t clkcfg; |
188 | uint32_t clkcfg; |
Line 187... | Line 189... | ||
187 | 189 | ||
188 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
190 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
189 | if (IS_VALLEYVIEW(dev)) |
191 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Line 190... | Line 192... | ||
190 | return 200; |
192 | return 200; |
191 | 193 | ||
192 | clkcfg = I915_READ(CLKCFG); |
194 | clkcfg = I915_READ(CLKCFG); |
Line 212... | Line 214... | ||
212 | } |
214 | } |
213 | } |
215 | } |
Line 214... | Line 216... | ||
214 | 216 | ||
215 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
217 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
216 | { |
218 | { |
217 | if (!IS_VALLEYVIEW(dev_priv)) |
219 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
Line 218... | Line 220... | ||
218 | return; |
220 | return; |
219 | 221 | ||
Line 713... | Line 715... | ||
713 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
715 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
714 | INTELPllInvalid("m2 out of range\n"); |
716 | INTELPllInvalid("m2 out of range\n"); |
715 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
717 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
716 | INTELPllInvalid("m1 out of range\n"); |
718 | INTELPllInvalid("m1 out of range\n"); |
Line 717... | Line 719... | ||
717 | 719 | ||
- | 720 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
|
718 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
721 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) |
719 | if (clock->m1 <= clock->m2) |
722 | if (clock->m1 <= clock->m2) |
Line 720... | Line 723... | ||
720 | INTELPllInvalid("m1 <= m2\n"); |
723 | INTELPllInvalid("m1 <= m2\n"); |
721 | 724 | ||
722 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
725 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
723 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
726 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
724 | INTELPllInvalid("p out of range\n"); |
727 | INTELPllInvalid("p out of range\n"); |
725 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
728 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
Line 1094... | Line 1097... | ||
1094 | } |
1097 | } |
Line 1095... | Line 1098... | ||
1095 | 1098 | ||
1096 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1099 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1097 | { |
1100 | { |
1098 | struct drm_i915_private *dev_priv = dev->dev_private; |
1101 | struct drm_i915_private *dev_priv = dev->dev_private; |
1099 | u32 reg = PIPEDSL(pipe); |
1102 | i915_reg_t reg = PIPEDSL(pipe); |
1100 | u32 line1, line2; |
1103 | u32 line1, line2; |
Line 1101... | Line 1104... | ||
1101 | u32 line_mask; |
1104 | u32 line_mask; |
1102 | 1105 | ||
Line 1134... | Line 1137... | ||
1134 | struct drm_i915_private *dev_priv = dev->dev_private; |
1137 | struct drm_i915_private *dev_priv = dev->dev_private; |
1135 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1138 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1136 | enum pipe pipe = crtc->pipe; |
1139 | enum pipe pipe = crtc->pipe; |
Line 1137... | Line 1140... | ||
1137 | 1140 | ||
1138 | if (INTEL_INFO(dev)->gen >= 4) { |
1141 | if (INTEL_INFO(dev)->gen >= 4) { |
Line 1139... | Line 1142... | ||
1139 | int reg = PIPECONF(cpu_transcoder); |
1142 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
1140 | 1143 | ||
1141 | /* Wait for the Pipe State to go off */ |
1144 | /* Wait for the Pipe State to go off */ |
1142 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1145 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
Line 1284... | Line 1287... | ||
1284 | 1287 | ||
1285 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1288 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1286 | enum pipe pipe) |
1289 | enum pipe pipe) |
1287 | { |
1290 | { |
1288 | struct drm_device *dev = dev_priv->dev; |
1291 | struct drm_device *dev = dev_priv->dev; |
1289 | int pp_reg; |
1292 | i915_reg_t pp_reg; |
1290 | u32 val; |
1293 | u32 val; |
1291 | enum pipe panel_pipe = PIPE_A; |
1294 | enum pipe panel_pipe = PIPE_A; |
Line 1292... | Line 1295... | ||
1292 | bool locked = true; |
1295 | bool locked = true; |
Line 1302... | Line 1305... | ||
1302 | 1305 | ||
1303 | if (port_sel == PANEL_PORT_SELECT_LVDS && |
1306 | if (port_sel == PANEL_PORT_SELECT_LVDS && |
1304 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) |
1307 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) |
1305 | panel_pipe = PIPE_B; |
1308 | panel_pipe = PIPE_B; |
1306 | /* XXX: else fix for eDP */ |
1309 | /* XXX: else fix for eDP */ |
1307 | } else if (IS_VALLEYVIEW(dev)) { |
1310 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
1308 | /* presumably write lock depends on pipe, not port select */ |
1311 | /* presumably write lock depends on pipe, not port select */ |
1309 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); |
1312 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); |
1310 | panel_pipe = pipe; |
1313 | panel_pipe = pipe; |
1311 | } else { |
1314 | } else { |
Line 1346... | Line 1349... | ||
1346 | enum pipe pipe, bool state) |
1349 | enum pipe pipe, bool state) |
1347 | { |
1350 | { |
1348 | bool cur_state; |
1351 | bool cur_state; |
1349 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1352 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1350 | pipe); |
1353 | pipe); |
- | 1354 | enum intel_display_power_domain power_domain; |
|
Line 1351... | Line 1355... | ||
1351 | 1355 | ||
1352 | /* if we need the pipe quirk it must be always on */ |
1356 | /* if we need the pipe quirk it must be always on */ |
1353 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1357 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1354 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
1358 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
Line 1355... | Line -... | ||
1355 | state = true; |
- | |
1356 | 1359 | state = true; |
|
1357 | if (!intel_display_power_is_enabled(dev_priv, |
1360 | |
1358 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
- | |
1359 | cur_state = false; |
1361 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1360 | } else { |
1362 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { |
- | 1363 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
|
- | 1364 | cur_state = !!(val & PIPECONF_ENABLE); |
|
- | 1365 | ||
- | 1366 | intel_display_power_put(dev_priv, power_domain); |
|
1361 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
1367 | } else { |
Line 1362... | Line 1368... | ||
1362 | cur_state = !!(val & PIPECONF_ENABLE); |
1368 | cur_state = false; |
1363 | } |
1369 | } |
1364 | 1370 | ||
Line 1420... | Line 1426... | ||
1420 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
1426 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
1421 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
1427 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
1422 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1428 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1423 | sprite, pipe_name(pipe)); |
1429 | sprite, pipe_name(pipe)); |
1424 | } |
1430 | } |
1425 | } else if (IS_VALLEYVIEW(dev)) { |
1431 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
1426 | for_each_sprite(dev_priv, pipe, sprite) { |
1432 | for_each_sprite(dev_priv, pipe, sprite) { |
1427 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
1433 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
1428 | I915_STATE_WARN(val & SP_ENABLE, |
1434 | I915_STATE_WARN(val & SP_ENABLE, |
1429 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1435 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1430 | sprite_name(pipe, sprite), pipe_name(pipe)); |
1436 | sprite_name(pipe, sprite), pipe_name(pipe)); |
Line 1479... | Line 1485... | ||
1479 | { |
1485 | { |
1480 | if ((val & DP_PORT_EN) == 0) |
1486 | if ((val & DP_PORT_EN) == 0) |
1481 | return false; |
1487 | return false; |
Line 1482... | Line 1488... | ||
1482 | 1488 | ||
1483 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1489 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1484 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
- | |
1485 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1490 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
1486 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1491 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1487 | return false; |
1492 | return false; |
1488 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1493 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1489 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1494 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
Line 1544... | Line 1549... | ||
1544 | } |
1549 | } |
1545 | return true; |
1550 | return true; |
1546 | } |
1551 | } |
Line 1547... | Line 1552... | ||
1547 | 1552 | ||
1548 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1553 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
- | 1554 | enum pipe pipe, i915_reg_t reg, |
|
1549 | enum pipe pipe, int reg, u32 port_sel) |
1555 | u32 port_sel) |
1550 | { |
1556 | { |
1551 | u32 val = I915_READ(reg); |
1557 | u32 val = I915_READ(reg); |
1552 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
1558 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
1553 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
1559 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
Line 1554... | Line 1560... | ||
1554 | reg, pipe_name(pipe)); |
1560 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
1555 | 1561 | ||
1556 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1562 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1557 | && (val & DP_PIPEB_SELECT), |
1563 | && (val & DP_PIPEB_SELECT), |
Line 1558... | Line 1564... | ||
1558 | "IBX PCH dp port still using transcoder B\n"); |
1564 | "IBX PCH dp port still using transcoder B\n"); |
1559 | } |
1565 | } |
1560 | 1566 | ||
1561 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
1567 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
1562 | enum pipe pipe, int reg) |
1568 | enum pipe pipe, i915_reg_t reg) |
1563 | { |
1569 | { |
1564 | u32 val = I915_READ(reg); |
1570 | u32 val = I915_READ(reg); |
Line 1565... | Line 1571... | ||
1565 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1571 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1566 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
1572 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
1567 | reg, pipe_name(pipe)); |
1573 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
1568 | 1574 | ||
Line 1598... | Line 1604... | ||
1598 | static void vlv_enable_pll(struct intel_crtc *crtc, |
1604 | static void vlv_enable_pll(struct intel_crtc *crtc, |
1599 | const struct intel_crtc_state *pipe_config) |
1605 | const struct intel_crtc_state *pipe_config) |
1600 | { |
1606 | { |
1601 | struct drm_device *dev = crtc->base.dev; |
1607 | struct drm_device *dev = crtc->base.dev; |
1602 | struct drm_i915_private *dev_priv = dev->dev_private; |
1608 | struct drm_i915_private *dev_priv = dev->dev_private; |
1603 | int reg = DPLL(crtc->pipe); |
1609 | i915_reg_t reg = DPLL(crtc->pipe); |
1604 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
1610 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
Line 1605... | Line 1611... | ||
1605 | 1611 | ||
Line 1606... | Line -... | ||
1606 | assert_pipe_disabled(dev_priv, crtc->pipe); |
- | |
1607 | - | ||
1608 | /* No really, not for ILK+ */ |
- | |
1609 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
1612 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1610 | 1613 | ||
1611 | /* PLL is protected by panel, make sure we can write it */ |
1614 | /* PLL is protected by panel, make sure we can write it */ |
Line 1612... | Line 1615... | ||
1612 | if (IS_MOBILE(dev_priv->dev)) |
1615 | if (IS_MOBILE(dev_priv->dev)) |
Line 1643... | Line 1646... | ||
1643 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
1646 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
1644 | u32 tmp; |
1647 | u32 tmp; |
Line 1645... | Line 1648... | ||
1645 | 1648 | ||
Line 1646... | Line -... | ||
1646 | assert_pipe_disabled(dev_priv, crtc->pipe); |
- | |
1647 | - | ||
1648 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); |
1649 | assert_pipe_disabled(dev_priv, crtc->pipe); |
Line 1649... | Line 1650... | ||
1649 | 1650 | ||
1650 | mutex_lock(&dev_priv->sb_lock); |
1651 | mutex_lock(&dev_priv->sb_lock); |
1651 | 1652 | ||
Line 1687... | Line 1688... | ||
1687 | 1688 | ||
1688 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
1689 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
1689 | { |
1690 | { |
1690 | struct drm_device *dev = crtc->base.dev; |
1691 | struct drm_device *dev = crtc->base.dev; |
1691 | struct drm_i915_private *dev_priv = dev->dev_private; |
1692 | struct drm_i915_private *dev_priv = dev->dev_private; |
1692 | int reg = DPLL(crtc->pipe); |
1693 | i915_reg_t reg = DPLL(crtc->pipe); |
Line 1693... | Line 1694... | ||
1693 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
1694 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
Line 1694... | Line 1695... | ||
1694 | 1695 | ||
Line 1836... | Line 1837... | ||
1836 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1837 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1837 | struct intel_digital_port *dport, |
1838 | struct intel_digital_port *dport, |
1838 | unsigned int expected_mask) |
1839 | unsigned int expected_mask) |
1839 | { |
1840 | { |
1840 | u32 port_mask; |
1841 | u32 port_mask; |
1841 | int dpll_reg; |
1842 | i915_reg_t dpll_reg; |
Line 1842... | Line 1843... | ||
1842 | 1843 | ||
1843 | switch (dport->port) { |
1844 | switch (dport->port) { |
1844 | case PORT_B: |
1845 | case PORT_B: |
1845 | port_mask = DPLL_PORTB_READY_MASK; |
1846 | port_mask = DPLL_PORTB_READY_MASK; |
Line 1961... | Line 1962... | ||
1961 | enum pipe pipe) |
1962 | enum pipe pipe) |
1962 | { |
1963 | { |
1963 | struct drm_device *dev = dev_priv->dev; |
1964 | struct drm_device *dev = dev_priv->dev; |
1964 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1965 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1965 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1966 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 1967 | i915_reg_t reg; |
|
1966 | uint32_t reg, val, pipeconf_val; |
1968 | uint32_t val, pipeconf_val; |
Line 1967... | Line 1969... | ||
1967 | 1969 | ||
1968 | /* PCH only available on ILK+ */ |
1970 | /* PCH only available on ILK+ */ |
Line 1969... | Line 1971... | ||
1969 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
1971 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
Line 2050... | Line 2052... | ||
2050 | 2052 | ||
2051 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2053 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2052 | enum pipe pipe) |
2054 | enum pipe pipe) |
2053 | { |
2055 | { |
- | 2056 | struct drm_device *dev = dev_priv->dev; |
|
2054 | struct drm_device *dev = dev_priv->dev; |
2057 | i915_reg_t reg; |
Line 2055... | Line 2058... | ||
2055 | uint32_t reg, val; |
2058 | uint32_t val; |
2056 | 2059 | ||
2057 | /* FDI relies on the transcoder */ |
2060 | /* FDI relies on the transcoder */ |
Line 2067... | Line 2070... | ||
2067 | I915_WRITE(reg, val); |
2070 | I915_WRITE(reg, val); |
2068 | /* wait for PCH transcoder off, transcoder state */ |
2071 | /* wait for PCH transcoder off, transcoder state */ |
2069 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
2072 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
2070 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
2073 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
Line 2071... | Line 2074... | ||
2071 | 2074 | ||
2072 | if (!HAS_PCH_IBX(dev)) { |
2075 | if (HAS_PCH_CPT(dev)) { |
2073 | /* Workaround: Clear the timing override chicken bit again. */ |
2076 | /* Workaround: Clear the timing override chicken bit again. */ |
2074 | reg = TRANS_CHICKEN2(pipe); |
2077 | reg = TRANS_CHICKEN2(pipe); |
2075 | val = I915_READ(reg); |
2078 | val = I915_READ(reg); |
2076 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
2079 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
Line 2105... | Line 2108... | ||
2105 | static void intel_enable_pipe(struct intel_crtc *crtc) |
2108 | static void intel_enable_pipe(struct intel_crtc *crtc) |
2106 | { |
2109 | { |
2107 | struct drm_device *dev = crtc->base.dev; |
2110 | struct drm_device *dev = crtc->base.dev; |
2108 | struct drm_i915_private *dev_priv = dev->dev_private; |
2111 | struct drm_i915_private *dev_priv = dev->dev_private; |
2109 | enum pipe pipe = crtc->pipe; |
2112 | enum pipe pipe = crtc->pipe; |
2110 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2113 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
2111 | pipe); |
- | |
2112 | enum pipe pch_transcoder; |
2114 | enum pipe pch_transcoder; |
2113 | int reg; |
2115 | i915_reg_t reg; |
2114 | u32 val; |
2116 | u32 val; |
Line 2115... | Line 2117... | ||
2115 | 2117 | ||
Line 2116... | Line 2118... | ||
2116 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2118 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
Line 2128... | Line 2130... | ||
2128 | * A pipe without a PLL won't actually be able to drive bits from |
2130 | * A pipe without a PLL won't actually be able to drive bits from |
2129 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
2131 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
2130 | * need the check. |
2132 | * need the check. |
2131 | */ |
2133 | */ |
2132 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
2134 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
2133 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
2135 | if (crtc->config->has_dsi_encoder) |
2134 | assert_dsi_pll_enabled(dev_priv); |
2136 | assert_dsi_pll_enabled(dev_priv); |
2135 | else |
2137 | else |
2136 | assert_pll_enabled(dev_priv, pipe); |
2138 | assert_pll_enabled(dev_priv, pipe); |
2137 | else { |
2139 | else { |
2138 | if (crtc->config->has_pch_encoder) { |
2140 | if (crtc->config->has_pch_encoder) { |
Line 2169... | Line 2171... | ||
2169 | static void intel_disable_pipe(struct intel_crtc *crtc) |
2171 | static void intel_disable_pipe(struct intel_crtc *crtc) |
2170 | { |
2172 | { |
2171 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
2173 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
2172 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
2174 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
2173 | enum pipe pipe = crtc->pipe; |
2175 | enum pipe pipe = crtc->pipe; |
2174 | int reg; |
2176 | i915_reg_t reg; |
2175 | u32 val; |
2177 | u32 val; |
Line 2176... | Line 2178... | ||
2176 | 2178 | ||
Line 2177... | Line 2179... | ||
2177 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2179 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
Line 2268... | Line 2270... | ||
2268 | { |
2270 | { |
2269 | return ALIGN(height, intel_tile_height(dev, pixel_format, |
2271 | return ALIGN(height, intel_tile_height(dev, pixel_format, |
2270 | fb_format_modifier, 0)); |
2272 | fb_format_modifier, 0)); |
2271 | } |
2273 | } |
Line 2272... | Line 2274... | ||
2272 | 2274 | ||
2273 | static int |
2275 | static void |
2274 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2276 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2275 | const struct drm_plane_state *plane_state) |
2277 | const struct drm_plane_state *plane_state) |
2276 | { |
2278 | { |
2277 | struct intel_rotation_info *info = &view->rotation_info; |
2279 | struct intel_rotation_info *info = &view->params.rotation_info; |
Line 2278... | Line 2280... | ||
2278 | unsigned int tile_height, tile_pitch; |
2280 | unsigned int tile_height, tile_pitch; |
Line 2279... | Line 2281... | ||
2279 | 2281 | ||
2280 | *view = i915_ggtt_view_normal; |
2282 | *view = i915_ggtt_view_normal; |
Line 2281... | Line 2283... | ||
2281 | 2283 | ||
2282 | if (!plane_state) |
2284 | if (!plane_state) |
Line 2283... | Line 2285... | ||
2283 | return 0; |
2285 | return; |
Line 2284... | Line 2286... | ||
2284 | 2286 | ||
2285 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
2287 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
Line 2308... | Line 2310... | ||
2308 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, |
2310 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, |
2309 | tile_height); |
2311 | tile_height); |
2310 | info->size_uv = info->width_pages_uv * info->height_pages_uv * |
2312 | info->size_uv = info->width_pages_uv * info->height_pages_uv * |
2311 | PAGE_SIZE; |
2313 | PAGE_SIZE; |
2312 | } |
2314 | } |
2313 | - | ||
2314 | return 0; |
- | |
2315 | } |
2315 | } |
Line 2316... | Line 2316... | ||
2316 | 2316 | ||
2317 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2317 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2318 | { |
2318 | { |
2319 | if (INTEL_INFO(dev_priv)->gen >= 9) |
2319 | if (INTEL_INFO(dev_priv)->gen >= 9) |
2320 | return 256 * 1024; |
2320 | return 256 * 1024; |
2321 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
2321 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
2322 | IS_VALLEYVIEW(dev_priv)) |
2322 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
2323 | return 128 * 1024; |
2323 | return 128 * 1024; |
2324 | else if (INTEL_INFO(dev_priv)->gen >= 4) |
2324 | else if (INTEL_INFO(dev_priv)->gen >= 4) |
2325 | return 4 * 1024; |
2325 | return 4 * 1024; |
2326 | else |
2326 | else |
2327 | return 0; |
2327 | return 0; |
Line 2328... | Line 2328... | ||
2328 | } |
2328 | } |
2329 | 2329 | ||
2330 | int |
2330 | int |
2331 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2331 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2332 | struct drm_framebuffer *fb, |
- | |
2333 | const struct drm_plane_state *plane_state, |
- | |
2334 | struct intel_engine_cs *pipelined, |
2332 | struct drm_framebuffer *fb, |
2335 | struct drm_i915_gem_request **pipelined_request) |
2333 | const struct drm_plane_state *plane_state) |
2336 | { |
2334 | { |
2337 | struct drm_device *dev = fb->dev; |
2335 | struct drm_device *dev = fb->dev; |
2338 | struct drm_i915_private *dev_priv = dev->dev_private; |
2336 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 2365... | Line 2363... | ||
2365 | default: |
2363 | default: |
2366 | MISSING_CASE(fb->modifier[0]); |
2364 | MISSING_CASE(fb->modifier[0]); |
2367 | return -EINVAL; |
2365 | return -EINVAL; |
2368 | } |
2366 | } |
Line 2369... | Line 2367... | ||
2369 | 2367 | ||
2370 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
- | |
2371 | if (ret) |
- | |
Line 2372... | Line 2368... | ||
2372 | return ret; |
2368 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2373 | 2369 | ||
2374 | /* Note that the w/a also requires 64 PTE of padding following the |
2370 | /* Note that the w/a also requires 64 PTE of padding following the |
2375 | * bo. We currently fill all unused PTE with the shadow page and so |
2371 | * bo. We currently fill all unused PTE with the shadow page and so |
Line 2386... | Line 2382... | ||
2386 | * intel_runtime_pm_put(), so it is correct to wrap only the |
2382 | * intel_runtime_pm_put(), so it is correct to wrap only the |
2387 | * pin/unpin/fence and not more. |
2383 | * pin/unpin/fence and not more. |
2388 | */ |
2384 | */ |
2389 | intel_runtime_pm_get(dev_priv); |
2385 | intel_runtime_pm_get(dev_priv); |
Line 2390... | Line -... | ||
2390 | - | ||
2391 | dev_priv->mm.interruptible = false; |
2386 | |
2392 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
2387 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2393 | pipelined_request, &view); |
2388 | &view); |
2394 | if (ret) |
2389 | if (ret) |
Line 2395... | Line 2390... | ||
2395 | goto err_interruptible; |
2390 | goto err_pm; |
2396 | 2391 | ||
2397 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2392 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2398 | * fence, whereas 965+ only requires a fence if using |
2393 | * fence, whereas 965+ only requires a fence if using |
Line 2416... | Line 2411... | ||
2416 | goto err_unpin; |
2411 | goto err_unpin; |
Line 2417... | Line 2412... | ||
2417 | 2412 | ||
2418 | i915_gem_object_pin_fence(obj); |
2413 | i915_gem_object_pin_fence(obj); |
Line 2419... | Line -... | ||
2419 | } |
- | |
2420 | 2414 | } |
|
2421 | dev_priv->mm.interruptible = true; |
2415 | |
Line 2422... | Line 2416... | ||
2422 | intel_runtime_pm_put(dev_priv); |
2416 | intel_runtime_pm_put(dev_priv); |
2423 | return 0; |
2417 | return 0; |
2424 | 2418 | ||
2425 | err_unpin: |
- | |
2426 | i915_gem_object_unpin_from_display_plane(obj, &view); |
2419 | err_unpin: |
2427 | err_interruptible: |
2420 | i915_gem_object_unpin_from_display_plane(obj, &view); |
2428 | dev_priv->mm.interruptible = true; |
2421 | err_pm: |
Line 2429... | Line 2422... | ||
2429 | intel_runtime_pm_put(dev_priv); |
2422 | intel_runtime_pm_put(dev_priv); |
2430 | return ret; |
2423 | return ret; |
2431 | } |
2424 | } |
2432 | 2425 | ||
2433 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2426 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2434 | const struct drm_plane_state *plane_state) |
- | |
Line 2435... | Line 2427... | ||
2435 | { |
2427 | const struct drm_plane_state *plane_state) |
Line 2436... | Line 2428... | ||
2436 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2428 | { |
2437 | struct i915_ggtt_view view; |
- | |
Line 2438... | Line 2429... | ||
2438 | int ret; |
2429 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2439 | 2430 | struct i915_ggtt_view view; |
|
Line 2440... | Line 2431... | ||
2440 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2431 | |
Line 2693... | Line 2684... | ||
2693 | bool visible = to_intel_plane_state(primary->state)->visible; |
2684 | bool visible = to_intel_plane_state(primary->state)->visible; |
2694 | struct drm_i915_gem_object *obj; |
2685 | struct drm_i915_gem_object *obj; |
2695 | int plane = intel_crtc->plane; |
2686 | int plane = intel_crtc->plane; |
2696 | unsigned long linear_offset; |
2687 | unsigned long linear_offset; |
2697 | u32 dspcntr; |
2688 | u32 dspcntr; |
2698 | u32 reg = DSPCNTR(plane); |
2689 | i915_reg_t reg = DSPCNTR(plane); |
2699 | int pixel_size; |
2690 | int pixel_size; |
Line 2700... | Line 2691... | ||
2700 | 2691 | ||
2701 | if (!visible || !fb) { |
2692 | if (!visible || !fb) { |
2702 | I915_WRITE(reg, 0); |
2693 | I915_WRITE(reg, 0); |
Line 2823... | Line 2814... | ||
2823 | bool visible = to_intel_plane_state(primary->state)->visible; |
2814 | bool visible = to_intel_plane_state(primary->state)->visible; |
2824 | struct drm_i915_gem_object *obj; |
2815 | struct drm_i915_gem_object *obj; |
2825 | int plane = intel_crtc->plane; |
2816 | int plane = intel_crtc->plane; |
2826 | unsigned long linear_offset; |
2817 | unsigned long linear_offset; |
2827 | u32 dspcntr; |
2818 | u32 dspcntr; |
2828 | u32 reg = DSPCNTR(plane); |
2819 | i915_reg_t reg = DSPCNTR(plane); |
2829 | int pixel_size; |
2820 | int pixel_size; |
Line 2830... | Line 2821... | ||
2830 | 2821 | ||
2831 | if (!visible || !fb) { |
2822 | if (!visible || !fb) { |
2832 | I915_WRITE(reg, 0); |
2823 | I915_WRITE(reg, 0); |
Line 2952... | Line 2943... | ||
2952 | 2943 | ||
2953 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2944 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2954 | struct drm_i915_gem_object *obj, |
2945 | struct drm_i915_gem_object *obj, |
2955 | unsigned int plane) |
2946 | unsigned int plane) |
2956 | { |
2947 | { |
2957 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
2948 | struct i915_ggtt_view view; |
2958 | struct i915_vma *vma; |
2949 | struct i915_vma *vma; |
Line 2959... | Line 2950... | ||
2959 | u64 offset; |
2950 | u64 offset; |
2960 | 2951 | ||
Line 2961... | Line 2952... | ||
2961 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) |
2952 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
2962 | view = &i915_ggtt_view_rotated; |
2953 | intel_plane->base.state); |
2963 | 2954 | ||
2964 | vma = i915_gem_obj_to_ggtt_view(obj, view); |
2955 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
Line 2965... | Line 2956... | ||
2965 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
2956 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
Line 2966... | Line 2957... | ||
2966 | view->type)) |
2957 | view.type)) |
2967 | return -1; |
2958 | return -1; |
2968 | 2959 | ||
2969 | offset = vma->node.start; |
2960 | offset = vma->node.start; |
Line 2970... | Line 2961... | ||
2970 | 2961 | ||
Line 3197... | Line 3188... | ||
3197 | int x, int y, enum mode_set_atomic state) |
3188 | int x, int y, enum mode_set_atomic state) |
3198 | { |
3189 | { |
3199 | struct drm_device *dev = crtc->dev; |
3190 | struct drm_device *dev = crtc->dev; |
3200 | struct drm_i915_private *dev_priv = dev->dev_private; |
3191 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 3201... | Line 3192... | ||
3201 | 3192 | ||
3202 | if (dev_priv->fbc.disable_fbc) |
3193 | if (dev_priv->fbc.deactivate) |
Line 3203... | Line 3194... | ||
3203 | dev_priv->fbc.disable_fbc(dev_priv); |
3194 | dev_priv->fbc.deactivate(dev_priv); |
Line 3204... | Line 3195... | ||
3204 | 3195 | ||
3205 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3196 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
Line 3227... | Line 3218... | ||
3227 | for_each_crtc(dev, crtc) { |
3218 | for_each_crtc(dev, crtc) { |
3228 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3219 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3229 | struct intel_plane_state *plane_state; |
3220 | struct intel_plane_state *plane_state; |
Line 3230... | Line 3221... | ||
3230 | 3221 | ||
3231 | drm_modeset_lock_crtc(crtc, &plane->base); |
- | |
3232 | 3222 | drm_modeset_lock_crtc(crtc, &plane->base); |
|
Line 3233... | Line 3223... | ||
3233 | plane_state = to_intel_plane_state(plane->base.state); |
3223 | plane_state = to_intel_plane_state(plane->base.state); |
3234 | 3224 | ||
Line 3235... | Line 3225... | ||
3235 | if (plane_state->base.fb) |
3225 | if (crtc->state->active && plane_state->base.fb) |
3236 | plane->commit_plane(&plane->base, plane_state); |
3226 | plane->commit_plane(&plane->base, plane_state); |
3237 | 3227 | ||
Line 3306... | Line 3296... | ||
3306 | intel_hpd_init(dev_priv); |
3296 | intel_hpd_init(dev_priv); |
Line 3307... | Line 3297... | ||
3307 | 3297 | ||
3308 | drm_modeset_unlock_all(dev); |
3298 | drm_modeset_unlock_all(dev); |
Line 3309... | Line -... | ||
3309 | } |
- | |
3310 | - | ||
3311 | static void |
- | |
3312 | intel_finish_fb(struct drm_framebuffer *old_fb) |
- | |
3313 | { |
- | |
3314 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
- | |
3315 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
- | |
3316 | bool was_interruptible = dev_priv->mm.interruptible; |
- | |
3317 | int ret; |
- | |
3318 | - | ||
3319 | /* Big Hammer, we also need to ensure that any pending |
- | |
3320 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
- | |
3321 | * current scanout is retired before unpinning the old |
- | |
3322 | * framebuffer. Note that we rely on userspace rendering |
- | |
3323 | * into the buffer attached to the pipe they are waiting |
- | |
3324 | * on. If not, userspace generates a GPU hang with IPEHR |
- | |
3325 | * point to the MI_WAIT_FOR_EVENT. |
- | |
3326 | * |
- | |
3327 | * This should only fail upon a hung GPU, in which case we |
- | |
3328 | * can safely continue. |
- | |
3329 | */ |
- | |
3330 | dev_priv->mm.interruptible = false; |
- | |
3331 | ret = i915_gem_object_wait_rendering(obj, true); |
- | |
3332 | dev_priv->mm.interruptible = was_interruptible; |
- | |
3333 | - | ||
3334 | WARN_ON(ret); |
- | |
3335 | } |
3299 | } |
3336 | 3300 | ||
3337 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3301 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3338 | { |
3302 | { |
3339 | struct drm_device *dev = crtc->dev; |
3303 | struct drm_device *dev = crtc->dev; |
Line 3401... | Line 3365... | ||
3401 | { |
3365 | { |
3402 | struct drm_device *dev = crtc->dev; |
3366 | struct drm_device *dev = crtc->dev; |
3403 | struct drm_i915_private *dev_priv = dev->dev_private; |
3367 | struct drm_i915_private *dev_priv = dev->dev_private; |
3404 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3368 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3405 | int pipe = intel_crtc->pipe; |
3369 | int pipe = intel_crtc->pipe; |
- | 3370 | i915_reg_t reg; |
|
3406 | u32 reg, temp; |
3371 | u32 temp; |
Line 3407... | Line 3372... | ||
3407 | 3372 | ||
3408 | /* enable normal train */ |
3373 | /* enable normal train */ |
3409 | reg = FDI_TX_CTL(pipe); |
3374 | reg = FDI_TX_CTL(pipe); |
3410 | temp = I915_READ(reg); |
3375 | temp = I915_READ(reg); |
Line 3443... | Line 3408... | ||
3443 | { |
3408 | { |
3444 | struct drm_device *dev = crtc->dev; |
3409 | struct drm_device *dev = crtc->dev; |
3445 | struct drm_i915_private *dev_priv = dev->dev_private; |
3410 | struct drm_i915_private *dev_priv = dev->dev_private; |
3446 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3411 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3447 | int pipe = intel_crtc->pipe; |
3412 | int pipe = intel_crtc->pipe; |
- | 3413 | i915_reg_t reg; |
|
3448 | u32 reg, temp, tries; |
3414 | u32 temp, tries; |
Line 3449... | Line 3415... | ||
3449 | 3415 | ||
3450 | /* FDI needs bits from pipe first */ |
3416 | /* FDI needs bits from pipe first */ |
Line 3451... | Line 3417... | ||
3451 | assert_pipe_enabled(dev_priv, pipe); |
3417 | assert_pipe_enabled(dev_priv, pipe); |
Line 3543... | Line 3509... | ||
3543 | { |
3509 | { |
3544 | struct drm_device *dev = crtc->dev; |
3510 | struct drm_device *dev = crtc->dev; |
3545 | struct drm_i915_private *dev_priv = dev->dev_private; |
3511 | struct drm_i915_private *dev_priv = dev->dev_private; |
3546 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3512 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3547 | int pipe = intel_crtc->pipe; |
3513 | int pipe = intel_crtc->pipe; |
- | 3514 | i915_reg_t reg; |
|
3548 | u32 reg, temp, i, retry; |
3515 | u32 temp, i, retry; |
Line 3549... | Line 3516... | ||
3549 | 3516 | ||
3550 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3517 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3551 | for train result */ |
3518 | for train result */ |
3552 | reg = FDI_RX_IMR(pipe); |
3519 | reg = FDI_RX_IMR(pipe); |
Line 3675... | Line 3642... | ||
3675 | { |
3642 | { |
3676 | struct drm_device *dev = crtc->dev; |
3643 | struct drm_device *dev = crtc->dev; |
3677 | struct drm_i915_private *dev_priv = dev->dev_private; |
3644 | struct drm_i915_private *dev_priv = dev->dev_private; |
3678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3645 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3679 | int pipe = intel_crtc->pipe; |
3646 | int pipe = intel_crtc->pipe; |
- | 3647 | i915_reg_t reg; |
|
3680 | u32 reg, temp, i, j; |
3648 | u32 temp, i, j; |
Line 3681... | Line 3649... | ||
3681 | 3649 | ||
3682 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3650 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3683 | for train result */ |
3651 | for train result */ |
3684 | reg = FDI_RX_IMR(pipe); |
3652 | reg = FDI_RX_IMR(pipe); |
Line 3792... | Line 3760... | ||
3792 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
3760 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
3793 | { |
3761 | { |
3794 | struct drm_device *dev = intel_crtc->base.dev; |
3762 | struct drm_device *dev = intel_crtc->base.dev; |
3795 | struct drm_i915_private *dev_priv = dev->dev_private; |
3763 | struct drm_i915_private *dev_priv = dev->dev_private; |
3796 | int pipe = intel_crtc->pipe; |
3764 | int pipe = intel_crtc->pipe; |
- | 3765 | i915_reg_t reg; |
|
3797 | u32 reg, temp; |
3766 | u32 temp; |
3798 | - | ||
Line 3799... | Line 3767... | ||
3799 | 3767 | ||
3800 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
3768 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
3801 | reg = FDI_RX_CTL(pipe); |
3769 | reg = FDI_RX_CTL(pipe); |
3802 | temp = I915_READ(reg); |
3770 | temp = I915_READ(reg); |
Line 3829... | Line 3797... | ||
3829 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3797 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3830 | { |
3798 | { |
3831 | struct drm_device *dev = intel_crtc->base.dev; |
3799 | struct drm_device *dev = intel_crtc->base.dev; |
3832 | struct drm_i915_private *dev_priv = dev->dev_private; |
3800 | struct drm_i915_private *dev_priv = dev->dev_private; |
3833 | int pipe = intel_crtc->pipe; |
3801 | int pipe = intel_crtc->pipe; |
- | 3802 | i915_reg_t reg; |
|
3834 | u32 reg, temp; |
3803 | u32 temp; |
Line 3835... | Line 3804... | ||
3835 | 3804 | ||
3836 | /* Switch from PCDclk to Rawclk */ |
3805 | /* Switch from PCDclk to Rawclk */ |
3837 | reg = FDI_RX_CTL(pipe); |
3806 | reg = FDI_RX_CTL(pipe); |
3838 | temp = I915_READ(reg); |
3807 | temp = I915_READ(reg); |
Line 3859... | Line 3828... | ||
3859 | { |
3828 | { |
3860 | struct drm_device *dev = crtc->dev; |
3829 | struct drm_device *dev = crtc->dev; |
3861 | struct drm_i915_private *dev_priv = dev->dev_private; |
3830 | struct drm_i915_private *dev_priv = dev->dev_private; |
3862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3831 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3863 | int pipe = intel_crtc->pipe; |
3832 | int pipe = intel_crtc->pipe; |
- | 3833 | i915_reg_t reg; |
|
3864 | u32 reg, temp; |
3834 | u32 temp; |
Line 3865... | Line 3835... | ||
3865 | 3835 | ||
3866 | /* disable CPU FDI tx and PCH FDI rx */ |
3836 | /* disable CPU FDI tx and PCH FDI rx */ |
3867 | reg = FDI_TX_CTL(pipe); |
3837 | reg = FDI_TX_CTL(pipe); |
3868 | temp = I915_READ(reg); |
3838 | temp = I915_READ(reg); |
Line 3946... | Line 3916... | ||
3946 | work->event); |
3916 | work->event); |
Line 3947... | Line 3917... | ||
3947 | 3917 | ||
Line 3948... | Line 3918... | ||
3948 | drm_crtc_vblank_put(&intel_crtc->base); |
3918 | drm_crtc_vblank_put(&intel_crtc->base); |
- | 3919 | ||
- | 3920 | wake_up_all(&dev_priv->pending_flip_queue); |
|
3949 | 3921 | queue_work(dev_priv->wq, &work->work); |
|
3950 | wake_up_all(&dev_priv->pending_flip_queue); |
3922 | |
3951 | trace_i915_flip_complete(intel_crtc->plane, |
- | |
3952 | work->pending_flip_obj); |
- | |
3953 | 3923 | trace_i915_flip_complete(intel_crtc->plane, |
|
Line 3954... | Line 3924... | ||
3954 | queue_work(dev_priv->wq, &work->work); |
3924 | work->pending_flip_obj); |
3955 | } |
3925 | } |
3956 | 3926 | ||
3957 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3927 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
- | 3928 | { |
|
Line 3958... | Line 3929... | ||
3958 | { |
3929 | struct drm_device *dev = crtc->dev; |
- | 3930 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3931 | long ret; |
|
3959 | struct drm_device *dev = crtc->dev; |
3932 | |
3960 | struct drm_i915_private *dev_priv = dev->dev_private; |
3933 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
- | 3934 | ||
- | 3935 | ret = wait_event_interruptible_timeout( |
|
- | 3936 | dev_priv->pending_flip_queue, |
|
- | 3937 | !intel_crtc_has_pending_flip(crtc), |
|
- | 3938 | 60*HZ); |
|
3961 | 3939 | ||
3962 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3940 | if (ret < 0) |
Line 3963... | Line 3941... | ||
3963 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3941 | return ret; |
3964 | !intel_crtc_has_pending_flip(crtc), |
3942 | |
3965 | 60*HZ) == 0)) { |
3943 | if (ret == 0) { |
3966 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3944 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3967 | 3945 | ||
3968 | spin_lock_irq(&dev->event_lock); |
3946 | spin_lock_irq(&dev->event_lock); |
3969 | if (intel_crtc->unpin_work) { |
3947 | if (intel_crtc->unpin_work) { |
Line 3970... | Line 3948... | ||
3970 | WARN_ONCE(1, "Removing stuck page flip\n"); |
3948 | WARN_ONCE(1, "Removing stuck page flip\n"); |
3971 | page_flip_completed(intel_crtc); |
- | |
3972 | } |
- | |
3973 | spin_unlock_irq(&dev->event_lock); |
- | |
3974 | } |
3949 | page_flip_completed(intel_crtc); |
- | 3950 | } |
|
- | 3951 | spin_unlock_irq(&dev->event_lock); |
|
- | 3952 | } |
|
- | 3953 | ||
- | 3954 | return 0; |
|
- | 3955 | } |
|
- | 3956 | ||
- | 3957 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
|
- | 3958 | { |
|
- | 3959 | u32 temp; |
|
- | 3960 | ||
- | 3961 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
|
- | 3962 | ||
- | 3963 | mutex_lock(&dev_priv->sb_lock); |
|
3975 | 3964 | ||
Line 3976... | Line 3965... | ||
3976 | if (crtc->primary->fb) { |
3965 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
3977 | mutex_lock(&dev->struct_mutex); |
3966 | temp |= SBI_SSCCTL_DISABLE; |
3978 | intel_finish_fb(crtc->primary->fb); |
3967 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
Line 3987... | Line 3976... | ||
3987 | struct drm_i915_private *dev_priv = dev->dev_private; |
3976 | struct drm_i915_private *dev_priv = dev->dev_private; |
3988 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
3977 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
3989 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3978 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3990 | u32 temp; |
3979 | u32 temp; |
Line 3991... | Line 3980... | ||
3991 | 3980 | ||
3992 | mutex_lock(&dev_priv->sb_lock); |
- | |
3993 | - | ||
3994 | /* It is necessary to ungate the pixclk gate prior to programming |
- | |
3995 | * the divisors, and gate it back when it is done. |
- | |
3996 | */ |
- | |
3997 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
- | |
3998 | - | ||
3999 | /* Disable SSCCTL */ |
- | |
4000 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
- | |
4001 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
- | |
4002 | SBI_SSCCTL_DISABLE, |
- | |
Line 4003... | Line 3981... | ||
4003 | SBI_ICLK); |
3981 | lpt_disable_iclkip(dev_priv); |
4004 | 3982 | ||
4005 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
3983 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
4006 | if (clock == 20000) { |
3984 | if (clock == 20000) { |
Line 4016... | Line 3994... | ||
4016 | */ |
3994 | */ |
4017 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3995 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4018 | u32 iclk_pi_range = 64; |
3996 | u32 iclk_pi_range = 64; |
4019 | u32 desired_divisor, msb_divisor_value, pi_value; |
3997 | u32 desired_divisor, msb_divisor_value, pi_value; |
Line 4020... | Line 3998... | ||
4020 | 3998 | ||
4021 | desired_divisor = (iclk_virtual_root_freq / clock); |
3999 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
4022 | msb_divisor_value = desired_divisor / iclk_pi_range; |
4000 | msb_divisor_value = desired_divisor / iclk_pi_range; |
Line 4023... | Line 4001... | ||
4023 | pi_value = desired_divisor % iclk_pi_range; |
4001 | pi_value = desired_divisor % iclk_pi_range; |
4024 | 4002 | ||
Line 4038... | Line 4016... | ||
4038 | auxdiv, |
4016 | auxdiv, |
4039 | divsel, |
4017 | divsel, |
4040 | phasedir, |
4018 | phasedir, |
4041 | phaseinc); |
4019 | phaseinc); |
Line -... | Line 4020... | ||
- | 4020 | ||
- | 4021 | mutex_lock(&dev_priv->sb_lock); |
|
4042 | 4022 | ||
4043 | /* Program SSCDIVINTPHASE6 */ |
4023 | /* Program SSCDIVINTPHASE6 */ |
4044 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
4024 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
4045 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4025 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4046 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
4026 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
Line 4059... | Line 4039... | ||
4059 | /* Enable modulator and associated divider */ |
4039 | /* Enable modulator and associated divider */ |
4060 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
4040 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
4061 | temp &= ~SBI_SSCCTL_DISABLE; |
4041 | temp &= ~SBI_SSCCTL_DISABLE; |
4062 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
4042 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
Line -... | Line 4043... | ||
- | 4043 | ||
- | 4044 | mutex_unlock(&dev_priv->sb_lock); |
|
4063 | 4045 | ||
4064 | /* Wait for initialization time */ |
4046 | /* Wait for initialization time */ |
Line 4065... | Line 4047... | ||
4065 | udelay(24); |
4047 | udelay(24); |
4066 | - | ||
4067 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
- | |
4068 | 4048 | ||
Line 4069... | Line 4049... | ||
4069 | mutex_unlock(&dev_priv->sb_lock); |
4049 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
4070 | } |
4050 | } |
4071 | 4051 | ||
Line 4135... | Line 4115... | ||
4135 | default: |
4115 | default: |
4136 | BUG(); |
4116 | BUG(); |
4137 | } |
4117 | } |
4138 | } |
4118 | } |
Line -... | Line 4119... | ||
- | 4119 | ||
- | 4120 | /* Return which DP Port should be selected for Transcoder DP control */ |
|
- | 4121 | static enum port |
|
- | 4122 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
|
- | 4123 | { |
|
- | 4124 | struct drm_device *dev = crtc->dev; |
|
- | 4125 | struct intel_encoder *encoder; |
|
- | 4126 | ||
- | 4127 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
|
- | 4128 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
|
- | 4129 | encoder->type == INTEL_OUTPUT_EDP) |
|
- | 4130 | return enc_to_dig_port(&encoder->base)->port; |
|
- | 4131 | } |
|
- | 4132 | ||
- | 4133 | return -1; |
|
- | 4134 | } |
|
4139 | 4135 | ||
4140 | /* |
4136 | /* |
4141 | * Enable PCH resources required for PCH ports: |
4137 | * Enable PCH resources required for PCH ports: |
4142 | * - PCH PLLs |
4138 | * - PCH PLLs |
4143 | * - FDI training & RX/TX |
4139 | * - FDI training & RX/TX |
Line 4149... | Line 4145... | ||
4149 | { |
4145 | { |
4150 | struct drm_device *dev = crtc->dev; |
4146 | struct drm_device *dev = crtc->dev; |
4151 | struct drm_i915_private *dev_priv = dev->dev_private; |
4147 | struct drm_i915_private *dev_priv = dev->dev_private; |
4152 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4153 | int pipe = intel_crtc->pipe; |
4149 | int pipe = intel_crtc->pipe; |
4154 | u32 reg, temp; |
4150 | u32 temp; |
Line 4155... | Line 4151... | ||
4155 | 4151 | ||
Line 4156... | Line 4152... | ||
4156 | assert_pch_transcoder_disabled(dev_priv, pipe); |
4152 | assert_pch_transcoder_disabled(dev_priv, pipe); |
4157 | 4153 | ||
Line 4161... | Line 4157... | ||
4161 | /* Write the TU size bits before fdi link training, so that error |
4157 | /* Write the TU size bits before fdi link training, so that error |
4162 | * detection works. */ |
4158 | * detection works. */ |
4163 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
4159 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
4164 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
4160 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
Line -... | Line 4161... | ||
- | 4161 | ||
- | 4162 | /* |
|
- | 4163 | * Sometimes spurious CPU pipe underruns happen during FDI |
|
- | 4164 | * training, at least with VGA+HDMI cloning. Suppress them. |
|
- | 4165 | */ |
|
- | 4166 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
|
4165 | 4167 | ||
4166 | /* For PCH output, training FDI link */ |
4168 | /* For PCH output, training FDI link */ |
Line 4167... | Line 4169... | ||
4167 | dev_priv->display.fdi_link_train(crtc); |
4169 | dev_priv->display.fdi_link_train(crtc); |
4168 | 4170 | ||
Line 4194... | Line 4196... | ||
4194 | assert_panel_unlocked(dev_priv, pipe); |
4196 | assert_panel_unlocked(dev_priv, pipe); |
4195 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
4197 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
Line 4196... | Line 4198... | ||
4196 | 4198 | ||
Line -... | Line 4199... | ||
- | 4199 | intel_fdi_normal_train(crtc); |
|
- | 4200 | ||
4197 | intel_fdi_normal_train(crtc); |
4201 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4198 | 4202 | ||
- | 4203 | /* For PCH DP, enable TRANS_DP_CTL */ |
|
- | 4204 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
|
4199 | /* For PCH DP, enable TRANS_DP_CTL */ |
4205 | const struct drm_display_mode *adjusted_mode = |
4200 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
4206 | &intel_crtc->config->base.adjusted_mode; |
4201 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
4207 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
4202 | reg = TRANS_DP_CTL(pipe); |
4208 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
4203 | temp = I915_READ(reg); |
4209 | temp = I915_READ(reg); |
4204 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
4210 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
4205 | TRANS_DP_SYNC_MASK | |
4211 | TRANS_DP_SYNC_MASK | |
4206 | TRANS_DP_BPC_MASK); |
4212 | TRANS_DP_BPC_MASK); |
Line 4207... | Line 4213... | ||
4207 | temp |= TRANS_DP_OUTPUT_ENABLE; |
4213 | temp |= TRANS_DP_OUTPUT_ENABLE; |
4208 | temp |= bpc << 9; /* same format but at 11:9 */ |
4214 | temp |= bpc << 9; /* same format but at 11:9 */ |
4209 | 4215 | ||
4210 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
4216 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
Line 4211... | Line 4217... | ||
4211 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
4217 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
4212 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
4218 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
4213 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
4219 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
4214 | 4220 | ||
4215 | switch (intel_trans_dp_port_sel(crtc)) { |
4221 | switch (intel_trans_dp_port_sel(crtc)) { |
4216 | case PCH_DP_B: |
4222 | case PORT_B: |
4217 | temp |= TRANS_DP_PORT_SEL_B; |
4223 | temp |= TRANS_DP_PORT_SEL_B; |
4218 | break; |
4224 | break; |
4219 | case PCH_DP_C: |
4225 | case PORT_C: |
4220 | temp |= TRANS_DP_PORT_SEL_C; |
4226 | temp |= TRANS_DP_PORT_SEL_C; |
4221 | break; |
4227 | break; |
4222 | case PCH_DP_D: |
4228 | case PORT_D: |
4223 | temp |= TRANS_DP_PORT_SEL_D; |
4229 | temp |= TRANS_DP_PORT_SEL_D; |
Line 4357... | Line 4363... | ||
4357 | } |
4363 | } |
Line 4358... | Line 4364... | ||
4358 | 4364 | ||
4359 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
4365 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
4360 | { |
4366 | { |
4361 | struct drm_i915_private *dev_priv = dev->dev_private; |
4367 | struct drm_i915_private *dev_priv = dev->dev_private; |
4362 | int dslreg = PIPEDSL(pipe); |
4368 | i915_reg_t dslreg = PIPEDSL(pipe); |
Line 4363... | Line 4369... | ||
4363 | u32 temp; |
4369 | u32 temp; |
4364 | 4370 | ||
4365 | temp = I915_READ(dslreg); |
4371 | temp = I915_READ(dslreg); |
Line 4650... | Line 4656... | ||
4650 | /* The clocks have to be on to load the palette. */ |
4656 | /* The clocks have to be on to load the palette. */ |
4651 | if (!crtc->state->active) |
4657 | if (!crtc->state->active) |
4652 | return; |
4658 | return; |
Line 4653... | Line 4659... | ||
4653 | 4659 | ||
4654 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
4660 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
4655 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
4661 | if (intel_crtc->config->has_dsi_encoder) |
4656 | assert_dsi_pll_enabled(dev_priv); |
4662 | assert_dsi_pll_enabled(dev_priv); |
4657 | else |
4663 | else |
4658 | assert_pll_enabled(dev_priv, pipe); |
4664 | assert_pll_enabled(dev_priv, pipe); |
Line 4667... | Line 4673... | ||
4667 | hsw_disable_ips(intel_crtc); |
4673 | hsw_disable_ips(intel_crtc); |
4668 | reenable_ips = true; |
4674 | reenable_ips = true; |
4669 | } |
4675 | } |
Line 4670... | Line 4676... | ||
4670 | 4676 | ||
4671 | for (i = 0; i < 256; i++) { |
4677 | for (i = 0; i < 256; i++) { |
Line 4672... | Line 4678... | ||
4672 | u32 palreg; |
4678 | i915_reg_t palreg; |
4673 | 4679 | ||
4674 | if (HAS_GMCH_DISPLAY(dev)) |
4680 | if (HAS_GMCH_DISPLAY(dev)) |
4675 | palreg = PALETTE(pipe, i); |
4681 | palreg = PALETTE(pipe, i); |
Line 4721... | Line 4727... | ||
4721 | struct drm_i915_private *dev_priv = dev->dev_private; |
4727 | struct drm_i915_private *dev_priv = dev->dev_private; |
4722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4728 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4723 | int pipe = intel_crtc->pipe; |
4729 | int pipe = intel_crtc->pipe; |
Line 4724... | Line 4730... | ||
4724 | 4730 | ||
4725 | /* |
- | |
4726 | * BDW signals flip done immediately if the plane |
- | |
4727 | * is disabled, even if the plane enable is already |
- | |
4728 | * armed to occur at the next vblank :( |
- | |
4729 | */ |
- | |
4730 | if (IS_BROADWELL(dev)) |
- | |
4731 | intel_wait_for_vblank(dev, pipe); |
- | |
4732 | - | ||
4733 | /* |
4731 | /* |
4734 | * FIXME IPS should be fine as long as one plane is |
4732 | * FIXME IPS should be fine as long as one plane is |
4735 | * enabled, but in practice it seems to have problems |
4733 | * enabled, but in practice it seems to have problems |
4736 | * when going from primary only to sprite only and vice |
4734 | * when going from primary only to sprite only and vice |
4737 | * versa. |
4735 | * versa. |
Line 4746... | Line 4744... | ||
4746 | * but leave the pipe running. |
4744 | * but leave the pipe running. |
4747 | */ |
4745 | */ |
4748 | if (IS_GEN2(dev)) |
4746 | if (IS_GEN2(dev)) |
4749 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4747 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
Line 4750... | Line 4748... | ||
4750 | 4748 | ||
4751 | /* Underruns don't raise interrupts, so check manually. */ |
4749 | /* Underruns don't always raise interrupts, so check manually. */ |
4752 | if (HAS_GMCH_DISPLAY(dev)) |
4750 | intel_check_cpu_fifo_underruns(dev_priv); |
4753 | i9xx_check_fifo_underruns(dev_priv); |
4751 | intel_check_pch_fifo_underruns(dev_priv); |
Line 4754... | Line 4752... | ||
4754 | } |
4752 | } |
4755 | 4753 | ||
4756 | /** |
4754 | /** |
Line 4805... | Line 4803... | ||
4805 | } |
4803 | } |
Line 4806... | Line 4804... | ||
4806 | 4804 | ||
4807 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4805 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4808 | { |
4806 | { |
- | 4807 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
|
- | 4808 | struct intel_crtc_state *pipe_config = |
|
4809 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
4809 | to_intel_crtc_state(crtc->base.state); |
4810 | struct drm_device *dev = crtc->base.dev; |
- | |
4811 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
Line 4812... | Line 4810... | ||
4812 | struct drm_plane *plane; |
4810 | struct drm_device *dev = crtc->base.dev; |
4813 | 4811 | ||
Line 4814... | Line 4812... | ||
4814 | if (atomic->wait_vblank) |
4812 | if (atomic->wait_vblank) |
Line 4815... | Line -... | ||
4815 | intel_wait_for_vblank(dev, crtc->pipe); |
- | |
4816 | 4813 | intel_wait_for_vblank(dev, crtc->pipe); |
|
Line 4817... | Line 4814... | ||
4817 | intel_frontbuffer_flip(dev, atomic->fb_bits); |
4814 | |
4818 | 4815 | intel_frontbuffer_flip(dev, atomic->fb_bits); |
|
Line 4819... | Line 4816... | ||
4819 | if (atomic->disable_cxsr) |
4816 | |
4820 | crtc->wm.cxsr_allowed = true; |
4817 | crtc->wm.cxsr_allowed = true; |
Line 4821... | Line 4818... | ||
4821 | 4818 | ||
4822 | if (crtc->atomic.update_wm_post) |
4819 | if (pipe_config->update_wm_post && pipe_config->base.active) |
Line 4823... | Line -... | ||
4823 | intel_update_watermarks(&crtc->base); |
- | |
4824 | - | ||
4825 | if (atomic->update_fbc) |
- | |
4826 | intel_fbc_update(dev_priv); |
- | |
4827 | 4820 | intel_update_watermarks(&crtc->base); |
|
4828 | if (atomic->post_enable_primary) |
4821 | |
Line 4829... | Line 4822... | ||
4829 | intel_post_enable_primary(&crtc->base); |
4822 | if (atomic->update_fbc) |
4830 | 4823 | intel_fbc_update(crtc); |
|
4831 | drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks) |
4824 | |
4832 | intel_update_sprite_watermarks(plane, &crtc->base, |
4825 | if (atomic->post_enable_primary) |
4833 | 0, 0, 0, false, false); |
4826 | intel_post_enable_primary(&crtc->base); |
4834 | - | ||
4835 | memset(atomic, 0, sizeof(*atomic)); |
- | |
4836 | } |
- | |
4837 | - | ||
4838 | static void intel_pre_plane_update(struct intel_crtc *crtc) |
4827 | |
4839 | { |
- | |
4840 | struct drm_device *dev = crtc->base.dev; |
- | |
4841 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
4842 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
- | |
4843 | struct drm_plane *p; |
- | |
4844 | - | ||
4845 | /* Track fb's for any planes being disabled */ |
- | |
4846 | drm_for_each_plane_mask(p, dev, atomic->disabled_planes) { |
- | |
4847 | struct intel_plane *plane = to_intel_plane(p); |
4828 | memset(atomic, 0, sizeof(*atomic)); |
Line 4848... | Line 4829... | ||
4848 | 4829 | } |
|
4849 | mutex_lock(&dev->struct_mutex); |
4830 | |
Line 4850... | Line 4831... | ||
4850 | i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, |
4831 | static void intel_pre_plane_update(struct intel_crtc *crtc) |
4851 | plane->frontbuffer_bit); |
4832 | { |
Line 4852... | Line 4833... | ||
4852 | mutex_unlock(&dev->struct_mutex); |
4833 | struct drm_device *dev = crtc->base.dev; |
4853 | } |
4834 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 4854... | Line 4835... | ||
4854 | 4835 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
|
4855 | if (atomic->wait_for_flips) |
4836 | struct intel_crtc_state *pipe_config = |
4856 | intel_crtc_wait_for_pending_flips(&crtc->base); |
4837 | to_intel_crtc_state(crtc->base.state); |
4857 | 4838 | ||
- | 4839 | if (atomic->disable_fbc) |
|
- | 4840 | intel_fbc_deactivate(crtc); |
|
- | 4841 | ||
4858 | if (atomic->disable_fbc) |
4842 | if (crtc->atomic.disable_ips) |
Line 4859... | Line 4843... | ||
4859 | intel_fbc_disable_crtc(crtc); |
4843 | hsw_disable_ips(crtc); |
4860 | 4844 | ||
4861 | if (crtc->atomic.disable_ips) |
4845 | if (atomic->pre_disable_primary) |
Line 4900... | Line 4884... | ||
4900 | 4884 | ||
4901 | if (WARN_ON(intel_crtc->active)) |
4885 | if (WARN_ON(intel_crtc->active)) |
Line 4902... | Line 4886... | ||
4902 | return; |
4886 | return; |
- | 4887 | ||
- | 4888 | if (intel_crtc->config->has_pch_encoder) |
|
- | 4889 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
|
4903 | 4890 | ||
Line 4904... | Line 4891... | ||
4904 | if (intel_crtc->config->has_pch_encoder) |
4891 | if (intel_crtc->config->has_pch_encoder) |
4905 | intel_prepare_shared_dpll(intel_crtc); |
4892 | intel_prepare_shared_dpll(intel_crtc); |
Line 4917... | Line 4904... | ||
4917 | ironlake_set_pipeconf(crtc); |
4904 | ironlake_set_pipeconf(crtc); |
Line 4918... | Line 4905... | ||
4918 | 4905 | ||
Line 4919... | Line 4906... | ||
4919 | intel_crtc->active = true; |
4906 | intel_crtc->active = true; |
4920 | - | ||
Line 4921... | Line 4907... | ||
4921 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4907 | |
4922 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
4908 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4923 | 4909 | ||
Line 4955... | Line 4941... | ||
4955 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4941 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4956 | encoder->enable(encoder); |
4942 | encoder->enable(encoder); |
Line 4957... | Line 4943... | ||
4957 | 4943 | ||
4958 | if (HAS_PCH_CPT(dev)) |
4944 | if (HAS_PCH_CPT(dev)) |
- | 4945 | cpt_verify_modeset(dev, intel_crtc->pipe); |
|
- | 4946 | ||
- | 4947 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ |
|
- | 4948 | if (intel_crtc->config->has_pch_encoder) |
|
- | 4949 | intel_wait_for_vblank(dev, pipe); |
|
- | 4950 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
|
- | 4951 | ||
4959 | cpt_verify_modeset(dev, intel_crtc->pipe); |
4952 | intel_fbc_enable(intel_crtc); |
Line 4960... | Line 4953... | ||
4960 | } |
4953 | } |
4961 | 4954 | ||
4962 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4955 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
Line 4972... | Line 4965... | ||
4972 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4965 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4973 | struct intel_encoder *encoder; |
4966 | struct intel_encoder *encoder; |
4974 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4967 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4975 | struct intel_crtc_state *pipe_config = |
4968 | struct intel_crtc_state *pipe_config = |
4976 | to_intel_crtc_state(crtc->state); |
4969 | to_intel_crtc_state(crtc->state); |
4977 | bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
- | |
Line 4978... | Line 4970... | ||
4978 | 4970 | ||
4979 | if (WARN_ON(intel_crtc->active)) |
4971 | if (WARN_ON(intel_crtc->active)) |
Line -... | Line 4972... | ||
- | 4972 | return; |
|
- | 4973 | ||
- | 4974 | if (intel_crtc->config->has_pch_encoder) |
|
- | 4975 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
|
4980 | return; |
4976 | false); |
4981 | 4977 | ||
Line 4982... | Line 4978... | ||
4982 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4978 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4983 | intel_enable_shared_dpll(intel_crtc); |
4979 | intel_enable_shared_dpll(intel_crtc); |
Line 5001... | Line 4997... | ||
5001 | 4997 | ||
Line 5002... | Line 4998... | ||
5002 | intel_set_pipe_csc(crtc); |
4998 | intel_set_pipe_csc(crtc); |
Line -... | Line 4999... | ||
- | 4999 | ||
- | 5000 | intel_crtc->active = true; |
|
- | 5001 | ||
5003 | 5002 | if (intel_crtc->config->has_pch_encoder) |
|
- | 5003 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
|
5004 | intel_crtc->active = true; |
5004 | else |
5005 | - | ||
5006 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
- | |
5007 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5005 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5008 | if (encoder->pre_pll_enable) |
5006 | |
5009 | encoder->pre_pll_enable(encoder); |
5007 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Line 5010... | Line 5008... | ||
5010 | if (encoder->pre_enable) |
5008 | if (encoder->pre_enable) |
5011 | encoder->pre_enable(encoder); |
- | |
5012 | } |
- | |
5013 | 5009 | encoder->pre_enable(encoder); |
|
5014 | if (intel_crtc->config->has_pch_encoder) { |
- | |
Line 5015... | Line 5010... | ||
5015 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5010 | } |
5016 | true); |
5011 | |
Line 5017... | Line 5012... | ||
5017 | dev_priv->display.fdi_link_train(crtc); |
5012 | if (intel_crtc->config->has_pch_encoder) |
5018 | } |
5013 | dev_priv->display.fdi_link_train(crtc); |
5019 | 5014 | ||
Line 5030... | Line 5025... | ||
5030 | * clocks enabled |
5025 | * clocks enabled |
5031 | */ |
5026 | */ |
5032 | intel_crtc_load_lut(crtc); |
5027 | intel_crtc_load_lut(crtc); |
Line 5033... | Line 5028... | ||
5033 | 5028 | ||
5034 | intel_ddi_set_pipe_settings(crtc); |
5029 | intel_ddi_set_pipe_settings(crtc); |
5035 | if (!is_dsi) |
5030 | if (!intel_crtc->config->has_dsi_encoder) |
Line 5036... | Line 5031... | ||
5036 | intel_ddi_enable_transcoder_func(crtc); |
5031 | intel_ddi_enable_transcoder_func(crtc); |
5037 | 5032 | ||
Line 5038... | Line 5033... | ||
5038 | intel_update_watermarks(crtc); |
5033 | intel_update_watermarks(crtc); |
5039 | intel_enable_pipe(intel_crtc); |
5034 | intel_enable_pipe(intel_crtc); |
Line 5040... | Line 5035... | ||
5040 | 5035 | ||
5041 | if (intel_crtc->config->has_pch_encoder) |
5036 | if (intel_crtc->config->has_pch_encoder) |
Line 5042... | Line 5037... | ||
5042 | lpt_pch_enable(crtc); |
5037 | lpt_pch_enable(crtc); |
5043 | 5038 | ||
Line 5044... | Line 5039... | ||
5044 | if (intel_crtc->config->dp_encoder_is_mst && !is_dsi) |
5039 | if (intel_crtc->config->dp_encoder_is_mst) |
5045 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5040 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5046 | 5041 | ||
5047 | assert_vblank_disabled(crtc); |
5042 | assert_vblank_disabled(crtc); |
Line -... | Line 5043... | ||
- | 5043 | drm_crtc_vblank_on(crtc); |
|
- | 5044 | ||
- | 5045 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
|
- | 5046 | encoder->enable(encoder); |
|
- | 5047 | intel_opregion_notify_encoder(encoder, true); |
|
- | 5048 | } |
|
- | 5049 | ||
- | 5050 | if (intel_crtc->config->has_pch_encoder) { |
|
5048 | drm_crtc_vblank_on(crtc); |
5051 | intel_wait_for_vblank(dev, pipe); |
5049 | 5052 | intel_wait_for_vblank(dev, pipe); |
|
5050 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5053 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5051 | encoder->enable(encoder); |
5054 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5052 | intel_opregion_notify_encoder(encoder, true); |
5055 | true); |
5053 | } |
5056 | } |
5054 | 5057 | ||
- | 5058 | /* If we change the relative order between pipe/planes enabling, we need |
|
- | 5059 | * to change the workaround. */ |
|
5055 | /* If we change the relative order between pipe/planes enabling, we need |
5060 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
Line 5056... | Line 5061... | ||
5056 | * to change the workaround. */ |
5061 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { |
5057 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5062 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
5058 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { |
5063 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
Line 5081... | Line 5086... | ||
5081 | struct drm_device *dev = crtc->dev; |
5086 | struct drm_device *dev = crtc->dev; |
5082 | struct drm_i915_private *dev_priv = dev->dev_private; |
5087 | struct drm_i915_private *dev_priv = dev->dev_private; |
5083 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5088 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5084 | struct intel_encoder *encoder; |
5089 | struct intel_encoder *encoder; |
5085 | int pipe = intel_crtc->pipe; |
5090 | int pipe = intel_crtc->pipe; |
- | 5091 | ||
5086 | u32 reg, temp; |
5092 | if (intel_crtc->config->has_pch_encoder) |
- | 5093 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
|
Line 5087... | Line 5094... | ||
5087 | 5094 | ||
5088 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5095 | for_each_encoder_on_crtc(dev, crtc, encoder) |
Line 5089... | Line 5096... | ||
5089 | encoder->disable(encoder); |
5096 | encoder->disable(encoder); |
5090 | 5097 | ||
Line -... | Line 5098... | ||
- | 5098 | drm_crtc_vblank_off(crtc); |
|
- | 5099 | assert_vblank_disabled(crtc); |
|
- | 5100 | ||
- | 5101 | /* |
|
- | 5102 | * Sometimes spurious CPU pipe underruns happen when the |
|
5091 | drm_crtc_vblank_off(crtc); |
5103 | * pipe is already disabled, but FDI RX/TX is still enabled. |
5092 | assert_vblank_disabled(crtc); |
5104 | * Happens at least with VGA+HDMI cloning. Suppress them. |
Line 5093... | Line 5105... | ||
5093 | 5105 | */ |
|
Line 5094... | Line 5106... | ||
5094 | if (intel_crtc->config->has_pch_encoder) |
5106 | if (intel_crtc->config->has_pch_encoder) |
Line 5095... | Line 5107... | ||
5095 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
5107 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
5096 | 5108 | ||
- | 5109 | intel_disable_pipe(intel_crtc); |
|
- | 5110 | ||
Line 5097... | Line 5111... | ||
5097 | intel_disable_pipe(intel_crtc); |
5111 | ironlake_pfit_disable(intel_crtc, false); |
5098 | 5112 | ||
5099 | ironlake_pfit_disable(intel_crtc, false); |
5113 | if (intel_crtc->config->has_pch_encoder) { |
Line 5100... | Line 5114... | ||
5100 | 5114 | ironlake_fdi_disable(crtc); |
|
5101 | if (intel_crtc->config->has_pch_encoder) |
5115 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
Line 5102... | Line 5116... | ||
5102 | ironlake_fdi_disable(crtc); |
5116 | } |
- | 5117 | ||
- | 5118 | for_each_encoder_on_crtc(dev, crtc, encoder) |
|
- | 5119 | if (encoder->post_disable) |
|
5103 | 5120 | encoder->post_disable(encoder); |
|
5104 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5121 | |
5105 | if (encoder->post_disable) |
5122 | if (intel_crtc->config->has_pch_encoder) { |
5106 | encoder->post_disable(encoder); |
5123 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
5107 | 5124 | ||
Line 5123... | Line 5140... | ||
5123 | I915_WRITE(PCH_DPLL_SEL, temp); |
5140 | I915_WRITE(PCH_DPLL_SEL, temp); |
5124 | } |
5141 | } |
Line 5125... | Line 5142... | ||
5125 | 5142 | ||
5126 | ironlake_fdi_pll_disable(intel_crtc); |
5143 | ironlake_fdi_pll_disable(intel_crtc); |
- | 5144 | } |
|
- | 5145 | ||
- | 5146 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
|
- | 5147 | ||
5127 | } |
5148 | intel_fbc_disable_crtc(intel_crtc); |
Line 5128... | Line 5149... | ||
5128 | } |
5149 | } |
5129 | 5150 | ||
5130 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
5151 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
5131 | { |
5152 | { |
5132 | struct drm_device *dev = crtc->dev; |
5153 | struct drm_device *dev = crtc->dev; |
5133 | struct drm_i915_private *dev_priv = dev->dev_private; |
5154 | struct drm_i915_private *dev_priv = dev->dev_private; |
5134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | 5156 | struct intel_encoder *encoder; |
|
- | 5157 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
|
5135 | struct intel_encoder *encoder; |
5158 | |
- | 5159 | if (intel_crtc->config->has_pch_encoder) |
|
Line 5136... | Line 5160... | ||
5136 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
5160 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5137 | bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
5161 | false); |
5138 | 5162 | ||
5139 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5163 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Line 5140... | Line 5164... | ||
5140 | intel_opregion_notify_encoder(encoder, false); |
5164 | intel_opregion_notify_encoder(encoder, false); |
5141 | encoder->disable(encoder); |
5165 | encoder->disable(encoder); |
Line 5142... | Line -... | ||
5142 | } |
- | |
5143 | - | ||
5144 | drm_crtc_vblank_off(crtc); |
- | |
5145 | assert_vblank_disabled(crtc); |
5166 | } |
Line 5146... | Line 5167... | ||
5146 | 5167 | ||
5147 | if (intel_crtc->config->has_pch_encoder) |
5168 | drm_crtc_vblank_off(crtc); |
Line 5148... | Line 5169... | ||
5148 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5169 | assert_vblank_disabled(crtc); |
5149 | false); |
5170 | |
Line 5150... | Line 5171... | ||
5150 | intel_disable_pipe(intel_crtc); |
5171 | intel_disable_pipe(intel_crtc); |
5151 | 5172 | ||
5152 | if (intel_crtc->config->dp_encoder_is_mst) |
5173 | if (intel_crtc->config->dp_encoder_is_mst) |
5153 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5174 | intel_ddi_set_vc_payload_alloc(crtc, false); |
Line 5154... | Line 5175... | ||
5154 | 5175 | ||
5155 | if (!is_dsi) |
5176 | if (!intel_crtc->config->has_dsi_encoder) |
Line -... | Line 5177... | ||
- | 5177 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
|
- | 5178 | ||
- | 5179 | if (INTEL_INFO(dev)->gen >= 9) |
|
- | 5180 | skylake_scaler_disable(intel_crtc); |
|
5156 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
5181 | else |
5157 | 5182 | ironlake_pfit_disable(intel_crtc, false); |
|
- | 5183 | ||
5158 | if (INTEL_INFO(dev)->gen >= 9) |
5184 | if (!intel_crtc->config->has_dsi_encoder) |
- | 5185 | intel_ddi_disable_pipe_clock(intel_crtc); |
|
- | 5186 | ||
- | 5187 | for_each_encoder_on_crtc(dev, crtc, encoder) |
|
5159 | skylake_scaler_disable(intel_crtc); |
5188 | if (encoder->post_disable) |
Line 5160... | Line -... | ||
5160 | else |
- | |
5161 | ironlake_pfit_disable(intel_crtc, false); |
- | |
5162 | 5189 | encoder->post_disable(encoder); |
|
5163 | if (!is_dsi) |
5190 | |
Line 5164... | Line 5191... | ||
5164 | intel_ddi_disable_pipe_clock(intel_crtc); |
5191 | if (intel_crtc->config->has_pch_encoder) { |
5165 | 5192 | lpt_disable_pch_transcoder(dev_priv); |
|
5166 | if (intel_crtc->config->has_pch_encoder) { |
5193 | lpt_disable_iclkip(dev_priv); |
Line 5199... | Line 5226... | ||
5199 | 5226 | ||
5200 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5227 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5201 | { |
5228 | { |
5202 | switch (port) { |
5229 | switch (port) { |
5203 | case PORT_A: |
5230 | case PORT_A: |
5204 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; |
5231 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
5205 | case PORT_B: |
5232 | case PORT_B: |
5206 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; |
5233 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
5207 | case PORT_C: |
5234 | case PORT_C: |
5208 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; |
5235 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
5209 | case PORT_D: |
5236 | case PORT_D: |
5210 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; |
5237 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
5211 | case PORT_E: |
5238 | case PORT_E: |
5212 | return POWER_DOMAIN_PORT_DDI_E_2_LANES; |
5239 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
5213 | default: |
5240 | default: |
5214 | MISSING_CASE(port); |
5241 | MISSING_CASE(port); |
5215 | return POWER_DOMAIN_PORT_OTHER; |
5242 | return POWER_DOMAIN_PORT_OTHER; |
5216 | } |
5243 | } |
Line 5234... | Line 5261... | ||
5234 | MISSING_CASE(port); |
5261 | MISSING_CASE(port); |
5235 | return POWER_DOMAIN_AUX_A; |
5262 | return POWER_DOMAIN_AUX_A; |
5236 | } |
5263 | } |
5237 | } |
5264 | } |
Line 5238... | Line -... | ||
5238 | - | ||
5239 | #define for_each_power_domain(domain, mask) \ |
- | |
5240 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
- | |
5241 | if ((1 << (domain)) & (mask)) |
- | |
5242 | 5265 | ||
5243 | enum intel_display_power_domain |
5266 | enum intel_display_power_domain |
5244 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) |
5267 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) |
5245 | { |
5268 | { |
5246 | struct drm_device *dev = intel_encoder->base.dev; |
5269 | struct drm_device *dev = intel_encoder->base.dev; |
Line 5302... | Line 5325... | ||
5302 | struct drm_device *dev = crtc->dev; |
5325 | struct drm_device *dev = crtc->dev; |
5303 | struct intel_encoder *intel_encoder; |
5326 | struct intel_encoder *intel_encoder; |
5304 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5327 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5305 | enum pipe pipe = intel_crtc->pipe; |
5328 | enum pipe pipe = intel_crtc->pipe; |
5306 | unsigned long mask; |
5329 | unsigned long mask; |
5307 | enum transcoder transcoder; |
5330 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
Line 5308... | Line 5331... | ||
5308 | 5331 | ||
5309 | if (!crtc->state->active) |
5332 | if (!crtc->state->active) |
Line 5310... | Line -... | ||
5310 | return 0; |
- | |
5311 | - | ||
5312 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
5333 | return 0; |
5313 | 5334 | ||
5314 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5335 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5315 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
5336 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
5316 | if (intel_crtc->config->pch_pfit.enabled || |
5337 | if (intel_crtc->config->pch_pfit.enabled || |
Line 5395... | Line 5416... | ||
5395 | 5416 | ||
5396 | static void intel_update_max_cdclk(struct drm_device *dev) |
5417 | static void intel_update_max_cdclk(struct drm_device *dev) |
5397 | { |
5418 | { |
Line 5398... | Line 5419... | ||
5398 | struct drm_i915_private *dev_priv = dev->dev_private; |
5419 | struct drm_i915_private *dev_priv = dev->dev_private; |
5399 | 5420 | ||
Line 5400... | Line 5421... | ||
5400 | if (IS_SKYLAKE(dev)) { |
5421 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
5401 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5422 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5402 | 5423 | ||
Line 5452... | Line 5473... | ||
5452 | /* |
5473 | /* |
5453 | * Program the gmbus_freq based on the cdclk frequency. |
5474 | * Program the gmbus_freq based on the cdclk frequency. |
5454 | * BSpec erroneously claims we should aim for 4MHz, but |
5475 | * BSpec erroneously claims we should aim for 4MHz, but |
5455 | * in fact 1MHz is the correct frequency. |
5476 | * in fact 1MHz is the correct frequency. |
5456 | */ |
5477 | */ |
5457 | if (IS_VALLEYVIEW(dev)) { |
5478 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
5458 | /* |
5479 | /* |
5459 | * Program the gmbus_freq based on the cdclk frequency. |
5480 | * Program the gmbus_freq based on the cdclk frequency. |
5460 | * BSpec erroneously claims we should aim for 4MHz, but |
5481 | * BSpec erroneously claims we should aim for 4MHz, but |
5461 | * in fact 1MHz is the correct frequency. |
5482 | * in fact 1MHz is the correct frequency. |
5462 | */ |
5483 | */ |
Line 5812... | Line 5833... | ||
5812 | udelay(10); |
5833 | udelay(10); |
Line 5813... | Line 5834... | ||
5813 | 5834 | ||
5814 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) |
5835 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) |
Line 5815... | Line -... | ||
5815 | DRM_ERROR("DBuf power disable timeout\n"); |
- | |
5816 | - | ||
5817 | /* |
- | |
5818 | * DMC assumes ownership of LCPLL and will get confused if we touch it. |
- | |
5819 | */ |
5836 | DRM_ERROR("DBuf power disable timeout\n"); |
5820 | if (dev_priv->csr.dmc_payload) { |
5837 | |
5821 | /* disable DPLL0 */ |
- | |
5822 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & |
5838 | /* disable DPLL0 */ |
5823 | ~LCPLL_PLL_ENABLE); |
5839 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); |
5824 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) |
5840 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) |
Line 5825... | Line -... | ||
5825 | DRM_ERROR("Couldn't disable DPLL0\n"); |
- | |
5826 | } |
- | |
5827 | - | ||
5828 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
5841 | DRM_ERROR("Couldn't disable DPLL0\n"); |
5829 | } |
5842 | } |
5830 | - | ||
5831 | void skl_init_cdclk(struct drm_i915_private *dev_priv) |
5843 | |
Line 5832... | Line -... | ||
5832 | { |
- | |
5833 | u32 val; |
- | |
5834 | unsigned int required_vco; |
- | |
5835 | - | ||
5836 | /* enable PCH reset handshake */ |
- | |
5837 | val = I915_READ(HSW_NDE_RSTWRN_OPT); |
- | |
5838 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); |
- | |
5839 | 5844 | void skl_init_cdclk(struct drm_i915_private *dev_priv) |
|
5840 | /* enable PG1 and Misc I/O */ |
5845 | { |
5841 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5846 | unsigned int required_vco; |
5842 | 5847 | ||
5843 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5848 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
Line 5858... | Line 5863... | ||
5858 | 5863 | ||
5859 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) |
5864 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) |
5860 | DRM_ERROR("DBuf power enable timeout\n"); |
5865 | DRM_ERROR("DBuf power enable timeout\n"); |
Line -... | Line 5866... | ||
- | 5866 | } |
|
- | 5867 | ||
- | 5868 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
|
- | 5869 | { |
|
- | 5870 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); |
|
- | 5871 | uint32_t cdctl = I915_READ(CDCLK_CTL); |
|
- | 5872 | int freq = dev_priv->skl_boot_cdclk; |
|
- | 5873 | ||
- | 5874 | /* |
|
- | 5875 | * check if the pre-os intialized the display |
|
- | 5876 | * There is SWF18 scratchpad register defined which is set by the |
|
- | 5877 | * pre-os which can be used by the OS drivers to check the status |
|
- | 5878 | */ |
|
- | 5879 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) |
|
- | 5880 | goto sanitize; |
|
- | 5881 | ||
- | 5882 | /* Is PLL enabled and locked ? */ |
|
- | 5883 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) |
|
- | 5884 | goto sanitize; |
|
- | 5885 | ||
- | 5886 | /* DPLL okay; verify the cdclock |
|
- | 5887 | * |
|
- | 5888 | * Noticed in some instances that the freq selection is correct but |
|
- | 5889 | * decimal part is programmed wrong from BIOS where pre-os does not |
|
- | 5890 | * enable display. Verify the same as well. |
|
- | 5891 | */ |
|
- | 5892 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) |
|
- | 5893 | /* All well; nothing to sanitize */ |
|
- | 5894 | return false; |
|
- | 5895 | sanitize: |
|
- | 5896 | /* |
|
- | 5897 | * As of now initialize with max cdclk till |
|
- | 5898 | * we get dynamic cdclk support |
|
- | 5899 | * */ |
|
- | 5900 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; |
|
- | 5901 | skl_init_cdclk(dev_priv); |
|
- | 5902 | ||
- | 5903 | /* we did have to sanitize */ |
|
- | 5904 | return true; |
|
5861 | } |
5905 | } |
5862 | 5906 | ||
5863 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5907 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5864 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
5908 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
5865 | { |
5909 | { |
Line 6139... | Line 6183... | ||
6139 | struct drm_device *dev = crtc->dev; |
6183 | struct drm_device *dev = crtc->dev; |
6140 | struct drm_i915_private *dev_priv = to_i915(dev); |
6184 | struct drm_i915_private *dev_priv = to_i915(dev); |
6141 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6185 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6142 | struct intel_encoder *encoder; |
6186 | struct intel_encoder *encoder; |
6143 | int pipe = intel_crtc->pipe; |
6187 | int pipe = intel_crtc->pipe; |
6144 | bool is_dsi; |
- | |
Line 6145... | Line 6188... | ||
6145 | 6188 | ||
6146 | if (WARN_ON(intel_crtc->active)) |
6189 | if (WARN_ON(intel_crtc->active)) |
Line 6147... | Line -... | ||
6147 | return; |
- | |
6148 | - | ||
6149 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
6190 | return; |
6150 | 6191 | ||
Line 6151... | Line 6192... | ||
6151 | if (intel_crtc->config->has_dp_encoder) |
6192 | if (intel_crtc->config->has_dp_encoder) |
Line 6168... | Line 6209... | ||
6168 | 6209 | ||
6169 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6210 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6170 | if (encoder->pre_pll_enable) |
6211 | if (encoder->pre_pll_enable) |
Line 6171... | Line 6212... | ||
6171 | encoder->pre_pll_enable(encoder); |
6212 | encoder->pre_pll_enable(encoder); |
6172 | 6213 | ||
6173 | if (!is_dsi) { |
6214 | if (!intel_crtc->config->has_dsi_encoder) { |
6174 | if (IS_CHERRYVIEW(dev)) { |
6215 | if (IS_CHERRYVIEW(dev)) { |
6175 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
6216 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
6176 | chv_enable_pll(intel_crtc, intel_crtc->config); |
6217 | chv_enable_pll(intel_crtc, intel_crtc->config); |
Line 6186... | Line 6227... | ||
6186 | 6227 | ||
Line 6187... | Line 6228... | ||
6187 | i9xx_pfit_enable(intel_crtc); |
6228 | i9xx_pfit_enable(intel_crtc); |
Line -... | Line 6229... | ||
- | 6229 | ||
6188 | 6230 | intel_crtc_load_lut(crtc); |
|
Line 6189... | Line 6231... | ||
6189 | intel_crtc_load_lut(crtc); |
6231 | |
6190 | 6232 | intel_update_watermarks(crtc); |
|
Line 6247... | Line 6289... | ||
6247 | assert_vblank_disabled(crtc); |
6289 | assert_vblank_disabled(crtc); |
6248 | drm_crtc_vblank_on(crtc); |
6290 | drm_crtc_vblank_on(crtc); |
Line 6249... | Line 6291... | ||
6249 | 6291 | ||
6250 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6292 | for_each_encoder_on_crtc(dev, crtc, encoder) |
- | 6293 | encoder->enable(encoder); |
|
- | 6294 | ||
6251 | encoder->enable(encoder); |
6295 | intel_fbc_enable(intel_crtc); |
Line 6252... | Line 6296... | ||
6252 | } |
6296 | } |
6253 | 6297 | ||
6254 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6298 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
Line 6294... | Line 6338... | ||
6294 | 6338 | ||
6295 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6339 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6296 | if (encoder->post_disable) |
6340 | if (encoder->post_disable) |
Line 6297... | Line 6341... | ||
6297 | encoder->post_disable(encoder); |
6341 | encoder->post_disable(encoder); |
6298 | 6342 | ||
6299 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
6343 | if (!intel_crtc->config->has_dsi_encoder) { |
6300 | if (IS_CHERRYVIEW(dev)) |
6344 | if (IS_CHERRYVIEW(dev)) |
6301 | chv_disable_pll(dev_priv, pipe); |
6345 | chv_disable_pll(dev_priv, pipe); |
6302 | else if (IS_VALLEYVIEW(dev)) |
6346 | else if (IS_VALLEYVIEW(dev)) |
Line 6309... | Line 6353... | ||
6309 | if (encoder->post_pll_disable) |
6353 | if (encoder->post_pll_disable) |
6310 | encoder->post_pll_disable(encoder); |
6354 | encoder->post_pll_disable(encoder); |
Line 6311... | Line 6355... | ||
6311 | 6355 | ||
6312 | if (!IS_GEN2(dev)) |
6356 | if (!IS_GEN2(dev)) |
- | 6357 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
|
- | 6358 | ||
6313 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
6359 | intel_fbc_disable_crtc(intel_crtc); |
Line 6314... | Line 6360... | ||
6314 | } |
6360 | } |
6315 | 6361 | ||
6316 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6362 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
Line 6322... | Line 6368... | ||
6322 | 6368 | ||
6323 | if (!intel_crtc->active) |
6369 | if (!intel_crtc->active) |
Line 6324... | Line 6370... | ||
6324 | return; |
6370 | return; |
6325 | 6371 | ||
- | 6372 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
|
6326 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
6373 | WARN_ON(intel_crtc->unpin_work); |
Line 6327... | Line 6374... | ||
6327 | intel_crtc_wait_for_pending_flips(crtc); |
6374 | |
6328 | intel_pre_disable_primary(crtc); |
6375 | intel_pre_disable_primary(crtc); |
6329 | 6376 | ||
Line 6447... | Line 6494... | ||
6447 | } |
6494 | } |
6448 | } |
6495 | } |
Line 6449... | Line 6496... | ||
6449 | 6496 | ||
6450 | int intel_connector_init(struct intel_connector *connector) |
6497 | int intel_connector_init(struct intel_connector *connector) |
6451 | { |
6498 | { |
Line 6452... | Line -... | ||
6452 | struct drm_connector_state *connector_state; |
- | |
6453 | 6499 | drm_atomic_helper_connector_reset(&connector->base); |
|
6454 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); |
6500 | |
Line 6455... | Line -... | ||
6455 | if (!connector_state) |
- | |
6456 | return -ENOMEM; |
6501 | if (!connector->base.state) |
6457 | 6502 | return -ENOMEM; |
|
Line 6458... | Line 6503... | ||
6458 | connector->base.state = connector_state; |
6503 | |
6459 | return 0; |
6504 | return 0; |
Line 6642... | Line 6687... | ||
6642 | pipe_config->ips_enabled = i915.enable_ips && |
6687 | pipe_config->ips_enabled = i915.enable_ips && |
6643 | hsw_crtc_supports_ips(crtc) && |
6688 | hsw_crtc_supports_ips(crtc) && |
6644 | pipe_config_supports_ips(dev_priv, pipe_config); |
6689 | pipe_config_supports_ips(dev_priv, pipe_config); |
6645 | } |
6690 | } |
Line -... | Line 6691... | ||
- | 6691 | ||
- | 6692 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
|
- | 6693 | { |
|
- | 6694 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
|
- | 6695 | ||
- | 6696 | /* GDG double wide on either pipe, otherwise pipe A only */ |
|
- | 6697 | return INTEL_INFO(dev_priv)->gen < 4 && |
|
- | 6698 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); |
|
- | 6699 | } |
|
6646 | 6700 | ||
6647 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6701 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6648 | struct intel_crtc_state *pipe_config) |
6702 | struct intel_crtc_state *pipe_config) |
6649 | { |
6703 | { |
6650 | struct drm_device *dev = crtc->base.dev; |
6704 | struct drm_device *dev = crtc->base.dev; |
6651 | struct drm_i915_private *dev_priv = dev->dev_private; |
6705 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 6652... | Line 6706... | ||
6652 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6706 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6653 | 6707 | ||
6654 | /* FIXME should check pixel clock limits on all platforms */ |
6708 | /* FIXME should check pixel clock limits on all platforms */ |
Line 6655... | Line 6709... | ||
6655 | if (INTEL_INFO(dev)->gen < 4) { |
6709 | if (INTEL_INFO(dev)->gen < 4) { |
6656 | int clock_limit = dev_priv->max_cdclk_freq; |
6710 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
6657 | 6711 | ||
6658 | /* |
- | |
6659 | * Enable pixel doubling when the dot clock |
- | |
6660 | * is > 90% of the (display) core speed. |
- | |
6661 | * |
6712 | /* |
6662 | * GDG double wide on either pipe, |
6713 | * Enable double wide mode when the dot clock |
6663 | * otherwise pipe A only. |
6714 | * is > 90% of the (display) core speed. |
6664 | */ |
6715 | */ |
6665 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
6716 | if (intel_crtc_supports_double_wide(crtc) && |
6666 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
6717 | adjusted_mode->crtc_clock > clock_limit) { |
Line 6667... | Line 6718... | ||
6667 | clock_limit *= 2; |
6718 | clock_limit *= 2; |
- | 6719 | pipe_config->double_wide = true; |
|
- | 6720 | } |
|
- | 6721 | ||
6668 | pipe_config->double_wide = true; |
6722 | if (adjusted_mode->crtc_clock > clock_limit) { |
6669 | } |
6723 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", |
- | 6724 | adjusted_mode->crtc_clock, clock_limit, |
|
Line 6670... | Line 6725... | ||
6670 | 6725 | yesno(pipe_config->double_wide)); |
|
6671 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
6726 | return -EINVAL; |
6672 | return -EINVAL; |
6727 | } |
6673 | } |
6728 | } |
Line 7144... | Line 7199... | ||
7144 | struct drm_i915_private *dev_priv = dev->dev_private; |
7199 | struct drm_i915_private *dev_priv = dev->dev_private; |
7145 | int refclk; |
7200 | int refclk; |
Line 7146... | Line 7201... | ||
7146 | 7201 | ||
Line 7147... | Line 7202... | ||
7147 | WARN_ON(!crtc_state->base.state); |
7202 | WARN_ON(!crtc_state->base.state); |
7148 | 7203 | ||
7149 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
7204 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
7150 | refclk = 100000; |
7205 | refclk = 100000; |
7151 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
7206 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
7152 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
7207 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
Line 7432... | Line 7487... | ||
7432 | const struct intel_crtc_state *pipe_config) |
7487 | const struct intel_crtc_state *pipe_config) |
7433 | { |
7488 | { |
7434 | struct drm_device *dev = crtc->base.dev; |
7489 | struct drm_device *dev = crtc->base.dev; |
7435 | struct drm_i915_private *dev_priv = dev->dev_private; |
7490 | struct drm_i915_private *dev_priv = dev->dev_private; |
7436 | int pipe = crtc->pipe; |
7491 | int pipe = crtc->pipe; |
7437 | int dpll_reg = DPLL(crtc->pipe); |
7492 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
7438 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
7493 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
7439 | u32 loopfilter, tribuf_calcntr; |
7494 | u32 loopfilter, tribuf_calcntr; |
7440 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
7495 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
7441 | u32 dpio_val; |
7496 | u32 dpio_val; |
7442 | int vco; |
7497 | int vco; |
Line 7843... | Line 7898... | ||
7843 | 7898 | ||
7844 | if (intel_crtc->config->double_wide) |
7899 | if (intel_crtc->config->double_wide) |
Line 7845... | Line 7900... | ||
7845 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
7900 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
7846 | 7901 | ||
7847 | /* only g4x and later have fancy bpc/dither controls */ |
7902 | /* only g4x and later have fancy bpc/dither controls */ |
7848 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
7903 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
7849 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
7904 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
7850 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
7905 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
Line 7883... | Line 7938... | ||
7883 | else |
7938 | else |
7884 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; |
7939 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; |
7885 | } else |
7940 | } else |
7886 | pipeconf |= PIPECONF_PROGRESSIVE; |
7941 | pipeconf |= PIPECONF_PROGRESSIVE; |
Line -... | Line 7942... | ||
- | 7942 | ||
7887 | 7943 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
|
7888 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
7944 | intel_crtc->config->limited_color_range) |
Line 7889... | Line 7945... | ||
7889 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
7945 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
7890 | 7946 | ||
7891 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7947 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
Line 7898... | Line 7954... | ||
7898 | struct drm_device *dev = crtc->base.dev; |
7954 | struct drm_device *dev = crtc->base.dev; |
7899 | struct drm_i915_private *dev_priv = dev->dev_private; |
7955 | struct drm_i915_private *dev_priv = dev->dev_private; |
7900 | int refclk, num_connectors = 0; |
7956 | int refclk, num_connectors = 0; |
7901 | intel_clock_t clock; |
7957 | intel_clock_t clock; |
7902 | bool ok; |
7958 | bool ok; |
7903 | bool is_dsi = false; |
- | |
7904 | struct intel_encoder *encoder; |
- | |
7905 | const intel_limit_t *limit; |
7959 | const intel_limit_t *limit; |
7906 | struct drm_atomic_state *state = crtc_state->base.state; |
7960 | struct drm_atomic_state *state = crtc_state->base.state; |
7907 | struct drm_connector *connector; |
7961 | struct drm_connector *connector; |
7908 | struct drm_connector_state *connector_state; |
7962 | struct drm_connector_state *connector_state; |
7909 | int i; |
7963 | int i; |
Line 7910... | Line 7964... | ||
7910 | 7964 | ||
7911 | memset(&crtc_state->dpll_hw_state, 0, |
7965 | memset(&crtc_state->dpll_hw_state, 0, |
Line 7912... | Line -... | ||
7912 | sizeof(crtc_state->dpll_hw_state)); |
- | |
7913 | 7966 | sizeof(crtc_state->dpll_hw_state)); |
|
7914 | for_each_connector_in_state(state, connector, connector_state, i) { |
- | |
7915 | if (connector_state->crtc != &crtc->base) |
- | |
7916 | continue; |
- | |
7917 | - | ||
7918 | encoder = to_intel_encoder(connector_state->best_encoder); |
- | |
7919 | - | ||
7920 | switch (encoder->type) { |
- | |
7921 | case INTEL_OUTPUT_DSI: |
- | |
7922 | is_dsi = true; |
- | |
7923 | break; |
7967 | |
7924 | default: |
- | |
Line -... | Line 7968... | ||
- | 7968 | if (crtc_state->has_dsi_encoder) |
|
- | 7969 | return 0; |
|
7925 | break; |
7970 | |
7926 | } |
7971 | for_each_connector_in_state(state, connector, connector_state, i) { |
Line 7927... | Line -... | ||
7927 | - | ||
7928 | num_connectors++; |
- | |
7929 | } |
- | |
7930 | 7972 | if (connector_state->crtc == &crtc->base) |
|
7931 | if (is_dsi) |
7973 | num_connectors++; |
Line 7932... | Line 7974... | ||
7932 | return 0; |
7974 | } |
7933 | 7975 | ||
Line 8131... | Line 8173... | ||
8131 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
8173 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
8132 | struct intel_crtc_state *pipe_config) |
8174 | struct intel_crtc_state *pipe_config) |
8133 | { |
8175 | { |
8134 | struct drm_device *dev = crtc->base.dev; |
8176 | struct drm_device *dev = crtc->base.dev; |
8135 | struct drm_i915_private *dev_priv = dev->dev_private; |
8177 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 8178 | enum intel_display_power_domain power_domain; |
|
8136 | uint32_t tmp; |
8179 | uint32_t tmp; |
- | 8180 | bool ret; |
|
Line 8137... | Line -... | ||
8137 | - | ||
8138 | if (!intel_display_power_is_enabled(dev_priv, |
8181 | |
- | 8182 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
|
8139 | POWER_DOMAIN_PIPE(crtc->pipe))) |
8183 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Line 8140... | Line 8184... | ||
8140 | return false; |
8184 | return false; |
8141 | 8185 | ||
Line -... | Line 8186... | ||
- | 8186 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
|
- | 8187 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
|
8142 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8188 | |
8143 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8189 | ret = false; |
8144 | 8190 | ||
Line 8145... | Line 8191... | ||
8145 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8191 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8146 | if (!(tmp & PIPECONF_ENABLE)) |
8192 | if (!(tmp & PIPECONF_ENABLE)) |
8147 | return false; |
8193 | goto out; |
8148 | 8194 | ||
8149 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
8195 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
8150 | switch (tmp & PIPECONF_BPC_MASK) { |
8196 | switch (tmp & PIPECONF_BPC_MASK) { |
Line 8160... | Line 8206... | ||
8160 | default: |
8206 | default: |
8161 | break; |
8207 | break; |
8162 | } |
8208 | } |
8163 | } |
8209 | } |
Line -... | Line 8210... | ||
- | 8210 | ||
8164 | 8211 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
|
8165 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
8212 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
Line 8166... | Line 8213... | ||
8166 | pipe_config->limited_color_range = true; |
8213 | pipe_config->limited_color_range = true; |
8167 | 8214 | ||
Line 8188... | Line 8235... | ||
8188 | * port and will be fixed up in the encoder->get_config |
8235 | * port and will be fixed up in the encoder->get_config |
8189 | * function. */ |
8236 | * function. */ |
8190 | pipe_config->pixel_multiplier = 1; |
8237 | pipe_config->pixel_multiplier = 1; |
8191 | } |
8238 | } |
8192 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
8239 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
8193 | if (!IS_VALLEYVIEW(dev)) { |
8240 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
8194 | /* |
8241 | /* |
8195 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs |
8242 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs |
8196 | * on 830. Filter it out here so that we don't |
8243 | * on 830. Filter it out here so that we don't |
8197 | * report errors due to that. |
8244 | * report errors due to that. |
8198 | */ |
8245 | */ |
Line 8221... | Line 8268... | ||
8221 | * default. |
8268 | * default. |
8222 | */ |
8269 | */ |
8223 | pipe_config->base.adjusted_mode.crtc_clock = |
8270 | pipe_config->base.adjusted_mode.crtc_clock = |
8224 | pipe_config->port_clock / pipe_config->pixel_multiplier; |
8271 | pipe_config->port_clock / pipe_config->pixel_multiplier; |
Line 8225... | Line 8272... | ||
8225 | 8272 | ||
- | 8273 | ret = true; |
|
- | 8274 | ||
- | 8275 | out: |
|
- | 8276 | intel_display_power_put(dev_priv, power_domain); |
|
- | 8277 | ||
8226 | return true; |
8278 | return ret; |
Line 8227... | Line 8279... | ||
8227 | } |
8279 | } |
8228 | 8280 | ||
8229 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
8281 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
8230 | { |
8282 | { |
8231 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
8232 | struct intel_encoder *encoder; |
8283 | struct drm_i915_private *dev_priv = dev->dev_private; |
8233 | int i; |
8284 | struct intel_encoder *encoder; |
8234 | u32 val, final; |
8285 | u32 val, final; |
8235 | bool has_lvds = false; |
8286 | bool has_lvds = false; |
8236 | bool has_cpu_edp = false; |
8287 | bool has_cpu_edp = false; |
8237 | bool has_panel = false; |
8288 | bool has_panel = false; |
8238 | bool has_ck505 = false; |
- | |
Line 8239... | Line 8289... | ||
8239 | bool can_ssc = false; |
8289 | bool has_ck505 = false; |
8240 | bool using_ssc_source = false; |
8290 | bool can_ssc = false; |
8241 | 8291 | ||
8242 | /* We need to take the global config into account */ |
8292 | /* We need to take the global config into account */ |
Line 8262... | Line 8312... | ||
8262 | } else { |
8312 | } else { |
8263 | has_ck505 = false; |
8313 | has_ck505 = false; |
8264 | can_ssc = true; |
8314 | can_ssc = true; |
8265 | } |
8315 | } |
Line 8266... | Line -... | ||
8266 | - | ||
8267 | /* Check if any DPLLs are using the SSC source */ |
- | |
8268 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
- | |
8269 | u32 temp = I915_READ(PCH_DPLL(i)); |
- | |
8270 | - | ||
8271 | if (!(temp & DPLL_VCO_ENABLE)) |
- | |
8272 | continue; |
- | |
8273 | - | ||
8274 | if ((temp & PLL_REF_INPUT_MASK) == |
- | |
8275 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
- | |
8276 | using_ssc_source = true; |
- | |
8277 | break; |
- | |
8278 | } |
- | |
8279 | } |
- | |
8280 | 8316 | ||
8281 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", |
8317 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
Line 8282... | Line 8318... | ||
8282 | has_panel, has_lvds, has_ck505, using_ssc_source); |
8318 | has_panel, has_lvds, has_ck505); |
8283 | 8319 | ||
8284 | /* Ironlake: try to setup display ref clock before DPLL |
8320 | /* Ironlake: try to setup display ref clock before DPLL |
8285 | * enabling. This is only under driver's control after |
8321 | * enabling. This is only under driver's control after |
Line 8314... | Line 8350... | ||
8314 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
8350 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
8315 | else |
8351 | else |
8316 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
8352 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
8317 | } else |
8353 | } else |
8318 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
8354 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
8319 | } else if (using_ssc_source) { |
8355 | } else { |
8320 | final |= DREF_SSC_SOURCE_ENABLE; |
8356 | final |= DREF_SSC_SOURCE_DISABLE; |
8321 | final |= DREF_SSC1_ENABLE; |
8357 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
8322 | } |
8358 | } |
Line 8323... | Line 8359... | ||
8323 | 8359 | ||
8324 | if (final == val) |
8360 | if (final == val) |
Line 8362... | Line 8398... | ||
8362 | 8398 | ||
8363 | I915_WRITE(PCH_DREF_CONTROL, val); |
8399 | I915_WRITE(PCH_DREF_CONTROL, val); |
8364 | POSTING_READ(PCH_DREF_CONTROL); |
8400 | POSTING_READ(PCH_DREF_CONTROL); |
8365 | udelay(200); |
8401 | udelay(200); |
8366 | } else { |
8402 | } else { |
Line 8367... | Line 8403... | ||
8367 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
8403 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
Line 8368... | Line 8404... | ||
8368 | 8404 | ||
8369 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8405 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
Line 8370... | Line 8406... | ||
8370 | 8406 | ||
8371 | /* Turn off CPU output */ |
8407 | /* Turn off CPU output */ |
8372 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
8408 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Line 8373... | Line -... | ||
8373 | - | ||
8374 | I915_WRITE(PCH_DREF_CONTROL, val); |
- | |
8375 | POSTING_READ(PCH_DREF_CONTROL); |
- | |
8376 | udelay(200); |
8409 | |
8377 | 8410 | I915_WRITE(PCH_DREF_CONTROL, val); |
|
8378 | if (!using_ssc_source) { |
8411 | POSTING_READ(PCH_DREF_CONTROL); |
Line 8379... | Line 8412... | ||
8379 | DRM_DEBUG_KMS("Disabling SSC source\n"); |
8412 | udelay(200); |
Line 8387... | Line 8420... | ||
8387 | 8420 | ||
8388 | I915_WRITE(PCH_DREF_CONTROL, val); |
8421 | I915_WRITE(PCH_DREF_CONTROL, val); |
8389 | POSTING_READ(PCH_DREF_CONTROL); |
8422 | POSTING_READ(PCH_DREF_CONTROL); |
8390 | udelay(200); |
8423 | udelay(200); |
8391 | } |
- | |
Line 8392... | Line 8424... | ||
8392 | } |
8424 | } |
8393 | 8425 | ||
Line 8394... | Line 8426... | ||
8394 | BUG_ON(val != final); |
8426 | BUG_ON(val != final); |
Line 8560... | Line 8592... | ||
8560 | } |
8592 | } |
Line 8561... | Line 8593... | ||
8561 | 8593 | ||
8562 | mutex_unlock(&dev_priv->sb_lock); |
8594 | mutex_unlock(&dev_priv->sb_lock); |
Line -... | Line 8595... | ||
- | 8595 | } |
|
- | 8596 | ||
- | 8597 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
|
- | 8598 | ||
- | 8599 | static const uint16_t sscdivintphase[] = { |
|
- | 8600 | [BEND_IDX( 50)] = 0x3B23, |
|
- | 8601 | [BEND_IDX( 45)] = 0x3B23, |
|
- | 8602 | [BEND_IDX( 40)] = 0x3C23, |
|
- | 8603 | [BEND_IDX( 35)] = 0x3C23, |
|
- | 8604 | [BEND_IDX( 30)] = 0x3D23, |
|
- | 8605 | [BEND_IDX( 25)] = 0x3D23, |
|
- | 8606 | [BEND_IDX( 20)] = 0x3E23, |
|
- | 8607 | [BEND_IDX( 15)] = 0x3E23, |
|
- | 8608 | [BEND_IDX( 10)] = 0x3F23, |
|
- | 8609 | [BEND_IDX( 5)] = 0x3F23, |
|
- | 8610 | [BEND_IDX( 0)] = 0x0025, |
|
- | 8611 | [BEND_IDX( -5)] = 0x0025, |
|
- | 8612 | [BEND_IDX(-10)] = 0x0125, |
|
- | 8613 | [BEND_IDX(-15)] = 0x0125, |
|
- | 8614 | [BEND_IDX(-20)] = 0x0225, |
|
- | 8615 | [BEND_IDX(-25)] = 0x0225, |
|
- | 8616 | [BEND_IDX(-30)] = 0x0325, |
|
- | 8617 | [BEND_IDX(-35)] = 0x0325, |
|
- | 8618 | [BEND_IDX(-40)] = 0x0425, |
|
- | 8619 | [BEND_IDX(-45)] = 0x0425, |
|
- | 8620 | [BEND_IDX(-50)] = 0x0525, |
|
- | 8621 | }; |
|
- | 8622 | ||
- | 8623 | /* |
|
- | 8624 | * Bend CLKOUT_DP |
|
- | 8625 | * steps -50 to 50 inclusive, in steps of 5 |
|
- | 8626 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) |
|
- | 8627 | * change in clock period = -(steps / 10) * 5.787 ps |
|
- | 8628 | */ |
|
- | 8629 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) |
|
- | 8630 | { |
|
- | 8631 | uint32_t tmp; |
|
- | 8632 | int idx = BEND_IDX(steps); |
|
- | 8633 | ||
- | 8634 | if (WARN_ON(steps % 5 != 0)) |
|
- | 8635 | return; |
|
- | 8636 | ||
- | 8637 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) |
|
- | 8638 | return; |
|
- | 8639 | ||
- | 8640 | mutex_lock(&dev_priv->sb_lock); |
|
- | 8641 | ||
- | 8642 | if (steps % 10 != 0) |
|
- | 8643 | tmp = 0xAAAAAAAB; |
|
- | 8644 | else |
|
- | 8645 | tmp = 0x00000000; |
|
- | 8646 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); |
|
- | 8647 | ||
- | 8648 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); |
|
- | 8649 | tmp &= 0xffff0000; |
|
- | 8650 | tmp |= sscdivintphase[idx]; |
|
- | 8651 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); |
|
- | 8652 | ||
- | 8653 | mutex_unlock(&dev_priv->sb_lock); |
|
- | 8654 | } |
|
- | 8655 | ||
8563 | } |
8656 | #undef BEND_IDX |
8564 | 8657 | ||
8565 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8658 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8566 | { |
8659 | { |
Line 8575... | Line 8668... | ||
8575 | default: |
8668 | default: |
8576 | break; |
8669 | break; |
8577 | } |
8670 | } |
8578 | } |
8671 | } |
Line 8579... | Line 8672... | ||
8579 | 8672 | ||
- | 8673 | if (has_vga) { |
|
8580 | if (has_vga) |
8674 | lpt_bend_clkout_dp(to_i915(dev), 0); |
8581 | lpt_enable_clkout_dp(dev, true, true); |
8675 | lpt_enable_clkout_dp(dev, true, true); |
8582 | else |
8676 | } else { |
8583 | lpt_disable_clkout_dp(dev); |
8677 | lpt_disable_clkout_dp(dev); |
- | 8678 | } |
|
Line 8584... | Line 8679... | ||
8584 | } |
8679 | } |
8585 | 8680 | ||
8586 | /* |
8681 | /* |
8587 | * Initialize reference clocks when the driver loads |
8682 | * Initialize reference clocks when the driver loads |
Line 8941... | Line 9036... | ||
8941 | struct intel_shared_dpll *pll; |
9036 | struct intel_shared_dpll *pll; |
Line 8942... | Line 9037... | ||
8942 | 9037 | ||
8943 | memset(&crtc_state->dpll_hw_state, 0, |
9038 | memset(&crtc_state->dpll_hw_state, 0, |
Line 8944... | Line 9039... | ||
8944 | sizeof(crtc_state->dpll_hw_state)); |
9039 | sizeof(crtc_state->dpll_hw_state)); |
Line 8945... | Line 9040... | ||
8945 | 9040 | ||
8946 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
9041 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
Line 8947... | Line 9042... | ||
8947 | 9042 | ||
Line 9282... | Line 9377... | ||
9282 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
9377 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
9283 | struct intel_crtc_state *pipe_config) |
9378 | struct intel_crtc_state *pipe_config) |
9284 | { |
9379 | { |
9285 | struct drm_device *dev = crtc->base.dev; |
9380 | struct drm_device *dev = crtc->base.dev; |
9286 | struct drm_i915_private *dev_priv = dev->dev_private; |
9381 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 9382 | enum intel_display_power_domain power_domain; |
|
9287 | uint32_t tmp; |
9383 | uint32_t tmp; |
- | 9384 | bool ret; |
|
Line 9288... | Line -... | ||
9288 | - | ||
9289 | if (!intel_display_power_is_enabled(dev_priv, |
9385 | |
- | 9386 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
|
9290 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9387 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Line 9291... | Line 9388... | ||
9291 | return false; |
9388 | return false; |
9292 | 9389 | ||
Line -... | Line 9390... | ||
- | 9390 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
|
9293 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9391 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9294 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9392 | |
9295 | 9393 | ret = false; |
|
Line 9296... | Line 9394... | ||
9296 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9394 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9297 | if (!(tmp & PIPECONF_ENABLE)) |
9395 | if (!(tmp & PIPECONF_ENABLE)) |
9298 | return false; |
9396 | goto out; |
9299 | 9397 | ||
Line 9356... | Line 9454... | ||
9356 | 9454 | ||
Line 9357... | Line 9455... | ||
9357 | intel_get_pipe_timings(crtc, pipe_config); |
9455 | intel_get_pipe_timings(crtc, pipe_config); |
Line 9358... | Line 9456... | ||
9358 | 9456 | ||
- | 9457 | ironlake_get_pfit_config(crtc, pipe_config); |
|
- | 9458 | ||
- | 9459 | ret = true; |
|
- | 9460 | ||
- | 9461 | out: |
|
9359 | ironlake_get_pfit_config(crtc, pipe_config); |
9462 | intel_display_power_put(dev_priv, power_domain); |
Line 9360... | Line 9463... | ||
9360 | 9463 | ||
9361 | return true; |
9464 | return ret; |
9362 | } |
9465 | } |
Line 9370... | Line 9473... | ||
9370 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
9473 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
9371 | pipe_name(crtc->pipe)); |
9474 | pipe_name(crtc->pipe)); |
Line 9372... | Line 9475... | ||
9372 | 9475 | ||
9373 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9476 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9374 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
9477 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
9375 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9478 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9376 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); |
9479 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); |
9377 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9480 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9378 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
9481 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
9379 | "CPU PWM1 enabled\n"); |
9482 | "CPU PWM1 enabled\n"); |
9380 | if (IS_HASWELL(dev)) |
9483 | if (IS_HASWELL(dev)) |
Line 9717... | Line 9820... | ||
9717 | else if (max_pixclk > 337500) |
9820 | else if (max_pixclk > 337500) |
9718 | cdclk = 450000; |
9821 | cdclk = 450000; |
9719 | else |
9822 | else |
9720 | cdclk = 337500; |
9823 | cdclk = 337500; |
Line 9721... | Line -... | ||
9721 | - | ||
9722 | /* |
- | |
9723 | * FIXME move the cdclk caclulation to |
- | |
9724 | * compute_config() so we can fail gracegully. |
- | |
9725 | */ |
9824 | |
9726 | if (cdclk > dev_priv->max_cdclk_freq) { |
9825 | if (cdclk > dev_priv->max_cdclk_freq) { |
9727 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9826 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9728 | cdclk, dev_priv->max_cdclk_freq); |
9827 | cdclk, dev_priv->max_cdclk_freq); |
9729 | cdclk = dev_priv->max_cdclk_freq; |
9828 | return -EINVAL; |
Line 9730... | Line 9829... | ||
9730 | } |
9829 | } |
Line 9731... | Line 9830... | ||
9731 | 9830 | ||
Line 9819... | Line 9918... | ||
9819 | case PORT_CLK_SEL_WRPLL2: |
9918 | case PORT_CLK_SEL_WRPLL2: |
9820 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; |
9919 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; |
9821 | break; |
9920 | break; |
9822 | case PORT_CLK_SEL_SPLL: |
9921 | case PORT_CLK_SEL_SPLL: |
9823 | pipe_config->shared_dpll = DPLL_ID_SPLL; |
9922 | pipe_config->shared_dpll = DPLL_ID_SPLL; |
- | 9923 | break; |
|
9824 | } |
9924 | } |
9825 | } |
9925 | } |
Line 9826... | Line 9926... | ||
9826 | 9926 | ||
9827 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
9927 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
Line 9835... | Line 9935... | ||
9835 | 9935 | ||
Line 9836... | Line 9936... | ||
9836 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
9936 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
Line 9837... | Line 9937... | ||
9837 | 9937 | ||
9838 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; |
9938 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; |
9839 | 9939 | ||
9840 | if (IS_SKYLAKE(dev)) |
9940 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
9841 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
9941 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
9842 | else if (IS_BROXTON(dev)) |
9942 | else if (IS_BROXTON(dev)) |
Line 9871... | Line 9971... | ||
9871 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
9971 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
9872 | struct intel_crtc_state *pipe_config) |
9972 | struct intel_crtc_state *pipe_config) |
9873 | { |
9973 | { |
9874 | struct drm_device *dev = crtc->base.dev; |
9974 | struct drm_device *dev = crtc->base.dev; |
9875 | struct drm_i915_private *dev_priv = dev->dev_private; |
9975 | struct drm_i915_private *dev_priv = dev->dev_private; |
9876 | enum intel_display_power_domain pfit_domain; |
9976 | enum intel_display_power_domain power_domain; |
- | 9977 | unsigned long power_domain_mask; |
|
9877 | uint32_t tmp; |
9978 | uint32_t tmp; |
- | 9979 | bool ret; |
|
Line -... | Line 9980... | ||
- | 9980 | ||
9878 | 9981 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
|
9879 | if (!intel_display_power_is_enabled(dev_priv, |
- | |
9880 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9982 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
- | 9983 | return false; |
|
- | 9984 | power_domain_mask = BIT(power_domain); |
|
- | 9985 | ||
Line 9881... | Line 9986... | ||
9881 | return false; |
9986 | ret = false; |
9882 | 9987 | ||
Line 9883... | Line 9988... | ||
9883 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9988 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Line 9903... | Line 10008... | ||
9903 | 10008 | ||
9904 | if (trans_edp_pipe == crtc->pipe) |
10009 | if (trans_edp_pipe == crtc->pipe) |
9905 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
10010 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
Line 9906... | Line -... | ||
9906 | } |
- | |
9907 | 10011 | } |
|
- | 10012 | ||
9908 | if (!intel_display_power_is_enabled(dev_priv, |
10013 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); |
- | 10014 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
|
Line 9909... | Line 10015... | ||
9909 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
10015 | goto out; |
9910 | return false; |
10016 | power_domain_mask |= BIT(power_domain); |
9911 | 10017 | ||
Line 9912... | Line 10018... | ||
9912 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
10018 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
Line 9913... | Line 10019... | ||
9913 | if (!(tmp & PIPECONF_ENABLE)) |
10019 | if (!(tmp & PIPECONF_ENABLE)) |
Line 9914... | Line 10020... | ||
9914 | return false; |
10020 | goto out; |
9915 | 10021 | ||
9916 | haswell_get_ddi_port_state(crtc, pipe_config); |
10022 | haswell_get_ddi_port_state(crtc, pipe_config); |
Line 9917... | Line -... | ||
9917 | - | ||
9918 | intel_get_pipe_timings(crtc, pipe_config); |
- | |
9919 | 10023 | ||
9920 | if (INTEL_INFO(dev)->gen >= 9) { |
10024 | intel_get_pipe_timings(crtc, pipe_config); |
9921 | skl_init_scalers(dev, crtc, pipe_config); |
10025 | |
9922 | } |
10026 | if (INTEL_INFO(dev)->gen >= 9) { |
Line -... | Line 10027... | ||
- | 10027 | skl_init_scalers(dev, crtc, pipe_config); |
|
9923 | 10028 | } |
|
- | 10029 | ||
9924 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10030 | if (INTEL_INFO(dev)->gen >= 9) { |
9925 | 10031 | pipe_config->scaler_state.scaler_id = -1; |
|
9926 | if (INTEL_INFO(dev)->gen >= 9) { |
10032 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); |
9927 | pipe_config->scaler_state.scaler_id = -1; |
10033 | } |
9928 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); |
10034 | |
Line 9944... | Line 10050... | ||
9944 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; |
10050 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; |
9945 | } else { |
10051 | } else { |
9946 | pipe_config->pixel_multiplier = 1; |
10052 | pipe_config->pixel_multiplier = 1; |
9947 | } |
10053 | } |
Line 9948... | Line 10054... | ||
9948 | 10054 | ||
- | 10055 | ret = true; |
|
- | 10056 | ||
- | 10057 | out: |
|
- | 10058 | for_each_power_domain(power_domain, power_domain_mask) |
|
- | 10059 | intel_display_power_put(dev_priv, power_domain); |
|
- | 10060 | ||
9949 | return true; |
10061 | return ret; |
Line 9950... | Line 10062... | ||
9950 | } |
10062 | } |
9951 | 10063 | ||
9952 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
10064 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
Line 10176... | Line 10288... | ||
10176 | { |
10288 | { |
10177 | struct intel_framebuffer *intel_fb; |
10289 | struct intel_framebuffer *intel_fb; |
10178 | int ret; |
10290 | int ret; |
Line 10179... | Line 10291... | ||
10179 | 10291 | ||
10180 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
10292 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
10181 | if (!intel_fb) { |
- | |
10182 | drm_gem_object_unreference(&obj->base); |
10293 | if (!intel_fb) |
10183 | return ERR_PTR(-ENOMEM); |
- | |
Line 10184... | Line 10294... | ||
10184 | } |
10294 | return ERR_PTR(-ENOMEM); |
10185 | 10295 | ||
10186 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
10296 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
Line 10187... | Line 10297... | ||
10187 | if (ret) |
10297 | if (ret) |
- | 10298 | goto err; |
|
10188 | goto err; |
10299 | |
10189 | - | ||
10190 | return &intel_fb->base; |
10300 | return &intel_fb->base; |
10191 | err: |
- | |
10192 | drm_gem_object_unreference(&obj->base); |
10301 | |
10193 | kfree(intel_fb); |
10302 | err: |
Line 10194... | Line 10303... | ||
10194 | 10303 | kfree(intel_fb); |
|
10195 | return ERR_PTR(ret); |
10304 | return ERR_PTR(ret); |
Line 10229... | Line 10338... | ||
10229 | static struct drm_framebuffer * |
10338 | static struct drm_framebuffer * |
10230 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
10339 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
10231 | struct drm_display_mode *mode, |
10340 | struct drm_display_mode *mode, |
10232 | int depth, int bpp) |
10341 | int depth, int bpp) |
10233 | { |
10342 | { |
- | 10343 | struct drm_framebuffer *fb; |
|
10234 | struct drm_i915_gem_object *obj; |
10344 | struct drm_i915_gem_object *obj; |
10235 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
10345 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
Line 10236... | Line 10346... | ||
10236 | 10346 | ||
10237 | obj = i915_gem_alloc_object(dev, |
10347 | obj = i915_gem_alloc_object(dev, |
Line 10243... | Line 10353... | ||
10243 | mode_cmd.height = mode->vdisplay; |
10353 | mode_cmd.height = mode->vdisplay; |
10244 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10354 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10245 | bpp); |
10355 | bpp); |
10246 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
10356 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
Line 10247... | Line 10357... | ||
10247 | 10357 | ||
- | 10358 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
|
- | 10359 | if (IS_ERR(fb)) |
|
- | 10360 | drm_gem_object_unreference_unlocked(&obj->base); |
|
- | 10361 | ||
10248 | return intel_framebuffer_create(dev, &mode_cmd, obj); |
10362 | return fb; |
Line 10249... | Line 10363... | ||
10249 | } |
10363 | } |
10250 | 10364 | ||
10251 | static struct drm_framebuffer * |
10365 | static struct drm_framebuffer * |
Line 10778... | Line 10892... | ||
10778 | work = intel_crtc->unpin_work; |
10892 | work = intel_crtc->unpin_work; |
10779 | intel_crtc->unpin_work = NULL; |
10893 | intel_crtc->unpin_work = NULL; |
10780 | spin_unlock_irq(&dev->event_lock); |
10894 | spin_unlock_irq(&dev->event_lock); |
Line 10781... | Line 10895... | ||
10781 | 10895 | ||
10782 | if (work) { |
10896 | if (work) { |
10783 | cancel_work_sync(&work->work); |
10897 | // cancel_work_sync(&work->work); |
10784 | kfree(work); |
10898 | kfree(work); |
Line 10785... | Line 10899... | ||
10785 | } |
10899 | } |
Line 11146... | Line 11260... | ||
11146 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
11260 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
11147 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
11261 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
11148 | */ |
11262 | */ |
11149 | if (ring->id == RCS) { |
11263 | if (ring->id == RCS) { |
11150 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
11264 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
11151 | intel_ring_emit(ring, DERRMR); |
11265 | intel_ring_emit_reg(ring, DERRMR); |
11152 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11266 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11153 | DERRMR_PIPEB_PRI_FLIP_DONE | |
11267 | DERRMR_PIPEB_PRI_FLIP_DONE | |
11154 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
11268 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
11155 | if (IS_GEN8(dev)) |
11269 | if (IS_GEN8(dev)) |
11156 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
11270 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
11157 | MI_SRM_LRM_GLOBAL_GTT); |
11271 | MI_SRM_LRM_GLOBAL_GTT); |
11158 | else |
11272 | else |
11159 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
11273 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
11160 | MI_SRM_LRM_GLOBAL_GTT); |
11274 | MI_SRM_LRM_GLOBAL_GTT); |
11161 | intel_ring_emit(ring, DERRMR); |
11275 | intel_ring_emit_reg(ring, DERRMR); |
11162 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
11276 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
11163 | if (IS_GEN8(dev)) { |
11277 | if (IS_GEN8(dev)) { |
11164 | intel_ring_emit(ring, 0); |
11278 | intel_ring_emit(ring, 0); |
11165 | intel_ring_emit(ring, MI_NOOP); |
11279 | intel_ring_emit(ring, MI_NOOP); |
11166 | } |
11280 | } |
Line 11196... | Line 11310... | ||
11196 | return false; |
11310 | return false; |
11197 | else if (i915.use_mmio_flip > 0) |
11311 | else if (i915.use_mmio_flip > 0) |
11198 | return true; |
11312 | return true; |
11199 | else if (i915.enable_execlists) |
11313 | else if (i915.enable_execlists) |
11200 | return true; |
11314 | return true; |
- | 11315 | // else if (obj->base.dma_buf && |
|
- | 11316 | // !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, |
|
- | 11317 | // false)) |
|
- | 11318 | // return true; |
|
11201 | else |
11319 | else |
11202 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
11320 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
11203 | } |
11321 | } |
Line 11204... | Line 11322... | ||
11204 | 11322 | ||
- | 11323 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
|
11205 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
11324 | unsigned int rotation, |
11206 | struct intel_unpin_work *work) |
11325 | struct intel_unpin_work *work) |
11207 | { |
11326 | { |
11208 | struct drm_device *dev = intel_crtc->base.dev; |
11327 | struct drm_device *dev = intel_crtc->base.dev; |
11209 | struct drm_i915_private *dev_priv = dev->dev_private; |
11328 | struct drm_i915_private *dev_priv = dev->dev_private; |
11210 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
11329 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
11211 | const enum pipe pipe = intel_crtc->pipe; |
11330 | const enum pipe pipe = intel_crtc->pipe; |
Line 11212... | Line 11331... | ||
11212 | u32 ctl, stride; |
11331 | u32 ctl, stride, tile_height; |
11213 | 11332 | ||
11214 | ctl = I915_READ(PLANE_CTL(pipe, 0)); |
11333 | ctl = I915_READ(PLANE_CTL(pipe, 0)); |
11215 | ctl &= ~PLANE_CTL_TILED_MASK; |
11334 | ctl &= ~PLANE_CTL_TILED_MASK; |
Line 11231... | Line 11350... | ||
11231 | 11350 | ||
11232 | /* |
11351 | /* |
11233 | * The stride is either expressed as a multiple of 64 bytes chunks for |
11352 | * The stride is either expressed as a multiple of 64 bytes chunks for |
11234 | * linear buffers or in number of tiles for tiled buffers. |
11353 | * linear buffers or in number of tiles for tiled buffers. |
- | 11354 | */ |
|
- | 11355 | if (intel_rotation_90_or_270(rotation)) { |
|
- | 11356 | /* stride = Surface height in tiles */ |
|
- | 11357 | tile_height = intel_tile_height(dev, fb->pixel_format, |
|
- | 11358 | fb->modifier[0], 0); |
|
- | 11359 | stride = DIV_ROUND_UP(fb->height, tile_height); |
|
11235 | */ |
11360 | } else { |
11236 | stride = fb->pitches[0] / |
11361 | stride = fb->pitches[0] / |
11237 | intel_fb_stride_alignment(dev, fb->modifier[0], |
11362 | intel_fb_stride_alignment(dev, fb->modifier[0], |
- | 11363 | fb->pixel_format); |
|
Line 11238... | Line 11364... | ||
11238 | fb->pixel_format); |
11364 | } |
11239 | 11365 | ||
11240 | /* |
11366 | /* |
11241 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on |
11367 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on |
Line 11254... | Line 11380... | ||
11254 | struct drm_device *dev = intel_crtc->base.dev; |
11380 | struct drm_device *dev = intel_crtc->base.dev; |
11255 | struct drm_i915_private *dev_priv = dev->dev_private; |
11381 | struct drm_i915_private *dev_priv = dev->dev_private; |
11256 | struct intel_framebuffer *intel_fb = |
11382 | struct intel_framebuffer *intel_fb = |
11257 | to_intel_framebuffer(intel_crtc->base.primary->fb); |
11383 | to_intel_framebuffer(intel_crtc->base.primary->fb); |
11258 | struct drm_i915_gem_object *obj = intel_fb->obj; |
11384 | struct drm_i915_gem_object *obj = intel_fb->obj; |
- | 11385 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
|
11259 | u32 dspcntr; |
11386 | u32 dspcntr; |
11260 | u32 reg; |
- | |
Line 11261... | Line -... | ||
11261 | - | ||
11262 | reg = DSPCNTR(intel_crtc->plane); |
11387 | |
Line 11263... | Line 11388... | ||
11263 | dspcntr = I915_READ(reg); |
11388 | dspcntr = I915_READ(reg); |
11264 | 11389 | ||
11265 | if (obj->tiling_mode != I915_TILING_NONE) |
11390 | if (obj->tiling_mode != I915_TILING_NONE) |
Line 11291... | Line 11416... | ||
11291 | intel_mark_page_flip_active(work); |
11416 | intel_mark_page_flip_active(work); |
Line 11292... | Line 11417... | ||
11292 | 11417 | ||
Line 11293... | Line 11418... | ||
11293 | intel_pipe_update_start(crtc); |
11418 | intel_pipe_update_start(crtc); |
11294 | 11419 | ||
11295 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
11420 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
11296 | skl_do_mmio_flip(crtc, work); |
11421 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
11297 | else |
11422 | else |
Line 11298... | Line 11423... | ||
11298 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ |
11423 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ |
Line 11303... | Line 11428... | ||
11303 | 11428 | ||
11304 | static void intel_mmio_flip_work_func(struct work_struct *work) |
11429 | static void intel_mmio_flip_work_func(struct work_struct *work) |
11305 | { |
11430 | { |
11306 | struct intel_mmio_flip *mmio_flip = |
11431 | struct intel_mmio_flip *mmio_flip = |
- | 11432 | container_of(work, struct intel_mmio_flip, work); |
|
- | 11433 | struct intel_framebuffer *intel_fb = |
|
- | 11434 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); |
|
Line 11307... | Line 11435... | ||
11307 | container_of(work, struct intel_mmio_flip, work); |
11435 | struct drm_i915_gem_object *obj = intel_fb->obj; |
11308 | 11436 | ||
11309 | if (mmio_flip->req) { |
11437 | if (mmio_flip->req) { |
11310 | WARN_ON(__i915_wait_request(mmio_flip->req, |
11438 | WARN_ON(__i915_wait_request(mmio_flip->req, |
11311 | mmio_flip->crtc->reset_counter, |
11439 | mmio_flip->crtc->reset_counter, |
11312 | false, NULL, |
11440 | false, NULL, |
11313 | &mmio_flip->i915->rps.mmioflips)); |
11441 | &mmio_flip->i915->rps.mmioflips)); |
Line -... | Line 11442... | ||
- | 11442 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
|
- | 11443 | } |
|
- | 11444 | ||
- | 11445 | /* For framebuffer backed by dmabuf, wait for fence */ |
|
- | 11446 | // if (obj->base.dma_buf) |
|
- | 11447 | // WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, |
|
11314 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11448 | // false, false, |
11315 | } |
11449 | // MAX_SCHEDULE_TIMEOUT) < 0); |
11316 | 11450 | ||
Line 11317... | Line 11451... | ||
11317 | intel_do_mmio_flip(mmio_flip); |
11451 | intel_do_mmio_flip(mmio_flip); |
11318 | kfree(mmio_flip); |
11452 | kfree(mmio_flip); |
11319 | } |
- | |
11320 | 11453 | } |
|
11321 | static int intel_queue_mmio_flip(struct drm_device *dev, |
- | |
11322 | struct drm_crtc *crtc, |
- | |
11323 | struct drm_framebuffer *fb, |
11454 | |
11324 | struct drm_i915_gem_object *obj, |
11455 | static int intel_queue_mmio_flip(struct drm_device *dev, |
Line 11325... | Line 11456... | ||
11325 | struct intel_engine_cs *ring, |
11456 | struct drm_crtc *crtc, |
11326 | uint32_t flags) |
11457 | struct drm_i915_gem_object *obj) |
11327 | { |
11458 | { |
Line 11328... | Line 11459... | ||
11328 | struct intel_mmio_flip *mmio_flip; |
11459 | struct intel_mmio_flip *mmio_flip; |
11329 | 11460 | ||
11330 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); |
11461 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); |
- | 11462 | if (mmio_flip == NULL) |
|
Line 11331... | Line 11463... | ||
11331 | if (mmio_flip == NULL) |
11463 | return -ENOMEM; |
11332 | return -ENOMEM; |
11464 | |
Line 11333... | Line 11465... | ||
11333 | 11465 | mmio_flip->i915 = to_i915(dev); |
|
Line 11398... | Line 11530... | ||
11398 | struct drm_i915_private *dev_priv = dev->dev_private; |
11530 | struct drm_i915_private *dev_priv = dev->dev_private; |
11399 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11531 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11400 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11401 | struct intel_unpin_work *work; |
11533 | struct intel_unpin_work *work; |
Line -... | Line 11534... | ||
- | 11534 | ||
- | 11535 | WARN_ON(!in_interrupt()); |
|
11402 | 11536 | ||
11403 | if (crtc == NULL) |
11537 | if (crtc == NULL) |
Line 11404... | Line 11538... | ||
11404 | return; |
11538 | return; |
11405 | 11539 | ||
Line 11513... | Line 11647... | ||
11513 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
11647 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Line 11514... | Line 11648... | ||
11514 | 11648 | ||
11515 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
11649 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
Line 11516... | Line 11650... | ||
11516 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
11650 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
11517 | 11651 | ||
11518 | if (IS_VALLEYVIEW(dev)) { |
11652 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
11519 | ring = &dev_priv->ring[BCS]; |
11653 | ring = &dev_priv->ring[BCS]; |
11520 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
11654 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
11521 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11655 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
Line 11535... | Line 11669... | ||
11535 | /* When using CS flips, we want to emit semaphores between rings. |
11669 | /* When using CS flips, we want to emit semaphores between rings. |
11536 | * However, when using mmio flips we will create a task to do the |
11670 | * However, when using mmio flips we will create a task to do the |
11537 | * synchronisation, so all we want here is to pin the framebuffer |
11671 | * synchronisation, so all we want here is to pin the framebuffer |
11538 | * into the display plane and skip any waits. |
11672 | * into the display plane and skip any waits. |
11539 | */ |
11673 | */ |
- | 11674 | if (!mmio_flip) { |
|
- | 11675 | ret = i915_gem_object_sync(obj, ring, &request); |
|
- | 11676 | if (ret) |
|
- | 11677 | goto cleanup_pending; |
|
- | 11678 | } |
|
- | 11679 | ||
11540 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
11680 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
11541 | crtc->primary->state, |
11681 | crtc->primary->state); |
11542 | mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request); |
- | |
11543 | if (ret) |
11682 | if (ret) |
11544 | goto cleanup_pending; |
11683 | goto cleanup_pending; |
Line 11545... | Line 11684... | ||
11545 | 11684 | ||
11546 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11685 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11547 | obj, 0); |
11686 | obj, 0); |
Line 11548... | Line 11687... | ||
11548 | work->gtt_offset += intel_crtc->dspaddr_offset; |
11687 | work->gtt_offset += intel_crtc->dspaddr_offset; |
11549 | 11688 | ||
11550 | if (mmio_flip) { |
- | |
11551 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
11689 | if (mmio_flip) { |
11552 | page_flip_flags); |
11690 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
Line 11553... | Line 11691... | ||
11553 | if (ret) |
11691 | if (ret) |
11554 | goto cleanup_unpin; |
11692 | goto cleanup_unpin; |
Line 11578... | Line 11716... | ||
11578 | 11716 | ||
11579 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
11717 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
11580 | to_intel_plane(primary)->frontbuffer_bit); |
11718 | to_intel_plane(primary)->frontbuffer_bit); |
Line 11581... | Line 11719... | ||
11581 | mutex_unlock(&dev->struct_mutex); |
11719 | mutex_unlock(&dev->struct_mutex); |
11582 | 11720 | ||
11583 | intel_fbc_disable_crtc(intel_crtc); |
11721 | intel_fbc_deactivate(intel_crtc); |
Line 11584... | Line 11722... | ||
11584 | intel_frontbuffer_flip_prepare(dev, |
11722 | intel_frontbuffer_flip_prepare(dev, |
Line 11661... | Line 11799... | ||
11661 | * Returns true or false. |
11799 | * Returns true or false. |
11662 | */ |
11800 | */ |
11663 | static bool intel_wm_need_update(struct drm_plane *plane, |
11801 | static bool intel_wm_need_update(struct drm_plane *plane, |
11664 | struct drm_plane_state *state) |
11802 | struct drm_plane_state *state) |
11665 | { |
11803 | { |
11666 | /* Update watermarks on tiling changes. */ |
11804 | struct intel_plane_state *new = to_intel_plane_state(state); |
11667 | if (!plane->state->fb || !state->fb || |
11805 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); |
- | 11806 | ||
11668 | plane->state->fb->modifier[0] != state->fb->modifier[0] || |
11807 | /* Update watermarks on tiling or size changes. */ |
11669 | plane->state->rotation != state->rotation) |
11808 | if (new->visible != cur->visible) |
11670 | return true; |
11809 | return true; |
Line 11671... | Line 11810... | ||
11671 | 11810 | ||
- | 11811 | if (!cur->base.fb || !new->base.fb) |
|
- | 11812 | return false; |
|
- | 11813 | ||
- | 11814 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || |
|
- | 11815 | cur->base.rotation != new->base.rotation || |
|
- | 11816 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
|
- | 11817 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || |
|
- | 11818 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || |
|
11672 | if (plane->state->crtc_w != state->crtc_w) |
11819 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) |
Line 11673... | Line 11820... | ||
11673 | return true; |
11820 | return true; |
11674 | 11821 | ||
Line -... | Line 11822... | ||
- | 11822 | return false; |
|
- | 11823 | } |
|
- | 11824 | ||
- | 11825 | static bool needs_scaling(struct intel_plane_state *state) |
|
- | 11826 | { |
|
- | 11827 | int src_w = drm_rect_width(&state->src) >> 16; |
|
- | 11828 | int src_h = drm_rect_height(&state->src) >> 16; |
|
- | 11829 | int dst_w = drm_rect_width(&state->dst); |
|
- | 11830 | int dst_h = drm_rect_height(&state->dst); |
|
- | 11831 | ||
11675 | return false; |
11832 | return (src_w != dst_w || src_h != dst_h); |
11676 | } |
11833 | } |
11677 | 11834 | ||
- | 11835 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
|
11678 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11836 | struct drm_plane_state *plane_state) |
11679 | struct drm_plane_state *plane_state) |
11837 | { |
11680 | { |
11838 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
11681 | struct drm_crtc *crtc = crtc_state->crtc; |
11839 | struct drm_crtc *crtc = crtc_state->crtc; |
11682 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11840 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 11688... | Line 11846... | ||
11688 | int idx = intel_crtc->base.base.id, ret; |
11846 | int idx = intel_crtc->base.base.id, ret; |
11689 | int i = drm_plane_index(plane); |
11847 | int i = drm_plane_index(plane); |
11690 | bool mode_changed = needs_modeset(crtc_state); |
11848 | bool mode_changed = needs_modeset(crtc_state); |
11691 | bool was_crtc_enabled = crtc->state->active; |
11849 | bool was_crtc_enabled = crtc->state->active; |
11692 | bool is_crtc_enabled = crtc_state->active; |
11850 | bool is_crtc_enabled = crtc_state->active; |
11693 | - | ||
11694 | bool turn_off, turn_on, visible, was_visible; |
11851 | bool turn_off, turn_on, visible, was_visible; |
11695 | struct drm_framebuffer *fb = plane_state->fb; |
11852 | struct drm_framebuffer *fb = plane_state->fb; |
Line 11696... | Line 11853... | ||
11696 | 11853 | ||
11697 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && |
11854 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && |
Line 11701... | Line 11858... | ||
11701 | to_intel_plane_state(plane_state)); |
11858 | to_intel_plane_state(plane_state)); |
11702 | if (ret) |
11859 | if (ret) |
11703 | return ret; |
11860 | return ret; |
11704 | } |
11861 | } |
Line 11705... | Line -... | ||
11705 | - | ||
11706 | /* |
- | |
11707 | * Disabling a plane is always okay; we just need to update |
- | |
11708 | * fb tracking in a special way since cleanup_fb() won't |
- | |
11709 | * get called by the plane helpers. |
- | |
11710 | */ |
- | |
11711 | if (old_plane_state->base.fb && !fb) |
- | |
11712 | intel_crtc->atomic.disabled_planes |= 1 << i; |
- | |
11713 | 11862 | ||
11714 | was_visible = old_plane_state->visible; |
11863 | was_visible = old_plane_state->visible; |
Line 11715... | Line 11864... | ||
11715 | visible = to_intel_plane_state(plane_state)->visible; |
11864 | visible = to_intel_plane_state(plane_state)->visible; |
11716 | 11865 | ||
Line 11732... | Line 11881... | ||
11732 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", |
11881 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", |
11733 | plane->base.id, was_visible, visible, |
11882 | plane->base.id, was_visible, visible, |
11734 | turn_off, turn_on, mode_changed); |
11883 | turn_off, turn_on, mode_changed); |
Line 11735... | Line 11884... | ||
11735 | 11884 | ||
11736 | if (turn_on) { |
11885 | if (turn_on) { |
- | 11886 | pipe_config->update_wm_pre = true; |
|
11737 | intel_crtc->atomic.update_wm_pre = true; |
11887 | |
11738 | /* must disable cxsr around plane enable/disable */ |
11888 | /* must disable cxsr around plane enable/disable */ |
11739 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
11889 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
11740 | intel_crtc->atomic.disable_cxsr = true; |
- | |
11741 | /* to potentially re-enable cxsr */ |
- | |
11742 | intel_crtc->atomic.wait_vblank = true; |
- | |
11743 | intel_crtc->atomic.update_wm_post = true; |
- | |
11744 | } |
11890 | pipe_config->disable_cxsr = true; |
11745 | } else if (turn_off) { |
11891 | } else if (turn_off) { |
- | 11892 | pipe_config->update_wm_post = true; |
|
11746 | intel_crtc->atomic.update_wm_post = true; |
11893 | |
11747 | /* must disable cxsr around plane enable/disable */ |
11894 | /* must disable cxsr around plane enable/disable */ |
11748 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
11895 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
11749 | if (is_crtc_enabled) |
11896 | if (is_crtc_enabled) |
11750 | intel_crtc->atomic.wait_vblank = true; |
11897 | intel_crtc->atomic.wait_vblank = true; |
11751 | intel_crtc->atomic.disable_cxsr = true; |
11898 | pipe_config->disable_cxsr = true; |
11752 | } |
11899 | } |
- | 11900 | } else if (intel_wm_need_update(plane, plane_state)) { |
|
11753 | } else if (intel_wm_need_update(plane, plane_state)) { |
11901 | /* FIXME bollocks */ |
- | 11902 | pipe_config->update_wm_pre = true; |
|
11754 | intel_crtc->atomic.update_wm_pre = true; |
11903 | pipe_config->update_wm_post = true; |
Line 11755... | Line 11904... | ||
11755 | } |
11904 | } |
11756 | 11905 | ||
11757 | if (visible || was_visible) |
11906 | if (visible || was_visible) |
Line 11758... | Line 11907... | ||
11758 | intel_crtc->atomic.fb_bits |= |
11907 | intel_crtc->atomic.fb_bits |= |
11759 | to_intel_plane(plane)->frontbuffer_bit; |
11908 | to_intel_plane(plane)->frontbuffer_bit; |
11760 | - | ||
11761 | switch (plane->type) { |
11909 | |
11762 | case DRM_PLANE_TYPE_PRIMARY: |
11910 | switch (plane->type) { |
Line 11763... | Line 11911... | ||
11763 | intel_crtc->atomic.wait_for_flips = true; |
11911 | case DRM_PLANE_TYPE_PRIMARY: |
11764 | intel_crtc->atomic.pre_disable_primary = turn_off; |
11912 | intel_crtc->atomic.pre_disable_primary = turn_off; |
Line 11806... | Line 11954... | ||
11806 | intel_crtc->atomic.update_fbc |= visible || mode_changed; |
11954 | intel_crtc->atomic.update_fbc |= visible || mode_changed; |
11807 | break; |
11955 | break; |
11808 | case DRM_PLANE_TYPE_CURSOR: |
11956 | case DRM_PLANE_TYPE_CURSOR: |
11809 | break; |
11957 | break; |
11810 | case DRM_PLANE_TYPE_OVERLAY: |
11958 | case DRM_PLANE_TYPE_OVERLAY: |
- | 11959 | /* |
|
- | 11960 | * WaCxSRDisabledForSpriteScaling:ivb |
|
- | 11961 | * |
|
- | 11962 | * cstate->update_wm was already set above, so this flag will |
|
- | 11963 | * take effect when we commit and program watermarks. |
|
- | 11964 | */ |
|
- | 11965 | if (IS_IVYBRIDGE(dev) && |
|
- | 11966 | needs_scaling(to_intel_plane_state(plane_state)) && |
|
- | 11967 | !needs_scaling(old_plane_state)) { |
|
- | 11968 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; |
|
11811 | if (turn_off && !mode_changed) { |
11969 | } else if (turn_off && !mode_changed) { |
11812 | intel_crtc->atomic.wait_vblank = true; |
11970 | intel_crtc->atomic.wait_vblank = true; |
11813 | intel_crtc->atomic.update_sprite_watermarks |= |
11971 | intel_crtc->atomic.update_sprite_watermarks |= |
11814 | 1 << i; |
11972 | 1 << i; |
11815 | } |
11973 | } |
- | 11974 | ||
- | 11975 | break; |
|
11816 | } |
11976 | } |
11817 | return 0; |
11977 | return 0; |
11818 | } |
11978 | } |
Line 11819... | Line 11979... | ||
11819 | 11979 | ||
Line 11883... | Line 12043... | ||
11883 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
12043 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
11884 | return -EINVAL; |
12044 | return -EINVAL; |
11885 | } |
12045 | } |
Line 11886... | Line 12046... | ||
11886 | 12046 | ||
11887 | if (mode_changed && !crtc_state->active) |
12047 | if (mode_changed && !crtc_state->active) |
Line 11888... | Line 12048... | ||
11888 | intel_crtc->atomic.update_wm_post = true; |
12048 | pipe_config->update_wm_post = true; |
11889 | 12049 | ||
11890 | if (mode_changed && crtc_state->enable && |
12050 | if (mode_changed && crtc_state->enable && |
11891 | dev_priv->display.crtc_compute_clock && |
12051 | dev_priv->display.crtc_compute_clock && |
Line 11895... | Line 12055... | ||
11895 | if (ret) |
12055 | if (ret) |
11896 | return ret; |
12056 | return ret; |
11897 | } |
12057 | } |
Line 11898... | Line 12058... | ||
11898 | 12058 | ||
- | 12059 | ret = 0; |
|
- | 12060 | if (dev_priv->display.compute_pipe_wm) { |
|
- | 12061 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); |
|
- | 12062 | if (ret) |
|
- | 12063 | return ret; |
|
- | 12064 | } |
|
11899 | ret = 0; |
12065 | |
11900 | if (INTEL_INFO(dev)->gen >= 9) { |
12066 | if (INTEL_INFO(dev)->gen >= 9) { |
11901 | if (mode_changed) |
12067 | if (mode_changed) |
Line 11902... | Line 12068... | ||
11902 | ret = skl_update_scaler_crtc(pipe_config); |
12068 | ret = skl_update_scaler_crtc(pipe_config); |
Line 11950... | Line 12116... | ||
11950 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
12116 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
11951 | bpp, connector->base.display_info.bpc*3); |
12117 | bpp, connector->base.display_info.bpc*3); |
11952 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
12118 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
11953 | } |
12119 | } |
Line 11954... | Line 12120... | ||
11954 | 12120 | ||
11955 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
12121 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
- | 12122 | if (connector->base.display_info.bpc == 0) { |
|
- | 12123 | int type = connector->base.connector_type; |
|
- | 12124 | int clamp_bpp = 24; |
|
- | 12125 | ||
- | 12126 | /* Fall back to 18 bpp when DP sink capability is unknown. */ |
|
- | 12127 | if (type == DRM_MODE_CONNECTOR_DisplayPort || |
|
- | 12128 | type == DRM_MODE_CONNECTOR_eDP) |
|
- | 12129 | clamp_bpp = 18; |
|
- | 12130 | ||
11956 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
12131 | if (bpp > clamp_bpp) { |
11957 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
12132 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", |
11958 | bpp); |
12133 | bpp, clamp_bpp); |
- | 12134 | pipe_config->pipe_bpp = clamp_bpp; |
|
11959 | pipe_config->pipe_bpp = 24; |
12135 | } |
11960 | } |
12136 | } |
Line 11961... | Line 12137... | ||
11961 | } |
12137 | } |
11962 | 12138 | ||
Line 11968... | Line 12144... | ||
11968 | struct drm_atomic_state *state; |
12144 | struct drm_atomic_state *state; |
11969 | struct drm_connector *connector; |
12145 | struct drm_connector *connector; |
11970 | struct drm_connector_state *connector_state; |
12146 | struct drm_connector_state *connector_state; |
11971 | int bpp, i; |
12147 | int bpp, i; |
Line 11972... | Line 12148... | ||
11972 | 12148 | ||
11973 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
12149 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
11974 | bpp = 10*3; |
12150 | bpp = 10*3; |
11975 | else if (INTEL_INFO(dev)->gen >= 5) |
12151 | else if (INTEL_INFO(dev)->gen >= 5) |
11976 | bpp = 12*3; |
12152 | bpp = 12*3; |
11977 | else |
12153 | else |
Line 12084... | Line 12260... | ||
12084 | pipe_config->dpll_hw_state.pll6, |
12260 | pipe_config->dpll_hw_state.pll6, |
12085 | pipe_config->dpll_hw_state.pll8, |
12261 | pipe_config->dpll_hw_state.pll8, |
12086 | pipe_config->dpll_hw_state.pll9, |
12262 | pipe_config->dpll_hw_state.pll9, |
12087 | pipe_config->dpll_hw_state.pll10, |
12263 | pipe_config->dpll_hw_state.pll10, |
12088 | pipe_config->dpll_hw_state.pcsdw12); |
12264 | pipe_config->dpll_hw_state.pcsdw12); |
12089 | } else if (IS_SKYLAKE(dev)) { |
12265 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
12090 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12266 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12091 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", |
12267 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", |
12092 | pipe_config->ddi_pll_sel, |
12268 | pipe_config->ddi_pll_sel, |
12093 | pipe_config->dpll_hw_state.ctrl1, |
12269 | pipe_config->dpll_hw_state.ctrl1, |
12094 | pipe_config->dpll_hw_state.cfgcr1, |
12270 | pipe_config->dpll_hw_state.cfgcr1, |
Line 12342... | Line 12518... | ||
12342 | /* Update hwmode for vblank functions */ |
12518 | /* Update hwmode for vblank functions */ |
12343 | if (crtc->state->active) |
12519 | if (crtc->state->active) |
12344 | crtc->hwmode = crtc->state->adjusted_mode; |
12520 | crtc->hwmode = crtc->state->adjusted_mode; |
12345 | else |
12521 | else |
12346 | crtc->hwmode.crtc_clock = 0; |
12522 | crtc->hwmode.crtc_clock = 0; |
- | 12523 | ||
- | 12524 | /* |
|
- | 12525 | * Update legacy state to satisfy fbc code. This can |
|
- | 12526 | * be removed when fbc uses the atomic state. |
|
- | 12527 | */ |
|
- | 12528 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { |
|
- | 12529 | struct drm_plane_state *plane_state = crtc->primary->state; |
|
- | 12530 | ||
- | 12531 | crtc->primary->fb = plane_state->fb; |
|
- | 12532 | crtc->x = plane_state->src_x >> 16; |
|
- | 12533 | crtc->y = plane_state->src_y >> 16; |
|
- | 12534 | } |
|
12347 | } |
12535 | } |
12348 | } |
12536 | } |
Line 12349... | Line 12537... | ||
12349 | 12537 | ||
12350 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
12538 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
Line 12367... | Line 12555... | ||
12367 | 12555 | ||
12368 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12556 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12369 | list_for_each_entry((intel_crtc), \ |
12557 | list_for_each_entry((intel_crtc), \ |
12370 | &(dev)->mode_config.crtc_list, \ |
12558 | &(dev)->mode_config.crtc_list, \ |
12371 | base.head) \ |
12559 | base.head) \ |
Line 12372... | Line 12560... | ||
12372 | if (mask & (1 <<(intel_crtc)->pipe)) |
12560 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
12373 | 12561 | ||
12374 | static bool |
12562 | static bool |
12375 | intel_compare_m_n(unsigned int m, unsigned int n, |
12563 | intel_compare_m_n(unsigned int m, unsigned int n, |
Line 12551... | Line 12739... | ||
12551 | if (current_config->has_drrs) |
12739 | if (current_config->has_drrs) |
12552 | PIPE_CONF_CHECK_M_N(dp_m2_n2); |
12740 | PIPE_CONF_CHECK_M_N(dp_m2_n2); |
12553 | } else |
12741 | } else |
12554 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); |
12742 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); |
Line -... | Line 12743... | ||
- | 12743 | ||
- | 12744 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
|
12555 | 12745 | ||
12556 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12746 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12557 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); |
12747 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); |
12558 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); |
12748 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); |
12559 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); |
12749 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); |
Line 12568... | Line 12758... | ||
12568 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); |
12758 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); |
Line 12569... | Line 12759... | ||
12569 | 12759 | ||
12570 | PIPE_CONF_CHECK_I(pixel_multiplier); |
12760 | PIPE_CONF_CHECK_I(pixel_multiplier); |
12571 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
12761 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
12572 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
12762 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
12573 | IS_VALLEYVIEW(dev)) |
12763 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
12574 | PIPE_CONF_CHECK_I(limited_color_range); |
12764 | PIPE_CONF_CHECK_I(limited_color_range); |
Line 12575... | Line 12765... | ||
12575 | PIPE_CONF_CHECK_I(has_infoframe); |
12765 | PIPE_CONF_CHECK_I(has_infoframe); |
Line 13105... | Line 13295... | ||
13105 | return haswell_mode_set_planes_workaround(state); |
13295 | return haswell_mode_set_planes_workaround(state); |
Line 13106... | Line 13296... | ||
13106 | 13296 | ||
13107 | return 0; |
13297 | return 0; |
Line -... | Line 13298... | ||
- | 13298 | } |
|
- | 13299 | ||
- | 13300 | /* |
|
- | 13301 | * Handle calculation of various watermark data at the end of the atomic check |
|
- | 13302 | * phase. The code here should be run after the per-crtc and per-plane 'check' |
|
- | 13303 | * handlers to ensure that all derived state has been updated. |
|
- | 13304 | */ |
|
- | 13305 | static void calc_watermark_data(struct drm_atomic_state *state) |
|
- | 13306 | { |
|
- | 13307 | struct drm_device *dev = state->dev; |
|
- | 13308 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
|
- | 13309 | struct drm_crtc *crtc; |
|
- | 13310 | struct drm_crtc_state *cstate; |
|
- | 13311 | struct drm_plane *plane; |
|
- | 13312 | struct drm_plane_state *pstate; |
|
- | 13313 | ||
- | 13314 | /* |
|
- | 13315 | * Calculate watermark configuration details now that derived |
|
- | 13316 | * plane/crtc state is all properly updated. |
|
- | 13317 | */ |
|
- | 13318 | drm_for_each_crtc(crtc, dev) { |
|
- | 13319 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: |
|
- | 13320 | crtc->state; |
|
- | 13321 | ||
- | 13322 | if (cstate->active) |
|
- | 13323 | intel_state->wm_config.num_pipes_active++; |
|
- | 13324 | } |
|
- | 13325 | drm_for_each_legacy_plane(plane, dev) { |
|
- | 13326 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: |
|
- | 13327 | plane->state; |
|
- | 13328 | ||
- | 13329 | if (!to_intel_plane_state(pstate)->visible) |
|
- | 13330 | continue; |
|
- | 13331 | ||
- | 13332 | intel_state->wm_config.sprites_enabled = true; |
|
- | 13333 | if (pstate->crtc_w != pstate->src_w >> 16 || |
|
- | 13334 | pstate->crtc_h != pstate->src_h >> 16) |
|
- | 13335 | intel_state->wm_config.sprites_scaled = true; |
|
- | 13336 | } |
|
13108 | } |
13337 | } |
13109 | 13338 | ||
13110 | /** |
13339 | /** |
13111 | * intel_atomic_check - validate state object |
13340 | * intel_atomic_check - validate state object |
13112 | * @dev: drm device |
13341 | * @dev: drm device |
13113 | * @state: state to validate |
13342 | * @state: state to validate |
13114 | */ |
13343 | */ |
13115 | static int intel_atomic_check(struct drm_device *dev, |
13344 | static int intel_atomic_check(struct drm_device *dev, |
- | 13345 | struct drm_atomic_state *state) |
|
13116 | struct drm_atomic_state *state) |
13346 | { |
13117 | { |
13347 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13118 | struct drm_crtc *crtc; |
13348 | struct drm_crtc *crtc; |
13119 | struct drm_crtc_state *crtc_state; |
13349 | struct drm_crtc_state *crtc_state; |
Line 13180... | Line 13410... | ||
13180 | ret = intel_modeset_checks(state); |
13410 | ret = intel_modeset_checks(state); |
Line 13181... | Line 13411... | ||
13181 | 13411 | ||
13182 | if (ret) |
13412 | if (ret) |
13183 | return ret; |
13413 | return ret; |
13184 | } else |
13414 | } else |
- | 13415 | intel_state->cdclk = to_i915(state->dev)->cdclk_freq; |
|
13185 | to_intel_atomic_state(state)->cdclk = |
13416 | |
- | 13417 | ret = drm_atomic_helper_check_planes(state->dev, state); |
|
- | 13418 | if (ret) |
|
Line -... | Line 13419... | ||
- | 13419 | return ret; |
|
- | 13420 | ||
- | 13421 | calc_watermark_data(state); |
|
- | 13422 | ||
- | 13423 | return 0; |
|
- | 13424 | } |
|
- | 13425 | ||
- | 13426 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
|
- | 13427 | struct drm_atomic_state *state, |
|
- | 13428 | bool async) |
|
- | 13429 | { |
|
- | 13430 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 13431 | struct drm_plane_state *plane_state; |
|
- | 13432 | struct drm_crtc_state *crtc_state; |
|
- | 13433 | struct drm_plane *plane; |
|
- | 13434 | struct drm_crtc *crtc; |
|
- | 13435 | int i, ret; |
|
- | 13436 | ||
- | 13437 | if (async) { |
|
- | 13438 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); |
|
- | 13439 | return -EINVAL; |
|
- | 13440 | } |
|
- | 13441 | ||
- | 13442 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
|
- | 13443 | if (state->legacy_cursor_update) |
|
- | 13444 | continue; |
|
- | 13445 | ||
- | 13446 | ret = intel_crtc_wait_for_pending_flips(crtc); |
|
- | 13447 | if (ret) |
|
- | 13448 | return ret; |
|
- | 13449 | ||
- | 13450 | // if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
|
- | 13451 | // flush_workqueue(dev_priv->wq); |
|
- | 13452 | } |
|
- | 13453 | ||
- | 13454 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
|
- | 13455 | if (ret) |
|
13186 | to_i915(state->dev)->cdclk_freq; |
13456 | return ret; |
- | 13457 | ||
- | 13458 | ret = drm_atomic_helper_prepare_planes(dev, state); |
|
- | 13459 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
|
- | 13460 | u32 reset_counter; |
|
- | 13461 | ||
- | 13462 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
|
- | 13463 | mutex_unlock(&dev->struct_mutex); |
|
- | 13464 | ||
- | 13465 | for_each_plane_in_state(state, plane, plane_state, i) { |
|
- | 13466 | struct intel_plane_state *intel_plane_state = |
|
- | 13467 | to_intel_plane_state(plane_state); |
|
- | 13468 | ||
- | 13469 | if (!intel_plane_state->wait_req) |
|
- | 13470 | continue; |
|
- | 13471 | ||
- | 13472 | ret = __i915_wait_request(intel_plane_state->wait_req, |
|
- | 13473 | reset_counter, true, |
|
- | 13474 | NULL, NULL); |
|
- | 13475 | ||
- | 13476 | /* Swallow -EIO errors to allow updates during hw lockup. */ |
|
- | 13477 | if (ret == -EIO) |
|
- | 13478 | ret = 0; |
|
- | 13479 | ||
- | 13480 | if (ret) |
|
- | 13481 | break; |
|
- | 13482 | } |
|
- | 13483 | ||
- | 13484 | if (!ret) |
|
- | 13485 | return 0; |
|
- | 13486 | ||
- | 13487 | mutex_lock(&dev->struct_mutex); |
|
- | 13488 | drm_atomic_helper_cleanup_planes(dev, state); |
|
- | 13489 | } |
|
- | 13490 | ||
13187 | 13491 | mutex_unlock(&dev->struct_mutex); |
|
Line 13188... | Line 13492... | ||
13188 | return drm_atomic_helper_check_planes(state->dev, state); |
13492 | return ret; |
13189 | } |
13493 | } |
13190 | 13494 | ||
Line 13207... | Line 13511... | ||
13207 | static int intel_atomic_commit(struct drm_device *dev, |
13511 | static int intel_atomic_commit(struct drm_device *dev, |
13208 | struct drm_atomic_state *state, |
13512 | struct drm_atomic_state *state, |
13209 | bool async) |
13513 | bool async) |
13210 | { |
13514 | { |
13211 | struct drm_i915_private *dev_priv = dev->dev_private; |
13515 | struct drm_i915_private *dev_priv = dev->dev_private; |
13212 | struct drm_crtc *crtc; |
- | |
13213 | struct drm_crtc_state *crtc_state; |
13516 | struct drm_crtc_state *crtc_state; |
- | 13517 | struct drm_crtc *crtc; |
|
13214 | int ret = 0; |
13518 | int ret = 0; |
13215 | int i; |
13519 | int i; |
13216 | bool any_ms = false; |
13520 | bool any_ms = false; |
Line 13217... | Line -... | ||
13217 | - | ||
13218 | if (async) { |
- | |
13219 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); |
- | |
13220 | return -EINVAL; |
- | |
13221 | } |
- | |
13222 | 13521 | ||
13223 | ret = drm_atomic_helper_prepare_planes(dev, state); |
13522 | ret = intel_atomic_prepare_commit(dev, state, async); |
- | 13523 | if (ret) { |
|
13224 | if (ret) |
13524 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); |
- | 13525 | return ret; |
|
Line 13225... | Line 13526... | ||
13225 | return ret; |
13526 | } |
- | 13527 | ||
Line 13226... | Line 13528... | ||
13226 | 13528 | drm_atomic_helper_swap_state(dev, state); |
|
13227 | drm_atomic_helper_swap_state(dev, state); |
13529 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
Line 13228... | Line 13530... | ||
13228 | 13530 | ||
Line 13238... | Line 13540... | ||
13238 | if (crtc_state->active) { |
13540 | if (crtc_state->active) { |
13239 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); |
13541 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); |
13240 | dev_priv->display.crtc_disable(crtc); |
13542 | dev_priv->display.crtc_disable(crtc); |
13241 | intel_crtc->active = false; |
13543 | intel_crtc->active = false; |
13242 | intel_disable_shared_dpll(intel_crtc); |
13544 | intel_disable_shared_dpll(intel_crtc); |
- | 13545 | ||
- | 13546 | /* |
|
- | 13547 | * Underruns don't always raise |
|
- | 13548 | * interrupts, so check manually. |
|
- | 13549 | */ |
|
- | 13550 | intel_check_cpu_fifo_underruns(dev_priv); |
|
- | 13551 | intel_check_pch_fifo_underruns(dev_priv); |
|
- | 13552 | ||
- | 13553 | if (!crtc->state->active) |
|
- | 13554 | intel_update_watermarks(crtc); |
|
13243 | } |
13555 | } |
13244 | } |
13556 | } |
Line 13245... | Line 13557... | ||
13245 | 13557 | ||
13246 | /* Only after disabling all output pipelines that will be changed can we |
13558 | /* Only after disabling all output pipelines that will be changed can we |
Line 13260... | Line 13572... | ||
13260 | bool modeset = needs_modeset(crtc->state); |
13572 | bool modeset = needs_modeset(crtc->state); |
13261 | bool update_pipe = !modeset && |
13573 | bool update_pipe = !modeset && |
13262 | to_intel_crtc_state(crtc->state)->update_pipe; |
13574 | to_intel_crtc_state(crtc->state)->update_pipe; |
13263 | unsigned long put_domains = 0; |
13575 | unsigned long put_domains = 0; |
Line -... | Line 13576... | ||
- | 13576 | ||
- | 13577 | if (modeset) |
|
- | 13578 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
|
13264 | 13579 | ||
13265 | if (modeset && crtc->state->active) { |
13580 | if (modeset && crtc->state->active) { |
13266 | update_scanline_offset(to_intel_crtc(crtc)); |
13581 | update_scanline_offset(to_intel_crtc(crtc)); |
13267 | dev_priv->display.crtc_enable(crtc); |
13582 | dev_priv->display.crtc_enable(crtc); |
Line 13275... | Line 13590... | ||
13275 | } |
13590 | } |
Line 13276... | Line 13591... | ||
13276 | 13591 | ||
13277 | if (!modeset) |
13592 | if (!modeset) |
Line -... | Line 13593... | ||
- | 13593 | intel_pre_plane_update(intel_crtc); |
|
- | 13594 | ||
13278 | intel_pre_plane_update(intel_crtc); |
13595 | if (crtc->state->active && |
Line 13279... | Line 13596... | ||
13279 | 13596 | (crtc->state->planes_changed || update_pipe)) |
|
13280 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
13597 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
Line 13281... | Line 13598... | ||
13281 | 13598 | ||
- | 13599 | if (put_domains) |
|
- | 13600 | modeset_put_power_domains(dev_priv, put_domains); |
|
- | 13601 | ||
13282 | if (put_domains) |
13602 | intel_post_plane_update(intel_crtc); |
Line 13283... | Line 13603... | ||
13283 | modeset_put_power_domains(dev_priv, put_domains); |
13603 | |
Line 13284... | Line 13604... | ||
13284 | 13604 | if (modeset) |
|
- | 13605 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
|
- | 13606 | } |
|
13285 | intel_post_plane_update(intel_crtc); |
13607 | |
- | 13608 | /* FIXME: add subpixel order */ |
|
Line 13286... | Line 13609... | ||
13286 | } |
13609 | |
13287 | 13610 | drm_atomic_helper_wait_for_vblanks(dev, state); |
|
Line 13288... | Line 13611... | ||
13288 | /* FIXME: add subpixel order */ |
13611 | |
Line 13351... | Line 13674... | ||
13351 | struct intel_shared_dpll *pll, |
13674 | struct intel_shared_dpll *pll, |
13352 | struct intel_dpll_hw_state *hw_state) |
13675 | struct intel_dpll_hw_state *hw_state) |
13353 | { |
13676 | { |
13354 | uint32_t val; |
13677 | uint32_t val; |
Line 13355... | Line 13678... | ||
13355 | 13678 | ||
13356 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
13679 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
Line 13357... | Line 13680... | ||
13357 | return false; |
13680 | return false; |
13358 | 13681 | ||
13359 | val = I915_READ(PCH_DPLL(pll->id)); |
13682 | val = I915_READ(PCH_DPLL(pll->id)); |
13360 | hw_state->dpll = val; |
13683 | hw_state->dpll = val; |
Line -... | Line 13684... | ||
- | 13684 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
|
- | 13685 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
|
13361 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
13686 | |
13362 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
13687 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
Line 13363... | Line 13688... | ||
13363 | 13688 | ||
13364 | return val & DPLL_VCO_ENABLE; |
13689 | return val & DPLL_VCO_ENABLE; |
Line 13455... | Line 13780... | ||
13455 | * Prepares a framebuffer for usage on a display plane. Generally this |
13780 | * Prepares a framebuffer for usage on a display plane. Generally this |
13456 | * involves pinning the underlying object and updating the frontbuffer tracking |
13781 | * involves pinning the underlying object and updating the frontbuffer tracking |
13457 | * bits. Some older platforms need special physical address handling for |
13782 | * bits. Some older platforms need special physical address handling for |
13458 | * cursor planes. |
13783 | * cursor planes. |
13459 | * |
13784 | * |
- | 13785 | * Must be called with struct_mutex held. |
|
- | 13786 | * |
|
13460 | * Returns 0 on success, negative error code on failure. |
13787 | * Returns 0 on success, negative error code on failure. |
13461 | */ |
13788 | */ |
13462 | int |
13789 | int |
13463 | intel_prepare_plane_fb(struct drm_plane *plane, |
13790 | intel_prepare_plane_fb(struct drm_plane *plane, |
13464 | const struct drm_plane_state *new_state) |
13791 | const struct drm_plane_state *new_state) |
13465 | { |
13792 | { |
13466 | struct drm_device *dev = plane->dev; |
13793 | struct drm_device *dev = plane->dev; |
13467 | struct drm_framebuffer *fb = new_state->fb; |
13794 | struct drm_framebuffer *fb = new_state->fb; |
13468 | struct intel_plane *intel_plane = to_intel_plane(plane); |
13795 | struct intel_plane *intel_plane = to_intel_plane(plane); |
13469 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
13796 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
13470 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); |
13797 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
13471 | int ret = 0; |
13798 | int ret = 0; |
Line 13472... | Line 13799... | ||
13472 | 13799 | ||
13473 | if (!obj) |
13800 | if (!obj && !old_obj) |
Line -... | Line 13801... | ||
- | 13801 | return 0; |
|
13474 | return 0; |
13802 | |
- | 13803 | if (old_obj) { |
|
Line -... | Line 13804... | ||
- | 13804 | struct drm_crtc_state *crtc_state = |
|
- | 13805 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); |
|
- | 13806 | ||
- | 13807 | /* Big Hammer, we also need to ensure that any pending |
|
- | 13808 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
|
- | 13809 | * current scanout is retired before unpinning the old |
|
- | 13810 | * framebuffer. Note that we rely on userspace rendering |
|
- | 13811 | * into the buffer attached to the pipe they are waiting |
|
- | 13812 | * on. If not, userspace generates a GPU hang with IPEHR |
|
- | 13813 | * point to the MI_WAIT_FOR_EVENT. |
|
- | 13814 | * |
|
- | 13815 | * This should only fail upon a hung GPU, in which case we |
|
- | 13816 | * can safely continue. |
|
- | 13817 | */ |
|
- | 13818 | if (needs_modeset(crtc_state)) |
|
- | 13819 | ret = i915_gem_object_wait_rendering(old_obj, true); |
|
- | 13820 | ||
- | 13821 | /* Swallow -EIO errors to allow updates during hw lockup. */ |
|
- | 13822 | if (ret && ret != -EIO) |
|
- | 13823 | return ret; |
|
- | 13824 | } |
|
- | 13825 | ||
- | 13826 | /* For framebuffer backed by dmabuf, wait for fence */ |
|
13475 | 13827 | ||
13476 | mutex_lock(&dev->struct_mutex); |
13828 | if (!obj) { |
13477 | 13829 | ret = 0; |
|
13478 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13830 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13479 | INTEL_INFO(dev)->cursor_needs_physical) { |
13831 | INTEL_INFO(dev)->cursor_needs_physical) { |
13480 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
13832 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
13481 | ret = 1; |
13833 | ret = i915_gem_object_attach_phys(obj, align); |
13482 | if (ret) |
13834 | if (ret) |
13483 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
13835 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
Line 13484... | Line 13836... | ||
13484 | } else { |
13836 | } else { |
- | 13837 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
|
- | 13838 | } |
|
13485 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL); |
13839 | |
Line -... | Line 13840... | ||
- | 13840 | if (ret == 0) { |
|
13486 | } |
13841 | if (obj) { |
- | 13842 | struct intel_plane_state *plane_state = |
|
- | 13843 | to_intel_plane_state(new_state); |
|
- | 13844 | ||
- | 13845 | i915_gem_request_assign(&plane_state->wait_req, |
|
Line 13487... | Line 13846... | ||
13487 | 13846 | obj->last_write_req); |
|
13488 | if (ret == 0) |
13847 | } |
Line 13489... | Line 13848... | ||
13489 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
13848 | |
13490 | 13849 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
|
13491 | mutex_unlock(&dev->struct_mutex); |
13850 | } |
13492 | 13851 | ||
13493 | return ret; |
13852 | return ret; |
13494 | } |
13853 | } |
- | 13854 | ||
- | 13855 | /** |
|
13495 | 13856 | * intel_cleanup_plane_fb - Cleans up an fb after plane use |
|
13496 | /** |
13857 | * @plane: drm plane to clean up for |
13497 | * intel_cleanup_plane_fb - Cleans up an fb after plane use |
13858 | * @fb: old framebuffer that was on plane |
13498 | * @plane: drm plane to clean up for |
13859 | * |
13499 | * @fb: old framebuffer that was on plane |
13860 | * Cleans up a framebuffer that has just been removed from a plane. |
13500 | * |
13861 | * |
- | 13862 | * Must be called with struct_mutex held. |
|
- | 13863 | */ |
|
13501 | * Cleans up a framebuffer that has just been removed from a plane. |
13864 | void |
- | 13865 | intel_cleanup_plane_fb(struct drm_plane *plane, |
|
Line -... | Line 13866... | ||
- | 13866 | const struct drm_plane_state *old_state) |
|
- | 13867 | { |
|
13502 | */ |
13868 | struct drm_device *dev = plane->dev; |
13503 | void |
13869 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Line 13504... | Line 13870... | ||
13504 | intel_cleanup_plane_fb(struct drm_plane *plane, |
13870 | struct intel_plane_state *old_intel_state; |
13505 | const struct drm_plane_state *old_state) |
13871 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13506 | { |
- | |
13507 | struct drm_device *dev = plane->dev; |
13872 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); |
- | 13873 | ||
- | 13874 | old_intel_state = to_intel_plane_state(old_state); |
|
- | 13875 | ||
- | 13876 | if (!obj && !old_obj) |
|
- | 13877 | return; |
|
- | 13878 | ||
13508 | struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb); |
13879 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13509 | 13880 | !INTEL_INFO(dev)->cursor_needs_physical)) |
|
13510 | if (!obj) |
13881 | intel_unpin_fb_obj(old_state->fb, old_state); |
Line 13511... | Line 13882... | ||
13511 | return; |
13882 | |
13512 | 13883 | /* prepare_fb aborted? */ |
|
13513 | if (plane->type != DRM_PLANE_TYPE_CURSOR || |
13884 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || |
Line 13532... | Line 13903... | ||
13532 | dev = intel_crtc->base.dev; |
13903 | dev = intel_crtc->base.dev; |
13533 | dev_priv = dev->dev_private; |
13904 | dev_priv = dev->dev_private; |
13534 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
13905 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
13535 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
13906 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
Line 13536... | Line 13907... | ||
13536 | 13907 | ||
13537 | if (!crtc_clock || !cdclk) |
13908 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
Line 13538... | Line 13909... | ||
13538 | return DRM_PLANE_HELPER_NO_SCALING; |
13909 | return DRM_PLANE_HELPER_NO_SCALING; |
13539 | 13910 | ||
13540 | /* |
13911 | /* |
Line 13581... | Line 13952... | ||
13581 | { |
13952 | { |
13582 | struct drm_crtc *crtc = state->base.crtc; |
13953 | struct drm_crtc *crtc = state->base.crtc; |
13583 | struct drm_framebuffer *fb = state->base.fb; |
13954 | struct drm_framebuffer *fb = state->base.fb; |
13584 | struct drm_device *dev = plane->dev; |
13955 | struct drm_device *dev = plane->dev; |
13585 | struct drm_i915_private *dev_priv = dev->dev_private; |
13956 | struct drm_i915_private *dev_priv = dev->dev_private; |
13586 | struct intel_crtc *intel_crtc; |
- | |
13587 | struct drm_rect *src = &state->src; |
- | |
Line 13588... | Line 13957... | ||
13588 | 13957 | ||
13589 | crtc = crtc ? crtc : plane->crtc; |
- | |
13590 | intel_crtc = to_intel_crtc(crtc); |
- | |
13591 | - | ||
13592 | plane->fb = fb; |
- | |
13593 | crtc->x = src->x1 >> 16; |
- | |
13594 | crtc->y = src->y1 >> 16; |
- | |
13595 | - | ||
13596 | if (!crtc->state->active) |
- | |
Line 13597... | Line 13958... | ||
13597 | return; |
13958 | crtc = crtc ? crtc : plane->crtc; |
13598 | 13959 | ||
13599 | dev_priv->display.update_primary_plane(crtc, fb, |
13960 | dev_priv->display.update_primary_plane(crtc, fb, |
13600 | state->src.x1 >> 16, |
13961 | state->src.x1 >> 16, |
Line 13618... | Line 13979... | ||
13618 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13979 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13619 | struct intel_crtc_state *old_intel_state = |
13980 | struct intel_crtc_state *old_intel_state = |
13620 | to_intel_crtc_state(old_crtc_state); |
13981 | to_intel_crtc_state(old_crtc_state); |
13621 | bool modeset = needs_modeset(crtc->state); |
13982 | bool modeset = needs_modeset(crtc->state); |
Line 13622... | Line -... | ||
13622 | - | ||
13623 | if (intel_crtc->atomic.update_wm_pre) |
- | |
13624 | intel_update_watermarks(crtc); |
- | |
13625 | 13983 | ||
13626 | /* Perform vblank evasion around commit operation */ |
- | |
13627 | if (crtc->state->active) |
13984 | /* Perform vblank evasion around commit operation */ |
Line 13628... | Line 13985... | ||
13628 | intel_pipe_update_start(intel_crtc); |
13985 | intel_pipe_update_start(intel_crtc); |
13629 | 13986 | ||
Line 13639... | Line 13996... | ||
13639 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13996 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13640 | struct drm_crtc_state *old_crtc_state) |
13997 | struct drm_crtc_state *old_crtc_state) |
13641 | { |
13998 | { |
13642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13999 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 13643... | Line -... | ||
13643 | - | ||
13644 | if (crtc->state->active) |
14000 | |
13645 | intel_pipe_update_end(intel_crtc); |
14001 | intel_pipe_update_end(intel_crtc); |
Line 13646... | Line 14002... | ||
13646 | } |
14002 | } |
13647 | 14003 | ||
Line 13717... | Line 14073... | ||
13717 | } |
14073 | } |
Line 13718... | Line 14074... | ||
13718 | 14074 | ||
13719 | drm_universal_plane_init(dev, &primary->base, 0, |
14075 | drm_universal_plane_init(dev, &primary->base, 0, |
13720 | &intel_plane_funcs, |
14076 | &intel_plane_funcs, |
13721 | intel_primary_formats, num_formats, |
14077 | intel_primary_formats, num_formats, |
Line 13722... | Line 14078... | ||
13722 | DRM_PLANE_TYPE_PRIMARY); |
14078 | DRM_PLANE_TYPE_PRIMARY, NULL); |
13723 | 14079 | ||
Line 13724... | Line 14080... | ||
13724 | if (INTEL_INFO(dev)->gen >= 4) |
14080 | if (INTEL_INFO(dev)->gen >= 4) |
Line 13869... | Line 14225... | ||
13869 | 14225 | ||
13870 | drm_universal_plane_init(dev, &cursor->base, 0, |
14226 | drm_universal_plane_init(dev, &cursor->base, 0, |
13871 | &intel_plane_funcs, |
14227 | &intel_plane_funcs, |
13872 | intel_cursor_formats, |
14228 | intel_cursor_formats, |
13873 | ARRAY_SIZE(intel_cursor_formats), |
14229 | ARRAY_SIZE(intel_cursor_formats), |
Line 13874... | Line 14230... | ||
13874 | DRM_PLANE_TYPE_CURSOR); |
14230 | DRM_PLANE_TYPE_CURSOR, NULL); |
13875 | 14231 | ||
13876 | if (INTEL_INFO(dev)->gen >= 4) { |
14232 | if (INTEL_INFO(dev)->gen >= 4) { |
13877 | if (!dev->mode_config.rotation_property) |
14233 | if (!dev->mode_config.rotation_property) |
Line 13946... | Line 14302... | ||
13946 | cursor = intel_cursor_plane_create(dev, pipe); |
14302 | cursor = intel_cursor_plane_create(dev, pipe); |
13947 | if (!cursor) |
14303 | if (!cursor) |
13948 | goto fail; |
14304 | goto fail; |
Line 13949... | Line 14305... | ||
13949 | 14305 | ||
13950 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
14306 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
13951 | cursor, &intel_crtc_funcs); |
14307 | cursor, &intel_crtc_funcs, NULL); |
13952 | if (ret) |
14308 | if (ret) |
Line 13953... | Line 14309... | ||
13953 | goto fail; |
14309 | goto fail; |
13954 | 14310 | ||
Line 14072... | Line 14428... | ||
14072 | return false; |
14428 | return false; |
Line 14073... | Line 14429... | ||
14073 | 14429 | ||
14074 | if (IS_CHERRYVIEW(dev)) |
14430 | if (IS_CHERRYVIEW(dev)) |
Line -... | Line 14431... | ||
- | 14431 | return false; |
|
- | 14432 | ||
- | 14433 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
|
- | 14434 | return false; |
|
- | 14435 | ||
- | 14436 | /* DDI E can't be used if DDI A requires 4 lanes */ |
|
- | 14437 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
|
14075 | return false; |
14438 | return false; |
14076 | 14439 | ||
Line 14077... | Line 14440... | ||
14077 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) |
14440 | if (!dev_priv->vbt.int_crt_support) |
14078 | return false; |
14441 | return false; |
Line 14108... | Line 14471... | ||
14108 | * On SKL pre-D0 the strap isn't connected, so we assume |
14471 | * On SKL pre-D0 the strap isn't connected, so we assume |
14109 | * it's there. |
14472 | * it's there. |
14110 | */ |
14473 | */ |
14111 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
14474 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
14112 | /* WaIgnoreDDIAStrap: skl */ |
14475 | /* WaIgnoreDDIAStrap: skl */ |
14113 | if (found || IS_SKYLAKE(dev)) |
14476 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
14114 | intel_ddi_init(dev, PORT_A); |
14477 | intel_ddi_init(dev, PORT_A); |
Line 14115... | Line 14478... | ||
14115 | 14478 | ||
14116 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
14479 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
14117 | * register */ |
14480 | * register */ |
Line 14124... | Line 14487... | ||
14124 | if (found & SFUSE_STRAP_DDID_DETECTED) |
14487 | if (found & SFUSE_STRAP_DDID_DETECTED) |
14125 | intel_ddi_init(dev, PORT_D); |
14488 | intel_ddi_init(dev, PORT_D); |
14126 | /* |
14489 | /* |
14127 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. |
14490 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. |
14128 | */ |
14491 | */ |
14129 | if (IS_SKYLAKE(dev) && |
14492 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
14130 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14493 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14131 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || |
14494 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || |
14132 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) |
14495 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) |
14133 | intel_ddi_init(dev, PORT_E); |
14496 | intel_ddi_init(dev, PORT_E); |
Line 14139... | Line 14502... | ||
14139 | if (has_edp_a(dev)) |
14502 | if (has_edp_a(dev)) |
14140 | intel_dp_init(dev, DP_A, PORT_A); |
14503 | intel_dp_init(dev, DP_A, PORT_A); |
Line 14141... | Line 14504... | ||
14141 | 14504 | ||
14142 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
14505 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
14143 | /* PCH SDVOB multiplex with HDMIB */ |
14506 | /* PCH SDVOB multiplex with HDMIB */ |
14144 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
14507 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
14145 | if (!found) |
14508 | if (!found) |
14146 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
14509 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
14147 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
14510 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
14148 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
14511 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
Line 14157... | Line 14520... | ||
14157 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
14520 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
14158 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
14521 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
Line 14159... | Line 14522... | ||
14159 | 14522 | ||
14160 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
14523 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
14161 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
14524 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
14162 | } else if (IS_VALLEYVIEW(dev)) { |
- | |
14163 | bool has_edp, has_port; |
- | |
14164 | 14525 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
|
14165 | /* |
14526 | /* |
14166 | * The DP_DETECTED bit is the latched state of the DDC |
14527 | * The DP_DETECTED bit is the latched state of the DDC |
14167 | * SDA pin at boot. However since eDP doesn't require DDC |
14528 | * SDA pin at boot. However since eDP doesn't require DDC |
14168 | * (no way to plug in a DP->HDMI dongle) the DDC pins for |
14529 | * (no way to plug in a DP->HDMI dongle) the DDC pins for |
14169 | * eDP ports may have been muxed to an alternate function. |
14530 | * eDP ports may have been muxed to an alternate function. |
14170 | * Thus we can't rely on the DP_DETECTED bit alone to detect |
14531 | * Thus we can't rely on the DP_DETECTED bit alone to detect |
14171 | * eDP ports. Consult the VBT as well as DP_DETECTED to |
14532 | * eDP ports. Consult the VBT as well as DP_DETECTED to |
14172 | * detect eDP ports. |
- | |
14173 | * |
- | |
14174 | * Sadly the straps seem to be missing sometimes even for HDMI |
- | |
14175 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap |
- | |
14176 | * and VBT for the presence of the port. Additionally we can't |
- | |
14177 | * trust the port type the VBT declares as we've seen at least |
- | |
14178 | * HDMI ports that the VBT claim are DP or eDP. |
14533 | * detect eDP ports. |
14179 | */ |
- | |
14180 | has_edp = intel_dp_is_edp(dev, PORT_B); |
- | |
14181 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
14534 | */ |
14182 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) |
14535 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
14183 | has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); |
- | |
14184 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
14536 | !intel_dp_is_edp(dev, PORT_B)) |
- | 14537 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
|
- | 14538 | if (I915_READ(VLV_DP_B) & DP_DETECTED || |
|
- | 14539 | intel_dp_is_edp(dev, PORT_B)) |
|
Line 14185... | Line -... | ||
14185 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
- | |
14186 | - | ||
14187 | has_edp = intel_dp_is_edp(dev, PORT_C); |
14540 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
14188 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
14541 | |
14189 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) |
- | |
14190 | has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); |
14542 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
- | 14543 | !intel_dp_is_edp(dev, PORT_C)) |
|
- | 14544 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
|
- | 14545 | if (I915_READ(VLV_DP_C) & DP_DETECTED || |
|
Line 14191... | Line 14546... | ||
14191 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
14546 | intel_dp_is_edp(dev, PORT_C)) |
14192 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
- | |
14193 | 14547 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
|
14194 | if (IS_CHERRYVIEW(dev)) { |
- | |
14195 | /* |
- | |
14196 | * eDP not supported on port D, |
- | |
14197 | * so no need to worry about it |
- | |
14198 | */ |
- | |
14199 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); |
14548 | |
14200 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) |
14549 | if (IS_CHERRYVIEW(dev)) { |
- | 14550 | /* eDP not supported on port D, so don't check VBT */ |
|
- | 14551 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
|
14201 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
14552 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); |
Line 14202... | Line 14553... | ||
14202 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
14553 | if (I915_READ(CHV_DP_D) & DP_DETECTED) |
14203 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); |
14554 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
14204 | } |
14555 | } |
Line 14205... | Line 14556... | ||
14205 | 14556 | ||
14206 | intel_dsi_init(dev); |
14557 | intel_dsi_init(dev); |
14207 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
14558 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
14208 | bool found = false; |
14559 | bool found = false; |
14209 | 14560 | ||
14210 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
14561 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
14211 | DRM_DEBUG_KMS("probing SDVOB\n"); |
14562 | DRM_DEBUG_KMS("probing SDVOB\n"); |
Line 14221... | Line 14572... | ||
14221 | 14572 | ||
Line 14222... | Line 14573... | ||
14222 | /* Before G4X SDVOC doesn't have its own detect register */ |
14573 | /* Before G4X SDVOC doesn't have its own detect register */ |
14223 | 14574 | ||
14224 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
14575 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
14225 | DRM_DEBUG_KMS("probing SDVOC\n"); |
14576 | DRM_DEBUG_KMS("probing SDVOC\n"); |
Line 14226... | Line 14577... | ||
14226 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
14577 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
Line 14227... | Line 14578... | ||
14227 | } |
14578 | } |
Line 14240... | Line 14591... | ||
14240 | (I915_READ(DP_D) & DP_DETECTED)) |
14591 | (I915_READ(DP_D) & DP_DETECTED)) |
14241 | intel_dp_init(dev, DP_D, PORT_D); |
14592 | intel_dp_init(dev, DP_D, PORT_D); |
14242 | } else if (IS_GEN2(dev)) |
14593 | } else if (IS_GEN2(dev)) |
14243 | intel_dvo_init(dev); |
14594 | intel_dvo_init(dev); |
Line -... | Line 14595... | ||
- | 14595 | ||
- | 14596 | // if (SUPPORTS_TV(dev)) |
|
- | 14597 | // intel_tv_init(dev); |
|
14244 | 14598 | ||
Line 14245... | Line 14599... | ||
14245 | intel_psr_init(dev); |
14599 | intel_psr_init(dev); |
14246 | 14600 | ||
14247 | for_each_intel_encoder(dev, encoder) { |
14601 | for_each_intel_encoder(dev, encoder) { |
Line 14315... | Line 14669... | ||
14315 | if (gen >= 9) { |
14669 | if (gen >= 9) { |
14316 | /* "The stride in bytes must not exceed the of the size of 8K |
14670 | /* "The stride in bytes must not exceed the of the size of 8K |
14317 | * pixels and 32K bytes." |
14671 | * pixels and 32K bytes." |
14318 | */ |
14672 | */ |
14319 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); |
14673 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); |
14320 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { |
14674 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
14321 | return 32*1024; |
14675 | return 32*1024; |
14322 | } else if (gen >= 4) { |
14676 | } else if (gen >= 4) { |
14323 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
14677 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
14324 | return 16*1024; |
14678 | return 16*1024; |
14325 | else |
14679 | else |
Line 14419... | Line 14773... | ||
14419 | drm_get_format_name(mode_cmd->pixel_format)); |
14773 | drm_get_format_name(mode_cmd->pixel_format)); |
14420 | return -EINVAL; |
14774 | return -EINVAL; |
14421 | } |
14775 | } |
14422 | break; |
14776 | break; |
14423 | case DRM_FORMAT_ABGR8888: |
14777 | case DRM_FORMAT_ABGR8888: |
14424 | if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { |
14778 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
- | 14779 | INTEL_INFO(dev)->gen < 9) { |
|
14425 | DRM_DEBUG("unsupported pixel format: %s\n", |
14780 | DRM_DEBUG("unsupported pixel format: %s\n", |
14426 | drm_get_format_name(mode_cmd->pixel_format)); |
14781 | drm_get_format_name(mode_cmd->pixel_format)); |
14427 | return -EINVAL; |
14782 | return -EINVAL; |
14428 | } |
14783 | } |
14429 | break; |
14784 | break; |
Line 14435... | Line 14790... | ||
14435 | drm_get_format_name(mode_cmd->pixel_format)); |
14790 | drm_get_format_name(mode_cmd->pixel_format)); |
14436 | return -EINVAL; |
14791 | return -EINVAL; |
14437 | } |
14792 | } |
14438 | break; |
14793 | break; |
14439 | case DRM_FORMAT_ABGR2101010: |
14794 | case DRM_FORMAT_ABGR2101010: |
14440 | if (!IS_VALLEYVIEW(dev)) { |
14795 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
14441 | DRM_DEBUG("unsupported pixel format: %s\n", |
14796 | DRM_DEBUG("unsupported pixel format: %s\n", |
14442 | drm_get_format_name(mode_cmd->pixel_format)); |
14797 | drm_get_format_name(mode_cmd->pixel_format)); |
14443 | return -EINVAL; |
14798 | return -EINVAL; |
14444 | } |
14799 | } |
14445 | break; |
14800 | break; |
Line 14484... | Line 14839... | ||
14484 | } |
14839 | } |
Line 14485... | Line 14840... | ||
14485 | 14840 | ||
14486 | static struct drm_framebuffer * |
14841 | static struct drm_framebuffer * |
14487 | intel_user_framebuffer_create(struct drm_device *dev, |
14842 | intel_user_framebuffer_create(struct drm_device *dev, |
14488 | struct drm_file *filp, |
14843 | struct drm_file *filp, |
14489 | struct drm_mode_fb_cmd2 *user_mode_cmd) |
14844 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
- | 14845 | { |
|
14490 | { |
14846 | struct drm_framebuffer *fb; |
14491 | struct drm_i915_gem_object *obj; |
14847 | struct drm_i915_gem_object *obj; |
Line 14492... | Line 14848... | ||
14492 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
14848 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
14493 | 14849 | ||
14494 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14850 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14495 | mode_cmd.handles[0])); |
14851 | mode_cmd.handles[0])); |
Line 14496... | Line 14852... | ||
14496 | if (&obj->base == NULL) |
14852 | if (&obj->base == NULL) |
- | 14853 | return ERR_PTR(-ENOENT); |
|
- | 14854 | ||
- | 14855 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
|
- | 14856 | if (IS_ERR(fb)) |
|
14497 | return ERR_PTR(-ENOENT); |
14857 | drm_gem_object_unreference_unlocked(&obj->base); |
Line 14498... | Line 14858... | ||
14498 | 14858 | ||
14499 | return intel_framebuffer_create(dev, &mode_cmd, obj); |
14859 | return fb; |
14500 | } |
14860 | } |
Line 14558... | Line 14918... | ||
14558 | ironlake_crtc_compute_clock; |
14918 | ironlake_crtc_compute_clock; |
14559 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14919 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14560 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
14920 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
14561 | dev_priv->display.update_primary_plane = |
14921 | dev_priv->display.update_primary_plane = |
14562 | ironlake_update_primary_plane; |
14922 | ironlake_update_primary_plane; |
14563 | } else if (IS_VALLEYVIEW(dev)) { |
14923 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
14564 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
14924 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
14565 | dev_priv->display.get_initial_plane_config = |
14925 | dev_priv->display.get_initial_plane_config = |
14566 | i9xx_get_initial_plane_config; |
14926 | i9xx_get_initial_plane_config; |
14567 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
14927 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
14568 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14928 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
Line 14579... | Line 14939... | ||
14579 | dev_priv->display.update_primary_plane = |
14939 | dev_priv->display.update_primary_plane = |
14580 | i9xx_update_primary_plane; |
14940 | i9xx_update_primary_plane; |
14581 | } |
14941 | } |
Line 14582... | Line 14942... | ||
14582 | 14942 | ||
14583 | /* Returns the core display clock speed */ |
14943 | /* Returns the core display clock speed */ |
14584 | if (IS_SKYLAKE(dev)) |
14944 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
14585 | dev_priv->display.get_display_clock_speed = |
14945 | dev_priv->display.get_display_clock_speed = |
14586 | skylake_get_display_clock_speed; |
14946 | skylake_get_display_clock_speed; |
14587 | else if (IS_BROXTON(dev)) |
14947 | else if (IS_BROXTON(dev)) |
14588 | dev_priv->display.get_display_clock_speed = |
14948 | dev_priv->display.get_display_clock_speed = |
Line 14591... | Line 14951... | ||
14591 | dev_priv->display.get_display_clock_speed = |
14951 | dev_priv->display.get_display_clock_speed = |
14592 | broadwell_get_display_clock_speed; |
14952 | broadwell_get_display_clock_speed; |
14593 | else if (IS_HASWELL(dev)) |
14953 | else if (IS_HASWELL(dev)) |
14594 | dev_priv->display.get_display_clock_speed = |
14954 | dev_priv->display.get_display_clock_speed = |
14595 | haswell_get_display_clock_speed; |
14955 | haswell_get_display_clock_speed; |
14596 | else if (IS_VALLEYVIEW(dev)) |
14956 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
14597 | dev_priv->display.get_display_clock_speed = |
14957 | dev_priv->display.get_display_clock_speed = |
14598 | valleyview_get_display_clock_speed; |
14958 | valleyview_get_display_clock_speed; |
14599 | else if (IS_GEN5(dev)) |
14959 | else if (IS_GEN5(dev)) |
14600 | dev_priv->display.get_display_clock_speed = |
14960 | dev_priv->display.get_display_clock_speed = |
14601 | ilk_get_display_clock_speed; |
14961 | ilk_get_display_clock_speed; |
Line 14619... | Line 14979... | ||
14619 | dev_priv->display.get_display_clock_speed = |
14979 | dev_priv->display.get_display_clock_speed = |
14620 | i915_get_display_clock_speed; |
14980 | i915_get_display_clock_speed; |
14621 | else if (IS_I945GM(dev) || IS_845G(dev)) |
14981 | else if (IS_I945GM(dev) || IS_845G(dev)) |
14622 | dev_priv->display.get_display_clock_speed = |
14982 | dev_priv->display.get_display_clock_speed = |
14623 | i9xx_misc_get_display_clock_speed; |
14983 | i9xx_misc_get_display_clock_speed; |
14624 | else if (IS_PINEVIEW(dev)) |
- | |
14625 | dev_priv->display.get_display_clock_speed = |
- | |
14626 | pnv_get_display_clock_speed; |
- | |
14627 | else if (IS_I915GM(dev)) |
14984 | else if (IS_I915GM(dev)) |
14628 | dev_priv->display.get_display_clock_speed = |
14985 | dev_priv->display.get_display_clock_speed = |
14629 | i915gm_get_display_clock_speed; |
14986 | i915gm_get_display_clock_speed; |
14630 | else if (IS_I865G(dev)) |
14987 | else if (IS_I865G(dev)) |
14631 | dev_priv->display.get_display_clock_speed = |
14988 | dev_priv->display.get_display_clock_speed = |
Line 14652... | Line 15009... | ||
14652 | dev_priv->display.modeset_commit_cdclk = |
15009 | dev_priv->display.modeset_commit_cdclk = |
14653 | broadwell_modeset_commit_cdclk; |
15010 | broadwell_modeset_commit_cdclk; |
14654 | dev_priv->display.modeset_calc_cdclk = |
15011 | dev_priv->display.modeset_calc_cdclk = |
14655 | broadwell_modeset_calc_cdclk; |
15012 | broadwell_modeset_calc_cdclk; |
14656 | } |
15013 | } |
14657 | } else if (IS_VALLEYVIEW(dev)) { |
15014 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
14658 | dev_priv->display.modeset_commit_cdclk = |
15015 | dev_priv->display.modeset_commit_cdclk = |
14659 | valleyview_modeset_commit_cdclk; |
15016 | valleyview_modeset_commit_cdclk; |
14660 | dev_priv->display.modeset_calc_cdclk = |
15017 | dev_priv->display.modeset_calc_cdclk = |
14661 | valleyview_modeset_calc_cdclk; |
15018 | valleyview_modeset_calc_cdclk; |
14662 | } else if (IS_BROXTON(dev)) { |
15019 | } else if (IS_BROXTON(dev)) { |
Line 14868... | Line 15225... | ||
14868 | /* Disable the VGA plane that we never use */ |
15225 | /* Disable the VGA plane that we never use */ |
14869 | static void i915_disable_vga(struct drm_device *dev) |
15226 | static void i915_disable_vga(struct drm_device *dev) |
14870 | { |
15227 | { |
14871 | struct drm_i915_private *dev_priv = dev->dev_private; |
15228 | struct drm_i915_private *dev_priv = dev->dev_private; |
14872 | u8 sr1; |
15229 | u8 sr1; |
14873 | u32 vga_reg = i915_vgacntrl_reg(dev); |
15230 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
Line 14874... | Line 15231... | ||
14874 | 15231 | ||
14875 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
15232 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
14876 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
15233 | // vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
14877 | outb(SR01, VGA_SR_INDEX); |
15234 | outb(SR01, VGA_SR_INDEX); |
Line 14980... | Line 15337... | ||
14980 | 15337 | ||
14981 | /* Just disable it once at startup */ |
15338 | /* Just disable it once at startup */ |
14982 | i915_disable_vga(dev); |
15339 | i915_disable_vga(dev); |
Line 14983... | Line -... | ||
14983 | intel_setup_outputs(dev); |
- | |
14984 | - | ||
14985 | /* Just in case the BIOS is doing something questionable. */ |
- | |
14986 | intel_fbc_disable(dev_priv); |
15340 | intel_setup_outputs(dev); |
14987 | 15341 | ||
14988 | drm_modeset_lock_all(dev); |
15342 | drm_modeset_lock_all(dev); |
Line 14989... | Line 15343... | ||
14989 | intel_modeset_setup_hw_state(dev); |
15343 | intel_modeset_setup_hw_state(dev); |
Line 15069... | Line 15423... | ||
15069 | 15423 | ||
15070 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15424 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15071 | { |
15425 | { |
15072 | struct drm_device *dev = crtc->base.dev; |
15426 | struct drm_device *dev = crtc->base.dev; |
15073 | struct drm_i915_private *dev_priv = dev->dev_private; |
15427 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 15074... | Line 15428... | ||
15074 | u32 reg; |
15428 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
15075 | - | ||
15076 | /* Clear any frame start delays used for debugging left by the BIOS */ |
15429 | |
Line 15077... | Line 15430... | ||
15077 | reg = PIPECONF(crtc->config->cpu_transcoder); |
15430 | /* Clear any frame start delays used for debugging left by the BIOS */ |
15078 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15431 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15079 | 15432 | ||
Line 15139... | Line 15492... | ||
15139 | crtc->active ? "enabled" : "disabled"); |
15492 | crtc->active ? "enabled" : "disabled"); |
Line 15140... | Line 15493... | ||
15140 | 15493 | ||
15141 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
15494 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
15142 | crtc->base.state->active = crtc->active; |
15495 | crtc->base.state->active = crtc->active; |
- | 15496 | crtc->base.enabled = crtc->active; |
|
Line 15143... | Line 15497... | ||
15143 | crtc->base.enabled = crtc->active; |
15497 | crtc->base.state->connector_mask = 0; |
15144 | 15498 | ||
15145 | /* Because we only establish the connector -> encoder -> |
15499 | /* Because we only establish the connector -> encoder -> |
15146 | * crtc links if something is active, this means the |
15500 | * crtc links if something is active, this means the |
Line 15226... | Line 15580... | ||
15226 | } |
15580 | } |
Line 15227... | Line 15581... | ||
15227 | 15581 | ||
15228 | void i915_redisable_vga_power_on(struct drm_device *dev) |
15582 | void i915_redisable_vga_power_on(struct drm_device *dev) |
15229 | { |
15583 | { |
15230 | struct drm_i915_private *dev_priv = dev->dev_private; |
15584 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 15231... | Line 15585... | ||
15231 | u32 vga_reg = i915_vgacntrl_reg(dev); |
15585 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
15232 | 15586 | ||
15233 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15587 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15234 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
15588 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
Line 15245... | Line 15599... | ||
15245 | * structures are not yet restored. Since this function is at a very |
15599 | * structures are not yet restored. Since this function is at a very |
15246 | * paranoid "someone might have enabled VGA while we were not looking" |
15600 | * paranoid "someone might have enabled VGA while we were not looking" |
15247 | * level, just check if the power well is enabled instead of trying to |
15601 | * level, just check if the power well is enabled instead of trying to |
15248 | * follow the "don't touch the power well if we don't need it" policy |
15602 | * follow the "don't touch the power well if we don't need it" policy |
15249 | * the rest of the driver uses. */ |
15603 | * the rest of the driver uses. */ |
15250 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
15604 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
15251 | return; |
15605 | return; |
Line 15252... | Line 15606... | ||
15252 | 15606 | ||
- | 15607 | i915_redisable_vga_power_on(dev); |
|
- | 15608 | ||
15253 | i915_redisable_vga_power_on(dev); |
15609 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); |
Line 15254... | Line 15610... | ||
15254 | } |
15610 | } |
15255 | 15611 | ||
15256 | static bool primary_get_hw_state(struct intel_plane *plane) |
15612 | static bool primary_get_hw_state(struct intel_plane *plane) |
Line 15265... | Line 15621... | ||
15265 | { |
15621 | { |
15266 | struct drm_plane *primary = crtc->base.primary; |
15622 | struct drm_plane *primary = crtc->base.primary; |
15267 | struct intel_plane_state *plane_state = |
15623 | struct intel_plane_state *plane_state = |
15268 | to_intel_plane_state(primary->state); |
15624 | to_intel_plane_state(primary->state); |
Line 15269... | Line 15625... | ||
15269 | 15625 | ||
15270 | plane_state->visible = |
15626 | plane_state->visible = crtc->active && |
Line 15271... | Line 15627... | ||
15271 | primary_get_hw_state(to_intel_plane(primary)); |
15627 | primary_get_hw_state(to_intel_plane(primary)); |
15272 | 15628 | ||
15273 | if (plane_state->visible) |
15629 | if (plane_state->visible) |
Line 15341... | Line 15697... | ||
15341 | } |
15697 | } |
Line 15342... | Line 15698... | ||
15342 | 15698 | ||
15343 | for_each_intel_connector(dev, connector) { |
15699 | for_each_intel_connector(dev, connector) { |
15344 | if (connector->get_hw_state(connector)) { |
15700 | if (connector->get_hw_state(connector)) { |
- | 15701 | connector->base.dpms = DRM_MODE_DPMS_ON; |
|
- | 15702 | ||
15345 | connector->base.dpms = DRM_MODE_DPMS_ON; |
15703 | encoder = connector->encoder; |
- | 15704 | connector->base.encoder = &encoder->base; |
|
- | 15705 | ||
- | 15706 | if (encoder->base.crtc && |
|
- | 15707 | encoder->base.crtc->state->active) { |
|
- | 15708 | /* |
|
- | 15709 | * This has to be done during hardware readout |
|
- | 15710 | * because anything calling .crtc_disable may |
|
- | 15711 | * rely on the connector_mask being accurate. |
|
- | 15712 | */ |
|
- | 15713 | encoder->base.crtc->state->connector_mask |= |
|
- | 15714 | 1 << drm_connector_index(&connector->base); |
|
- | 15715 | } |
|
15346 | connector->base.encoder = &connector->encoder->base; |
15716 | |
15347 | } else { |
15717 | } else { |
15348 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15718 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15349 | connector->base.encoder = NULL; |
15719 | connector->base.encoder = NULL; |
15350 | } |
15720 | } |
Line 15426... | Line 15796... | ||
15426 | 15796 | ||
15427 | pll->disable(dev_priv, pll); |
15797 | pll->disable(dev_priv, pll); |
15428 | pll->on = false; |
15798 | pll->on = false; |
Line 15429... | Line 15799... | ||
15429 | } |
15799 | } |
15430 | 15800 | ||
15431 | if (IS_VALLEYVIEW(dev)) |
15801 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
15432 | vlv_wm_get_hw_state(dev); |
15802 | vlv_wm_get_hw_state(dev); |
15433 | else if (IS_GEN9(dev)) |
15803 | else if (IS_GEN9(dev)) |
15434 | skl_wm_get_hw_state(dev); |
15804 | skl_wm_get_hw_state(dev); |
Line 15522... | Line 15892... | ||
15522 | continue; |
15892 | continue; |
Line 15523... | Line 15893... | ||
15523 | 15893 | ||
15524 | mutex_lock(&dev->struct_mutex); |
15894 | mutex_lock(&dev->struct_mutex); |
15525 | ret = intel_pin_and_fence_fb_obj(c->primary, |
15895 | ret = intel_pin_and_fence_fb_obj(c->primary, |
15526 | c->primary->fb, |
15896 | c->primary->fb, |
15527 | c->primary->state, |
- | |
15528 | NULL, NULL); |
15897 | c->primary->state); |
15529 | mutex_unlock(&dev->struct_mutex); |
15898 | mutex_unlock(&dev->struct_mutex); |
15530 | if (ret) { |
15899 | if (ret) { |
15531 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15900 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15532 | to_intel_crtc(c)->pipe); |
15901 | to_intel_crtc(c)->pipe); |
Line 15551... | Line 15920... | ||
15551 | 15920 | ||
15552 | void intel_modeset_cleanup(struct drm_device *dev) |
15921 | void intel_modeset_cleanup(struct drm_device *dev) |
15553 | { |
15922 | { |
15554 | #if 0 |
15923 | #if 0 |
15555 | struct drm_i915_private *dev_priv = dev->dev_private; |
15924 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 15556... | Line 15925... | ||
15556 | struct drm_connector *connector; |
15925 | struct intel_connector *connector; |
Line 15557... | Line 15926... | ||
15557 | 15926 | ||
Line 15578... | Line 15947... | ||
15578 | 15947 | ||
15579 | /* flush any delayed tasks or pending work */ |
15948 | /* flush any delayed tasks or pending work */ |
Line 15580... | Line 15949... | ||
15580 | flush_scheduled_work(); |
15949 | flush_scheduled_work(); |
15581 | - | ||
15582 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15950 | |
15583 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
- | |
15584 | struct intel_connector *intel_connector; |
- | |
15585 | 15951 | /* destroy the backlight and sysfs files before encoders/connectors */ |
|
15586 | intel_connector = to_intel_connector(connector); |
- | |
Line 15587... | Line 15952... | ||
15587 | intel_connector->unregister(intel_connector); |
15952 | for_each_intel_connector(dev, connector) |
Line 15588... | Line 15953... | ||
15588 | } |
15953 | connector->unregister(connector); |