WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_irq.c

 } while (0)
 /*
  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
  */
+static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
-static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
+				    i915_reg_t reg)
+{
 	u32 val = I915_READ(reg);
 	if (val == 0)
 		return;
 	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
-	     reg, val);
+	     i915_mmio_reg_offset(reg), val);
 	I915_WRITE(reg, 0xffffffff);
 	POSTING_READ(reg);
  * ilk_update_display_irq - update DEIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
  */
-static void ilk_update_display_irq(struct drm_i915_private *dev_priv,
+void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 				   uint32_t interrupt_mask,
 				   uint32_t enabled_irq_mask)
+{
 	uint32_t new_val;
 		I915_WRITE(DEIMR, dev_priv->irq_mask);
 		POSTING_READ(DEIMR);
+	}
+}
-void
-ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
-{
-	ilk_update_display_irq(dev_priv, mask, mask);
-}
-void
-ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
-{
-	ilk_update_display_irq(dev_priv, mask, 0);
-}
 /**
  * ilk_update_gt_irq - update GTIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
+{
 	ilk_update_gt_irq(dev_priv, mask, 0);
+}
-static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
+static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
+{
 	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 }
-static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
+static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
+{
 	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
+}
-static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
+static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
+{
+}
 void gen6_reset_rps_interrupts(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t reg = gen6_pm_iir(dev_priv);
+	i915_reg_t reg = gen6_pm_iir(dev_priv);
 	spin_lock_irq(&dev_priv->irq_lock);
 	I915_WRITE(reg, dev_priv->pm_rps_events);
 	spin_lock_irq(&dev_priv->irq_lock);
 	dev_priv->rps.interrupts_enabled = false;
-	spin_unlock_irq(&dev_priv->irq_lock);
 	spin_unlock_irq(&dev_priv->irq_lock);
 	cancel_work_sync(&dev_priv->rps.work);
 		POSTING_READ(GEN8_DE_PORT_IMR);
+	}
+}
+/**
+ * bdw_update_pipe_irq - update DE pipe interrupt
+ * @dev_priv: driver private
+ * @pipe: pipe whose interrupt to update
+ * @interrupt_mask: mask of interrupt bits to update
+ * @enabled_irq_mask: mask of interrupt bits to enable
+ */
+void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
+			 enum pipe pipe,
+			 uint32_t interrupt_mask,
+			 uint32_t enabled_irq_mask)
+{
+	uint32_t new_val;
+	assert_spin_locked(&dev_priv->irq_lock);
+	WARN_ON(enabled_irq_mask & ~interrupt_mask);
+	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
+		return;
+	new_val = dev_priv->de_irq_mask[pipe];
+	new_val &= ~interrupt_mask;
+	new_val |= (~enabled_irq_mask & interrupt_mask);
+	if (new_val != dev_priv->de_irq_mask[pipe]) {
+		dev_priv->de_irq_mask[pipe] = new_val;
+		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+		POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
+	}
+}
 /**
  * ibx_display_interrupt_update - update SDEIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
 static void
 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 		       u32 enable_mask, u32 status_mask)
 {
-	u32 reg = PIPESTAT(pipe);
+	i915_reg_t reg = PIPESTAT(pipe);
 	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 static void
 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 		        u32 enable_mask, u32 status_mask)
 {
-	u32 reg = PIPESTAT(pipe);
+	i915_reg_t reg = PIPESTAT(pipe);
 	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 		     u32 status_mask)
+{
 	u32 enable_mask;
-	if (IS_VALLEYVIEW(dev_priv->dev))
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 							   status_mask);
 	else
 		enable_mask = status_mask << 16;
 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 		      u32 status_mask)
+{
 	u32 enable_mask;
-	if (IS_VALLEYVIEW(dev_priv->dev))
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 							   status_mask);
 	else
 		enable_mask = status_mask << 16;
  * we use as a pipe index
  */
 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	unsigned long high_frame;
-	unsigned long low_frame;
+	i915_reg_t high_frame, low_frame;
 	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 	struct intel_crtc *intel_crtc =
 		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 	const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 }
-/* raw reads, only for fast reads of display block, no need for forcewake etc. */
 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
+{
 	struct drm_device *dev = crtc->base.dev;
 	vtotal = mode->crtc_vtotal;
 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 		vtotal /= 2;
 	if (IS_GEN2(dev))
-		position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
+		position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 	else
-		position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
+		position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 	/*
 	 * On HSW, the DSL reg (0x70000) appears to return 0 if we
 	} else {
 		/* Have access to pixelcount since start of frame.
 		 * We can split this into vertical and horizontal
 		 * scanout position.
 		 */
-		position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
+		position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 		/* convert to pixel counts */
 		vbl_start *= htotal;
 		vbl_end *= htotal;
 	ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
 	ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
 	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
+}
+static bool vlv_c0_above(struct drm_i915_private *dev_priv,
+			 const struct intel_rps_ei *old,
+			 const struct intel_rps_ei *now,
+			 int threshold)
+{
+	u64 time, c0;
+	unsigned int mul = 100;
+	if (old->cz_clock == 0)
+		return false;
+	if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
+		mul <<= 8;
+	time = now->cz_clock - old->cz_clock;
+	time *= threshold * dev_priv->czclk_freq;
+	/* Workload can be split between render + media, e.g. SwapBuffers
+	 * being blitted in X after being rendered in mesa. To account for
+	 * this we need to combine both engines into our activity counter.
+	 */
+	c0 = now->render_c0 - old->render_c0;
+	c0 += now->media_c0 - old->media_c0;
+	c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
+	return c0 >= time;
+}
 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
+{
-{
+	vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
-	memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei));
+	dev_priv->rps.up_ei = dev_priv->rps.down_ei;
+}
-static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 	const struct intel_rps_ei *prev = &dev_priv->rps.ei;
 	struct intel_rps_ei now;
 	u32 events = 0;
-	if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
+	if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
 		return 0;
-	vlv_c0_read(dev_priv, &now);
-	if (now.cz_clock == 0)
-		return 0;
-	if (prev->cz_clock) {
-		u64 time, c0;
-		unsigned int mul;
+	vlv_c0_read(dev_priv, &now);
-		mul = VLV_CZ_CLOCK_TO_MILLI_SEC * 100; /* scale to threshold% */
+	if (now.cz_clock == 0)
-		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
-			mul <<= 8;
+		return 0;
-		time = now.cz_clock - prev->cz_clock;
-		time *= dev_priv->czclk_freq;
+	if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
+		if (!vlv_c0_above(dev_priv,
-		/* Workload can be split between render + media,
-		 * e.g. SwapBuffers being blitted in X after being rendered in
-		 * mesa. To account for this we need to combine both engines
-		 * into our activity counter.
+				  &dev_priv->rps.down_ei, &now,
+				  dev_priv->rps.down_threshold))
-		 */
+			events |= GEN6_PM_RP_DOWN_THRESHOLD;
-		c0 = now.render_c0 - prev->render_c0;
+		dev_priv->rps.down_ei = now;
-		c0 += now.media_c0 - prev->media_c0;
+	}
-		c0 *= mul;
+	if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
-		if (c0 > time * dev_priv->rps.up_threshold)
+		if (vlv_c0_above(dev_priv,
-			events = GEN6_PM_RP_UP_THRESHOLD;
+				 &dev_priv->rps.up_ei, &now,
-		else if (c0 < time * dev_priv->rps.down_threshold)
+				 dev_priv->rps.up_threshold))
-			events = GEN6_PM_RP_DOWN_THRESHOLD;
+			events |= GEN6_PM_RP_UP_THRESHOLD;
 	/* Speed up work cancelation during disabling rps interrupts. */
 	if (!dev_priv->rps.interrupts_enabled) {
 		spin_unlock_irq(&dev_priv->irq_lock);
 		return;
+	}
+	/*
+	 * The RPS work is synced during runtime suspend, we don't require a
+	 * wakeref. TODO: instead of disabling the asserts make sure that we
+	 * always hold an RPM reference while the work is running.
+	 */
+	DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
 	pm_iir = dev_priv->rps.pm_iir;
 	dev_priv->rps.pm_iir = 0;
 	/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
 	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 	client_boost = dev_priv->rps.client_boost;
 	/* Make sure we didn't queue anything we're not going to process. */
 	WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
 	if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
-		return;
+		goto out;
 	new_delay = clamp_t(int, new_delay, min, max);
 	intel_set_rps(dev_priv->dev, new_delay);
+	mutex_unlock(&dev_priv->rps.hw_lock);
 out:
-	mutex_unlock(&dev_priv->rps.hw_lock);
+	ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
+}
 	misccpctl = I915_READ(GEN7_MISCCPCTL);
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 	POSTING_READ(GEN7_MISCCPCTL);
 	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
-		u32 reg;
+		i915_reg_t reg;
 		slice--;
 		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
 			break;
 		dev_priv->l3_parity.which_slice &= ~(1<
-		reg = GEN7_L3CDERRST1 + (slice * 0x200);
+		reg = GEN7_L3CDERRST1(slice);
 	if (gt_iir & GT_PARITY_ERROR(dev))
 		ivybridge_parity_error_irq_handler(dev, gt_iir);
+}
+static __always_inline void
+gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir, int test_shift)
+{
+	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
+		notify_ring(ring);
+	if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
+		intel_lrc_irq_handler(ring);
+}
 static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
 				       u32 master_ctl)
+{
 	irqreturn_t ret = IRQ_NONE;
 	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
-		u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
+		u32 iir = I915_READ_FW(GEN8_GT_IIR(0));
-		if (tmp) {
-			I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
+		if (iir) {
-			ret = IRQ_HANDLED;
+			I915_WRITE_FW(GEN8_GT_IIR(0), iir);
-			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
-				intel_lrc_irq_handler(&dev_priv->ring[RCS]);
+			ret = IRQ_HANDLED;
-			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
-				notify_ring(&dev_priv->ring[RCS]);
 			gen8_cs_irq_handler(&dev_priv->ring[RCS],
-			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
+					iir, GEN8_RCS_IRQ_SHIFT);
 				intel_lrc_irq_handler(&dev_priv->ring[BCS]);
-			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
+			gen8_cs_irq_handler(&dev_priv->ring[BCS],
-				notify_ring(&dev_priv->ring[BCS]);
+					iir, GEN8_BCS_IRQ_SHIFT);
 		} else
 			DRM_ERROR("The master control interrupt lied (GT0)!\n");
+	}
-	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
-		u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
-		if (tmp) {
+	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
-			I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
-			ret = IRQ_HANDLED;
+		u32 iir = I915_READ_FW(GEN8_GT_IIR(1));
+		if (iir) {
-			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
-				intel_lrc_irq_handler(&dev_priv->ring[VCS]);
+			I915_WRITE_FW(GEN8_GT_IIR(1), iir);
-			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
+			ret = IRQ_HANDLED;
 				notify_ring(&dev_priv->ring[VCS]);
 			gen8_cs_irq_handler(&dev_priv->ring[VCS],
-			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
+					iir, GEN8_VCS1_IRQ_SHIFT);
-				intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
-			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
+			gen8_cs_irq_handler(&dev_priv->ring[VCS2],
-				notify_ring(&dev_priv->ring[VCS2]);
+					iir, GEN8_VCS2_IRQ_SHIFT);
-		} else
-			DRM_ERROR("The master control interrupt lied (GT1)!\n");
+		} else
-	}
+			DRM_ERROR("The master control interrupt lied (GT1)!\n");
 	if (master_ctl & GEN8_GT_VECS_IRQ) {
 		u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
-		if (tmp) {
+	if (master_ctl & GEN8_GT_VECS_IRQ) {
-			I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
+		u32 iir = I915_READ_FW(GEN8_GT_IIR(3));
-			ret = IRQ_HANDLED;
+		if (iir) {
+			I915_WRITE_FW(GEN8_GT_IIR(3), iir);
-			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
+			ret = IRQ_HANDLED;
-				intel_lrc_irq_handler(&dev_priv->ring[VECS]);
-			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
+			gen8_cs_irq_handler(&dev_priv->ring[VECS],
-				notify_ring(&dev_priv->ring[VECS]);
+					iir, GEN8_VECS_IRQ_SHIFT);
 		} else
 			DRM_ERROR("The master control interrupt lied (GT3)!\n");
+	}
 	u32 pipe_stats[I915_MAX_PIPES] = { };
 	int pipe;
 	spin_lock(&dev_priv->irq_lock);
 	for_each_pipe(dev_priv, pipe) {
-		int reg;
+		i915_reg_t reg;
 		u32 mask, iir_bit = 0;
 		/*
 	 * Make sure hotplug status is cleared before we clear IIR, or else we
 	 * may miss hotplug events.
 	 */
 	POSTING_READ(PORT_HOTPLUG_STAT);
-	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+	if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
 		if (hotplug_trigger) {
 	irqreturn_t ret = IRQ_NONE;
 	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
-		return IRQ_NONE;
+	disable_rpm_wakeref_asserts(dev_priv);
 	while (true) {
 		/* Find, clear, then process each source of interrupt */
 		 * signalled in iir */
 		valleyview_pipestat_irq_handler(dev, iir);
+	}
+out:
+	enable_rpm_wakeref_asserts(dev_priv);
 out:
 	return ret;
+}
 	irqreturn_t ret = IRQ_NONE;
 	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
-		return IRQ_NONE;
+	disable_rpm_wakeref_asserts(dev_priv);
 	for (;;) {
 		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
 		I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
 		POSTING_READ(GEN8_MASTER_IRQ);
+	}
 	enable_rpm_wakeref_asserts(dev_priv);
 	return ret;
+}
 static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
 				const u32 hpd[HPD_NUM_PINS])
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
+	/*
+	 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
 	 * unless we touch the hotplug register, even if hotplug_trigger is
+	 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
+	 * errors.
+	 */
+	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
+	if (!hotplug_trigger) {
+		u32 mask = PORTA_HOTPLUG_STATUS_MASK |
+			PORTD_HOTPLUG_STATUS_MASK |
+			PORTC_HOTPLUG_STATUS_MASK |
-	struct drm_i915_private *dev_priv = to_i915(dev);
+			PORTB_HOTPLUG_STATUS_MASK;
+		dig_hotplug_reg &= ~mask;
+	}
 	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
 	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
-	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
+	if (!hotplug_trigger)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe;
 	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
 	if (hotplug_trigger)
 		ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
 	if (pch_iir & SDE_AUDIO_POWER_MASK) {
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe;
 	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
 	if (hotplug_trigger)
 		ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
 	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
 	irqreturn_t ret = IRQ_NONE;
 	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
-		return IRQ_NONE;
+	disable_rpm_wakeref_asserts(dev_priv);
 	/* We get interrupts on unclaimed registers, so check for this before we
 	 * do any I915_{READ,WRITE}. */
 	if (!HAS_PCH_NOP(dev)) {
 		I915_WRITE(SDEIER, sde_ier);
 		POSTING_READ(SDEIER);
+	}
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
+	enable_rpm_wakeref_asserts(dev_priv);
 	return ret;
+}
 	u32 aux_mask = GEN8_AUX_CHANNEL_A;
 	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
-		return IRQ_NONE;
+	disable_rpm_wakeref_asserts(dev_priv);
 	if (INTEL_INFO(dev_priv)->gen >= 9)
 		aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
 			GEN9_AUX_CHANNEL_D;
 	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
 	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
 	if (!master_ctl)
+	}
 	I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+	POSTING_READ_FW(GEN8_MASTER_IRQ);
+out:
-	POSTING_READ_FW(GEN8_MASTER_IRQ);
+	enable_rpm_wakeref_asserts(dev_priv);
 	return ret;
+}
 	 * the reset in-progress bit is only ever set by code outside of this
 	 * work we don't need to worry about any other races.
 	 */
 	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
 		DRM_DEBUG_DRIVER("resetting chip\n");
+		/*
+		 * In most cases it's guaranteed that we get here with an RPM
+		 * reference held, for example because there is a pending GPU
+		 * request that won't finish until the reset is done. This
+		 * isn't the case at least when we get here by doing a
+		 * simulated reset via debugs, so get an RPM reference.
+		 */
 		intel_runtime_pm_get(dev_priv);
 		/*
 		 * All state reset _must_ be completed before we update the
 	unsigned long irqflags;
 	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
 						     DE_PIPE_VBLANK(pipe);
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	ironlake_enable_display_irq(dev_priv, bit);
+	ilk_enable_display_irq(dev_priv, bit);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned long irqflags;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
-	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
-	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
+	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	return 0;
+}
 	unsigned long irqflags;
 	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
 						     DE_PIPE_VBLANK(pipe);
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	ironlake_disable_display_irq(dev_priv, bit);
+	ilk_disable_display_irq(dev_priv, bit);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned long irqflags;
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
-	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
-	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
+	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
 #define HUNG 20
 	if (!i915.enable_hangcheck)
+		return;
+	/*
+	 * The hangcheck work is synced during runtime suspend, we don't
+	 * require a wakeref. TODO: instead of disabling the asserts make
+	 * sure that we hold a reference when this work is running.
+	 */
-		return;
+	DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
 	for_each_ring(ring, dev_priv, i) {
 		u64 acthd;
+		 *
 		 * spinlocking not required here for correctness since interrupt
 		 * setup is guaranteed to run in single-threaded context. But we
 		 * need it to make the assert_spin_locked happy. */
 		spin_lock_irq(&dev_priv->irq_lock);
-		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
+		ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
 		spin_unlock_irq(&dev_priv->irq_lock);
+	}
 	return 0;
 	u32 pipe_stats[2];
 	int pipe;
 	u16 flip_mask =
 		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
 		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+	irqreturn_t ret;
 	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
+	disable_rpm_wakeref_asserts(dev_priv);
 		return IRQ_NONE;
 	ret = IRQ_NONE;
 	iir = I915_READ16(IIR);
 	if (iir == 0)
-		return IRQ_NONE;
+		goto out;
 	while (iir & ~flip_mask) {
 		spin_lock(&dev_priv->irq_lock);
 		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
 		for_each_pipe(dev_priv, pipe) {
-			int reg = PIPESTAT(pipe);
+			i915_reg_t reg = PIPESTAT(pipe);
 			pipe_stats[pipe] = I915_READ(reg);
 			/*
 								    pipe);
+		}
 		iir = new_iir;
+	}
+	ret = IRQ_HANDLED;
+out:
-	}
+	enable_rpm_wakeref_asserts(dev_priv);
-	return IRQ_HANDLED;
+	return ret;
+}
 	int pipe, ret = IRQ_NONE;
 	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
-		return IRQ_NONE;
+	disable_rpm_wakeref_asserts(dev_priv);
 	iir = I915_READ(IIR);
 	do {
 		spin_lock(&dev_priv->irq_lock);
 		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
 		for_each_pipe(dev_priv, pipe) {
-			int reg = PIPESTAT(pipe);
+			i915_reg_t reg = PIPESTAT(pipe);
 			pipe_stats[pipe] = I915_READ(reg);
 			/* Clear the PIPE*STAT regs before the IIR */
 		 */
 		ret = IRQ_HANDLED;
 		iir = new_iir;
 	} while (iir & ~flip_mask);
+	enable_rpm_wakeref_asserts(dev_priv);
 	return ret;
+}
 		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
 	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
-		return IRQ_NONE;
+	disable_rpm_wakeref_asserts(dev_priv);
 	iir = I915_READ(IIR);
 		spin_lock(&dev_priv->irq_lock);
 		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
 		for_each_pipe(dev_priv, pipe) {
-			int reg = PIPESTAT(pipe);
+			i915_reg_t reg = PIPESTAT(pipe);
 			pipe_stats[pipe] = I915_READ(reg);
 			/*
 		 * stray interrupts.
 		 */
 		iir = new_iir;
+	}
+	enable_rpm_wakeref_asserts(dev_priv);
 	return ret;
+}
 	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
 	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
 	/* Let's track the enabled rps events */
-	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
+	if (IS_VALLEYVIEW(dev_priv))
 		/* WaGsvRC0ResidencyMethod:vlv */
-		dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
+		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
 	else
 		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_irq.c – Rev 6935 → 6937