WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem.c

 #include "i915_trace.h"
 #include "intel_drv.h"
 #include
 #include
 //#include
+#include
 #include
 extern int x86_clflush_size;
 	loff_t offset;
 	int shmem_page_offset, page_length, ret = 0;
 	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 	int prefaulted = 0;
 	int needs_clflush = 0;
-	struct scatterlist *sg;
+	struct sg_page_iter sg_iter;
-	int i;
-	user_data = (char __user *) (uintptr_t) args->data_ptr;
+	user_data = to_user_ptr(args->data_ptr);
 	remain = args->size;
 	i915_gem_object_pin_pages(obj);
-	offset = args->offset;
-	for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
+	offset = args->offset;
-		struct page *page;
 	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
-		if (i < offset >> PAGE_SHIFT)
+			 offset >> PAGE_SHIFT) {
-			continue;
+		struct page *page = sg_page_iter_page(&sg_iter);
 		shmem_page_offset = offset_in_page(offset);
 		page_length = remain;
 		if ((shmem_page_offset + page_length) > PAGE_SIZE)
 			page_length = PAGE_SIZE - shmem_page_offset;
 		page = sg_page(sg);
 		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 			(page_to_phys(page) & (1 << 17)) != 0;
 	if (args->size == 0)
 		return 0;
 	if (!access_ok(VERIFY_WRITE,
-		       (char __user *)(uintptr_t)args->data_ptr,
+		       to_user_ptr(args->data_ptr),
 		       args->size))
 		return -EFAULT;
 	int shmem_page_offset, page_length, ret = 0;
 	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 	int hit_slowpath = 0;
 	int needs_clflush_after = 0;
 	int needs_clflush_before = 0;
-	int i;
-	struct scatterlist *sg;
+	struct sg_page_iter sg_iter;
-	user_data = (char __user *) (uintptr_t) args->data_ptr;
+	user_data = to_user_ptr(args->data_ptr);
 	remain = args->size;
 	i915_gem_object_pin_pages(obj);
 	offset = args->offset;
 	obj->dirty = 1;
+	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
-	for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
+			 offset >> PAGE_SHIFT) {
-		struct page *page;
-		int partial_cacheline_write;
-		if (i < offset >> PAGE_SHIFT)
+		struct page *page = sg_page_iter_page(&sg_iter);
-			continue;
+		int partial_cacheline_write;
 		if (remain <= 0)
 		 * overcomplicate things and flush the entire patch. */
 		partial_cacheline_write = needs_clflush_before &&
 			((shmem_page_offset | page_length)
 				& (x86_clflush_size - 1));
 		page = sg_page(sg);
 		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 			(page_to_phys(page) & (1 << 17)) != 0;
 	case -EIO:
 	case -EAGAIN: /* Wedged */
 	case -ERESTARTSYS: /* Signal */
 		return (int)end;
 	case 0: /* Timeout */
-		if (timeout)
-			set_normalized_timespec(timeout, 0, 0);
 		return -ETIME;
 	default: /* Completed */
 		WARN_ON(end < 0); /* We're not aware of other errors */
 		return 0;
+	}
+}
 static void
 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
-{
-	int page_count = obj->base.size / PAGE_SIZE;
+{
-	struct scatterlist *sg;
+	struct sg_page_iter sg_iter;
-	int ret, i;
+	int ret;
 	BUG_ON(obj->madv == __I915_MADV_PURGED);
+	}
 	if (obj->madv == I915_MADV_DONTNEED)
 		obj->dirty = 0;
-	for_each_sg(obj->pages->sgl, sg, page_count, i) {
+	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
-		struct page *page = sg_page(sg);
+		struct page *page = sg_page_iter_page(&sg_iter);
 static int
 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
+{
 	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
     int page_count, i;
-	struct address_space *mapping;
 	struct sg_table *st;
 	struct scatterlist *sg;
+	struct sg_page_iter sg_iter;
 	struct page *page;
+	unsigned long last_pfn = 0;	/* suppress gcc warning */
 	gfp_t gfp;
 	/* Assert that the object is not currently in any GPU domain. As it
 	 * wasn't in the GTT, there shouldn't be any way it could have been in
 	page_count = obj->base.size / PAGE_SIZE;
 	if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
 		sg_free_table(st);
+		kfree(st);
-		kfree(st);
+        FAIL();
 		return -ENOMEM;
+	}
 	/* Get the list of pages out of our struct file.  They'll be pinned
 	 * at this point until we release them.
+	 *
+	 * Fail silently without starting the shrinker
+	 */
-	 * Fail silently without starting the shrinker
+	sg = st->sgl;
-	 */
+	st->nents = 0;
-	for_each_sg(st->sgl, sg, page_count, i) {
+	for (i = 0; i < page_count; i++) {
 		page = shmem_read_mapping_page_gfp(obj->base.filp, i, gfp);
 		if (IS_ERR(page)) {
             dbgprintf("%s invalid page %p\n", __FUNCTION__, page);
+			goto err_pages;
+		}
+		if (!i || page_to_pfn(page) != last_pfn + 1) {
-			goto err_pages;
+			if (i)
+				sg = sg_next(sg);
+			st->nents++;
+		sg_set_page(sg, page, PAGE_SIZE, 0);
+		} else {
 			sg->length += PAGE_SIZE;
+		}
 		last_pfn = page_to_pfn(page);
-		sg_set_page(sg, page, PAGE_SIZE, 0);
-	}
+	}
 	obj->pages = st;
+		sg_mark_end(sg);
+	obj->pages = st;
-//    DRM_DEBUG_KMS("%s alloc %d pages\n", __FUNCTION__, page_count);
 	return 0;
 	return 0;
+err_pages:
 	sg_mark_end(sg);
-err_pages:
+	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
-	for_each_sg(st->sgl, sg, i, page_count)
+		page_cache_release(sg_page_iter_page(&sg_iter));
-		page_cache_release(sg_page(sg));
+	sg_free_table(st);
 		i915_gem_object_move_to_inactive(obj);
+	}
 }
-static void i915_gem_reset_fences(struct drm_device *dev)
+void i915_gem_restore_fences(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int i;
-	for (i = 0; i < dev_priv->num_fence_regs; i++) {
-		struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
-		i915_gem_write_fence(dev, i, NULL);
-		if (reg->obj)
-			i915_gem_object_fence_lost(reg->obj);
-		reg->pin_count = 0;
+	for (i = 0; i < dev_priv->num_fence_regs; i++) {
-		reg->obj = NULL;
-		INIT_LIST_HEAD(®->lru_list);
 		struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
 		i915_gem_write_fence(dev, i, reg->obj);
 	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
+}
 			    mm_list)
+	{
 		obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
+	}
-	/* The fence registers are invalidated so clear them out */
-	i915_gem_reset_fences(dev);
+	i915_gem_restore_fences(dev);
+}
 /**
 			       struct drm_i915_fence_reg *fence)
+{
 	return fence - dev_priv->fence_regs;
+}
+static void i915_gem_write_fence__ipi(void *data)
+{
+    asm volatile("wbinvd");
+}
 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
 					 struct drm_i915_fence_reg *fence,
 					 bool enable)
+{
-{
+	struct drm_device *dev = obj->base.dev;
-	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int fence_reg = fence_number(dev_priv, fence);
+	/* In order to fully serialize access to the fenced region and
+	 * the update to the fence register we need to take extreme
+	 * measures on SNB+. In theory, the write to the fence register
+	 * flushes all memory transactions before, and coupled with the
+	 * mb() placed around the register write we serialise all memory
+	 * operations with respect to the changes in the tiler. Yet, on
+	 * SNB+ we need to take a step further and emit an explicit wbinvd()
+	 * on each processor in order to manually flush all memory
+	 * transactions before updating the fence register.
+	 */
-	int reg = fence_number(dev_priv, fence);
+	if (HAS_LLC(obj->base.dev))
 		on_each_cpu(i915_gem_write_fence__ipi, NULL, 1);
-	i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
+	i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL);
 	if (enable) {
-		obj->fence_reg = reg;
+		obj->fence_reg = fence_reg;
 		fence->obj = obj;
 		list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
 int
 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
+{
+	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
-	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+	struct drm_i915_fence_reg *fence;
 	int ret;
 	ret = i915_gem_object_wait_fence(obj);
 	if (ret)
 		return ret;
-	if (obj->fence_reg == I915_FENCE_REG_NONE)
-		return 0;
+	if (obj->fence_reg == I915_FENCE_REG_NONE)
 		return 0;
-	i915_gem_object_update_fence(obj,
+	fence = &dev_priv->fence_regs[obj->fence_reg];
 				     &dev_priv->fence_regs[obj->fence_reg],
-				     false);
+	i915_gem_object_fence_lost(obj);
 	 * before evicting everything in a vain attempt to find space.
 	 */
 	if (obj->base.size >
 	    (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) {
 		DRM_ERROR("Attempting to bind an object larger than the aperture\n");
+        FAIL();
 		return -E2BIG;
+	}
 	ret = i915_gem_object_get_pages(obj);
+{
 	struct drm_i915_gem_object *obj;
 	struct address_space *mapping;
 	gfp_t mask;
+	obj = i915_gem_object_alloc(dev);
 	obj = kzalloc(sizeof(*obj), GFP_KERNEL);
+	if (obj == NULL)
+    {
-	if (obj == NULL)
+        FAIL();
+		return NULL;
-		return NULL;
+    };
+	if (drm_gem_object_init(dev, &obj->base, size) != 0) {
-	if (drm_gem_object_init(dev, &obj->base, size) != 0) {
+		kfree(obj);
-		kfree(obj);
+        FAIL();
 		return NULL;
 	/* Under UMS, be paranoid and evict. */
 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		i915_gem_evict_everything(dev);
-	i915_gem_reset_fences(dev);
+		i915_gem_evict_everything(dev);
 	/* Hack!  Don't let anybody do execbuf while we don't control the chip.
 	 * We need to replace this with a semaphore, or something.
 	 * And not confound mm.suspended!
 		return -EIO;
 	if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
+		I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
+	if (HAS_PCH_NOP(dev)) {
+		u32 temp = I915_READ(GEN7_MSG_CTL);
+		temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
+		I915_WRITE(GEN7_MSG_CTL, temp);
 		I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
 	i915_gem_l3_remap(dev);
 	/*
 	 * XXX: There was some w/a described somewhere suggesting loading
 	 * contexts before PPGTT.
 	 */
 	i915_gem_context_init(dev);
+	if (dev_priv->mm.aliasing_ppgtt) {
+		ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
+		if (ret) {
-	i915_gem_init_ppgtt(dev);
+			i915_gem_cleanup_aliasing_ppgtt(dev);
+			DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
+		}
+	}
 	return 0;
+}
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
+	mutex_lock(&dev->struct_mutex);
+	if (IS_VALLEYVIEW(dev)) {
+		/* VLVA0 (potential hack), BIOS isn't actually waking us */
+		I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
+		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
+			DRM_DEBUG_DRIVER("allow wake ack timed out\n");
+	}
 	mutex_lock(&dev->struct_mutex);
+	i915_gem_init_global_gtt(dev);
 	i915_gem_init_global_gtt(dev);
 	ret = i915_gem_init_hw(dev);
 	mutex_unlock(&dev->struct_mutex);
 	if (ret) {
 		i915_gem_cleanup_aliasing_ppgtt(dev);
 		return ret;
+	}
     return 0;
+}
 			   _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
+    }
+    dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
-    dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
+	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
 		dev_priv->num_fence_regs = 32;
-    if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
         dev_priv->num_fence_regs = 16;
     else
+        dev_priv->num_fence_regs = 8;
-        dev_priv->num_fence_regs = 8;
     /* Initialize fence registers to zero */
-    /* Initialize fence registers to zero */
+	INIT_LIST_HEAD(&dev_priv->mm.fence_list);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gem.c – Rev 3482 → 3746