WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem.c

  * Authors:
  *    Eric Anholt
+ *
  */
-#include "drmP.h"
-#include "drm.h"
+#include
-#include "i915_drm.h"
+#include
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include "intel_drv.h"
 //#include
 #define I915_EXEC_CONSTANTS_MASK        (3<<6)
 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
 #define I915_EXEC_CONSTANTS_ABSOLUTE    (1<<6)
 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
-static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
-static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
-							  bool write);
-static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
-								  uint64_t offset,
-								  uint64_t size);
-static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
+static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
 						    unsigned alignment,
-						    bool map_and_fenceable);
-static void i915_gem_clear_fence_reg(struct drm_device *dev,
+						    bool map_and_fenceable,
-				     struct drm_i915_fence_reg *reg);
+						    bool nonblocking);
 static int i915_gem_phys_pwrite(struct drm_device *dev,
 				struct drm_i915_gem_object *obj,
 				struct drm_i915_gem_pwrite *args,
-				struct drm_file *file);
-static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
+				struct drm_file *file);
+static void i915_gem_write_fence(struct drm_device *dev, int reg,
+				 struct drm_i915_gem_object *obj);
+static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
+					 struct drm_i915_fence_reg *fence,
+					 bool enable);
+static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
+static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
+static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
+static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
+{
+	if (obj->tiling_mode)
+		i915_gem_release_mmap(obj);
+	/* As we do not have an associated fence register, we will force
+	 * a tiling change if we ever need to acquire one.
+	 */
+	obj->fence_dirty = false;
-//static int i915_gem_inactive_shrink(struct shrinker *shrinker,
+	obj->fence_reg = I915_FENCE_REG_NONE;
 //                   struct shrink_control *sc);
 /* some bookkeeping */
 	int ret;
 	if (!atomic_read(&dev_priv->mm.wedged))
+		return 0;
+	/*
+	 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
+	 * userspace. If it takes that long something really bad is going on and
-		return 0;
+	 * we should simply try to bail out and fail as gracefully as possible.
+	 */
+	ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
+	if (ret == 0) {
+		DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
-	ret = wait_for_completion_interruptible(x);
+		return -EIO;
+	} else if (ret < 0) {
-	if (ret)
+		return ret;
 		return ret;
 	if (atomic_read(&dev_priv->mm.wedged)) {
 #endif
 static inline bool
 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 {
-	return obj->gtt_space && !obj->active && obj->pin_count == 0;
+	return obj->gtt_space && !obj->active;
-}
-void i915_gem_do_init(struct drm_device *dev,
-		      unsigned long start,
-		      unsigned long mappable_end,
-		      unsigned long end)
-{
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
-	dev_priv->mm.gtt_start = start;
-	dev_priv->mm.gtt_mappable_end = mappable_end;
-	dev_priv->mm.gtt_end = end;
-	dev_priv->mm.gtt_total = end - start;
-	dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
-	/* Take over this portion of the GTT */
 	intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 #if 0
 int
+i915_gem_init_ioctl(struct drm_device *dev, void *data,
+		    struct drm_file *file)
+{
-i915_gem_init_ioctl(struct drm_device *dev, void *data,
+	struct drm_i915_gem_init *args = data;
 		    struct drm_file *file)
 	if (drm_core_check_feature(dev, DRIVER_MODESET))
+		return -ENODEV;
+	if (args->gtt_start >= args->gtt_end ||
+	    (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
-	struct drm_i915_gem_init *args = data;
+		return -EINVAL;
+	/* GEM with user mode setting was never supported on ilk and later. */
-	if (args->gtt_start >= args->gtt_end ||
+	if (INTEL_INFO(dev)->gen >= 5)
-	    (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
+		return -ENODEV;
 		return -EINVAL;
 	mutex_lock(&dev->struct_mutex);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_get_aperture *args = data;
 	struct drm_i915_gem_object *obj;
 	size_t pinned;
 	pinned = 0;
 	mutex_lock(&dev->struct_mutex);
+	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
-	list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
+		if (obj->pin_count)
 		pinned += obj->gtt_space->size;
 	mutex_unlock(&dev->struct_mutex);
 	args->aper_size = dev_priv->mm.gtt_total;
 	args->aper_available_size = args->aper_size - pinned;
 	return 0;
 }
 #if 0
 static int
-int i915_gem_create(struct drm_file *file,
+i915_gem_create(struct drm_file *file,
 		struct drm_device *dev,
 int
 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 		      struct drm_file *file)
+{
 	struct drm_i915_gem_create *args = data;
 	return i915_gem_create(file, dev,
 			       args->size, &args->handle);
+}
 	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 		obj->tiling_mode != I915_TILING_NONE;
 }
-static inline void
+static inline int
-slow_shmem_copy(struct page *dst_page,
-		int dst_offset,
-		struct page *src_page,
+__copy_to_user_swizzled(char __user *cpu_vaddr,
-		int src_offset,
+			const char *gpu_vaddr, int gpu_offset,
 		int length)
 {
-	char *dst_vaddr, *src_vaddr;
+	int ret, cpu_offset = 0;
+	while (length > 0) {
+		int cacheline_end = ALIGN(gpu_offset + 1, 64);
+		int this_length = min(cacheline_end - gpu_offset, length);
+		int swizzled_gpu_offset = gpu_offset ^ 64;
+		ret = __copy_to_user(cpu_vaddr + cpu_offset,
+				     gpu_vaddr + swizzled_gpu_offset,
-	dst_vaddr = kmap(dst_page);
+				     this_length);
-	src_vaddr = kmap(src_page);
+		if (ret)
 			return ret + length;
-	memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
-	kunmap(src_page);
-	kunmap(dst_page);
-}
-static inline void
-slow_shmem_bit17_copy(struct page *gpu_page,
-		      int gpu_offset,
-		      struct page *cpu_page,
-		      int cpu_offset,
-		      int length,
-		      int is_read)
-{
-	char *gpu_vaddr, *cpu_vaddr;
-	/* Use the unswizzled path if this page isn't affected. */
-	if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
-		if (is_read)
+		cpu_offset += this_length;
+		gpu_offset += this_length;
+		length -= this_length;
-			return slow_shmem_copy(cpu_page, cpu_offset,
+	}
+	return 0;
-					       gpu_page, gpu_offset, length);
+}
-		else
-			return slow_shmem_copy(gpu_page, gpu_offset,
-					       cpu_page, cpu_offset, length);
 static inline int
-	gpu_vaddr = kmap(gpu_page);
+__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
-	cpu_vaddr = kmap(cpu_page);
+			  const char __user *cpu_vaddr,
-	/* Copy the data, XORing A6 with A17 (1). The user already knows he's
-	 * XORing with the other bits (A9 for Y, A9 and A10 for X)
-	 */
-	while (length > 0) {
-		int cacheline_end = ALIGN(gpu_offset + 1, 64);
+			  int length)
 		int this_length = min(cacheline_end - gpu_offset, length);
-		int swizzled_gpu_offset = gpu_offset ^ 64;
+	int ret, cpu_offset = 0;
+	while (length > 0) {
+		int cacheline_end = ALIGN(gpu_offset + 1, 64);
-		if (is_read) {
+		int this_length = min(cacheline_end - gpu_offset, length);
-			memcpy(cpu_vaddr + cpu_offset,
+		int swizzled_gpu_offset = gpu_offset ^ 64;
 			       gpu_vaddr + swizzled_gpu_offset,
-			       this_length);
+		ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
+			       cpu_vaddr + cpu_offset,
+			       this_length);
+		if (ret)
+			return ret + length;
+		cpu_offset += this_length;
+		gpu_offset += this_length;
+		length -= this_length;
+	}
+	return 0;
+}
+/* Per-page copy function for the shmem pread fastpath.
+ * Flushes invalid cachelines before reading the target if
+ * needs_clflush is set. */
+static int
+shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
+		 char __user *user_data,
+		 bool page_do_bit17_swizzling, bool needs_clflush)
+{
+		char *vaddr;
+		int ret;
-		} else {
+	if (unlikely(page_do_bit17_swizzling))
+		return -EINVAL;
+		vaddr = kmap_atomic(page);
+	if (needs_clflush)
+		drm_clflush_virt_range(vaddr + shmem_page_offset,
+				       page_length);
+		ret = __copy_to_user_inatomic(user_data,
+				      vaddr + shmem_page_offset,
+					      page_length);
+		kunmap_atomic(vaddr);
+	return ret ? -EFAULT : 0;
+}
+static void
+shmem_clflush_swizzled_range(char *addr, unsigned long length,
+			     bool swizzled)
+{
+	if (unlikely(swizzled)) {
+		unsigned long start = (unsigned long) addr;
+		unsigned long end = (unsigned long) addr + length;
+		/* For swizzling simply ensure that we always flush both
+		 * channels. Lame, but simple and it works. Swizzled
+		 * pwrite/pread is far from a hotpath - current userspace
+		 * doesn't use it at all. */
+		start = round_down(start, 128);
+		end = round_up(end, 128);
+		drm_clflush_virt_range((void *)start, end - start);
+	} else {
+		drm_clflush_virt_range(addr, length);
+	}
+}
+/* Only difference to the fast-path function is that this can handle bit17
+ * and uses non-atomic copy and kmap functions. */
+static int
+shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
+		 char __user *user_data,
+		 bool page_do_bit17_swizzling, bool needs_clflush)
+{
+	char *vaddr;
+	int ret;
+	vaddr = kmap(page);
+	if (needs_clflush)
+		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
+					     page_length,
-			memcpy(gpu_vaddr + swizzled_gpu_offset,
+					     page_do_bit17_swizzling);
+	if (page_do_bit17_swizzling)
-			       cpu_vaddr + cpu_offset,
+		ret = __copy_to_user_swizzled(user_data,
-			       this_length);
-		}
-		cpu_offset += this_length;
-		gpu_offset += this_length;
-		length -= this_length;
 					      vaddr, shmem_page_offset,
+					      page_length);
-	kunmap(cpu_page);
+	else
-	kunmap(gpu_page);
+		ret = __copy_to_user(user_data,
 				     vaddr + shmem_page_offset,
 				     page_length);
-/**
+	kunmap(page);
  * This is the fast shmem pread path, which attempts to copy_from_user directly
- * from the backing pages of the object to the user's address space.  On a
+	return ret ? - EFAULT : 0;
+}
- * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
+static int
- */
+i915_gem_shmem_pread(struct drm_device *dev,
+			  struct drm_i915_gem_object *obj,
+			  struct drm_i915_gem_pread *args,
+			  struct drm_file *file)
 static int
-i915_gem_shmem_pread_fast(struct drm_device *dev,
+	char __user *user_data;
+	ssize_t remain;
+	loff_t offset;
+	int shmem_page_offset, page_length, ret = 0;
+	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
+	int hit_slowpath = 0;
+	int prefaulted = 0;
+	int needs_clflush = 0;
+	struct scatterlist *sg;
+	int i;
+	user_data = (char __user *) (uintptr_t) args->data_ptr;
+	remain = args->size;
+	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
+	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
+		/* If we're not in the cpu read domain, set ourself into the gtt
+		 * read domain and manually flush cachelines (if required). This
+		 * optimizes for the case when the gpu will dirty the data
+		 * anyway again before the next pread happens. */
+		if (obj->cache_level == I915_CACHE_NONE)
+			needs_clflush = 1;
-			  struct drm_i915_gem_object *obj,
+		if (obj->gtt_space) {
-			  struct drm_i915_gem_pread *args,
+			ret = i915_gem_object_set_to_gtt_domain(obj, false);
-			  struct drm_file *file)
+			if (ret)
+				return ret;
+		}
-{
+	}
+	ret = i915_gem_object_get_pages(obj);
-	struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
+	if (ret)
-	ssize_t remain;
+		return ret;
 	loff_t offset;
-	char __user *user_data;
+	i915_gem_object_pin_pages(obj);
 	int page_offset, page_length;
 	offset = args->offset;
-	user_data = (char __user *) (uintptr_t) args->data_ptr;
-	remain = args->size;
+	for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
+		struct page *page;
-	offset = args->offset;
+		if (i < offset >> PAGE_SHIFT)
+			continue;
+		if (remain <= 0)
+			break;
+		/* Operation in this page
-	while (remain > 0) {
+		 *
-		struct page *page;
+		 * shmem_page_offset = offset within page in shmem file
+		 * page_length = bytes to copy for this page
-		char *vaddr;
+		 */
+		shmem_page_offset = offset_in_page(offset);
+		page_length = remain;
-		int ret;
+		if ((shmem_page_offset + page_length) > PAGE_SIZE)
+			page_length = PAGE_SIZE - shmem_page_offset;
+		page = sg_page(sg);
-		/* Operation in this page
+		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
+			(page_to_phys(page) & (1 << 17)) != 0;
-		 *
+		ret = shmem_pread_fast(page, shmem_page_offset, page_length,
+				       user_data, page_do_bit17_swizzling,
+				       needs_clflush);
+		if (ret == 0)
+			goto next_page;
+		hit_slowpath = 1;
+		mutex_unlock(&dev->struct_mutex);
 		 * page_offset = offset within page
-		 * page_length = bytes to copy for this page
+		if (!prefaulted) {
-		 */
+			ret = fault_in_multipages_writeable(user_data, remain);
-		page_offset = offset_in_page(offset);
+			/* Userspace is tricking us, but we've already clobbered
-		page_length = remain;
+			 * its pages with the prefault and promised to write the
-		if ((page_offset + remain) > PAGE_SIZE)
+			 * data up to the first fault. Hence ignore any errors
-			page_length = PAGE_SIZE - page_offset;
+			 * and just continue. */
 			(void)ret;
+			prefaulted = 1;
+		}
+		ret = shmem_pread_slow(page, shmem_page_offset, page_length,
+				       user_data, page_do_bit17_swizzling,
+				       needs_clflush);
+		mutex_lock(&dev->struct_mutex);
+next_page:
+		mark_page_accessed(page);
+		if (ret)
+			goto out;
+		remain -= page_length;
+		user_data += page_length;
+		offset += page_length;
+	}
+out:
+	i915_gem_object_unpin_pages(obj);
+	if (hit_slowpath) {
+		/* Fixup: Kill any reinstated backing storage pages */
+		if (obj->madv == __I915_MADV_PURGED)
-		page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
+			i915_gem_object_truncate(obj);
+	}
+	return ret;
+}
+/**
+ * Reads data from the object referenced by handle.
+ *
+ * On error, the contents of *data are undefined.
+ */
+int
+i915_gem_pread_ioctl(struct drm_device *dev, void *data,
+		     struct drm_file *file)
+{
+	struct drm_i915_gem_pread *args = data;
+	struct drm_i915_gem_object *obj;
+	int ret = 0;
+	if (args->size == 0)
+		return 0;
+	if (!access_ok(VERIFY_WRITE,
+		       (char __user *)(uintptr_t)args->data_ptr,
+		       args->size))
+		return -EFAULT;
+	ret = i915_mutex_lock_interruptible(dev);
+	if (ret)
+		return ret;
+	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
+	if (&obj->base == NULL) {
+		ret = -ENOENT;
+		goto unlock;
+	}
+	/* Bounds check source.  */
+	if (args->offset > obj->base.size ||
+	    args->size > obj->base.size - args->offset) {
+		ret = -EINVAL;
+		goto out;
+	}
+	/* prime objects have no backing filp to GEM pread/pwrite
+	 * pages from.
+	 */
+	if (!obj->base.filp) {
+		ret = -EINVAL;
+		goto out;
+	}
+	trace_i915_gem_object_pread(obj, args->offset, args->size);
+	ret = i915_gem_shmem_pread(dev, obj, args, file);
+out:
+	drm_gem_object_unreference(&obj->base);
+unlock:
+	mutex_unlock(&dev->struct_mutex);
+	return ret;
+}
+/* This is the fast write path which cannot handle
-		if (IS_ERR(page))
+ * page faults in the source data
-			return PTR_ERR(page);
+ */
-		vaddr = kmap_atomic(page);
-		ret = __copy_to_user_inatomic(user_data,
-					      vaddr + page_offset,
+static inline int
-					      page_length);
+fast_user_write(struct io_mapping *mapping,
-		kunmap_atomic(vaddr);
+		loff_t page_base, int page_offset,
+		char __user *user_data,
-		mark_page_accessed(page);
+		int length)
-		page_cache_release(page);
+{
-		if (ret)
+	void __iomem *vaddr_atomic;
-			return -EFAULT;
+	void *vaddr;
-		remain -= page_length;
+	unsigned long unwritten;
-		user_data += page_length;
 		offset += page_length;
-	}
+	vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
-	return 0;
+	/* We can use the cpu mem copy function because this is X86. */
-}
+	vaddr = (void __force*)vaddr_atomic + page_offset;
-/**
- * This is the fallback shmem pread path, which allocates temporary storage
- * in kernel space to copy_to_user into outside of the struct_mutex, so we
+	unwritten = __copy_from_user_inatomic_nocache(vaddr,
+						      user_data, length);
+	io_mapping_unmap_atomic(vaddr_atomic);
+	return unwritten;
+}
+/**
+ * This is the fast pwrite path, where we copy the data directly from the
+ * user into the GTT, uncached.
+ */
+static int
+i915_gem_gtt_pwrite_fast(struct drm_device *dev,
+			 struct drm_i915_gem_object *obj,
- * can copy out of the object's backing pages while holding the struct mutex
+			 struct drm_i915_gem_pwrite *args,
- * and not take page faults.
- */
-static int
-i915_gem_shmem_pread_slow(struct drm_device *dev,
-			  struct drm_i915_gem_object *obj,
-			  struct drm_i915_gem_pread *args,
-			  struct drm_file *file)
+			 struct drm_file *file)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	ssize_t remain;
-{
+	loff_t offset, page_base;
+	char __user *user_data;
+	int page_offset, page_length, ret;
+	ret = i915_gem_object_pin(obj, 0, true, true);
-	struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
+	if (ret)
-	struct mm_struct *mm = current->mm;
+		goto out;
+	ret = i915_gem_object_set_to_gtt_domain(obj, true);
-	struct page **user_pages;
-	ssize_t remain;
-	loff_t offset, pinned_pages, i;
+	if (ret)
-	loff_t first_data_page, last_data_page, num_pages;
+		goto out_unpin;
-	int shmem_page_offset;
+	ret = i915_gem_object_put_fence(obj);
-	int data_page_index, data_page_offset;
+	if (ret)
-	int page_length;
+		goto out_unpin;
 	int ret;
-	uint64_t data_ptr = args->data_ptr;
+	user_data = (char __user *) (uintptr_t) args->data_ptr;
-	int do_bit17_swizzling;
+	remain = args->size;
+	offset = obj->gtt_offset + args->offset;
+	while (remain > 0) {
+		/* Operation in this page
+		 *
+		 * page_base = page offset within aperture
+		 * page_offset = offset within page
+		 * page_length = bytes to copy for this page
+		 */
+		page_base = offset & PAGE_MASK;
+		page_offset = offset_in_page(offset);
+		page_length = remain;
+		if ((page_offset + remain) > PAGE_SIZE)
+			page_length = PAGE_SIZE - page_offset;
+		/* If we get a fault while copying data, then (presumably) our
+		 * source page isn't available.  Return the error and we'll
+		 * retry in the slow path.
+		 */
+		if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
+				    page_offset, user_data, page_length)) {
+			ret = -EFAULT;
+			goto out_unpin;
+		}
+		remain -= page_length;
+		user_data += page_length;
+		offset += page_length;
+	}
+out_unpin:
+	i915_gem_object_unpin(obj);
+out:
+	return ret;
+}
+/* Per-page copy function for the shmem pwrite fastpath.
+ * Flushes invalid cachelines before writing to the target if
+ * needs_clflush_before is set and flushes out any written cachelines after
+ * writing if needs_clflush is set. */
+static int
+shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
+		  char __user *user_data,
+		  bool page_do_bit17_swizzling,
+		  bool needs_clflush_before,
+		  bool needs_clflush_after)
+{
+	char *vaddr;
+	int ret;
+	if (unlikely(page_do_bit17_swizzling))
+		return -EINVAL;
+	vaddr = kmap_atomic(page);
+	if (needs_clflush_before)
+		drm_clflush_virt_range(vaddr + shmem_page_offset,
+				       page_length);
+	ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
+						user_data,
+						page_length);
+	if (needs_clflush_after)
+		drm_clflush_virt_range(vaddr + shmem_page_offset,
-	remain = args->size;
+				       page_length);
+	kunmap_atomic(vaddr);
+	return ret ? -EFAULT : 0;
+}
+/* Only difference to the fast-path function is that this can handle bit17
+ * and uses non-atomic copy and kmap functions. */
+static int
+shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
+		  char __user *user_data,
+		  bool page_do_bit17_swizzling,
+		  bool needs_clflush_before,
+		  bool needs_clflush_after)
+{
+	char *vaddr;
+	int ret;
+	vaddr = kmap(page);
+	if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
+		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
+					     page_length,
+					     page_do_bit17_swizzling);
+	if (page_do_bit17_swizzling)
+		ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
+						user_data,
+						page_length);
+	else
+		ret = __copy_from_user(vaddr + shmem_page_offset,
+				       user_data,
+				       page_length);
+	if (needs_clflush_after)
+		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
+					     page_length,
+					     page_do_bit17_swizzling);
+	kunmap(page);
+	return ret ? -EFAULT : 0;
+}
+static int
+i915_gem_shmem_pwrite(struct drm_device *dev,
+		      struct drm_i915_gem_object *obj,
+		      struct drm_i915_gem_pwrite *args,
+		      struct drm_file *file)
 	/* Pin the user pages containing the data.  We can't fault while
+	ssize_t remain;
+	loff_t offset;
+	char __user *user_data;
+	int shmem_page_offset, page_length, ret = 0;
+	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
+	int hit_slowpath = 0;
+	int needs_clflush_after = 0;
+	int needs_clflush_before = 0;
+	int i;
+	struct scatterlist *sg;
-	 * holding the struct mutex, yet we want to hold it while
+	user_data = (char __user *) (uintptr_t) args->data_ptr;
-	 * dereferencing the user data.
+	remain = args->size;
 	 */
+	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
-	first_data_page = data_ptr / PAGE_SIZE;
-	last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
+	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
+		/* If we're not in the cpu write domain, set ourself into the gtt
+		 * write domain and manually flush cachelines (if required). This
+		 * optimizes for the case when the gpu will use the data
+		 * right away and we therefore have to clflush anyway. */
+		if (obj->cache_level == I915_CACHE_NONE)
+			needs_clflush_after = 1;
+		if (obj->gtt_space) {
-	num_pages = last_data_page - first_data_page + 1;
+			ret = i915_gem_object_set_to_gtt_domain(obj, true);
 			if (ret)
-	user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
+				return ret;
-	if (user_pages == NULL)
-		return -ENOMEM;
+		}
 	mutex_unlock(&dev->struct_mutex);
-	down_read(&mm->mmap_sem);
+	/* Same trick applies for invalidate partially written cachelines before
-	pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
-				      num_pages, 1, 0, user_pages, NULL);
-	up_read(&mm->mmap_sem);
+	 * writing.  */
-	mutex_lock(&dev->struct_mutex);
+	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
-	if (pinned_pages < num_pages) {
+	    && obj->cache_level == I915_CACHE_NONE)
-		ret = -EFAULT;
-		goto out;
+		needs_clflush_before = 1;
+	ret = i915_gem_object_get_pages(obj);
+	if (ret)
-	}
+		return ret;
+	i915_gem_object_pin_pages(obj);
+	offset = args->offset;
+	obj->dirty = 1;
+	for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
+		struct page *page;
+		int partial_cacheline_write;
-	ret = i915_gem_object_set_cpu_read_domain_range(obj,
-							args->offset,
+		if (i < offset >> PAGE_SHIFT)
-							args->size);
+			continue;
-	if (ret)
-		goto out;
-	do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
+		if (remain <= 0)
-	offset = args->offset;
-	while (remain > 0) {
-		struct page *page;
+			break;
-		/* Operation in this page
-		 *
+		/* Operation in this page
-		 * shmem_page_offset = offset within page in shmem file
+		 *
-		 * data_page_index = page number in get_user_pages return
+		 * shmem_page_offset = offset within page in shmem file
+		 * page_length = bytes to copy for this page
+		 */
+		shmem_page_offset = offset_in_page(offset);
 		 * data_page_offset = offset with data_page_index page.
+		page_length = remain;
+		if ((shmem_page_offset + page_length) > PAGE_SIZE)
-		 * page_length = bytes to copy for this page
+			page_length = PAGE_SIZE - shmem_page_offset;
 		 */
-		shmem_page_offset = offset_in_page(offset);
+		/* If we don't overwrite a cacheline completely we need to be
-		data_page_index = data_ptr / PAGE_SIZE - first_data_page;
+		 * careful to have up-to-date data by first clflushing. Don't
-		data_page_offset = offset_in_page(data_ptr);
+		 * overcomplicate things and flush the entire patch. */
 		partial_cacheline_write = needs_clflush_before &&
-		page_length = remain;
+			((shmem_page_offset | page_length)
+				& (boot_cpu_data.x86_clflush_size - 1));
+		page = sg_page(sg);
+		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
-		if ((shmem_page_offset + page_length) > PAGE_SIZE)
+			(page_to_phys(page) & (1 << 17)) != 0;
+		ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
+					user_data, page_do_bit17_swizzling,
-			page_length = PAGE_SIZE - shmem_page_offset;
+					partial_cacheline_write,
-		if ((data_page_offset + page_length) > PAGE_SIZE)
+					needs_clflush_after);
+		if (ret == 0)
-			page_length = PAGE_SIZE - data_page_offset;
+			goto next_page;
+		hit_slowpath = 1;
+		mutex_unlock(&dev->struct_mutex);
-		page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
+		ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
-		if (IS_ERR(page)) {
+					user_data, page_do_bit17_swizzling,
+					partial_cacheline_write,
+					needs_clflush_after);
+		mutex_lock(&dev->struct_mutex);
+next_page:
+		set_page_dirty(page);
+		mark_page_accessed(page);
+		if (ret)
+			goto out;
+		remain -= page_length;
+		user_data += page_length;
+		offset += page_length;
+	}
+out:
+	i915_gem_object_unpin_pages(obj);
+	if (hit_slowpath) {
+		/* Fixup: Kill any reinstated backing storage pages */
+		if (obj->madv == __I915_MADV_PURGED)
+			i915_gem_object_truncate(obj);
+		/* and flush dirty cachelines in case the object isn't in the cpu write
+		 * domain anymore. */
+		if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
+			i915_gem_clflush_object(obj);
+			intel_gtt_chipset_flush();
+		}
+	}
+	if (needs_clflush_after)
+		intel_gtt_chipset_flush();
+	return ret;
+}
+/**
+ * Writes data to the object referenced by handle.
+ *
+ * On error, the contents of the buffer that were to be modified are undefined.
+ */
+int
+i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
+		      struct drm_file *file)
+{
+	struct drm_i915_gem_pwrite *args = data;
+	struct drm_i915_gem_object *obj;
+	int ret;
+	if (args->size == 0)
+		return 0;
+	if (!access_ok(VERIFY_READ,
+		       (char __user *)(uintptr_t)args->data_ptr,
+		       args->size))
+		return -EFAULT;
+	ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
+					   args->size);
+	if (ret)
+		return -EFAULT;
+	ret = i915_mutex_lock_interruptible(dev);
+	if (ret)
+		return ret;
+	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
+	if (&obj->base == NULL) {
+		ret = -ENOENT;
+		goto unlock;
+	}
+	/* Bounds check destination. */
+	if (args->offset > obj->base.size ||
+	    args->size > obj->base.size - args->offset) {
+		ret = -EINVAL;
+		goto out;
+	}
+	/* prime objects have no backing filp to GEM pread/pwrite
+	 * pages from.
+	 */
+	if (!obj->base.filp) {
-			ret = PTR_ERR(page);
+		ret = -EINVAL;
+		goto out;
+	}
+	trace_i915_gem_object_pwrite(obj, args->offset, args->size);
+	ret = -EFAULT;
+	/* We can only do the GTT pwrite on untiled buffers, as otherwise
+	 * it would end up going through the fenced access, and we'll get
+	 * different detiling behavior between reading and writing.
+	 * pread/pwrite currently are reading and writing from the CPU
+	 * perspective, requiring manual detiling by the client.
+	 */
+	if (obj->phys_obj) {
+		ret = i915_gem_phys_pwrite(dev, obj, args, file);
+		goto out;
+	}
+	if (obj->cache_level == I915_CACHE_NONE &&
+	    obj->tiling_mode == I915_TILING_NONE &&
+	    obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
+		ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
+		/* Note that the gtt paths might fail with non-page-backed user
+		 * pointers (e.g. gtt mappings when moving data between
+		 * textures). Fallback to the shmem path in that case. */
+	}
+	if (ret == -EFAULT || ret == -ENOSPC)
+		ret = i915_gem_shmem_pwrite(dev, obj, args, file);
+out:
+	drm_gem_object_unreference(&obj->base);
+unlock:
+	mutex_unlock(&dev->struct_mutex);
+	return ret;
+}
+#endif
+int
+i915_gem_check_wedge(struct drm_i915_private *dev_priv,
+		     bool interruptible)
+{
+	if (atomic_read(&dev_priv->mm.wedged)) {
+		struct completion *x = &dev_priv->error_completion;
+		bool recovery_complete;
+		unsigned long flags;
+		/* Give the error handler a chance to run. */
+		spin_lock_irqsave(&x->wait.lock, flags);
+		recovery_complete = x->done > 0;
+		spin_unlock_irqrestore(&x->wait.lock, flags);
+		/* Non-interruptible callers can't handle -EAGAIN, hence return
+		 * -EIO unconditionally for these. */
+		if (!interruptible)
+			return -EIO;
+		/* Recovery complete, but still wedged means reset failure. */
+		if (recovery_complete)
+			return -EIO;
+		return -EAGAIN;
+	}
+	return 0;
+}
+/*
+ * Compare seqno against outstanding lazy request. Emit a request if they are
+ * equal.
+ */
+static int
+i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
+{
+	int ret;
+	BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
+	ret = 0;
+	if (seqno == ring->outstanding_lazy_request)
+		ret = i915_add_request(ring, NULL, NULL);
+	return ret;
+}
+/**
+ * __wait_seqno - wait until execution of seqno has finished
+ * @ring: the ring expected to report seqno
+ * @seqno: duh!
+ * @interruptible: do an interruptible wait (normally yes)
+ * @timeout: in - how long to wait (NULL forever); out - how much time remaining
+ *
+ * Returns 0 if the seqno was found within the alloted time. Else returns the
+ * errno with remaining time filled in timeout argument.
+ */
+static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
+			bool interruptible, struct timespec *timeout)
+{
+	drm_i915_private_t *dev_priv = ring->dev->dev_private;
+	struct timespec before, now, wait_time={1,0};
+	unsigned long timeout_jiffies;
+	long end;
+	bool wait_forever = true;
+	int ret;
+	if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
+		return 0;
+	trace_i915_gem_request_wait_begin(ring, seqno);
+	if (timeout != NULL) {
+		wait_time = *timeout;
+		wait_forever = false;
+	}
+//   timeout_jiffies = timespec_to_jiffies(&wait_time);
+	if (WARN_ON(!ring->irq_get(ring)))
+		return -ENODEV;
+#if 0
+    /* Record current time in case interrupted by signal, or wedged * */
+	getrawmonotonic(&before);
+#define EXIT_COND \
+	(i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
+	atomic_read(&dev_priv->mm.wedged))
+	do {
+			end = wait_event_timeout(ring->irq_queue, EXIT_COND,
+						 timeout_jiffies);
+		ret = i915_gem_check_wedge(dev_priv, interruptible);
+		if (ret)
+			end = ret;
+	} while (end == 0 && wait_forever);
+	getrawmonotonic(&now);
+	ring->irq_put(ring);
+	trace_i915_gem_request_wait_end(ring, seqno);
+#undef EXIT_COND
+	if (timeout) {
+//       struct timespec sleep_time = timespec_sub(now, before);
+//       *timeout = timespec_sub(*timeout, sleep_time);
+	}
+	switch (end) {
+	case -EIO:
+	case -EAGAIN: /* Wedged */
+	case -ERESTARTSYS: /* Signal */
+		return (int)end;
+	case 0: /* Timeout */
+//		if (timeout)
+//			set_normalized_timespec(timeout, 0, 0);
+		return -ETIME;
+	default: /* Completed */
+		WARN_ON(end < 0); /* We're not aware of other errors */
+		return 0;
+	}
+#endif
+#define EXIT_COND \
+    (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
+    atomic_read(&dev_priv->mm.wedged))
+    wait_event(ring->irq_queue, EXIT_COND);
+/**
+ * i915_gem_release_mmap - remove physical page mappings
+ * @obj: obj in question
+ *
+ * Preserve the reservation of the mmapping with the DRM core code, but
+ * relinquish ownership of the pages back to the system.
+ *
+ * It is vital that we remove the page mapping if we have mapped a tiled
+ * object through the GTT and then lose the fence register due to
+ * resource pressure. Similarly if the object has been moved out of the
+ * aperture, than pages mapped into userspace must be revoked. Removing the
+ * mapping will then trigger a page fault on the next user access, allowing
+ * fixup by i915_gem_fault().
+ */
+void
+i915_gem_release_mmap(struct drm_i915_gem_object *obj)
+{
+	if (!obj->fault_mappable)
+		return;
+	if (obj->base.dev->dev_mapping)
 //		unmap_mapping_range(obj->base.dev->dev_mapping,
 //				    (loff_t)obj->base.map_list.hash.key<
 //				    obj->base.size, 1);
 	 * the power-of-tile object size.
 	 */
 	return i915_gem_get_gtt_size(dev, size, tiling_mode);
+}
+/* Immediately discard the backing storage */
+static void
+i915_gem_object_truncate(struct drm_i915_gem_object *obj)
+{
+//	struct inode *inode;
+//	i915_gem_object_free_mmap_offset(obj);
+//	if (obj->base.filp == NULL)
+//		return;
+	/* Our goal here is to return as much of the memory as
+	 * is possible back to the system as we are called from OOM.
+	 * To do this we must instruct the shmfs to drop all of its
+	 * backing pages, *now*.
+	 */
+//	inode = obj->base.filp->f_path.dentry->d_inode;
+//	shmem_truncate_range(inode, 0, (loff_t)-1);
+	obj->madv = __I915_MADV_PURGED;
+}
+static inline int
+i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
+{
+	return obj->madv == I915_MADV_DONTNEED;
+}
+static void
+i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
+{
+	int ret, i;
+	BUG_ON(obj->madv == __I915_MADV_PURGED);
+	ret = i915_gem_object_set_to_cpu_domain(obj, true);
+	if (ret) {
+		/* In the event of a disaster, abandon all caches and
+		 * hope for the best.
+		 */
+		WARN_ON(ret != -EIO);
+		i915_gem_clflush_object(obj);
+		obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
+	}
+	if (obj->madv == I915_MADV_DONTNEED)
+		obj->dirty = 0;
+    for (i = 0; i < obj->pages.nents; i++)
+        FreePage(obj->pages.page[i]);
+	obj->dirty = 0;
+	kfree(obj->pages.page);
+}
+static int
+i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
+{
+	const struct drm_i915_gem_object_ops *ops = obj->ops;
+	if (obj->pages.page == NULL)
+		return 0;
+	BUG_ON(obj->gtt_space);
+	if (obj->pages_pin_count)
+		return -EBUSY;
+	ops->put_pages(obj);
+    obj->pages.page = NULL;
+	list_del(&obj->gtt_list);
 	if (i915_gem_object_is_purgeable(obj))
+		i915_gem_object_truncate(obj);
 	return 0;
+}
 static int
-i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
-			      gfp_t gfpmask)
+static int
 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
-	int page_count, i;
+{
-	struct page *page;
+    dma_addr_t page;
+	int page_count, i;
-	/* Get the list of pages out of our struct file.  They'll be pinned
+	/* Get the list of pages out of our struct file.  They'll be pinned
 	 * at this point until we release them.
 	 */
 	page_count = obj->base.size / PAGE_SIZE;
-	BUG_ON(obj->pages != NULL);
+    BUG_ON(obj->pages.page != NULL);
+    obj->pages.page = malloc(page_count * sizeof(dma_addr_t));
+    if (obj->pages.page == NULL)
+		return -ENOMEM;
-    obj->pages = malloc(page_count * sizeof(struct page *));
+	for (i = 0; i < page_count; i++) {
-	if (obj->pages == NULL)
-		return -ENOMEM;
         page = AllocPage(); // oh-oh
+        if ( page == 0 )
+			goto err_pages;
+        obj->pages.page[i] = page;
+    };
+    obj->pages.nents = page_count;
-	for (i = 0; i < page_count; i++) {
-        page = (struct page*)AllocPage(); // oh-oh
+//   if (obj->tiling_mode != I915_TILING_NONE)
-		if (IS_ERR(page))
+//       i915_gem_object_do_bit_17_swizzle(obj);
-			goto err_pages;
+	return 0;
-		obj->pages[i] = page;
-	}
+err_pages:
-//   if (obj->tiling_mode != I915_TILING_NONE)
+    while (i--)
-//       i915_gem_object_do_bit_17_swizzle(obj);
+        FreePage(obj->pages.page[i]);
-	return 0;
+    free(obj->pages.page);
+    obj->pages.page  = NULL;
-err_pages:
+    obj->pages.nents = 0;
     while (i--)
-        FreePage((addr_t)obj->pages[i]);
+    return -ENOMEM;
+}
     free(obj->pages);
 	/* Move from whatever list we were on to the tail of execution. */
 	list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
 	list_move_tail(&obj->ring_list, &ring->active_list);
-	obj->last_rendering_seqno = seqno;
-	if (obj->fenced_gpu_access) {
-		struct drm_i915_fence_reg *reg;
 	obj->last_read_seqno = seqno;
+	if (obj->fenced_gpu_access) {
+		obj->last_fenced_seqno = seqno;
-		BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
 		/* Bump MRU to take account of the delayed flush */
-		obj->last_fenced_seqno = seqno;
+		if (obj->fence_reg != I915_FENCE_REG_NONE) {
+		struct drm_i915_fence_reg *reg;
 		obj->last_fenced_ring = ring;
 		reg = &dev_priv->fence_regs[obj->fence_reg];
-		reg = &dev_priv->fence_regs[obj->fence_reg];
-		list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
-	}
-}
-static void
-i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
+			list_move_tail(®->lru_list,
 				       &dev_priv->mm.fence_list);
-	list_del_init(&obj->ring_list);
+		}
 	obj->last_rendering_seqno = 0;
+}
+static void
-static void
+i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
-i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
-{
-	struct drm_device *dev = obj->base.dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	BUG_ON(!obj->active);
+{
-	list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
+	struct drm_device *dev = obj->base.dev;
-	i915_gem_object_move_off_active(obj);
-}
-static void
-i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
+	struct drm_i915_private *dev_priv = dev->dev_private;
-{
-	struct drm_device *dev = obj->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
+	BUG_ON(!obj->active);
+	if (obj->pin_count) /* are we a framebuffer? */
+		intel_mark_fb_idle(obj);
-	if (obj->pin_count != 0)
+		list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
 		list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
-	else
-		list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
+	list_del_init(&obj->ring_list);
 	obj->ring = NULL;
 	BUG_ON(!list_empty(&obj->gpu_write_list));
-	BUG_ON(!obj->active);
-	obj->ring = NULL;
+	obj->last_read_seqno = 0;
+	obj->last_write_seqno = 0;
-	i915_gem_object_move_off_active(obj);
+	obj->base.write_domain = 0;
-	obj->fenced_gpu_access = false;
-	obj->active = 0;
-	obj->pending_gpu_write = false;
-	drm_gem_object_unreference(&obj->base);
+	obj->last_fenced_seqno = 0;
-	WARN_ON(i915_verify_lists(dev));
-}
+	obj->fenced_gpu_access = false;
+	obj->active = 0;
-/* Immediately discard the backing storage */
+	drm_gem_object_unreference(&obj->base);
-static void
-i915_gem_object_truncate(struct drm_i915_gem_object *obj)
-{
 	struct inode *inode;
+	WARN_ON(i915_verify_lists(dev));
-	/* Our goal here is to return as much of the memory as
+}
-	 * is possible back to the system as we are called from OOM.
 	 * To do this we must instruct the shmfs to drop all of its
+static u32
-	 * backing pages, *now*.
+i915_gem_get_seqno(struct drm_device *dev)
-	 */
+{
-	obj->madv = __I915_MADV_PURGED;
-}
-static inline int
-i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
-{
-	return obj->madv == I915_MADV_DONTNEED;
-}
-static void
-i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
-			       uint32_t flush_domains)
-{
-	struct drm_i915_gem_object *obj, *next;
 	drm_i915_private_t *dev_priv = dev->dev_private;
-	list_for_each_entry_safe(obj, next,
+	u32 seqno = dev_priv->next_seqno;
 				 &ring->gpu_write_list,
-				 gpu_write_list) {
+	/* reserve 0 for non-seqno */
-		if (obj->base.write_domain & flush_domains) {
+	if (++dev_priv->next_seqno == 0)
-			uint32_t old_write_domain = obj->base.write_domain;
+		dev_priv->next_seqno = 1;
+	return seqno;
+}
-			obj->base.write_domain = 0;
-			list_del_init(&obj->gpu_write_list);
+u32
-			i915_gem_object_move_to_active(obj, ring,
+i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
+{
+	if (ring->outstanding_lazy_request == 0)
+		ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
+	return ring->outstanding_lazy_request;
+}
+int
+i915_add_request(struct intel_ring_buffer *ring,
+		 struct drm_file *file,
+		 u32 *out_seqno)
+{
-						       i915_gem_next_request_seqno(ring));
+	drm_i915_private_t *dev_priv = ring->dev->dev_private;
+	struct drm_i915_gem_request *request;
+	u32 request_ring_position;
+	u32 seqno;
+	int was_empty;
+	int ret;
+	/*
+	 * Emit any outstanding flushes - execbuf can fail to emit the flush
+	 * after having emitted the batchbuffer command. Hence we need to fix
+	 * things up similar to emitting the lazy request. The difference here
 	 * is that the flush _must_ happen before the next request, no matter
-			trace_i915_gem_object_change_domain(obj,
+	 * what.
+	 */
-							    obj->base.read_domains,
+	ret = intel_ring_flush_all_caches(ring);
+	if (ret)
-							    old_write_domain);
+		return ret;
 	request = kmalloc(sizeof(*request), GFP_KERNEL);
+	if (request == NULL)
-}
+		return -ENOMEM;
-int
+	seqno = i915_gem_next_request_seqno(ring);
-i915_add_request(struct intel_ring_buffer *ring,
+	/* Record the position of the start of the request so that
-		 struct drm_file *file,
+	 * should we detect the updated seqno part-way through the
-		 struct drm_i915_gem_request *request)
+	 * GPU processing the request, we never over-estimate the
 	 * position of the head.
-	drm_i915_private_t *dev_priv = ring->dev->dev_private;
+	 */
-	uint32_t seqno;
+	request_ring_position = intel_ring_get_tail(ring);
 	int was_empty;
-	int ret;
+	ret = ring->add_request(ring, &seqno);
 	if (ret) {
-	BUG_ON(request == NULL);
+		kfree(request);
+	    return ret;
+	}
-	ret = ring->add_request(ring, &seqno);
 	if (ret)
+	trace_i915_gem_request_add(ring, seqno);
+	request->seqno = seqno;
+	request->ring = ring;
+	request->tail = request_ring_position;
+    request->emitted_jiffies = GetTimerTicks();
+	was_empty = list_empty(&ring->request_list);
+	list_add_tail(&request->list, &ring->request_list);
+	request->file_priv = NULL;
+	ring->outstanding_lazy_request = 0;
+	if (!dev_priv->mm.suspended) {
+		if (i915_enable_hangcheck) {
+//			mod_timer(&dev_priv->hangcheck_timer,
+//				  jiffies +
+//				  msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
+		}
+		if (was_empty) {
+           queue_delayed_work(dev_priv->wq,
+                      &dev_priv->mm.retire_work, HZ);
+			intel_mark_busy(dev_priv->dev);
+		}
+	}
+	if (out_seqno)
+		*out_seqno = seqno;
+	return 0;
+}
+static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
+				      struct intel_ring_buffer *ring)
+{
+	while (!list_empty(&ring->request_list)) {
+		struct drm_i915_gem_request *request;
+		request = list_first_entry(&ring->request_list,
+					   struct drm_i915_gem_request,
+					   list);
+		list_del(&request->list);
+//       i915_gem_request_remove_from_client(request);
+		kfree(request);
+	}
+	while (!list_empty(&ring->active_list)) {
+		struct drm_i915_gem_object *obj;
+		obj = list_first_entry(&ring->active_list,
+				       struct drm_i915_gem_object,
+				       ring_list);
+		i915_gem_object_move_to_inactive(obj);
+	}
-	    return ret;
+}
-	trace_i915_gem_request_add(ring, seqno);
+static void i915_gem_reset_fences(struct drm_device *dev)
+{
-	request->seqno = seqno;
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	request->ring = ring;
+	int i;
 	request->emitted_jiffies = jiffies;
-	was_empty = list_empty(&ring->request_list);
+	for (i = 0; i < dev_priv->num_fence_regs; i++) {
-	list_add_tail(&request->list, &ring->request_list);
+		struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
 		i915_gem_write_fence(dev, i, NULL);
 	ring->outstanding_lazy_request = false;
+		if (reg->obj)
-	if (!dev_priv->mm.suspended) {
+			i915_gem_object_fence_lost(reg->obj);
 		if (i915_enable_hangcheck) {
-//			mod_timer(&dev_priv->hangcheck_timer,
+		reg->pin_count = 0;
 		if (!i915_seqno_passed(seqno, request->seqno))
 			break;
+		trace_i915_gem_request_retire(ring, request->seqno);
+		/* We know the GPU must have read the request to have
+		 * sent us the seqno + interrupt, so use the position
+		 * of tail of the request to update the last known position
+		 * of the GPU head.
 		 */
-		trace_i915_gem_request_retire(ring, request->seqno);
+		ring->last_retired_head = request->tail;
 		obj = list_first_entry(&ring->active_list,
 				      struct drm_i915_gem_object,
 				      ring_list);
-		if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
-			break;
-		if (obj->base.write_domain != 0)
+		if (!i915_seqno_passed(seqno, obj->last_read_seqno))
-			i915_gem_object_move_to_flushing(obj);
+			break;
 		else
 			i915_gem_object_move_to_inactive(obj);
 void
 i915_gem_retire_requests(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
-	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct intel_ring_buffer *ring;
-	int i;
-	if (!list_empty(&dev_priv->mm.deferred_free_list)) {
-	    struct drm_i915_gem_object *obj, *next;
-	    /* We must be careful that during unbind() we do not
-	     * accidentally infinitely recurse into retire requests.
-	     * Currently:
-	     *   retire -> free -> unbind -> wait -> retire_ring
+	int i;
-	     */
-	    list_for_each_entry_safe(obj, next,
-				     &dev_priv->mm.deferred_free_list,
-				     mm_list)
-		    i915_gem_free_object_tail(obj);
-	}
-	for (i = 0; i < I915_NUM_RINGS; i++)
+	for_each_ring(ring, dev_priv, i)
-		i915_gem_retire_requests_ring(&dev_priv->ring[i]);
+		i915_gem_retire_requests_ring(ring);
+}
 static void
 i915_gem_retire_work_handler(struct work_struct *work)
+{
 	drm_i915_private_t *dev_priv;
-	drm_i915_private_t *dev_priv;
+	struct drm_device *dev;
-	struct drm_device *dev;
+	struct intel_ring_buffer *ring;
 	/* Send a periodic flush down the ring so we don't hold onto GEM
 	 * objects indefinitely.
 	 */
-	idle = true;
-	for (i = 0; i < I915_NUM_RINGS; i++) {
+	idle = true;
-		struct intel_ring_buffer *ring = &dev_priv->ring[i];
+	for_each_ring(ring, dev_priv, i) {
-		if (!list_empty(&ring->gpu_write_list)) {
-			struct drm_i915_gem_request *request;
-			int ret;
-			ret = i915_gem_flush_ring(ring,
-, I915_GEM_GPU_DOMAINS);
-			request = kzalloc(sizeof(*request), GFP_KERNEL);
-			if (ret || request == NULL ||
+		if (ring->gpu_caches_dirty)
-			    i915_add_request(ring, NULL, request))
-			    kfree(request);
 			i915_add_request(ring, NULL, NULL);
 		idle &= list_empty(&ring->request_list);
+	}
+   if (!dev_priv->mm.suspended && !idle)
        queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
-   if (!dev_priv->mm.suspended && !idle)
+	if (idle)
-       queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
+		intel_mark_idle(dev);
 	mutex_unlock(&dev->struct_mutex);
 //    LEAVE();
+}
+/**
-/**
+ * Ensures that an object will eventually get non-busy by flushing any required
- * Waits for a sequence number to be signaled, and cleans up the
- * request and object lists appropriately for that event.
+ * write domains, emitting any outstanding lazy request and retiring and
- */
-int
-i915_wait_request(struct intel_ring_buffer *ring,
+ * completed requests.
-		  uint32_t seqno)
-{
-	drm_i915_private_t *dev_priv = ring->dev->dev_private;
-	u32 ier;
-	int ret = 0;
-	BUG_ON(seqno == 0);
-//   if (atomic_read(&dev_priv->mm.wedged)) {
-//       struct completion *x = &dev_priv->error_completion;
-//       bool recovery_complete;
-//       unsigned long flags;
-		/* Give the error handler a chance to run. */
-//       spin_lock_irqsave(&x->wait.lock, flags);
-//       recovery_complete = x->done > 0;
-//       spin_unlock_irqrestore(&x->wait.lock, flags);
-//
-//       return recovery_complete ? -EIO : -EAGAIN;
-//   }
-	if (seqno == ring->outstanding_lazy_request) {
+ */
-		struct drm_i915_gem_request *request;
+static int
+i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
-		request = kzalloc(sizeof(*request), GFP_KERNEL);
 		if (request == NULL)
-			return -ENOMEM;
+	int ret;
 		ret = i915_add_request(ring, NULL, request);
-		if (ret) {
-			kfree(request);
-			return ret;
-		}
+	if (obj->active) {
-		seqno = request->seqno;
-	}
-	if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
-		if (HAS_PCH_SPLIT(ring->dev))
-			ier = I915_READ(DEIER) | I915_READ(GTIER);
+		ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
-		else
-			ier = I915_READ(IER);
-		if (!ier) {
-			DRM_ERROR("something (likely vbetool) disabled "
-				  "interrupts, re-enabling\n");
-//           ring->dev->driver->irq_preinstall(ring->dev);
-//           ring->dev->driver->irq_postinstall(ring->dev);
-		}
-		trace_i915_gem_request_wait_begin(ring, seqno);
-		ring->waiting_seqno = seqno;
-        if (ring->irq_get(ring)) {
-//            printf("enter wait\n");
-            wait_event(ring->irq_queue,
-                      i915_seqno_passed(ring->get_seqno(ring), seqno)
-                      || atomic_read(&dev_priv->mm.wedged));
-           ring->irq_put(ring);
-        } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring),
-							     seqno) ||
-					   atomic_read(&dev_priv->mm.wedged), 3000))
-			ret = -EBUSY;
-		ring->waiting_seqno = 0;
-		trace_i915_gem_request_wait_end(ring, seqno);
-	}
-	if (atomic_read(&dev_priv->mm.wedged))
-		ret = -EAGAIN;
+		if (ret)
-	if (ret && ret != -ERESTARTSYS)
+			return ret;
-		DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
+		i915_gem_retire_requests_ring(obj->ring);
+	}
+	return 0;
+}
-			  __func__, ret, seqno, ring->get_seqno(ring),
-			  dev_priv->next_seqno);
 	/* Directly dispatch request retiring.  While we have the work queue
-	 * to handle this, the waiter on a request often wants an associated
-	 * buffer to have made it to the inactive list, and we would need
+/**
+ * i915_gem_object_sync - sync an object to a ring.
+ *
-	 * a separate wait queue to handle that.
+ * @obj: object which may be in use on another ring.
-	 */
-	if (ret == 0)
+ * @to: ring we wish to use the object on. May be NULL.
-		i915_gem_retire_requests_ring(ring);
+ *
+ * This code is meant to abstract object synchronization with the GPU.
-	return ret;
+ * Calling with NULL implies synchronizing the object with the CPU
-}
+ * rather than a particular GPU ring.
+ *
+ * Returns 0 if successful, else propagates up the lower layer error.
-/**
+ */
+int
+i915_gem_object_sync(struct drm_i915_gem_object *obj,
+		     struct intel_ring_buffer *to)
- * Ensures that all rendering to the object has completed and the object is
+{
- * safe to unbind from the GTT or access from the CPU.
+	struct intel_ring_buffer *from = obj->ring;
- */
+	u32 seqno;
-int
+	int ret, idx;
+	if (from == NULL || to == from)
+		return 0;
-i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
 	if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
-	int ret;
+		return i915_gem_object_wait_rendering(obj, false);
-	/* This function only exists to support waiting for existing rendering,
+	idx = intel_ring_sync_index(from, to);
  * Unbinds an object from the GTT aperture.
  */
 int
 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
+{
+	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 	int ret = 0;
 	if (obj->gtt_space == NULL)
 		return 0;
-	if (obj->pin_count != 0) {
-		DRM_ERROR("Attempting to unbind pinned buffer\n");
+	if (obj->pin_count)
+		return -EBUSY;
 		return -EINVAL;
-	}
+    BUG_ON(obj->pages.page == NULL);
 	ret = i915_gem_object_finish_gpu(obj);
-	if (ret == -ERESTARTSYS)
+	if (ret)
 		return ret;
 	/* Continue on if we fail due to EIO, the GPU is hung so we
 	 * should be safe and we need to cleanup or else we might
-	 * cause memory corruption through use-after-free.
-	 */
-	i915_gem_object_finish_gtt(obj);
-	/* Move the object to the CPU domain to ensure that
-	 * any possible CPU writes while it's not in the GTT
-	 * are flushed when we go to remap it.
-	 */
-	if (ret == 0)
-		ret = i915_gem_object_set_to_cpu_domain(obj, 1);
-	if (ret == -ERESTARTSYS)
-		return ret;
-	if (ret) {
-		/* In the event of a disaster, abandon all caches and
-		 * hope for the best.
-		 */
+	 * cause memory corruption through use-after-free.
-		i915_gem_clflush_object(obj);
+	 */
-		obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 	i915_gem_object_finish_gtt(obj);
+	/* release the fence reg _after_ flushing */
-	/* release the fence reg _after_ flushing */
+	ret = i915_gem_object_put_fence(obj);
+	if (ret)
+		return ret;
+	trace_i915_gem_object_unbind(obj);
-	ret = i915_gem_object_put_fence(obj);
-	if (ret == -ERESTARTSYS)
+	if (obj->has_global_gtt_mapping)
-		return ret;
+	i915_gem_gtt_unbind_object(obj);
 	if (obj->has_aliasing_ppgtt_mapping) {
-	trace_i915_gem_object_unbind(obj);
+		i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
 		obj->has_aliasing_ppgtt_mapping = 0;
 	i915_gem_gtt_unbind_object(obj);
-	i915_gem_object_put_pages_gtt(obj);
+	i915_gem_gtt_finish_object(obj);
-	list_del_init(&obj->gtt_list);
-	list_del_init(&obj->mm_list);
-	/* Avoid an unnecessary call to unbind on rebind. */
-	obj->map_and_fenceable = true;
-	drm_mm_put_block(obj->gtt_space);
-	obj->gtt_space = NULL;
-	obj->gtt_offset = 0;
-	if (i915_gem_object_is_purgeable(obj))
-		i915_gem_object_truncate(obj);
-	return ret;
-}
-int
-i915_gem_flush_ring(struct intel_ring_buffer *ring,
-		    uint32_t invalidate_domains,
-		    uint32_t flush_domains)
-{
-	int ret;
-	if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
-		return 0;
-	trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
+	list_del(&obj->mm_list);
 	list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
-	ret = ring->flush(ring, invalidate_domains, flush_domains);
+	/* Avoid an unnecessary call to unbind on rebind. */
-	if (ret)
-		return ret;
+	obj->map_and_fenceable = true;
 	if (flush_domains & I915_GEM_GPU_DOMAINS)
-		i915_gem_process_flushing_list(ring, flush_domains);
-	return 0;
-}
-static int i915_ring_idle(struct intel_ring_buffer *ring)
-{
-	int ret;
+	drm_mm_put_block(obj->gtt_space);
 	obj->gtt_space = NULL;
-	if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
-		return 0;
+	obj->gtt_offset = 0;
-	if (!list_empty(&ring->gpu_write_list)) {
+	return 0;
+}
 		ret = i915_gem_flush_ring(ring,
-				    I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+static int i915_ring_idle(struct intel_ring_buffer *ring)
-		if (ret)
+{
+	if (list_empty(&ring->active_list))
+		return 0;
+	return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
-			return ret;
+}
 int i915_gpu_idle(struct drm_device *dev)
 	return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring;
+	int ret, i;
+	/* Flush everything onto the inactive list. */
+	for_each_ring(ring, dev_priv, i) {
+		ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
+		if (ret)
+			return ret;
+		ret = i915_ring_idle(ring);
+		if (ret)
+			return ret;
+	}
+	return 0;
+}
+static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
+					struct drm_i915_gem_object *obj)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	uint64_t val;
+	if (obj) {
+		u32 size = obj->gtt_space->size;
+		val = (uint64_t)((obj->gtt_offset + size - 4096) &
+xfffff000) << 32;
+		val |= obj->gtt_offset & 0xfffff000;
+		val |= (uint64_t)((obj->stride / 128) - 1) <<
+			SANDYBRIDGE_FENCE_PITCH_SHIFT;
+		if (obj->tiling_mode == I915_TILING_Y)
+			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
+		val |= I965_FENCE_REG_VALID;
+	} else
+		val = 0;
+	I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
+	POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
+}
+static void i965_write_fence_reg(struct drm_device *dev, int reg,
+				 struct drm_i915_gem_object *obj)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	uint64_t val;
+	if (obj) {
+		u32 size = obj->gtt_space->size;
+		val = (uint64_t)((obj->gtt_offset + size - 4096) &
+xfffff000) << 32;
+		val |= obj->gtt_offset & 0xfffff000;
+		val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
+		if (obj->tiling_mode == I915_TILING_Y)
+			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
+		val |= I965_FENCE_REG_VALID;
+	} else
+		val = 0;
+	I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
+	POSTING_READ(FENCE_REG_965_0 + reg * 8);
+}
+static void i915_write_fence_reg(struct drm_device *dev, int reg,
+				 struct drm_i915_gem_object *obj)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	u32 val;
+	if (obj) {
+		u32 size = obj->gtt_space->size;
+		int pitch_val;
+		int tile_width;
+		WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
+		     (size & -size) != size ||
+		     (obj->gtt_offset & (size - 1)),
+		     "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
+		     obj->gtt_offset, obj->map_and_fenceable, size);
+		if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
+			tile_width = 128;
+		else
+			tile_width = 512;
+		/* Note: pitch better be a power of two tile widths */
+		pitch_val = obj->stride / tile_width;
+		pitch_val = ffs(pitch_val) - 1;
+		val = obj->gtt_offset;
+		if (obj->tiling_mode == I915_TILING_Y)
+			val |= 1 << I830_FENCE_TILING_Y_SHIFT;
+		val |= I915_FENCE_SIZE_BITS(size);
+		val |= pitch_val << I830_FENCE_PITCH_SHIFT;
+		val |= I830_FENCE_REG_VALID;
+	} else
+		val = 0;
+	if (reg < 8)
+		reg = FENCE_REG_830_0 + reg * 4;
+	else
+		reg = FENCE_REG_945_8 + (reg - 8) * 4;
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+}
+static void i830_write_fence_reg(struct drm_device *dev, int reg,
+				struct drm_i915_gem_object *obj)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	uint32_t val;
+	if (obj) {
+		u32 size = obj->gtt_space->size;
+		uint32_t pitch_val;
+		WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
+		     (size & -size) != size ||
-int
-i915_gpu_idle(struct drm_device *dev)
-{
-	drm_i915_private_t *dev_priv = dev->dev_private;
+		     (obj->gtt_offset & (size - 1)),
+		     "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
-	int ret, i;
+		     obj->gtt_offset, size);
-	/* Flush everything onto the inactive list. */
+		pitch_val = obj->stride / 128;
-	for (i = 0; i < I915_NUM_RINGS; i++) {
-		ret = i915_ring_idle(&dev_priv->ring[i]);
+		pitch_val = ffs(pitch_val) - 1;
-		if (ret)
+		val = obj->gtt_offset;
-			return ret;
+		if (obj->tiling_mode == I915_TILING_Y)
+			val |= 1 << I830_FENCE_TILING_Y_SHIFT;
-	}
+		val |= I830_FENCE_SIZE_BITS(size);
-	return 0;
-}
+		val |= pitch_val << I830_FENCE_PITCH_SHIFT;
+		val |= I830_FENCE_REG_VALID;
+	} else
+		val = 0;
+	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
+	POSTING_READ(FENCE_REG_830_0 + reg * 4);
+}
+static void i915_gem_write_fence(struct drm_device *dev, int reg,
 				 struct drm_i915_gem_object *obj)
+{
+	switch (INTEL_INFO(dev)->gen) {
+	case 7:
+	case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
+	case 5:
 	case 4: i965_write_fence_reg(dev, reg, obj); break;
 	case 3: i915_write_fence_reg(dev, reg, obj); break;
 	case 2: i830_write_fence_reg(dev, reg, obj); break;
 	default: break;
+	}
+}
 static inline int fence_number(struct drm_i915_private *dev_priv,
 			       struct drm_i915_fence_reg *fence)
+{
-static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
+	return fence - dev_priv->fence_regs;
+}
 	return i915_seqno_passed(ring->get_seqno(ring), seqno);
 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
 					 struct drm_i915_fence_reg *fence,
+					 bool enable)
 static int
-i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
-			    struct intel_ring_buffer *pipelined)
-{
-	int ret;
+	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 	int reg = fence_number(dev_priv, fence);
 	if (obj->fenced_gpu_access) {
-		if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
+	i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
-			ret = i915_gem_flush_ring(obj->last_fenced_ring,
-, obj->base.write_domain);
-			if (ret)
+	if (enable) {
-				return ret;
+		obj->fence_reg = reg;
-		}
+		fence->obj = obj;
+		list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
 	} else {
-		obj->fenced_gpu_access = false;
+		obj->fence_reg = I915_FENCE_REG_NONE;
+		fence->obj = NULL;
+		list_del_init(&fence->lru_list);
+	}
+}
+static int
+i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
+{
+	if (obj->last_fenced_seqno) {
+		int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
+			if (ret)
+				return ret;
+		obj->last_fenced_seqno = 0;
+	}
+	/* Ensure that all CPU reads are completed before installing a fence
+	 * and all writes before removing the fence.
+	 */
+	if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
+		mb();
+	obj->fenced_gpu_access = false;
+	return 0;
+}
+int
+i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
+{
+	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+	int ret;
+	ret = i915_gem_object_flush_fence(obj);
+	if (ret)
+		return ret;
+	if (obj->fence_reg == I915_FENCE_REG_NONE)
+		return 0;
+	i915_gem_object_update_fence(obj,
+				     &dev_priv->fence_regs[obj->fence_reg],
+				     false);
+	i915_gem_object_fence_lost(obj);
+	return 0;
+}
+static struct drm_i915_fence_reg *
+i915_find_fence_reg(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_fence_reg *reg, *avail;
+	int i;
+	/* First try to find a free reg */
+	avail = NULL;
+	for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
+		reg = &dev_priv->fence_regs[i];
+		if (!reg->obj)
+			return reg;
+		if (!reg->pin_count)
+			avail = reg;
+	}
+	if (avail == NULL)
+		return NULL;
+	/* None available, try to steal one or wait for a user to finish */
+	list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
+		if (reg->pin_count)
+			continue;
+		return reg;
+	}
+	return NULL;
+}
+/**
+ * i915_gem_object_get_fence - set up fencing for an object
+ * @obj: object to map through a fence reg
+ *
+ * When mapping objects through the GTT, userspace wants to be able to write
+ * to them without having to worry about swizzling if the object is tiled.
+ * This function walks the fence regs looking for a free one for @obj,
+ * stealing one if it can't find any.
+ *
+ * It then sets up the reg based on the object's properties: address, pitch
+ * and tiling format.
+ *
+ * For an untiled surface, this removes any existing fence.
+ */
+int
+i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
+{
+	struct drm_device *dev = obj->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	bool enable = obj->tiling_mode != I915_TILING_NONE;
+	struct drm_i915_fence_reg *reg;
+	int ret;
+	/* Have we updated the tiling parameters upon the object and so
-	}
-	if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
-		if (!ring_passed_seqno(obj->last_fenced_ring,
-				       obj->last_fenced_seqno)) {
-			ret = i915_wait_request(obj->last_fenced_ring,
-						obj->last_fenced_seqno);
-			if (ret)
-				return ret;
-		}
-		obj->last_fenced_seqno = 0;
-		obj->last_fenced_ring = NULL;
-	}
-	/* Ensure that all CPU reads are completed before installing a fence
-	 * and all writes before removing the fence.
+	 * will need to serialise the write to the associated fence register?
-	 */
-	if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
+	 */
-		mb();
-	return 0;
-}
-int
-i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
-{
+	if (obj->fence_dirty) {
-	int ret;
-//   if (obj->tiling_mode)
+		ret = i915_gem_object_flush_fence(obj);
-//       i915_gem_release_mmap(obj);
-	ret = i915_gem_object_flush_fence(obj, NULL);
+		if (ret)
-	if (ret)
-		return ret;
+			return ret;
-	if (obj->fence_reg != I915_FENCE_REG_NONE) {
+	}
+	/* Just update our place in the LRU if our fence is getting reused. */
+	if (obj->fence_reg != I915_FENCE_REG_NONE) {
+		reg = &dev_priv->fence_regs[obj->fence_reg];
+		if (!obj->fence_dirty) {
+			list_move_tail(®->lru_list,
+				       &dev_priv->mm.fence_list);
+			return 0;
+		}
+	} else if (enable) {
+		reg = i915_find_fence_reg(dev);
-		struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+		if (reg == NULL)
+			return -EDEADLK;
+		if (reg->obj) {
+			struct drm_i915_gem_object *old = reg->obj;
+			ret = i915_gem_object_flush_fence(old);
+			if (ret)
+				return ret;
+			i915_gem_object_fence_lost(old);
-		i915_gem_clear_fence_reg(obj->base.dev,
+		}
+	} else
+		return 0;
-					 &dev_priv->fence_regs[obj->fence_reg]);
+	i915_gem_object_update_fence(obj, reg, enable);
-		obj->fence_reg = I915_FENCE_REG_NONE;
+	obj->fence_dirty = false;
-	}
 	return 0;
 	return 0;
 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
 				     struct drm_mm_node *gtt_space,
 				     unsigned long cache_level)
+{
+	struct drm_mm_node *other;
 	/* On non-LLC machines we have to be careful when putting differing
 	 * types of snoopable memory together to avoid the prefetcher
 	 * crossing memory domains and dieing.
 	 */
 	if (HAS_LLC(dev))
 		return true;
 	if (gtt_space == NULL)
 	    (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
 		DRM_ERROR("Attempting to bind an object larger than the aperture\n");
 		return -E2BIG;
+	}
+	ret = i915_gem_object_get_pages(obj);
+	if (ret)
+		return ret;
  search_free:
 	if (map_and_fenceable)
 		free_space =
-			drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
+			drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
-						    size, alignment, 0,
+							  size, alignment, obj->cache_level,
-						    dev_priv->mm.gtt_mappable_end,
+, dev_priv->mm.gtt_mappable_end,
-);
+							  false);
 	else
-		free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
+		free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
+						      size, alignment, obj->cache_level,
-						size, alignment, 0);
+						      false);
 	if (free_space != NULL) {
 		if (map_and_fenceable)
 			obj->gtt_space =
 				drm_mm_get_block_range_generic(free_space,
-							       size, alignment, 0,
+							       size, alignment, obj->cache_level,
-							       dev_priv->mm.gtt_mappable_end,
+, dev_priv->mm.gtt_mappable_end,
-);
+							       false);
 		else
+			obj->gtt_space =
+				drm_mm_get_block_generic(free_space,
-			obj->gtt_space =
+							 size, alignment, obj->cache_level,
-				drm_mm_get_block(free_space, size, alignment);
+							 false);
-	}
-	if (obj->gtt_space == NULL) {
-		/* If the gtt is empty and we're still having trouble
 		 * fitting our object in, we're out of memory.
-		 */
+	if (obj->gtt_space == NULL) {
         ret = 1; //i915_gem_evict_something(dev, size, alignment,
                  //         map_and_fenceable);
 		if (ret)
 			return ret;
-		goto search_free;
+		goto search_free;
 	}
 	if (WARN_ON(!i915_gem_valid_gtt_space(dev,
-	ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
+					      obj->gtt_space,
-	if (ret) {
-		drm_mm_put_block(obj->gtt_space);
-		obj->gtt_space = NULL;
-#if 0
-		if (ret == -ENOMEM) {
-			/* first try to reclaim some memory by clearing the GTT */
-			ret = i915_gem_evict_everything(dev, false);
-			if (ret) {
-				/* now try to shrink everyone else */
-				if (gfpmask) {
-					gfpmask = 0;
-					goto search_free;
+					      obj->cache_level))) {
 		drm_mm_put_block(obj->gtt_space);
-				return -ENOMEM;
-			}
-			goto search_free;
-		}
+		obj->gtt_space = NULL;
-#endif
+		return -EINVAL;
-		return ret;
+	}
-	ret = i915_gem_gtt_bind_object(obj);
-	if (ret) {
         i915_gem_object_put_pages_gtt(obj);
-		drm_mm_put_block(obj->gtt_space);
-		obj->gtt_space = NULL;
 	ret = i915_gem_gtt_prepare_object(obj);
-//       if (i915_gem_evict_everything(dev, false))
+	if (ret) {
-			return ret;
+		drm_mm_put_block(obj->gtt_space);
+		obj->gtt_space = NULL;
-//       goto search_free;
-	}
-	list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
-	list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
+			return ret;
+	}
 	/* Assert that the object is not currently in any GPU domain. As it
-	 * wasn't in the GTT, there shouldn't be any way it could have been in
+	if (!dev_priv->mm.aliasing_ppgtt)
 		obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
 	obj->map_and_fenceable = mappable && fenceable;
 	trace_i915_gem_object_bind(obj, map_and_fenceable);
-	trace_i915_gem_object_bind(obj, map_and_fenceable);
+	i915_gem_verify_gtt(dev);
 	return 0;
+}
 void
 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
+{
 	/* If we don't have a page list set up, then we're not pinned
 	 * to GPU, and we can ignore the cache flush because it'll happen
 	 * again at bind time.
 	 */
-	if (obj->pages == NULL)
+    if (obj->pages.page == NULL)
 		return;
         uint8_t *page_virtual;
         unsigned int i;
         page_virtual = AllocKernelSpace(obj->base.size);
         if(page_virtual != NULL)
+        {
-            u32_t *src, *dst;
+            dma_addr_t *src, *dst;
             u32 count;
 #define page_tabs  0xFDC00000      /* really dirty hack */
-            src =  (u32_t*)obj->pages;
+            src =  obj->pages.page;
-            dst =  &((u32_t*)page_tabs)[(u32_t)page_virtual >> 12];
+            dst =  &((dma_addr_t*)page_tabs)[(u32_t)page_virtual >> 12];
             count = obj->base.size/4096;
             "mfence");
+        }
+     }
+}
-/** Flushes any GPU write domain for the object if it's dirty. */
-static int
-i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
-{
-	if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
-		return 0;
-	/* Queue the GPU write cache flushing we need. */
-	return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
-}
 /** Flushes the GTT write domain for the object if it's dirty. */
 static void
 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
+{
  * flushes to occur.
  */
 int
 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
+{
+	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 	uint32_t old_write_domain, old_read_domains;
 	int ret;
 	/* Not valid to be called on unbound objects. */
 	if (obj->gtt_space == NULL)
 		return -EINVAL;
 	if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
 		return 0;
-	ret = i915_gem_object_flush_gpu_write_domain(obj);
-	if (ret)
-		return ret;
-	if (obj->pending_gpu_write || write) {
-		ret = i915_gem_object_wait_rendering(obj);
-		if (ret)
+	ret = i915_gem_object_wait_rendering(obj, !write);
-			return ret;
+		if (ret)
 			return ret;
 	trace_i915_gem_object_change_domain(obj,
 					    old_read_domains,
+					    old_write_domain);
+	/* And bump the LRU for this access */
+	if (i915_gem_object_is_inactive(obj))
-					    old_write_domain);
+		list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
 	return 0;
+}
+int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
+				    enum i915_cache_level cache_level)
 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
-				    enum i915_cache_level cache_level)
+	struct drm_device *dev = obj->base.dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int ret;
 	if (obj->cache_level == cache_level)
 		return 0;
+	if (obj->pin_count) {
+		DRM_DEBUG("can not change the cache level of pinned objects\n");
+		return -EBUSY;
+	}
 	if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
-	if (obj->pin_count) {
+		ret = i915_gem_object_unbind(obj);
-		DRM_DEBUG("can not change the cache level of pinned objects\n");
+		if (ret)
-		return -EBUSY;
+			return ret;
 		/* Before SandyBridge, you could not use tiling or fence
 		 * registers with snooped memory, so relinquish any fences
 		 * currently pointing to our region in the aperture.
 		 */
-		if (INTEL_INFO(obj->base.dev)->gen < 6) {
+		if (INTEL_INFO(dev)->gen < 6) {
 			ret = i915_gem_object_put_fence(obj);
 			if (ret)
 				return ret;
+		}
-		}
+		if (obj->has_global_gtt_mapping)
+			i915_gem_gtt_bind_object(obj, cache_level);
+		if (obj->has_aliasing_ppgtt_mapping)
+			i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
+					       obj, cache_level);
-		i915_gem_gtt_rebind_object(obj, cache_level);
+		obj->gtt_space->color = cache_level;
+	}
 						    old_read_domains,
 						    old_write_domain);
+    }
+	obj->cache_level = cache_level;
-	obj->cache_level = cache_level;
+	i915_gem_verify_gtt(dev);
 	return 0;
+}
 /*
  * Prepare buffer for display plane (scanout, cursors, etc).
- * Can be called from an uninterruptible phase (modesetting) and allows
- * any flushes to be pipelined (for pageflips).
- *
- * For the display plane, we want to be in the GTT but out of any write
- * domains. So in many ways this looks like set_to_gtt_domain() apart from the
- * ability to pipeline the waits, pinning and any additional subtleties
+ * Can be called from an uninterruptible phase (modesetting) and allows
- * that may differentiate the display plane from ordinary buffers.
+ * any flushes to be pipelined (for pageflips).
  */
 int
 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 				     u32 alignment,
 				     struct intel_ring_buffer *pipelined)
+{
-	u32 old_read_domains, old_write_domain;
-	int ret;
-	ret = i915_gem_object_flush_gpu_write_domain(obj);
-	if (ret)
+	u32 old_read_domains, old_write_domain;
-		return ret;
+	int ret;
 	if (pipelined != obj->ring) {
-		ret = i915_gem_object_wait_rendering(obj);
+		ret = i915_gem_object_sync(obj, pipelined);
-		if (ret == -ERESTARTSYS)
+	if (ret)
-			return ret;
+		return ret;
 	/* As the user may map the buffer once pinned in the display plane
 	 * (e.g. libkms for the bootup splash), we have to ensure that we
 	 * always use map_and_fenceable for all scanout buffers.
 	 */
-	ret = i915_gem_object_pin(obj, alignment, true);
+	ret = i915_gem_object_pin(obj, alignment, true, false);
 	if (ret)
 		return ret;
 	old_read_domains = obj->base.read_domains;
 	/* It should now be out of any other write domains, and we can update
 	 * the domain values for our changes.
 	 */
-	BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
+	obj->base.write_domain = 0;
 	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
 	trace_i915_gem_object_change_domain(obj,
 	int ret;
 	if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
-		return 0;
+		return 0;
 	if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
-		ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
+	ret = i915_gem_object_wait_rendering(obj, false);
-		if (ret)
-			return ret;
+		if (ret)
 			return ret;
-	/* Ensure that we invalidate the GPU's caches and TLBs. */
-	obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
+	/* Ensure that we invalidate the GPU's caches and TLBs. */
 	obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
-	return i915_gem_object_wait_rendering(obj);
+	return 0;
+}
 /**
  * Moves a single object to the CPU read, and possibly write domain.
  *
  * This function returns when the move is complete, including waiting on
  * flushes to occur.
  */
-static int
+int
 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
+{
-	uint32_t old_write_domain, old_read_domains;
-	int ret;
-	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
-		return 0;
+	uint32_t old_write_domain, old_read_domains;
 	int ret;
 	ret = i915_gem_object_flush_gpu_write_domain(obj);
-	if (ret)
+	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
-		return ret;
 		return 0;
 	ret = i915_gem_object_wait_rendering(obj);
-	if (ret)
+	ret = i915_gem_object_wait_rendering(obj, !write);
-		return ret;
+	if (ret)
 					    old_write_domain);
 	return 0;
 }
+#if 0
-/**
+/* Throttle our rendering by waiting until the ring has completed our requests
- * Moves the object from a partially CPU read to a full one.
+ * emitted over 20 msec ago.
  *
+ * Note that if we were to use the current jiffies each time around the loop,
+ * we wouldn't escape the function with any frames outstanding if the time to
+ * render a frame was over 20ms.
+ *
- * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
+ * This should get us reasonable parallelism between CPU and GPU but also
- * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
+ * relatively low latency when blocking on a particular request to finish.
  */
-static void
+static int
-i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
-{
-	if (!obj->page_cpu_valid)
-		return;
+i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
-	/* If we're partially in the CPU read domain, finish moving it in.
+{
-	 */
-	if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
-	}
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_file_private *file_priv = file->driver_priv;
-	/* Free the page_cpu_valid mappings which are now stale, whether
-	 * or not we've got I915_GEM_DOMAIN_CPU.
+	unsigned long recent_enough = GetTimerTics() - msecs_to_jiffies(20);
-	 */
+	struct drm_i915_gem_request *request;
-	kfree(obj->page_cpu_valid);
+	struct intel_ring_buffer *ring = NULL;
-	obj->page_cpu_valid = NULL;
+	u32 seqno = 0;
+	int ret;
+	if (atomic_read(&dev_priv->mm.wedged))
+		return -EIO;
-}
+	spin_lock(&file_priv->mm.lock);
+	list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
 		if (time_after_eq(request->emitted_jiffies, recent_enough))
+			break;
+		ring = request->ring;
+		seqno = request->seqno;
+	}
+	spin_unlock(&file_priv->mm.lock);
-int gem_object_lock(struct drm_i915_gem_object *obj)
+	if (seqno == 0)
-{
-    return i915_gem_object_set_to_cpu_domain(obj, true);
-}
+		return 0;
 	ret = __wait_seqno(ring, seqno, true, NULL);
 	if (ret == 0)
+		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
 	return ret;
+}
+#endif
-int
-i915_gem_object_pin(struct drm_i915_gem_object *obj,
+int
-		    uint32_t alignment,
+i915_gem_object_pin(struct drm_i915_gem_object *obj,
-		    bool map_and_fenceable)
+		    uint32_t alignment,
 		    bool map_and_fenceable,
+	}
 #endif
 	if (obj->gtt_space == NULL) {
 		ret = i915_gem_object_bind_to_gtt(obj, alignment,
+						  map_and_fenceable,
-						  map_and_fenceable);
+						  nonblocking);
 		if (ret)
 			return ret;
 	}
-	if (obj->pin_count++ == 0) {
-		if (!obj->active)
-			list_move_tail(&obj->mm_list,
+	if (!obj->has_global_gtt_mapping && map_and_fenceable)
+		i915_gem_gtt_bind_object(obj, obj->cache_level);
 				       &dev_priv->mm.pinned_list);
-	}
-	obj->pin_mappable |= map_and_fenceable;
+	obj->pin_count++;
 	obj->pin_mappable |= map_and_fenceable;
 	WARN_ON(i915_verify_lists(dev));
 	return 0;
+}
-void
-i915_gem_object_unpin(struct drm_i915_gem_object *obj)
-{
 	struct drm_device *dev = obj->base.dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
+void
+i915_gem_object_unpin(struct drm_i915_gem_object *obj)
-	WARN_ON(i915_verify_lists(dev));
-	BUG_ON(obj->pin_count == 0);
-	BUG_ON(obj->gtt_space == NULL);
+{
-	if (--obj->pin_count == 0) {
+	BUG_ON(obj->pin_count == 0);
+	BUG_ON(obj->gtt_space == NULL);
+	if (--obj->pin_count == 0)
+		obj->pin_mappable = false;
+}
-		if (!obj->active)
+#if 0
+int
+i915_gem_pin_ioctl(struct drm_device *dev, void *data,
+		   struct drm_file *file)
+{
+	struct drm_i915_gem_pin *args = data;
+	struct drm_i915_gem_object *obj;
+	int ret;
+	ret = i915_mutex_lock_interruptible(dev);
+	if (ret)
+		return ret;
 			list_move_tail(&obj->mm_list,
+	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
+	if (&obj->base == NULL) {
+		ret = -ENOENT;
+		goto unlock;
+	}
+	if (obj->madv != I915_MADV_WILLNEED) {
+		DRM_ERROR("Attempting to pin a purgeable buffer\n");
+		ret = -EINVAL;
+		goto out;
+	}
+	if (obj->pin_filp != NULL && obj->pin_filp != file) {
+		DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
+			  args->handle);
+		ret = -EINVAL;
+		goto out;
+	}
+	obj->user_pin_count++;
+	obj->pin_filp = file;
+	if (obj->user_pin_count == 1) {
+		ret = i915_gem_object_pin(obj, args->alignment, true, false);
+		if (ret)
+			goto out;
+	}
+	/* XXX - flush the CPU caches for pinned objects
+	 * as the X server doesn't manage domains yet
+	 */
+	i915_gem_object_flush_cpu_write_domain(obj);
+	args->offset = obj->gtt_offset;
+out:
+	drm_gem_object_unreference(&obj->base);
+unlock:
+	mutex_unlock(&dev->struct_mutex);
+	return ret;
+}
+int
+i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
+		     struct drm_file *file)
+{
+	struct drm_i915_gem_pin *args = data;
+	struct drm_i915_gem_object *obj;
+	int ret;
+	ret = i915_mutex_lock_interruptible(dev);
+	if (ret)
+		return ret;
+	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
+	if (&obj->base == NULL) {
+		ret = -ENOENT;
+		goto unlock;
+	}
+	if (obj->pin_filp != file) {
+		DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
+			  args->handle);
+		ret = -EINVAL;
+		goto out;
+	}
+	obj->user_pin_count--;
+	if (obj->user_pin_count == 0) {
+		obj->pin_filp = NULL;
+		i915_gem_object_unpin(obj);
+	}
+out:
+	drm_gem_object_unreference(&obj->base);
+unlock:
+	mutex_unlock(&dev->struct_mutex);
+	return ret;
+}
+int
+i915_gem_busy_ioctl(struct drm_device *dev, void *data,
+		    struct drm_file *file)
+{
+	struct drm_i915_gem_busy *args = data;
+	struct drm_i915_gem_object *obj;
+	int ret;
+	ret = i915_mutex_lock_interruptible(dev);
+	if (ret)
+		return ret;
+	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
+	if (&obj->base == NULL) {
+		ret = -ENOENT;
+		goto unlock;
+	}
+	/* Count all active objects as busy, even if they are currently not used
+	 * by the gpu. Users of this interface expect objects to eventually
+	 * become non-busy without any further actions, therefore emit any
+	 * necessary flushes here.
+	 */
+	ret = i915_gem_object_flush_active(obj);
+	args->busy = obj->active;
+	if (obj->ring) {
+		BUILD_BUG_ON(I915_NUM_RINGS > 16);
+		args->busy |= intel_ring_flag(obj->ring) << 16;
+	}
+	drm_gem_object_unreference(&obj->base);
+unlock:
+	mutex_unlock(&dev->struct_mutex);
+	return ret;
+}
+int
+i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
+			struct drm_file *file_priv)
+{
+	return i915_gem_ring_throttle(dev, file_priv);
+}
+int
+i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
+		       struct drm_file *file_priv)
+{
+	struct drm_i915_gem_madvise *args = data;
+	struct drm_i915_gem_object *obj;
+	int ret;
+	switch (args->madv) {
+	case I915_MADV_DONTNEED:
+	case I915_MADV_WILLNEED:
+	    break;
+	default:
+	    return -EINVAL;
+	}
+	ret = i915_mutex_lock_interruptible(dev);
+	if (ret)
+		return ret;
+	obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
+	if (&obj->base == NULL) {
+		ret = -ENOENT;
+		goto unlock;
+	}
+	if (obj->pin_count) {
+		ret = -EINVAL;
+		goto out;
+	}
+	if (obj->madv != __I915_MADV_PURGED)
+		obj->madv = args->madv;
+	/* if the object is no longer attached, discard its backing storage */
+	if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
-				       &dev_priv->mm.inactive_list);
+		i915_gem_object_truncate(obj);
 		obj->pin_mappable = false;
 	args->retained = obj->madv != __I915_MADV_PURGED;
-	WARN_ON(i915_verify_lists(dev));
+out:
+	drm_gem_object_unreference(&obj->base);
 unlock:
 	mutex_unlock(&dev->struct_mutex);
 	return ret;
 		kfree(obj);
 		return NULL;
+	}
-	i915_gem_info_add_obj(dev_priv, size);
+	i915_gem_object_init(obj, &i915_gem_object_ops);
 	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
-	if (IS_GEN6(dev) || IS_GEN7(dev)) {
+	if (HAS_LLC(dev)) {
-		/* On Gen6, we can have the GPU use the LLC (the CPU
+		/* On some devices, we can have the GPU use the LLC (the CPU
 		 * cache) for about a 10% performance improvement
 		 */
 		obj->cache_level = I915_CACHE_LLC;
 	} else
 		obj->cache_level = I915_CACHE_NONE;
-	obj->base.driver_private = NULL;
-	obj->fence_reg = I915_FENCE_REG_NONE;
-	INIT_LIST_HEAD(&obj->mm_list);
-	INIT_LIST_HEAD(&obj->gtt_list);
-	INIT_LIST_HEAD(&obj->ring_list);
-	INIT_LIST_HEAD(&obj->exec_list);
-	INIT_LIST_HEAD(&obj->gpu_write_list);
-	obj->madv = I915_MADV_WILLNEED;
-	/* Avoid an unnecessary call to unbind on the first bind. */
-	obj->map_and_fenceable = true;
 	return obj;
+}
 int i915_gem_init_object(struct drm_gem_object *obj)
+{
 	BUG();
 	return 0;
+}
 void i915_gem_free_object(struct drm_gem_object *gem_obj)
-static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
 {
+	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
+	struct drm_device *dev = obj->base.dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	trace_i915_gem_object_destroy(obj);
-	struct drm_device *dev = obj->base.dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
+//   if (obj->phys_obj)
+//       i915_gem_detach_phys_object(dev, obj);
-	int ret;
+	obj->pin_count = 0;
+	if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
+		bool was_interruptible;
+		was_interruptible = dev_priv->mm.interruptible;
-	ret = i915_gem_object_unbind(obj);
+		dev_priv->mm.interruptible = false;
-	if (ret == -ERESTARTSYS) {
+		WARN_ON(i915_gem_object_unbind(obj));
+		dev_priv->mm.interruptible = was_interruptible;
+	}
-		list_move(&obj->mm_list,
-			  &dev_priv->mm.deferred_free_list);
+	obj->pages_pin_count = 0;
-		return;
+	i915_gem_object_put_pages(obj);
 //   i915_gem_object_free_mmap_offset(obj);
 	trace_i915_gem_object_destroy(obj);
     BUG_ON(obj->pages.page);
 //	if (obj->base.map_list.map)
+//   if (obj->base.import_attach)
+//       drm_prime_gem_destroy(&obj->base, NULL);
-//		drm_gem_free_mmap_offset(&obj->base);
 	drm_gem_object_release(&obj->base);
-	drm_gem_object_release(&obj->base);
+	i915_gem_info_remove_obj(dev_priv, obj->base.size);
-	i915_gem_info_remove_obj(dev_priv, obj->base.size);
-	kfree(obj->page_cpu_valid);
+	kfree(obj->bit_17);
-	kfree(obj->bit_17);
+	kfree(obj);
-	kfree(obj);
+}
+#if 0
-}
+int
+i915_gem_idle(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
 	int ret;
+	mutex_lock(&dev->struct_mutex);
+	if (dev_priv->mm.suspended) {
+		mutex_unlock(&dev->struct_mutex);
+		return 0;
+	}
+	ret = i915_gpu_idle(dev);
+	if (ret) {
+		mutex_unlock(&dev->struct_mutex);
+		return ret;
+	}
+	i915_gem_retire_requests(dev);
+	i915_gem_reset_fences(dev);
+	/* Hack!  Don't let anybody do execbuf while we don't control the chip.
+	 * We need to replace this with a semaphore, or something.
+	 * And not confound mm.suspended!
+	 */
+	dev_priv->mm.suspended = 1;
+	del_timer_sync(&dev_priv->hangcheck_timer);
+	i915_kernel_lost_context(dev);
+	i915_gem_cleanup_ringbuffer(dev);
+	mutex_unlock(&dev->struct_mutex);
+	/* Cancel the retire work handler, which should be idle now. */
+//   cancel_delayed_work_sync(&dev_priv->mm.retire_work);
+	return 0;
+}
+#endif
+void i915_gem_l3_remap(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	u32 misccpctl;
+	int i;
+	if (!IS_IVYBRIDGE(dev))
+		return;
+	if (!dev_priv->mm.l3_remap_info)
+		return;
+	misccpctl = I915_READ(GEN7_MISCCPCTL);
+	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+	POSTING_READ(GEN7_MISCCPCTL);
+	for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
+		u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
+		if (remap && remap != dev_priv->mm.l3_remap_info[i/4])
+			DRM_DEBUG("0x%x was already programmed to %x\n",
+				  GEN7_L3LOG_BASE + i, remap);
+		if (remap && !dev_priv->mm.l3_remap_info[i/4])
+			DRM_DEBUG_DRIVER("Clearing remapped register\n");
+		I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]);
+	}
+	/* Make sure all the writes land before disabling dop clock gating */
+	POSTING_READ(GEN7_L3LOG_BASE);
+	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+}
+void i915_gem_init_swizzling(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	if (INTEL_INFO(dev)->gen < 5 ||
+	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+		return;
+	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+				 DISP_TILE_SURFACE_SWIZZLING);
+	if (IS_GEN5(dev))
+		return;
+	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
+	if (IS_GEN6(dev))
+		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
+	else
+		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
+}
+void i915_gem_init_ppgtt(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	uint32_t pd_offset;
+	struct intel_ring_buffer *ring;
+	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+	uint32_t __iomem *pd_addr;
+	uint32_t pd_entry;
+	int i;
+	if (!dev_priv->mm.aliasing_ppgtt)
+		return;
+	pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
+	for (i = 0; i < ppgtt->num_pd_entries; i++) {
+		dma_addr_t pt_addr;
+		if (dev_priv->mm.gtt->needs_dmar)
+			pt_addr = ppgtt->pt_dma_addr[i];
+		else
+            pt_addr = ppgtt->pt_pages[i];
+		pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
+		pd_entry |= GEN6_PDE_VALID;
+		writel(pd_entry, pd_addr + i);
+	}
+	readl(pd_addr);
+	pd_offset = ppgtt->pd_offset;
+	pd_offset /= 64; /* in cachelines, */
+	pd_offset <<= 16;
+	if (INTEL_INFO(dev)->gen == 6) {
+		uint32_t ecochk, gab_ctl, ecobits;
+		ecobits = I915_READ(GAC_ECO_BITS);
+		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
+		gab_ctl = I915_READ(GAB_CTL);
+		I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
+		ecochk = I915_READ(GAM_ECOCHK);
+		I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
+				       ECOCHK_PPGTT_CACHE64B);
+		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+	} else if (INTEL_INFO(dev)->gen >= 7) {
+		I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
+		/* GFX_MODE is per-ring on gen7+ */
+	}
+	for_each_ring(ring, dev_priv, i) {
-void i915_gem_free_object(struct drm_gem_object *gem_obj)
+		if (INTEL_INFO(dev)->gen >= 7)
-{
+			I915_WRITE(RING_MODE_GEN7(ring),
-	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
+				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 	struct drm_device *dev = obj->base.dev;
 		I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
+		I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
+	}
+}
+static bool
+intel_enable_blt(struct drm_device *dev)
+{
+	if (!HAS_BLT(dev))
+		return false;
-    while (obj->pin_count > 0)
+	/* The blitter was dysfunctional on early prototypes */
-		i915_gem_object_unpin(obj);
+	if (IS_GEN6(dev) && dev->pdev->revision < 8) {
 		DRM_INFO("BLT not supported on this pre-production hardware;"
-//	if (obj->phys_obj)
+			 " graphics performance will be degraded.\n");
-//		i915_gem_detach_phys_object(dev, obj);
+		return false;
+	}
 	i915_gem_free_object_tail(obj);
 	return true;
+}
 int
 i915_gem_init_hw(struct drm_device *dev)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
+	int ret;
+	if (!intel_enable_gtt())
+		return -EIO;
+	if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
+		I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
 	i915_gem_l3_remap(dev);
 	i915_gem_init_swizzling(dev);
 	ret = intel_init_render_ring_buffer(dev);
-int
+	if (ret)
+		return ret;
+    if (HAS_BSD(dev)) {
+		ret = intel_init_bsd_ring_buffer(dev);
+		if (ret)
+			goto cleanup_render_ring;
+	}
+	if (intel_enable_blt(dev)) {
+		ret = intel_init_blt_ring_buffer(dev);
+		if (ret)
+			goto cleanup_bsd_ring;
+	}
+	dev_priv->next_seqno = 1;
+	/*
+	 * XXX: There was some w/a described somewhere suggesting loading
+	 * contexts before PPGTT.
+	 */
+	i915_gem_context_init(dev);
+	i915_gem_init_ppgtt(dev);
+	return 0;
+cleanup_bsd_ring:
+	intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
+cleanup_render_ring:
+	intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
+	return ret;
+}
+static bool
+intel_enable_ppgtt(struct drm_device *dev)
+{
+	if (i915_enable_ppgtt >= 0)
+		return i915_enable_ppgtt;
+#ifdef CONFIG_INTEL_IOMMU
+	/* Disable ppgtt on SNB if VT-d is on. */
+	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
-i915_gem_init_ringbuffer(struct drm_device *dev)
+		return false;
+#endif
+	return true;
+}
+#define LFB_SIZE 0xC00000
+int i915_gem_init(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long gtt_size, mappable_size;
+	int ret;
+	gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
+	mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
+	mutex_lock(&dev->struct_mutex);
+	if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
+		/* PPGTT pdes are stolen from global gtt ptes, so shrink the
+		 * aperture accordingly when using aliasing ppgtt. */
+		gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
-	drm_i915_private_t *dev_priv = dev->dev_private;
+        i915_gem_init_global_gtt(dev, LFB_SIZE, mappable_size, gtt_size - LFB_SIZE);
 	int ret;
 		ret = i915_gem_init_aliasing_ppgtt(dev);
+		if (ret) {
-	ret = intel_init_render_ring_buffer(dev);
+			mutex_unlock(&dev->struct_mutex);
-	if (ret)
+			return ret;
-		return ret;
+		}
 	} else {
+		/* Let GEM Manage all of the aperture.
+		 *
-    if (HAS_BSD(dev)) {
+		 * However, leave one page at the end still bound to the scratch
-		ret = intel_init_bsd_ring_buffer(dev);
+		 * page.  There are a number of places where the hardware
-		if (ret)
+		 * apparently prefetches past the end of the object, and we've
-			goto cleanup_render_ring;
+		 * seen multiple hangs with the GPU head pointer stuck in a
 		 * batchbuffer bound at the last page of the aperture.  One page
+		 * should be enough to keep any prefetching inside of the
-	if (HAS_BLT(dev)) {
+		 * aperture.
-		ret = intel_init_blt_ring_buffer(dev);
+		 */
-		if (ret)
+        i915_gem_init_global_gtt(dev, LFB_SIZE, mappable_size, gtt_size - LFB_SIZE);
+	}
 	mutex_lock(&dev->struct_mutex);
 	dev_priv->mm.suspended = 0;
-	ret = i915_gem_init_ringbuffer(dev);
+	ret = i915_gem_init_hw(dev);
 	if (ret != 0) {
 		mutex_unlock(&dev->struct_mutex);
 		return ret;
-	}
-	BUG_ON(!list_empty(&dev_priv->mm.active_list));
-	BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
-	BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
-	for (i = 0; i < I915_NUM_RINGS; i++) {
 		BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
 		BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
 	BUG_ON(!list_empty(&dev_priv->mm.active_list));
 	mutex_unlock(&dev->struct_mutex);
 static void
 init_ring_lists(struct intel_ring_buffer *ring)
+{
     INIT_LIST_HEAD(&ring->active_list);
     INIT_LIST_HEAD(&ring->request_list);
-    INIT_LIST_HEAD(&ring->gpu_write_list);
+}
 void
 i915_gem_load(struct drm_device *dev)
+{
     int i;
     drm_i915_private_t *dev_priv = dev->dev_private;
     INIT_LIST_HEAD(&dev_priv->mm.active_list);
+    INIT_LIST_HEAD(&dev_priv->mm.active_list);
-    INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
+    INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
-    INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
+	INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
-    INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
-    INIT_LIST_HEAD(&dev_priv->mm.fence_list);
-    INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
+	INIT_LIST_HEAD(&dev_priv->mm.bound_list);
-    INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
+    INIT_LIST_HEAD(&dev_priv->mm.fence_list);
     for (i = 0; i < I915_NUM_RINGS; i++)
         init_ring_lists(&dev_priv->ring[i]);
 	for (i = 0; i < I915_MAX_NUM_FENCES; i++)
         INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
 	INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
 			  i915_gem_retire_work_handler);
     /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
-    if (IS_GEN3(dev)) {
-        u32 tmp = I915_READ(MI_ARB_STATE);
-        if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
-            /* arb state is a masked write, so set bit + bit in mask */
-            tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
+    if (IS_GEN3(dev)) {
-            I915_WRITE(MI_ARB_STATE, tmp);
+		I915_WRITE(MI_ARB_STATE,
 			   _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
+    }
     dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
-    if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-        dev_priv->num_fence_regs = 16;
+    if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-    else
-        dev_priv->num_fence_regs = 8;
+        dev_priv->num_fence_regs = 16;
     else

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gem.c – Rev 2360 → 3031