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Rev 3037 | Rev 3243 | ||
---|---|---|---|
Line 104... | Line 104... | ||
104 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
104 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
105 | I915_WRITE(HWS_PGA, addr); |
105 | I915_WRITE(HWS_PGA, addr); |
106 | } |
106 | } |
Line 107... | Line 107... | ||
107 | 107 | ||
108 | /** |
- | |
109 | * Sets up the hardware status page for devices that need a physical address |
- | |
110 | * in the register. |
- | |
111 | */ |
- | |
112 | static int i915_init_phys_hws(struct drm_device *dev) |
- | |
113 | { |
- | |
114 | drm_i915_private_t *dev_priv = dev->dev_private; |
- | |
115 | - | ||
116 | /* Program Hardware Status Page */ |
- | |
117 | dev_priv->status_page_dmah = |
- | |
118 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
- | |
119 | - | ||
120 | if (!dev_priv->status_page_dmah) { |
- | |
121 | DRM_ERROR("Can not allocate hardware status page\n"); |
- | |
122 | return -ENOMEM; |
- | |
123 | } |
- | |
124 | - | ||
125 | memset((void __force __iomem *)dev_priv->status_page_dmah->vaddr, |
- | |
126 | 0, PAGE_SIZE); |
- | |
127 | - | ||
128 | i915_write_hws_pga(dev); |
- | |
129 | - | ||
130 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
- | |
131 | return 0; |
- | |
132 | } |
- | |
133 | - | ||
134 | /** |
108 | /** |
135 | * Frees the hardware status page, whether it's a physical address or a virtual |
109 | * Frees the hardware status page, whether it's a physical address or a virtual |
136 | * address set up by the X Server. |
110 | * address set up by the X Server. |
137 | */ |
111 | */ |
138 | static void i915_free_hws(struct drm_device *dev) |
112 | static void i915_free_hws(struct drm_device *dev) |
Line 169... | Line 143... | ||
169 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
143 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
170 | return; |
144 | return; |
Line 171... | Line 145... | ||
171 | 145 | ||
172 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
146 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
173 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
147 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
174 | ring->space = ring->head - (ring->tail + 8); |
148 | ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE); |
175 | if (ring->space < 0) |
149 | if (ring->space < 0) |
Line 176... | Line 150... | ||
176 | ring->space += ring->size; |
150 | ring->space += ring->size; |
177 | 151 | ||
Line 453... | Line 427... | ||
453 | static void i915_emit_breadcrumb(struct drm_device *dev) |
427 | static void i915_emit_breadcrumb(struct drm_device *dev) |
454 | { |
428 | { |
455 | drm_i915_private_t *dev_priv = dev->dev_private; |
429 | drm_i915_private_t *dev_priv = dev->dev_private; |
456 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
430 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Line 457... | Line 431... | ||
457 | 431 | ||
458 | dev_priv->counter++; |
432 | dev_priv->dri1.counter++; |
459 | if (dev_priv->counter > 0x7FFFFFFFUL) |
433 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) |
460 | dev_priv->counter = 0; |
434 | dev_priv->dri1.counter = 0; |
461 | if (master_priv->sarea_priv) |
435 | if (master_priv->sarea_priv) |
Line 462... | Line 436... | ||
462 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
436 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
463 | 437 | ||
464 | if (BEGIN_LP_RING(4) == 0) { |
438 | if (BEGIN_LP_RING(4) == 0) { |
465 | OUT_RING(MI_STORE_DWORD_INDEX); |
439 | OUT_RING(MI_STORE_DWORD_INDEX); |
466 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
440 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
467 | OUT_RING(dev_priv->counter); |
441 | OUT_RING(dev_priv->dri1.counter); |
468 | OUT_RING(0); |
442 | OUT_RING(0); |
469 | ADVANCE_LP_RING(); |
443 | ADVANCE_LP_RING(); |
Line 604... | Line 578... | ||
604 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
578 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
605 | OUT_RING(0); |
579 | OUT_RING(0); |
Line 606... | Line 580... | ||
606 | 580 | ||
Line 607... | Line 581... | ||
607 | ADVANCE_LP_RING(); |
581 | ADVANCE_LP_RING(); |
Line 608... | Line 582... | ||
608 | 582 | ||
609 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
583 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++; |
610 | 584 | ||
611 | if (BEGIN_LP_RING(4) == 0) { |
585 | if (BEGIN_LP_RING(4) == 0) { |
612 | OUT_RING(MI_STORE_DWORD_INDEX); |
586 | OUT_RING(MI_STORE_DWORD_INDEX); |
613 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
587 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
614 | OUT_RING(dev_priv->counter); |
588 | OUT_RING(dev_priv->dri1.counter); |
Line 615... | Line 589... | ||
615 | OUT_RING(0); |
589 | OUT_RING(0); |
616 | ADVANCE_LP_RING(); |
590 | ADVANCE_LP_RING(); |
617 | } |
591 | } |
Line 618... | Line 592... | ||
618 | 592 | ||
619 | master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page; |
593 | master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page; |
620 | return 0; |
- | |
621 | } |
- | |
622 | 594 | return 0; |
|
623 | static int i915_quiescent(struct drm_device *dev) |
595 | } |
624 | { |
596 | |
Line 625... | Line 597... | ||
625 | struct intel_ring_buffer *ring = LP_RING(dev->dev_private); |
597 | static int i915_quiescent(struct drm_device *dev) |
626 | 598 | { |
|
627 | i915_kernel_lost_context(dev); |
599 | i915_kernel_lost_context(dev); |
Line 777... | Line 749... | ||
777 | 749 | ||
Line 778... | Line 750... | ||
778 | i915_kernel_lost_context(dev); |
750 | i915_kernel_lost_context(dev); |
Line 779... | Line 751... | ||
779 | 751 | ||
780 | DRM_DEBUG_DRIVER("\n"); |
752 | DRM_DEBUG_DRIVER("\n"); |
781 | 753 | ||
782 | dev_priv->counter++; |
754 | dev_priv->dri1.counter++; |
783 | if (dev_priv->counter > 0x7FFFFFFFUL) |
755 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) |
Line 784... | Line 756... | ||
784 | dev_priv->counter = 1; |
756 | dev_priv->dri1.counter = 1; |
785 | if (master_priv->sarea_priv) |
757 | if (master_priv->sarea_priv) |
786 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
758 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
787 | 759 | ||
788 | if (BEGIN_LP_RING(4) == 0) { |
760 | if (BEGIN_LP_RING(4) == 0) { |
789 | OUT_RING(MI_STORE_DWORD_INDEX); |
761 | OUT_RING(MI_STORE_DWORD_INDEX); |
790 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
762 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Line 791... | Line 763... | ||
791 | OUT_RING(dev_priv->counter); |
763 | OUT_RING(dev_priv->dri1.counter); |
792 | OUT_RING(MI_USER_INTERRUPT); |
764 | OUT_RING(MI_USER_INTERRUPT); |
Line 793... | Line 765... | ||
793 | ADVANCE_LP_RING(); |
765 | ADVANCE_LP_RING(); |
794 | } |
766 | } |
795 | 767 | ||
Line 822... | Line 794... | ||
822 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) |
794 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) |
823 | ret = -EBUSY; |
795 | ret = -EBUSY; |
Line 824... | Line 796... | ||
824 | 796 | ||
825 | if (ret == -EBUSY) { |
797 | if (ret == -EBUSY) { |
826 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
798 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
827 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
799 | READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter); |
Line 828... | Line 800... | ||
828 | } |
800 | } |
829 | 801 | ||
Line 1016... | Line 988... | ||
1016 | value = i915_semaphore_is_enabled(dev); |
988 | value = i915_semaphore_is_enabled(dev); |
1017 | break; |
989 | break; |
1018 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
990 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
1019 | value = 1; |
991 | value = 1; |
1020 | break; |
992 | break; |
- | 993 | case I915_PARAM_HAS_SECURE_BATCHES: |
|
- | 994 | value = capable(CAP_SYS_ADMIN); |
|
- | 995 | break; |
|
- | 996 | case I915_PARAM_HAS_PINNED_BATCHES: |
|
- | 997 | value = 1; |
|
- | 998 | break; |
|
1021 | default: |
999 | default: |
1022 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
1000 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
1023 | param->param); |
1001 | param->param); |
1024 | return -EINVAL; |
1002 | return -EINVAL; |
1025 | } |
1003 | } |
Line 1072... | Line 1050... | ||
1072 | static int i915_set_status_page(struct drm_device *dev, void *data, |
1050 | static int i915_set_status_page(struct drm_device *dev, void *data, |
1073 | struct drm_file *file_priv) |
1051 | struct drm_file *file_priv) |
1074 | { |
1052 | { |
1075 | drm_i915_private_t *dev_priv = dev->dev_private; |
1053 | drm_i915_private_t *dev_priv = dev->dev_private; |
1076 | drm_i915_hws_addr_t *hws = data; |
1054 | drm_i915_hws_addr_t *hws = data; |
1077 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1055 | struct intel_ring_buffer *ring; |
Line 1078... | Line 1056... | ||
1078 | 1056 | ||
1079 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1057 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
Line 1080... | Line 1058... | ||
1080 | return -ENODEV; |
1058 | return -ENODEV; |
Line 1092... | Line 1070... | ||
1092 | return 0; |
1070 | return 0; |
1093 | } |
1071 | } |
Line 1094... | Line 1072... | ||
1094 | 1072 | ||
Line -... | Line 1073... | ||
- | 1073 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
|
1095 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
1074 | |
Line 1096... | Line 1075... | ||
1096 | 1075 | ring = LP_RING(dev_priv); |
|
1097 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
1076 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
1098 | 1077 | ||
Line 1297... | Line 1276... | ||
1297 | int ret = 0, mmio_bar, mmio_size; |
1276 | int ret = 0, mmio_bar, mmio_size; |
1298 | uint32_t aperture_size; |
1277 | uint32_t aperture_size; |
Line 1299... | Line 1278... | ||
1299 | 1278 | ||
Line 1300... | Line -... | ||
1300 | info = (struct intel_device_info *) flags; |
- | |
1301 | - | ||
1302 | #if 0 |
- | |
1303 | /* Refuse to load on gen6+ without kms enabled. */ |
- | |
1304 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) |
- | |
1305 | return -ENODEV; |
- | |
1306 | - | ||
1307 | /* i915 has 4 more counters */ |
- | |
1308 | dev->counters += 4; |
- | |
1309 | dev->types[6] = _DRM_STAT_IRQ; |
- | |
1310 | dev->types[7] = _DRM_STAT_PRIMARY; |
- | |
1311 | dev->types[8] = _DRM_STAT_SECONDARY; |
- | |
Line 1312... | Line 1279... | ||
1312 | dev->types[9] = _DRM_STAT_DMA; |
1279 | info = (struct intel_device_info *) flags; |
1313 | #endif |
1280 | |
1314 | 1281 | ||
Line 1325... | Line 1292... | ||
1325 | if (i915_get_bridge_dev(dev)) { |
1292 | if (i915_get_bridge_dev(dev)) { |
1326 | ret = -EIO; |
1293 | ret = -EIO; |
1327 | goto free_priv; |
1294 | goto free_priv; |
1328 | } |
1295 | } |
Line 1329... | Line 1296... | ||
1329 | 1296 | ||
1330 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL); |
1297 | ret = i915_gem_gtt_init(dev); |
1331 | if (!ret) { |
- | |
1332 | DRM_ERROR("failed to set up gmch\n"); |
- | |
1333 | ret = -EIO; |
1298 | if (ret) |
1334 | goto put_bridge; |
- | |
1335 | } |
- | |
1336 | - | ||
1337 | dev_priv->mm.gtt = intel_gtt_get(); |
- | |
1338 | if (!dev_priv->mm.gtt) { |
- | |
1339 | DRM_ERROR("Failed to initialize GTT\n"); |
- | |
1340 | ret = -ENODEV; |
- | |
1341 | goto put_gmch; |
- | |
Line 1342... | Line 1299... | ||
1342 | } |
1299 | goto put_bridge; |
Line 1343... | Line 1300... | ||
1343 | 1300 | ||
1344 | - | ||
1345 | pci_set_master(dev->pdev); |
- | |
Line 1346... | Line 1301... | ||
1346 | 1301 | ||
1347 | /* overlay on gen2 is broken and can't address above 1G */ |
1302 | pci_set_master(dev->pdev); |
1348 | // if (IS_GEN2(dev)) |
1303 | |
1349 | // dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); |
1304 | /* overlay on gen2 is broken and can't address above 1G */ |
1350 | 1305 | ||
1351 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1306 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1352 | * using 32bit addressing, overwriting memory if HWS is located |
1307 | * using 32bit addressing, overwriting memory if HWS is located |
1353 | * above 4GB. |
1308 | * above 4GB. |
1354 | * |
- | |
1355 | * The documentation also mentions an issue with undefined |
- | |
Line 1356... | Line 1309... | ||
1356 | * behaviour if any general state is accessed within a page above 4GB, |
1309 | * |
1357 | * which also needs to be handled carefully. |
1310 | * The documentation also mentions an issue with undefined |
1358 | */ |
1311 | * behaviour if any general state is accessed within a page above 4GB, |
1359 | // if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1312 | * which also needs to be handled carefully. |
Line 1380... | Line 1333... | ||
1380 | } |
1333 | } |
Line 1381... | Line 1334... | ||
1381 | 1334 | ||
1382 | aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
1335 | aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
Line 1383... | Line -... | ||
1383 | dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr; |
- | |
1384 | - | ||
Line 1385... | Line -... | ||
1385 | DRM_INFO("gtt_base_addr %x aperture_size %d\n", |
- | |
1386 | dev_priv->mm.gtt_base_addr, aperture_size ); |
- | |
Line 1387... | Line 1336... | ||
1387 | 1336 | dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr; |
|
1388 | // i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr, |
1337 | |
1389 | // aperture_size); |
1338 | |
1390 | 1339 | ||
Line 1417... | Line 1366... | ||
1417 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1366 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1418 | intel_setup_mchbar(dev); |
1367 | intel_setup_mchbar(dev); |
1419 | intel_setup_gmbus(dev); |
1368 | intel_setup_gmbus(dev); |
1420 | intel_opregion_setup(dev); |
1369 | intel_opregion_setup(dev); |
Line 1421... | Line -... | ||
1421 | - | ||
1422 | /* Make sure the bios did its job and set up vital registers */ |
1370 | |
Line 1423... | Line 1371... | ||
1423 | intel_setup_bios(dev); |
1371 | intel_setup_bios(dev); |
Line 1424... | Line -... | ||
1424 | - | ||
1425 | i915_gem_load(dev); |
- | |
1426 | - | ||
1427 | /* Init HWS */ |
- | |
1428 | if (!I915_NEED_GFX_HWS(dev)) { |
- | |
1429 | ret = i915_init_phys_hws(dev); |
- | |
1430 | if (ret) |
- | |
1431 | goto out_gem_unload; |
1372 | |
1432 | } |
1373 | i915_gem_load(dev); |
1433 | 1374 | ||
1434 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1375 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1435 | * integrated graphics even though the support isn't actually there |
1376 | * integrated graphics even though the support isn't actually there |
Line 1446... | Line 1387... | ||
1446 | spin_lock_init(&dev_priv->irq_lock); |
1387 | spin_lock_init(&dev_priv->irq_lock); |
1447 | spin_lock_init(&dev_priv->error_lock); |
1388 | spin_lock_init(&dev_priv->error_lock); |
1448 | spin_lock_init(&dev_priv->rps.lock); |
1389 | spin_lock_init(&dev_priv->rps.lock); |
1449 | spin_lock_init(&dev_priv->dpio_lock); |
1390 | spin_lock_init(&dev_priv->dpio_lock); |
Line -... | Line 1391... | ||
- | 1391 | ||
- | 1392 | mutex_init(&dev_priv->rps.hw_lock); |
|
1450 | 1393 | ||
1451 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
1394 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
1452 | dev_priv->num_pipe = 3; |
1395 | dev_priv->num_pipe = 3; |
1453 | else if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
1396 | else if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
1454 | dev_priv->num_pipe = 2; |
1397 | dev_priv->num_pipe = 2; |
Line 1467... | Line 1410... | ||
1467 | DRM_ERROR("failed to init modeset\n"); |
1410 | DRM_ERROR("failed to init modeset\n"); |
1468 | goto out_gem_unload; |
1411 | goto out_gem_unload; |
1469 | } |
1412 | } |
Line 1470... | Line 1413... | ||
1470 | 1413 | ||
1471 | /* Must be done after probing outputs */ |
- | |
1472 | // intel_opregion_init(dev); |
- | |
1473 | // acpi_video_register(); |
- | |
1474 | - | ||
1475 | // setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
- | |
Line 1476... | Line 1414... | ||
1476 | // (unsigned long) dev); |
1414 | /* Must be done after probing outputs */ |
1477 | 1415 | ||
Line 1545... | Line 1483... | ||
1545 | acpi_video_unregister(); |
1483 | acpi_video_unregister(); |
Line 1546... | Line 1484... | ||
1546 | 1484 | ||
1547 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1485 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1548 | intel_fbdev_fini(dev); |
1486 | intel_fbdev_fini(dev); |
- | 1487 | intel_modeset_cleanup(dev); |
|
Line 1549... | Line 1488... | ||
1549 | intel_modeset_cleanup(dev); |
1488 | cancel_work_sync(&dev_priv->console_resume_work); |
1550 | 1489 | ||
1551 | /* |
1490 | /* |
1552 | * free the memory space allocated for the child device |
1491 | * free the memory space allocated for the child device |