WebSVN – Kolibri OS – Diff – /contrib/toolchain/binutils/include/opcode/mips.h

 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
-   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-, 2004, 2005, 2008, 2009, 2010, 2013
-   Free Software Foundation, Inc.
+   Copyright (C) 1993-2015 Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
      which.  */
   OP_VU0_SUFFIX,
   /* Like OP_VU0_SUFFIX, but used when the operand's value has already
      been set.  Any suffix used here must match the previous value.  */
+  OP_VU0_MATCH_SUFFIX,
+  /* An index selected by an integer, e.g. [1].  */
+  OP_IMM_INDEX,
+  /* An index selected by a register, e.g. [$2].  */
+  OP_REG_INDEX,
+  /* The operand spans two 5-bit register fields, both of which must be set to
+     the source register.  */
+  OP_SAME_RS_RT,
+  /* Described by mips_prev_operand.  */
+  OP_CHECK_PREV,
+  /* A register operand that must not be zero.  */
-  OP_VU0_MATCH_SUFFIX
+  OP_NON_ZERO_REG
 };
 /* Enumerates the types of MIPS register.  */
   /* R5900 VU0 registers $I, $Q, $R and $ACC.  */
   OP_REG_R5900_I,
   OP_REG_R5900_Q,
   OP_REG_R5900_R,
+  OP_REG_R5900_ACC,
+  /* MSA registers $w0-$w31.  */
+  OP_REG_MSA,
+  /* MSA control registers $0-$31.  */
-  OP_REG_R5900_ACC
+  OP_REG_MSA_CTRL
 };
 /* Base class for all operands.  */
   /* If nonnull, REG_MAP[N] gives the register associated with encoding N,
      otherwise the encoding is the same as the register number.  */
   const unsigned char *reg_map;
 };
+/* Describes an operand that which must match a condition based on the
+   previous operand.  */
+struct mips_check_prev_operand
+{
+  struct mips_operand root;
+  bfd_boolean greater_than_ok;
+  bfd_boolean less_than_ok;
+  bfd_boolean equal_ok;
+  bfd_boolean zero_ok;
+};
 /* Describes an operand that encodes a pair of registers.  */
 struct mips_reg_pair_operand
+{
    "+Z" 5-bit fz register (OP_*_FZ)
    Enhanced VA Scheme:
+   "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
+   MSA Extension:
+   "+d" 5-bit MSA register (FD)
+   "+e" 5-bit MSA register (FS)
+   "+h" 5-bit MSA register (FT)
+   "+k" 5-bit GPR at bit 6
+   "+l" 5-bit MSA control register at bit 6
+   "+n" 5-bit MSA control register at bit 11
+   "+o" 4-bit vector element index at bit 16
+   "+u" 3-bit vector element index at bit 16
+   "+v" 2-bit vector element index at bit 16
+   "+w" 1-bit vector element index at bit 16
+   "+T" (-512 .. 511) << 0 at bit 16
+   "+U" (-512 .. 511) << 1 at bit 16
+   "+V" (-512 .. 511) << 2 at bit 16
+   "+W" (-512 .. 511) << 3 at bit 16
+   "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+   "+!" 3 bit unsigned bit position at bit 16
+   "+@" 4 bit unsigned bit position at bit 16
+   "+#" 6 bit unsigned bit position at bit 16
+   "+$" 5 bit unsigned immediate at bit 16
+   "+%" 5 bit signed immediate at bit 16
+   "+^" 10 bit signed immediate at bit 11
+   "+&" 0 vector element index
+   "+*" 5-bit register vector element index at bit 16
+   "+|" 8-bit mask at bit 16
+   MIPS R6:
+   "+:" 11-bit mask at bit 0
+   "+'" 26 bit PC relative branch target address
+   "+"" 21 bit PC relative branch target address
+   "+;" 5 bit same register in both OP_*_RS and OP_*_RT
+   "+I" 2bit unsigned bit position at bit 6
+   "+O" 3bit unsigned bit position at bit 6
+   "+R" must be program counter
+   "-a" (-262144 .. 262143) << 2 at bit 0
+   "-b" (-131072 .. 131071) << 3 at bit 0
+   "-d" Same as destination register GP
+   "-s" 5 bit source register specifier (OP_*_RS) not $0
+   "-t" 5 bit source register specifier (OP_*_RT) not $0
+   "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS
+   "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS
+   "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS
+   "-x" 5 bit source register specifier (OP_*_RT) greater than or
+        equal to OP_*_RS
+   "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS
+   "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0
-   "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
+   "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0
    Other:
    "()" parens surrounding optional value
    ","  separates operands
    "+"  Start of extension sequence.
    Characters used so far, for quick reference when adding more:
    "1234567890"
-   "%[]<>(),+:'@!#$*&\~"
+   "%[]<>(),+-:'@!#$*&\~"
    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
    "abcdefghijklopqrstuvwxz"
+   Extension character sequences used so far ("+" followed by the
-   Extension character sequences used so far ("+" followed by the
+   following), for quick reference when adding more:
+   "1234567890"
+   "~!@#$%^&*|:'";"
+   "ABCEFGHIJKLMNOPQRSTUVWXZ"
+   "abcdefghijklmnopqrstuvwxyz"
-   following), for quick reference when adding more:
+   Extension character sequences used so far ("-" followed by the
-   "1234567890"
+   following), for quick reference when adding more:
-   "ABCEFGHJKLMNPQSXZ"
+   "AB"
 #define INSN_READ_COND_CODE         0x00000100
 /* TLB operation.  */
 #define INSN_TLB                    0x00000200
 /* Reads coprocessor register other than floating point register.  */
 #define INSN_COP                    0x00000400
-/* Instruction loads value from memory, requiring delay.  */
+/* Instruction loads value from memory.  */
-#define INSN_LOAD_MEMORY_DELAY      0x00000800
+#define INSN_LOAD_MEMORY	    0x00000800
-/* Instruction loads value from coprocessor, requiring delay.  */
+/* Instruction loads value from coprocessor, (may require delay).  */
-#define INSN_LOAD_COPROC_DELAY	    0x00001000
+#define INSN_LOAD_COPROC	    0x00001000
 /* Instruction has unconditional branch delay slot.  */
 #define INSN_UNCOND_BRANCH_DELAY    0x00002000
 /* Instruction has conditional branch delay slot.  */
 #define INSN_COND_BRANCH_DELAY      0x00004000
 /* Conditional branch likely: if branch not taken, insn nullified.  */
 #define INSN_COND_BRANCH_LIKELY	    0x00008000
-/* Moves to coprocessor register, requiring delay.  */
+/* Moves to coprocessor register, (may require delay).  */
-#define INSN_COPROC_MOVE_DELAY      0x00010000
+#define INSN_COPROC_MOVE            0x00010000
 /* Loads coprocessor register from memory, requiring delay.  */
 #define INSN_COPROC_MEMORY_DELAY    0x00020000
 /* Reads the HI register.  */
 #define INSN_READ_HI		    0x00040000
 /* Reads the LO register.  */
 #define INSN2_COND_BRANCH	    0x00001000
 /* Reads from $16.  This is true of the MIPS16 0x6500 nop.  */
 #define INSN2_READ_GPR_16           0x00002000
 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask.  */
 #define INSN2_VU0_CHANNEL_SUFFIX    0x00004000
+/* Instruction has a forbidden slot.  */
+#define INSN2_FORBIDDEN_SLOT        0x00008000
 /* Masks used to mark instructions to indicate which MIPS ISA level
    they were introduced in.  INSN_ISA_MASK masks an enumeration that
    specifies the base ISA level(s).  The remainder of a 32-bit
    word constructed using these macros is a bitmask of the remaining
    INSN_* values below.  */
-#define INSN_ISA_MASK		  0x0000000ful
+#define INSN_ISA_MASK		  0x0000001ful
 /* We cannot start at zero due to ISA_UNKNOWN below.  */
 #define INSN_ISA1                 1
 #define INSN_ISA2                 2
 #define INSN_ISA3                 3
 #define INSN_ISA4                 4
+#define INSN_ISA5                 5
+#define INSN_ISA32                6
+#define INSN_ISA32R2              7
-#define INSN_ISA5                 5
+#define INSN_ISA32R3              8
-#define INSN_ISA32                6
+#define INSN_ISA32R5              9
+#define INSN_ISA32R6              10
+#define INSN_ISA64                11
+#define INSN_ISA64R2              12
-#define INSN_ISA32R2              7
+#define INSN_ISA64R3              13
-#define INSN_ISA64                8
+#define INSN_ISA64R5              14
-#define INSN_ISA64R2              9
+#define INSN_ISA64R6              15
 /* Below this point the INSN_* values correspond to combinations of ISAs.
    They are only for use in the opcodes table to indicate membership of
    a combination of ISAs that cannot be expressed using the usual inclusion
    ordering on the above INSN_* values.  */
-#define INSN_ISA3_32              10
+#define INSN_ISA3_32              16
-#define INSN_ISA3_32R2            11
+#define INSN_ISA3_32R2            17
-#define INSN_ISA4_32              12
+#define INSN_ISA4_32              18
-#define INSN_ISA4_32R2            13
+#define INSN_ISA4_32R2            19
-#define INSN_ISA5_32R2            14
+#define INSN_ISA5_32R2            20
-/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
+/* The R6 definitions shown below state that they support all previous ISAs.
-   INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
+   This is not actually true as some instructions are removed in R6.
-   this table describes whether at least one of the ISAs described by X
+   The problem is that the removed instructions in R6 come from different
+   ISAs.  One approach to solve this would be to describe in the membership
-   is/are implemented by ISA Y.  (Think of Y as the ISA level supported by
+   field of the opcode table the different ISAs an instruction belongs to.
+   This would require us to create a large amount of different ISA
-   a particular core and X as the ISA level(s) at which a certain instruction
+   combinations which is hard to manage.  A cleaner approach (which is
+   implemented here) is to say that R6 is an extension of R5 and then to
+   deal with the removed instructions by adding instruction exclusions
+   for R6 in the opcode table.  */
+/* Bit INSN_ISA - 1 of INSN_UPTO is set if ISA Y includes ISA X.  */
+#define ISAF(X) (1 << (INSN_ISA##X - 1))
+#define INSN_UPTO1    ISAF(1)
+#define INSN_UPTO2    INSN_UPTO1 | ISAF(2)
+#define INSN_UPTO3    INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2)
+#define INSN_UPTO4    INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2)
+#define INSN_UPTO5    INSN_UPTO4 | ISAF(5) | ISAF(5_32R2)
+#define INSN_UPTO32   INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32)
+#define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \
+			| ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2)
+#define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3)
+#define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5)
+#define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6)
+#define INSN_UPTO64   INSN_UPTO5 | ISAF(64) | ISAF(32)
+#define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2)
+#define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3)
+#define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5)
+#define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6)
-   is defined.)  The ISA(s) described by X is/are implemented by Y iff
+/* The same information in table form: bit INSN_ISA - 1 of index
+   INSN_UPTO - 1 is set if ISA Y includes ISA X.  */
+static const unsigned int mips_isa_table[] = {
+  INSN_UPTO1,
+  INSN_UPTO2,
+  INSN_UPTO3,
+  INSN_UPTO4,
+  INSN_UPTO5,
+  INSN_UPTO32,
-   (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
+  INSN_UPTO32R2,
+  INSN_UPTO32R3,
+  INSN_UPTO32R5,
+  INSN_UPTO32R6,
+  INSN_UPTO64,
+  INSN_UPTO64R2,
+  INSN_UPTO64R3,
+  INSN_UPTO64R5,
-   is non-zero.  */
+  INSN_UPTO64R6
-static const unsigned int mips_isa_table[] =
+};
-  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
+#undef ISAF
 /* Masks used for Chip specific instructions.  */
 #define INSN_CHIP_MASK		  0xc3ff0f20
 /* Cavium Networks Octeon instructions.  */
-/* Cavium Networks Octeon instructions.  */
+#define INSN_OCTEON		  0x00000800
-#define INSN_OCTEON		  0x00000800
+#define INSN_OCTEONP		  0x00000200
 /* SmartMIPS ASE  */
 #define ASE_SMARTMIPS		0x00000100
 /* Virtualization ASE */
 #define ASE_VIRT		0x00000200
 #define ASE_VIRT64		0x00000400
+/* MSA Extension  */
+#define ASE_MSA			0x00000800
+#define ASE_MSA64		0x00001000
+/* eXtended Physical Address (XPA) Extension.  */
+#define ASE_XPA			0x00002000
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 #define       ISA_MIPS32      INSN_ISA32
 #define       ISA_MIPS64      INSN_ISA64
+#define       ISA_MIPS32R2    INSN_ISA32R2
 #define       ISA_MIPS32R3    INSN_ISA32R3
+#define       ISA_MIPS32R5    INSN_ISA32R5
+#define       ISA_MIPS64R2    INSN_ISA64R2
+#define       ISA_MIPS64R3    INSN_ISA64R3
+#define       ISA_MIPS64R5    INSN_ISA64R5
 #define       ISA_MIPS32R2    INSN_ISA32R2
-#define       ISA_MIPS64R2    INSN_ISA64R2
+#define       ISA_MIPS32R6    INSN_ISA32R6
 #define       ISA_MIPS64R6    INSN_ISA64R6
 #define CPU_R14000	14000
 #define CPU_R16000	16000
 #define CPU_MIPS16	16
 #define CPU_MIPS32	32
 #define CPU_MIPS32R2	33
+#define CPU_MIPS32R3	34
+#define CPU_MIPS32R5	36
+#define CPU_MIPS32R6	37
 #define CPU_MIPS5       5
 #define CPU_MIPS64      64
 #define CPU_MIPS64R2	65
+#define CPU_MIPS64R3	66
+#define CPU_MIPS64R5	68
+#define CPU_MIPS64R6	69
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 #define CPU_LOONGSON_2E 3001
 #define CPU_LOONGSON_2F 3002
 #define CPU_LOONGSON_3A 3003
 #define CPU_OCTEON	6501
 #define CPU_OCTEONP	6601
 #define CPU_OCTEON2	6502
+#define CPU_OCTEON3	6503
 #define CPU_XLR     	887682   	/* decimal 'XLR'   */
 /* Return true if the given CPU is included in INSN_* mask MASK.  */
       return (mask & INSN_OCTEONP) != 0;
     case CPU_OCTEON2:
+      return (mask & INSN_OCTEON2) != 0;
+    case CPU_OCTEON3:
-      return (mask & INSN_OCTEON2) != 0;
+      return (mask & INSN_OCTEON3) != 0;
+    case CPU_XLR:
+      return (mask & INSN_XLR) != 0;
+    case CPU_MIPS32R6:
+      return (mask & INSN_ISA_MASK) == INSN_ISA32R6;
+    case CPU_MIPS64R6:
-    case CPU_XLR:
+      return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
-      return (mask & INSN_XLR) != 0;
+	     || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
     default:
    "w" 5-bit same register used as both target and destination
        (MICROMIPSOP_*_RT)
    "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
    "z" must be zero register
    "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
-   "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
    "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
    "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
         LSB (MICROMIPSOP_*_EXTLSB).
 	Requires that "+A" or "+E" occur first to set position.
 	Enforces: 32 < (pos+size) <= 64.
    "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
 	Requires that "+A" or "+E" occur first to set position.
 	Enforces: 32 < (pos+size) <= 64.
+   "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code
+        (MICROMIPSOP_*_CODE10)
    PC-relative addition (ADDIUPC) instruction:
    "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
    "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
    microMIPS Enhanced VA Scheme:
+   "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
+   MSA Extension:
+   "+d" 5-bit MSA register (FD)
+   "+e" 5-bit MSA register (FS)
+   "+h" 5-bit MSA register (FT)
+   "+k" 5-bit GPR at bit 6
+   "+l" 5-bit MSA control register at bit 6
+   "+n" 5-bit MSA control register at bit 11
+   "+o" 4-bit vector element index at bit 16
+   "+u" 3-bit vector element index at bit 16
+   "+v" 2-bit vector element index at bit 16
+   "+w" 1-bit vector element index at bit 16
+   "+x" 5-bit shift amount at bit 16
+   "+T" (-512 .. 511) << 0 at bit 16
+   "+U" (-512 .. 511) << 1 at bit 16
+   "+V" (-512 .. 511) << 2 at bit 16
+   "+W" (-512 .. 511) << 3 at bit 16
+   "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+   "+!" 3 bit unsigned bit position at bit 16
+   "+@" 4 bit unsigned bit position at bit 16
+   "+#" 6 bit unsigned bit position at bit 16
+   "+$" 5 bit unsigned immediate at bit 16
+   "+%" 5 bit signed immediate at bit 16
+   "+^" 10 bit signed immediate at bit 11
+   "+&" 0 vector element index
+   "+*" 5-bit register vector element index at bit 16
-   "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
+   "+|" 8-bit mask at bit 16
    Other:
    "()" parens surrounding optional value
    ","  separates operands
    "+"  start of extension sequence
    "m"  start of microMIPS extension sequence
    Characters used so far, for quick reference when adding more:
    "12345678 0"
-   "<>(),+.@\^|~"
+   "<>(),+-.@\^|~"
    "ABCDEFGHI KLMN   RST V    "
    "abcd f hijklmnopqrstuvw yz"
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
    ""
-   ""
+   "~!@#$%^&*|"
-   "ABCEFGH"
+   "ABCEFGHJTUVW"
-   "ij"
+   "dehijklnouvwx"
    Extension character sequences used so far ("m" followed by the
+   following), for quick reference when adding more:
+   ""
+   ""
+   " BCDEFGHIJ LMNOPQ   U WXYZ"
+   " bcdefghij lmn pq st   xyz"
-   following), for quick reference when adding more:
+   Extension character sequences used so far ("-" followed by the
-   ""
+   following), for quick reference when adding more:
    ""
-   " BCDEFGHIJ LMNOPQ   U WXYZ"
+   ""

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(root)/contrib/toolchain/binutils/include/opcode/mips.h – Rev 5191 → 6324