Rev 5271 | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 5271 | Rev 6104 | ||
---|---|---|---|
Line 36... | Line 36... | ||
36 | * of the RS600 GART block). |
36 | * of the RS600 GART block). |
37 | */ |
37 | */ |
38 | #include |
38 | #include |
39 | #include "radeon.h" |
39 | #include "radeon.h" |
40 | #include "radeon_asic.h" |
40 | #include "radeon_asic.h" |
- | 41 | #include "radeon_audio.h" |
|
41 | #include "atom.h" |
42 | #include "atom.h" |
42 | #include "rs600d.h" |
43 | #include "rs600d.h" |
Line 43... | Line 44... | ||
43 | 44 | ||
Line 519... | Line 520... | ||
519 | /* Enable bus master */ |
520 | /* Enable bus master */ |
520 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
521 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
521 | WREG32(RADEON_BUS_CNTL, tmp); |
522 | WREG32(RADEON_BUS_CNTL, tmp); |
522 | /* FIXME: setup default page */ |
523 | /* FIXME: setup default page */ |
523 | WREG32_MC(R_000100_MC_PT0_CNTL, |
524 | WREG32_MC(R_000100_MC_PT0_CNTL, |
524 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
525 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
525 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
526 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
Line 526... | Line 527... | ||
526 | 527 | ||
527 | for (i = 0; i < 19; i++) { |
528 | for (i = 0; i < 19; i++) { |
528 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
529 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
529 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
530 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
530 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
531 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
531 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
532 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
532 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
533 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
533 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
534 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
534 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
535 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
535 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
536 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
536 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
537 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
537 | } |
538 | } |
538 | /* enable first context */ |
539 | /* enable first context */ |
539 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
540 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
540 | S_000102_ENABLE_PAGE_TABLE(1) | |
541 | S_000102_ENABLE_PAGE_TABLE(1) | |
Line 541... | Line 542... | ||
541 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
542 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
542 | 543 | ||
543 | /* disable all other contexts */ |
544 | /* disable all other contexts */ |
Line 544... | Line 545... | ||
544 | for (i = 1; i < 8; i++) |
545 | for (i = 1; i < 8; i++) |
545 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
546 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
546 | 547 | ||
547 | /* setup the page table */ |
548 | /* setup the page table */ |
548 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
549 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
549 | rdev->gart.table_addr); |
550 | rdev->gart.table_addr); |
Line 550... | Line 551... | ||
550 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
551 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
Line 584... | Line 585... | ||
584 | radeon_gart_fini(rdev); |
585 | radeon_gart_fini(rdev); |
585 | rs600_gart_disable(rdev); |
586 | rs600_gart_disable(rdev); |
586 | radeon_gart_table_vram_free(rdev); |
587 | radeon_gart_table_vram_free(rdev); |
587 | } |
588 | } |
Line 588... | Line -... | ||
588 | - | ||
589 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, |
589 | |
590 | uint64_t addr, uint32_t flags) |
590 | uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags) |
591 | { |
- | |
592 | void __iomem *ptr = (void *)rdev->gart.ptr; |
- | |
593 | 591 | { |
|
594 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
592 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
595 | addr |= R600_PTE_SYSTEM; |
593 | addr |= R600_PTE_SYSTEM; |
596 | if (flags & RADEON_GART_PAGE_VALID) |
594 | if (flags & RADEON_GART_PAGE_VALID) |
597 | addr |= R600_PTE_VALID; |
595 | addr |= R600_PTE_VALID; |
598 | if (flags & RADEON_GART_PAGE_READ) |
596 | if (flags & RADEON_GART_PAGE_READ) |
599 | addr |= R600_PTE_READABLE; |
597 | addr |= R600_PTE_READABLE; |
600 | if (flags & RADEON_GART_PAGE_WRITE) |
598 | if (flags & RADEON_GART_PAGE_WRITE) |
601 | addr |= R600_PTE_WRITEABLE; |
599 | addr |= R600_PTE_WRITEABLE; |
602 | if (flags & RADEON_GART_PAGE_SNOOP) |
600 | if (flags & RADEON_GART_PAGE_SNOOP) |
- | 601 | addr |= R600_PTE_SNOOPED; |
|
- | 602 | return addr; |
|
- | 603 | } |
|
- | 604 | ||
- | 605 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, |
|
- | 606 | uint64_t entry) |
|
- | 607 | { |
|
603 | addr |= R600_PTE_SNOOPED; |
608 | void __iomem *ptr = (void *)rdev->gart.ptr; |
604 | writeq(addr, ptr + (i * 8)); |
609 | writeq(entry, ptr + (i * 8)); |
Line 605... | Line 610... | ||
605 | } |
610 | } |
606 | 611 | ||
607 | int rs600_irq_set(struct radeon_device *rdev) |
612 | int rs600_irq_set(struct radeon_device *rdev) |
Line 617... | Line 622... | ||
617 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
622 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
618 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
623 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
619 | else |
624 | else |
620 | hdmi0 = 0; |
625 | hdmi0 = 0; |
Line 621... | Line 626... | ||
621 | 626 | ||
622 | if (!rdev->irq.installed) { |
627 | if (!rdev->irq.installed) { |
623 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
628 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
624 | WREG32(R_000040_GEN_INT_CNTL, 0); |
629 | WREG32(R_000040_GEN_INT_CNTL, 0); |
625 | return -EINVAL; |
630 | return -EINVAL; |
626 | } |
631 | } |
Line 648... | Line 653... | ||
648 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
653 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
649 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
654 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
650 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
655 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
651 | if (ASIC_IS_DCE2(rdev)) |
656 | if (ASIC_IS_DCE2(rdev)) |
652 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
657 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
- | 658 | ||
- | 659 | /* posting read */ |
|
- | 660 | RREG32(R_000040_GEN_INT_CNTL); |
|
- | 661 | ||
653 | return 0; |
662 | return 0; |
654 | } |
663 | } |
Line 655... | Line 664... | ||
655 | 664 | ||
656 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
665 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
Line 732... | Line 741... | ||
732 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
741 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
733 | } |
742 | } |
734 | /* Vertical blank interrupts */ |
743 | /* Vertical blank interrupts */ |
735 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
744 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
736 | if (rdev->irq.crtc_vblank_int[0]) { |
745 | if (rdev->irq.crtc_vblank_int[0]) { |
737 | // drm_handle_vblank(rdev->ddev, 0); |
746 | drm_handle_vblank(rdev->ddev, 0); |
738 | rdev->pm.vblank_sync = true; |
747 | rdev->pm.vblank_sync = true; |
739 | // wake_up(&rdev->irq.vblank_queue); |
748 | wake_up(&rdev->irq.vblank_queue); |
740 | } |
749 | } |
741 | // if (rdev->irq.pflip[0]) |
750 | if (atomic_read(&rdev->irq.pflip[0])) |
742 | // radeon_crtc_handle_flip(rdev, 0); |
751 | radeon_crtc_handle_vblank(rdev, 0); |
743 | } |
752 | } |
744 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
753 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
745 | if (rdev->irq.crtc_vblank_int[1]) { |
754 | if (rdev->irq.crtc_vblank_int[1]) { |
746 | // drm_handle_vblank(rdev->ddev, 1); |
755 | drm_handle_vblank(rdev->ddev, 1); |
747 | rdev->pm.vblank_sync = true; |
756 | rdev->pm.vblank_sync = true; |
748 | // wake_up(&rdev->irq.vblank_queue); |
757 | wake_up(&rdev->irq.vblank_queue); |
749 | } |
758 | } |
750 | // if (rdev->irq.pflip[1]) |
759 | if (atomic_read(&rdev->irq.pflip[1])) |
751 | // radeon_crtc_handle_flip(rdev, 1); |
760 | radeon_crtc_handle_vblank(rdev, 1); |
752 | } |
761 | } |
753 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
762 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
754 | queue_hotplug = true; |
763 | queue_hotplug = true; |
755 | DRM_DEBUG("HPD1\n"); |
764 | DRM_DEBUG("HPD1\n"); |
756 | } |
765 | } |
Line 936... | Line 945... | ||
936 | rs600_gpu_init(rdev); |
945 | rs600_gpu_init(rdev); |
937 | /* Initialize GART (initialize after TTM so we can allocate |
946 | /* Initialize GART (initialize after TTM so we can allocate |
938 | * memory through TTM but finalize after TTM) */ |
947 | * memory through TTM but finalize after TTM) */ |
939 | r = rs600_gart_enable(rdev); |
948 | r = rs600_gart_enable(rdev); |
940 | if (r) |
949 | if (r) |
941 | return r; |
950 | return r; |
Line 942... | Line 951... | ||
942 | 951 | ||
943 | /* allocate wb buffer */ |
952 | /* allocate wb buffer */ |
944 | r = radeon_wb_init(rdev); |
953 | r = radeon_wb_init(rdev); |
945 | if (r) |
954 | if (r) |
Line 971... | Line 980... | ||
971 | if (r) { |
980 | if (r) { |
972 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
981 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
973 | return r; |
982 | return r; |
974 | } |
983 | } |
Line 975... | Line 984... | ||
975 | 984 | ||
976 | r = r600_audio_init(rdev); |
985 | r = radeon_audio_init(rdev); |
977 | if (r) { |
986 | if (r) { |
978 | dev_err(rdev->dev, "failed initializing audio\n"); |
987 | dev_err(rdev->dev, "failed initializing audio\n"); |
979 | return r; |
988 | return r; |
Line 980... | Line 989... | ||
980 | } |
989 | } |
981 | 990 | ||
Line -... | Line 991... | ||
- | 991 | return 0; |
|
- | 992 | } |
|
- | 993 | ||
- | 994 | ||
- | 995 | void rs600_fini(struct radeon_device *rdev) |
|
- | 996 | { |
|
- | 997 | radeon_pm_fini(rdev); |
|
- | 998 | radeon_audio_fini(rdev); |
|
- | 999 | r100_cp_fini(rdev); |
|
- | 1000 | radeon_wb_fini(rdev); |
|
- | 1001 | radeon_ib_pool_fini(rdev); |
|
- | 1002 | radeon_gem_fini(rdev); |
|
- | 1003 | rs600_gart_fini(rdev); |
|
- | 1004 | radeon_irq_kms_fini(rdev); |
|
- | 1005 | radeon_fence_driver_fini(rdev); |
|
- | 1006 | radeon_bo_fini(rdev); |
|
Line 982... | Line 1007... | ||
982 | return 0; |
1007 | radeon_atombios_fini(rdev); |
983 | } |
1008 | kfree(rdev->bios); |
984 | 1009 | rdev->bios = NULL; |
|
Line 1044... | Line 1069... | ||
1044 | rdev->accel_working = true; |
1069 | rdev->accel_working = true; |
1045 | r = rs600_startup(rdev); |
1070 | r = rs600_startup(rdev); |
1046 | if (r) { |
1071 | if (r) { |
1047 | /* Somethings want wront with the accel init stop accel */ |
1072 | /* Somethings want wront with the accel init stop accel */ |
1048 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
1073 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
1049 | // r100_cp_fini(rdev); |
1074 | r100_cp_fini(rdev); |
1050 | // r100_wb_fini(rdev); |
1075 | radeon_wb_fini(rdev); |
1051 | // r100_ib_fini(rdev); |
1076 | radeon_ib_pool_fini(rdev); |
1052 | rs600_gart_fini(rdev); |
1077 | rs600_gart_fini(rdev); |
1053 | // radeon_irq_kms_fini(rdev); |
1078 | radeon_irq_kms_fini(rdev); |
1054 | rdev->accel_working = false; |
1079 | rdev->accel_working = false; |
1055 | } |
1080 | } |
1056 | return 0; |
1081 | return 0; |
1057 | }><>>>>><>><> |
1082 | }><>>>>><>><> |