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Rev 2004 | Rev 2160 | ||
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Line 1... | Line 1... | ||
1 | #include |
1 | #include |
2 | #include |
2 | #include |
3 | #include |
3 | #include |
4 | #include |
- | |
5 | #include |
4 | #include |
- | 5 | #include |
|
6 | #include |
6 | #include |
Line 7... | Line 7... | ||
7 | 7 | ||
Line 8... | Line 8... | ||
8 | static LIST_HEAD(devices); |
8 | static LIST_HEAD(devices); |
Line 93... | Line 93... | ||
93 | 93 | ||
Line 94... | Line 94... | ||
94 | res = &dev->resource[pos]; |
94 | res = &dev->resource[pos]; |
Line 95... | Line 95... | ||
95 | 95 | ||
96 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
96 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
97 | l = PciRead32(dev->bus, dev->devfn, reg); |
97 | l = PciRead32(dev->busnr, dev->devfn, reg); |
98 | PciWrite32(dev->bus, dev->devfn, reg, ~0); |
98 | PciWrite32(dev->busnr, dev->devfn, reg, ~0); |
99 | sz = PciRead32(dev->bus, dev->devfn, reg); |
99 | sz = PciRead32(dev->busnr, dev->devfn, reg); |
Line 100... | Line 100... | ||
100 | PciWrite32(dev->bus, dev->devfn, reg, l); |
100 | PciWrite32(dev->busnr, dev->devfn, reg, l); |
101 | 101 | ||
Line 102... | Line 102... | ||
102 | if (!sz || sz == 0xffffffff) |
102 | if (!sz || sz == 0xffffffff) |
Line 132... | Line 132... | ||
132 | if (is_64bit_memory(l)) |
132 | if (is_64bit_memory(l)) |
133 | { |
133 | { |
134 | u32_t szhi, lhi; |
134 | u32_t szhi, lhi; |
135 | 135 | ||
Line 136... | Line 136... | ||
136 | lhi = PciRead32(dev->bus, dev->devfn, reg+4); |
136 | lhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
137 | PciWrite32(dev->bus, dev->devfn, reg+4, ~0); |
137 | PciWrite32(dev->busnr, dev->devfn, reg+4, ~0); |
138 | szhi = PciRead32(dev->bus, dev->devfn, reg+4); |
138 | szhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
139 | PciWrite32(dev->bus, dev->devfn, reg+4, lhi); |
139 | PciWrite32(dev->busnr, dev->devfn, reg+4, lhi); |
140 | sz64 = ((u64_t)szhi << 32) | raw_sz; |
140 | sz64 = ((u64_t)szhi << 32) | raw_sz; |
141 | l64 = ((u64_t)lhi << 32) | l; |
141 | l64 = ((u64_t)lhi << 32) | l; |
142 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
142 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
143 | next++; |
143 | next++; |
Line 160... | Line 160... | ||
160 | } |
160 | } |
161 | else if (lhi) |
161 | else if (lhi) |
162 | { |
162 | { |
163 | /* 64-bit wide address, treat as disabled */ |
163 | /* 64-bit wide address, treat as disabled */ |
164 | PciWrite32(dev->bus, dev->devfn, reg, |
164 | PciWrite32(dev->busnr, dev->devfn, reg, |
165 | l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
165 | l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
166 | PciWrite32(dev->bus, dev->devfn, reg+4, 0); |
166 | PciWrite32(dev->busnr, dev->devfn, reg+4, 0); |
167 | res->start = 0; |
167 | res->start = 0; |
168 | res->end = sz; |
168 | res->end = sz; |
169 | } |
169 | } |
170 | #endif |
170 | #endif |
171 | } |
171 | } |
172 | } |
172 | } |
Line 175... | Line 175... | ||
175 | { |
175 | { |
176 | dev->rom_base_reg = rom; |
176 | dev->rom_base_reg = rom; |
177 | res = &dev->resource[PCI_ROM_RESOURCE]; |
177 | res = &dev->resource[PCI_ROM_RESOURCE]; |
178 | 178 | ||
Line 179... | Line 179... | ||
179 | l = PciRead32(dev->bus, dev->devfn, rom); |
179 | l = PciRead32(dev->busnr, dev->devfn, rom); |
180 | PciWrite32(dev->bus, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
180 | PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
181 | sz = PciRead32(dev->bus, dev->devfn, rom); |
181 | sz = PciRead32(dev->busnr, dev->devfn, rom); |
182 | PciWrite32(dev->bus, dev->devfn, rom, l); |
182 | PciWrite32(dev->busnr, dev->devfn, rom, l); |
Line 183... | Line 183... | ||
183 | 183 | ||
184 | if (l == 0xffffffff) |
184 | if (l == 0xffffffff) |
Line 185... | Line 185... | ||
185 | l = 0; |
185 | l = 0; |
Line 203... | Line 203... | ||
203 | static void pci_read_irq(struct pci_dev *dev) |
203 | static void pci_read_irq(struct pci_dev *dev) |
204 | { |
204 | { |
205 | u8_t irq; |
205 | u8_t irq; |
Line 206... | Line 206... | ||
206 | 206 | ||
207 | irq = PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_PIN); |
207 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN); |
208 | dev->pin = irq; |
208 | dev->pin = irq; |
209 | if (irq) |
209 | if (irq) |
210 | irq = PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_LINE); |
210 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE); |
211 | dev->irq = irq; |
211 | dev->irq = irq; |
Line 212... | Line 212... | ||
212 | }; |
212 | }; |
213 | 213 | ||
214 | 214 | ||
Line 215... | Line 215... | ||
215 | static int pci_setup_device(struct pci_dev *dev) |
215 | int pci_setup_device(struct pci_dev *dev) |
216 | { |
216 | { |
217 | u32_t class; |
217 | u32_t class; |
218 | 218 | ||
Line 219... | Line 219... | ||
219 | class = PciRead32(dev->bus, dev->devfn, PCI_CLASS_REVISION); |
219 | class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION); |
Line 234... | Line 234... | ||
234 | if (class == PCI_CLASS_BRIDGE_PCI) |
234 | if (class == PCI_CLASS_BRIDGE_PCI) |
235 | goto bad; |
235 | goto bad; |
236 | pci_read_irq(dev); |
236 | pci_read_irq(dev); |
237 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
237 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
238 | dev->subsystem_vendor = PciRead16(dev->bus, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
238 | dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
239 | dev->subsystem_device = PciRead16(dev->bus, dev->devfn, PCI_SUBSYSTEM_ID); |
239 | dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID); |
240 | 240 | ||
Line 241... | Line 241... | ||
241 | /* |
241 | /* |
242 | * Do the ugly legacy mode stuff here rather than broken chip |
242 | * Do the ugly legacy mode stuff here rather than broken chip |
243 | * quirk code. Legacy mode ATA controllers have fixed |
243 | * quirk code. Legacy mode ATA controllers have fixed |
244 | * addresses. These are not always echoed in BAR0-3, and |
244 | * addresses. These are not always echoed in BAR0-3, and |
Line 247... | Line 247... | ||
247 | if (class == PCI_CLASS_STORAGE_IDE) |
247 | if (class == PCI_CLASS_STORAGE_IDE) |
248 | { |
248 | { |
249 | u8_t progif; |
249 | u8_t progif; |
250 | 250 | ||
Line 251... | Line 251... | ||
251 | progif = PciRead8(dev->bus, dev->devfn,PCI_CLASS_PROG); |
251 | progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG); |
252 | if ((progif & 1) == 0) |
252 | if ((progif & 1) == 0) |
253 | { |
253 | { |
254 | dev->resource[0].start = 0x1F0; |
254 | dev->resource[0].start = 0x1F0; |
255 | dev->resource[0].end = 0x1F7; |
255 | dev->resource[0].end = 0x1F7; |
256 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
256 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
Line 285... | Line 285... | ||
285 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
285 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
286 | goto bad; |
286 | goto bad; |
287 | pci_read_irq(dev); |
287 | pci_read_irq(dev); |
288 | pci_read_bases(dev, 1, 0); |
288 | pci_read_bases(dev, 1, 0); |
289 | dev->subsystem_vendor = PciRead16(dev->bus, |
289 | dev->subsystem_vendor = PciRead16(dev->busnr, |
290 | dev->devfn, |
290 | dev->devfn, |
291 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
291 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
292 | 292 | ||
Line 293... | Line 293... | ||
293 | dev->subsystem_device = PciRead16(dev->bus, |
293 | dev->subsystem_device = PciRead16(dev->busnr, |
294 | dev->devfn, |
294 | dev->devfn, |
295 | PCI_CB_SUBSYSTEM_ID); |
295 | PCI_CB_SUBSYSTEM_ID); |
296 | break; |
296 | break; |
Line 297... | Line 297... | ||
297 | 297 | ||
Line 310... | Line 310... | ||
310 | 310 | ||
Line 311... | Line 311... | ||
311 | return 0; |
311 | return 0; |
312 | }; |
312 | }; |
Line 313... | Line 313... | ||
313 | 313 | ||
314 | static pci_dev_t* pci_scan_device(u32_t bus, int devfn) |
314 | static pci_dev_t* pci_scan_device(u32_t busnr, int devfn) |
315 | { |
315 | { |
Line 316... | Line 316... | ||
316 | pci_dev_t *dev; |
316 | pci_dev_t *dev; |
317 | 317 | ||
Line 318... | Line 318... | ||
318 | u32_t id; |
318 | u32_t id; |
Line 319... | Line 319... | ||
319 | u8_t hdr; |
319 | u8_t hdr; |
Line 320... | Line 320... | ||
320 | 320 | ||
321 | int timeout = 10; |
321 | int timeout = 10; |
322 | 322 | ||
323 | id = PciRead32(bus,devfn, PCI_VENDOR_ID); |
323 | id = PciRead32(busnr, devfn, PCI_VENDOR_ID); |
Line 332... | Line 332... | ||
332 | 332 | ||
Line 333... | Line 333... | ||
333 | delay(timeout/10); |
333 | delay(timeout/10); |
334 | timeout *= 2; |
334 | timeout *= 2; |
Line 335... | Line 335... | ||
335 | 335 | ||
Line 336... | Line 336... | ||
336 | id = PciRead32(bus, devfn, PCI_VENDOR_ID); |
336 | id = PciRead32(busnr, devfn, PCI_VENDOR_ID); |
337 | 337 | ||
338 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
338 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
339 | if (timeout > 60 * 100) |
339 | if (timeout > 60 * 100) |
340 | { |
340 | { |
341 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
341 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
342 | "responding\n", bus,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
342 | "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
343 | return NULL; |
343 | return NULL; |
Line 344... | Line 344... | ||
344 | } |
344 | } |
Line 345... | Line 345... | ||
345 | }; |
345 | }; |
Line 346... | Line 346... | ||
346 | 346 | ||
Line 347... | Line 347... | ||
347 | hdr = PciRead8(bus, devfn, PCI_HEADER_TYPE); |
347 | hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE); |
348 | 348 | ||
Line 349... | Line 349... | ||
349 | dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0); |
349 | dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0); |
350 | 350 | ||
351 | INIT_LIST_HEAD(&dev->link); |
351 | INIT_LIST_HEAD(&dev->link); |
352 | 352 | ||
353 | if(unlikely(dev == NULL)) |
353 | if(unlikely(dev == NULL)) |
354 | return NULL; |
354 | return NULL; |
Line 503... | Line 503... | ||
503 | int pci_find_capability(struct pci_dev *dev, int cap) |
503 | int pci_find_capability(struct pci_dev *dev, int cap) |
504 | { |
504 | { |
505 | int pos; |
505 | int pos; |
Line 506... | Line 506... | ||
506 | 506 | ||
507 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); |
507 | pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type); |
508 | if (pos) |
508 | if (pos) |
Line 509... | Line 509... | ||
509 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); |
509 | pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap); |
510 | 510 | ||
Line 644... | Line 644... | ||
644 | u16_t cmd, old_cmd; |
644 | u16_t cmd, old_cmd; |
645 | int idx; |
645 | int idx; |
646 | struct resource *r; |
646 | struct resource *r; |
647 | 647 | ||
Line 648... | Line 648... | ||
648 | cmd = PciRead16(dev->bus, dev->devfn, PCI_COMMAND); |
648 | cmd = PciRead16(dev->busnr, dev->devfn, PCI_COMMAND); |
649 | old_cmd = cmd; |
649 | old_cmd = cmd; |
650 | for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) |
650 | for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) |
651 | { |
651 | { |
652 | /* Only set up the requested stuff */ |
652 | /* Only set up the requested stuff */ |
653 | if (!(mask & (1 << idx))) |
653 | if (!(mask & (1 << idx))) |
Line 672... | Line 672... | ||
672 | } |
672 | } |
673 | if (cmd != old_cmd) { |
673 | if (cmd != old_cmd) { |
674 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
674 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
675 | pci_name(dev), old_cmd, cmd); |
675 | pci_name(dev), old_cmd, cmd); |
676 | PciWrite16(dev->bus, dev->devfn, PCI_COMMAND, cmd); |
676 | PciWrite16(dev->busnr, dev->devfn, PCI_COMMAND, cmd); |
677 | } |
677 | } |
678 | return 0; |
678 | return 0; |
679 | } |
679 | } |
680 | 680 |