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Line 22... | Line 22... | ||
22 | * Authors: Alex Deucher |
22 | * Authors: Alex Deucher |
23 | */ |
23 | */ |
24 | #include |
24 | #include |
25 | //#include |
25 | //#include |
26 | #include |
26 | #include |
- | 27 | #include |
|
27 | #include "drmP.h" |
28 | #include |
28 | #include "radeon.h" |
29 | #include "radeon.h" |
29 | #include "radeon_asic.h" |
30 | #include "radeon_asic.h" |
30 | #include "radeon_drm.h" |
31 | #include |
31 | #include "nid.h" |
32 | #include "nid.h" |
32 | #include "atom.h" |
33 | #include "atom.h" |
33 | #include "ni_reg.h" |
34 | #include "ni_reg.h" |
34 | #include "cayman_blit_shaders.h" |
35 | #include "cayman_blit_shaders.h" |
Line 37... | Line 38... | ||
37 | extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
38 | extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
38 | extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
39 | extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
39 | extern void evergreen_mc_program(struct radeon_device *rdev); |
40 | extern void evergreen_mc_program(struct radeon_device *rdev); |
40 | extern void evergreen_irq_suspend(struct radeon_device *rdev); |
41 | extern void evergreen_irq_suspend(struct radeon_device *rdev); |
41 | extern int evergreen_mc_init(struct radeon_device *rdev); |
42 | extern int evergreen_mc_init(struct radeon_device *rdev); |
- | 43 | extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); |
|
- | 44 | extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev); |
|
- | 45 | extern void si_rlc_fini(struct radeon_device *rdev); |
|
- | 46 | extern int si_rlc_init(struct radeon_device *rdev); |
|
Line 42... | Line 47... | ||
42 | 47 | ||
43 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
48 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
44 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
49 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
45 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
50 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
Line 48... | Line 53... | ||
48 | #define CAYMAN_PFP_UCODE_SIZE 2176 |
53 | #define CAYMAN_PFP_UCODE_SIZE 2176 |
49 | #define CAYMAN_PM4_UCODE_SIZE 2176 |
54 | #define CAYMAN_PM4_UCODE_SIZE 2176 |
50 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
55 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
51 | #define CAYMAN_MC_UCODE_SIZE 6037 |
56 | #define CAYMAN_MC_UCODE_SIZE 6037 |
Line -... | Line 57... | ||
- | 57 | ||
- | 58 | #define ARUBA_RLC_UCODE_SIZE 1536 |
|
52 | 59 | ||
53 | /* Firmware Names */ |
60 | /* Firmware Names */ |
54 | MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); |
61 | MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); |
55 | MODULE_FIRMWARE("radeon/BARTS_me.bin"); |
62 | MODULE_FIRMWARE("radeon/BARTS_me.bin"); |
56 | MODULE_FIRMWARE("radeon/BARTS_mc.bin"); |
63 | MODULE_FIRMWARE("radeon/BARTS_mc.bin"); |
Line 63... | Line 70... | ||
63 | MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); |
70 | MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); |
64 | MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); |
71 | MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); |
65 | MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); |
72 | MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); |
66 | MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); |
73 | MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); |
67 | MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); |
74 | MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); |
- | 75 | MODULE_FIRMWARE("radeon/ARUBA_pfp.bin"); |
|
- | 76 | MODULE_FIRMWARE("radeon/ARUBA_me.bin"); |
|
- | 77 | MODULE_FIRMWARE("radeon/ARUBA_rlc.bin"); |
|
Line 68... | Line 78... | ||
68 | 78 | ||
Line 69... | Line 79... | ||
69 | #define BTC_IO_MC_REGS_SIZE 29 |
79 | #define BTC_IO_MC_REGS_SIZE 29 |
70 | 80 | ||
Line 257... | Line 267... | ||
257 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
267 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
258 | WREG32(MC_SEQ_SUP_CNTL, 0x00000004); |
268 | WREG32(MC_SEQ_SUP_CNTL, 0x00000004); |
259 | WREG32(MC_SEQ_SUP_CNTL, 0x00000001); |
269 | WREG32(MC_SEQ_SUP_CNTL, 0x00000001); |
Line 260... | Line 270... | ||
260 | 270 | ||
- | 271 | /* wait for training to complete */ |
|
261 | /* wait for training to complete */ |
272 | for (i = 0; i < rdev->usec_timeout; i++) { |
- | 273 | if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) |
|
262 | while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)) |
274 | break; |
- | 275 | udelay(1); |
|
Line 263... | Line 276... | ||
263 | udelay(10); |
276 | } |
264 | 277 | ||
265 | if (running) |
278 | if (running) |
Line 318... | Line 331... | ||
318 | pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; |
331 | pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; |
319 | me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; |
332 | me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; |
320 | rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; |
333 | rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; |
321 | mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; |
334 | mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; |
322 | break; |
335 | break; |
- | 336 | case CHIP_ARUBA: |
|
- | 337 | chip_name = "ARUBA"; |
|
- | 338 | rlc_chip_name = "ARUBA"; |
|
- | 339 | /* pfp/me same size as CAYMAN */ |
|
- | 340 | pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; |
|
- | 341 | me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; |
|
- | 342 | rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4; |
|
- | 343 | mc_req_size = 0; |
|
- | 344 | break; |
|
323 | default: BUG(); |
345 | default: BUG(); |
324 | } |
346 | } |
Line 325... | Line 347... | ||
325 | 347 | ||
Line 357... | Line 379... | ||
357 | "ni_rlc: Bogus length %zu in firmware \"%s\"\n", |
379 | "ni_rlc: Bogus length %zu in firmware \"%s\"\n", |
358 | rdev->rlc_fw->size, fw_name); |
380 | rdev->rlc_fw->size, fw_name); |
359 | err = -EINVAL; |
381 | err = -EINVAL; |
360 | } |
382 | } |
Line -... | Line 383... | ||
- | 383 | ||
- | 384 | /* no MC ucode on TN */ |
|
361 | 385 | if (!(rdev->flags & RADEON_IS_IGP)) { |
|
362 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); |
386 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); |
363 | err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev); |
387 | err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev); |
364 | if (err) |
388 | if (err) |
365 | goto out; |
389 | goto out; |
366 | if (rdev->mc_fw->size != mc_req_size) { |
390 | if (rdev->mc_fw->size != mc_req_size) { |
367 | printk(KERN_ERR |
391 | printk(KERN_ERR |
368 | "ni_mc: Bogus length %zu in firmware \"%s\"\n", |
392 | "ni_mc: Bogus length %zu in firmware \"%s\"\n", |
369 | rdev->mc_fw->size, fw_name); |
393 | rdev->mc_fw->size, fw_name); |
370 | err = -EINVAL; |
394 | err = -EINVAL; |
- | 395 | } |
|
371 | } |
396 | } |
372 | out: |
397 | out: |
Line 373... | Line 398... | ||
373 | platform_device_unregister(pdev); |
398 | platform_device_unregister(pdev); |
374 | 399 | ||
Line 390... | Line 415... | ||
390 | } |
415 | } |
Line 391... | Line 416... | ||
391 | 416 | ||
392 | /* |
417 | /* |
393 | * Core functions |
418 | * Core functions |
394 | */ |
- | |
395 | static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
- | |
396 | u32 num_tile_pipes, |
- | |
397 | u32 num_backends_per_asic, |
- | |
398 | u32 *backend_disable_mask_per_asic, |
- | |
399 | u32 num_shader_engines) |
- | |
400 | { |
- | |
401 | u32 backend_map = 0; |
- | |
402 | u32 enabled_backends_mask = 0; |
- | |
403 | u32 enabled_backends_count = 0; |
- | |
404 | u32 num_backends_per_se; |
- | |
405 | u32 cur_pipe; |
- | |
406 | u32 swizzle_pipe[CAYMAN_MAX_PIPES]; |
- | |
407 | u32 cur_backend = 0; |
- | |
408 | u32 i; |
- | |
409 | bool force_no_swizzle; |
- | |
410 | - | ||
411 | /* force legal values */ |
- | |
412 | if (num_tile_pipes < 1) |
- | |
413 | num_tile_pipes = 1; |
- | |
414 | if (num_tile_pipes > rdev->config.cayman.max_tile_pipes) |
- | |
415 | num_tile_pipes = rdev->config.cayman.max_tile_pipes; |
- | |
416 | if (num_shader_engines < 1) |
- | |
417 | num_shader_engines = 1; |
- | |
418 | if (num_shader_engines > rdev->config.cayman.max_shader_engines) |
- | |
419 | num_shader_engines = rdev->config.cayman.max_shader_engines; |
- | |
420 | if (num_backends_per_asic < num_shader_engines) |
- | |
421 | num_backends_per_asic = num_shader_engines; |
- | |
422 | if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines)) |
- | |
423 | num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines; |
- | |
424 | - | ||
425 | /* make sure we have the same number of backends per se */ |
- | |
426 | num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines); |
- | |
427 | /* set up the number of backends per se */ |
- | |
428 | num_backends_per_se = num_backends_per_asic / num_shader_engines; |
- | |
429 | if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) { |
- | |
430 | num_backends_per_se = rdev->config.cayman.max_backends_per_se; |
- | |
431 | num_backends_per_asic = num_backends_per_se * num_shader_engines; |
- | |
432 | } |
- | |
433 | - | ||
434 | /* create enable mask and count for enabled backends */ |
- | |
435 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
- | |
436 | if (((*backend_disable_mask_per_asic >> i) & 1) == 0) { |
- | |
437 | enabled_backends_mask |= (1 << i); |
- | |
438 | ++enabled_backends_count; |
- | |
439 | } |
- | |
440 | if (enabled_backends_count == num_backends_per_asic) |
- | |
441 | break; |
- | |
442 | } |
- | |
443 | - | ||
444 | /* force the backends mask to match the current number of backends */ |
- | |
445 | if (enabled_backends_count != num_backends_per_asic) { |
- | |
446 | u32 this_backend_enabled; |
- | |
447 | u32 shader_engine; |
- | |
448 | u32 backend_per_se; |
- | |
449 | - | ||
450 | enabled_backends_mask = 0; |
- | |
451 | enabled_backends_count = 0; |
- | |
452 | *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK; |
- | |
453 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
- | |
454 | /* calc the current se */ |
- | |
455 | shader_engine = i / rdev->config.cayman.max_backends_per_se; |
- | |
456 | /* calc the backend per se */ |
- | |
457 | backend_per_se = i % rdev->config.cayman.max_backends_per_se; |
- | |
458 | /* default to not enabled */ |
- | |
459 | this_backend_enabled = 0; |
- | |
460 | if ((shader_engine < num_shader_engines) && |
- | |
461 | (backend_per_se < num_backends_per_se)) |
- | |
462 | this_backend_enabled = 1; |
- | |
463 | if (this_backend_enabled) { |
- | |
464 | enabled_backends_mask |= (1 << i); |
- | |
465 | *backend_disable_mask_per_asic &= ~(1 << i); |
- | |
466 | ++enabled_backends_count; |
- | |
467 | } |
- | |
468 | } |
- | |
469 | } |
- | |
470 | - | ||
471 | - | ||
472 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES); |
- | |
473 | switch (rdev->family) { |
- | |
474 | case CHIP_CAYMAN: |
- | |
475 | force_no_swizzle = true; |
- | |
476 | break; |
- | |
477 | default: |
- | |
478 | force_no_swizzle = false; |
- | |
479 | break; |
- | |
480 | } |
- | |
481 | if (force_no_swizzle) { |
- | |
482 | bool last_backend_enabled = false; |
- | |
483 | - | ||
484 | force_no_swizzle = false; |
- | |
485 | for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { |
- | |
486 | if (((enabled_backends_mask >> i) & 1) == 1) { |
- | |
487 | if (last_backend_enabled) |
- | |
488 | force_no_swizzle = true; |
- | |
489 | last_backend_enabled = true; |
- | |
490 | } else |
- | |
491 | last_backend_enabled = false; |
- | |
492 | } |
- | |
493 | } |
- | |
494 | - | ||
495 | switch (num_tile_pipes) { |
- | |
496 | case 1: |
- | |
497 | case 3: |
- | |
498 | case 5: |
- | |
499 | case 7: |
- | |
500 | DRM_ERROR("odd number of pipes!\n"); |
- | |
501 | break; |
- | |
502 | case 2: |
- | |
503 | swizzle_pipe[0] = 0; |
- | |
504 | swizzle_pipe[1] = 1; |
- | |
505 | break; |
- | |
506 | case 4: |
- | |
507 | if (force_no_swizzle) { |
- | |
508 | swizzle_pipe[0] = 0; |
- | |
509 | swizzle_pipe[1] = 1; |
- | |
510 | swizzle_pipe[2] = 2; |
- | |
511 | swizzle_pipe[3] = 3; |
- | |
512 | } else { |
- | |
513 | swizzle_pipe[0] = 0; |
- | |
514 | swizzle_pipe[1] = 2; |
- | |
515 | swizzle_pipe[2] = 1; |
- | |
516 | swizzle_pipe[3] = 3; |
- | |
517 | } |
- | |
518 | break; |
- | |
519 | case 6: |
- | |
520 | if (force_no_swizzle) { |
- | |
521 | swizzle_pipe[0] = 0; |
- | |
522 | swizzle_pipe[1] = 1; |
- | |
523 | swizzle_pipe[2] = 2; |
- | |
524 | swizzle_pipe[3] = 3; |
- | |
525 | swizzle_pipe[4] = 4; |
- | |
526 | swizzle_pipe[5] = 5; |
- | |
527 | } else { |
- | |
528 | swizzle_pipe[0] = 0; |
- | |
529 | swizzle_pipe[1] = 2; |
- | |
530 | swizzle_pipe[2] = 4; |
- | |
531 | swizzle_pipe[3] = 1; |
- | |
532 | swizzle_pipe[4] = 3; |
- | |
533 | swizzle_pipe[5] = 5; |
- | |
534 | } |
- | |
535 | break; |
- | |
536 | case 8: |
- | |
537 | if (force_no_swizzle) { |
- | |
538 | swizzle_pipe[0] = 0; |
- | |
539 | swizzle_pipe[1] = 1; |
- | |
540 | swizzle_pipe[2] = 2; |
- | |
541 | swizzle_pipe[3] = 3; |
- | |
542 | swizzle_pipe[4] = 4; |
- | |
543 | swizzle_pipe[5] = 5; |
- | |
544 | swizzle_pipe[6] = 6; |
- | |
545 | swizzle_pipe[7] = 7; |
- | |
546 | } else { |
- | |
547 | swizzle_pipe[0] = 0; |
- | |
548 | swizzle_pipe[1] = 2; |
- | |
549 | swizzle_pipe[2] = 4; |
- | |
550 | swizzle_pipe[3] = 6; |
- | |
551 | swizzle_pipe[4] = 1; |
- | |
552 | swizzle_pipe[5] = 3; |
- | |
553 | swizzle_pipe[6] = 5; |
- | |
554 | swizzle_pipe[7] = 7; |
- | |
555 | } |
- | |
556 | break; |
- | |
557 | } |
- | |
558 | - | ||
559 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { |
- | |
560 | while (((1 << cur_backend) & enabled_backends_mask) == 0) |
- | |
561 | cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; |
- | |
562 | - | ||
563 | backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); |
- | |
564 | - | ||
565 | cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; |
- | |
566 | } |
- | |
567 | - | ||
568 | return backend_map; |
- | |
569 | } |
- | |
570 | - | ||
571 | static void cayman_program_channel_remap(struct radeon_device *rdev) |
- | |
572 | { |
- | |
573 | u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; |
- | |
574 | - | ||
575 | tmp = RREG32(MC_SHARED_CHMAP); |
- | |
576 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
- | |
577 | case 0: |
- | |
578 | case 1: |
- | |
579 | case 2: |
- | |
580 | case 3: |
- | |
581 | default: |
- | |
582 | /* default mapping */ |
- | |
583 | mc_shared_chremap = 0x00fac688; |
- | |
584 | break; |
- | |
585 | } |
- | |
586 | - | ||
587 | switch (rdev->family) { |
- | |
588 | case CHIP_CAYMAN: |
- | |
589 | default: |
- | |
590 | //tcp_chan_steer_lo = 0x54763210 |
- | |
591 | tcp_chan_steer_lo = 0x76543210; |
- | |
592 | tcp_chan_steer_hi = 0x0000ba98; |
- | |
593 | break; |
- | |
594 | } |
- | |
595 | - | ||
596 | WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); |
- | |
597 | WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); |
- | |
598 | WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); |
- | |
599 | } |
- | |
600 | - | ||
601 | static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, |
- | |
602 | u32 disable_mask_per_se, |
- | |
603 | u32 max_disable_mask_per_se, |
- | |
604 | u32 num_shader_engines) |
- | |
605 | { |
- | |
606 | u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se); |
- | |
607 | u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se; |
- | |
608 | - | ||
609 | if (num_shader_engines == 1) |
- | |
610 | return disable_mask_per_asic; |
- | |
611 | else if (num_shader_engines == 2) |
- | |
612 | return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se); |
- | |
613 | else |
- | |
614 | return 0xffffffff; |
- | |
615 | } |
- | |
616 | 419 | */ |
|
617 | static void cayman_gpu_init(struct radeon_device *rdev) |
420 | static void cayman_gpu_init(struct radeon_device *rdev) |
618 | { |
- | |
619 | u32 cc_rb_backend_disable = 0; |
- | |
620 | u32 cc_gc_shader_pipe_config; |
421 | { |
621 | u32 gb_addr_config = 0; |
422 | u32 gb_addr_config = 0; |
622 | u32 mc_shared_chmap, mc_arb_ramcfg; |
- | |
623 | u32 gb_backend_map; |
423 | u32 mc_shared_chmap, mc_arb_ramcfg; |
624 | u32 cgts_tcc_disable; |
424 | u32 cgts_tcc_disable; |
625 | u32 sx_debug_1; |
425 | u32 sx_debug_1; |
626 | u32 smx_dc_ctl0; |
- | |
627 | u32 gc_user_shader_pipe_config; |
- | |
628 | u32 gc_user_rb_backend_disable; |
- | |
629 | u32 cgts_user_tcc_disable; |
426 | u32 smx_dc_ctl0; |
630 | u32 cgts_sm_ctrl_reg; |
427 | u32 cgts_sm_ctrl_reg; |
631 | u32 hdp_host_path_cntl; |
428 | u32 hdp_host_path_cntl; |
- | 429 | u32 tmp; |
|
632 | u32 tmp; |
430 | u32 disabled_rb_mask; |
Line 633... | Line 431... | ||
633 | int i, j; |
431 | int i, j; |
634 | 432 | ||
635 | switch (rdev->family) { |
- | |
636 | case CHIP_CAYMAN: |
433 | switch (rdev->family) { |
637 | default: |
434 | case CHIP_CAYMAN: |
638 | rdev->config.cayman.max_shader_engines = 2; |
435 | rdev->config.cayman.max_shader_engines = 2; |
639 | rdev->config.cayman.max_pipes_per_simd = 4; |
436 | rdev->config.cayman.max_pipes_per_simd = 4; |
640 | rdev->config.cayman.max_tile_pipes = 8; |
437 | rdev->config.cayman.max_tile_pipes = 8; |
Line 653... | Line 450... | ||
653 | rdev->config.cayman.sq_num_cf_insts = 2; |
450 | rdev->config.cayman.sq_num_cf_insts = 2; |
Line 654... | Line 451... | ||
654 | 451 | ||
655 | rdev->config.cayman.sc_prim_fifo_size = 0x100; |
452 | rdev->config.cayman.sc_prim_fifo_size = 0x100; |
656 | rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; |
453 | rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; |
- | 454 | rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; |
|
- | 455 | gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN; |
|
- | 456 | break; |
|
- | 457 | case CHIP_ARUBA: |
|
- | 458 | default: |
|
- | 459 | rdev->config.cayman.max_shader_engines = 1; |
|
- | 460 | rdev->config.cayman.max_pipes_per_simd = 4; |
|
- | 461 | rdev->config.cayman.max_tile_pipes = 2; |
|
- | 462 | if ((rdev->pdev->device == 0x9900) || |
|
- | 463 | (rdev->pdev->device == 0x9901) || |
|
- | 464 | (rdev->pdev->device == 0x9905) || |
|
- | 465 | (rdev->pdev->device == 0x9906) || |
|
- | 466 | (rdev->pdev->device == 0x9907) || |
|
- | 467 | (rdev->pdev->device == 0x9908) || |
|
- | 468 | (rdev->pdev->device == 0x9909) || |
|
- | 469 | (rdev->pdev->device == 0x9910) || |
|
- | 470 | (rdev->pdev->device == 0x9917)) { |
|
- | 471 | rdev->config.cayman.max_simds_per_se = 6; |
|
- | 472 | rdev->config.cayman.max_backends_per_se = 2; |
|
- | 473 | } else if ((rdev->pdev->device == 0x9903) || |
|
- | 474 | (rdev->pdev->device == 0x9904) || |
|
- | 475 | (rdev->pdev->device == 0x990A) || |
|
- | 476 | (rdev->pdev->device == 0x9913) || |
|
- | 477 | (rdev->pdev->device == 0x9918)) { |
|
- | 478 | rdev->config.cayman.max_simds_per_se = 4; |
|
- | 479 | rdev->config.cayman.max_backends_per_se = 2; |
|
- | 480 | } else if ((rdev->pdev->device == 0x9919) || |
|
- | 481 | (rdev->pdev->device == 0x9990) || |
|
- | 482 | (rdev->pdev->device == 0x9991) || |
|
- | 483 | (rdev->pdev->device == 0x9994) || |
|
- | 484 | (rdev->pdev->device == 0x99A0)) { |
|
- | 485 | rdev->config.cayman.max_simds_per_se = 3; |
|
- | 486 | rdev->config.cayman.max_backends_per_se = 1; |
|
- | 487 | } else { |
|
- | 488 | rdev->config.cayman.max_simds_per_se = 2; |
|
- | 489 | rdev->config.cayman.max_backends_per_se = 1; |
|
- | 490 | } |
|
- | 491 | rdev->config.cayman.max_texture_channel_caches = 2; |
|
- | 492 | rdev->config.cayman.max_gprs = 256; |
|
- | 493 | rdev->config.cayman.max_threads = 256; |
|
- | 494 | rdev->config.cayman.max_gs_threads = 32; |
|
- | 495 | rdev->config.cayman.max_stack_entries = 512; |
|
- | 496 | rdev->config.cayman.sx_num_of_sets = 8; |
|
- | 497 | rdev->config.cayman.sx_max_export_size = 256; |
|
- | 498 | rdev->config.cayman.sx_max_export_pos_size = 64; |
|
- | 499 | rdev->config.cayman.sx_max_export_smx_size = 192; |
|
- | 500 | rdev->config.cayman.max_hw_contexts = 8; |
|
- | 501 | rdev->config.cayman.sq_num_cf_insts = 2; |
|
- | 502 | ||
- | 503 | rdev->config.cayman.sc_prim_fifo_size = 0x40; |
|
- | 504 | rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; |
|
- | 505 | rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; |
|
657 | rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; |
506 | gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN; |
658 | break; |
507 | break; |
Line 659... | Line 508... | ||
659 | } |
508 | } |
660 | 509 | ||
Line 667... | Line 516... | ||
667 | WREG32((0x2c24 + j), 0x00000000); |
516 | WREG32((0x2c24 + j), 0x00000000); |
668 | } |
517 | } |
Line 669... | Line 518... | ||
669 | 518 | ||
Line -... | Line 519... | ||
- | 519 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
|
- | 520 | ||
670 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
521 | evergreen_fix_pci_max_read_req_size(rdev); |
671 | 522 | ||
Line 672... | Line -... | ||
672 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); |
- | |
673 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
- | |
674 | - | ||
675 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE); |
- | |
676 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); |
- | |
677 | cgts_tcc_disable = 0xff000000; |
- | |
678 | gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE); |
- | |
679 | gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG); |
- | |
680 | cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE); |
- | |
681 | - | ||
682 | rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines; |
- | |
683 | tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; |
- | |
684 | rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp); |
- | |
685 | rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes; |
- | |
686 | tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT; |
- | |
687 | rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp); |
- | |
688 | tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; |
- | |
689 | rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp); |
- | |
690 | tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; |
- | |
691 | rdev->config.cayman.backend_disable_mask_per_asic = |
- | |
692 | cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK, |
- | |
693 | rdev->config.cayman.num_shader_engines); |
- | |
694 | rdev->config.cayman.backend_map = |
- | |
695 | cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, |
- | |
696 | rdev->config.cayman.num_backends_per_se * |
- | |
697 | rdev->config.cayman.num_shader_engines, |
- | |
698 | &rdev->config.cayman.backend_disable_mask_per_asic, |
- | |
699 | rdev->config.cayman.num_shader_engines); |
- | |
700 | tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT; |
- | |
701 | rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp); |
- | |
702 | tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT; |
- | |
703 | rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; |
523 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); |
704 | if (rdev->config.cayman.mem_max_burst_length_bytes > 512) |
524 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
705 | rdev->config.cayman.mem_max_burst_length_bytes = 512; |
525 | |
706 | tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; |
526 | tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; |
707 | rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; |
527 | rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; |
708 | if (rdev->config.cayman.mem_row_size_in_kb > 4) |
528 | if (rdev->config.cayman.mem_row_size_in_kb > 4) |
709 | rdev->config.cayman.mem_row_size_in_kb = 4; |
529 | rdev->config.cayman.mem_row_size_in_kb = 4; |
710 | /* XXX use MC settings? */ |
530 | /* XXX use MC settings? */ |
Line 711... | Line -... | ||
711 | rdev->config.cayman.shader_engine_tile_size = 32; |
- | |
712 | rdev->config.cayman.num_gpus = 1; |
- | |
713 | rdev->config.cayman.multi_gpu_tile_size = 64; |
- | |
714 | - | ||
715 | //gb_addr_config = 0x02011003 |
- | |
716 | #if 0 |
- | |
717 | gb_addr_config = RREG32(GB_ADDR_CONFIG); |
- | |
718 | #else |
- | |
719 | gb_addr_config = 0; |
- | |
720 | switch (rdev->config.cayman.num_tile_pipes) { |
- | |
721 | case 1: |
- | |
722 | default: |
- | |
723 | gb_addr_config |= NUM_PIPES(0); |
- | |
724 | break; |
- | |
725 | case 2: |
- | |
726 | gb_addr_config |= NUM_PIPES(1); |
- | |
727 | break; |
- | |
728 | case 4: |
- | |
729 | gb_addr_config |= NUM_PIPES(2); |
- | |
730 | break; |
- | |
731 | case 8: |
- | |
732 | gb_addr_config |= NUM_PIPES(3); |
- | |
733 | break; |
- | |
734 | } |
- | |
735 | - | ||
736 | tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1; |
- | |
737 | gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp); |
- | |
738 | gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1); |
- | |
739 | tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1; |
- | |
740 | gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp); |
- | |
741 | switch (rdev->config.cayman.num_gpus) { |
- | |
742 | case 1: |
- | |
743 | default: |
- | |
744 | gb_addr_config |= NUM_GPUS(0); |
- | |
745 | break; |
- | |
746 | case 2: |
- | |
747 | gb_addr_config |= NUM_GPUS(1); |
- | |
748 | break; |
- | |
749 | case 4: |
- | |
750 | gb_addr_config |= NUM_GPUS(2); |
- | |
751 | break; |
- | |
752 | } |
- | |
753 | switch (rdev->config.cayman.multi_gpu_tile_size) { |
- | |
754 | case 16: |
- | |
755 | gb_addr_config |= MULTI_GPU_TILE_SIZE(0); |
- | |
756 | break; |
- | |
757 | case 32: |
- | |
758 | default: |
- | |
759 | gb_addr_config |= MULTI_GPU_TILE_SIZE(1); |
- | |
760 | break; |
- | |
761 | case 64: |
- | |
762 | gb_addr_config |= MULTI_GPU_TILE_SIZE(2); |
- | |
763 | break; |
- | |
764 | case 128: |
- | |
765 | gb_addr_config |= MULTI_GPU_TILE_SIZE(3); |
- | |
766 | break; |
- | |
767 | } |
- | |
768 | switch (rdev->config.cayman.mem_row_size_in_kb) { |
- | |
769 | case 1: |
- | |
770 | default: |
- | |
771 | gb_addr_config |= ROW_SIZE(0); |
- | |
772 | break; |
- | |
773 | case 2: |
- | |
774 | gb_addr_config |= ROW_SIZE(1); |
- | |
775 | break; |
- | |
776 | case 4: |
- | |
777 | gb_addr_config |= ROW_SIZE(2); |
- | |
778 | break; |
531 | rdev->config.cayman.shader_engine_tile_size = 32; |
779 | } |
532 | rdev->config.cayman.num_gpus = 1; |
780 | #endif |
533 | rdev->config.cayman.multi_gpu_tile_size = 64; |
781 | 534 | ||
782 | tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; |
535 | tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; |
Line 790... | Line 543... | ||
790 | tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; |
543 | tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; |
791 | rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; |
544 | rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; |
792 | tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; |
545 | tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; |
793 | rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; |
546 | rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; |
Line 794... | Line -... | ||
794 | - | ||
795 | //gb_backend_map = 0x76541032; |
- | |
796 | #if 0 |
- | |
797 | gb_backend_map = RREG32(GB_BACKEND_MAP); |
547 | |
798 | #else |
- | |
799 | gb_backend_map = |
- | |
800 | cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, |
- | |
801 | rdev->config.cayman.num_backends_per_se * |
- | |
802 | rdev->config.cayman.num_shader_engines, |
- | |
803 | &rdev->config.cayman.backend_disable_mask_per_asic, |
- | |
804 | rdev->config.cayman.num_shader_engines); |
- | |
805 | #endif |
548 | |
806 | /* setup tiling info dword. gb_addr_config is not adequate since it does |
549 | /* setup tiling info dword. gb_addr_config is not adequate since it does |
807 | * not have bank info, so create a custom tiling dword. |
550 | * not have bank info, so create a custom tiling dword. |
808 | * bits 3:0 num_pipes |
551 | * bits 3:0 num_pipes |
809 | * bits 7:4 num_banks |
552 | * bits 7:4 num_banks |
Line 824... | Line 567... | ||
824 | break; |
567 | break; |
825 | case 8: |
568 | case 8: |
826 | rdev->config.cayman.tile_config |= (3 << 0); |
569 | rdev->config.cayman.tile_config |= (3 << 0); |
827 | break; |
570 | break; |
828 | } |
571 | } |
- | 572 | ||
- | 573 | /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ |
|
- | 574 | if (rdev->flags & RADEON_IS_IGP) |
|
829 | rdev->config.cayman.tile_config |= |
575 | rdev->config.cayman.tile_config |= 1 << 4; |
- | 576 | else { |
|
830 | ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; |
577 | switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { |
- | 578 | case 0: /* four banks */ |
|
- | 579 | rdev->config.cayman.tile_config |= 0 << 4; |
|
- | 580 | break; |
|
- | 581 | case 1: /* eight banks */ |
|
- | 582 | rdev->config.cayman.tile_config |= 1 << 4; |
|
- | 583 | break; |
|
- | 584 | case 2: /* sixteen banks */ |
|
- | 585 | default: |
|
- | 586 | rdev->config.cayman.tile_config |= 2 << 4; |
|
- | 587 | break; |
|
- | 588 | } |
|
- | 589 | } |
|
831 | rdev->config.cayman.tile_config |= |
590 | rdev->config.cayman.tile_config |= |
832 | ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; |
591 | ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; |
833 | rdev->config.cayman.tile_config |= |
592 | rdev->config.cayman.tile_config |= |
834 | ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; |
593 | ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; |
Line -... | Line 594... | ||
- | 594 | ||
835 | 595 | tmp = 0; |
|
- | 596 | for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { |
|
- | 597 | u32 rb_disable_bitmap; |
|
836 | rdev->config.cayman.backend_map = gb_backend_map; |
598 | |
- | 599 | WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); |
|
- | 600 | WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); |
|
- | 601 | rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; |
|
- | 602 | tmp <<= 4; |
|
- | 603 | tmp |= rb_disable_bitmap; |
|
- | 604 | } |
|
- | 605 | /* enabled rb are just the one not disabled :) */ |
|
- | 606 | disabled_rb_mask = tmp; |
|
- | 607 | ||
- | 608 | WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
|
- | 609 | WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
|
837 | WREG32(GB_BACKEND_MAP, gb_backend_map); |
610 | |
838 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
611 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
839 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
612 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
Line 840... | Line 613... | ||
840 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
613 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
841 | - | ||
842 | cayman_program_channel_remap(rdev); |
614 | |
843 | 615 | tmp = gb_addr_config & NUM_PIPES_MASK; |
|
- | 616 | tmp = r6xx_remap_render_backend(rdev, tmp, |
|
844 | /* primary versions */ |
617 | rdev->config.cayman.max_backends_per_se * |
845 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
618 | rdev->config.cayman.max_shader_engines, |
846 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
619 | CAYMAN_MAX_BACKENDS, disabled_rb_mask); |
- | 620 | WREG32(GB_BACKEND_MAP, tmp); |
|
- | 621 | ||
- | 622 | cgts_tcc_disable = 0xffff0000; |
|
847 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
623 | for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) |
848 | 624 | cgts_tcc_disable &= ~(1 << (16 + i)); |
|
849 | WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); |
- | |
850 | WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); |
- | |
851 | - | ||
852 | /* user versions */ |
- | |
853 | WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
- | |
854 | WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
- | |
855 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
625 | WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); |
856 | 626 | WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); |
|
Line 857... | Line 627... | ||
857 | WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); |
627 | WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); |
858 | WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); |
628 | WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); |
Line 954... | Line 724... | ||
954 | 724 | ||
955 | /* bits 0-7 are the VM contexts0-7 */ |
725 | /* bits 0-7 are the VM contexts0-7 */ |
956 | WREG32(VM_INVALIDATE_REQUEST, 1); |
726 | WREG32(VM_INVALIDATE_REQUEST, 1); |
Line 957... | Line 727... | ||
957 | } |
727 | } |
958 | 728 | ||
959 | int cayman_pcie_gart_enable(struct radeon_device *rdev) |
729 | static int cayman_pcie_gart_enable(struct radeon_device *rdev) |
Line 960... | Line 730... | ||
960 | { |
730 | { |
961 | int r; |
731 | int i, r; |
962 | 732 | ||
963 | if (rdev->gart.table.vram.robj == NULL) { |
733 | if (rdev->gart.robj == NULL) { |
964 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
734 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
965 | return -EINVAL; |
735 | return -EINVAL; |
966 | } |
736 | } |
967 | r = radeon_gart_table_vram_pin(rdev); |
737 | r = radeon_gart_table_vram_pin(rdev); |
968 | if (r) |
738 | if (r) |
969 | return r; |
739 | return r; |
- | 740 | radeon_gart_restore(rdev); |
|
- | 741 | /* Setup TLB control */ |
|
970 | radeon_gart_restore(rdev); |
742 | WREG32(MC_VM_MX_L1_TLB_CNTL, |
971 | /* Setup TLB control */ |
743 | (0xA << 7) | |
- | 744 | ENABLE_L1_TLB | |
|
972 | WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB | |
745 | ENABLE_L1_FRAGMENT_PROCESSING | |
973 | ENABLE_L1_FRAGMENT_PROCESSING | |
746 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
974 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
747 | ENABLE_ADVANCED_DRIVER_MODEL | |
975 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
748 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
976 | /* Setup L2 cache */ |
749 | /* Setup L2 cache */ |
Line 989... | Line 762... | ||
989 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
762 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
990 | (u32)(rdev->dummy_page.addr >> 12)); |
763 | (u32)(rdev->dummy_page.addr >> 12)); |
991 | WREG32(VM_CONTEXT0_CNTL2, 0); |
764 | WREG32(VM_CONTEXT0_CNTL2, 0); |
992 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
765 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
993 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
766 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
- | 767 | ||
- | 768 | WREG32(0x15D4, 0); |
|
- | 769 | WREG32(0x15D8, 0); |
|
- | 770 | WREG32(0x15DC, 0); |
|
- | 771 | ||
- | 772 | /* empty context1-7 */ |
|
- | 773 | /* Assign the pt base to something valid for now; the pts used for |
|
- | 774 | * the VMs are determined by the application and setup and assigned |
|
- | 775 | * on the fly in the vm part of radeon_gart.c |
|
- | 776 | */ |
|
- | 777 | for (i = 1; i < 8; i++) { |
|
- | 778 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); |
|
- | 779 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn); |
|
- | 780 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), |
|
- | 781 | rdev->gart.table_addr >> 12); |
|
- | 782 | } |
|
- | 783 | ||
994 | /* disable context1-7 */ |
784 | /* enable context1-7 */ |
- | 785 | WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, |
|
- | 786 | (u32)(rdev->dummy_page.addr >> 12)); |
|
995 | WREG32(VM_CONTEXT1_CNTL2, 0); |
787 | WREG32(VM_CONTEXT1_CNTL2, 0); |
996 | WREG32(VM_CONTEXT1_CNTL, 0); |
788 | WREG32(VM_CONTEXT1_CNTL, 0); |
- | 789 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | |
|
- | 790 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
|
Line 997... | Line 791... | ||
997 | 791 | ||
- | 792 | cayman_pcie_gart_tlb_flush(rdev); |
|
- | 793 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
|
- | 794 | (unsigned)(rdev->mc.gtt_size >> 20), |
|
998 | cayman_pcie_gart_tlb_flush(rdev); |
795 | (unsigned long long)rdev->gart.table_addr); |
999 | rdev->gart.ready = true; |
796 | rdev->gart.ready = true; |
1000 | return 0; |
797 | return 0; |
Line 1001... | Line 798... | ||
1001 | } |
798 | } |
1002 | 799 | ||
1003 | void cayman_pcie_gart_disable(struct radeon_device *rdev) |
- | |
1004 | { |
- | |
1005 | int r; |
800 | static void cayman_pcie_gart_disable(struct radeon_device *rdev) |
1006 | 801 | { |
|
1007 | /* Disable all tables */ |
802 | /* Disable all tables */ |
1008 | WREG32(VM_CONTEXT0_CNTL, 0); |
803 | WREG32(VM_CONTEXT0_CNTL, 0); |
1009 | WREG32(VM_CONTEXT1_CNTL, 0); |
804 | WREG32(VM_CONTEXT1_CNTL, 0); |
Line 1017... | Line 812... | ||
1017 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
812 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
1018 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
813 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
1019 | WREG32(VM_L2_CNTL2, 0); |
814 | WREG32(VM_L2_CNTL2, 0); |
1020 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
815 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
1021 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
816 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
1022 | if (rdev->gart.table.vram.robj) { |
817 | radeon_gart_table_vram_unpin(rdev); |
1023 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
- | |
1024 | if (likely(r == 0)) { |
- | |
1025 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
- | |
1026 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
- | |
1027 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
- | |
1028 | } |
- | |
1029 | } |
- | |
1030 | } |
818 | } |
Line -... | Line 819... | ||
- | 819 | ||
- | 820 | void cayman_cp_int_cntl_setup(struct radeon_device *rdev, |
|
- | 821 | int ring, u32 cp_int_cntl) |
|
- | 822 | { |
|
- | 823 | u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3; |
|
- | 824 | ||
- | 825 | WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3)); |
|
- | 826 | WREG32(CP_INT_CNTL, cp_int_cntl); |
|
Line 1031... | Line 827... | ||
1031 | 827 | } |
|
1032 | 828 | ||
1033 | /* |
829 | /* |
- | 830 | * CP. |
|
- | 831 | */ |
|
- | 832 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
|
- | 833 | struct radeon_fence *fence) |
|
- | 834 | { |
|
- | 835 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
|
- | 836 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
|
- | 837 | ||
- | 838 | /* flush read cache over gart for this vmid */ |
|
- | 839 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
|
- | 840 | radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); |
|
- | 841 | radeon_ring_write(ring, 0); |
|
- | 842 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
|
- | 843 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); |
|
- | 844 | radeon_ring_write(ring, 0xFFFFFFFF); |
|
- | 845 | radeon_ring_write(ring, 0); |
|
- | 846 | radeon_ring_write(ring, 10); /* poll interval */ |
|
- | 847 | /* EVENT_WRITE_EOP - flush caches, send int */ |
|
- | 848 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
|
- | 849 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); |
|
- | 850 | radeon_ring_write(ring, addr & 0xffffffff); |
|
- | 851 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); |
|
- | 852 | radeon_ring_write(ring, fence->seq); |
|
- | 853 | radeon_ring_write(ring, 0); |
|
- | 854 | } |
|
- | 855 | ||
- | 856 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
|
- | 857 | { |
|
- | 858 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
|
- | 859 | ||
- | 860 | /* set to DX10/11 mode */ |
|
- | 861 | radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); |
|
- | 862 | radeon_ring_write(ring, 1); |
|
- | 863 | ||
- | 864 | if (ring->rptr_save_reg) { |
|
- | 865 | uint32_t next_rptr = ring->wptr + 3 + 4 + 8; |
|
- | 866 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
|
- | 867 | radeon_ring_write(ring, ((ring->rptr_save_reg - |
|
- | 868 | PACKET3_SET_CONFIG_REG_START) >> 2)); |
|
- | 869 | radeon_ring_write(ring, next_rptr); |
|
- | 870 | } |
|
- | 871 | ||
- | 872 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
|
- | 873 | radeon_ring_write(ring, |
|
- | 874 | #ifdef __BIG_ENDIAN |
|
- | 875 | (2 << 0) | |
|
- | 876 | #endif |
|
- | 877 | (ib->gpu_addr & 0xFFFFFFFC)); |
|
- | 878 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
|
- | 879 | radeon_ring_write(ring, ib->length_dw | |
|
- | 880 | (ib->vm ? (ib->vm->id << 24) : 0)); |
|
- | 881 | ||
- | 882 | /* flush read cache over gart for this vmid */ |
|
- | 883 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
|
- | 884 | radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); |
|
- | 885 | radeon_ring_write(ring, ib->vm ? ib->vm->id : 0); |
|
- | 886 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
|
- | 887 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); |
|
- | 888 | radeon_ring_write(ring, 0xFFFFFFFF); |
|
- | 889 | radeon_ring_write(ring, 0); |
|
- | 890 | radeon_ring_write(ring, 10); /* poll interval */ |
|
1034 | * CP. |
891 | } |
1035 | */ |
892 | |
1036 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
893 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
1037 | { |
894 | { |
1038 | if (enable) |
895 | if (enable) |
Line 1070... | Line 927... | ||
1070 | return 0; |
927 | return 0; |
1071 | } |
928 | } |
Line 1072... | Line 929... | ||
1072 | 929 | ||
1073 | static int cayman_cp_start(struct radeon_device *rdev) |
930 | static int cayman_cp_start(struct radeon_device *rdev) |
- | 931 | { |
|
1074 | { |
932 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Line 1075... | Line 933... | ||
1075 | int r, i; |
933 | int r, i; |
1076 | 934 | ||
1077 | r = radeon_ring_lock(rdev, 7); |
935 | r = radeon_ring_lock(rdev, ring, 7); |
1078 | if (r) { |
936 | if (r) { |
1079 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
937 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
1080 | return r; |
938 | return r; |
1081 | } |
939 | } |
1082 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
940 | radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
1083 | radeon_ring_write(rdev, 0x1); |
941 | radeon_ring_write(ring, 0x1); |
1084 | radeon_ring_write(rdev, 0x0); |
942 | radeon_ring_write(ring, 0x0); |
1085 | radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1); |
943 | radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); |
1086 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
944 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
1087 | radeon_ring_write(rdev, 0); |
945 | radeon_ring_write(ring, 0); |
Line 1088... | Line 946... | ||
1088 | radeon_ring_write(rdev, 0); |
946 | radeon_ring_write(ring, 0); |
Line 1089... | Line 947... | ||
1089 | radeon_ring_unlock_commit(rdev); |
947 | radeon_ring_unlock_commit(rdev, ring); |
1090 | 948 | ||
1091 | cayman_cp_enable(rdev, true); |
949 | cayman_cp_enable(rdev, true); |
1092 | 950 | ||
1093 | r = radeon_ring_lock(rdev, cayman_default_size + 19); |
951 | r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); |
Line 1094... | Line 952... | ||
1094 | if (r) { |
952 | if (r) { |
1095 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
953 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
1096 | return r; |
954 | return r; |
Line 1097... | Line 955... | ||
1097 | } |
955 | } |
1098 | 956 | ||
Line 1099... | Line 957... | ||
1099 | /* setup clear context state */ |
957 | /* setup clear context state */ |
1100 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
958 | radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
Line 1101... | Line 959... | ||
1101 | radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); |
959 | radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); |
1102 | 960 | ||
1103 | for (i = 0; i < cayman_default_size; i++) |
961 | for (i = 0; i < cayman_default_size; i++) |
Line 1104... | Line 962... | ||
1104 | radeon_ring_write(rdev, cayman_default_state[i]); |
962 | radeon_ring_write(ring, cayman_default_state[i]); |
1105 | 963 | ||
1106 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
964 | radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
1107 | radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); |
965 | radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); |
1108 | 966 | ||
Line 1109... | Line 967... | ||
1109 | /* set clear context state */ |
967 | /* set clear context state */ |
1110 | radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); |
968 | radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); |
1111 | radeon_ring_write(rdev, 0); |
969 | radeon_ring_write(ring, 0); |
1112 | 970 | ||
1113 | /* SQ_VTX_BASE_VTX_LOC */ |
971 | /* SQ_VTX_BASE_VTX_LOC */ |
1114 | radeon_ring_write(rdev, 0xc0026f00); |
972 | radeon_ring_write(ring, 0xc0026f00); |
1115 | radeon_ring_write(rdev, 0x00000000); |
973 | radeon_ring_write(ring, 0x00000000); |
1116 | radeon_ring_write(rdev, 0x00000000); |
974 | radeon_ring_write(ring, 0x00000000); |
1117 | radeon_ring_write(rdev, 0x00000000); |
975 | radeon_ring_write(ring, 0x00000000); |
1118 | 976 | ||
1119 | /* Clear consts */ |
977 | /* Clear consts */ |
Line 1120... | Line 978... | ||
1120 | radeon_ring_write(rdev, 0xc0036f00); |
978 | radeon_ring_write(ring, 0xc0036f00); |
Line 1121... | Line 979... | ||
1121 | radeon_ring_write(rdev, 0x00000bc4); |
979 | radeon_ring_write(ring, 0x00000bc4); |
Line 1122... | Line 980... | ||
1122 | radeon_ring_write(rdev, 0xffffffff); |
980 | radeon_ring_write(ring, 0xffffffff); |
1123 | radeon_ring_write(rdev, 0xffffffff); |
981 | radeon_ring_write(ring, 0xffffffff); |
Line 1124... | Line -... | ||
1124 | radeon_ring_write(rdev, 0xffffffff); |
- | |
1125 | 982 | radeon_ring_write(ring, 0xffffffff); |
|
1126 | radeon_ring_write(rdev, 0xc0026900); |
983 | |
- | 984 | radeon_ring_write(ring, 0xc0026900); |
|
- | 985 | radeon_ring_write(ring, 0x00000316); |
|
- | 986 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
|
- | 987 | radeon_ring_write(ring, 0x00000010); /* */ |
|
1127 | radeon_ring_write(rdev, 0x00000316); |
988 | |
- | 989 | radeon_ring_unlock_commit(rdev, ring); |
|
- | 990 | ||
- | 991 | /* XXX init other rings */ |
|
- | 992 | ||
- | 993 | return 0; |
|
- | 994 | } |
|
- | 995 | ||
- | 996 | ||
- | 997 | static int cayman_cp_resume(struct radeon_device *rdev) |
|
- | 998 | { |
|
- | 999 | static const int ridx[] = { |
|
- | 1000 | RADEON_RING_TYPE_GFX_INDEX, |
|
- | 1001 | CAYMAN_RING_TYPE_CP1_INDEX, |
|
- | 1002 | CAYMAN_RING_TYPE_CP2_INDEX |
|
- | 1003 | }; |
|
- | 1004 | static const unsigned cp_rb_cntl[] = { |
|
- | 1005 | CP_RB0_CNTL, |
|
1128 | radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
1006 | CP_RB1_CNTL, |
- | 1007 | CP_RB2_CNTL, |
|
- | 1008 | }; |
|
- | 1009 | static const unsigned cp_rb_rptr_addr[] = { |
|
1129 | radeon_ring_write(rdev, 0x00000010); /* */ |
1010 | CP_RB0_RPTR_ADDR, |
Line 1130... | Line 1011... | ||
1130 | 1011 | CP_RB1_RPTR_ADDR, |
|
1131 | radeon_ring_unlock_commit(rdev); |
1012 | CP_RB2_RPTR_ADDR |
1132 | 1013 | }; |
|
1133 | /* XXX init other rings */ |
1014 | static const unsigned cp_rb_rptr_addr_hi[] = { |
Line 1153... | Line 1034... | ||
1153 | RREG32(GRBM_SOFT_RESET); |
1034 | RREG32(GRBM_SOFT_RESET); |
1154 | mdelay(15); |
1035 | mdelay(15); |
1155 | WREG32(GRBM_SOFT_RESET, 0); |
1036 | WREG32(GRBM_SOFT_RESET, 0); |
1156 | RREG32(GRBM_SOFT_RESET); |
1037 | RREG32(GRBM_SOFT_RESET); |
Line 1157... | Line 1038... | ||
1157 | 1038 | ||
- | 1039 | WREG32(CP_SEM_WAIT_TIMER, 0x0); |
|
Line 1158... | Line 1040... | ||
1158 | WREG32(CP_SEM_WAIT_TIMER, 0x4); |
1040 | WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); |
1159 | 1041 | ||
Line 1160... | Line 1042... | ||
1160 | /* Set the write pointer delay */ |
1042 | /* Set the write pointer delay */ |
Line 1161... | Line -... | ||
1161 | WREG32(CP_RB_WPTR_DELAY, 0); |
- | |
1162 | - | ||
1163 | WREG32(CP_DEBUG, (1 << 27)); |
- | |
1164 | - | ||
1165 | /* ring 0 - compute and gfx */ |
- | |
1166 | /* Set ring buffer size */ |
- | |
1167 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); |
- | |
1168 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
- | |
1169 | #ifdef __BIG_ENDIAN |
- | |
1170 | tmp |= BUF_SWAP_32BIT; |
- | |
1171 | #endif |
- | |
1172 | WREG32(CP_RB0_CNTL, tmp); |
- | |
1173 | - | ||
1174 | /* Initialize the ring buffer's read and write pointers */ |
1043 | WREG32(CP_RB_WPTR_DELAY, 0); |
1175 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); |
- | |
1176 | WREG32(CP_RB0_WPTR, 0); |
- | |
1177 | 1044 | ||
1178 | /* set the wb address wether it's enabled or not */ |
- | |
1179 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); |
- | |
1180 | WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
1045 | WREG32(CP_DEBUG, (1 << 27)); |
1181 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
- | |
1182 | - | ||
1183 | if (rdev->wb.enabled) |
- | |
1184 | WREG32(SCRATCH_UMSK, 0xff); |
- | |
1185 | else { |
- | |
1186 | tmp |= RB_NO_UPDATE; |
- | |
1187 | WREG32(SCRATCH_UMSK, 0); |
- | |
1188 | } |
- | |
1189 | - | ||
Line 1190... | Line 1046... | ||
1190 | mdelay(1); |
1046 | |
1191 | WREG32(CP_RB0_CNTL, tmp); |
1047 | /* set the wb address wether it's enabled or not */ |
- | 1048 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
|
Line 1192... | Line -... | ||
1192 | - | ||
1193 | WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); |
1049 | WREG32(SCRATCH_UMSK, 0xff); |
- | 1050 | ||
1194 | 1051 | for (i = 0; i < 3; ++i) { |
|
1195 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); |
1052 | uint32_t rb_cntl; |
1196 | rdev->cp.wptr = RREG32(CP_RB0_WPTR); |
1053 | uint64_t addr; |
1197 | 1054 | ||
1198 | /* ring1 - compute only */ |
1055 | /* Set ring buffer size */ |
1199 | /* Set ring buffer size */ |
1056 | ring = &rdev->ring[ridx[i]]; |
1200 | rb_bufsz = drm_order(rdev->cp1.ring_size / 8); |
- | |
1201 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
- | |
1202 | #ifdef __BIG_ENDIAN |
- | |
1203 | tmp |= BUF_SWAP_32BIT; |
- | |
Line 1204... | Line 1057... | ||
1204 | #endif |
1057 | rb_cntl = drm_order(ring->ring_size / 8); |
1205 | WREG32(CP_RB1_CNTL, tmp); |
1058 | rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8; |
1206 | - | ||
1207 | /* Initialize the ring buffer's read and write pointers */ |
- | |
1208 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); |
- | |
1209 | WREG32(CP_RB1_WPTR, 0); |
1059 | #ifdef __BIG_ENDIAN |
1210 | - | ||
1211 | /* set the wb address wether it's enabled or not */ |
1060 | rb_cntl |= BUF_SWAP_32BIT; |
1212 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); |
1061 | #endif |
1213 | WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); |
- | |
1214 | - | ||
Line 1215... | Line 1062... | ||
1215 | mdelay(1); |
1062 | WREG32(cp_rb_cntl[i], rb_cntl); |
1216 | WREG32(CP_RB1_CNTL, tmp); |
1063 | |
1217 | 1064 | /* set the wb address wether it's enabled or not */ |
|
1218 | WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); |
1065 | addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; |
1219 | - | ||
1220 | rdev->cp1.rptr = RREG32(CP_RB1_RPTR); |
- | |
1221 | rdev->cp1.wptr = RREG32(CP_RB1_WPTR); |
1066 | WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC); |
1222 | - | ||
Line -... | Line 1067... | ||
- | 1067 | WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); |
|
1223 | /* ring2 - compute only */ |
1068 | } |
1224 | /* Set ring buffer size */ |
1069 | |
1225 | rb_bufsz = drm_order(rdev->cp2.ring_size / 8); |
1070 | /* set the rb base addr, this causes an internal reset of ALL rings */ |
Line 1226... | Line 1071... | ||
1226 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
1071 | for (i = 0; i < 3; ++i) { |
1227 | #ifdef __BIG_ENDIAN |
1072 | ring = &rdev->ring[ridx[i]]; |
1228 | tmp |= BUF_SWAP_32BIT; |
1073 | WREG32(cp_rb_base[i], ring->gpu_addr >> 8); |
Line 1229... | Line 1074... | ||
1229 | #endif |
1074 | } |
1230 | WREG32(CP_RB2_CNTL, tmp); |
- | |
1231 | - | ||
1232 | /* Initialize the ring buffer's read and write pointers */ |
1075 | |
1233 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); |
1076 | for (i = 0; i < 3; ++i) { |
1234 | WREG32(CP_RB2_WPTR, 0); |
- | |
1235 | - | ||
Line 1236... | Line 1077... | ||
1236 | /* set the wb address wether it's enabled or not */ |
1077 | /* Initialize the ring buffer's read and write pointers */ |
1237 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); |
1078 | ring = &rdev->ring[ridx[i]]; |
1238 | WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); |
1079 | WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); |
1239 | 1080 | ||
1240 | mdelay(1); |
1081 | ring->rptr = ring->wptr = 0; |
1241 | WREG32(CP_RB2_CNTL, tmp); |
1082 | WREG32(ring->rptr_reg, ring->rptr); |
1242 | 1083 | WREG32(ring->wptr_reg, ring->wptr); |
|
1243 | WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); |
1084 | |
1244 | 1085 | mdelay(1); |
|
1245 | rdev->cp2.rptr = RREG32(CP_RB2_RPTR); |
1086 | WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); |
1246 | rdev->cp2.wptr = RREG32(CP_RB2_WPTR); |
1087 | } |
1247 | 1088 | ||
1248 | /* start the rings */ |
1089 | /* start the rings */ |
Line 1249... | Line 1090... | ||
1249 | cayman_cp_start(rdev); |
1090 | cayman_cp_start(rdev); |
1250 | rdev->cp.ready = true; |
1091 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; |
Line 1251... | Line -... | ||
1251 | rdev->cp1.ready = true; |
- | |
1252 | rdev->cp2.ready = true; |
- | |
1253 | /* this only test cp0 */ |
- | |
1254 | r = radeon_ring_test(rdev); |
- | |
1255 | if (r) { |
- | |
1256 | rdev->cp.ready = false; |
- | |
1257 | rdev->cp1.ready = false; |
- | |
1258 | rdev->cp2.ready = false; |
- | |
1259 | return r; |
- | |
1260 | } |
- | |
1261 | - | ||
1262 | return 0; |
- | |
1263 | } |
- | |
1264 | - | ||
1265 | bool cayman_gpu_is_lockup(struct radeon_device *rdev) |
- | |
1266 | { |
- | |
1267 | u32 srbm_status; |
- | |
1268 | u32 grbm_status; |
- | |
1269 | u32 grbm_status_se0, grbm_status_se1; |
- | |
1270 | struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup; |
- | |
1271 | int r; |
- | |
1272 | - | ||
1273 | srbm_status = RREG32(SRBM_STATUS); |
- | |
1274 | grbm_status = RREG32(GRBM_STATUS); |
- | |
1275 | grbm_status_se0 = RREG32(GRBM_STATUS_SE0); |
- | |
1276 | grbm_status_se1 = RREG32(GRBM_STATUS_SE1); |
- | |
1277 | if (!(grbm_status & GUI_ACTIVE)) { |
- | |
1278 | r100_gpu_lockup_update(lockup, &rdev->cp); |
- | |
1279 | return false; |
- | |
1280 | } |
1092 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; |
1281 | /* force CP activities */ |
1093 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; |
1282 | r = radeon_ring_lock(rdev, 2); |
1094 | /* this only test cp0 */ |
1283 | if (!r) { |
1095 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
Line 1306... | Line 1118... | ||
1306 | RREG32(GRBM_STATUS_SE0)); |
1118 | RREG32(GRBM_STATUS_SE0)); |
1307 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
1119 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
1308 | RREG32(GRBM_STATUS_SE1)); |
1120 | RREG32(GRBM_STATUS_SE1)); |
1309 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
1121 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
1310 | RREG32(SRBM_STATUS)); |
1122 | RREG32(SRBM_STATUS)); |
- | 1123 | dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", |
|
- | 1124 | RREG32(CP_STALLED_STAT1)); |
|
- | 1125 | dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", |
|
- | 1126 | RREG32(CP_STALLED_STAT2)); |
|
- | 1127 | dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", |
|
- | 1128 | RREG32(CP_BUSY_STAT)); |
|
- | 1129 | dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", |
|
- | 1130 | RREG32(CP_STAT)); |
|
- | 1131 | dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", |
|
- | 1132 | RREG32(0x14F8)); |
|
- | 1133 | dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", |
|
- | 1134 | RREG32(0x14D8)); |
|
- | 1135 | dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", |
|
- | 1136 | RREG32(0x14FC)); |
|
- | 1137 | dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", |
|
- | 1138 | RREG32(0x14DC)); |
|
- | 1139 | ||
1311 | evergreen_mc_stop(rdev, &save); |
1140 | evergreen_mc_stop(rdev, &save); |
1312 | if (evergreen_mc_wait_for_idle(rdev)) { |
1141 | if (evergreen_mc_wait_for_idle(rdev)) { |
1313 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
1142 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
1314 | } |
1143 | } |
1315 | /* Disable CP parsing/prefetching */ |
1144 | /* Disable CP parsing/prefetching */ |
Line 1336... | Line 1165... | ||
1336 | udelay(50); |
1165 | udelay(50); |
1337 | WREG32(GRBM_SOFT_RESET, 0); |
1166 | WREG32(GRBM_SOFT_RESET, 0); |
1338 | (void)RREG32(GRBM_SOFT_RESET); |
1167 | (void)RREG32(GRBM_SOFT_RESET); |
1339 | /* Wait a little for things to settle down */ |
1168 | /* Wait a little for things to settle down */ |
1340 | udelay(50); |
1169 | udelay(50); |
- | 1170 | ||
1341 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
1171 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
1342 | RREG32(GRBM_STATUS)); |
1172 | RREG32(GRBM_STATUS)); |
1343 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
1173 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
1344 | RREG32(GRBM_STATUS_SE0)); |
1174 | RREG32(GRBM_STATUS_SE0)); |
1345 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
1175 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
1346 | RREG32(GRBM_STATUS_SE1)); |
1176 | RREG32(GRBM_STATUS_SE1)); |
1347 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
1177 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
1348 | RREG32(SRBM_STATUS)); |
1178 | RREG32(SRBM_STATUS)); |
- | 1179 | dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", |
|
- | 1180 | RREG32(CP_STALLED_STAT1)); |
|
- | 1181 | dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", |
|
- | 1182 | RREG32(CP_STALLED_STAT2)); |
|
- | 1183 | dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", |
|
- | 1184 | RREG32(CP_BUSY_STAT)); |
|
- | 1185 | dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", |
|
- | 1186 | RREG32(CP_STAT)); |
|
1349 | evergreen_mc_resume(rdev, &save); |
1187 | evergreen_mc_resume(rdev, &save); |
1350 | return 0; |
1188 | return 0; |
1351 | } |
1189 | } |
Line 1352... | Line 1190... | ||
1352 | 1190 | ||
Line 1355... | Line 1193... | ||
1355 | return cayman_gpu_soft_reset(rdev); |
1193 | return cayman_gpu_soft_reset(rdev); |
1356 | } |
1194 | } |
Line 1357... | Line 1195... | ||
1357 | 1195 | ||
1358 | static int cayman_startup(struct radeon_device *rdev) |
1196 | static int cayman_startup(struct radeon_device *rdev) |
- | 1197 | { |
|
1359 | { |
1198 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Line -... | Line 1199... | ||
- | 1199 | int r; |
|
- | 1200 | ||
- | 1201 | /* enable pcie gen2 link */ |
|
- | 1202 | evergreen_pcie_gen2_enable(rdev); |
|
- | 1203 | ||
- | 1204 | if (rdev->flags & RADEON_IS_IGP) { |
|
- | 1205 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
|
- | 1206 | r = ni_init_microcode(rdev); |
|
- | 1207 | if (r) { |
|
- | 1208 | DRM_ERROR("Failed to load firmware!\n"); |
|
- | 1209 | return r; |
|
- | 1210 | } |
|
1360 | int r; |
1211 | } |
1361 | 1212 | } else { |
|
1362 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { |
1213 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { |
1363 | r = ni_init_microcode(rdev); |
1214 | r = ni_init_microcode(rdev); |
1364 | if (r) { |
1215 | if (r) { |
1365 | DRM_ERROR("Failed to load firmware!\n"); |
1216 | DRM_ERROR("Failed to load firmware!\n"); |
1366 | return r; |
1217 | return r; |
- | 1218 | } |
|
1367 | } |
1219 | } |
1368 | } |
1220 | |
1369 | r = ni_mc_load_microcode(rdev); |
1221 | r = ni_mc_load_microcode(rdev); |
1370 | if (r) { |
1222 | if (r) { |
1371 | DRM_ERROR("Failed to load MC firmware!\n"); |
1223 | DRM_ERROR("Failed to load MC firmware!\n"); |
- | 1224 | return r; |
|
- | 1225 | } |
|
- | 1226 | } |
|
- | 1227 | ||
- | 1228 | r = r600_vram_scratch_init(rdev); |
|
Line 1372... | Line 1229... | ||
1372 | return r; |
1229 | if (r) |
1373 | } |
1230 | return r; |
1374 | 1231 | ||
1375 | evergreen_mc_program(rdev); |
1232 | evergreen_mc_program(rdev); |
1376 | r = cayman_pcie_gart_enable(rdev); |
1233 | r = cayman_pcie_gart_enable(rdev); |
Line 1377... | Line 1234... | ||
1377 | if (r) |
1234 | if (r) |
1378 | return r; |
1235 | return r; |
1379 | cayman_gpu_init(rdev); |
1236 | cayman_gpu_init(rdev); |
1380 | 1237 | ||
1381 | r = evergreen_blit_init(rdev); |
1238 | r = evergreen_blit_init(rdev); |
1382 | if (r) { |
1239 | if (r) { |
Line -... | Line 1240... | ||
- | 1240 | // r600_blit_fini(rdev); |
|
- | 1241 | rdev->asic->copy.copy = NULL; |
|
- | 1242 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
|
- | 1243 | } |
|
- | 1244 | ||
- | 1245 | /* allocate rlc buffers */ |
|
- | 1246 | if (rdev->flags & RADEON_IS_IGP) { |
|
- | 1247 | r = si_rlc_init(rdev); |
|
- | 1248 | if (r) { |
|
1383 | // evergreen_blit_fini(rdev); |
1249 | DRM_ERROR("Failed to init rlc BOs!\n"); |
1384 | rdev->asic->copy = NULL; |
1250 | return r; |
1385 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
1251 | } |
1386 | } |
1252 | } |
Line 1397... | Line 1263... | ||
1397 | // radeon_irq_kms_fini(rdev); |
1263 | // radeon_irq_kms_fini(rdev); |
1398 | return r; |
1264 | return r; |
1399 | } |
1265 | } |
1400 | evergreen_irq_set(rdev); |
1266 | evergreen_irq_set(rdev); |
Line 1401... | Line 1267... | ||
1401 | 1267 | ||
- | 1268 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
|
- | 1269 | CP_RB0_RPTR, CP_RB0_WPTR, |
|
1402 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
1270 | 0, 0xfffff, RADEON_CP_PACKET2); |
1403 | if (r) |
1271 | if (r) |
1404 | return r; |
1272 | return r; |
1405 | r = cayman_cp_load_microcode(rdev); |
1273 | r = cayman_cp_load_microcode(rdev); |
1406 | if (r) |
1274 | if (r) |
Line 1422... | Line 1290... | ||
1422 | * should also allow to remove a bunch of callback function |
1290 | * should also allow to remove a bunch of callback function |
1423 | * like vram_info. |
1291 | * like vram_info. |
1424 | */ |
1292 | */ |
1425 | int cayman_init(struct radeon_device *rdev) |
1293 | int cayman_init(struct radeon_device *rdev) |
1426 | { |
1294 | { |
- | 1295 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
|
1427 | int r; |
1296 | int r; |
Line 1428... | Line -... | ||
1428 | - | ||
1429 | /* This don't do much */ |
- | |
1430 | r = radeon_gem_init(rdev); |
- | |
1431 | if (r) |
- | |
1432 | return r; |
1297 | |
1433 | /* Read BIOS */ |
1298 | /* Read BIOS */ |
1434 | if (!radeon_get_bios(rdev)) { |
1299 | if (!radeon_get_bios(rdev)) { |
1435 | if (ASIC_IS_AVIVO(rdev)) |
1300 | if (ASIC_IS_AVIVO(rdev)) |
1436 | return -EINVAL; |
1301 | return -EINVAL; |
Line 1474... | Line 1339... | ||
1474 | 1339 | ||
1475 | r = radeon_irq_kms_init(rdev); |
1340 | r = radeon_irq_kms_init(rdev); |
1476 | if (r) |
1341 | if (r) |
Line 1477... | Line 1342... | ||
1477 | return r; |
1342 | return r; |
1478 | 1343 | ||
Line 1479... | Line 1344... | ||
1479 | rdev->cp.ring_obj = NULL; |
1344 | ring->ring_obj = NULL; |
1480 | r600_ring_init(rdev, 1024 * 1024); |
1345 | r600_ring_init(rdev, ring, 1024 * 1024); |
Line 1481... | Line 1346... | ||
1481 | 1346 | ||
Line 1490... | Line 1355... | ||
1490 | r = cayman_startup(rdev); |
1355 | r = cayman_startup(rdev); |
1491 | if (r) { |
1356 | if (r) { |
1492 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
1357 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
1493 | rdev->accel_working = false; |
1358 | rdev->accel_working = false; |
1494 | } |
1359 | } |
1495 | if (rdev->accel_working) { |
- | |
1496 | r = radeon_ib_pool_init(rdev); |
- | |
1497 | if (r) { |
- | |
1498 | DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); |
- | |
1499 | rdev->accel_working = false; |
- | |
1500 | } |
- | |
1501 | r = r600_ib_test(rdev); |
- | |
1502 | if (r) { |
- | |
1503 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
- | |
1504 | rdev->accel_working = false; |
- | |
1505 | } |
- | |
1506 | } |
- | |
Line 1507... | Line 1360... | ||
1507 | 1360 | ||
1508 | /* Don't start up if the MC ucode is missing. |
1361 | /* Don't start up if the MC ucode is missing. |
1509 | * The default clocks and voltages before the MC ucode |
1362 | * The default clocks and voltages before the MC ucode |
- | 1363 | * is loaded are not suffient for advanced operations. |
|
- | 1364 | * |
|
- | 1365 | * We can skip this check for TN, because there is no MC |
|
1510 | * is loaded are not suffient for advanced operations. |
1366 | * ucode. |
1511 | */ |
1367 | */ |
1512 | if (!rdev->mc_fw) { |
1368 | if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { |
1513 | DRM_ERROR("radeon: MC ucode required for NI+.\n"); |
1369 | DRM_ERROR("radeon: MC ucode required for NI+.\n"); |
1514 | return -EINVAL; |
1370 | return -EINVAL; |
Line 1515... | Line 1371... | ||
1515 | } |
1371 | } |
1516 | 1372 | ||
Line -... | Line 1373... | ||
- | 1373 | return 0; |
|
- | 1374 | } |
|
- | 1375 | ||
- | 1376 | /* |
|
- | 1377 | * vm |
|
- | 1378 | */ |
|
- | 1379 | int cayman_vm_init(struct radeon_device *rdev) |
|
- | 1380 | { |
|
- | 1381 | /* number of VMs */ |
|
- | 1382 | rdev->vm_manager.nvm = 8; |
|
- | 1383 | /* base offset of vram pages */ |
|
- | 1384 | if (rdev->flags & RADEON_IS_IGP) { |
|
- | 1385 | u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET); |
|
- | 1386 | tmp <<= 22; |
|
- | 1387 | rdev->vm_manager.vram_base_offset = tmp; |
|
- | 1388 | } else |
|
- | 1389 | rdev->vm_manager.vram_base_offset = 0; |
|
- | 1390 | return 0; |
|
- | 1391 | } |
|
- | 1392 | ||
- | 1393 | void cayman_vm_fini(struct radeon_device *rdev) |
|
- | 1394 | { |
|
- | 1395 | } |
|
- | 1396 | ||
- | 1397 | #define R600_ENTRY_VALID (1 << 0) |
|
- | 1398 | #define R600_PTE_SYSTEM (1 << 1) |
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- | 1399 | #define R600_PTE_SNOOPED (1 << 2) |
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- | 1400 | #define R600_PTE_READABLE (1 << 5) |
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- | 1401 | #define R600_PTE_WRITEABLE (1 << 6) |
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- | 1402 | ||
- | 1403 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags) |
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- | 1404 | { |
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- | 1405 | uint32_t r600_flags = 0; |
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- | 1406 | r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0; |
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- | 1407 | r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0; |
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- | 1408 | r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0; |
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- | 1409 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
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- | 1410 | r600_flags |= R600_PTE_SYSTEM; |
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- | 1411 | r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0; |
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- | 1412 | } |
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- | 1413 | return r600_flags; |
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- | 1414 | } |
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- | 1415 | ||
- | 1416 | /** |
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- | 1417 | * cayman_vm_set_page - update the page tables using the CP |
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- | 1418 | * |
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- | 1419 | * @rdev: radeon_device pointer |
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- | 1420 | * @pe: addr of the page entry |
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- | 1421 | * @addr: dst addr to write into pe |
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- | 1422 | * @count: number of page entries to update |
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- | 1423 | * @incr: increase next addr by incr bytes |
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- | 1424 | * @flags: access flags |
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- | 1425 | * |
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- | 1426 | * Update the page tables using the CP (cayman-si). |
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- | 1427 | */ |
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- | 1428 | void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, |
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- | 1429 | uint64_t addr, unsigned count, |
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- | 1430 | uint32_t incr, uint32_t flags) |
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- | 1431 | { |
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- | 1432 | struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index]; |
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- | 1433 | uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); |
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- | 1434 | ||
- | 1435 | while (count) { |
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- | 1436 | unsigned ndw = 1 + count * 2; |
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- | 1437 | if (ndw > 0x3FFF) |
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- | 1438 | ndw = 0x3FFF; |
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- | 1439 | ||
- | 1440 | radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw)); |
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- | 1441 | radeon_ring_write(ring, pe); |
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- | 1442 | radeon_ring_write(ring, upper_32_bits(pe) & 0xff); |
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- | 1443 | for (; ndw > 1; ndw -= 2, --count, pe += 8) { |
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- | 1444 | uint64_t value = 0; |
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- | 1445 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
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- | 1446 | value = radeon_vm_map_gart(rdev, addr); |
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- | 1447 | value &= 0xFFFFFFFFFFFFF000ULL; |
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- | 1448 | addr += incr; |
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- | 1449 | ||
- | 1450 | } else if (flags & RADEON_VM_PAGE_VALID) { |
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- | 1451 | value = addr; |
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- | 1452 | addr += incr; |
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- | 1453 | } |
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- | 1454 | ||
- | 1455 | value |= r600_flags; |
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- | 1456 | radeon_ring_write(ring, value); |
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- | 1457 | radeon_ring_write(ring, upper_32_bits(value)); |
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- | 1458 | } |
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- | 1459 | } |
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- | 1460 | } |
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- | 1461 | ||
- | 1462 | /** |
|
- | 1463 | * cayman_vm_flush - vm flush using the CP |
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- | 1464 | * |
|
- | 1465 | * @rdev: radeon_device pointer |
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- | 1466 | * |
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- | 1467 | * Update the page table base and flush the VM TLB |
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- | 1468 | * using the CP (cayman-si). |
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- | 1469 | */ |
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- | 1470 | void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) |
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- | 1471 | { |
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- | 1472 | struct radeon_ring *ring = &rdev->ring[ridx]; |
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- | 1473 | ||
- | 1474 | if (vm == NULL) |
|
- | 1475 | return; |
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- | 1476 | ||
- | 1477 | radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0)); |
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- | 1478 | radeon_ring_write(ring, vm->pd_gpu_addr >> 12); |
|
- | 1479 | ||
- | 1480 | /* flush hdp cache */ |
|
- | 1481 | radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); |
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- | 1482 | radeon_ring_write(ring, 0x1); |
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- | 1483 | ||
- | 1484 | /* bits 0-7 are the VM contexts0-7 */ |
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- | 1485 | radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); |
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- | 1486 | radeon_ring_write(ring, 1 << vm->id); |
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- | 1487 | ||
- | 1488 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |