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Rev 808 Rev 812
1
SymTabRec RHDChipsets[] = {
1
SymTabRec RHDChipsets[] = {
2
    /* R500 */
2
    /* R500 */
3
    { RHD_RV505, "RV505" },
3
    { RHD_RV505, "RV505" },
4
    { RHD_RV515, "RV515" },
4
    { RHD_RV515, "RV515" },
5
    { RHD_RV516, "RV516" },
5
    { RHD_RV516, "RV516" },
6
    { RHD_R520,  "R520" },
6
    { RHD_R520,  "R520" },
7
    { RHD_RV530, "RV530" },
7
    { RHD_RV530, "RV530" },
8
    { RHD_RV535, "RV535" },
8
    { RHD_RV535, "RV535" },
9
    { RHD_RV550, "RV550" },
9
    { RHD_RV550, "RV550" },
10
    { RHD_RV560, "RV560" },
10
    { RHD_RV560, "RV560" },
11
    { RHD_RV570, "RV570" },
11
    { RHD_RV570, "RV570" },
12
    { RHD_R580,  "R580" },
12
    { RHD_R580,  "R580" },
13
    /* R500 Mobility */
13
    /* R500 Mobility */
14
    { RHD_M52,   "M52" },
14
    { RHD_M52,   "M52" },
15
    { RHD_M54,   "M54" },
15
    { RHD_M54,   "M54" },
16
    { RHD_M56,   "M56" },
16
    { RHD_M56,   "M56" },
17
    { RHD_M58,   "M58" },
17
    { RHD_M58,   "M58" },
18
    { RHD_M62,   "M62" },
18
    { RHD_M62,   "M62" },
19
    { RHD_M64,   "M64" },
19
    { RHD_M64,   "M64" },
20
    { RHD_M66,   "M66" },
20
    { RHD_M66,   "M66" },
21
    { RHD_M68,   "M68" },
21
    { RHD_M68,   "M68" },
22
    { RHD_M71,   "M71" },
22
    { RHD_M71,   "M71" },
23
    /* R500 integrated */
23
    /* R500 integrated */
24
    { RHD_RS600, "RS600" },
24
    { RHD_RS600, "RS600" },
25
    { RHD_RS690, "RS690" },
25
    { RHD_RS690, "RS690" },
26
    { RHD_RS740, "RS740" },
26
    { RHD_RS740, "RS740" },
27
    /* R600 */
27
    /* R600 */
28
    { RHD_R600,  "R600" },
28
    { RHD_R600,  "R600" },
29
    { RHD_RV610, "RV610" },
29
    { RHD_RV610, "RV610" },
30
    { RHD_RV630, "RV630" },
30
    { RHD_RV630, "RV630" },
31
    /* R600 Mobility */
31
    /* R600 Mobility */
32
    { RHD_M72,   "M72" },
32
    { RHD_M72,   "M72" },
33
    { RHD_M74,   "M74" },
33
    { RHD_M74,   "M74" },
34
    { RHD_M76,   "M76" },
34
    { RHD_M76,   "M76" },
35
    /* RV670 came into existence after RV6x0 and M7x */
35
    /* RV670 came into existence after RV6x0 and M7x */
36
    { RHD_RV670, "RV670" },
36
    { RHD_RV670, "RV670" },
37
    { RHD_R680,  "R680"  },
37
    { RHD_R680,  "R680"  },
38
    { RHD_RV620, "RV620" },
38
    { RHD_RV620, "RV620" },
39
    { RHD_RV635, "RV635" },
39
    { RHD_RV635, "RV635" },
40
    { -1,      NULL }
40
    { -1,      NULL }
41
};
41
};
42
 
42
 
-
 
43
 
-
 
44
 
-
 
45
static struct rhdChipsetMapStruct {
-
 
46
    enum RHD_FAMILIES family;
-
 
47
    Bool IGP;
-
 
48
} rhdChipsetMap[] = {
-
 
49
    { RHD_FAMILY_UNKNOWN, 0 }, /* RHD_UNKNOWN */
-
 
50
 
-
 
51
    { RHD_FAMILY_R300,  0 },     /* RHD_R300 */
-
 
52
    { RHD_FAMILY_R350,  0 },     /* RHD_R350 */
-
 
53
    { RHD_FAMILY_RV350, 0 },     /* RHD_RV350 */
-
 
54
    { RHD_FAMILY_RV380, 0 },     /* RHD_RV370 */
-
 
55
    { RHD_FAMILY_RV380, 0 },     /* RHD_RV380 */
-
 
56
 
-
 
57
 
-
 
58
    { RHD_FAMILY_RV515, 0 },     /* RHD_RV505 */
-
 
59
    { RHD_FAMILY_RV515, 0 },     /* RHD_RV515 */
-
 
60
    { RHD_FAMILY_RV515, 0 },     /* RHD_RV516 */
-
 
61
    { RHD_FAMILY_R520,  0 },     /* RHD_R520 */
-
 
62
    { RHD_FAMILY_RV530, 0 },     /* RHD_RV530 */
-
 
63
    { RHD_FAMILY_RV530, 0 },     /* RHD_RV535 */
-
 
64
    { RHD_FAMILY_RV515, 0 },     /* RHD_RV550 */
-
 
65
    { RHD_FAMILY_RV560, 0 },     /* RHD_RV560 */
-
 
66
    { RHD_FAMILY_RV570, 0 },     /* RHD_RV570 */
-
 
67
    { RHD_FAMILY_R580,  0 },     /* RHD_R580 */
-
 
68
    { RHD_FAMILY_RV515, 0 },     /* RHD_M52 */
-
 
69
    { RHD_FAMILY_RV515, 0 },     /* RHD_M54 */
-
 
70
    { RHD_FAMILY_RV530, 0 },     /* RHD_M56 */
-
 
71
    { RHD_FAMILY_R520,  0 },     /* RHD_M58 */
-
 
72
    { RHD_FAMILY_RV515, 0 },     /* RHD_M62 */
-
 
73
    { RHD_FAMILY_RV515, 0 },     /* RHD_M64 */
-
 
74
    { RHD_FAMILY_RV530, 0 },     /* RHD_M66 */
-
 
75
    { RHD_FAMILY_R580,  0 },     /* RHD_M68 */
-
 
76
    { RHD_FAMILY_RV515, 0 },     /* RHD_M71 */
-
 
77
    { RHD_FAMILY_RS690, 1 },     /* RHD_RS600 */
-
 
78
    { RHD_FAMILY_RS690, 1 },     /* RHD_RS690 */
-
 
79
    { RHD_FAMILY_RS690, 1 },     /* RHD_RS740 */
-
 
80
    { RHD_FAMILY_R600,  0 },     /* RHD_R600 */
-
 
81
    { RHD_FAMILY_RV610, 0 },     /* RHD_RV610 */
-
 
82
    { RHD_FAMILY_RV630, 0 },     /* RHD_RV630 */
-
 
83
    { RHD_FAMILY_RV610, 0 },     /* RHD_M72 */
-
 
84
    { RHD_FAMILY_RV610, 0 },     /* RHD_M74 */
-
 
85
    { RHD_FAMILY_RV630, 0 },     /* RHD_M76 */
-
 
86
    { RHD_FAMILY_RV670, 0 },     /* RHD_RV670 */
-
 
87
    { RHD_FAMILY_RV670, 0 },     /* RHD_R680 */
-
 
88
    { RHD_FAMILY_RV620, 0 },     /* RHD_RV620 */
-
 
89
    { RHD_FAMILY_RV620, 0 },     /* RHD_M82 */
-
 
90
    { RHD_FAMILY_RV635, 0 },     /* RHD_RV635 */
-
 
91
    { RHD_FAMILY_UNKNOWN, 0 },   /* RHD_M86 */
-
 
92
    { RHD_FAMILY_RS780, 1 }      /* RHD_RS780 */
-
 
93
    /* RHD_CHIP_END */
-
 
94
};
-
 
95
 
-
 
96
 
43
# define RHD_DEVICE_MATCH(d, i) { (d),(i) }
97
# define RHD_DEVICE_MATCH(d, i) { (d),(i) }
44
# define PCI_ID_LIST PciChipset_t RHDPCIchipsets[]
98
# define PCI_ID_LIST PciChipset_t RHDPCIchipsets[]
45
# define LIST_END { 0,  0}
99
# define LIST_END { 0,  0}
46
 
100
 
47
const PCI_ID_LIST = {
101
const PCI_ID_LIST = {
48
    RHD_DEVICE_MATCH(  0x7100, RHD_R520  ), /* Radeon X1800 */
102
 
-
 
103
    RHD_DEVICE_MATCH(  0x4144, RHD_R300  ), /* ATI Radeon 9500    */
-
 
104
    RHD_DEVICE_MATCH(  0x4145, RHD_R300  ), /* ATI Radeon 9500    */
-
 
105
    RHD_DEVICE_MATCH(  0x4146, RHD_R300  ), /* ATI Radeon 9600TX  */
-
 
106
    RHD_DEVICE_MATCH(  0x4147, RHD_R300  ), /* ATI FireGL Z1      */
-
 
107
    RHD_DEVICE_MATCH(  0x4148, RHD_R350  ), /* ATI Radeon 9800SE  */
-
 
108
    RHD_DEVICE_MATCH(  0x4149, RHD_R350  ), /* ATI Radeon 9800    */
-
 
109
    RHD_DEVICE_MATCH(  0x414A, RHD_R350  ), /* ATI Radeon 9800    */
-
 
110
    RHD_DEVICE_MATCH(  0x414B, RHD_R350  ), /* ATI FireGL X2      */
-
 
111
 
-
 
112
    RHD_DEVICE_MATCH(  0x4150, RHD_RV350 ), /* ATI Radeon 9600    */
-
 
113
    RHD_DEVICE_MATCH(  0x4151, RHD_RV350 ), /* ATI Radeon 9600SE  */
-
 
114
    RHD_DEVICE_MATCH(  0x4152, RHD_RV350 ), /* ATI Radeon 9600XT  */
-
 
115
    RHD_DEVICE_MATCH(  0x4153, RHD_RV350 ), /* ATI Radeon 9600    */
-
 
116
    RHD_DEVICE_MATCH(  0x4154, RHD_RV350 ), /* ATI FireGL T2      */
-
 
117
    RHD_DEVICE_MATCH(  0x4155, RHD_RV350 ), /* ATI Radeon 9650    */
-
 
118
    RHD_DEVICE_MATCH(  0x4156, RHD_RV350 ), /* ATI FireGL RV360   */
-
 
119
 
-
 
120
    RHD_DEVICE_MATCH(  0x4E44, RHD_R300  ),
-
 
121
    RHD_DEVICE_MATCH(  0x4E45, RHD_R300  ),
-
 
122
    RHD_DEVICE_MATCH(  0x4E46, RHD_R300  ),
-
 
123
    RHD_DEVICE_MATCH(  0x4E47, RHD_R300  ),
-
 
124
    RHD_DEVICE_MATCH(  0x4E48, RHD_R350  ),
-
 
125
    RHD_DEVICE_MATCH(  0x4E49, RHD_R350  ),
-
 
126
    RHD_DEVICE_MATCH(  0x4E4A, RHD_R350  ),
-
 
127
    RHD_DEVICE_MATCH(  0x4E4B, RHD_R350  ),
-
 
128
    RHD_DEVICE_MATCH(  0x4E50, RHD_RV350 ),
-
 
129
    RHD_DEVICE_MATCH(  0x4E51, RHD_RV350 ),
-
 
130
    RHD_DEVICE_MATCH(  0x4E52, RHD_RV350 ),
-
 
131
    RHD_DEVICE_MATCH(  0x4E53, RHD_RV350 ),
-
 
132
    RHD_DEVICE_MATCH(  0x4E54, RHD_RV350 ),
-
 
133
    RHD_DEVICE_MATCH(  0x4E56, RHD_RV350 ),
-
 
134
 
-
 
135
 
-
 
136
    RHD_DEVICE_MATCH(  0x5B60, RHD_RV380 ),
-
 
137
    RHD_DEVICE_MATCH(  0x5B62, RHD_RV380 ),
-
 
138
    RHD_DEVICE_MATCH(  0x5B63, RHD_RV380 ),
-
 
139
    RHD_DEVICE_MATCH(  0x5B64, RHD_RV380 ),
-
 
140
    RHD_DEVICE_MATCH(  0x5B65, RHD_RV380 ),
-
 
141
 
-
 
142
    RHD_DEVICE_MATCH(  0x7100, RHD_R520  ), /* Radeon X1800 */
49
    RHD_DEVICE_MATCH(  0x7101, RHD_M58   ), /* Mobility Radeon X1800 XT */
143
    RHD_DEVICE_MATCH(  0x7101, RHD_M58   ), /* Mobility Radeon X1800 XT */
50
    RHD_DEVICE_MATCH(  0x7102, RHD_M58   ), /* Mobility Radeon X1800 */
144
    RHD_DEVICE_MATCH(  0x7102, RHD_M58   ), /* Mobility Radeon X1800 */
51
    RHD_DEVICE_MATCH(  0x7103, RHD_M58   ), /* Mobility FireGL V7200 */
145
    RHD_DEVICE_MATCH(  0x7103, RHD_M58   ), /* Mobility FireGL V7200 */
52
    RHD_DEVICE_MATCH(  0x7104, RHD_R520  ), /* FireGL V7200 */
146
    RHD_DEVICE_MATCH(  0x7104, RHD_R520  ), /* FireGL V7200 */
53
    RHD_DEVICE_MATCH(  0x7105, RHD_R520  ), /* FireGL V5300 */
147
    RHD_DEVICE_MATCH(  0x7105, RHD_R520  ), /* FireGL V5300 */
54
    RHD_DEVICE_MATCH(  0x7106, RHD_M58   ), /* Mobility FireGL V7100 */
148
    RHD_DEVICE_MATCH(  0x7106, RHD_M58   ), /* Mobility FireGL V7100 */
55
    RHD_DEVICE_MATCH(  0x7108, RHD_R520  ), /* Radeon X1800 */
149
    RHD_DEVICE_MATCH(  0x7108, RHD_R520  ), /* Radeon X1800 */
56
    RHD_DEVICE_MATCH(  0x7109, RHD_R520  ), /* Radeon X1800 */
150
    RHD_DEVICE_MATCH(  0x7109, RHD_R520  ), /* Radeon X1800 */
57
    RHD_DEVICE_MATCH(  0x710A, RHD_R520  ), /* Radeon X1800 */
151
    RHD_DEVICE_MATCH(  0x710A, RHD_R520  ), /* Radeon X1800 */
58
    RHD_DEVICE_MATCH(  0x710B, RHD_R520  ), /* Radeon X1800 */
152
    RHD_DEVICE_MATCH(  0x710B, RHD_R520  ), /* Radeon X1800 */
59
    RHD_DEVICE_MATCH(  0x710C, RHD_R520  ), /* Radeon X1800 */
153
    RHD_DEVICE_MATCH(  0x710C, RHD_R520  ), /* Radeon X1800 */
60
    RHD_DEVICE_MATCH(  0x710E, RHD_R520  ), /* FireGL V7300 */
154
    RHD_DEVICE_MATCH(  0x710E, RHD_R520  ), /* FireGL V7300 */
61
    RHD_DEVICE_MATCH(  0x710F, RHD_R520  ), /* FireGL V7350 */
155
    RHD_DEVICE_MATCH(  0x710F, RHD_R520  ), /* FireGL V7350 */
62
    RHD_DEVICE_MATCH(  0x7140, RHD_RV515 ), /* Radeon X1600/X1550 */
156
    RHD_DEVICE_MATCH(  0x7140, RHD_RV515 ), /* Radeon X1600/X1550 */
63
    RHD_DEVICE_MATCH(  0x7141, RHD_RV505 ), /* RV505 */
157
    RHD_DEVICE_MATCH(  0x7141, RHD_RV505 ), /* RV505 */
64
    RHD_DEVICE_MATCH(  0x7142, RHD_RV515 ), /* Radeon X1300/X1550 */
158
    RHD_DEVICE_MATCH(  0x7142, RHD_RV515 ), /* Radeon X1300/X1550 */
65
    RHD_DEVICE_MATCH(  0x7143, RHD_RV505 ), /* Radeon X1550 */
159
    RHD_DEVICE_MATCH(  0x7143, RHD_RV505 ), /* Radeon X1550 */
66
    RHD_DEVICE_MATCH(  0x7144, RHD_M54   ), /* M54-GL */
160
    RHD_DEVICE_MATCH(  0x7144, RHD_M54   ), /* M54-GL */
67
    RHD_DEVICE_MATCH(  0x7145, RHD_M54   ), /* Mobility Radeon X1400 */
161
    RHD_DEVICE_MATCH(  0x7145, RHD_M54   ), /* Mobility Radeon X1400 */
68
    RHD_DEVICE_MATCH(  0x7146, RHD_RV515 ), /* Radeon X1300/X1550 */
162
    RHD_DEVICE_MATCH(  0x7146, RHD_RV515 ), /* Radeon X1300/X1550 */
69
    RHD_DEVICE_MATCH(  0x7147, RHD_RV505 ), /* Radeon X1550 64-bit */
163
    RHD_DEVICE_MATCH(  0x7147, RHD_RV505 ), /* Radeon X1550 64-bit */
70
    RHD_DEVICE_MATCH(  0x7149, RHD_M52   ), /* Mobility Radeon X1300 */
164
    RHD_DEVICE_MATCH(  0x7149, RHD_M52   ), /* Mobility Radeon X1300 */
71
    RHD_DEVICE_MATCH(  0x714A, RHD_M52   ), /* Mobility Radeon X1300 */
165
    RHD_DEVICE_MATCH(  0x714A, RHD_M52   ), /* Mobility Radeon X1300 */
72
    RHD_DEVICE_MATCH(  0x714B, RHD_M52   ), /* Mobility Radeon X1300 */
166
    RHD_DEVICE_MATCH(  0x714B, RHD_M52   ), /* Mobility Radeon X1300 */
73
    RHD_DEVICE_MATCH(  0x714C, RHD_M52   ), /* Mobility Radeon X1300 */
167
    RHD_DEVICE_MATCH(  0x714C, RHD_M52   ), /* Mobility Radeon X1300 */
74
    RHD_DEVICE_MATCH(  0x714D, RHD_RV515 ), /* Radeon X1300 */
168
    RHD_DEVICE_MATCH(  0x714D, RHD_RV515 ), /* Radeon X1300 */
75
    RHD_DEVICE_MATCH(  0x714E, RHD_RV515 ), /* Radeon X1300 */
169
    RHD_DEVICE_MATCH(  0x714E, RHD_RV515 ), /* Radeon X1300 */
76
    RHD_DEVICE_MATCH(  0x714F, RHD_RV505 ), /* RV505 */
170
    RHD_DEVICE_MATCH(  0x714F, RHD_RV505 ), /* RV505 */
77
    RHD_DEVICE_MATCH(  0x7151, RHD_RV505 ), /* RV505 */
171
    RHD_DEVICE_MATCH(  0x7151, RHD_RV505 ), /* RV505 */
78
    RHD_DEVICE_MATCH(  0x7152, RHD_RV515 ), /* FireGL V3300 */
172
    RHD_DEVICE_MATCH(  0x7152, RHD_RV515 ), /* FireGL V3300 */
79
    RHD_DEVICE_MATCH(  0x7153, RHD_RV515 ), /* FireGL V3350 */
173
    RHD_DEVICE_MATCH(  0x7153, RHD_RV515 ), /* FireGL V3350 */
80
    RHD_DEVICE_MATCH(  0x715E, RHD_RV515 ), /* Radeon X1300 */
174
    RHD_DEVICE_MATCH(  0x715E, RHD_RV515 ), /* Radeon X1300 */
81
    RHD_DEVICE_MATCH(  0x715F, RHD_RV505 ), /* Radeon X1550 64-bit */
175
    RHD_DEVICE_MATCH(  0x715F, RHD_RV505 ), /* Radeon X1550 64-bit */
82
    RHD_DEVICE_MATCH(  0x7180, RHD_RV516 ), /* Radeon X1300/X1550 */
176
    RHD_DEVICE_MATCH(  0x7180, RHD_RV516 ), /* Radeon X1300/X1550 */
83
    RHD_DEVICE_MATCH(  0x7181, RHD_RV516 ), /* Radeon X1600 */
177
    RHD_DEVICE_MATCH(  0x7181, RHD_RV516 ), /* Radeon X1600 */
84
    RHD_DEVICE_MATCH(  0x7183, RHD_RV516 ), /* Radeon X1300/X1550 */
178
    RHD_DEVICE_MATCH(  0x7183, RHD_RV516 ), /* Radeon X1300/X1550 */
85
    RHD_DEVICE_MATCH(  0x7186, RHD_M64   ), /* Mobility Radeon X1450 */
179
    RHD_DEVICE_MATCH(  0x7186, RHD_M64   ), /* Mobility Radeon X1450 */
86
    RHD_DEVICE_MATCH(  0x7187, RHD_RV516 ), /* Radeon X1300/X1550 */
180
    RHD_DEVICE_MATCH(  0x7187, RHD_RV516 ), /* Radeon X1300/X1550 */
87
    RHD_DEVICE_MATCH(  0x7188, RHD_M64   ), /* Mobility Radeon X2300 */
181
    RHD_DEVICE_MATCH(  0x7188, RHD_M64   ), /* Mobility Radeon X2300 */
88
    RHD_DEVICE_MATCH(  0x718A, RHD_M64   ), /* Mobility Radeon X2300 */
182
    RHD_DEVICE_MATCH(  0x718A, RHD_M64   ), /* Mobility Radeon X2300 */
89
    RHD_DEVICE_MATCH(  0x718B, RHD_M62   ), /* Mobility Radeon X1350 */
183
    RHD_DEVICE_MATCH(  0x718B, RHD_M62   ), /* Mobility Radeon X1350 */
90
    RHD_DEVICE_MATCH(  0x718C, RHD_M62   ), /* Mobility Radeon X1350 */
184
    RHD_DEVICE_MATCH(  0x718C, RHD_M62   ), /* Mobility Radeon X1350 */
91
    RHD_DEVICE_MATCH(  0x718D, RHD_M64   ), /* Mobility Radeon X1450 */
185
    RHD_DEVICE_MATCH(  0x718D, RHD_M64   ), /* Mobility Radeon X1450 */
92
    RHD_DEVICE_MATCH(  0x718F, RHD_RV516 ), /* Radeon X1300 */
186
    RHD_DEVICE_MATCH(  0x718F, RHD_RV516 ), /* Radeon X1300 */
93
    RHD_DEVICE_MATCH(  0x7193, RHD_RV516 ), /* Radeon X1550 */
187
    RHD_DEVICE_MATCH(  0x7193, RHD_RV516 ), /* Radeon X1550 */
94
    RHD_DEVICE_MATCH(  0x7196, RHD_M62   ), /* Mobility Radeon X1350 */
188
    RHD_DEVICE_MATCH(  0x7196, RHD_M62   ), /* Mobility Radeon X1350 */
95
    RHD_DEVICE_MATCH(  0x719B, RHD_RV516 ), /* FireMV 2250 */
189
    RHD_DEVICE_MATCH(  0x719B, RHD_RV516 ), /* FireMV 2250 */
96
    RHD_DEVICE_MATCH(  0x719F, RHD_RV516 ), /* Radeon X1550 64-bit */
190
    RHD_DEVICE_MATCH(  0x719F, RHD_RV516 ), /* Radeon X1550 64-bit */
97
    RHD_DEVICE_MATCH(  0x71C0, RHD_RV530 ), /* Radeon X1600 */
191
    RHD_DEVICE_MATCH(  0x71C0, RHD_RV530 ), /* Radeon X1600 */
98
    RHD_DEVICE_MATCH(  0x71C1, RHD_RV535 ), /* Radeon X1650 */
192
    RHD_DEVICE_MATCH(  0x71C1, RHD_RV535 ), /* Radeon X1650 */
99
    RHD_DEVICE_MATCH(  0x71C2, RHD_RV530 ), /* Radeon X1600 */
193
    RHD_DEVICE_MATCH(  0x71C2, RHD_RV530 ), /* Radeon X1600 */
100
    RHD_DEVICE_MATCH(  0x71C3, RHD_RV535 ), /* Radeon X1600 */
194
    RHD_DEVICE_MATCH(  0x71C3, RHD_RV535 ), /* Radeon X1600 */
101
    RHD_DEVICE_MATCH(  0x71C4, RHD_M56   ), /* Mobility FireGL V5200 */
195
    RHD_DEVICE_MATCH(  0x71C4, RHD_M56   ), /* Mobility FireGL V5200 */
102
    RHD_DEVICE_MATCH(  0x71C5, RHD_M56   ), /* Mobility Radeon X1600 */
196
    RHD_DEVICE_MATCH(  0x71C5, RHD_M56   ), /* Mobility Radeon X1600 */
103
    RHD_DEVICE_MATCH(  0x71C6, RHD_RV530 ), /* Radeon X1650 */
197
    RHD_DEVICE_MATCH(  0x71C6, RHD_RV530 ), /* Radeon X1650 */
104
    RHD_DEVICE_MATCH(  0x71C7, RHD_RV535 ), /* Radeon X1650 */
198
    RHD_DEVICE_MATCH(  0x71C7, RHD_RV535 ), /* Radeon X1650 */
105
    RHD_DEVICE_MATCH(  0x71CD, RHD_RV530 ), /* Radeon X1600 */
199
    RHD_DEVICE_MATCH(  0x71CD, RHD_RV530 ), /* Radeon X1600 */
106
    RHD_DEVICE_MATCH(  0x71CE, RHD_RV530 ), /* Radeon X1300 XT/X1600 Pro */
200
    RHD_DEVICE_MATCH(  0x71CE, RHD_RV530 ), /* Radeon X1300 XT/X1600 Pro */
107
    RHD_DEVICE_MATCH(  0x71D2, RHD_RV530 ), /* FireGL V3400 */
201
    RHD_DEVICE_MATCH(  0x71D2, RHD_RV530 ), /* FireGL V3400 */
108
    RHD_DEVICE_MATCH(  0x71D4, RHD_M66   ), /* Mobility FireGL V5250 */
202
    RHD_DEVICE_MATCH(  0x71D4, RHD_M66   ), /* Mobility FireGL V5250 */
109
    RHD_DEVICE_MATCH(  0x71D5, RHD_M66   ), /* Mobility Radeon X1700 */
203
    RHD_DEVICE_MATCH(  0x71D5, RHD_M66   ), /* Mobility Radeon X1700 */
110
    RHD_DEVICE_MATCH(  0x71D6, RHD_M66   ), /* Mobility Radeon X1700 XT */
204
    RHD_DEVICE_MATCH(  0x71D6, RHD_M66   ), /* Mobility Radeon X1700 XT */
111
    RHD_DEVICE_MATCH(  0x71DA, RHD_RV530 ), /* FireGL V5200 */
205
    RHD_DEVICE_MATCH(  0x71DA, RHD_RV530 ), /* FireGL V5200 */
112
    RHD_DEVICE_MATCH(  0x71DE, RHD_M66   ), /* Mobility Radeon X1700 */
206
    RHD_DEVICE_MATCH(  0x71DE, RHD_M66   ), /* Mobility Radeon X1700 */
113
    RHD_DEVICE_MATCH(  0x7200, RHD_RV550 ), /*  Radeon X2300HD  */
207
    RHD_DEVICE_MATCH(  0x7200, RHD_RV550 ), /*  Radeon X2300HD  */
114
    RHD_DEVICE_MATCH(  0x7210, RHD_M71   ), /* Mobility Radeon HD 2300 */
208
    RHD_DEVICE_MATCH(  0x7210, RHD_M71   ), /* Mobility Radeon HD 2300 */
115
    RHD_DEVICE_MATCH(  0x7211, RHD_M71   ), /* Mobility Radeon HD 2300 */
209
    RHD_DEVICE_MATCH(  0x7211, RHD_M71   ), /* Mobility Radeon HD 2300 */
116
    RHD_DEVICE_MATCH(  0x7240, RHD_R580  ), /* Radeon X1950 */
210
    RHD_DEVICE_MATCH(  0x7240, RHD_R580  ), /* Radeon X1950 */
117
    RHD_DEVICE_MATCH(  0x7243, RHD_R580  ), /* Radeon X1900 */
211
    RHD_DEVICE_MATCH(  0x7243, RHD_R580  ), /* Radeon X1900 */
118
    RHD_DEVICE_MATCH(  0x7244, RHD_R580  ), /* Radeon X1950 */
212
    RHD_DEVICE_MATCH(  0x7244, RHD_R580  ), /* Radeon X1950 */
119
    RHD_DEVICE_MATCH(  0x7245, RHD_R580  ), /* Radeon X1900 */
213
    RHD_DEVICE_MATCH(  0x7245, RHD_R580  ), /* Radeon X1900 */
120
    RHD_DEVICE_MATCH(  0x7246, RHD_R580  ), /* Radeon X1900 */
214
    RHD_DEVICE_MATCH(  0x7246, RHD_R580  ), /* Radeon X1900 */
121
    RHD_DEVICE_MATCH(  0x7247, RHD_R580  ), /* Radeon X1900 */
215
    RHD_DEVICE_MATCH(  0x7247, RHD_R580  ), /* Radeon X1900 */
122
    RHD_DEVICE_MATCH(  0x7248, RHD_R580  ), /* Radeon X1900 */
216
    RHD_DEVICE_MATCH(  0x7248, RHD_R580  ), /* Radeon X1900 */
123
    RHD_DEVICE_MATCH(  0x7249, RHD_R580  ), /* Radeon X1900 */
217
    RHD_DEVICE_MATCH(  0x7249, RHD_R580  ), /* Radeon X1900 */
124
    RHD_DEVICE_MATCH(  0x724A, RHD_R580  ), /* Radeon X1900 */
218
    RHD_DEVICE_MATCH(  0x724A, RHD_R580  ), /* Radeon X1900 */
125
    RHD_DEVICE_MATCH(  0x724B, RHD_R580  ), /* Radeon X1900 */
219
    RHD_DEVICE_MATCH(  0x724B, RHD_R580  ), /* Radeon X1900 */
126
    RHD_DEVICE_MATCH(  0x724C, RHD_R580  ), /* Radeon X1900 */
220
    RHD_DEVICE_MATCH(  0x724C, RHD_R580  ), /* Radeon X1900 */
127
    RHD_DEVICE_MATCH(  0x724D, RHD_R580  ), /* Radeon X1900 */
221
    RHD_DEVICE_MATCH(  0x724D, RHD_R580  ), /* Radeon X1900 */
128
    RHD_DEVICE_MATCH(  0x724E, RHD_R580  ), /* AMD Stream Processor */
222
    RHD_DEVICE_MATCH(  0x724E, RHD_R580  ), /* AMD Stream Processor */
129
    RHD_DEVICE_MATCH(  0x724F, RHD_R580  ), /* Radeon X1900 */
223
    RHD_DEVICE_MATCH(  0x724F, RHD_R580  ), /* Radeon X1900 */
130
    RHD_DEVICE_MATCH(  0x7280, RHD_RV570 ), /* Radeon X1950 */
224
    RHD_DEVICE_MATCH(  0x7280, RHD_RV570 ), /* Radeon X1950 */
131
    RHD_DEVICE_MATCH(  0x7281, RHD_RV560 ), /* RV560 */
225
    RHD_DEVICE_MATCH(  0x7281, RHD_RV560 ), /* RV560 */
132
    RHD_DEVICE_MATCH(  0x7283, RHD_RV560 ), /* RV560 */
226
    RHD_DEVICE_MATCH(  0x7283, RHD_RV560 ), /* RV560 */
133
    RHD_DEVICE_MATCH(  0x7284, RHD_M68   ), /* Mobility Radeon X1900 */
227
    RHD_DEVICE_MATCH(  0x7284, RHD_M68   ), /* Mobility Radeon X1900 */
134
    RHD_DEVICE_MATCH(  0x7287, RHD_RV560 ), /* RV560 */
228
    RHD_DEVICE_MATCH(  0x7287, RHD_RV560 ), /* RV560 */
135
    RHD_DEVICE_MATCH(  0x7288, RHD_RV570 ), /* Radeon X1950 GT */
229
    RHD_DEVICE_MATCH(  0x7288, RHD_RV570 ), /* Radeon X1950 GT */
136
    RHD_DEVICE_MATCH(  0x7289, RHD_RV570 ), /* RV570 */
230
    RHD_DEVICE_MATCH(  0x7289, RHD_RV570 ), /* RV570 */
137
    RHD_DEVICE_MATCH(  0x728B, RHD_RV570 ), /* RV570 */
231
    RHD_DEVICE_MATCH(  0x728B, RHD_RV570 ), /* RV570 */
138
    RHD_DEVICE_MATCH(  0x728C, RHD_RV570 ), /* ATI FireGL V7400  */
232
    RHD_DEVICE_MATCH(  0x728C, RHD_RV570 ), /* ATI FireGL V7400  */
139
    RHD_DEVICE_MATCH(  0x7290, RHD_RV560 ), /* RV560 */
233
    RHD_DEVICE_MATCH(  0x7290, RHD_RV560 ), /* RV560 */
140
    RHD_DEVICE_MATCH(  0x7291, RHD_RV560 ), /* Radeon X1650 */
234
    RHD_DEVICE_MATCH(  0x7291, RHD_RV560 ), /* Radeon X1650 */
141
    RHD_DEVICE_MATCH(  0x7293, RHD_RV560 ), /* Radeon X1650 */
235
    RHD_DEVICE_MATCH(  0x7293, RHD_RV560 ), /* Radeon X1650 */
142
    RHD_DEVICE_MATCH(  0x7297, RHD_RV560 ), /* RV560 */
236
    RHD_DEVICE_MATCH(  0x7297, RHD_RV560 ), /* RV560 */
143
    RHD_DEVICE_MATCH(  0x791E, RHD_RS690 ), /* Radeon X1200 */
237
    RHD_DEVICE_MATCH(  0x791E, RHD_RS690 ), /* Radeon X1200 */
144
    RHD_DEVICE_MATCH(  0x791F, RHD_RS690 ), /* Radeon X1200 */
238
    RHD_DEVICE_MATCH(  0x791F, RHD_RS690 ), /* Radeon X1200 */
145
    RHD_DEVICE_MATCH(  0x793F, RHD_RS600 ), /* Radeon Xpress 1200 */
239
    RHD_DEVICE_MATCH(  0x793F, RHD_RS600 ), /* Radeon Xpress 1200 */
146
    RHD_DEVICE_MATCH(  0x7941, RHD_RS600 ), /* Radeon Xpress 1200 */
240
    RHD_DEVICE_MATCH(  0x7941, RHD_RS600 ), /* Radeon Xpress 1200 */
147
    RHD_DEVICE_MATCH(  0x7942, RHD_RS600 ), /* Radeon Xpress 1200 (M) */
241
    RHD_DEVICE_MATCH(  0x7942, RHD_RS600 ), /* Radeon Xpress 1200 (M) */
148
    RHD_DEVICE_MATCH(  0x796C, RHD_RS740 ), /* RS740 */
242
    RHD_DEVICE_MATCH(  0x796C, RHD_RS740 ), /* RS740 */
149
    RHD_DEVICE_MATCH(  0x796D, RHD_RS740 ), /* RS740M */
243
    RHD_DEVICE_MATCH(  0x796D, RHD_RS740 ), /* RS740M */
150
    RHD_DEVICE_MATCH(  0x796E, RHD_RS740 ), /* ATI Radeon 2100 RS740 */
244
    RHD_DEVICE_MATCH(  0x796E, RHD_RS740 ), /* ATI Radeon 2100 RS740 */
151
    RHD_DEVICE_MATCH(  0x796F, RHD_RS740 ), /* RS740M */
245
    RHD_DEVICE_MATCH(  0x796F, RHD_RS740 ), /* RS740M */
152
    RHD_DEVICE_MATCH(  0x9400, RHD_R600  ), /* Radeon HD 2900 XT */
246
    RHD_DEVICE_MATCH(  0x9400, RHD_R600  ), /* Radeon HD 2900 XT */
153
    RHD_DEVICE_MATCH(  0x9401, RHD_R600  ), /* Radeon HD 2900 XT */
247
    RHD_DEVICE_MATCH(  0x9401, RHD_R600  ), /* Radeon HD 2900 XT */
154
    RHD_DEVICE_MATCH(  0x9402, RHD_R600  ), /* Radeon HD 2900 XT */
248
    RHD_DEVICE_MATCH(  0x9402, RHD_R600  ), /* Radeon HD 2900 XT */
155
    RHD_DEVICE_MATCH(  0x9403, RHD_R600  ), /* Radeon HD 2900 Pro */
249
    RHD_DEVICE_MATCH(  0x9403, RHD_R600  ), /* Radeon HD 2900 Pro */
156
    RHD_DEVICE_MATCH(  0x9405, RHD_R600  ), /* Radeon HD 2900 GT */
250
    RHD_DEVICE_MATCH(  0x9405, RHD_R600  ), /* Radeon HD 2900 GT */
157
    RHD_DEVICE_MATCH(  0x940A, RHD_R600  ), /* FireGL V8650 */
251
    RHD_DEVICE_MATCH(  0x940A, RHD_R600  ), /* FireGL V8650 */
158
    RHD_DEVICE_MATCH(  0x940B, RHD_R600  ), /* FireGL V8600 */
252
    RHD_DEVICE_MATCH(  0x940B, RHD_R600  ), /* FireGL V8600 */
159
    RHD_DEVICE_MATCH(  0x940F, RHD_R600  ), /* FireGL V7600 */
253
    RHD_DEVICE_MATCH(  0x940F, RHD_R600  ), /* FireGL V7600 */
160
    RHD_DEVICE_MATCH(  0x94C0, RHD_RV610 ), /* RV610 */
254
    RHD_DEVICE_MATCH(  0x94C0, RHD_RV610 ), /* RV610 */
161
    RHD_DEVICE_MATCH(  0x94C1, RHD_RV610 ), /* Radeon HD 2400 XT */
255
    RHD_DEVICE_MATCH(  0x94C1, RHD_RV610 ), /* Radeon HD 2400 XT */
162
    RHD_DEVICE_MATCH(  0x94C3, RHD_RV610 ), /* Radeon HD 2400 Pro */
256
    RHD_DEVICE_MATCH(  0x94C3, RHD_RV610 ), /* Radeon HD 2400 Pro */
163
    RHD_DEVICE_MATCH(  0x94C4, RHD_RV610 ), /* ATI Radeon HD 2400 PRO AGP */
257
    RHD_DEVICE_MATCH(  0x94C4, RHD_RV610 ), /* ATI Radeon HD 2400 PRO AGP */
164
    RHD_DEVICE_MATCH(  0x94C5, RHD_RV610 ), /* FireGL V4000 */
258
    RHD_DEVICE_MATCH(  0x94C5, RHD_RV610 ), /* FireGL V4000 */
165
    RHD_DEVICE_MATCH(  0x94C6, RHD_RV610 ), /* RV610 */
259
    RHD_DEVICE_MATCH(  0x94C6, RHD_RV610 ), /* RV610 */
166
    RHD_DEVICE_MATCH(  0x94C7, RHD_RV610 ), /* ATI Radeon HD 2350 */
260
    RHD_DEVICE_MATCH(  0x94C7, RHD_RV610 ), /* ATI Radeon HD 2350 */
167
    RHD_DEVICE_MATCH(  0x94C8, RHD_M74   ), /* Mobility Radeon HD 2400 XT */
261
    RHD_DEVICE_MATCH(  0x94C8, RHD_M74   ), /* Mobility Radeon HD 2400 XT */
168
    RHD_DEVICE_MATCH(  0x94C9, RHD_M72   ), /* Mobility Radeon HD 2400 */
262
    RHD_DEVICE_MATCH(  0x94C9, RHD_M72   ), /* Mobility Radeon HD 2400 */
169
    RHD_DEVICE_MATCH(  0x94CB, RHD_M72   ), /* ATI RADEON E2400 */
263
    RHD_DEVICE_MATCH(  0x94CB, RHD_M72   ), /* ATI RADEON E2400 */
170
    RHD_DEVICE_MATCH(  0x94CC, RHD_RV610 ), /* ATI Radeon HD 2400 */
264
    RHD_DEVICE_MATCH(  0x94CC, RHD_RV610 ), /* ATI Radeon HD 2400 */
171
    RHD_DEVICE_MATCH(  0x9500, RHD_RV670 ), /* RV670 */
265
    RHD_DEVICE_MATCH(  0x9500, RHD_RV670 ), /* RV670 */
172
    RHD_DEVICE_MATCH(  0x9501, RHD_RV670 ), /* ATI Radeon HD3870 */
266
    RHD_DEVICE_MATCH(  0x9501, RHD_RV670 ), /* ATI Radeon HD3870 */
173
    RHD_DEVICE_MATCH(  0x9505, RHD_RV670 ), /* ATI Radeon HD3850 */
267
    RHD_DEVICE_MATCH(  0x9505, RHD_RV670 ), /* ATI Radeon HD3850 */
174
    RHD_DEVICE_MATCH(  0x9507, RHD_RV670 ), /* RV670 */
268
    RHD_DEVICE_MATCH(  0x9507, RHD_RV670 ), /* RV670 */
175
    RHD_DEVICE_MATCH(  0x950F, RHD_R680  ), /* ATI Radeon HD3870 X2 */
269
    RHD_DEVICE_MATCH(  0x950F, RHD_R680  ), /* ATI Radeon HD3870 X2 */
176
    RHD_DEVICE_MATCH(  0x9511, RHD_RV670 ), /* ATI FireGL V7700 */
270
    RHD_DEVICE_MATCH(  0x9511, RHD_RV670 ), /* ATI FireGL V7700 */
177
    RHD_DEVICE_MATCH(  0x9515, RHD_RV670 ), /* ATI Radeon HD 3850 AGP */
271
    RHD_DEVICE_MATCH(  0x9515, RHD_RV670 ), /* ATI Radeon HD 3850 AGP */
178
    RHD_DEVICE_MATCH(  0x9580, RHD_RV630 ), /* RV630 */
272
    RHD_DEVICE_MATCH(  0x9580, RHD_RV630 ), /* RV630 */
179
    RHD_DEVICE_MATCH(  0x9581, RHD_M76   ), /* Mobility Radeon HD 2600 */
273
    RHD_DEVICE_MATCH(  0x9581, RHD_M76   ), /* Mobility Radeon HD 2600 */
180
    RHD_DEVICE_MATCH(  0x9583, RHD_M76   ), /* Mobility Radeon HD 2600 XT */
274
    RHD_DEVICE_MATCH(  0x9583, RHD_M76   ), /* Mobility Radeon HD 2600 XT */
181
    RHD_DEVICE_MATCH(  0x9586, RHD_RV630 ), /* ATI Radeon HD 2600 XT AGP */
275
    RHD_DEVICE_MATCH(  0x9586, RHD_RV630 ), /* ATI Radeon HD 2600 XT AGP */
182
    RHD_DEVICE_MATCH(  0x9587, RHD_RV630 ), /* ATI Radeon HD 2600 Pro AGP */
276
    RHD_DEVICE_MATCH(  0x9587, RHD_RV630 ), /* ATI Radeon HD 2600 Pro AGP */
183
    RHD_DEVICE_MATCH(  0x9588, RHD_RV630 ), /* Radeon HD 2600 XT */
277
    RHD_DEVICE_MATCH(  0x9588, RHD_RV630 ), /* Radeon HD 2600 XT */
184
    RHD_DEVICE_MATCH(  0x9589, RHD_RV630 ), /* Radeon HD 2600 Pro */
278
    RHD_DEVICE_MATCH(  0x9589, RHD_RV630 ), /* Radeon HD 2600 Pro */
185
    RHD_DEVICE_MATCH(  0x958A, RHD_RV630 ), /* Gemini RV630 */
279
    RHD_DEVICE_MATCH(  0x958A, RHD_RV630 ), /* Gemini RV630 */
186
    RHD_DEVICE_MATCH(  0x958B, RHD_M76   ), /* Gemini ATI Mobility Radeon HD 2600 XT */
280
    RHD_DEVICE_MATCH(  0x958B, RHD_M76   ), /* Gemini ATI Mobility Radeon HD 2600 XT */
187
    RHD_DEVICE_MATCH(  0x958C, RHD_RV630 ), /* FireGL V5600 */
281
    RHD_DEVICE_MATCH(  0x958C, RHD_RV630 ), /* FireGL V5600 */
188
    RHD_DEVICE_MATCH(  0x958D, RHD_RV630 ), /* FireGL V3600 */
282
    RHD_DEVICE_MATCH(  0x958D, RHD_RV630 ), /* FireGL V3600 */
189
    RHD_DEVICE_MATCH(  0x958E, RHD_RV630 ), /* ATI Radeon HD 2600 LE */
283
    RHD_DEVICE_MATCH(  0x958E, RHD_RV630 ), /* ATI Radeon HD 2600 LE */
190
    RHD_DEVICE_MATCH(  0x9590, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
284
    RHD_DEVICE_MATCH(  0x9590, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
191
    RHD_DEVICE_MATCH(  0x9591, RHD_RV635 ), /* ATI Mobility Radeon HD 3650 */
285
    RHD_DEVICE_MATCH(  0x9591, RHD_RV635 ), /* ATI Mobility Radeon HD 3650 */
192
    RHD_DEVICE_MATCH(  0x9596, RHD_RV635 ), /* ATI Radeon HD 3650 AGP */
286
    RHD_DEVICE_MATCH(  0x9596, RHD_RV635 ), /* ATI Radeon HD 3650 AGP */
193
    RHD_DEVICE_MATCH(  0x9597, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
287
    RHD_DEVICE_MATCH(  0x9597, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
194
    RHD_DEVICE_MATCH(  0x9598, RHD_RV635 ), /* ATI Radeon HD 3670 */
288
    RHD_DEVICE_MATCH(  0x9598, RHD_RV635 ), /* ATI Radeon HD 3670 */
195
    RHD_DEVICE_MATCH(  0x9599, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
289
    RHD_DEVICE_MATCH(  0x9599, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
196
    RHD_DEVICE_MATCH(  0x95C0, RHD_RV620 ), /* ATI Radeon HD 3470 */
290
    RHD_DEVICE_MATCH(  0x95C0, RHD_RV620 ), /* ATI Radeon HD 3470 */
197
    RHD_DEVICE_MATCH(  0x95C2, RHD_M82   ), /* ATI Mobility Radeon HD 3430 (M82) */
291
    RHD_DEVICE_MATCH(  0x95C2, RHD_M82   ), /* ATI Mobility Radeon HD 3430 (M82) */
198
    RHD_DEVICE_MATCH(  0x95C4, RHD_M82 ), /* ATI Mobility Radeon HD 3400 Series (M82)  */
292
    RHD_DEVICE_MATCH(  0x95C4, RHD_M82 ), /* ATI Mobility Radeon HD 3400 Series (M82)  */
199
    RHD_DEVICE_MATCH(  0x95C5, RHD_RV620 ), /* ATI Radeon HD 3450 */
293
    RHD_DEVICE_MATCH(  0x95C5, RHD_RV620 ), /* ATI Radeon HD 3450 */
200
    RHD_DEVICE_MATCH(  0x95C7, RHD_RV620 ), /* ATI Radeon HD 3430 */
294
    RHD_DEVICE_MATCH(  0x95C7, RHD_RV620 ), /* ATI Radeon HD 3430 */
201
    RHD_DEVICE_MATCH(  0x95CD, RHD_RV620 ), /* ATI FireMV 2450  */
295
    RHD_DEVICE_MATCH(  0x95CD, RHD_RV620 ), /* ATI FireMV 2450  */
202
    RHD_DEVICE_MATCH(  0x95CE, RHD_RV620 ), /* ATI FireMV 2260  */
296
    RHD_DEVICE_MATCH(  0x95CE, RHD_RV620 ), /* ATI FireMV 2260  */
203
    RHD_DEVICE_MATCH(  0x95CF, RHD_RV620 ), /* ATI FireMV 2260  */
297
    RHD_DEVICE_MATCH(  0x95CF, RHD_RV620 ), /* ATI FireMV 2260  */
204
    LIST_END
298
    LIST_END
205
};
299
};
206
 
300
 
207
const char *
301
const char *
208
xf86TokenToString(SymTabPtr table, int token)
302
xf86TokenToString(SymTabPtr table, int token)
209
{
303
{
210
    int i;
304
    int i;
211
 
305
 
212
    for (i = 0; table[i].token >= 0 && table[i].token != token; i++){};
306
    for (i = 0; table[i].token >= 0 && table[i].token != token; i++){};
213
 
307
 
214
    if (table[i].token < 0)
308
    if (table[i].token < 0)
215
      return NULL;
309
      return NULL;
216
    else
310
    else
217
      return(table[i].name);
311
      return(table[i].name);
218
}
312
}
219
 
313
 
220
RHDPtr FindPciDevice()
314
RHDPtr FindPciDevice()
221
{
315
{
222
  const PciChipset_t *dev;
316
  const PciChipset_t *dev;
223
  u32 bus, last_bus;
317
  u32 bus, last_bus;
224
 
318
 
225
  if( (last_bus = PciApi(1))==-1)
319
  if( (last_bus = PciApi(1))==-1)
226
    return 0;
320
    return 0;
227
 
321
 
228
  for(bus=0;bus<=last_bus;bus++)
322
  for(bus=0;bus<=last_bus;bus++)
229
  {
323
  {
230
    u32 devfn;
324
    u32 devfn;
231
 
325
 
232
    for(devfn=0;devfn<256;devfn++)
326
    for(devfn=0;devfn<256;devfn++)
233
    {
327
    {
234
      u32 id;
328
      u32 id;
235
      id = PciRead32(bus,devfn, 0);
329
      id = PciRead32(bus,devfn, 0);
236
 
330
 
237
      if( (CARD16)id != VENDOR_ATI)
331
      if( (CARD16)id != VENDOR_ATI)
238
        continue;
332
        continue;
239
 
333
 
240
      if( (dev=PciDevMatch(id>>16,RHDPCIchipsets))!=NULL)
334
      if( (dev=PciDevMatch(id>>16,RHDPCIchipsets))!=NULL)
241
      {
335
      {
242
        CARD32 reg2C;
336
        CARD32 reg2C;
243
        int i;
337
        int i;
244
 
338
 
245
        rhd.PciDeviceID = (id>>16);
339
        rhd.PciDeviceID = (id>>16);
246
 
340
 
247
        rhd.bus = bus;
341
        rhd.bus = bus;
248
        rhd.devfn = devfn;
342
        rhd.devfn = devfn;
249
        rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7);
343
        rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7);
250
 
344
 
251
        rhd.ChipSet = dev->ChipSet;
345
        rhd.ChipSet = dev->ChipSet;
252
 
346
 
253
        reg2C = PciRead32(bus,devfn, 0x2C);
347
        reg2C = PciRead32(bus,devfn, 0x2C);
254
 
348
 
255
        rhd.subvendor_id = reg2C & 0xFFFF;;
349
        rhd.subvendor_id = reg2C & 0xFFFF;;
256
        rhd.subdevice_id = reg2C >> 16;
350
        rhd.subdevice_id = reg2C >> 16;
257
 
351
 
258
        for (i = 0; i < 6; i++)
352
        for (i = 0; i < 6; i++)
259
        {
353
        {
260
          CARD32 base;
354
          CARD32 base;
261
          Bool validSize;
355
          Bool validSize;
262
 
356
 
263
          base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2));
357
          base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2));
264
          if(base)
358
          if(base)
265
          {
359
          {
266
            if (base & PCI_MAP_IO)
360
            if (base & PCI_MAP_IO)
267
            {
361
            {
268
              rhd.ioBase[i] = (CARD32)PCIGETIO(base);
362
              rhd.ioBase[i] = (CARD32)PCIGETIO(base);
269
              rhd.memtype[i]   = base & PCI_MAP_IO_ATTR_MASK;
363
              rhd.memtype[i]   = base & PCI_MAP_IO_ATTR_MASK;
270
            }
364
            }
271
            else
365
            else
272
            {
366
            {
273
              rhd.memBase[i] = (CARD32)PCIGETMEMORY(base);
367
              rhd.memBase[i] = (CARD32)PCIGETMEMORY(base);
274
              rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK;
368
              rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK;
275
            }
369
            }
276
          }
370
          }
277
          rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize);
371
          rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize);
278
        }
372
        }
279
        rhd.ChipName = (char*)xf86TokenToString(RHDChipsets, rhd.PciDeviceID);
373
        rhd.ChipName = (char*)xf86TokenToString(RHDChipsets, rhd.PciDeviceID);
280
 
374
 
281
        return &rhd;
375
        return &rhd;
282
      }
376
      }
283
    };
377
    };
284
  };
378
  };
285
  return NULL;
379
  return NULL;
286
}
380
}
287
 
381
 
288
const PciChipset_t *PciDevMatch(CARD16 dev,const PciChipset_t *list)
382
const PciChipset_t *PciDevMatch(CARD16 dev,const PciChipset_t *list)
289
{
383
{
290
  while(list->device)
384
  while(list->device)
291
  {
385
  {
292
    if(dev==list->device)
386
    if(dev==list->device)
293
      return list;
387
      return list;
294
    list++;
388
    list++;
295
  }
389
  }
296
  return 0;
390
  return 0;
297
}
391
}
298
 
392
 
299
 
393
 
300
CARD32 pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min)
394
CARD32 pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min)
301
{
395
{
302
  int offset;
396
  int offset;
303
  CARD32 addr1;
397
  CARD32 addr1;
304
  CARD32 addr2;
398
  CARD32 addr2;
305
  CARD32 mask1;
399
  CARD32 mask1;
306
  CARD32 mask2;
400
  CARD32 mask2;
307
  int bits = 0;
401
  int bits = 0;
308
 
402
 
309
  /*
403
  /*
310
   * silently ignore bogus index values.  Valid values are 0-6.  0-5 are
404
   * silently ignore bogus index values.  Valid values are 0-6.  0-5 are
311
   * the 6 base address registers, and 6 is the ROM base address register.
405
   * the 6 base address registers, and 6 is the ROM base address register.
312
   */
406
   */
313
  if (index < 0 || index > 6)
407
  if (index < 0 || index > 6)
314
    return 0;
408
    return 0;
315
 
409
 
316
  if (min)
410
  if (min)
317
    *min = destructive;
411
    *min = destructive;
318
 
412
 
319
  /* Get the PCI offset */
413
  /* Get the PCI offset */
320
  if (index == 6)
414
  if (index == 6)
321
    offset = PCI_MAP_ROM_REG;
415
    offset = PCI_MAP_ROM_REG;
322
  else
416
  else
323
    offset = PCI_MAP_REG_START + (index << 2);
417
    offset = PCI_MAP_REG_START + (index << 2);
324
 
418
 
325
  addr1 = PciRead32(bus, devfn, offset);
419
  addr1 = PciRead32(bus, devfn, offset);
326
  /*
420
  /*
327
   * Check if this is the second part of a 64 bit address.
421
   * Check if this is the second part of a 64 bit address.
328
   * XXX need to check how endianness affects 64 bit addresses.
422
   * XXX need to check how endianness affects 64 bit addresses.
329
   */
423
   */
330
  if (index > 0 && index < 6) {
424
  if (index > 0 && index < 6) {
331
    addr2 = PciRead32(bus, devfn, offset - 4);
425
    addr2 = PciRead32(bus, devfn, offset - 4);
332
    if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2))
426
    if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2))
333
      return 0;
427
      return 0;
334
  }
428
  }
335
 
429
 
336
  if (destructive) {
430
  if (destructive) {
337
     PciWrite32(bus, devfn, offset, 0xffffffff);
431
     PciWrite32(bus, devfn, offset, 0xffffffff);
338
     mask1 = PciRead32(bus, devfn, offset);
432
     mask1 = PciRead32(bus, devfn, offset);
339
     PciWrite32(bus, devfn, offset, addr1);
433
     PciWrite32(bus, devfn, offset, addr1);
340
  } else {
434
  } else {
341
    mask1 = addr1;
435
    mask1 = addr1;
342
  }
436
  }
343
 
437
 
344
  /* Check if this is the first part of a 64 bit address. */
438
  /* Check if this is the first part of a 64 bit address. */
345
  if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1))
439
  if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1))
346
  {
440
  {
347
    if (PCIGETMEMORY(mask1) == 0)
441
    if (PCIGETMEMORY(mask1) == 0)
348
    {
442
    {
349
      addr2 = PciRead32(bus, devfn, offset + 4);
443
      addr2 = PciRead32(bus, devfn, offset + 4);
350
      if (destructive)
444
      if (destructive)
351
      {
445
      {
352
        PciWrite32(bus, devfn, offset + 4, 0xffffffff);
446
        PciWrite32(bus, devfn, offset + 4, 0xffffffff);
353
        mask2 = PciRead32(bus, devfn, offset + 4);
447
        mask2 = PciRead32(bus, devfn, offset + 4);
354
        PciWrite32(bus, devfn, offset + 4, addr2);
448
        PciWrite32(bus, devfn, offset + 4, addr2);
355
      }
449
      }
356
      else
450
      else
357
     {
451
     {
358
       mask2 = addr2;
452
       mask2 = addr2;
359
     }
453
     }
360
     if (mask2 == 0)
454
     if (mask2 == 0)
361
       return 0;
455
       return 0;
362
     bits = 32;
456
     bits = 32;
363
     while ((mask2 & 1) == 0)
457
     while ((mask2 & 1) == 0)
364
     {
458
     {
365
       bits++;
459
       bits++;
366
       mask2 >>= 1;
460
       mask2 >>= 1;
367
     }
461
     }
368
     if (bits > 32)
462
     if (bits > 32)
369
	  return bits;
463
	  return bits;
370
    }
464
    }
371
  }
465
  }
372
  if (index < 6)
466
  if (index < 6)
373
    if (PCI_MAP_IS_MEM(mask1))
467
    if (PCI_MAP_IS_MEM(mask1))
374
      mask1 = PCIGETMEMORY(mask1);
468
      mask1 = PCIGETMEMORY(mask1);
375
    else
469
    else
376
      mask1 = PCIGETIO(mask1);
470
      mask1 = PCIGETIO(mask1);
377
  else
471
  else
378
    mask1 = PCIGETROM(mask1);
472
    mask1 = PCIGETROM(mask1);
379
  if (mask1 == 0)
473
  if (mask1 == 0)
380
    return 0;
474
    return 0;
381
  bits = 0;
475
  bits = 0;
382
  while ((mask1 & 1) == 0) {
476
  while ((mask1 & 1) == 0) {
383
    bits++;
477
    bits++;
384
    mask1 >>= 1;
478
    mask1 >>= 1;
385
  }
479
  }
386
  /* I/O maps can be no larger than 8 bits */
480
  /* I/O maps can be no larger than 8 bits */
387
 
481
 
388
  if ((index < 6) && PCI_MAP_IS_IO(addr1) && bits > 8)
482
  if ((index < 6) && PCI_MAP_IS_IO(addr1) && bits > 8)
389
    bits = 8;
483
    bits = 8;
390
  /* ROM maps can be no larger than 24 bits */
484
  /* ROM maps can be no larger than 24 bits */
391
  if (index == 6 && bits > 24)
485
  if (index == 6 && bits > 24)
392
    bits = 24;
486
    bits = 24;
393
  return bits;
487
  return bits;
394
}
488
}
395
>
489
>
396
>
490
>