WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/rs600.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
/* RS600 / Radeon X1250/X1270 integrated GPU
 *
 * This file gather function specific to RS600 which is the IGP of
 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
 * is the X1250/X1270 supporting AMD CPU). The display engine are
 * the avivo one, bios is an atombios, 3D block are the one of the
 * R4XX family. The GART is different from the RS400 one and is very
 * close to the one of the R600 family (R600 likely being an evolution
 * of the RS600 GART block).
 */
#include 
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"
#include "rs600d.h"
 
#include "rs600_reg_safe.h"
 
static void rs600_gpu_init(struct radeon_device *rdev);
int rs600_mc_wait_for_idle(struct radeon_device *rdev);
 
static const u32 crtc_offsets[2] =
{
	0,
	AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
};
 
void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
{
	int i;
 
	if (crtc >= rdev->num_crtc)
		return;
 
	if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) {
		for (i = 0; i < rdev->usec_timeout; i++) {
			if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK))
				break;
			udelay(1);
		}
		for (i = 0; i < rdev->usec_timeout; i++) {
			if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
				break;
			udelay(1);
		}
	}
}
/* hpd for digital panel detect/disconnect */
bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
{
	u32 tmp;
	bool connected = false;
 
	switch (hpd) {
	case RADEON_HPD_1:
		tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
		if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
			connected = true;
		break;
	case RADEON_HPD_2:
		tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
		if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
			connected = true;
		break;
	default:
		break;
	}
	return connected;
}
 
void rs600_hpd_set_polarity(struct radeon_device *rdev,
			    enum radeon_hpd_id hpd)
{
	u32 tmp;
	bool connected = rs600_hpd_sense(rdev, hpd);
 
	switch (hpd) {
	case RADEON_HPD_1:
		tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
		if (connected)
			tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
		else
			tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
		WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
		break;
	case RADEON_HPD_2:
		tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
		if (connected)
			tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
		else
			tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
		WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
		break;
	default:
		break;
	}
}
 
void rs600_hpd_init(struct radeon_device *rdev)
{
	struct drm_device *dev = rdev->ddev;
	struct drm_connector *connector;
	unsigned enable = 0;
 
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		switch (radeon_connector->hpd.hpd) {
		case RADEON_HPD_1:
			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
			       S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
 
			break;
		case RADEON_HPD_2:
			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
			       S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
 
			break;
		default:
			break;
		}
		enable |= 1 << radeon_connector->hpd.hpd;
		radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
	}
 
//	radeon_irq_kms_enable_hpd(rdev, enable);
}
 
void rs600_hpd_fini(struct radeon_device *rdev)
{
	struct drm_device *dev = rdev->ddev;
	struct drm_connector *connector;
	unsigned disable = 0;
 
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		switch (radeon_connector->hpd.hpd) {
		case RADEON_HPD_1:
			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
			       S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
 
			break;
		case RADEON_HPD_2:
			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
			       S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
 
			break;
		default:
			break;
		}
		disable |= 1 << radeon_connector->hpd.hpd;
	}
 
 
//	radeon_irq_kms_disable_hpd(rdev, disable);
 
 
 
 
 
 
 
}
 
int rs600_asic_reset(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
	u32 status, tmp;
	int ret = 0;
 
	status = RREG32(R_000E40_RBBM_STATUS);
	if (!G_000E40_GUI_ACTIVE(status)) {
		return 0;
	}
	/* Stops all mc clients */
	rv515_mc_stop(rdev, &save);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* stop CP */
	WREG32(RADEON_CP_CSQ_CNTL, 0);
	tmp = RREG32(RADEON_CP_RB_CNTL);
	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
	WREG32(RADEON_CP_RB_RPTR_WR, 0);
	WREG32(RADEON_CP_RB_WPTR, 0);
	WREG32(RADEON_CP_RB_CNTL, tmp);
//   pci_save_state(rdev->pdev);
	/* disable bus mastering */
//	pci_clear_master(rdev->pdev);
	mdelay(1);
	/* reset GA+VAP */
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
					S_0000F0_SOFT_RESET_GA(1));
	RREG32(R_0000F0_RBBM_SOFT_RESET);
	mdelay(500);
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
	mdelay(1);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* reset CP */
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
	RREG32(R_0000F0_RBBM_SOFT_RESET);
	mdelay(500);
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
	mdelay(1);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* reset MC */
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
	RREG32(R_0000F0_RBBM_SOFT_RESET);
	mdelay(500);
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
	mdelay(1);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* restore PCI & busmastering */
//   pci_restore_state(rdev->pdev);
	/* Check if GPU is idle */
	if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
		dev_err(rdev->dev, "failed to reset GPU\n");
 
		ret = -1;
	} else
		dev_info(rdev->dev, "GPU reset succeed\n");
	rv515_mc_resume(rdev, &save);
	return ret;
}
 
/*
 * GART.
 */
void rs600_gart_tlb_flush(struct radeon_device *rdev)
{
	uint32_t tmp;
 
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
}
 
static int rs600_gart_init(struct radeon_device *rdev)
{
	int r;
 
	if (rdev->gart.robj) {
		WARN(1, "RS600 GART already initialized\n");
		return 0;
	}
	/* Initialize common gart structure */
	r = radeon_gart_init(rdev);
	if (r) {
		return r;
	}
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
	return radeon_gart_table_vram_alloc(rdev);
}
 
static int rs600_gart_enable(struct radeon_device *rdev)
{
	u32 tmp;
	int r, i;
 
	if (rdev->gart.robj == NULL) {
		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		return -EINVAL;
	}
	r = radeon_gart_table_vram_pin(rdev);
	if (r)
		return r;
	radeon_gart_restore(rdev);
	/* Enable bus master */
	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
	WREG32(RADEON_BUS_CNTL, tmp);
	/* FIXME: setup default page */
	WREG32_MC(R_000100_MC_PT0_CNTL,
		 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
		  S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
 
	for (i = 0; i < 19; i++) {
		WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
			S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
			S_00016C_SYSTEM_ACCESS_MODE_MASK(
				  V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
			S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
				  V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
			  S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
			S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
			  S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
	}
	/* enable first context */
	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
			S_000102_ENABLE_PAGE_TABLE(1) |
			S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
 
	/* disable all other contexts */
	for (i = 1; i < 8; i++)
		WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
 
	/* setup the page table */
	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
		 rdev->gart.table_addr);
	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 
	/* System context maps to VRAM space */
	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
 
	/* enable page tables */
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
	tmp = RREG32_MC(R_000009_MC_CNTL1);
	WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
	rs600_gart_tlb_flush(rdev);
	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
		 (unsigned)(rdev->mc.gtt_size >> 20),
		 (unsigned long long)rdev->gart.table_addr);
	rdev->gart.ready = true;
	return 0;
}
 
static void rs600_gart_disable(struct radeon_device *rdev)
{
 
	u32 tmp;
 
	/* FIXME: disable out of gart access */
	WREG32_MC(R_000100_MC_PT0_CNTL, 0);
	tmp = RREG32_MC(R_000009_MC_CNTL1);
	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
	radeon_gart_table_vram_unpin(rdev);
 
 
 
 
 
 
 
}
 
static void rs600_gart_fini(struct radeon_device *rdev)
{
	radeon_gart_fini(rdev);
	rs600_gart_disable(rdev);
	radeon_gart_table_vram_free(rdev);
}
 
#define R600_PTE_VALID     (1 << 0)
#define R600_PTE_SYSTEM    (1 << 1)
#define R600_PTE_SNOOPED   (1 << 2)
#define R600_PTE_READABLE  (1 << 5)
#define R600_PTE_WRITEABLE (1 << 6)
 
int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
{
	void __iomem *ptr = (void *)rdev->gart.ptr;
 
	if (i < 0 || i > rdev->gart.num_gpu_pages) {
		return -EINVAL;
	}
	addr = addr & 0xFFFFFFFFFFFFF000ULL;
	addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
	addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
	writeq(addr, ptr + (i * 8));
	return 0;
}
 
int rs600_irq_set(struct radeon_device *rdev)
{
	uint32_t tmp = 0;
	uint32_t mode_int = 0;
	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
		~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
		~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
	u32 hdmi0;
	if (ASIC_IS_DCE2(rdev))
		hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
			~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
	else
		hdmi0 = 0;
 
   if (!rdev->irq.installed) {
		WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
		WREG32(R_000040_GEN_INT_CNTL, 0);
		return -EINVAL;
	}
	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
		tmp |= S_000040_SW_INT_EN(1);
	}
 
 
 
	if (rdev->irq.crtc_vblank_int[0] ||
	    atomic_read(&rdev->irq.pflip[0])) {
		mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
	}
	if (rdev->irq.crtc_vblank_int[1] ||
	    atomic_read(&rdev->irq.pflip[1])) {
		mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
	}
	if (rdev->irq.hpd[0]) {
		hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
	}
	if (rdev->irq.hpd[1]) {
		hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
	}
	if (rdev->irq.afmt[0]) {
		hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
	}
	WREG32(R_000040_GEN_INT_CNTL, tmp);
	WREG32(R_006540_DxMODE_INT_MASK, mode_int);
	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
	if (ASIC_IS_DCE2(rdev))
		WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
	return 0;
}
 
static inline u32 rs600_irq_ack(struct radeon_device *rdev)
{
	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
	uint32_t irq_mask = S_000044_SW_INT(1);
	u32 tmp;
 
 
 
 
 
 
 
	if (G_000044_DISPLAY_INT_STAT(irqs)) {
		rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			WREG32(R_006534_D1MODE_VBLANK_STATUS,
				S_006534_D1MODE_VBLANK_ACK(1));
		}
		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			WREG32(R_006D34_D2MODE_VBLANK_STATUS,
				S_006D34_D2MODE_VBLANK_ACK(1));
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
			tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
			WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
			tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
			WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
		}
	} else {
		rdev->irq.stat_regs.r500.disp_int = 0;
	}
 
	if (ASIC_IS_DCE2(rdev)) {
		rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
			S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
		if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
			tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
			tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
			WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
		}
	} else
		rdev->irq.stat_regs.r500.hdmi0_status = 0;
 
	if (irqs) {
		WREG32(R_000044_GEN_INT_STATUS, irqs);
	}
	return irqs & irq_mask;
}
 
void rs600_irq_disable(struct radeon_device *rdev)
{
	u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
		~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
	WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
	WREG32(R_000040_GEN_INT_CNTL, 0);
	WREG32(R_006540_DxMODE_INT_MASK, 0);
	/* Wait and acknowledge irq */
	mdelay(1);
	rs600_irq_ack(rdev);
}
 
int rs600_irq_process(struct radeon_device *rdev)
{
	u32 status, msi_rearm;
	bool queue_hotplug = false;
 
 
	bool queue_hdmi = false;
 
	status = rs600_irq_ack(rdev);
	if (!status &&
	    !rdev->irq.stat_regs.r500.disp_int &&
	    !rdev->irq.stat_regs.r500.hdmi0_status) {
		return IRQ_NONE;
	}
	while (status ||
	       rdev->irq.stat_regs.r500.disp_int ||
	       rdev->irq.stat_regs.r500.hdmi0_status) {
		/* SW interrupt */
		if (G_000044_SW_INT(status)) {
 
 
 
 
 
 
			radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
		}
		/* Vertical blank interrupts */
		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			if (rdev->irq.crtc_vblank_int[0]) {
//				drm_handle_vblank(rdev->ddev, 0);
				rdev->pm.vblank_sync = true;
//				wake_up(&rdev->irq.vblank_queue);
			}
//			if (rdev->irq.pflip[0])
//				radeon_crtc_handle_flip(rdev, 0);
		}
		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			if (rdev->irq.crtc_vblank_int[1]) {
//				drm_handle_vblank(rdev->ddev, 1);
				rdev->pm.vblank_sync = true;
//				wake_up(&rdev->irq.vblank_queue);
			}
//			if (rdev->irq.pflip[1])
//				radeon_crtc_handle_flip(rdev, 1);
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			queue_hotplug = true;
			DRM_DEBUG("HPD1\n");
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			queue_hotplug = true;
			DRM_DEBUG("HPD2\n");
		}
		if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
			queue_hdmi = true;
			DRM_DEBUG("HDMI0\n");
		}
		status = rs600_irq_ack(rdev);
	}
 
 
//	if (queue_hotplug)
//		schedule_work(&rdev->hotplug_work);
//	if (queue_hdmi)
//		schedule_work(&rdev->audio_work);
	if (rdev->msi_enabled) {
		switch (rdev->family) {
		case CHIP_RS600:
		case CHIP_RS690:
		case CHIP_RS740:
			msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
			WREG32(RADEON_BUS_CNTL, msi_rearm);
			WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
			break;
		default:
 
 
			WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
			break;
		}
	}
	return IRQ_HANDLED;
}
 
u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
{
	if (crtc == 0)
		return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
	else
		return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
}
 
int rs600_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
 
	for (i = 0; i < rdev->usec_timeout; i++) {
		if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
			return 0;
		udelay(1);
	}
	return -1;
}
 
static void rs600_gpu_init(struct radeon_device *rdev)
{
	r420_pipes_init(rdev);
	/* Wait for mc idle */
	if (rs600_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
}
 
static void rs600_mc_init(struct radeon_device *rdev)
{
	u64 base;
 
	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
	rdev->mc.vram_is_ddr = true;
	rdev->mc.vram_width = 128;
	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
	rdev->mc.visible_vram_size = rdev->mc.aper_size;
	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
	base = RREG32_MC(R_000004_MC_FB_LOCATION);
	base = G_000004_MC_FB_START(base) << 16;
	radeon_vram_location(rdev, &rdev->mc, base);
	rdev->mc.gtt_base_align = 0;
	radeon_gtt_location(rdev, &rdev->mc);
	radeon_update_bandwidth_info(rdev);
}
 
void rs600_bandwidth_update(struct radeon_device *rdev)
{
	struct drm_display_mode *mode0 = NULL;
	struct drm_display_mode *mode1 = NULL;
	u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
	/* FIXME: implement full support */
 
	radeon_update_display_priority(rdev);
 
	if (rdev->mode_info.crtcs[0]->base.enabled)
		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
	if (rdev->mode_info.crtcs[1]->base.enabled)
		mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 
	rs690_line_buffer_adjust(rdev, mode0, mode1);
 
	if (rdev->disp_priority == 2) {
		d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
		d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
		d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
		d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
		WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
		WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
		WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
		WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
	}
}
 
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
{
	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
		S_000070_MC_IND_CITF_ARB0(1));
	return RREG32(R_000074_MC_IND_DATA);
}
 
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
		S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
	WREG32(R_000074_MC_IND_DATA, v);
}
 
static void rs600_debugfs(struct radeon_device *rdev)
{
	if (r100_debugfs_rbbm_init(rdev))
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
}
 
void rs600_set_safe_registers(struct radeon_device *rdev)
{
	rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
}
 
static void rs600_mc_program(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
 
	/* Stops all mc clients */
	rv515_mc_stop(rdev, &save);
 
	/* Wait for mc idle */
	if (rs600_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 
	/* FIXME: What does AGP means for such chipset ? */
	WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
	WREG32_MC(R_000006_AGP_BASE, 0);
	WREG32_MC(R_000007_AGP_BASE_2, 0);
	/* Program MC */
	WREG32_MC(R_000004_MC_FB_LOCATION,
			S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
			S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
	WREG32(R_000134_HDP_FB_LOCATION,
		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 
	rv515_mc_resume(rdev, &save);
}
 
static int rs600_startup(struct radeon_device *rdev)
{
	int r;
 
	rs600_mc_program(rdev);
	/* Resume clock */
	rv515_clock_startup(rdev);
	/* Initialize GPU configuration (# pipes, ...) */
	rs600_gpu_init(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	r = rs600_gart_enable(rdev);
	if (r)
	return r;
 
	/* allocate wb buffer */
	r = radeon_wb_init(rdev);
	if (r)
		return r;
 
	/* Enable IRQ */
	rs600_irq_set(rdev);
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
	r = r100_cp_init(rdev, 1024 * 1024);
	if (r) {
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
		return r;
	}
 
	r = radeon_ib_pool_init(rdev);
	if (r) {
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
		return r;
	}
 
 
	return 0;
}
 
 
 
int rs600_init(struct radeon_device *rdev)
{
	int r;
 
	/* Disable VGA */
	rv515_vga_render_disable(rdev);
	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* restore some register to sane defaults */
	r100_restore_sanity(rdev);
	/* BIOS */
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r)
			return r;
	} else {
		dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
		return -EINVAL;
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_asic_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (radeon_boot_test_post_card(rdev) == false)
		return -EINVAL;
 
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* initialize memory controller */
	rs600_mc_init(rdev);
	rs600_debugfs(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r)
		return r;
	r = radeon_irq_kms_init(rdev);
	if (r)
		return r;
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r)
		return r;
	r = rs600_gart_init(rdev);
	if (r)
		return r;
	rs600_set_safe_registers(rdev);
 
	rdev->accel_working = true;
	r = rs600_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
//		r100_cp_fini(rdev);
//		r100_wb_fini(rdev);
//		r100_ib_fini(rdev);
		rs600_gart_fini(rdev);
//		radeon_irq_kms_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}

Rev 2160	Rev 2997
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	/* RS600 / Radeon X1250/X1270 integrated GPU	28	/* RS600 / Radeon X1250/X1270 integrated GPU
29	*	29	*
30	* This file gather function specific to RS600 which is the IGP of	30	* This file gather function specific to RS600 which is the IGP of
31	* the X1250/X1270 family supporting intel CPU (while RS690/RS740	31	* the X1250/X1270 family supporting intel CPU (while RS690/RS740
32	* is the X1250/X1270 supporting AMD CPU). The display engine are	32	* is the X1250/X1270 supporting AMD CPU). The display engine are
33	* the avivo one, bios is an atombios, 3D block are the one of the	33	* the avivo one, bios is an atombios, 3D block are the one of the
34	* R4XX family. The GART is different from the RS400 one and is very	34	* R4XX family. The GART is different from the RS400 one and is very
35	* close to the one of the R600 family (R600 likely being an evolution	35	* close to the one of the R600 family (R600 likely being an evolution
36	* of the RS600 GART block).	36	* of the RS600 GART block).
37	*/	37	*/
38	#include "drmP.h"	38	#include
39	#include "radeon.h"	39	#include "radeon.h"
40	#include "radeon_asic.h"	40	#include "radeon_asic.h"
41	#include "atom.h"	41	#include "atom.h"
42	#include "rs600d.h"	42	#include "rs600d.h"
43		43
44	#include "rs600_reg_safe.h"	44	#include "rs600_reg_safe.h"
45		45
46	void rs600_gpu_init(struct radeon_device *rdev);	46	static void rs600_gpu_init(struct radeon_device *rdev);
-		47	int rs600_mc_wait_for_idle(struct radeon_device *rdev);
-		48
-		49	static const u32 crtc_offsets[2] =
-		50	{
-		51	0,
-		52	AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
-		53	};
-		54
-		55	void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
-		56	{
-		57	int i;
-		58
-		59	if (crtc >= rdev->num_crtc)
-		60	return;
-		61
-		62	if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) {
-		63	for (i = 0; i < rdev->usec_timeout; i++) {
-		64	if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK))
-		65	break;
-		66	udelay(1);
-		67	}
-		68	for (i = 0; i < rdev->usec_timeout; i++) {
-		69	if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
-		70	break;
-		71	udelay(1);
-		72	}
47	int rs600_mc_wait_for_idle(struct radeon_device *rdev);	73	}
48		74	}
49	/* hpd for digital panel detect/disconnect */	75	/* hpd for digital panel detect/disconnect */
50	bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)	76	bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
51	{	77	{
52	u32 tmp;	78	u32 tmp;
53	bool connected = false;	79	bool connected = false;
54		80
55	switch (hpd) {	81	switch (hpd) {
56	case RADEON_HPD_1:	82	case RADEON_HPD_1:
57	tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);	83	tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
58	if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))	84	if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
59	connected = true;	85	connected = true;
60	break;	86	break;
61	case RADEON_HPD_2:	87	case RADEON_HPD_2:
62	tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);	88	tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
63	if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))	89	if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
64	connected = true;	90	connected = true;
65	break;	91	break;
66	default:	92	default:
67	break;	93	break;
68	}	94	}
69	return connected;	95	return connected;
70	}	96	}
71		97
72	void rs600_hpd_set_polarity(struct radeon_device *rdev,	98	void rs600_hpd_set_polarity(struct radeon_device *rdev,
73	enum radeon_hpd_id hpd)	99	enum radeon_hpd_id hpd)
74	{	100	{
75	u32 tmp;	101	u32 tmp;
76	bool connected = rs600_hpd_sense(rdev, hpd);	102	bool connected = rs600_hpd_sense(rdev, hpd);
77		103
78	switch (hpd) {	104	switch (hpd) {
79	case RADEON_HPD_1:	105	case RADEON_HPD_1:
80	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);	106	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
81	if (connected)	107	if (connected)
82	tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);	108	tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
83	else	109	else
84	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);	110	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
85	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);	111	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
86	break;	112	break;
87	case RADEON_HPD_2:	113	case RADEON_HPD_2:
88	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);	114	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
89	if (connected)	115	if (connected)
90	tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);	116	tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
91	else	117	else
92	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);	118	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
93	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);	119	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
94	break;	120	break;
95	default:	121	default:
96	break;	122	break;
97	}	123	}
98	}	124	}
99		125
100	void rs600_hpd_init(struct radeon_device *rdev)	126	void rs600_hpd_init(struct radeon_device *rdev)
101	{	127	{
102	struct drm_device *dev = rdev->ddev;	128	struct drm_device *dev = rdev->ddev;
103	struct drm_connector *connector;	129	struct drm_connector *connector;
-		130	unsigned enable = 0;
104		131
105	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {	132	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
106	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	133	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
107	switch (radeon_connector->hpd.hpd) {	134	switch (radeon_connector->hpd.hpd) {
108	case RADEON_HPD_1:	135	case RADEON_HPD_1:
109	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,	136	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
110	S_007D00_DC_HOT_PLUG_DETECT1_EN(1));	137	S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
111	rdev->irq.hpd[0] = true;	-
112	break;	138	break;
113	case RADEON_HPD_2:	139	case RADEON_HPD_2:
114	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,	140	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
115	S_007D10_DC_HOT_PLUG_DETECT2_EN(1));	141	S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
116	rdev->irq.hpd[1] = true;	-
117	break;	142	break;
118	default:	143	default:
119	break;	144	break;
120	}	145	}
-		146	enable \|= 1 << radeon_connector->hpd.hpd;
-		147	radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
121	}	148	}
122	if (rdev->irq.installed)	-
123	rs600_irq_set(rdev);	149	// radeon_irq_kms_enable_hpd(rdev, enable);
124	}	150	}
125		151
126	void rs600_hpd_fini(struct radeon_device *rdev)	152	void rs600_hpd_fini(struct radeon_device *rdev)
127	{	153	{
128	struct drm_device *dev = rdev->ddev;	154	struct drm_device *dev = rdev->ddev;
129	struct drm_connector *connector;	155	struct drm_connector *connector;
-		156	unsigned disable = 0;
130		157
131	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {	158	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
132	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	159	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
133	switch (radeon_connector->hpd.hpd) {	160	switch (radeon_connector->hpd.hpd) {
134	case RADEON_HPD_1:	161	case RADEON_HPD_1:
135	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,	162	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
136	S_007D00_DC_HOT_PLUG_DETECT1_EN(0));	163	S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
137	rdev->irq.hpd[0] = false;	-
138	break;	164	break;
139	case RADEON_HPD_2:	165	case RADEON_HPD_2:
140	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,	166	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
141	S_007D10_DC_HOT_PLUG_DETECT2_EN(0));	167	S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
142	rdev->irq.hpd[1] = false;	-
143	break;	168	break;
144	default:	169	default:
145	break;	170	break;
146	}	171	}
-		172	disable \|= 1 << radeon_connector->hpd.hpd;
147	}	173	}
148	}	-
149		-
150	void rs600_bm_disable(struct radeon_device *rdev)	174	// radeon_irq_kms_disable_hpd(rdev, disable);
151	{	-
152	u32 tmp;	-
153		-
154	/* disable bus mastering */	-
155	tmp = PciRead16(rdev->pdev->bus, rdev->pdev->devfn, 0x4);	-
156	PciWrite16(rdev->pdev->bus, rdev->pdev->devfn, 0x4, tmp & 0xFFFB);	-
157	mdelay(1);	-
158	}	175	}
159		176
160	int rs600_asic_reset(struct radeon_device *rdev)	177	int rs600_asic_reset(struct radeon_device *rdev)
161	{	178	{
162	struct rv515_mc_save save;	179	struct rv515_mc_save save;
163	u32 status, tmp;	180	u32 status, tmp;
164	int ret = 0;	181	int ret = 0;
165		182
166	status = RREG32(R_000E40_RBBM_STATUS);	183	status = RREG32(R_000E40_RBBM_STATUS);
167	if (!G_000E40_GUI_ACTIVE(status)) {	184	if (!G_000E40_GUI_ACTIVE(status)) {
168	return 0;	185	return 0;
169	}	186	}
170	/* Stops all mc clients */	187	/* Stops all mc clients */
171	rv515_mc_stop(rdev, &save);	188	rv515_mc_stop(rdev, &save);
172	status = RREG32(R_000E40_RBBM_STATUS);	189	status = RREG32(R_000E40_RBBM_STATUS);
173	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	190	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
174	/* stop CP */	191	/* stop CP */
175	WREG32(RADEON_CP_CSQ_CNTL, 0);	192	WREG32(RADEON_CP_CSQ_CNTL, 0);
176	tmp = RREG32(RADEON_CP_RB_CNTL);	193	tmp = RREG32(RADEON_CP_RB_CNTL);
177	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);	194	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
178	WREG32(RADEON_CP_RB_RPTR_WR, 0);	195	WREG32(RADEON_CP_RB_RPTR_WR, 0);
179	WREG32(RADEON_CP_RB_WPTR, 0);	196	WREG32(RADEON_CP_RB_WPTR, 0);
180	WREG32(RADEON_CP_RB_CNTL, tmp);	197	WREG32(RADEON_CP_RB_CNTL, tmp);
181	// pci_save_state(rdev->pdev);	198	// pci_save_state(rdev->pdev);
182	/* disable bus mastering */	199	/* disable bus mastering */
183	rs600_bm_disable(rdev);	200	// pci_clear_master(rdev->pdev);
-		201	mdelay(1);
184	/* reset GA+VAP */	202	/* reset GA+VAP */
185	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) \|	203	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) \|
186	S_0000F0_SOFT_RESET_GA(1));	204	S_0000F0_SOFT_RESET_GA(1));
187	RREG32(R_0000F0_RBBM_SOFT_RESET);	205	RREG32(R_0000F0_RBBM_SOFT_RESET);
188	mdelay(500);	206	mdelay(500);
189	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);	207	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
190	mdelay(1);	208	mdelay(1);
191	status = RREG32(R_000E40_RBBM_STATUS);	209	status = RREG32(R_000E40_RBBM_STATUS);
192	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	210	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
193	/* reset CP */	211	/* reset CP */
194	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));	212	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
195	RREG32(R_0000F0_RBBM_SOFT_RESET);	213	RREG32(R_0000F0_RBBM_SOFT_RESET);
196	mdelay(500);	214	mdelay(500);
197	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);	215	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
198	mdelay(1);	216	mdelay(1);
199	status = RREG32(R_000E40_RBBM_STATUS);	217	status = RREG32(R_000E40_RBBM_STATUS);
200	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	218	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
201	/* reset MC */	219	/* reset MC */
202	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));	220	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
203	RREG32(R_0000F0_RBBM_SOFT_RESET);	221	RREG32(R_0000F0_RBBM_SOFT_RESET);
204	mdelay(500);	222	mdelay(500);
205	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);	223	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
206	mdelay(1);	224	mdelay(1);
207	status = RREG32(R_000E40_RBBM_STATUS);	225	status = RREG32(R_000E40_RBBM_STATUS);
208	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	226	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
209	/* restore PCI & busmastering */	227	/* restore PCI & busmastering */
210	// pci_restore_state(rdev->pdev);	228	// pci_restore_state(rdev->pdev);
211	/* Check if GPU is idle */	229	/* Check if GPU is idle */
212	if (G_000E40_GA_BUSY(status) \|\| G_000E40_VAP_BUSY(status)) {	230	if (G_000E40_GA_BUSY(status) \|\| G_000E40_VAP_BUSY(status)) {
213	dev_err(rdev->dev, "failed to reset GPU\n");	231	dev_err(rdev->dev, "failed to reset GPU\n");
214	rdev->gpu_lockup = true;	-
215	ret = -1;	232	ret = -1;
216	} else	233	} else
217	dev_info(rdev->dev, "GPU reset succeed\n");	234	dev_info(rdev->dev, "GPU reset succeed\n");
218	rv515_mc_resume(rdev, &save);	235	rv515_mc_resume(rdev, &save);
219	return ret;	236	return ret;
220	}	237	}
221		238
222	/*	239	/*
223	* GART.	240	* GART.
224	*/	241	*/
225	void rs600_gart_tlb_flush(struct radeon_device *rdev)	242	void rs600_gart_tlb_flush(struct radeon_device *rdev)
226	{	243	{
227	uint32_t tmp;	244	uint32_t tmp;
228		245
229	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	246	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
230	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;	247	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
231	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);	248	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
232		249
233	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	250	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
234	tmp \|= S_000100_INVALIDATE_ALL_L1_TLBS(1) \| S_000100_INVALIDATE_L2_CACHE(1);	251	tmp \|= S_000100_INVALIDATE_ALL_L1_TLBS(1) \| S_000100_INVALIDATE_L2_CACHE(1);
235	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);	252	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
236		253
237	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	254	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
238	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;	255	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
239	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);	256	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
240	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	257	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
241	}	258	}
242		259
243	int rs600_gart_init(struct radeon_device *rdev)	260	static int rs600_gart_init(struct radeon_device *rdev)
244	{	261	{
245	int r;	262	int r;
246		263
247	if (rdev->gart.table.vram.robj) {	264	if (rdev->gart.robj) {
248	WARN(1, "RS600 GART already initialized\n");	265	WARN(1, "RS600 GART already initialized\n");
249	return 0;	266	return 0;
250	}	267	}
251	/* Initialize common gart structure */	268	/* Initialize common gart structure */
252	r = radeon_gart_init(rdev);	269	r = radeon_gart_init(rdev);
253	if (r) {	270	if (r) {
254	return r;	271	return r;
255	}	272	}
256	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;	273	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
257	return radeon_gart_table_vram_alloc(rdev);	274	return radeon_gart_table_vram_alloc(rdev);
258	}	275	}
259		276
260	static int rs600_gart_enable(struct radeon_device *rdev)	277	static int rs600_gart_enable(struct radeon_device *rdev)
261	{	278	{
262	u32 tmp;	279	u32 tmp;
263	int r, i;	280	int r, i;
264		281
265	if (rdev->gart.table.vram.robj == NULL) {	282	if (rdev->gart.robj == NULL) {
266	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");	283	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
267	return -EINVAL;	284	return -EINVAL;
268	}	285	}
269	r = radeon_gart_table_vram_pin(rdev);	286	r = radeon_gart_table_vram_pin(rdev);
270	if (r)	287	if (r)
271	return r;	288	return r;
272	radeon_gart_restore(rdev);	289	radeon_gart_restore(rdev);
273	/* Enable bus master */	290	/* Enable bus master */
274	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;	291	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
275	WREG32(RADEON_BUS_CNTL, tmp);	292	WREG32(RADEON_BUS_CNTL, tmp);
276	/* FIXME: setup default page */	293	/* FIXME: setup default page */
277	WREG32_MC(R_000100_MC_PT0_CNTL,	294	WREG32_MC(R_000100_MC_PT0_CNTL,
278	(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) \|	295	(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) \|
279	S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));	296	S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
280		297
281	for (i = 0; i < 19; i++) {	298	for (i = 0; i < 19; i++) {
282	WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,	299	WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
283	S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) \|	300	S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) \|
284	S_00016C_SYSTEM_ACCESS_MODE_MASK(	301	S_00016C_SYSTEM_ACCESS_MODE_MASK(
285	V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) \|	302	V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) \|
286	S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(	303	S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
287	V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) \|	304	V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) \|
288	S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) \|	305	S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) \|
289	S_00016C_ENABLE_FRAGMENT_PROCESSING(1) \|	306	S_00016C_ENABLE_FRAGMENT_PROCESSING(1) \|
290	S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));	307	S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
291	}	308	}
292	/* enable first context */	309	/* enable first context */
293	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,	310	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
294	S_000102_ENABLE_PAGE_TABLE(1) \|	311	S_000102_ENABLE_PAGE_TABLE(1) \|
295	S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));	312	S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
296		313
297	/* disable all other contexts */	314	/* disable all other contexts */
298	for (i = 1; i < 8; i++)	315	for (i = 1; i < 8; i++)
299	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);	316	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
300		317
301	/* setup the page table */	318	/* setup the page table */
302	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,	319	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
303	rdev->gart.table_addr);	320	rdev->gart.table_addr);
304	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);	321	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
305	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);	322	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
306	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);	323	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
307		324
308	/* System context maps to VRAM space */	325	/* System context maps to VRAM space */
309	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);	326	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
310	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);	327	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
311		328
312	/* enable page tables */	329	/* enable page tables */
313	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	330	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
314	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp \| S_000100_ENABLE_PT(1)));	331	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp \| S_000100_ENABLE_PT(1)));
315	tmp = RREG32_MC(R_000009_MC_CNTL1);	332	tmp = RREG32_MC(R_000009_MC_CNTL1);
316	WREG32_MC(R_000009_MC_CNTL1, (tmp \| S_000009_ENABLE_PAGE_TABLES(1)));	333	WREG32_MC(R_000009_MC_CNTL1, (tmp \| S_000009_ENABLE_PAGE_TABLES(1)));
317	rs600_gart_tlb_flush(rdev);	334	rs600_gart_tlb_flush(rdev);
-		335	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
-		336	(unsigned)(rdev->mc.gtt_size >> 20),
-		337	(unsigned long long)rdev->gart.table_addr);
318	rdev->gart.ready = true;	338	rdev->gart.ready = true;
319	return 0;	339	return 0;
320	}	340	}
321		341
322	void rs600_gart_disable(struct radeon_device *rdev)	342	static void rs600_gart_disable(struct radeon_device *rdev)
323	{	343	{
324	u32 tmp;	-
325	int r;	344	u32 tmp;
326		345
327	/* FIXME: disable out of gart access */	346	/* FIXME: disable out of gart access */
328	WREG32_MC(R_000100_MC_PT0_CNTL, 0);	347	WREG32_MC(R_000100_MC_PT0_CNTL, 0);
329	tmp = RREG32_MC(R_000009_MC_CNTL1);	348	tmp = RREG32_MC(R_000009_MC_CNTL1);
330	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);	349	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
331	if (rdev->gart.table.vram.robj) {	350	radeon_gart_table_vram_unpin(rdev);
332	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);	-
333	if (r == 0) {	-
334	radeon_bo_kunmap(rdev->gart.table.vram.robj);	-
335	radeon_bo_unpin(rdev->gart.table.vram.robj);	-
336	radeon_bo_unreserve(rdev->gart.table.vram.robj);	-
337	}	-
338	}	-
339	}	351	}
340		352
341	void rs600_gart_fini(struct radeon_device *rdev)	353	static void rs600_gart_fini(struct radeon_device *rdev)
342	{	354	{
343	radeon_gart_fini(rdev);	355	radeon_gart_fini(rdev);
344	rs600_gart_disable(rdev);	356	rs600_gart_disable(rdev);
345	radeon_gart_table_vram_free(rdev);	357	radeon_gart_table_vram_free(rdev);
346	}	358	}
347		359
348	#define R600_PTE_VALID (1 << 0)	360	#define R600_PTE_VALID (1 << 0)
349	#define R600_PTE_SYSTEM (1 << 1)	361	#define R600_PTE_SYSTEM (1 << 1)
350	#define R600_PTE_SNOOPED (1 << 2)	362	#define R600_PTE_SNOOPED (1 << 2)
351	#define R600_PTE_READABLE (1 << 5)	363	#define R600_PTE_READABLE (1 << 5)
352	#define R600_PTE_WRITEABLE (1 << 6)	364	#define R600_PTE_WRITEABLE (1 << 6)
353		365
354	int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)	366	int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
355	{	367	{
356	void __iomem ptr = (void )rdev->gart.table.vram.ptr;	368	void __iomem ptr = (void )rdev->gart.ptr;
357		369
358	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {	370	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
359	return -EINVAL;	371	return -EINVAL;
360	}	372	}
361	addr = addr & 0xFFFFFFFFFFFFF000ULL;	373	addr = addr & 0xFFFFFFFFFFFFF000ULL;
362	addr \|= R600_PTE_VALID \| R600_PTE_SYSTEM \| R600_PTE_SNOOPED;	374	addr \|= R600_PTE_VALID \| R600_PTE_SYSTEM \| R600_PTE_SNOOPED;
363	addr \|= R600_PTE_READABLE \| R600_PTE_WRITEABLE;	375	addr \|= R600_PTE_READABLE \| R600_PTE_WRITEABLE;
364	writeq(addr, ptr + (i * 8));	376	writeq(addr, ptr + (i * 8));
365	return 0;	377	return 0;
366	}	378	}
367		379
368	int rs600_irq_set(struct radeon_device *rdev)	380	int rs600_irq_set(struct radeon_device *rdev)
369	{	381	{
370	uint32_t tmp = 0;	382	uint32_t tmp = 0;
371	uint32_t mode_int = 0;	383	uint32_t mode_int = 0;
372	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &	384	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
373	~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);	385	~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
374	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &	386	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
375	~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);	387	~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
-		388	u32 hdmi0;
-		389	if (ASIC_IS_DCE2(rdev))
-		390	hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
-		391	~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
-		392	else
-		393	hdmi0 = 0;
376		394
377	if (!rdev->irq.installed) {	395	if (!rdev->irq.installed) {
378	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");	396	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
379	WREG32(R_000040_GEN_INT_CNTL, 0);	397	WREG32(R_000040_GEN_INT_CNTL, 0);
380	return -EINVAL;	398	return -EINVAL;
381	}	399	}
382	if (rdev->irq.sw_int) {	400	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
383	tmp \|= S_000040_SW_INT_EN(1);	401	tmp \|= S_000040_SW_INT_EN(1);
384	}	402	}
385	if (rdev->irq.gui_idle) {	-
386	tmp \|= S_000040_GUI_IDLE(1);	-
387	}	-
388	if (rdev->irq.crtc_vblank_int[0] \|\|	403	if (rdev->irq.crtc_vblank_int[0] \|\|
389	rdev->irq.pflip[0]) {	404	atomic_read(&rdev->irq.pflip[0])) {
390	mode_int \|= S_006540_D1MODE_VBLANK_INT_MASK(1);	405	mode_int \|= S_006540_D1MODE_VBLANK_INT_MASK(1);
391	}	406	}
392	if (rdev->irq.crtc_vblank_int[1] \|\|	407	if (rdev->irq.crtc_vblank_int[1] \|\|
393	rdev->irq.pflip[1]) {	408	atomic_read(&rdev->irq.pflip[1])) {
394	mode_int \|= S_006540_D2MODE_VBLANK_INT_MASK(1);	409	mode_int \|= S_006540_D2MODE_VBLANK_INT_MASK(1);
395	}	410	}
396	if (rdev->irq.hpd[0]) {	411	if (rdev->irq.hpd[0]) {
397	hpd1 \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);	412	hpd1 \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
398	}	413	}
399	if (rdev->irq.hpd[1]) {	414	if (rdev->irq.hpd[1]) {
400	hpd2 \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);	415	hpd2 \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
401	}	416	}
-		417	if (rdev->irq.afmt[0]) {
-		418	hdmi0 \|= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
-		419	}
402	WREG32(R_000040_GEN_INT_CNTL, tmp);	420	WREG32(R_000040_GEN_INT_CNTL, tmp);
403	WREG32(R_006540_DxMODE_INT_MASK, mode_int);	421	WREG32(R_006540_DxMODE_INT_MASK, mode_int);
404	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);	422	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
405	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);	423	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
-		424	if (ASIC_IS_DCE2(rdev))
-		425	WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
406	return 0;	426	return 0;
407	}	427	}
408		428
409	static inline u32 rs600_irq_ack(struct radeon_device *rdev)	429	static inline u32 rs600_irq_ack(struct radeon_device *rdev)
410	{	430	{
411	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);	431	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
412	uint32_t irq_mask = S_000044_SW_INT(1);	432	uint32_t irq_mask = S_000044_SW_INT(1);
413	u32 tmp;	433	u32 tmp;
414		-
415	/* the interrupt works, but the status bit is permanently asserted */	-
416	if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {	-
417	if (!rdev->irq.gui_idle_acked)	-
418	irq_mask \|= S_000044_GUI_IDLE_STAT(1);	-
419	}	-
420		434
421	if (G_000044_DISPLAY_INT_STAT(irqs)) {	435	if (G_000044_DISPLAY_INT_STAT(irqs)) {
422	rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);	436	rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
423	if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	437	if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
424	WREG32(R_006534_D1MODE_VBLANK_STATUS,	438	WREG32(R_006534_D1MODE_VBLANK_STATUS,
425	S_006534_D1MODE_VBLANK_ACK(1));	439	S_006534_D1MODE_VBLANK_ACK(1));
426	}	440	}
427	if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	441	if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
428	WREG32(R_006D34_D2MODE_VBLANK_STATUS,	442	WREG32(R_006D34_D2MODE_VBLANK_STATUS,
429	S_006D34_D2MODE_VBLANK_ACK(1));	443	S_006D34_D2MODE_VBLANK_ACK(1));
430	}	444	}
431	if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	445	if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
432	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);	446	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
433	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);	447	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
434	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);	448	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
435	}	449	}
436	if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	450	if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
437	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);	451	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
438	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);	452	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
439	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);	453	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
440	}	454	}
441	} else {	455	} else {
442	rdev->irq.stat_regs.r500.disp_int = 0;	456	rdev->irq.stat_regs.r500.disp_int = 0;
443	}	457	}
-		458
-		459	if (ASIC_IS_DCE2(rdev)) {
-		460	rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
-		461	S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
-		462	if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
-		463	tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
-		464	tmp \|= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
-		465	WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
-		466	}
-		467	} else
-		468	rdev->irq.stat_regs.r500.hdmi0_status = 0;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/rs600.c – Rev 2160 → 2997