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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | //#include |
28 | //#include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | #include "radeon_reg.h" |
33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
34 | #include "radeon.h" |
35 | #include "atom.h" |
35 | #include "atom.h" |
36 | 36 | ||
37 | #include "bitmap.h" |
37 | #include "bitmap.h" |
38 | #include "display.h" |
38 | #include "display.h" |
39 | 39 | ||
40 | 40 | ||
41 | #include |
41 | #include |
42 | 42 | ||
43 | #define PCI_VENDOR_ID_ATI 0x1002 |
43 | #define PCI_VENDOR_ID_ATI 0x1002 |
44 | #define PCI_VENDOR_ID_APPLE 0x106b |
44 | #define PCI_VENDOR_ID_APPLE 0x106b |
45 | 45 | ||
46 | int radeon_no_wb; |
46 | int radeon_no_wb; |
47 | int radeon_modeset = -1; |
47 | int radeon_modeset = -1; |
48 | int radeon_dynclks = -1; |
48 | int radeon_dynclks = -1; |
49 | int radeon_r4xx_atom = 0; |
49 | int radeon_r4xx_atom = 0; |
50 | int radeon_agpmode = 0; |
50 | int radeon_agpmode = 0; |
51 | int radeon_vram_limit = 0; |
51 | int radeon_vram_limit = 0; |
52 | int radeon_gart_size = -1; /* auto */ |
52 | int radeon_gart_size = -1; /* auto */ |
53 | int radeon_benchmarking = 0; |
53 | int radeon_benchmarking = 0; |
54 | int radeon_testing = 0; |
54 | int radeon_testing = 0; |
55 | int radeon_connector_table = 0; |
55 | int radeon_connector_table = 0; |
56 | int radeon_tv = 1; |
56 | int radeon_tv = 1; |
57 | int radeon_audio = -1; |
57 | int radeon_audio = -1; |
58 | int radeon_disp_priority = 0; |
58 | int radeon_disp_priority = 0; |
59 | int radeon_hw_i2c = 0; |
59 | int radeon_hw_i2c = 0; |
60 | int radeon_pcie_gen2 = -1; |
60 | int radeon_pcie_gen2 = -1; |
61 | int radeon_msi = -1; |
61 | int radeon_msi = -1; |
62 | int radeon_lockup_timeout = 10000; |
62 | int radeon_lockup_timeout = 10000; |
63 | int radeon_fastfb = 0; |
63 | int radeon_fastfb = 0; |
64 | int radeon_dpm = -1; |
64 | int radeon_dpm = -1; |
65 | int radeon_aspm = -1; |
65 | int radeon_aspm = -1; |
66 | int radeon_runtime_pm = -1; |
66 | int radeon_runtime_pm = -1; |
67 | int radeon_hard_reset = 0; |
67 | int radeon_hard_reset = 0; |
68 | int radeon_vm_size = 8; |
68 | int radeon_vm_size = 8; |
69 | int radeon_vm_block_size = -1; |
69 | int radeon_vm_block_size = -1; |
70 | int radeon_deep_color = 0; |
70 | int radeon_deep_color = 0; |
71 | int radeon_use_pflipirq = 2; |
71 | int radeon_use_pflipirq = 2; |
72 | int irq_override = 0; |
72 | int irq_override = 0; |
73 | int radeon_bapm = -1; |
73 | int radeon_bapm = -1; |
74 | - | ||
- | 74 | int radeon_backlight = 0; |
|
75 | 75 | ||
76 | extern display_t *os_display; |
76 | extern display_t *os_display; |
77 | extern struct drm_device *main_device; |
77 | extern struct drm_device *main_device; |
78 | extern videomode_t usermode; |
78 | extern videomode_t usermode; |
79 | 79 | ||
80 | 80 | ||
81 | void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms); |
81 | void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms); |
82 | int init_display(struct radeon_device *rdev, videomode_t *mode); |
82 | int init_display(struct radeon_device *rdev, videomode_t *mode); |
83 | int init_display_kms(struct drm_device *dev, videomode_t *usermode); |
83 | int init_display_kms(struct drm_device *dev, videomode_t *usermode); |
84 | 84 | ||
85 | int get_modes(videomode_t *mode, u32_t *count); |
85 | int get_modes(videomode_t *mode, u32_t *count); |
86 | int set_user_mode(videomode_t *mode); |
86 | int set_user_mode(videomode_t *mode); |
87 | int r100_2D_test(struct radeon_device *rdev); |
87 | int r100_2D_test(struct radeon_device *rdev); |
88 | 88 | ||
89 | 89 | ||
90 | /* Legacy VGA regions */ |
90 | /* Legacy VGA regions */ |
91 | #define VGA_RSRC_NONE 0x00 |
91 | #define VGA_RSRC_NONE 0x00 |
92 | #define VGA_RSRC_LEGACY_IO 0x01 |
92 | #define VGA_RSRC_LEGACY_IO 0x01 |
93 | #define VGA_RSRC_LEGACY_MEM 0x02 |
93 | #define VGA_RSRC_LEGACY_MEM 0x02 |
94 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
94 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
95 | /* Non-legacy access */ |
95 | /* Non-legacy access */ |
96 | #define VGA_RSRC_NORMAL_IO 0x04 |
96 | #define VGA_RSRC_NORMAL_IO 0x04 |
97 | #define VGA_RSRC_NORMAL_MEM 0x08 |
97 | #define VGA_RSRC_NORMAL_MEM 0x08 |
98 | 98 | ||
99 | 99 | ||
100 | static const char radeon_family_name[][16] = { |
100 | static const char radeon_family_name[][16] = { |
101 | "R100", |
101 | "R100", |
102 | "RV100", |
102 | "RV100", |
103 | "RS100", |
103 | "RS100", |
104 | "RV200", |
104 | "RV200", |
105 | "RS200", |
105 | "RS200", |
106 | "R200", |
106 | "R200", |
107 | "RV250", |
107 | "RV250", |
108 | "RS300", |
108 | "RS300", |
109 | "RV280", |
109 | "RV280", |
110 | "R300", |
110 | "R300", |
111 | "R350", |
111 | "R350", |
112 | "RV350", |
112 | "RV350", |
113 | "RV380", |
113 | "RV380", |
114 | "R420", |
114 | "R420", |
115 | "R423", |
115 | "R423", |
116 | "RV410", |
116 | "RV410", |
117 | "RS400", |
117 | "RS400", |
118 | "RS480", |
118 | "RS480", |
119 | "RS600", |
119 | "RS600", |
120 | "RS690", |
120 | "RS690", |
121 | "RS740", |
121 | "RS740", |
122 | "RV515", |
122 | "RV515", |
123 | "R520", |
123 | "R520", |
124 | "RV530", |
124 | "RV530", |
125 | "RV560", |
125 | "RV560", |
126 | "RV570", |
126 | "RV570", |
127 | "R580", |
127 | "R580", |
128 | "R600", |
128 | "R600", |
129 | "RV610", |
129 | "RV610", |
130 | "RV630", |
130 | "RV630", |
131 | "RV670", |
131 | "RV670", |
132 | "RV620", |
132 | "RV620", |
133 | "RV635", |
133 | "RV635", |
134 | "RS780", |
134 | "RS780", |
135 | "RS880", |
135 | "RS880", |
136 | "RV770", |
136 | "RV770", |
137 | "RV730", |
137 | "RV730", |
138 | "RV710", |
138 | "RV710", |
139 | "RV740", |
139 | "RV740", |
140 | "CEDAR", |
140 | "CEDAR", |
141 | "REDWOOD", |
141 | "REDWOOD", |
142 | "JUNIPER", |
142 | "JUNIPER", |
143 | "CYPRESS", |
143 | "CYPRESS", |
144 | "HEMLOCK", |
144 | "HEMLOCK", |
145 | "PALM", |
145 | "PALM", |
146 | "SUMO", |
146 | "SUMO", |
147 | "SUMO2", |
147 | "SUMO2", |
148 | "BARTS", |
148 | "BARTS", |
149 | "TURKS", |
149 | "TURKS", |
150 | "CAICOS", |
150 | "CAICOS", |
151 | "CAYMAN", |
151 | "CAYMAN", |
152 | "ARUBA", |
152 | "ARUBA", |
153 | "TAHITI", |
153 | "TAHITI", |
154 | "PITCAIRN", |
154 | "PITCAIRN", |
155 | "VERDE", |
155 | "VERDE", |
156 | "OLAND", |
156 | "OLAND", |
157 | "HAINAN", |
157 | "HAINAN", |
158 | "BONAIRE", |
158 | "BONAIRE", |
159 | "KAVERI", |
159 | "KAVERI", |
160 | "KABINI", |
160 | "KABINI", |
161 | "HAWAII", |
161 | "HAWAII", |
162 | "MULLINS", |
162 | "MULLINS", |
163 | "LAST", |
163 | "LAST", |
164 | }; |
164 | }; |
165 | 165 | ||
166 | #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) |
166 | #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) |
167 | #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) |
167 | #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) |
168 | 168 | ||
169 | struct radeon_px_quirk { |
169 | struct radeon_px_quirk { |
170 | u32 chip_vendor; |
170 | u32 chip_vendor; |
171 | u32 chip_device; |
171 | u32 chip_device; |
172 | u32 subsys_vendor; |
172 | u32 subsys_vendor; |
173 | u32 subsys_device; |
173 | u32 subsys_device; |
174 | u32 px_quirk_flags; |
174 | u32 px_quirk_flags; |
175 | }; |
175 | }; |
176 | 176 | ||
177 | static struct radeon_px_quirk radeon_px_quirk_list[] = { |
177 | static struct radeon_px_quirk radeon_px_quirk_list[] = { |
178 | /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) |
178 | /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) |
179 | * https://bugzilla.kernel.org/show_bug.cgi?id=74551 |
179 | * https://bugzilla.kernel.org/show_bug.cgi?id=74551 |
180 | */ |
180 | */ |
181 | { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, |
181 | { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, |
182 | /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU |
182 | /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU |
183 | * https://bugzilla.kernel.org/show_bug.cgi?id=51381 |
183 | * https://bugzilla.kernel.org/show_bug.cgi?id=51381 |
184 | */ |
184 | */ |
185 | { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, |
185 | { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, |
- | 186 | /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU |
|
- | 187 | * https://bugzilla.kernel.org/show_bug.cgi?id=51381 |
|
- | 188 | */ |
|
- | 189 | { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, |
|
186 | /* macbook pro 8.2 */ |
190 | /* macbook pro 8.2 */ |
187 | { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, |
191 | { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, |
188 | { 0, 0, 0, 0, 0 }, |
192 | { 0, 0, 0, 0, 0 }, |
189 | }; |
193 | }; |
190 | 194 | ||
191 | bool radeon_is_px(struct drm_device *dev) |
195 | bool radeon_is_px(struct drm_device *dev) |
192 | { |
196 | { |
193 | struct radeon_device *rdev = dev->dev_private; |
197 | struct radeon_device *rdev = dev->dev_private; |
194 | 198 | ||
195 | if (rdev->flags & RADEON_IS_PX) |
199 | if (rdev->flags & RADEON_IS_PX) |
196 | return true; |
200 | return true; |
197 | return false; |
201 | return false; |
198 | } |
202 | } |
199 | 203 | ||
200 | static void radeon_device_handle_px_quirks(struct radeon_device *rdev) |
204 | static void radeon_device_handle_px_quirks(struct radeon_device *rdev) |
201 | { |
205 | { |
202 | struct radeon_px_quirk *p = radeon_px_quirk_list; |
206 | struct radeon_px_quirk *p = radeon_px_quirk_list; |
203 | 207 | ||
204 | /* Apply PX quirks */ |
208 | /* Apply PX quirks */ |
205 | while (p && p->chip_device != 0) { |
209 | while (p && p->chip_device != 0) { |
206 | if (rdev->pdev->vendor == p->chip_vendor && |
210 | if (rdev->pdev->vendor == p->chip_vendor && |
207 | rdev->pdev->device == p->chip_device && |
211 | rdev->pdev->device == p->chip_device && |
208 | rdev->pdev->subsystem_vendor == p->subsys_vendor && |
212 | rdev->pdev->subsystem_vendor == p->subsys_vendor && |
209 | rdev->pdev->subsystem_device == p->subsys_device) { |
213 | rdev->pdev->subsystem_device == p->subsys_device) { |
210 | rdev->px_quirk_flags = p->px_quirk_flags; |
214 | rdev->px_quirk_flags = p->px_quirk_flags; |
211 | break; |
215 | break; |
212 | } |
216 | } |
213 | ++p; |
217 | ++p; |
214 | } |
218 | } |
215 | 219 | ||
216 | if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) |
220 | if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) |
217 | rdev->flags &= ~RADEON_IS_PX; |
221 | rdev->flags &= ~RADEON_IS_PX; |
218 | } |
222 | } |
219 | 223 | ||
220 | /** |
224 | /** |
221 | * radeon_program_register_sequence - program an array of registers. |
225 | * radeon_program_register_sequence - program an array of registers. |
222 | * |
226 | * |
223 | * @rdev: radeon_device pointer |
227 | * @rdev: radeon_device pointer |
224 | * @registers: pointer to the register array |
228 | * @registers: pointer to the register array |
225 | * @array_size: size of the register array |
229 | * @array_size: size of the register array |
226 | * |
230 | * |
227 | * Programs an array or registers with and and or masks. |
231 | * Programs an array or registers with and and or masks. |
228 | * This is a helper for setting golden registers. |
232 | * This is a helper for setting golden registers. |
229 | */ |
233 | */ |
230 | void radeon_program_register_sequence(struct radeon_device *rdev, |
234 | void radeon_program_register_sequence(struct radeon_device *rdev, |
231 | const u32 *registers, |
235 | const u32 *registers, |
232 | const u32 array_size) |
236 | const u32 array_size) |
233 | { |
237 | { |
234 | u32 tmp, reg, and_mask, or_mask; |
238 | u32 tmp, reg, and_mask, or_mask; |
235 | int i; |
239 | int i; |
236 | 240 | ||
237 | if (array_size % 3) |
241 | if (array_size % 3) |
238 | return; |
242 | return; |
239 | 243 | ||
240 | for (i = 0; i < array_size; i +=3) { |
244 | for (i = 0; i < array_size; i +=3) { |
241 | reg = registers[i + 0]; |
245 | reg = registers[i + 0]; |
242 | and_mask = registers[i + 1]; |
246 | and_mask = registers[i + 1]; |
243 | or_mask = registers[i + 2]; |
247 | or_mask = registers[i + 2]; |
244 | 248 | ||
245 | if (and_mask == 0xffffffff) { |
249 | if (and_mask == 0xffffffff) { |
246 | tmp = or_mask; |
250 | tmp = or_mask; |
247 | } else { |
251 | } else { |
248 | tmp = RREG32(reg); |
252 | tmp = RREG32(reg); |
249 | tmp &= ~and_mask; |
253 | tmp &= ~and_mask; |
250 | tmp |= or_mask; |
254 | tmp |= or_mask; |
251 | } |
255 | } |
252 | WREG32(reg, tmp); |
256 | WREG32(reg, tmp); |
253 | } |
257 | } |
254 | } |
258 | } |
255 | 259 | ||
256 | void radeon_pci_config_reset(struct radeon_device *rdev) |
260 | void radeon_pci_config_reset(struct radeon_device *rdev) |
257 | { |
261 | { |
258 | pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); |
262 | pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); |
259 | } |
263 | } |
260 | 264 | ||
261 | /** |
265 | /** |
262 | * radeon_surface_init - Clear GPU surface registers. |
266 | * radeon_surface_init - Clear GPU surface registers. |
263 | * |
267 | * |
264 | * @rdev: radeon_device pointer |
268 | * @rdev: radeon_device pointer |
265 | * |
269 | * |
266 | * Clear GPU surface registers (r1xx-r5xx). |
270 | * Clear GPU surface registers (r1xx-r5xx). |
267 | */ |
271 | */ |
268 | void radeon_surface_init(struct radeon_device *rdev) |
272 | void radeon_surface_init(struct radeon_device *rdev) |
269 | { |
273 | { |
270 | /* FIXME: check this out */ |
274 | /* FIXME: check this out */ |
271 | if (rdev->family < CHIP_R600) { |
275 | if (rdev->family < CHIP_R600) { |
272 | int i; |
276 | int i; |
273 | 277 | ||
274 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
278 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
275 | if (rdev->surface_regs[i].bo) |
279 | if (rdev->surface_regs[i].bo) |
276 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); |
280 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); |
277 | else |
281 | else |
278 | radeon_clear_surface_reg(rdev, i); |
282 | radeon_clear_surface_reg(rdev, i); |
279 | } |
283 | } |
280 | /* enable surfaces */ |
284 | /* enable surfaces */ |
281 | WREG32(RADEON_SURFACE_CNTL, 0); |
285 | WREG32(RADEON_SURFACE_CNTL, 0); |
282 | } |
286 | } |
283 | } |
287 | } |
284 | 288 | ||
285 | /* |
289 | /* |
286 | * GPU scratch registers helpers function. |
290 | * GPU scratch registers helpers function. |
287 | */ |
291 | */ |
288 | /** |
292 | /** |
289 | * radeon_scratch_init - Init scratch register driver information. |
293 | * radeon_scratch_init - Init scratch register driver information. |
290 | * |
294 | * |
291 | * @rdev: radeon_device pointer |
295 | * @rdev: radeon_device pointer |
292 | * |
296 | * |
293 | * Init CP scratch register driver information (r1xx-r5xx) |
297 | * Init CP scratch register driver information (r1xx-r5xx) |
294 | */ |
298 | */ |
295 | void radeon_scratch_init(struct radeon_device *rdev) |
299 | void radeon_scratch_init(struct radeon_device *rdev) |
296 | { |
300 | { |
297 | int i; |
301 | int i; |
298 | 302 | ||
299 | /* FIXME: check this out */ |
303 | /* FIXME: check this out */ |
300 | if (rdev->family < CHIP_R300) { |
304 | if (rdev->family < CHIP_R300) { |
301 | rdev->scratch.num_reg = 5; |
305 | rdev->scratch.num_reg = 5; |
302 | } else { |
306 | } else { |
303 | rdev->scratch.num_reg = 7; |
307 | rdev->scratch.num_reg = 7; |
304 | } |
308 | } |
305 | rdev->scratch.reg_base = RADEON_SCRATCH_REG0; |
309 | rdev->scratch.reg_base = RADEON_SCRATCH_REG0; |
306 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
310 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
307 | rdev->scratch.free[i] = true; |
311 | rdev->scratch.free[i] = true; |
308 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
312 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
309 | } |
313 | } |
310 | } |
314 | } |
311 | 315 | ||
312 | /** |
316 | /** |
313 | * radeon_scratch_get - Allocate a scratch register |
317 | * radeon_scratch_get - Allocate a scratch register |
314 | * |
318 | * |
315 | * @rdev: radeon_device pointer |
319 | * @rdev: radeon_device pointer |
316 | * @reg: scratch register mmio offset |
320 | * @reg: scratch register mmio offset |
317 | * |
321 | * |
318 | * Allocate a CP scratch register for use by the driver (all asics). |
322 | * Allocate a CP scratch register for use by the driver (all asics). |
319 | * Returns 0 on success or -EINVAL on failure. |
323 | * Returns 0 on success or -EINVAL on failure. |
320 | */ |
324 | */ |
321 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
325 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
322 | { |
326 | { |
323 | int i; |
327 | int i; |
324 | 328 | ||
325 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
329 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
326 | if (rdev->scratch.free[i]) { |
330 | if (rdev->scratch.free[i]) { |
327 | rdev->scratch.free[i] = false; |
331 | rdev->scratch.free[i] = false; |
328 | *reg = rdev->scratch.reg[i]; |
332 | *reg = rdev->scratch.reg[i]; |
329 | return 0; |
333 | return 0; |
330 | } |
334 | } |
331 | } |
335 | } |
332 | return -EINVAL; |
336 | return -EINVAL; |
333 | } |
337 | } |
334 | 338 | ||
335 | /** |
339 | /** |
336 | * radeon_scratch_free - Free a scratch register |
340 | * radeon_scratch_free - Free a scratch register |
337 | * |
341 | * |
338 | * @rdev: radeon_device pointer |
342 | * @rdev: radeon_device pointer |
339 | * @reg: scratch register mmio offset |
343 | * @reg: scratch register mmio offset |
340 | * |
344 | * |
341 | * Free a CP scratch register allocated for use by the driver (all asics) |
345 | * Free a CP scratch register allocated for use by the driver (all asics) |
342 | */ |
346 | */ |
343 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
347 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
344 | { |
348 | { |
345 | int i; |
349 | int i; |
346 | 350 | ||
347 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
351 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
348 | if (rdev->scratch.reg[i] == reg) { |
352 | if (rdev->scratch.reg[i] == reg) { |
349 | rdev->scratch.free[i] = true; |
353 | rdev->scratch.free[i] = true; |
350 | return; |
354 | return; |
351 | } |
355 | } |
352 | } |
356 | } |
353 | } |
357 | } |
354 | 358 | ||
355 | /* |
359 | /* |
356 | * GPU doorbell aperture helpers function. |
360 | * GPU doorbell aperture helpers function. |
357 | */ |
361 | */ |
358 | /** |
362 | /** |
359 | * radeon_doorbell_init - Init doorbell driver information. |
363 | * radeon_doorbell_init - Init doorbell driver information. |
360 | * |
364 | * |
361 | * @rdev: radeon_device pointer |
365 | * @rdev: radeon_device pointer |
362 | * |
366 | * |
363 | * Init doorbell driver information (CIK) |
367 | * Init doorbell driver information (CIK) |
364 | * Returns 0 on success, error on failure. |
368 | * Returns 0 on success, error on failure. |
365 | */ |
369 | */ |
366 | static int radeon_doorbell_init(struct radeon_device *rdev) |
370 | static int radeon_doorbell_init(struct radeon_device *rdev) |
367 | { |
371 | { |
368 | /* doorbell bar mapping */ |
372 | /* doorbell bar mapping */ |
369 | rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); |
373 | rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); |
370 | rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); |
374 | rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); |
371 | 375 | ||
372 | rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); |
376 | rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); |
373 | if (rdev->doorbell.num_doorbells == 0) |
377 | if (rdev->doorbell.num_doorbells == 0) |
374 | return -EINVAL; |
378 | return -EINVAL; |
375 | 379 | ||
376 | rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); |
380 | rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); |
377 | if (rdev->doorbell.ptr == NULL) { |
381 | if (rdev->doorbell.ptr == NULL) { |
378 | return -ENOMEM; |
382 | return -ENOMEM; |
379 | } |
383 | } |
380 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); |
384 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); |
381 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); |
385 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); |
382 | 386 | ||
383 | memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); |
387 | memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); |
384 | 388 | ||
385 | return 0; |
389 | return 0; |
386 | } |
390 | } |
387 | 391 | ||
388 | /** |
392 | /** |
389 | * radeon_doorbell_fini - Tear down doorbell driver information. |
393 | * radeon_doorbell_fini - Tear down doorbell driver information. |
390 | * |
394 | * |
391 | * @rdev: radeon_device pointer |
395 | * @rdev: radeon_device pointer |
392 | * |
396 | * |
393 | * Tear down doorbell driver information (CIK) |
397 | * Tear down doorbell driver information (CIK) |
394 | */ |
398 | */ |
395 | static void radeon_doorbell_fini(struct radeon_device *rdev) |
399 | static void radeon_doorbell_fini(struct radeon_device *rdev) |
396 | { |
400 | { |
397 | iounmap(rdev->doorbell.ptr); |
401 | iounmap(rdev->doorbell.ptr); |
398 | rdev->doorbell.ptr = NULL; |
402 | rdev->doorbell.ptr = NULL; |
399 | } |
403 | } |
400 | 404 | ||
401 | /** |
405 | /** |
402 | * radeon_doorbell_get - Allocate a doorbell entry |
406 | * radeon_doorbell_get - Allocate a doorbell entry |
403 | * |
407 | * |
404 | * @rdev: radeon_device pointer |
408 | * @rdev: radeon_device pointer |
405 | * @doorbell: doorbell index |
409 | * @doorbell: doorbell index |
406 | * |
410 | * |
407 | * Allocate a doorbell for use by the driver (all asics). |
411 | * Allocate a doorbell for use by the driver (all asics). |
408 | * Returns 0 on success or -EINVAL on failure. |
412 | * Returns 0 on success or -EINVAL on failure. |
409 | */ |
413 | */ |
410 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) |
414 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) |
411 | { |
415 | { |
412 | unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); |
416 | unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); |
413 | if (offset < rdev->doorbell.num_doorbells) { |
417 | if (offset < rdev->doorbell.num_doorbells) { |
414 | __set_bit(offset, rdev->doorbell.used); |
418 | __set_bit(offset, rdev->doorbell.used); |
415 | *doorbell = offset; |
419 | *doorbell = offset; |
416 | return 0; |
420 | return 0; |
417 | } else { |
421 | } else { |
418 | return -EINVAL; |
422 | return -EINVAL; |
419 | } |
423 | } |
420 | } |
424 | } |
421 | 425 | ||
422 | /** |
426 | /** |
423 | * radeon_doorbell_free - Free a doorbell entry |
427 | * radeon_doorbell_free - Free a doorbell entry |
424 | * |
428 | * |
425 | * @rdev: radeon_device pointer |
429 | * @rdev: radeon_device pointer |
426 | * @doorbell: doorbell index |
430 | * @doorbell: doorbell index |
427 | * |
431 | * |
428 | * Free a doorbell allocated for use by the driver (all asics) |
432 | * Free a doorbell allocated for use by the driver (all asics) |
429 | */ |
433 | */ |
430 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) |
434 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) |
431 | { |
435 | { |
432 | if (doorbell < rdev->doorbell.num_doorbells) |
436 | if (doorbell < rdev->doorbell.num_doorbells) |
433 | __clear_bit(doorbell, rdev->doorbell.used); |
437 | __clear_bit(doorbell, rdev->doorbell.used); |
434 | } |
438 | } |
435 | 439 | ||
436 | /* |
440 | /* |
437 | * radeon_wb_*() |
441 | * radeon_wb_*() |
438 | * Writeback is the the method by which the the GPU updates special pages |
442 | * Writeback is the the method by which the the GPU updates special pages |
439 | * in memory with the status of certain GPU events (fences, ring pointers, |
443 | * in memory with the status of certain GPU events (fences, ring pointers, |
440 | * etc.). |
444 | * etc.). |
441 | */ |
445 | */ |
442 | 446 | ||
443 | /** |
447 | /** |
444 | * radeon_wb_disable - Disable Writeback |
448 | * radeon_wb_disable - Disable Writeback |
445 | * |
449 | * |
446 | * @rdev: radeon_device pointer |
450 | * @rdev: radeon_device pointer |
447 | * |
451 | * |
448 | * Disables Writeback (all asics). Used for suspend. |
452 | * Disables Writeback (all asics). Used for suspend. |
449 | */ |
453 | */ |
450 | void radeon_wb_disable(struct radeon_device *rdev) |
454 | void radeon_wb_disable(struct radeon_device *rdev) |
451 | { |
455 | { |
452 | rdev->wb.enabled = false; |
456 | rdev->wb.enabled = false; |
453 | } |
457 | } |
454 | 458 | ||
455 | /** |
459 | /** |
456 | * radeon_wb_fini - Disable Writeback and free memory |
460 | * radeon_wb_fini - Disable Writeback and free memory |
457 | * |
461 | * |
458 | * @rdev: radeon_device pointer |
462 | * @rdev: radeon_device pointer |
459 | * |
463 | * |
460 | * Disables Writeback and frees the Writeback memory (all asics). |
464 | * Disables Writeback and frees the Writeback memory (all asics). |
461 | * Used at driver shutdown. |
465 | * Used at driver shutdown. |
462 | */ |
466 | */ |
463 | void radeon_wb_fini(struct radeon_device *rdev) |
467 | void radeon_wb_fini(struct radeon_device *rdev) |
464 | { |
468 | { |
465 | radeon_wb_disable(rdev); |
469 | radeon_wb_disable(rdev); |
466 | if (rdev->wb.wb_obj) { |
470 | if (rdev->wb.wb_obj) { |
467 | if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { |
471 | if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { |
468 | radeon_bo_kunmap(rdev->wb.wb_obj); |
472 | radeon_bo_kunmap(rdev->wb.wb_obj); |
469 | radeon_bo_unpin(rdev->wb.wb_obj); |
473 | radeon_bo_unpin(rdev->wb.wb_obj); |
470 | radeon_bo_unreserve(rdev->wb.wb_obj); |
474 | radeon_bo_unreserve(rdev->wb.wb_obj); |
471 | } |
475 | } |
472 | radeon_bo_unref(&rdev->wb.wb_obj); |
476 | radeon_bo_unref(&rdev->wb.wb_obj); |
473 | rdev->wb.wb = NULL; |
477 | rdev->wb.wb = NULL; |
474 | rdev->wb.wb_obj = NULL; |
478 | rdev->wb.wb_obj = NULL; |
475 | } |
479 | } |
476 | } |
480 | } |
477 | 481 | ||
478 | /** |
482 | /** |
479 | * radeon_wb_init- Init Writeback driver info and allocate memory |
483 | * radeon_wb_init- Init Writeback driver info and allocate memory |
480 | * |
484 | * |
481 | * @rdev: radeon_device pointer |
485 | * @rdev: radeon_device pointer |
482 | * |
486 | * |
483 | * Disables Writeback and frees the Writeback memory (all asics). |
487 | * Disables Writeback and frees the Writeback memory (all asics). |
484 | * Used at driver startup. |
488 | * Used at driver startup. |
485 | * Returns 0 on success or an -error on failure. |
489 | * Returns 0 on success or an -error on failure. |
486 | */ |
490 | */ |
487 | int radeon_wb_init(struct radeon_device *rdev) |
491 | int radeon_wb_init(struct radeon_device *rdev) |
488 | { |
492 | { |
489 | int r; |
493 | int r; |
490 | 494 | ||
491 | if (rdev->wb.wb_obj == NULL) { |
495 | if (rdev->wb.wb_obj == NULL) { |
492 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, |
496 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, |
493 | RADEON_GEM_DOMAIN_GTT, 0, NULL, |
497 | RADEON_GEM_DOMAIN_GTT, 0, NULL, |
494 | &rdev->wb.wb_obj); |
498 | &rdev->wb.wb_obj); |
495 | if (r) { |
499 | if (r) { |
496 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
500 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
497 | return r; |
501 | return r; |
498 | } |
502 | } |
499 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
503 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
500 | if (unlikely(r != 0)) { |
504 | if (unlikely(r != 0)) { |
501 | radeon_wb_fini(rdev); |
505 | radeon_wb_fini(rdev); |
502 | return r; |
506 | return r; |
503 | } |
507 | } |
504 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
508 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
505 | &rdev->wb.gpu_addr); |
509 | &rdev->wb.gpu_addr); |
506 | if (r) { |
510 | if (r) { |
507 | radeon_bo_unreserve(rdev->wb.wb_obj); |
511 | radeon_bo_unreserve(rdev->wb.wb_obj); |
508 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); |
512 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); |
509 | radeon_wb_fini(rdev); |
513 | radeon_wb_fini(rdev); |
510 | return r; |
514 | return r; |
511 | } |
515 | } |
512 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
516 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
513 | radeon_bo_unreserve(rdev->wb.wb_obj); |
517 | radeon_bo_unreserve(rdev->wb.wb_obj); |
514 | if (r) { |
518 | if (r) { |
515 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
519 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
516 | radeon_wb_fini(rdev); |
520 | radeon_wb_fini(rdev); |
517 | return r; |
521 | return r; |
518 | } |
522 | } |
519 | } |
523 | } |
520 | 524 | ||
521 | /* clear wb memory */ |
525 | /* clear wb memory */ |
522 | memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); |
526 | memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); |
523 | /* disable event_write fences */ |
527 | /* disable event_write fences */ |
524 | rdev->wb.use_event = false; |
528 | rdev->wb.use_event = false; |
525 | /* disabled via module param */ |
529 | /* disabled via module param */ |
526 | if (radeon_no_wb == 1) { |
530 | if (radeon_no_wb == 1) { |
527 | rdev->wb.enabled = false; |
531 | rdev->wb.enabled = false; |
528 | } else { |
532 | } else { |
529 | if (rdev->flags & RADEON_IS_AGP) { |
533 | if (rdev->flags & RADEON_IS_AGP) { |
530 | /* often unreliable on AGP */ |
534 | /* often unreliable on AGP */ |
531 | rdev->wb.enabled = false; |
535 | rdev->wb.enabled = false; |
532 | } else if (rdev->family < CHIP_R300) { |
536 | } else if (rdev->family < CHIP_R300) { |
533 | /* often unreliable on pre-r300 */ |
537 | /* often unreliable on pre-r300 */ |
534 | rdev->wb.enabled = false; |
538 | rdev->wb.enabled = false; |
535 | } else { |
539 | } else { |
536 | rdev->wb.enabled = true; |
540 | rdev->wb.enabled = true; |
537 | /* event_write fences are only available on r600+ */ |
541 | /* event_write fences are only available on r600+ */ |
538 | if (rdev->family >= CHIP_R600) { |
542 | if (rdev->family >= CHIP_R600) { |
539 | rdev->wb.use_event = true; |
543 | rdev->wb.use_event = true; |
540 | } |
544 | } |
541 | } |
545 | } |
542 | } |
546 | } |
543 | /* always use writeback/events on NI, APUs */ |
547 | /* always use writeback/events on NI, APUs */ |
544 | if (rdev->family >= CHIP_PALM) { |
548 | if (rdev->family >= CHIP_PALM) { |
545 | rdev->wb.enabled = true; |
549 | rdev->wb.enabled = true; |
546 | rdev->wb.use_event = true; |
550 | rdev->wb.use_event = true; |
547 | } |
551 | } |
548 | 552 | ||
549 | dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); |
553 | dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); |
550 | 554 | ||
551 | return 0; |
555 | return 0; |
552 | } |
556 | } |
553 | 557 | ||
554 | /** |
558 | /** |
555 | * radeon_vram_location - try to find VRAM location |
559 | * radeon_vram_location - try to find VRAM location |
556 | * @rdev: radeon device structure holding all necessary informations |
560 | * @rdev: radeon device structure holding all necessary informations |
557 | * @mc: memory controller structure holding memory informations |
561 | * @mc: memory controller structure holding memory informations |
558 | * @base: base address at which to put VRAM |
562 | * @base: base address at which to put VRAM |
559 | * |
563 | * |
560 | * Function will place try to place VRAM at base address provided |
564 | * Function will place try to place VRAM at base address provided |
561 | * as parameter (which is so far either PCI aperture address or |
565 | * as parameter (which is so far either PCI aperture address or |
562 | * for IGP TOM base address). |
566 | * for IGP TOM base address). |
563 | * |
567 | * |
564 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
568 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
565 | * address space then we limit the VRAM size to the aperture. |
569 | * address space then we limit the VRAM size to the aperture. |
566 | * |
570 | * |
567 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
571 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
568 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
572 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
569 | * size and print a warning. |
573 | * size and print a warning. |
570 | * |
574 | * |
571 | * This function will never fails, worst case are limiting VRAM. |
575 | * This function will never fails, worst case are limiting VRAM. |
572 | * |
576 | * |
573 | * Note: GTT start, end, size should be initialized before calling this |
577 | * Note: GTT start, end, size should be initialized before calling this |
574 | * function on AGP platform. |
578 | * function on AGP platform. |
575 | * |
579 | * |
576 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, |
580 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, |
577 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
581 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
578 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
582 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
579 | * not IGP. |
583 | * not IGP. |
580 | * |
584 | * |
581 | * Note: we use mc_vram_size as on some board we need to program the mc to |
585 | * Note: we use mc_vram_size as on some board we need to program the mc to |
582 | * cover the whole aperture even if VRAM size is inferior to aperture size |
586 | * cover the whole aperture even if VRAM size is inferior to aperture size |
583 | * Novell bug 204882 + along with lots of ubuntu ones |
587 | * Novell bug 204882 + along with lots of ubuntu ones |
584 | * |
588 | * |
585 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
589 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
586 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
590 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
587 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
591 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
588 | * ones) |
592 | * ones) |
589 | * |
593 | * |
590 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
594 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
591 | * explicitly check for that thought. |
595 | * explicitly check for that thought. |
592 | * |
596 | * |
593 | * FIXME: when reducing VRAM size align new size on power of 2. |
597 | * FIXME: when reducing VRAM size align new size on power of 2. |
594 | */ |
598 | */ |
595 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
599 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
596 | { |
600 | { |
597 | uint64_t limit = (uint64_t)radeon_vram_limit << 20; |
601 | uint64_t limit = (uint64_t)radeon_vram_limit << 20; |
598 | 602 | ||
599 | mc->vram_start = base; |
603 | mc->vram_start = base; |
600 | if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { |
604 | if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { |
601 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
605 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
602 | mc->real_vram_size = mc->aper_size; |
606 | mc->real_vram_size = mc->aper_size; |
603 | mc->mc_vram_size = mc->aper_size; |
607 | mc->mc_vram_size = mc->aper_size; |
604 | } |
608 | } |
605 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
609 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
606 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { |
610 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { |
607 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
611 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
608 | mc->real_vram_size = mc->aper_size; |
612 | mc->real_vram_size = mc->aper_size; |
609 | mc->mc_vram_size = mc->aper_size; |
613 | mc->mc_vram_size = mc->aper_size; |
610 | } |
614 | } |
611 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
615 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
612 | if (limit && limit < mc->real_vram_size) |
616 | if (limit && limit < mc->real_vram_size) |
613 | mc->real_vram_size = limit; |
617 | mc->real_vram_size = limit; |
614 | dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", |
618 | dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", |
615 | mc->mc_vram_size >> 20, mc->vram_start, |
619 | mc->mc_vram_size >> 20, mc->vram_start, |
616 | mc->vram_end, mc->real_vram_size >> 20); |
620 | mc->vram_end, mc->real_vram_size >> 20); |
617 | } |
621 | } |
618 | 622 | ||
619 | /** |
623 | /** |
620 | * radeon_gtt_location - try to find GTT location |
624 | * radeon_gtt_location - try to find GTT location |
621 | * @rdev: radeon device structure holding all necessary informations |
625 | * @rdev: radeon device structure holding all necessary informations |
622 | * @mc: memory controller structure holding memory informations |
626 | * @mc: memory controller structure holding memory informations |
623 | * |
627 | * |
624 | * Function will place try to place GTT before or after VRAM. |
628 | * Function will place try to place GTT before or after VRAM. |
625 | * |
629 | * |
626 | * If GTT size is bigger than space left then we ajust GTT size. |
630 | * If GTT size is bigger than space left then we ajust GTT size. |
627 | * Thus function will never fails. |
631 | * Thus function will never fails. |
628 | * |
632 | * |
629 | * FIXME: when reducing GTT size align new size on power of 2. |
633 | * FIXME: when reducing GTT size align new size on power of 2. |
630 | */ |
634 | */ |
631 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
635 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
632 | { |
636 | { |
633 | u64 size_af, size_bf; |
637 | u64 size_af, size_bf; |
634 | 638 | ||
635 | size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
639 | size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
636 | size_bf = mc->vram_start & ~mc->gtt_base_align; |
640 | size_bf = mc->vram_start & ~mc->gtt_base_align; |
637 | if (size_bf > size_af) { |
641 | if (size_bf > size_af) { |
638 | if (mc->gtt_size > size_bf) { |
642 | if (mc->gtt_size > size_bf) { |
639 | dev_warn(rdev->dev, "limiting GTT\n"); |
643 | dev_warn(rdev->dev, "limiting GTT\n"); |
640 | mc->gtt_size = size_bf; |
644 | mc->gtt_size = size_bf; |
641 | } |
645 | } |
642 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; |
646 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; |
643 | } else { |
647 | } else { |
644 | if (mc->gtt_size > size_af) { |
648 | if (mc->gtt_size > size_af) { |
645 | dev_warn(rdev->dev, "limiting GTT\n"); |
649 | dev_warn(rdev->dev, "limiting GTT\n"); |
646 | mc->gtt_size = size_af; |
650 | mc->gtt_size = size_af; |
647 | } |
651 | } |
648 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; |
652 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; |
649 | } |
653 | } |
650 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
654 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
651 | dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
655 | dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
652 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
656 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
653 | } |
657 | } |
654 | 658 | ||
655 | /* |
659 | /* |
656 | * GPU helpers function. |
660 | * GPU helpers function. |
657 | */ |
661 | */ |
658 | /** |
662 | /** |
659 | * radeon_card_posted - check if the hw has already been initialized |
663 | * radeon_card_posted - check if the hw has already been initialized |
660 | * |
664 | * |
661 | * @rdev: radeon_device pointer |
665 | * @rdev: radeon_device pointer |
662 | * |
666 | * |
663 | * Check if the asic has been initialized (all asics). |
667 | * Check if the asic has been initialized (all asics). |
664 | * Used at driver startup. |
668 | * Used at driver startup. |
665 | * Returns true if initialized or false if not. |
669 | * Returns true if initialized or false if not. |
666 | */ |
670 | */ |
667 | bool radeon_card_posted(struct radeon_device *rdev) |
671 | bool radeon_card_posted(struct radeon_device *rdev) |
668 | { |
672 | { |
669 | uint32_t reg; |
673 | uint32_t reg; |
670 | 674 | ||
671 | if (ASIC_IS_NODCE(rdev)) |
675 | if (ASIC_IS_NODCE(rdev)) |
672 | goto check_memsize; |
676 | goto check_memsize; |
673 | 677 | ||
674 | /* first check CRTCs */ |
678 | /* first check CRTCs */ |
675 | if (ASIC_IS_DCE4(rdev)) { |
679 | if (ASIC_IS_DCE4(rdev)) { |
676 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
680 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
677 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
681 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
678 | if (rdev->num_crtc >= 4) { |
682 | if (rdev->num_crtc >= 4) { |
679 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
683 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
680 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); |
684 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); |
681 | } |
685 | } |
682 | if (rdev->num_crtc >= 6) { |
686 | if (rdev->num_crtc >= 6) { |
683 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
687 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
684 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
688 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
685 | } |
689 | } |
686 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
690 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
687 | return true; |
691 | return true; |
688 | } else if (ASIC_IS_AVIVO(rdev)) { |
692 | } else if (ASIC_IS_AVIVO(rdev)) { |
689 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
693 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
690 | RREG32(AVIVO_D2CRTC_CONTROL); |
694 | RREG32(AVIVO_D2CRTC_CONTROL); |
691 | if (reg & AVIVO_CRTC_EN) { |
695 | if (reg & AVIVO_CRTC_EN) { |
692 | return true; |
696 | return true; |
693 | } |
697 | } |
694 | } else { |
698 | } else { |
695 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
699 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
696 | RREG32(RADEON_CRTC2_GEN_CNTL); |
700 | RREG32(RADEON_CRTC2_GEN_CNTL); |
697 | if (reg & RADEON_CRTC_EN) { |
701 | if (reg & RADEON_CRTC_EN) { |
698 | return true; |
702 | return true; |
699 | } |
703 | } |
700 | } |
704 | } |
701 | 705 | ||
702 | check_memsize: |
706 | check_memsize: |
703 | /* then check MEM_SIZE, in case the crtcs are off */ |
707 | /* then check MEM_SIZE, in case the crtcs are off */ |
704 | if (rdev->family >= CHIP_R600) |
708 | if (rdev->family >= CHIP_R600) |
705 | reg = RREG32(R600_CONFIG_MEMSIZE); |
709 | reg = RREG32(R600_CONFIG_MEMSIZE); |
706 | else |
710 | else |
707 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
711 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
708 | 712 | ||
709 | if (reg) |
713 | if (reg) |
710 | return true; |
714 | return true; |
711 | 715 | ||
712 | return false; |
716 | return false; |
713 | 717 | ||
714 | } |
718 | } |
715 | 719 | ||
716 | /** |
720 | /** |
717 | * radeon_update_bandwidth_info - update display bandwidth params |
721 | * radeon_update_bandwidth_info - update display bandwidth params |
718 | * |
722 | * |
719 | * @rdev: radeon_device pointer |
723 | * @rdev: radeon_device pointer |
720 | * |
724 | * |
721 | * Used when sclk/mclk are switched or display modes are set. |
725 | * Used when sclk/mclk are switched or display modes are set. |
722 | * params are used to calculate display watermarks (all asics) |
726 | * params are used to calculate display watermarks (all asics) |
723 | */ |
727 | */ |
724 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
728 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
725 | { |
729 | { |
726 | fixed20_12 a; |
730 | fixed20_12 a; |
727 | u32 sclk = rdev->pm.current_sclk; |
731 | u32 sclk = rdev->pm.current_sclk; |
728 | u32 mclk = rdev->pm.current_mclk; |
732 | u32 mclk = rdev->pm.current_mclk; |
729 | 733 | ||
730 | /* sclk/mclk in Mhz */ |
734 | /* sclk/mclk in Mhz */ |
731 | a.full = dfixed_const(100); |
735 | a.full = dfixed_const(100); |
732 | rdev->pm.sclk.full = dfixed_const(sclk); |
736 | rdev->pm.sclk.full = dfixed_const(sclk); |
733 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); |
737 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); |
734 | rdev->pm.mclk.full = dfixed_const(mclk); |
738 | rdev->pm.mclk.full = dfixed_const(mclk); |
735 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); |
739 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); |
736 | 740 | ||
737 | if (rdev->flags & RADEON_IS_IGP) { |
741 | if (rdev->flags & RADEON_IS_IGP) { |
738 | a.full = dfixed_const(16); |
742 | a.full = dfixed_const(16); |
739 | /* core_bandwidth = sclk(Mhz) * 16 */ |
743 | /* core_bandwidth = sclk(Mhz) * 16 */ |
740 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
744 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
741 | } |
745 | } |
742 | } |
746 | } |
743 | 747 | ||
744 | /** |
748 | /** |
745 | * radeon_boot_test_post_card - check and possibly initialize the hw |
749 | * radeon_boot_test_post_card - check and possibly initialize the hw |
746 | * |
750 | * |
747 | * @rdev: radeon_device pointer |
751 | * @rdev: radeon_device pointer |
748 | * |
752 | * |
749 | * Check if the asic is initialized and if not, attempt to initialize |
753 | * Check if the asic is initialized and if not, attempt to initialize |
750 | * it (all asics). |
754 | * it (all asics). |
751 | * Returns true if initialized or false if not. |
755 | * Returns true if initialized or false if not. |
752 | */ |
756 | */ |
753 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
757 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
754 | { |
758 | { |
755 | if (radeon_card_posted(rdev)) |
759 | if (radeon_card_posted(rdev)) |
756 | return true; |
760 | return true; |
757 | 761 | ||
758 | if (rdev->bios) { |
762 | if (rdev->bios) { |
759 | DRM_INFO("GPU not posted. posting now...\n"); |
763 | DRM_INFO("GPU not posted. posting now...\n"); |
760 | if (rdev->is_atom_bios) |
764 | if (rdev->is_atom_bios) |
761 | atom_asic_init(rdev->mode_info.atom_context); |
765 | atom_asic_init(rdev->mode_info.atom_context); |
762 | else |
766 | else |
763 | radeon_combios_asic_init(rdev->ddev); |
767 | radeon_combios_asic_init(rdev->ddev); |
764 | return true; |
768 | return true; |
765 | } else { |
769 | } else { |
766 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
770 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
767 | return false; |
771 | return false; |
768 | } |
772 | } |
769 | } |
773 | } |
770 | 774 | ||
771 | /** |
775 | /** |
772 | * radeon_dummy_page_init - init dummy page used by the driver |
776 | * radeon_dummy_page_init - init dummy page used by the driver |
773 | * |
777 | * |
774 | * @rdev: radeon_device pointer |
778 | * @rdev: radeon_device pointer |
775 | * |
779 | * |
776 | * Allocate the dummy page used by the driver (all asics). |
780 | * Allocate the dummy page used by the driver (all asics). |
777 | * This dummy page is used by the driver as a filler for gart entries |
781 | * This dummy page is used by the driver as a filler for gart entries |
778 | * when pages are taken out of the GART |
782 | * when pages are taken out of the GART |
779 | * Returns 0 on sucess, -ENOMEM on failure. |
783 | * Returns 0 on sucess, -ENOMEM on failure. |
780 | */ |
784 | */ |
781 | int radeon_dummy_page_init(struct radeon_device *rdev) |
785 | int radeon_dummy_page_init(struct radeon_device *rdev) |
782 | { |
786 | { |
783 | if (rdev->dummy_page.page) |
787 | if (rdev->dummy_page.page) |
784 | return 0; |
788 | return 0; |
785 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
789 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
786 | if (rdev->dummy_page.page == NULL) |
790 | if (rdev->dummy_page.page == NULL) |
787 | return -ENOMEM; |
791 | return -ENOMEM; |
788 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, |
792 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, |
789 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
793 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
790 | return 0; |
794 | return 0; |
791 | } |
795 | } |
792 | 796 | ||
793 | /** |
797 | /** |
794 | * radeon_dummy_page_fini - free dummy page used by the driver |
798 | * radeon_dummy_page_fini - free dummy page used by the driver |
795 | * |
799 | * |
796 | * @rdev: radeon_device pointer |
800 | * @rdev: radeon_device pointer |
797 | * |
801 | * |
798 | * Frees the dummy page used by the driver (all asics). |
802 | * Frees the dummy page used by the driver (all asics). |
799 | */ |
803 | */ |
800 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
804 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
801 | { |
805 | { |
802 | if (rdev->dummy_page.page == NULL) |
806 | if (rdev->dummy_page.page == NULL) |
803 | return; |
807 | return; |
804 | 808 | ||
805 | rdev->dummy_page.page = NULL; |
809 | rdev->dummy_page.page = NULL; |
806 | } |
810 | } |
807 | 811 | ||
808 | 812 | ||
809 | /* ATOM accessor methods */ |
813 | /* ATOM accessor methods */ |
810 | /* |
814 | /* |
811 | * ATOM is an interpreted byte code stored in tables in the vbios. The |
815 | * ATOM is an interpreted byte code stored in tables in the vbios. The |
812 | * driver registers callbacks to access registers and the interpreter |
816 | * driver registers callbacks to access registers and the interpreter |
813 | * in the driver parses the tables and executes then to program specific |
817 | * in the driver parses the tables and executes then to program specific |
814 | * actions (set display modes, asic init, etc.). See radeon_atombios.c, |
818 | * actions (set display modes, asic init, etc.). See radeon_atombios.c, |
815 | * atombios.h, and atom.c |
819 | * atombios.h, and atom.c |
816 | */ |
820 | */ |
817 | 821 | ||
818 | /** |
822 | /** |
819 | * cail_pll_read - read PLL register |
823 | * cail_pll_read - read PLL register |
820 | * |
824 | * |
821 | * @info: atom card_info pointer |
825 | * @info: atom card_info pointer |
822 | * @reg: PLL register offset |
826 | * @reg: PLL register offset |
823 | * |
827 | * |
824 | * Provides a PLL register accessor for the atom interpreter (r4xx+). |
828 | * Provides a PLL register accessor for the atom interpreter (r4xx+). |
825 | * Returns the value of the PLL register. |
829 | * Returns the value of the PLL register. |
826 | */ |
830 | */ |
827 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
831 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
828 | { |
832 | { |
829 | struct radeon_device *rdev = info->dev->dev_private; |
833 | struct radeon_device *rdev = info->dev->dev_private; |
830 | uint32_t r; |
834 | uint32_t r; |
831 | 835 | ||
832 | r = rdev->pll_rreg(rdev, reg); |
836 | r = rdev->pll_rreg(rdev, reg); |
833 | return r; |
837 | return r; |
834 | } |
838 | } |
835 | 839 | ||
836 | /** |
840 | /** |
837 | * cail_pll_write - write PLL register |
841 | * cail_pll_write - write PLL register |
838 | * |
842 | * |
839 | * @info: atom card_info pointer |
843 | * @info: atom card_info pointer |
840 | * @reg: PLL register offset |
844 | * @reg: PLL register offset |
841 | * @val: value to write to the pll register |
845 | * @val: value to write to the pll register |
842 | * |
846 | * |
843 | * Provides a PLL register accessor for the atom interpreter (r4xx+). |
847 | * Provides a PLL register accessor for the atom interpreter (r4xx+). |
844 | */ |
848 | */ |
845 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
849 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
846 | { |
850 | { |
847 | struct radeon_device *rdev = info->dev->dev_private; |
851 | struct radeon_device *rdev = info->dev->dev_private; |
848 | 852 | ||
849 | rdev->pll_wreg(rdev, reg, val); |
853 | rdev->pll_wreg(rdev, reg, val); |
850 | } |
854 | } |
851 | 855 | ||
852 | /** |
856 | /** |
853 | * cail_mc_read - read MC (Memory Controller) register |
857 | * cail_mc_read - read MC (Memory Controller) register |
854 | * |
858 | * |
855 | * @info: atom card_info pointer |
859 | * @info: atom card_info pointer |
856 | * @reg: MC register offset |
860 | * @reg: MC register offset |
857 | * |
861 | * |
858 | * Provides an MC register accessor for the atom interpreter (r4xx+). |
862 | * Provides an MC register accessor for the atom interpreter (r4xx+). |
859 | * Returns the value of the MC register. |
863 | * Returns the value of the MC register. |
860 | */ |
864 | */ |
861 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
865 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
862 | { |
866 | { |
863 | struct radeon_device *rdev = info->dev->dev_private; |
867 | struct radeon_device *rdev = info->dev->dev_private; |
864 | uint32_t r; |
868 | uint32_t r; |
865 | 869 | ||
866 | r = rdev->mc_rreg(rdev, reg); |
870 | r = rdev->mc_rreg(rdev, reg); |
867 | return r; |
871 | return r; |
868 | } |
872 | } |
869 | 873 | ||
870 | /** |
874 | /** |
871 | * cail_mc_write - write MC (Memory Controller) register |
875 | * cail_mc_write - write MC (Memory Controller) register |
872 | * |
876 | * |
873 | * @info: atom card_info pointer |
877 | * @info: atom card_info pointer |
874 | * @reg: MC register offset |
878 | * @reg: MC register offset |
875 | * @val: value to write to the pll register |
879 | * @val: value to write to the pll register |
876 | * |
880 | * |
877 | * Provides a MC register accessor for the atom interpreter (r4xx+). |
881 | * Provides a MC register accessor for the atom interpreter (r4xx+). |
878 | */ |
882 | */ |
879 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
883 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
880 | { |
884 | { |
881 | struct radeon_device *rdev = info->dev->dev_private; |
885 | struct radeon_device *rdev = info->dev->dev_private; |
882 | 886 | ||
883 | rdev->mc_wreg(rdev, reg, val); |
887 | rdev->mc_wreg(rdev, reg, val); |
884 | } |
888 | } |
885 | 889 | ||
886 | /** |
890 | /** |
887 | * cail_reg_write - write MMIO register |
891 | * cail_reg_write - write MMIO register |
888 | * |
892 | * |
889 | * @info: atom card_info pointer |
893 | * @info: atom card_info pointer |
890 | * @reg: MMIO register offset |
894 | * @reg: MMIO register offset |
891 | * @val: value to write to the pll register |
895 | * @val: value to write to the pll register |
892 | * |
896 | * |
893 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). |
897 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). |
894 | */ |
898 | */ |
895 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
899 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
896 | { |
900 | { |
897 | struct radeon_device *rdev = info->dev->dev_private; |
901 | struct radeon_device *rdev = info->dev->dev_private; |
898 | 902 | ||
899 | WREG32(reg*4, val); |
903 | WREG32(reg*4, val); |
900 | } |
904 | } |
901 | 905 | ||
902 | /** |
906 | /** |
903 | * cail_reg_read - read MMIO register |
907 | * cail_reg_read - read MMIO register |
904 | * |
908 | * |
905 | * @info: atom card_info pointer |
909 | * @info: atom card_info pointer |
906 | * @reg: MMIO register offset |
910 | * @reg: MMIO register offset |
907 | * |
911 | * |
908 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). |
912 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). |
909 | * Returns the value of the MMIO register. |
913 | * Returns the value of the MMIO register. |
910 | */ |
914 | */ |
911 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
915 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
912 | { |
916 | { |
913 | struct radeon_device *rdev = info->dev->dev_private; |
917 | struct radeon_device *rdev = info->dev->dev_private; |
914 | uint32_t r; |
918 | uint32_t r; |
915 | 919 | ||
916 | r = RREG32(reg*4); |
920 | r = RREG32(reg*4); |
917 | return r; |
921 | return r; |
918 | } |
922 | } |
919 | 923 | ||
920 | /** |
924 | /** |
921 | * cail_ioreg_write - write IO register |
925 | * cail_ioreg_write - write IO register |
922 | * |
926 | * |
923 | * @info: atom card_info pointer |
927 | * @info: atom card_info pointer |
924 | * @reg: IO register offset |
928 | * @reg: IO register offset |
925 | * @val: value to write to the pll register |
929 | * @val: value to write to the pll register |
926 | * |
930 | * |
927 | * Provides a IO register accessor for the atom interpreter (r4xx+). |
931 | * Provides a IO register accessor for the atom interpreter (r4xx+). |
928 | */ |
932 | */ |
929 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
933 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
930 | { |
934 | { |
931 | struct radeon_device *rdev = info->dev->dev_private; |
935 | struct radeon_device *rdev = info->dev->dev_private; |
932 | 936 | ||
933 | WREG32_IO(reg*4, val); |
937 | WREG32_IO(reg*4, val); |
934 | } |
938 | } |
935 | 939 | ||
936 | /** |
940 | /** |
937 | * cail_ioreg_read - read IO register |
941 | * cail_ioreg_read - read IO register |
938 | * |
942 | * |
939 | * @info: atom card_info pointer |
943 | * @info: atom card_info pointer |
940 | * @reg: IO register offset |
944 | * @reg: IO register offset |
941 | * |
945 | * |
942 | * Provides an IO register accessor for the atom interpreter (r4xx+). |
946 | * Provides an IO register accessor for the atom interpreter (r4xx+). |
943 | * Returns the value of the IO register. |
947 | * Returns the value of the IO register. |
944 | */ |
948 | */ |
945 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) |
949 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) |
946 | { |
950 | { |
947 | struct radeon_device *rdev = info->dev->dev_private; |
951 | struct radeon_device *rdev = info->dev->dev_private; |
948 | uint32_t r; |
952 | uint32_t r; |
949 | 953 | ||
950 | r = RREG32_IO(reg*4); |
954 | r = RREG32_IO(reg*4); |
951 | return r; |
955 | return r; |
952 | } |
956 | } |
953 | 957 | ||
954 | /** |
958 | /** |
955 | * radeon_atombios_init - init the driver info and callbacks for atombios |
959 | * radeon_atombios_init - init the driver info and callbacks for atombios |
956 | * |
960 | * |
957 | * @rdev: radeon_device pointer |
961 | * @rdev: radeon_device pointer |
958 | * |
962 | * |
959 | * Initializes the driver info and register access callbacks for the |
963 | * Initializes the driver info and register access callbacks for the |
960 | * ATOM interpreter (r4xx+). |
964 | * ATOM interpreter (r4xx+). |
961 | * Returns 0 on sucess, -ENOMEM on failure. |
965 | * Returns 0 on sucess, -ENOMEM on failure. |
962 | * Called at driver startup. |
966 | * Called at driver startup. |
963 | */ |
967 | */ |
964 | int radeon_atombios_init(struct radeon_device *rdev) |
968 | int radeon_atombios_init(struct radeon_device *rdev) |
965 | { |
969 | { |
966 | struct card_info *atom_card_info = |
970 | struct card_info *atom_card_info = |
967 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
971 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
968 | 972 | ||
969 | if (!atom_card_info) |
973 | if (!atom_card_info) |
970 | return -ENOMEM; |
974 | return -ENOMEM; |
971 | 975 | ||
972 | rdev->mode_info.atom_card_info = atom_card_info; |
976 | rdev->mode_info.atom_card_info = atom_card_info; |
973 | atom_card_info->dev = rdev->ddev; |
977 | atom_card_info->dev = rdev->ddev; |
974 | atom_card_info->reg_read = cail_reg_read; |
978 | atom_card_info->reg_read = cail_reg_read; |
975 | atom_card_info->reg_write = cail_reg_write; |
979 | atom_card_info->reg_write = cail_reg_write; |
976 | /* needed for iio ops */ |
980 | /* needed for iio ops */ |
977 | if (rdev->rio_mem) { |
981 | if (rdev->rio_mem) { |
978 | atom_card_info->ioreg_read = cail_ioreg_read; |
982 | atom_card_info->ioreg_read = cail_ioreg_read; |
979 | atom_card_info->ioreg_write = cail_ioreg_write; |
983 | atom_card_info->ioreg_write = cail_ioreg_write; |
980 | } else { |
984 | } else { |
981 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); |
985 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); |
982 | atom_card_info->ioreg_read = cail_reg_read; |
986 | atom_card_info->ioreg_read = cail_reg_read; |
983 | atom_card_info->ioreg_write = cail_reg_write; |
987 | atom_card_info->ioreg_write = cail_reg_write; |
984 | } |
988 | } |
985 | atom_card_info->mc_read = cail_mc_read; |
989 | atom_card_info->mc_read = cail_mc_read; |
986 | atom_card_info->mc_write = cail_mc_write; |
990 | atom_card_info->mc_write = cail_mc_write; |
987 | atom_card_info->pll_read = cail_pll_read; |
991 | atom_card_info->pll_read = cail_pll_read; |
988 | atom_card_info->pll_write = cail_pll_write; |
992 | atom_card_info->pll_write = cail_pll_write; |
989 | 993 | ||
990 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
994 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
991 | if (!rdev->mode_info.atom_context) { |
995 | if (!rdev->mode_info.atom_context) { |
992 | radeon_atombios_fini(rdev); |
996 | radeon_atombios_fini(rdev); |
993 | return -ENOMEM; |
997 | return -ENOMEM; |
994 | } |
998 | } |
995 | 999 | ||
996 | mutex_init(&rdev->mode_info.atom_context->mutex); |
1000 | mutex_init(&rdev->mode_info.atom_context->mutex); |
997 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
1001 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
998 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
1002 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
999 | return 0; |
1003 | return 0; |
1000 | } |
1004 | } |
1001 | 1005 | ||
1002 | /** |
1006 | /** |
1003 | * radeon_atombios_fini - free the driver info and callbacks for atombios |
1007 | * radeon_atombios_fini - free the driver info and callbacks for atombios |
1004 | * |
1008 | * |
1005 | * @rdev: radeon_device pointer |
1009 | * @rdev: radeon_device pointer |
1006 | * |
1010 | * |
1007 | * Frees the driver info and register access callbacks for the ATOM |
1011 | * Frees the driver info and register access callbacks for the ATOM |
1008 | * interpreter (r4xx+). |
1012 | * interpreter (r4xx+). |
1009 | * Called at driver shutdown. |
1013 | * Called at driver shutdown. |
1010 | */ |
1014 | */ |
1011 | void radeon_atombios_fini(struct radeon_device *rdev) |
1015 | void radeon_atombios_fini(struct radeon_device *rdev) |
1012 | { |
1016 | { |
1013 | if (rdev->mode_info.atom_context) { |
1017 | if (rdev->mode_info.atom_context) { |
1014 | kfree(rdev->mode_info.atom_context->scratch); |
1018 | kfree(rdev->mode_info.atom_context->scratch); |
1015 | } |
1019 | } |
1016 | kfree(rdev->mode_info.atom_context); |
1020 | kfree(rdev->mode_info.atom_context); |
1017 | rdev->mode_info.atom_context = NULL; |
1021 | rdev->mode_info.atom_context = NULL; |
1018 | kfree(rdev->mode_info.atom_card_info); |
1022 | kfree(rdev->mode_info.atom_card_info); |
1019 | rdev->mode_info.atom_card_info = NULL; |
1023 | rdev->mode_info.atom_card_info = NULL; |
1020 | } |
1024 | } |
1021 | 1025 | ||
1022 | /* COMBIOS */ |
1026 | /* COMBIOS */ |
1023 | /* |
1027 | /* |
1024 | * COMBIOS is the bios format prior to ATOM. It provides |
1028 | * COMBIOS is the bios format prior to ATOM. It provides |
1025 | * command tables similar to ATOM, but doesn't have a unified |
1029 | * command tables similar to ATOM, but doesn't have a unified |
1026 | * parser. See radeon_combios.c |
1030 | * parser. See radeon_combios.c |
1027 | */ |
1031 | */ |
1028 | 1032 | ||
1029 | /** |
1033 | /** |
1030 | * radeon_combios_init - init the driver info for combios |
1034 | * radeon_combios_init - init the driver info for combios |
1031 | * |
1035 | * |
1032 | * @rdev: radeon_device pointer |
1036 | * @rdev: radeon_device pointer |
1033 | * |
1037 | * |
1034 | * Initializes the driver info for combios (r1xx-r3xx). |
1038 | * Initializes the driver info for combios (r1xx-r3xx). |
1035 | * Returns 0 on sucess. |
1039 | * Returns 0 on sucess. |
1036 | * Called at driver startup. |
1040 | * Called at driver startup. |
1037 | */ |
1041 | */ |
1038 | int radeon_combios_init(struct radeon_device *rdev) |
1042 | int radeon_combios_init(struct radeon_device *rdev) |
1039 | { |
1043 | { |
1040 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
1044 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
1041 | return 0; |
1045 | return 0; |
1042 | } |
1046 | } |
1043 | 1047 | ||
1044 | /** |
1048 | /** |
1045 | * radeon_combios_fini - free the driver info for combios |
1049 | * radeon_combios_fini - free the driver info for combios |
1046 | * |
1050 | * |
1047 | * @rdev: radeon_device pointer |
1051 | * @rdev: radeon_device pointer |
1048 | * |
1052 | * |
1049 | * Frees the driver info for combios (r1xx-r3xx). |
1053 | * Frees the driver info for combios (r1xx-r3xx). |
1050 | * Called at driver shutdown. |
1054 | * Called at driver shutdown. |
1051 | */ |
1055 | */ |
1052 | void radeon_combios_fini(struct radeon_device *rdev) |
1056 | void radeon_combios_fini(struct radeon_device *rdev) |
1053 | { |
1057 | { |
1054 | } |
1058 | } |
1055 | 1059 | ||
1056 | /* if we get transitioned to only one device, take VGA back */ |
1060 | /* if we get transitioned to only one device, take VGA back */ |
1057 | /** |
1061 | /** |
1058 | * radeon_vga_set_decode - enable/disable vga decode |
1062 | * radeon_vga_set_decode - enable/disable vga decode |
1059 | * |
1063 | * |
1060 | * @cookie: radeon_device pointer |
1064 | * @cookie: radeon_device pointer |
1061 | * @state: enable/disable vga decode |
1065 | * @state: enable/disable vga decode |
1062 | * |
1066 | * |
1063 | * Enable/disable vga decode (all asics). |
1067 | * Enable/disable vga decode (all asics). |
1064 | * Returns VGA resource flags. |
1068 | * Returns VGA resource flags. |
1065 | */ |
1069 | */ |
1066 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
1070 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
1067 | { |
1071 | { |
1068 | struct radeon_device *rdev = cookie; |
1072 | struct radeon_device *rdev = cookie; |
1069 | radeon_vga_set_state(rdev, state); |
1073 | radeon_vga_set_state(rdev, state); |
1070 | if (state) |
1074 | if (state) |
1071 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
1075 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
1072 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
1076 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
1073 | else |
1077 | else |
1074 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
1078 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
1075 | } |
1079 | } |
1076 | 1080 | ||
1077 | /** |
1081 | /** |
1078 | * radeon_check_pot_argument - check that argument is a power of two |
1082 | * radeon_check_pot_argument - check that argument is a power of two |
1079 | * |
1083 | * |
1080 | * @arg: value to check |
1084 | * @arg: value to check |
1081 | * |
1085 | * |
1082 | * Validates that a certain argument is a power of two (all asics). |
1086 | * Validates that a certain argument is a power of two (all asics). |
1083 | * Returns true if argument is valid. |
1087 | * Returns true if argument is valid. |
1084 | */ |
1088 | */ |
1085 | static bool radeon_check_pot_argument(int arg) |
1089 | static bool radeon_check_pot_argument(int arg) |
1086 | { |
1090 | { |
1087 | return (arg & (arg - 1)) == 0; |
1091 | return (arg & (arg - 1)) == 0; |
1088 | } |
1092 | } |
1089 | 1093 | ||
1090 | /** |
1094 | /** |
1091 | * radeon_check_arguments - validate module params |
1095 | * radeon_check_arguments - validate module params |
1092 | * |
1096 | * |
1093 | * @rdev: radeon_device pointer |
1097 | * @rdev: radeon_device pointer |
1094 | * |
1098 | * |
1095 | * Validates certain module parameters and updates |
1099 | * Validates certain module parameters and updates |
1096 | * the associated values used by the driver (all asics). |
1100 | * the associated values used by the driver (all asics). |
1097 | */ |
1101 | */ |
1098 | static void radeon_check_arguments(struct radeon_device *rdev) |
1102 | static void radeon_check_arguments(struct radeon_device *rdev) |
1099 | { |
1103 | { |
1100 | /* vramlimit must be a power of two */ |
1104 | /* vramlimit must be a power of two */ |
1101 | if (!radeon_check_pot_argument(radeon_vram_limit)) { |
1105 | if (!radeon_check_pot_argument(radeon_vram_limit)) { |
1102 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
1106 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
1103 | radeon_vram_limit); |
1107 | radeon_vram_limit); |
1104 | radeon_vram_limit = 0; |
1108 | radeon_vram_limit = 0; |
1105 | } |
1109 | } |
1106 | 1110 | ||
1107 | if (radeon_gart_size == -1) { |
1111 | if (radeon_gart_size == -1) { |
1108 | /* default to a larger gart size on newer asics */ |
1112 | /* default to a larger gart size on newer asics */ |
1109 | if (rdev->family >= CHIP_RV770) |
1113 | if (rdev->family >= CHIP_RV770) |
1110 | radeon_gart_size = 1024; |
1114 | radeon_gart_size = 1024; |
1111 | else |
1115 | else |
1112 | radeon_gart_size = 512; |
1116 | radeon_gart_size = 512; |
1113 | } |
1117 | } |
1114 | /* gtt size must be power of two and greater or equal to 32M */ |
1118 | /* gtt size must be power of two and greater or equal to 32M */ |
1115 | if (radeon_gart_size < 32) { |
1119 | if (radeon_gart_size < 32) { |
1116 | dev_warn(rdev->dev, "gart size (%d) too small\n", |
1120 | dev_warn(rdev->dev, "gart size (%d) too small\n", |
1117 | radeon_gart_size); |
1121 | radeon_gart_size); |
1118 | if (rdev->family >= CHIP_RV770) |
1122 | if (rdev->family >= CHIP_RV770) |
1119 | radeon_gart_size = 1024; |
1123 | radeon_gart_size = 1024; |
1120 | else |
1124 | else |
1121 | radeon_gart_size = 512; |
1125 | radeon_gart_size = 512; |
1122 | } else if (!radeon_check_pot_argument(radeon_gart_size)) { |
1126 | } else if (!radeon_check_pot_argument(radeon_gart_size)) { |
1123 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
1127 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
1124 | radeon_gart_size); |
1128 | radeon_gart_size); |
1125 | if (rdev->family >= CHIP_RV770) |
1129 | if (rdev->family >= CHIP_RV770) |
1126 | radeon_gart_size = 1024; |
1130 | radeon_gart_size = 1024; |
1127 | else |
1131 | else |
1128 | radeon_gart_size = 512; |
1132 | radeon_gart_size = 512; |
1129 | } |
1133 | } |
1130 | rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; |
1134 | rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; |
1131 | 1135 | ||
1132 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
1136 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
1133 | switch (radeon_agpmode) { |
1137 | switch (radeon_agpmode) { |
1134 | case -1: |
1138 | case -1: |
1135 | case 0: |
1139 | case 0: |
1136 | case 1: |
1140 | case 1: |
1137 | case 2: |
1141 | case 2: |
1138 | case 4: |
1142 | case 4: |
1139 | case 8: |
1143 | case 8: |
1140 | break; |
1144 | break; |
1141 | default: |
1145 | default: |
1142 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
1146 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
1143 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
1147 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
1144 | radeon_agpmode = 0; |
1148 | radeon_agpmode = 0; |
1145 | break; |
1149 | break; |
1146 | } |
1150 | } |
1147 | 1151 | ||
1148 | if (!radeon_check_pot_argument(radeon_vm_size)) { |
1152 | if (!radeon_check_pot_argument(radeon_vm_size)) { |
1149 | dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", |
1153 | dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", |
1150 | radeon_vm_size); |
1154 | radeon_vm_size); |
1151 | radeon_vm_size = 4; |
1155 | radeon_vm_size = 4; |
1152 | } |
1156 | } |
1153 | 1157 | ||
1154 | if (radeon_vm_size < 1) { |
1158 | if (radeon_vm_size < 1) { |
1155 | dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n", |
1159 | dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n", |
1156 | radeon_vm_size); |
1160 | radeon_vm_size); |
1157 | radeon_vm_size = 4; |
1161 | radeon_vm_size = 4; |
1158 | } |
1162 | } |
1159 | 1163 | ||
1160 | /* |
1164 | /* |
1161 | * Max GPUVM size for Cayman, SI and CI are 40 bits. |
1165 | * Max GPUVM size for Cayman, SI and CI are 40 bits. |
1162 | */ |
1166 | */ |
1163 | if (radeon_vm_size > 1024) { |
1167 | if (radeon_vm_size > 1024) { |
1164 | dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", |
1168 | dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", |
1165 | radeon_vm_size); |
1169 | radeon_vm_size); |
1166 | radeon_vm_size = 4; |
1170 | radeon_vm_size = 4; |
1167 | } |
1171 | } |
1168 | 1172 | ||
1169 | /* defines number of bits in page table versus page directory, |
1173 | /* defines number of bits in page table versus page directory, |
1170 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the |
1174 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the |
1171 | * page table and the remaining bits are in the page directory */ |
1175 | * page table and the remaining bits are in the page directory */ |
1172 | if (radeon_vm_block_size == -1) { |
1176 | if (radeon_vm_block_size == -1) { |
1173 | 1177 | ||
1174 | /* Total bits covered by PD + PTs */ |
1178 | /* Total bits covered by PD + PTs */ |
1175 | unsigned bits = ilog2(radeon_vm_size) + 17; |
1179 | unsigned bits = ilog2(radeon_vm_size) + 18; |
1176 | 1180 | ||
1177 | /* Make sure the PD is 4K in size up to 8GB address space. |
1181 | /* Make sure the PD is 4K in size up to 8GB address space. |
1178 | Above that split equal between PD and PTs */ |
1182 | Above that split equal between PD and PTs */ |
1179 | if (radeon_vm_size <= 8) |
1183 | if (radeon_vm_size <= 8) |
1180 | radeon_vm_block_size = bits - 9; |
1184 | radeon_vm_block_size = bits - 9; |
1181 | else |
1185 | else |
1182 | radeon_vm_block_size = (bits + 3) / 2; |
1186 | radeon_vm_block_size = (bits + 3) / 2; |
1183 | 1187 | ||
1184 | } else if (radeon_vm_block_size < 9) { |
1188 | } else if (radeon_vm_block_size < 9) { |
1185 | dev_warn(rdev->dev, "VM page table size (%d) too small\n", |
1189 | dev_warn(rdev->dev, "VM page table size (%d) too small\n", |
1186 | radeon_vm_block_size); |
1190 | radeon_vm_block_size); |
1187 | radeon_vm_block_size = 9; |
1191 | radeon_vm_block_size = 9; |
1188 | } |
1192 | } |
1189 | 1193 | ||
1190 | if (radeon_vm_block_size > 24 || |
1194 | if (radeon_vm_block_size > 24 || |
1191 | (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { |
1195 | (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { |
1192 | dev_warn(rdev->dev, "VM page table size (%d) too large\n", |
1196 | dev_warn(rdev->dev, "VM page table size (%d) too large\n", |
1193 | radeon_vm_block_size); |
1197 | radeon_vm_block_size); |
1194 | radeon_vm_block_size = 9; |
1198 | radeon_vm_block_size = 9; |
1195 | } |
1199 | } |
1196 | } |
1200 | } |
1197 | 1201 | ||
1198 | /** |
1202 | /** |
1199 | * radeon_device_init - initialize the driver |
1203 | * radeon_device_init - initialize the driver |
1200 | * |
1204 | * |
1201 | * @rdev: radeon_device pointer |
1205 | * @rdev: radeon_device pointer |
1202 | * @pdev: drm dev pointer |
1206 | * @pdev: drm dev pointer |
1203 | * @pdev: pci dev pointer |
1207 | * @pdev: pci dev pointer |
1204 | * @flags: driver flags |
1208 | * @flags: driver flags |
1205 | * |
1209 | * |
1206 | * Initializes the driver info and hw (all asics). |
1210 | * Initializes the driver info and hw (all asics). |
1207 | * Returns 0 for success or an error on failure. |
1211 | * Returns 0 for success or an error on failure. |
1208 | * Called at driver startup. |
1212 | * Called at driver startup. |
1209 | */ |
1213 | */ |
1210 | int radeon_device_init(struct radeon_device *rdev, |
1214 | int radeon_device_init(struct radeon_device *rdev, |
1211 | struct drm_device *ddev, |
1215 | struct drm_device *ddev, |
1212 | struct pci_dev *pdev, |
1216 | struct pci_dev *pdev, |
1213 | uint32_t flags) |
1217 | uint32_t flags) |
1214 | { |
1218 | { |
1215 | int r, i; |
1219 | int r, i; |
1216 | int dma_bits; |
1220 | int dma_bits; |
1217 | bool runtime = false; |
1221 | bool runtime = false; |
1218 | 1222 | ||
1219 | rdev->shutdown = false; |
1223 | rdev->shutdown = false; |
1220 | rdev->dev = &pdev->dev; |
1224 | rdev->dev = &pdev->dev; |
1221 | rdev->ddev = ddev; |
1225 | rdev->ddev = ddev; |
1222 | rdev->pdev = pdev; |
1226 | rdev->pdev = pdev; |
1223 | rdev->flags = flags; |
1227 | rdev->flags = flags; |
1224 | rdev->family = flags & RADEON_FAMILY_MASK; |
1228 | rdev->family = flags & RADEON_FAMILY_MASK; |
1225 | rdev->is_atom_bios = false; |
1229 | rdev->is_atom_bios = false; |
1226 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
1230 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
1227 | rdev->mc.gtt_size = 512 * 1024 * 1024; |
1231 | rdev->mc.gtt_size = 512 * 1024 * 1024; |
1228 | rdev->accel_working = false; |
1232 | rdev->accel_working = false; |
1229 | /* set up ring ids */ |
1233 | /* set up ring ids */ |
1230 | for (i = 0; i < RADEON_NUM_RINGS; i++) { |
1234 | for (i = 0; i < RADEON_NUM_RINGS; i++) { |
1231 | rdev->ring[i].idx = i; |
1235 | rdev->ring[i].idx = i; |
1232 | } |
1236 | } |
1233 | 1237 | ||
1234 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", |
1238 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", |
1235 | radeon_family_name[rdev->family], pdev->vendor, pdev->device, |
1239 | radeon_family_name[rdev->family], pdev->vendor, pdev->device, |
1236 | pdev->subsystem_vendor, pdev->subsystem_device); |
1240 | pdev->subsystem_vendor, pdev->subsystem_device); |
1237 | 1241 | ||
1238 | /* mutex initialization are all done here so we |
1242 | /* mutex initialization are all done here so we |
1239 | * can recall function without having locking issues */ |
1243 | * can recall function without having locking issues */ |
1240 | mutex_init(&rdev->ring_lock); |
1244 | mutex_init(&rdev->ring_lock); |
1241 | mutex_init(&rdev->dc_hw_i2c_mutex); |
1245 | mutex_init(&rdev->dc_hw_i2c_mutex); |
1242 | atomic_set(&rdev->ih.lock, 0); |
1246 | atomic_set(&rdev->ih.lock, 0); |
1243 | mutex_init(&rdev->gem.mutex); |
1247 | mutex_init(&rdev->gem.mutex); |
1244 | mutex_init(&rdev->pm.mutex); |
1248 | mutex_init(&rdev->pm.mutex); |
1245 | mutex_init(&rdev->gpu_clock_mutex); |
1249 | mutex_init(&rdev->gpu_clock_mutex); |
1246 | mutex_init(&rdev->srbm_mutex); |
1250 | mutex_init(&rdev->srbm_mutex); |
1247 | // init_rwsem(&rdev->pm.mclk_lock); |
1251 | // init_rwsem(&rdev->pm.mclk_lock); |
1248 | // init_rwsem(&rdev->exclusive_lock); |
1252 | // init_rwsem(&rdev->exclusive_lock); |
1249 | init_waitqueue_head(&rdev->irq.vblank_queue); |
1253 | init_waitqueue_head(&rdev->irq.vblank_queue); |
1250 | r = radeon_gem_init(rdev); |
1254 | r = radeon_gem_init(rdev); |
1251 | if (r) |
1255 | if (r) |
1252 | return r; |
1256 | return r; |
1253 | 1257 | ||
1254 | radeon_check_arguments(rdev); |
1258 | radeon_check_arguments(rdev); |
1255 | /* Adjust VM size here. |
1259 | /* Adjust VM size here. |
1256 | * Max GPUVM size for cayman+ is 40 bits. |
1260 | * Max GPUVM size for cayman+ is 40 bits. |
1257 | */ |
1261 | */ |
1258 | rdev->vm_manager.max_pfn = radeon_vm_size << 18; |
1262 | rdev->vm_manager.max_pfn = radeon_vm_size << 18; |
1259 | 1263 | ||
1260 | /* Set asic functions */ |
1264 | /* Set asic functions */ |
1261 | r = radeon_asic_init(rdev); |
1265 | r = radeon_asic_init(rdev); |
1262 | if (r) |
1266 | if (r) |
1263 | return r; |
1267 | return r; |
1264 | 1268 | ||
1265 | /* all of the newer IGP chips have an internal gart |
1269 | /* all of the newer IGP chips have an internal gart |
1266 | * However some rs4xx report as AGP, so remove that here. |
1270 | * However some rs4xx report as AGP, so remove that here. |
1267 | */ |
1271 | */ |
1268 | if ((rdev->family >= CHIP_RS400) && |
1272 | if ((rdev->family >= CHIP_RS400) && |
1269 | (rdev->flags & RADEON_IS_IGP)) { |
1273 | (rdev->flags & RADEON_IS_IGP)) { |
1270 | rdev->flags &= ~RADEON_IS_AGP; |
1274 | rdev->flags &= ~RADEON_IS_AGP; |
1271 | } |
1275 | } |
1272 | 1276 | ||
1273 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
1277 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
1274 | radeon_agp_disable(rdev); |
1278 | radeon_agp_disable(rdev); |
1275 | } |
1279 | } |
1276 | 1280 | ||
1277 | /* Set the internal MC address mask |
1281 | /* Set the internal MC address mask |
1278 | * This is the max address of the GPU's |
1282 | * This is the max address of the GPU's |
1279 | * internal address space. |
1283 | * internal address space. |
1280 | */ |
1284 | */ |
1281 | if (rdev->family >= CHIP_CAYMAN) |
1285 | if (rdev->family >= CHIP_CAYMAN) |
1282 | rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ |
1286 | rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ |
1283 | else if (rdev->family >= CHIP_CEDAR) |
1287 | else if (rdev->family >= CHIP_CEDAR) |
1284 | rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ |
1288 | rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ |
1285 | else |
1289 | else |
1286 | rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ |
1290 | rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ |
1287 | 1291 | ||
1288 | /* set DMA mask + need_dma32 flags. |
1292 | /* set DMA mask + need_dma32 flags. |
1289 | * PCIE - can handle 40-bits. |
1293 | * PCIE - can handle 40-bits. |
1290 | * IGP - can handle 40-bits |
1294 | * IGP - can handle 40-bits |
1291 | * AGP - generally dma32 is safest |
1295 | * AGP - generally dma32 is safest |
1292 | * PCI - dma32 for legacy pci gart, 40 bits on newer asics |
1296 | * PCI - dma32 for legacy pci gart, 40 bits on newer asics |
1293 | */ |
1297 | */ |
1294 | rdev->need_dma32 = false; |
1298 | rdev->need_dma32 = false; |
1295 | if (rdev->flags & RADEON_IS_AGP) |
1299 | if (rdev->flags & RADEON_IS_AGP) |
1296 | rdev->need_dma32 = true; |
1300 | rdev->need_dma32 = true; |
1297 | if ((rdev->flags & RADEON_IS_PCI) && |
1301 | if ((rdev->flags & RADEON_IS_PCI) && |
1298 | (rdev->family <= CHIP_RS740)) |
1302 | (rdev->family <= CHIP_RS740)) |
1299 | rdev->need_dma32 = true; |
1303 | rdev->need_dma32 = true; |
1300 | 1304 | ||
1301 | dma_bits = rdev->need_dma32 ? 32 : 40; |
1305 | dma_bits = rdev->need_dma32 ? 32 : 40; |
1302 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
1306 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
1303 | if (r) { |
1307 | if (r) { |
1304 | rdev->need_dma32 = true; |
1308 | rdev->need_dma32 = true; |
1305 | dma_bits = 32; |
1309 | dma_bits = 32; |
1306 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
1310 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
1307 | } |
1311 | } |
1308 | 1312 | ||
1309 | /* Registers mapping */ |
1313 | /* Registers mapping */ |
1310 | /* TODO: block userspace mapping of io register */ |
1314 | /* TODO: block userspace mapping of io register */ |
1311 | spin_lock_init(&rdev->mmio_idx_lock); |
1315 | spin_lock_init(&rdev->mmio_idx_lock); |
1312 | spin_lock_init(&rdev->smc_idx_lock); |
1316 | spin_lock_init(&rdev->smc_idx_lock); |
1313 | spin_lock_init(&rdev->pll_idx_lock); |
1317 | spin_lock_init(&rdev->pll_idx_lock); |
1314 | spin_lock_init(&rdev->mc_idx_lock); |
1318 | spin_lock_init(&rdev->mc_idx_lock); |
1315 | spin_lock_init(&rdev->pcie_idx_lock); |
1319 | spin_lock_init(&rdev->pcie_idx_lock); |
1316 | spin_lock_init(&rdev->pciep_idx_lock); |
1320 | spin_lock_init(&rdev->pciep_idx_lock); |
1317 | spin_lock_init(&rdev->pif_idx_lock); |
1321 | spin_lock_init(&rdev->pif_idx_lock); |
1318 | spin_lock_init(&rdev->cg_idx_lock); |
1322 | spin_lock_init(&rdev->cg_idx_lock); |
1319 | spin_lock_init(&rdev->uvd_idx_lock); |
1323 | spin_lock_init(&rdev->uvd_idx_lock); |
1320 | spin_lock_init(&rdev->rcu_idx_lock); |
1324 | spin_lock_init(&rdev->rcu_idx_lock); |
1321 | spin_lock_init(&rdev->didt_idx_lock); |
1325 | spin_lock_init(&rdev->didt_idx_lock); |
1322 | spin_lock_init(&rdev->end_idx_lock); |
1326 | spin_lock_init(&rdev->end_idx_lock); |
1323 | if (rdev->family >= CHIP_BONAIRE) { |
1327 | if (rdev->family >= CHIP_BONAIRE) { |
1324 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); |
1328 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); |
1325 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); |
1329 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); |
1326 | } else { |
1330 | } else { |
1327 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
1331 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
1328 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
1332 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
1329 | } |
1333 | } |
1330 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
1334 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
1331 | if (rdev->rmmio == NULL) { |
1335 | if (rdev->rmmio == NULL) { |
1332 | return -ENOMEM; |
1336 | return -ENOMEM; |
1333 | } |
1337 | } |
1334 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
1338 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
1335 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
1339 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
1336 | 1340 | ||
1337 | /* doorbell bar mapping */ |
1341 | /* doorbell bar mapping */ |
1338 | if (rdev->family >= CHIP_BONAIRE) |
1342 | if (rdev->family >= CHIP_BONAIRE) |
1339 | radeon_doorbell_init(rdev); |
1343 | radeon_doorbell_init(rdev); |
1340 | 1344 | ||
1341 | /* io port mapping */ |
1345 | /* io port mapping */ |
1342 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
1346 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
1343 | if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { |
1347 | if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { |
1344 | rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); |
1348 | rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); |
1345 | rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); |
1349 | rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); |
1346 | break; |
1350 | break; |
1347 | } |
1351 | } |
1348 | } |
1352 | } |
1349 | if (rdev->rio_mem == NULL) |
1353 | if (rdev->rio_mem == NULL) |
1350 | DRM_ERROR("Unable to find PCI I/O BAR\n"); |
1354 | DRM_ERROR("Unable to find PCI I/O BAR\n"); |
1351 | 1355 | ||
1352 | if (rdev->flags & RADEON_IS_PX) |
1356 | if (rdev->flags & RADEON_IS_PX) |
1353 | radeon_device_handle_px_quirks(rdev); |
1357 | radeon_device_handle_px_quirks(rdev); |
1354 | if (rdev->flags & RADEON_IS_PX) |
1358 | if (rdev->flags & RADEON_IS_PX) |
1355 | runtime = true; |
1359 | runtime = true; |
1356 | 1360 | ||
1357 | r = radeon_init(rdev); |
1361 | r = radeon_init(rdev); |
1358 | if (r) |
1362 | if (r) |
1359 | return r; |
1363 | return r; |
1360 | 1364 | ||
1361 | r = radeon_ib_ring_tests(rdev); |
1365 | r = radeon_ib_ring_tests(rdev); |
1362 | if (r) |
1366 | if (r) |
1363 | DRM_ERROR("ib ring test failed (%d).\n", r); |
1367 | DRM_ERROR("ib ring test failed (%d).\n", r); |
1364 | 1368 | ||
1365 | 1369 | ||
1366 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
1370 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
1367 | /* Acceleration not working on AGP card try again |
1371 | /* Acceleration not working on AGP card try again |
1368 | * with fallback to PCI or PCIE GART |
1372 | * with fallback to PCI or PCIE GART |
1369 | */ |
1373 | */ |
1370 | radeon_asic_reset(rdev); |
1374 | radeon_asic_reset(rdev); |
1371 | radeon_fini(rdev); |
1375 | radeon_fini(rdev); |
1372 | radeon_agp_disable(rdev); |
1376 | radeon_agp_disable(rdev); |
1373 | r = radeon_init(rdev); |
1377 | r = radeon_init(rdev); |
1374 | if (r) |
1378 | if (r) |
1375 | return r; |
1379 | return r; |
1376 | } |
1380 | } |
1377 | 1381 | ||
1378 | if ((radeon_testing & 1)) { |
1382 | if ((radeon_testing & 1)) { |
1379 | if (rdev->accel_working) |
1383 | if (rdev->accel_working) |
1380 | radeon_test_moves(rdev); |
1384 | radeon_test_moves(rdev); |
1381 | else |
1385 | else |
1382 | DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); |
1386 | DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); |
1383 | } |
1387 | } |
1384 | if ((radeon_testing & 2)) { |
1388 | if ((radeon_testing & 2)) { |
1385 | if (rdev->accel_working) |
1389 | if (rdev->accel_working) |
1386 | radeon_test_syncing(rdev); |
1390 | radeon_test_syncing(rdev); |
1387 | else |
1391 | else |
1388 | DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); |
1392 | DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); |
1389 | } |
1393 | } |
1390 | if (radeon_benchmarking) { |
1394 | if (radeon_benchmarking) { |
1391 | if (rdev->accel_working) |
1395 | if (rdev->accel_working) |
1392 | radeon_benchmark(rdev, radeon_benchmarking); |
1396 | radeon_benchmark(rdev, radeon_benchmarking); |
1393 | else |
1397 | else |
1394 | DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); |
1398 | DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); |
1395 | } |
1399 | } |
1396 | return 0; |
1400 | return 0; |
1397 | } |
1401 | } |
1398 | 1402 | ||
1399 | /** |
1403 | /** |
1400 | * radeon_gpu_reset - reset the asic |
1404 | * radeon_gpu_reset - reset the asic |
1401 | * |
1405 | * |
1402 | * @rdev: radeon device pointer |
1406 | * @rdev: radeon device pointer |
1403 | * |
1407 | * |
1404 | * Attempt the reset the GPU if it has hung (all asics). |
1408 | * Attempt the reset the GPU if it has hung (all asics). |
1405 | * Returns 0 for success or an error on failure. |
1409 | * Returns 0 for success or an error on failure. |
1406 | */ |
1410 | */ |
1407 | int radeon_gpu_reset(struct radeon_device *rdev) |
1411 | int radeon_gpu_reset(struct radeon_device *rdev) |
1408 | { |
1412 | { |
1409 | unsigned ring_sizes[RADEON_NUM_RINGS]; |
1413 | unsigned ring_sizes[RADEON_NUM_RINGS]; |
1410 | uint32_t *ring_data[RADEON_NUM_RINGS]; |
1414 | uint32_t *ring_data[RADEON_NUM_RINGS]; |
1411 | 1415 | ||
1412 | bool saved = false; |
1416 | bool saved = false; |
1413 | 1417 | ||
1414 | int i, r; |
1418 | int i, r; |
1415 | int resched; |
1419 | int resched; |
1416 | 1420 | ||
1417 | // down_write(&rdev->exclusive_lock); |
1421 | // down_write(&rdev->exclusive_lock); |
1418 | rdev->needs_reset = false; |
1422 | rdev->needs_reset = false; |
1419 | 1423 | ||
1420 | radeon_save_bios_scratch_regs(rdev); |
1424 | radeon_save_bios_scratch_regs(rdev); |
1421 | /* block TTM */ |
1425 | /* block TTM */ |
1422 | // resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
1426 | // resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
1423 | radeon_suspend(rdev); |
1427 | radeon_suspend(rdev); |
1424 | 1428 | ||
1425 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
1429 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
1426 | ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], |
1430 | ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], |
1427 | &ring_data[i]); |
1431 | &ring_data[i]); |
1428 | if (ring_sizes[i]) { |
1432 | if (ring_sizes[i]) { |
1429 | saved = true; |
1433 | saved = true; |
1430 | dev_info(rdev->dev, "Saved %d dwords of commands " |
1434 | dev_info(rdev->dev, "Saved %d dwords of commands " |
1431 | "on ring %d.\n", ring_sizes[i], i); |
1435 | "on ring %d.\n", ring_sizes[i], i); |
1432 | } |
1436 | } |
1433 | } |
1437 | } |
1434 | 1438 | ||
1435 | retry: |
1439 | retry: |
1436 | r = radeon_asic_reset(rdev); |
1440 | r = radeon_asic_reset(rdev); |
1437 | if (!r) { |
1441 | if (!r) { |
1438 | dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); |
1442 | dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); |
1439 | radeon_resume(rdev); |
1443 | radeon_resume(rdev); |
1440 | } |
1444 | } |
1441 | 1445 | ||
1442 | radeon_restore_bios_scratch_regs(rdev); |
1446 | radeon_restore_bios_scratch_regs(rdev); |
1443 | 1447 | ||
1444 | if (!r) { |
1448 | if (!r) { |
1445 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
1449 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
1446 | radeon_ring_restore(rdev, &rdev->ring[i], |
1450 | radeon_ring_restore(rdev, &rdev->ring[i], |
1447 | ring_sizes[i], ring_data[i]); |
1451 | ring_sizes[i], ring_data[i]); |
1448 | ring_sizes[i] = 0; |
1452 | ring_sizes[i] = 0; |
1449 | ring_data[i] = NULL; |
1453 | ring_data[i] = NULL; |
1450 | } |
1454 | } |
1451 | 1455 | ||
1452 | // r = radeon_ib_ring_tests(rdev); |
1456 | // r = radeon_ib_ring_tests(rdev); |
1453 | // if (r) { |
1457 | // if (r) { |
1454 | // dev_err(rdev->dev, "ib ring test failed (%d).\n", r); |
1458 | // dev_err(rdev->dev, "ib ring test failed (%d).\n", r); |
1455 | // if (saved) { |
1459 | // if (saved) { |
1456 | // saved = false; |
1460 | // saved = false; |
1457 | // radeon_suspend(rdev); |
1461 | // radeon_suspend(rdev); |
1458 | // goto retry; |
1462 | // goto retry; |
1459 | // } |
1463 | // } |
1460 | // } |
1464 | // } |
1461 | } else { |
1465 | } else { |
1462 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
1466 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
1463 | kfree(ring_data[i]); |
1467 | kfree(ring_data[i]); |
1464 | } |
1468 | } |
1465 | } |
1469 | } |
1466 | 1470 | ||
1467 | // ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
1471 | // ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
1468 | if (r) { |
1472 | if (r) { |
1469 | /* bad news, how to tell it to userspace ? */ |
1473 | /* bad news, how to tell it to userspace ? */ |
1470 | dev_info(rdev->dev, "GPU reset failed\n"); |
1474 | dev_info(rdev->dev, "GPU reset failed\n"); |
1471 | } |
1475 | } |
1472 | 1476 | ||
1473 | // up_write(&rdev->exclusive_lock); |
1477 | // up_write(&rdev->exclusive_lock); |
1474 | return r; |
1478 | return r; |
1475 | } |
1479 | } |
1476 | 1480 | ||
1477 | 1481 | ||
1478 | /* |
1482 | /* |
1479 | * Driver load/unload |
1483 | * Driver load/unload |
1480 | */ |
1484 | */ |
1481 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
1485 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
1482 | { |
1486 | { |
1483 | struct radeon_device *rdev; |
1487 | struct radeon_device *rdev; |
1484 | int r; |
1488 | int r; |
1485 | 1489 | ||
1486 | 1490 | ||
1487 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1491 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1488 | if (rdev == NULL) { |
1492 | if (rdev == NULL) { |
1489 | return -ENOMEM; |
1493 | return -ENOMEM; |
1490 | }; |
1494 | }; |
1491 | 1495 | ||
1492 | dev->dev_private = (void *)rdev; |
1496 | dev->dev_private = (void *)rdev; |
1493 | 1497 | ||
1494 | /* update BUS flag */ |
1498 | /* update BUS flag */ |
1495 | if (drm_pci_device_is_agp(dev)) { |
1499 | if (drm_pci_device_is_agp(dev)) { |
1496 | flags |= RADEON_IS_AGP; |
1500 | flags |= RADEON_IS_AGP; |
1497 | } else if (drm_device_is_pcie(dev)) { |
1501 | } else if (drm_device_is_pcie(dev)) { |
1498 | flags |= RADEON_IS_PCIE; |
1502 | flags |= RADEON_IS_PCIE; |
1499 | } else { |
1503 | } else { |
1500 | flags |= RADEON_IS_PCI; |
1504 | flags |= RADEON_IS_PCI; |
1501 | } |
1505 | } |
1502 | 1506 | ||
1503 | /* radeon_device_init should report only fatal error |
1507 | /* radeon_device_init should report only fatal error |
1504 | * like memory allocation failure or iomapping failure, |
1508 | * like memory allocation failure or iomapping failure, |
1505 | * or memory manager initialization failure, it must |
1509 | * or memory manager initialization failure, it must |
1506 | * properly initialize the GPU MC controller and permit |
1510 | * properly initialize the GPU MC controller and permit |
1507 | * VRAM allocation |
1511 | * VRAM allocation |
1508 | */ |
1512 | */ |
1509 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
1513 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
1510 | if (r) { |
1514 | if (r) { |
1511 | DRM_ERROR("Fatal error while trying to initialize radeon.\n"); |
1515 | DRM_ERROR("Fatal error while trying to initialize radeon.\n"); |
1512 | return r; |
1516 | return r; |
1513 | } |
1517 | } |
1514 | /* Again modeset_init should fail only on fatal error |
1518 | /* Again modeset_init should fail only on fatal error |
1515 | * otherwise it should provide enough functionalities |
1519 | * otherwise it should provide enough functionalities |
1516 | * for shadowfb to run |
1520 | * for shadowfb to run |
1517 | */ |
1521 | */ |
1518 | main_device = dev; |
1522 | main_device = dev; |
1519 | 1523 | ||
1520 | if( radeon_modeset ) |
1524 | if( radeon_modeset ) |
1521 | { |
1525 | { |
1522 | r = radeon_modeset_init(rdev); |
1526 | r = radeon_modeset_init(rdev); |
1523 | if (r) { |
1527 | if (r) { |
1524 | return r; |
1528 | return r; |
1525 | } |
1529 | } |
1526 | init_display_kms(dev, &usermode); |
1530 | init_display_kms(dev, &usermode); |
1527 | } |
1531 | } |
1528 | else |
1532 | else |
1529 | init_display(rdev, &usermode); |
1533 | init_display(rdev, &usermode); |
1530 | 1534 | ||
1531 | return 0; |
1535 | return 0; |
1532 | } |
1536 | } |
1533 | 1537 | ||
1534 | 1538 | ||
1535 | 1539 | ||
1536 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
1540 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
1537 | { |
1541 | { |
1538 | return pci_resource_start(dev->pdev, resource); |
1542 | return pci_resource_start(dev->pdev, resource); |
1539 | } |
1543 | } |
1540 | 1544 | ||
1541 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
1545 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
1542 | { |
1546 | { |
1543 | return pci_resource_len(dev->pdev, resource); |
1547 | return pci_resource_len(dev->pdev, resource); |
1544 | } |
1548 | } |
1545 | 1549 | ||
1546 | 1550 | ||
1547 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
1551 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
1548 | { |
1552 | { |
1549 | uint64_t rem = *n; |
1553 | uint64_t rem = *n; |
1550 | uint64_t b = base; |
1554 | uint64_t b = base; |
1551 | uint64_t res, d = 1; |
1555 | uint64_t res, d = 1; |
1552 | uint32_t high = rem >> 32; |
1556 | uint32_t high = rem >> 32; |
1553 | 1557 | ||
1554 | /* Reduce the thing a bit first */ |
1558 | /* Reduce the thing a bit first */ |
1555 | res = 0; |
1559 | res = 0; |
1556 | if (high >= base) { |
1560 | if (high >= base) { |
1557 | high /= base; |
1561 | high /= base; |
1558 | res = (uint64_t) high << 32; |
1562 | res = (uint64_t) high << 32; |
1559 | rem -= (uint64_t) (high*base) << 32; |
1563 | rem -= (uint64_t) (high*base) << 32; |
1560 | } |
1564 | } |
1561 | 1565 | ||
1562 | while ((int64_t)b > 0 && b < rem) { |
1566 | while ((int64_t)b > 0 && b < rem) { |
1563 | b = b+b; |
1567 | b = b+b; |
1564 | d = d+d; |
1568 | d = d+d; |
1565 | } |
1569 | } |
1566 | 1570 | ||
1567 | do { |
1571 | do { |
1568 | if (rem >= b) { |
1572 | if (rem >= b) { |
1569 | rem -= b; |
1573 | rem -= b; |
1570 | res += d; |
1574 | res += d; |
1571 | } |
1575 | } |
1572 | b >>= 1; |
1576 | b >>= 1; |
1573 | d >>= 1; |
1577 | d >>= 1; |
1574 | } while (d); |
1578 | } while (d); |
1575 | 1579 | ||
1576 | *n = res; |
1580 | *n = res; |
1577 | return rem; |
1581 | return rem; |
1578 | } |
1582 | } |
1579 | 1583 | ||
1580 | static struct pci_device_id pciidlist[] = { |
1584 | static struct pci_device_id pciidlist[] = { |
1581 | radeon_PCI_IDS |
1585 | radeon_PCI_IDS |
1582 | }; |
1586 | }; |
1583 | 1587 | ||
1584 | void radeon_driver_irq_preinstall_kms(struct drm_device *dev); |
1588 | void radeon_driver_irq_preinstall_kms(struct drm_device *dev); |
1585 | int radeon_driver_irq_postinstall_kms(struct drm_device *dev); |
1589 | int radeon_driver_irq_postinstall_kms(struct drm_device *dev); |
1586 | void radeon_driver_irq_uninstall_kms(struct drm_device *dev); |
1590 | void radeon_driver_irq_uninstall_kms(struct drm_device *dev); |
1587 | irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); |
1591 | irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); |
1588 | 1592 | ||
1589 | 1593 | ||
1590 | static struct drm_driver kms_driver = { |
1594 | static struct drm_driver kms_driver = { |
1591 | .driver_features = |
1595 | .driver_features = |
1592 | DRIVER_USE_AGP | |
1596 | DRIVER_USE_AGP | |
1593 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | |
1597 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | |
1594 | DRIVER_PRIME | DRIVER_RENDER, |
1598 | DRIVER_PRIME | DRIVER_RENDER, |
1595 | .load = radeon_driver_load_kms, |
1599 | .load = radeon_driver_load_kms, |
1596 | // .open = radeon_driver_open_kms, |
1600 | // .open = radeon_driver_open_kms, |
1597 | // .preclose = radeon_driver_preclose_kms, |
1601 | // .preclose = radeon_driver_preclose_kms, |
1598 | // .postclose = radeon_driver_postclose_kms, |
1602 | // .postclose = radeon_driver_postclose_kms, |
1599 | // .lastclose = radeon_driver_lastclose_kms, |
1603 | // .lastclose = radeon_driver_lastclose_kms, |
1600 | // .unload = radeon_driver_unload_kms, |
1604 | // .unload = radeon_driver_unload_kms, |
1601 | // .get_vblank_counter = radeon_get_vblank_counter_kms, |
1605 | // .get_vblank_counter = radeon_get_vblank_counter_kms, |
1602 | // .enable_vblank = radeon_enable_vblank_kms, |
1606 | // .enable_vblank = radeon_enable_vblank_kms, |
1603 | // .disable_vblank = radeon_disable_vblank_kms, |
1607 | // .disable_vblank = radeon_disable_vblank_kms, |
1604 | // .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, |
1608 | // .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, |
1605 | // .get_scanout_position = radeon_get_crtc_scanoutpos, |
1609 | // .get_scanout_position = radeon_get_crtc_scanoutpos, |
1606 | #if defined(CONFIG_DEBUG_FS) |
1610 | #if defined(CONFIG_DEBUG_FS) |
1607 | .debugfs_init = radeon_debugfs_init, |
1611 | .debugfs_init = radeon_debugfs_init, |
1608 | .debugfs_cleanup = radeon_debugfs_cleanup, |
1612 | .debugfs_cleanup = radeon_debugfs_cleanup, |
1609 | #endif |
1613 | #endif |
1610 | .irq_preinstall = radeon_driver_irq_preinstall_kms, |
1614 | .irq_preinstall = radeon_driver_irq_preinstall_kms, |
1611 | .irq_postinstall = radeon_driver_irq_postinstall_kms, |
1615 | .irq_postinstall = radeon_driver_irq_postinstall_kms, |
1612 | .irq_uninstall = radeon_driver_irq_uninstall_kms, |
1616 | .irq_uninstall = radeon_driver_irq_uninstall_kms, |
1613 | .irq_handler = radeon_driver_irq_handler_kms, |
1617 | .irq_handler = radeon_driver_irq_handler_kms, |
1614 | // .ioctls = radeon_ioctls_kms, |
1618 | // .ioctls = radeon_ioctls_kms, |
1615 | // .gem_free_object = radeon_gem_object_free, |
1619 | // .gem_free_object = radeon_gem_object_free, |
1616 | // .gem_open_object = radeon_gem_object_open, |
1620 | // .gem_open_object = radeon_gem_object_open, |
1617 | // .gem_close_object = radeon_gem_object_close, |
1621 | // .gem_close_object = radeon_gem_object_close, |
1618 | // .dumb_create = radeon_mode_dumb_create, |
1622 | // .dumb_create = radeon_mode_dumb_create, |
1619 | // .dumb_map_offset = radeon_mode_dumb_mmap, |
1623 | // .dumb_map_offset = radeon_mode_dumb_mmap, |
1620 | // .dumb_destroy = drm_gem_dumb_destroy, |
1624 | // .dumb_destroy = drm_gem_dumb_destroy, |
1621 | // .fops = &radeon_driver_kms_fops, |
1625 | // .fops = &radeon_driver_kms_fops, |
1622 | 1626 | ||
1623 | // .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
1627 | // .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
1624 | // .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
1628 | // .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
1625 | // .gem_prime_export = drm_gem_prime_export, |
1629 | // .gem_prime_export = drm_gem_prime_export, |
1626 | // .gem_prime_import = drm_gem_prime_import, |
1630 | // .gem_prime_import = drm_gem_prime_import, |
1627 | // .gem_prime_pin = radeon_gem_prime_pin, |
1631 | // .gem_prime_pin = radeon_gem_prime_pin, |
1628 | // .gem_prime_unpin = radeon_gem_prime_unpin, |
1632 | // .gem_prime_unpin = radeon_gem_prime_unpin, |
1629 | // .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, |
1633 | // .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, |
1630 | // .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, |
1634 | // .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, |
1631 | // .gem_prime_vmap = radeon_gem_prime_vmap, |
1635 | // .gem_prime_vmap = radeon_gem_prime_vmap, |
1632 | // .gem_prime_vunmap = radeon_gem_prime_vunmap, |
1636 | // .gem_prime_vunmap = radeon_gem_prime_vunmap, |
1633 | 1637 | ||
1634 | }; |
1638 | }; |
1635 | 1639 | ||
1636 | int ati_init(void) |
1640 | int ati_init(void) |
1637 | { |
1641 | { |
1638 | static pci_dev_t device; |
1642 | static pci_dev_t device; |
1639 | const struct pci_device_id *ent; |
1643 | const struct pci_device_id *ent; |
1640 | int err; |
1644 | int err; |
1641 | 1645 | ||
1642 | ent = find_pci_device(&device, pciidlist); |
1646 | ent = find_pci_device(&device, pciidlist); |
1643 | if( unlikely(ent == NULL) ) |
1647 | if( unlikely(ent == NULL) ) |
1644 | { |
1648 | { |
1645 | dbgprintf("device not found\n"); |
1649 | dbgprintf("device not found\n"); |
1646 | return -ENODEV; |
1650 | return -ENODEV; |
1647 | }; |
1651 | }; |
1648 | 1652 | ||
1649 | drm_core_init(); |
1653 | drm_core_init(); |
1650 | 1654 | ||
1651 | DRM_INFO("device %x:%x\n", device.pci_dev.vendor, |
1655 | DRM_INFO("device %x:%x\n", device.pci_dev.vendor, |
1652 | device.pci_dev.device); |
1656 | device.pci_dev.device); |
1653 | 1657 | ||
1654 | kms_driver.driver_features |= DRIVER_MODESET; |
1658 | kms_driver.driver_features |= DRIVER_MODESET; |
1655 | 1659 | ||
1656 | err = drm_get_pci_dev(&device.pci_dev, ent, &kms_driver); |
1660 | err = drm_get_pci_dev(&device.pci_dev, ent, &kms_driver); |
1657 | 1661 | ||
1658 | return err; |
1662 | return err; |
1659 | }>><>><>>>>>=>><>>><>>>=>>><>>>=>><>>>>>>>>>>>><>><> |
1663 | }>><>><>>>>>=>><>>><>>>=>>><>>>=>><>>>>>>>>>>>><>><> |