WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_device.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
//#include 
#include 
#include 
#include 
#include 
#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"
 
#include "bitmap.h"
#include "display.h"
 
 
#include 
 
#define PCI_VENDOR_ID_ATI               0x1002
#define PCI_VENDOR_ID_APPLE             0x106b
 
int radeon_no_wb;
int radeon_modeset = -1;
int radeon_dynclks = -1;
int radeon_r4xx_atom = 0;
int radeon_agpmode = 0;
int radeon_vram_limit = 0;
int radeon_gart_size = -1; /* auto */
int radeon_benchmarking = 0;
int radeon_testing = 0;
int radeon_connector_table = 0;
int radeon_tv = 1;
int radeon_audio = -1;
int radeon_disp_priority = 0;
int radeon_hw_i2c = 0;
int radeon_pcie_gen2 = -1;
int radeon_msi = -1;
int radeon_lockup_timeout = 10000;
int radeon_fastfb = 0;
int radeon_dpm = -1;
int radeon_aspm = -1;
int radeon_runtime_pm = -1;
int radeon_hard_reset = 0;
int radeon_vm_size = 8;
int radeon_vm_block_size = -1;
int radeon_deep_color = 0;
int radeon_use_pflipirq = 2;
int irq_override = 0;
int radeon_bapm = -1;
 
 
extern display_t *os_display;
extern struct drm_device *main_device;
extern videomode_t usermode;
 
 
void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms);
int init_display(struct radeon_device *rdev, videomode_t *mode);
int init_display_kms(struct drm_device *dev, videomode_t *usermode);
 
int get_modes(videomode_t *mode, u32_t *count);
int set_user_mode(videomode_t *mode);
int r100_2D_test(struct radeon_device *rdev);
 
 
 /* Legacy VGA regions */
#define VGA_RSRC_NONE          0x00
#define VGA_RSRC_LEGACY_IO     0x01
#define VGA_RSRC_LEGACY_MEM    0x02
#define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
/* Non-legacy access */
#define VGA_RSRC_NORMAL_IO     0x04
#define VGA_RSRC_NORMAL_MEM    0x08
 
 
static const char radeon_family_name[][16] = {
	"R100",
	"RV100",
	"RS100",
	"RV200",
	"RS200",
	"R200",
	"RV250",
	"RS300",
	"RV280",
	"R300",
	"R350",
	"RV350",
	"RV380",
	"R420",
	"R423",
	"RV410",
	"RS400",
	"RS480",
	"RS600",
	"RS690",
	"RS740",
	"RV515",
	"R520",
	"RV530",
	"RV560",
	"RV570",
	"R580",
	"R600",
	"RV610",
	"RV630",
	"RV670",
	"RV620",
	"RV635",
	"RS780",
	"RS880",
	"RV770",
	"RV730",
	"RV710",
	"RV740",
	"CEDAR",
	"REDWOOD",
	"JUNIPER",
	"CYPRESS",
	"HEMLOCK",
	"PALM",
	"SUMO",
	"SUMO2",
	"BARTS",
	"TURKS",
	"CAICOS",
	"CAYMAN",
	"ARUBA",
	"TAHITI",
	"PITCAIRN",
	"VERDE",
	"OLAND",
	"HAINAN",
	"BONAIRE",
	"KAVERI",
	"KABINI",
	"HAWAII",
	"MULLINS",
	"LAST",
};
 
#define RADEON_PX_QUIRK_DISABLE_PX  (1 << 0)
#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
 
struct radeon_px_quirk {
	u32 chip_vendor;
	u32 chip_device;
	u32 subsys_vendor;
	u32 subsys_device;
	u32 px_quirk_flags;
};
 
static struct radeon_px_quirk radeon_px_quirk_list[] = {
	/* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
	 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
	 */
	{ PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
	/* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
	 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
	 */
	{ PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
	/* macbook pro 8.2 */
	{ PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP },
	{ 0, 0, 0, 0, 0 },
};
 
bool radeon_is_px(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
 
	if (rdev->flags & RADEON_IS_PX)
		return true;
	return false;
}
 
static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
{
	struct radeon_px_quirk *p = radeon_px_quirk_list;
 
	/* Apply PX quirks */
	while (p && p->chip_device != 0) {
		if (rdev->pdev->vendor == p->chip_vendor &&
		    rdev->pdev->device == p->chip_device &&
		    rdev->pdev->subsystem_vendor == p->subsys_vendor &&
		    rdev->pdev->subsystem_device == p->subsys_device) {
			rdev->px_quirk_flags = p->px_quirk_flags;
			break;
		}
		++p;
	}
 
	if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
		rdev->flags &= ~RADEON_IS_PX;
}
 
/**
 * radeon_program_register_sequence - program an array of registers.
 *
 * @rdev: radeon_device pointer
 * @registers: pointer to the register array
 * @array_size: size of the register array
 *
 * Programs an array or registers with and and or masks.
 * This is a helper for setting golden registers.
 */
void radeon_program_register_sequence(struct radeon_device *rdev,
				      const u32 *registers,
				      const u32 array_size)
{
	u32 tmp, reg, and_mask, or_mask;
	int i;
 
	if (array_size % 3)
		return;
 
	for (i = 0; i < array_size; i +=3) {
		reg = registers[i + 0];
		and_mask = registers[i + 1];
		or_mask = registers[i + 2];
 
		if (and_mask == 0xffffffff) {
			tmp = or_mask;
		} else {
			tmp = RREG32(reg);
			tmp &= ~and_mask;
			tmp |= or_mask;
		}
		WREG32(reg, tmp);
	}
}
 
void radeon_pci_config_reset(struct radeon_device *rdev)
{
	pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
}
 
/**
 * radeon_surface_init - Clear GPU surface registers.
 *
 * @rdev: radeon_device pointer
 *
 * Clear GPU surface registers (r1xx-r5xx).
 */
void radeon_surface_init(struct radeon_device *rdev)
{
    /* FIXME: check this out */
    if (rdev->family < CHIP_R600) {
        int i;
 
		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
			if (rdev->surface_regs[i].bo)
				radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
			else
           radeon_clear_surface_reg(rdev, i);
        }
		/* enable surfaces */
		WREG32(RADEON_SURFACE_CNTL, 0);
    }
}
 
/*
 * GPU scratch registers helpers function.
 */
/**
 * radeon_scratch_init - Init scratch register driver information.
 *
 * @rdev: radeon_device pointer
 *
 * Init CP scratch register driver information (r1xx-r5xx)
 */
void radeon_scratch_init(struct radeon_device *rdev)
{
    int i;
 
    /* FIXME: check this out */
    if (rdev->family < CHIP_R300) {
        rdev->scratch.num_reg = 5;
    } else {
        rdev->scratch.num_reg = 7;
    }
	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
    for (i = 0; i < rdev->scratch.num_reg; i++) {
        rdev->scratch.free[i] = true;
		rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
    }
}
 
/**
 * radeon_scratch_get - Allocate a scratch register
 *
 * @rdev: radeon_device pointer
 * @reg: scratch register mmio offset
 *
 * Allocate a CP scratch register for use by the driver (all asics).
 * Returns 0 on success or -EINVAL on failure.
 */
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
{
	int i;
 
	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.free[i]) {
			rdev->scratch.free[i] = false;
			*reg = rdev->scratch.reg[i];
			return 0;
		}
	}
	return -EINVAL;
}
 
/**
 * radeon_scratch_free - Free a scratch register
 *
 * @rdev: radeon_device pointer
 * @reg: scratch register mmio offset
 *
 * Free a CP scratch register allocated for use by the driver (all asics)
 */
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
{
	int i;
 
	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.reg[i] == reg) {
			rdev->scratch.free[i] = true;
			return;
		}
	}
}
 
/*
 * GPU doorbell aperture helpers function.
 */
/**
 * radeon_doorbell_init - Init doorbell driver information.
 *
 * @rdev: radeon_device pointer
 *
 * Init doorbell driver information (CIK)
 * Returns 0 on success, error on failure.
 */
static int radeon_doorbell_init(struct radeon_device *rdev)
{
	/* doorbell bar mapping */
	rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
	rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
 
	rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
	if (rdev->doorbell.num_doorbells == 0)
		return -EINVAL;
 
	rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
	if (rdev->doorbell.ptr == NULL) {
		return -ENOMEM;
	}
	DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
	DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
 
	memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
 
	return 0;
}
 
/**
 * radeon_doorbell_fini - Tear down doorbell driver information.
 *
 * @rdev: radeon_device pointer
 *
 * Tear down doorbell driver information (CIK)
 */
static void radeon_doorbell_fini(struct radeon_device *rdev)
{
	iounmap(rdev->doorbell.ptr);
	rdev->doorbell.ptr = NULL;
}
 
/**
 * radeon_doorbell_get - Allocate a doorbell entry
 *
 * @rdev: radeon_device pointer
 * @doorbell: doorbell index
 *
 * Allocate a doorbell for use by the driver (all asics).
 * Returns 0 on success or -EINVAL on failure.
 */
int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
{
	unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
	if (offset < rdev->doorbell.num_doorbells) {
		__set_bit(offset, rdev->doorbell.used);
		*doorbell = offset;
		return 0;
	} else {
		return -EINVAL;
	}
}
 
/**
 * radeon_doorbell_free - Free a doorbell entry
 *
 * @rdev: radeon_device pointer
 * @doorbell: doorbell index
 *
 * Free a doorbell allocated for use by the driver (all asics)
 */
void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
{
	if (doorbell < rdev->doorbell.num_doorbells)
		__clear_bit(doorbell, rdev->doorbell.used);
}
 
/*
 * radeon_wb_*()
 * Writeback is the the method by which the the GPU updates special pages
 * in memory with the status of certain GPU events (fences, ring pointers,
 * etc.).
 */
 
/**
 * radeon_wb_disable - Disable Writeback
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback (all asics).  Used for suspend.
 */
void radeon_wb_disable(struct radeon_device *rdev)
{
	rdev->wb.enabled = false;
}
 
/**
 * radeon_wb_fini - Disable Writeback and free memory
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback and frees the Writeback memory (all asics).
 * Used at driver shutdown.
 */
void radeon_wb_fini(struct radeon_device *rdev)
{
	radeon_wb_disable(rdev);
	if (rdev->wb.wb_obj) {
		if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
			radeon_bo_kunmap(rdev->wb.wb_obj);
			radeon_bo_unpin(rdev->wb.wb_obj);
			radeon_bo_unreserve(rdev->wb.wb_obj);
		}
		radeon_bo_unref(&rdev->wb.wb_obj);
		rdev->wb.wb = NULL;
		rdev->wb.wb_obj = NULL;
	}
}
 
/**
 * radeon_wb_init- Init Writeback driver info and allocate memory
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback and frees the Writeback memory (all asics).
 * Used at driver startup.
 * Returns 0 on success or an -error on failure.
 */
int radeon_wb_init(struct radeon_device *rdev)
{
	int r;
 
	if (rdev->wb.wb_obj == NULL) {
		r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
				     RADEON_GEM_DOMAIN_GTT, 0, NULL,
				     &rdev->wb.wb_obj);
		if (r) {
			dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
			return r;
		}
	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
	if (unlikely(r != 0)) {
		radeon_wb_fini(rdev);
		return r;
	}
	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
			  &rdev->wb.gpu_addr);
	if (r) {
		radeon_bo_unreserve(rdev->wb.wb_obj);
		dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
		radeon_wb_fini(rdev);
		return r;
	}
	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
	radeon_bo_unreserve(rdev->wb.wb_obj);
	if (r) {
		dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
		radeon_wb_fini(rdev);
		return r;
	}
	}
 
	/* clear wb memory */
	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
	/* disable event_write fences */
	rdev->wb.use_event = false;
	/* disabled via module param */
	if (radeon_no_wb == 1) {
		rdev->wb.enabled = false;
	} else {
		if (rdev->flags & RADEON_IS_AGP) {
		/* often unreliable on AGP */
			rdev->wb.enabled = false;
		} else if (rdev->family < CHIP_R300) {
			/* often unreliable on pre-r300 */
			rdev->wb.enabled = false;
		} else {
			rdev->wb.enabled = true;
			/* event_write fences are only available on r600+ */
			if (rdev->family >= CHIP_R600) {
				rdev->wb.use_event = true;
	}
		}
	}
	/* always use writeback/events on NI, APUs */
	if (rdev->family >= CHIP_PALM) {
		rdev->wb.enabled = true;
		rdev->wb.use_event = true;
	}
 
	dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
 
	return 0;
}
 
/**
 * radeon_vram_location - try to find VRAM location
 * @rdev: radeon device structure holding all necessary informations
 * @mc: memory controller structure holding memory informations
 * @base: base address at which to put VRAM
 *
 * Function will place try to place VRAM at base address provided
 * as parameter (which is so far either PCI aperture address or
 * for IGP TOM base address).
 *
 * If there is not enough space to fit the unvisible VRAM in the 32bits
 * address space then we limit the VRAM size to the aperture.
 *
 * If we are using AGP and if the AGP aperture doesn't allow us to have
 * room for all the VRAM than we restrict the VRAM to the PCI aperture
 * size and print a warning.
 *
 * This function will never fails, worst case are limiting VRAM.
 *
 * Note: GTT start, end, size should be initialized before calling this
 * function on AGP platform.
 *
 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 * this shouldn't be a problem as we are using the PCI aperture as a reference.
 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 * not IGP.
 *
 * Note: we use mc_vram_size as on some board we need to program the mc to
 * cover the whole aperture even if VRAM size is inferior to aperture size
 * Novell bug 204882 + along with lots of ubuntu ones
 *
 * Note: when limiting vram it's safe to overwritte real_vram_size because
 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 * ones)
 *
 * Note: IGP TOM addr should be the same as the aperture addr, we don't
 * explicitly check for that thought.
 *
 * FIXME: when reducing VRAM size align new size on power of 2.
 */
void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
{
	uint64_t limit = (uint64_t)radeon_vram_limit << 20;
 
	mc->vram_start = base;
	if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
		mc->real_vram_size = mc->aper_size;
		mc->mc_vram_size = mc->aper_size;
	}
	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
		mc->real_vram_size = mc->aper_size;
		mc->mc_vram_size = mc->aper_size;
		}
	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
	if (limit && limit < mc->real_vram_size)
		mc->real_vram_size = limit;
	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
			mc->mc_vram_size >> 20, mc->vram_start,
			mc->vram_end, mc->real_vram_size >> 20);
}
 
/**
 * radeon_gtt_location - try to find GTT location
 * @rdev: radeon device structure holding all necessary informations
 * @mc: memory controller structure holding memory informations
 *
 * Function will place try to place GTT before or after VRAM.
 *
 * If GTT size is bigger than space left then we ajust GTT size.
 * Thus function will never fails.
 *
 * FIXME: when reducing GTT size align new size on power of 2.
 */
void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
{
	u64 size_af, size_bf;
 
	size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
	size_bf = mc->vram_start & ~mc->gtt_base_align;
	if (size_bf > size_af) {
		if (mc->gtt_size > size_bf) {
			dev_warn(rdev->dev, "limiting GTT\n");
			mc->gtt_size = size_bf;
		}
		mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
	} else {
		if (mc->gtt_size > size_af) {
			dev_warn(rdev->dev, "limiting GTT\n");
			mc->gtt_size = size_af;
		}
		mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
	}
	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
			mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
}
 
/*
 * GPU helpers function.
 */
/**
 * radeon_card_posted - check if the hw has already been initialized
 *
 * @rdev: radeon_device pointer
 *
 * Check if the asic has been initialized (all asics).
 * Used at driver startup.
 * Returns true if initialized or false if not.
 */
bool radeon_card_posted(struct radeon_device *rdev)
{
	uint32_t reg;
 
	if (ASIC_IS_NODCE(rdev))
		goto check_memsize;
 
	/* first check CRTCs */
	if (ASIC_IS_DCE4(rdev)) {
		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
			if (rdev->num_crtc >= 4) {
				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
			}
			if (rdev->num_crtc >= 6) {
				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
			}
		if (reg & EVERGREEN_CRTC_MASTER_EN)
			return true;
	} else if (ASIC_IS_AVIVO(rdev)) {
		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
		      RREG32(AVIVO_D2CRTC_CONTROL);
		if (reg & AVIVO_CRTC_EN) {
			return true;
		}
	} else {
		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
		      RREG32(RADEON_CRTC2_GEN_CNTL);
		if (reg & RADEON_CRTC_EN) {
			return true;
		}
	}
 
check_memsize:
	/* then check MEM_SIZE, in case the crtcs are off */
	if (rdev->family >= CHIP_R600)
		reg = RREG32(R600_CONFIG_MEMSIZE);
	else
		reg = RREG32(RADEON_CONFIG_MEMSIZE);
 
	if (reg)
		return true;
 
	return false;
 
}
 
/**
 * radeon_update_bandwidth_info - update display bandwidth params
 *
 * @rdev: radeon_device pointer
 *
 * Used when sclk/mclk are switched or display modes are set.
 * params are used to calculate display watermarks (all asics)
 */
void radeon_update_bandwidth_info(struct radeon_device *rdev)
{
	fixed20_12 a;
	u32 sclk = rdev->pm.current_sclk;
	u32 mclk = rdev->pm.current_mclk;
 
	/* sclk/mclk in Mhz */
		a.full = dfixed_const(100);
		rdev->pm.sclk.full = dfixed_const(sclk);
		rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
		rdev->pm.mclk.full = dfixed_const(mclk);
		rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 
	if (rdev->flags & RADEON_IS_IGP) {
		a.full = dfixed_const(16);
		/* core_bandwidth = sclk(Mhz) * 16 */
		rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
	}
}
 
/**
 * radeon_boot_test_post_card - check and possibly initialize the hw
 *
 * @rdev: radeon_device pointer
 *
 * Check if the asic is initialized and if not, attempt to initialize
 * it (all asics).
 * Returns true if initialized or false if not.
 */
bool radeon_boot_test_post_card(struct radeon_device *rdev)
{
	if (radeon_card_posted(rdev))
		return true;
 
	if (rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		if (rdev->is_atom_bios)
			atom_asic_init(rdev->mode_info.atom_context);
		else
			radeon_combios_asic_init(rdev->ddev);
		return true;
	} else {
		dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
		return false;
	}
}
 
/**
 * radeon_dummy_page_init - init dummy page used by the driver
 *
 * @rdev: radeon_device pointer
 *
 * Allocate the dummy page used by the driver (all asics).
 * This dummy page is used by the driver as a filler for gart entries
 * when pages are taken out of the GART
 * Returns 0 on sucess, -ENOMEM on failure.
 */
int radeon_dummy_page_init(struct radeon_device *rdev)
{
	if (rdev->dummy_page.page)
		return 0;
	rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
	if (rdev->dummy_page.page == NULL)
		return -ENOMEM;
	rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
					0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	return 0;
}
 
/**
 * radeon_dummy_page_fini - free dummy page used by the driver
 *
 * @rdev: radeon_device pointer
 *
 * Frees the dummy page used by the driver (all asics).
 */
void radeon_dummy_page_fini(struct radeon_device *rdev)
{
	if (rdev->dummy_page.page == NULL)
		return;
 
	rdev->dummy_page.page = NULL;
}
 
 
/* ATOM accessor methods */
/*
 * ATOM is an interpreted byte code stored in tables in the vbios.  The
 * driver registers callbacks to access registers and the interpreter
 * in the driver parses the tables and executes then to program specific
 * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
 * atombios.h, and atom.c
 */
 
/**
 * cail_pll_read - read PLL register
 *
 * @info: atom card_info pointer
 * @reg: PLL register offset
 *
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 * Returns the value of the PLL register.
 */
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = rdev->pll_rreg(rdev, reg);
    return r;
}
 
/**
 * cail_pll_write - write PLL register
 *
 * @info: atom card_info pointer
 * @reg: PLL register offset
 * @val: value to write to the pll register
 *
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 */
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    rdev->pll_wreg(rdev, reg, val);
}
 
/**
 * cail_mc_read - read MC (Memory Controller) register
 *
 * @info: atom card_info pointer
 * @reg: MC register offset
 *
 * Provides an MC register accessor for the atom interpreter (r4xx+).
 * Returns the value of the MC register.
 */
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = rdev->mc_rreg(rdev, reg);
    return r;
}
 
/**
 * cail_mc_write - write MC (Memory Controller) register
 *
 * @info: atom card_info pointer
 * @reg: MC register offset
 * @val: value to write to the pll register
 *
 * Provides a MC register accessor for the atom interpreter (r4xx+).
 */
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    rdev->mc_wreg(rdev, reg, val);
}
 
/**
 * cail_reg_write - write MMIO register
 *
 * @info: atom card_info pointer
 * @reg: MMIO register offset
 * @val: value to write to the pll register
 *
 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 */
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    WREG32(reg*4, val);
}
 
/**
 * cail_reg_read - read MMIO register
 *
 * @info: atom card_info pointer
 * @reg: MMIO register offset
 *
 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 * Returns the value of the MMIO register.
 */
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = RREG32(reg*4);
    return r;
}
 
/**
 * cail_ioreg_write - write IO register
 *
 * @info: atom card_info pointer
 * @reg: IO register offset
 * @val: value to write to the pll register
 *
 * Provides a IO register accessor for the atom interpreter (r4xx+).
 */
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct radeon_device *rdev = info->dev->dev_private;
 
	WREG32_IO(reg*4, val);
}
 
/**
 * cail_ioreg_read - read IO register
 *
 * @info: atom card_info pointer
 * @reg: IO register offset
 *
 * Provides an IO register accessor for the atom interpreter (r4xx+).
 * Returns the value of the IO register.
 */
static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
{
	struct radeon_device *rdev = info->dev->dev_private;
	uint32_t r;
 
	r = RREG32_IO(reg*4);
	return r;
}
 
/**
 * radeon_atombios_init - init the driver info and callbacks for atombios
 *
 * @rdev: radeon_device pointer
 *
 * Initializes the driver info and register access callbacks for the
 * ATOM interpreter (r4xx+).
 * Returns 0 on sucess, -ENOMEM on failure.
 * Called at driver startup.
 */
int radeon_atombios_init(struct radeon_device *rdev)
{
	struct card_info *atom_card_info =
	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
 
	if (!atom_card_info)
		return -ENOMEM;
 
	rdev->mode_info.atom_card_info = atom_card_info;
	atom_card_info->dev = rdev->ddev;
	atom_card_info->reg_read = cail_reg_read;
	atom_card_info->reg_write = cail_reg_write;
	/* needed for iio ops */
	if (rdev->rio_mem) {
		atom_card_info->ioreg_read = cail_ioreg_read;
		atom_card_info->ioreg_write = cail_ioreg_write;
	} else {
		DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
		atom_card_info->ioreg_read = cail_reg_read;
		atom_card_info->ioreg_write = cail_reg_write;
	}
	atom_card_info->mc_read = cail_mc_read;
	atom_card_info->mc_write = cail_mc_write;
	atom_card_info->pll_read = cail_pll_read;
	atom_card_info->pll_write = cail_pll_write;
 
	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
	if (!rdev->mode_info.atom_context) {
		radeon_atombios_fini(rdev);
		return -ENOMEM;
	}
 
	mutex_init(&rdev->mode_info.atom_context->mutex);
    radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
    return 0;
}
 
/**
 * radeon_atombios_fini - free the driver info and callbacks for atombios
 *
 * @rdev: radeon_device pointer
 *
 * Frees the driver info and register access callbacks for the ATOM
 * interpreter (r4xx+).
 * Called at driver shutdown.
 */
void radeon_atombios_fini(struct radeon_device *rdev)
{
	if (rdev->mode_info.atom_context) {
		kfree(rdev->mode_info.atom_context->scratch);
	}
	kfree(rdev->mode_info.atom_context);
	rdev->mode_info.atom_context = NULL;
	kfree(rdev->mode_info.atom_card_info);
	rdev->mode_info.atom_card_info = NULL;
}
 
/* COMBIOS */
/*
 * COMBIOS is the bios format prior to ATOM. It provides
 * command tables similar to ATOM, but doesn't have a unified
 * parser.  See radeon_combios.c
 */
 
/**
 * radeon_combios_init - init the driver info for combios
 *
 * @rdev: radeon_device pointer
 *
 * Initializes the driver info for combios (r1xx-r3xx).
 * Returns 0 on sucess.
 * Called at driver startup.
 */
int radeon_combios_init(struct radeon_device *rdev)
{
	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
	return 0;
}
 
/**
 * radeon_combios_fini - free the driver info for combios
 *
 * @rdev: radeon_device pointer
 *
 * Frees the driver info for combios (r1xx-r3xx).
 * Called at driver shutdown.
 */
void radeon_combios_fini(struct radeon_device *rdev)
{
}
 
/* if we get transitioned to only one device, take VGA back */
/**
 * radeon_vga_set_decode - enable/disable vga decode
 *
 * @cookie: radeon_device pointer
 * @state: enable/disable vga decode
 *
 * Enable/disable vga decode (all asics).
 * Returns VGA resource flags.
 */
static unsigned int radeon_vga_set_decode(void *cookie, bool state)
{
	struct radeon_device *rdev = cookie;
	radeon_vga_set_state(rdev, state);
	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}
 
/**
 * radeon_check_pot_argument - check that argument is a power of two
 *
 * @arg: value to check
 *
 * Validates that a certain argument is a power of two (all asics).
 * Returns true if argument is valid.
 */
static bool radeon_check_pot_argument(int arg)
{
	return (arg & (arg - 1)) == 0;
}
 
/**
 * radeon_check_arguments - validate module params
 *
 * @rdev: radeon_device pointer
 *
 * Validates certain module parameters and updates
 * the associated values used by the driver (all asics).
 */
static void radeon_check_arguments(struct radeon_device *rdev)
{
	/* vramlimit must be a power of two */
	if (!radeon_check_pot_argument(radeon_vram_limit)) {
		dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
				radeon_vram_limit);
		radeon_vram_limit = 0;
	}
 
	if (radeon_gart_size == -1) {
		/* default to a larger gart size on newer asics */
		if (rdev->family >= CHIP_RV770)
			radeon_gart_size = 1024;
		else
			radeon_gart_size = 512;
	}
	/* gtt size must be power of two and greater or equal to 32M */
	if (radeon_gart_size < 32) {
		dev_warn(rdev->dev, "gart size (%d) too small\n",
				radeon_gart_size);
		if (rdev->family >= CHIP_RV770)
			radeon_gart_size = 1024;
		else
		radeon_gart_size = 512;
	} else if (!radeon_check_pot_argument(radeon_gart_size)) {
		dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
				radeon_gart_size);
		if (rdev->family >= CHIP_RV770)
			radeon_gart_size = 1024;
		else
		radeon_gart_size = 512;
	}
	rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
 
	/* AGP mode can only be -1, 1, 2, 4, 8 */
	switch (radeon_agpmode) {
	case -1:
	case 0:
	case 1:
	case 2:
	case 4:
	case 8:
		break;
	default:
		dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
				"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
		radeon_agpmode = 0;
		break;
	}
 
	if (!radeon_check_pot_argument(radeon_vm_size)) {
		dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
			 radeon_vm_size);
		radeon_vm_size = 4;
	}
 
	if (radeon_vm_size < 1) {
		dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n",
			 radeon_vm_size);
		radeon_vm_size = 4;
	}
 
       /*
        * Max GPUVM size for Cayman, SI and CI are 40 bits.
        */
	if (radeon_vm_size > 1024) {
		dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
			 radeon_vm_size);
		radeon_vm_size = 4;
	}
 
	/* defines number of bits in page table versus page directory,
	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
	 * page table and the remaining bits are in the page directory */
	if (radeon_vm_block_size == -1) {
 
		/* Total bits covered by PD + PTs */
		unsigned bits = ilog2(radeon_vm_size) + 17;
 
		/* Make sure the PD is 4K in size up to 8GB address space.
		   Above that split equal between PD and PTs */
		if (radeon_vm_size <= 8)
			radeon_vm_block_size = bits - 9;
		else
			radeon_vm_block_size = (bits + 3) / 2;
 
	} else if (radeon_vm_block_size < 9) {
		dev_warn(rdev->dev, "VM page table size (%d) too small\n",
			 radeon_vm_block_size);
		radeon_vm_block_size = 9;
	}
 
	if (radeon_vm_block_size > 24 ||
	    (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
		dev_warn(rdev->dev, "VM page table size (%d) too large\n",
			 radeon_vm_block_size);
		radeon_vm_block_size = 9;
	}
}
 
/**
 * radeon_device_init - initialize the driver
 *
 * @rdev: radeon_device pointer
 * @pdev: drm dev pointer
 * @pdev: pci dev pointer
 * @flags: driver flags
 *
 * Initializes the driver info and hw (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver startup.
 */
int radeon_device_init(struct radeon_device *rdev,
               struct drm_device *ddev,
               struct pci_dev *pdev,
               uint32_t flags)
{
	int r, i;
	int dma_bits;
	bool runtime = false;
 
    rdev->shutdown = false;
	rdev->dev = &pdev->dev;
    rdev->ddev = ddev;
    rdev->pdev = pdev;
    rdev->flags = flags;
    rdev->family = flags & RADEON_FAMILY_MASK;
    rdev->is_atom_bios = false;
    rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
	rdev->mc.gtt_size = 512 * 1024 * 1024;
	rdev->accel_working = false;
	/* set up ring ids */
	for (i = 0; i < RADEON_NUM_RINGS; i++) {
		rdev->ring[i].idx = i;
	}
 
	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
		radeon_family_name[rdev->family], pdev->vendor, pdev->device,
		pdev->subsystem_vendor, pdev->subsystem_device);
 
    /* mutex initialization are all done here so we
     * can recall function without having locking issues */
	mutex_init(&rdev->ring_lock);
	mutex_init(&rdev->dc_hw_i2c_mutex);
	atomic_set(&rdev->ih.lock, 0);
	mutex_init(&rdev->gem.mutex);
	mutex_init(&rdev->pm.mutex);
	mutex_init(&rdev->gpu_clock_mutex);
	mutex_init(&rdev->srbm_mutex);
//   init_rwsem(&rdev->pm.mclk_lock);
//   init_rwsem(&rdev->exclusive_lock);
	init_waitqueue_head(&rdev->irq.vblank_queue);
	r = radeon_gem_init(rdev);
	if (r)
		return r;
 
	radeon_check_arguments(rdev);
	/* Adjust VM size here.
	 * Max GPUVM size for cayman+ is 40 bits.
	 */
	rdev->vm_manager.max_pfn = radeon_vm_size << 18;
 
	/* Set asic functions */
	r = radeon_asic_init(rdev);
	if (r)
		return r;
 
	/* all of the newer IGP chips have an internal gart
	 * However some rs4xx report as AGP, so remove that here.
	 */
	if ((rdev->family >= CHIP_RS400) &&
	    (rdev->flags & RADEON_IS_IGP)) {
		rdev->flags &= ~RADEON_IS_AGP;
	}
 
	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
		radeon_agp_disable(rdev);
    }
 
	/* Set the internal MC address mask
	 * This is the max address of the GPU's
	 * internal address space.
	 */
	if (rdev->family >= CHIP_CAYMAN)
		rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
	else if (rdev->family >= CHIP_CEDAR)
		rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
	else
		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
 
	/* set DMA mask + need_dma32 flags.
	 * PCIE - can handle 40-bits.
	 * IGP - can handle 40-bits
	 * AGP - generally dma32 is safest
	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
	 */
	rdev->need_dma32 = false;
	if (rdev->flags & RADEON_IS_AGP)
		rdev->need_dma32 = true;
	if ((rdev->flags & RADEON_IS_PCI) &&
	    (rdev->family <= CHIP_RS740))
		rdev->need_dma32 = true;
 
	dma_bits = rdev->need_dma32 ? 32 : 40;
	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
    if (r) {
		rdev->need_dma32 = true;
		dma_bits = 32;
        printk(KERN_WARNING "radeon: No suitable DMA available.\n");
    }
 
    /* Registers mapping */
    /* TODO: block userspace mapping of io register */
	spin_lock_init(&rdev->mmio_idx_lock);
	spin_lock_init(&rdev->smc_idx_lock);
	spin_lock_init(&rdev->pll_idx_lock);
	spin_lock_init(&rdev->mc_idx_lock);
	spin_lock_init(&rdev->pcie_idx_lock);
	spin_lock_init(&rdev->pciep_idx_lock);
	spin_lock_init(&rdev->pif_idx_lock);
	spin_lock_init(&rdev->cg_idx_lock);
	spin_lock_init(&rdev->uvd_idx_lock);
	spin_lock_init(&rdev->rcu_idx_lock);
	spin_lock_init(&rdev->didt_idx_lock);
	spin_lock_init(&rdev->end_idx_lock);
	if (rdev->family >= CHIP_BONAIRE) {
		rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
		rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
	} else {
    rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
    rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
	}
	rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
    if (rdev->rmmio == NULL) {
        return -ENOMEM;
    }
    DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
    DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 
	/* doorbell bar mapping */
	if (rdev->family >= CHIP_BONAIRE)
		radeon_doorbell_init(rdev);
 
	/* io port mapping */
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
		if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
			rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
			rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
			break;
		}
	}
	if (rdev->rio_mem == NULL)
		DRM_ERROR("Unable to find PCI I/O BAR\n");
 
	if (rdev->flags & RADEON_IS_PX)
		radeon_device_handle_px_quirks(rdev);
	if (rdev->flags & RADEON_IS_PX)
		runtime = true;
 
	r = radeon_init(rdev);
	if (r)
        return r;
 
	r = radeon_ib_ring_tests(rdev);
	if (r)
		DRM_ERROR("ib ring test failed (%d).\n", r);
 
 
	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
		/* Acceleration not working on AGP card try again
		 * with fallback to PCI or PCIE GART
		 */
		radeon_asic_reset(rdev);
		radeon_fini(rdev);
		radeon_agp_disable(rdev);
		r = radeon_init(rdev);
		if (r)
		return r;
	}
 
	if ((radeon_testing & 1)) {
		if (rdev->accel_working)
			radeon_test_moves(rdev);
		else
			DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
	}
	if ((radeon_testing & 2)) {
		if (rdev->accel_working)
			radeon_test_syncing(rdev);
		else
			DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
	}
   if (radeon_benchmarking) {
		if (rdev->accel_working)
		radeon_benchmark(rdev, radeon_benchmarking);
		else
			DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
    }
	return 0;
}
 
/**
 * radeon_gpu_reset - reset the asic
 *
 * @rdev: radeon device pointer
 *
 * Attempt the reset the GPU if it has hung (all asics).
 * Returns 0 for success or an error on failure.
 */
int radeon_gpu_reset(struct radeon_device *rdev)
{
    unsigned ring_sizes[RADEON_NUM_RINGS];
    uint32_t *ring_data[RADEON_NUM_RINGS];
 
    bool saved = false;
 
    int i, r;
    int resched;
 
//    down_write(&rdev->exclusive_lock);
	rdev->needs_reset = false;
 
    radeon_save_bios_scratch_regs(rdev);
    /* block TTM */
//    resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
    radeon_suspend(rdev);
 
    for (i = 0; i < RADEON_NUM_RINGS; ++i) {
        ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
                           &ring_data[i]);
        if (ring_sizes[i]) {
            saved = true;
            dev_info(rdev->dev, "Saved %d dwords of commands "
                 "on ring %d.\n", ring_sizes[i], i);
        }
    }
 
retry:
    r = radeon_asic_reset(rdev);
    if (!r) {
        dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
        radeon_resume(rdev);
    }
 
    radeon_restore_bios_scratch_regs(rdev);
 
    if (!r) {
        for (i = 0; i < RADEON_NUM_RINGS; ++i) {
            radeon_ring_restore(rdev, &rdev->ring[i],
                        ring_sizes[i], ring_data[i]);
            ring_sizes[i] = 0;
            ring_data[i] = NULL;
        }
 
//        r = radeon_ib_ring_tests(rdev);
//        if (r) {
//            dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
//            if (saved) {
//                saved = false;
//                radeon_suspend(rdev);
//                goto retry;
//            }
//        }
    } else {
        for (i = 0; i < RADEON_NUM_RINGS; ++i) {
            kfree(ring_data[i]);
        }
    }
 
//    ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
    if (r) {
        /* bad news, how to tell it to userspace ? */
        dev_info(rdev->dev, "GPU reset failed\n");
    }
 
//    up_write(&rdev->exclusive_lock);
    return r;
}
 
 
/*
 * Driver load/unload
 */
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
{
    struct radeon_device *rdev;
    int r;
 
 
    rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
    if (rdev == NULL) {
        return -ENOMEM;
    };
 
    dev->dev_private = (void *)rdev;
 
    /* update BUS flag */
    if (drm_pci_device_is_agp(dev)) {
        flags |= RADEON_IS_AGP;
    } else if (drm_device_is_pcie(dev)) {
        flags |= RADEON_IS_PCIE;
    } else {
        flags |= RADEON_IS_PCI;
    }
 
    /* radeon_device_init should report only fatal error
     * like memory allocation failure or iomapping failure,
     * or memory manager initialization failure, it must
     * properly initialize the GPU MC controller and permit
     * VRAM allocation
     */
    r = radeon_device_init(rdev, dev, dev->pdev, flags);
    if (r) {
        DRM_ERROR("Fatal error while trying to initialize radeon.\n");
        return r;
    }
    /* Again modeset_init should fail only on fatal error
     * otherwise it should provide enough functionalities
     * for shadowfb to run
     */
    main_device = dev;
 
    if( radeon_modeset )
    {
        r = radeon_modeset_init(rdev);
        if (r) {
            return r;
        }
        init_display_kms(dev, &usermode);
    }
    else
        init_display(rdev, &usermode);
 
    return 0;
}
 
 
 
resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
{
    return pci_resource_start(dev->pdev, resource);
}
 
resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
{
    return pci_resource_len(dev->pdev, resource);
}
 
 
uint32_t __div64_32(uint64_t *n, uint32_t base)
{
        uint64_t rem = *n;
        uint64_t b = base;
        uint64_t res, d = 1;
        uint32_t high = rem >> 32;
 
        /* Reduce the thing a bit first */
        res = 0;
        if (high >= base) {
                high /= base;
                res = (uint64_t) high << 32;
                rem -= (uint64_t) (high*base) << 32;
        }
 
        while ((int64_t)b > 0 && b < rem) {
                b = b+b;
                d = d+d;
        }
 
        do {
                if (rem >= b) {
                        rem -= b;
                        res += d;
                }
                b >>= 1;
                d >>= 1;
        } while (d);
 
        *n = res;
        return rem;
}
 
static struct pci_device_id pciidlist[] = {
    radeon_PCI_IDS
};
 
void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
 
 
static struct drm_driver kms_driver = {
    .driver_features =
        DRIVER_USE_AGP |
        DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
        DRIVER_PRIME | DRIVER_RENDER,
    .load = radeon_driver_load_kms,
//    .open = radeon_driver_open_kms,
//    .preclose = radeon_driver_preclose_kms,
//    .postclose = radeon_driver_postclose_kms,
//    .lastclose = radeon_driver_lastclose_kms,
//    .unload = radeon_driver_unload_kms,
//    .get_vblank_counter = radeon_get_vblank_counter_kms,
//    .enable_vblank = radeon_enable_vblank_kms,
//    .disable_vblank = radeon_disable_vblank_kms,
//    .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
//    .get_scanout_position = radeon_get_crtc_scanoutpos,
#if defined(CONFIG_DEBUG_FS)
    .debugfs_init = radeon_debugfs_init,
    .debugfs_cleanup = radeon_debugfs_cleanup,
#endif
    .irq_preinstall = radeon_driver_irq_preinstall_kms,
    .irq_postinstall = radeon_driver_irq_postinstall_kms,
    .irq_uninstall = radeon_driver_irq_uninstall_kms,
    .irq_handler = radeon_driver_irq_handler_kms,
//    .ioctls = radeon_ioctls_kms,
//    .gem_free_object = radeon_gem_object_free,
//    .gem_open_object = radeon_gem_object_open,
//    .gem_close_object = radeon_gem_object_close,
//    .dumb_create = radeon_mode_dumb_create,
//    .dumb_map_offset = radeon_mode_dumb_mmap,
//    .dumb_destroy = drm_gem_dumb_destroy,
//    .fops = &radeon_driver_kms_fops,
 
//    .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
//    .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
//    .gem_prime_export = drm_gem_prime_export,
//    .gem_prime_import = drm_gem_prime_import,
//    .gem_prime_pin = radeon_gem_prime_pin,
//    .gem_prime_unpin = radeon_gem_prime_unpin,
//    .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
//    .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
//    .gem_prime_vmap = radeon_gem_prime_vmap,
//    .gem_prime_vunmap = radeon_gem_prime_vunmap,
 
};
 
int ati_init(void)
{
    static pci_dev_t device;
    const struct pci_device_id  *ent;
    int  err;
 
    ent = find_pci_device(&device, pciidlist);
    if( unlikely(ent == NULL) )
    {
        dbgprintf("device not found\n");
        return -ENODEV;
    };
 
    drm_core_init();
 
    DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
                                device.pci_dev.device);
 
    kms_driver.driver_features |= DRIVER_MODESET;
 
    err = drm_get_pci_dev(&device.pci_dev, ent, &kms_driver);
 
    return err;
}

Rev 5078	Rev 5097
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	//#include	28	//#include
29	#include	29	#include
30	#include	30	#include
31	#include	31	#include
32	#include	32	#include
33	#include "radeon_reg.h"	33	#include "radeon_reg.h"
34	#include "radeon.h"	34	#include "radeon.h"
35	#include "atom.h"	35	#include "atom.h"
36		36
37	#include "bitmap.h"	37	#include "bitmap.h"
38	#include "display.h"	38	#include "display.h"
39		39
40		40
41	#include	41	#include
42		42
43	#define PCI_VENDOR_ID_ATI 0x1002	43	#define PCI_VENDOR_ID_ATI 0x1002
44	#define PCI_VENDOR_ID_APPLE 0x106b	44	#define PCI_VENDOR_ID_APPLE 0x106b
45		45
46	int radeon_no_wb;	46	int radeon_no_wb;
47	int radeon_modeset = -1;	47	int radeon_modeset = -1;
48	int radeon_dynclks = -1;	48	int radeon_dynclks = -1;
49	int radeon_r4xx_atom = 0;	49	int radeon_r4xx_atom = 0;
50	int radeon_agpmode = 0;	50	int radeon_agpmode = 0;
51	int radeon_vram_limit = 0;	51	int radeon_vram_limit = 0;
52	int radeon_gart_size = -1; /* auto */	52	int radeon_gart_size = -1; /* auto */
53	int radeon_benchmarking = 0;	53	int radeon_benchmarking = 0;
54	int radeon_testing = 0;	54	int radeon_testing = 0;
55	int radeon_connector_table = 0;	55	int radeon_connector_table = 0;
56	int radeon_tv = 1;	56	int radeon_tv = 1;
57	int radeon_audio = -1;	57	int radeon_audio = -1;
58	int radeon_disp_priority = 0;	58	int radeon_disp_priority = 0;
59	int radeon_hw_i2c = 0;	59	int radeon_hw_i2c = 0;
60	int radeon_pcie_gen2 = -1;	60	int radeon_pcie_gen2 = -1;
61	int radeon_msi = -1;	61	int radeon_msi = -1;
62	int radeon_lockup_timeout = 10000;	62	int radeon_lockup_timeout = 10000;
63	int radeon_fastfb = 0;	63	int radeon_fastfb = 0;
64	int radeon_dpm = -1;	64	int radeon_dpm = -1;
65	int radeon_aspm = -1;	65	int radeon_aspm = -1;
66	int radeon_runtime_pm = -1;	66	int radeon_runtime_pm = -1;
67	int radeon_hard_reset = 0;	67	int radeon_hard_reset = 0;
68	int radeon_vm_size = 8;	68	int radeon_vm_size = 8;
69	int radeon_vm_block_size = -1;	69	int radeon_vm_block_size = -1;
70	int radeon_deep_color = 0;	70	int radeon_deep_color = 0;
71	int radeon_use_pflipirq = 2;	71	int radeon_use_pflipirq = 2;
72	int irq_override = 0;	72	int irq_override = 0;
73	int radeon_bapm = -1;	73	int radeon_bapm = -1;
74		74
75		75
76	extern display_t *os_display;	76	extern display_t *os_display;
77	extern struct drm_device *main_device;	77	extern struct drm_device *main_device;
78	extern videomode_t usermode;	78	extern videomode_t usermode;
79		79
80		80
81	void parse_cmdline(char cmdline, videomode_t mode, char log, int kms);	81	void parse_cmdline(char cmdline, videomode_t mode, char log, int kms);
82	int init_display(struct radeon_device rdev, videomode_t mode);	82	int init_display(struct radeon_device rdev, videomode_t mode);
83	int init_display_kms(struct drm_device dev, videomode_t usermode);	83	int init_display_kms(struct drm_device dev, videomode_t usermode);
84		84
85	int get_modes(videomode_t mode, u32_t count);	85	int get_modes(videomode_t mode, u32_t count);
86	int set_user_mode(videomode_t *mode);	86	int set_user_mode(videomode_t *mode);
87	int r100_2D_test(struct radeon_device *rdev);	87	int r100_2D_test(struct radeon_device *rdev);
88		88
89		89
90	/* Legacy VGA regions */	90	/* Legacy VGA regions */
91	#define VGA_RSRC_NONE 0x00	91	#define VGA_RSRC_NONE 0x00
92	#define VGA_RSRC_LEGACY_IO 0x01	92	#define VGA_RSRC_LEGACY_IO 0x01
93	#define VGA_RSRC_LEGACY_MEM 0x02	93	#define VGA_RSRC_LEGACY_MEM 0x02
94	#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM)	94	#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM)
95	/* Non-legacy access */	95	/* Non-legacy access */
96	#define VGA_RSRC_NORMAL_IO 0x04	96	#define VGA_RSRC_NORMAL_IO 0x04
97	#define VGA_RSRC_NORMAL_MEM 0x08	97	#define VGA_RSRC_NORMAL_MEM 0x08
98		98
99		99
100	static const char radeon_family_name[][16] = {	100	static const char radeon_family_name[][16] = {
101	"R100",	101	"R100",
102	"RV100",	102	"RV100",
103	"RS100",	103	"RS100",
104	"RV200",	104	"RV200",
105	"RS200",	105	"RS200",
106	"R200",	106	"R200",
107	"RV250",	107	"RV250",
108	"RS300",	108	"RS300",
109	"RV280",	109	"RV280",
110	"R300",	110	"R300",
111	"R350",	111	"R350",
112	"RV350",	112	"RV350",
113	"RV380",	113	"RV380",
114	"R420",	114	"R420",
115	"R423",	115	"R423",
116	"RV410",	116	"RV410",
117	"RS400",	117	"RS400",
118	"RS480",	118	"RS480",
119	"RS600",	119	"RS600",
120	"RS690",	120	"RS690",
121	"RS740",	121	"RS740",
122	"RV515",	122	"RV515",
123	"R520",	123	"R520",
124	"RV530",	124	"RV530",
125	"RV560",	125	"RV560",
126	"RV570",	126	"RV570",
127	"R580",	127	"R580",
128	"R600",	128	"R600",
129	"RV610",	129	"RV610",
130	"RV630",	130	"RV630",
131	"RV670",	131	"RV670",
132	"RV620",	132	"RV620",
133	"RV635",	133	"RV635",
134	"RS780",	134	"RS780",
135	"RS880",	135	"RS880",
136	"RV770",	136	"RV770",
137	"RV730",	137	"RV730",
138	"RV710",	138	"RV710",
139	"RV740",	139	"RV740",
140	"CEDAR",	140	"CEDAR",
141	"REDWOOD",	141	"REDWOOD",
142	"JUNIPER",	142	"JUNIPER",
143	"CYPRESS",	143	"CYPRESS",
144	"HEMLOCK",	144	"HEMLOCK",
145	"PALM",	145	"PALM",
146	"SUMO",	146	"SUMO",
147	"SUMO2",	147	"SUMO2",
148	"BARTS",	148	"BARTS",
149	"TURKS",	149	"TURKS",
150	"CAICOS",	150	"CAICOS",
151	"CAYMAN",	151	"CAYMAN",
152	"ARUBA",	152	"ARUBA",
153	"TAHITI",	153	"TAHITI",
154	"PITCAIRN",	154	"PITCAIRN",
155	"VERDE",	155	"VERDE",
156	"OLAND",	156	"OLAND",
157	"HAINAN",	157	"HAINAN",
158	"BONAIRE",	158	"BONAIRE",
159	"KAVERI",	159	"KAVERI",
160	"KABINI",	160	"KABINI",
161	"HAWAII",	161	"HAWAII",
162	"MULLINS",	162	"MULLINS",
163	"LAST",	163	"LAST",
164	};	164	};
165		165
166	#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)	166	#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
167	#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)	167	#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
168		168
169	struct radeon_px_quirk {	169	struct radeon_px_quirk {
170	u32 chip_vendor;	170	u32 chip_vendor;
171	u32 chip_device;	171	u32 chip_device;
172	u32 subsys_vendor;	172	u32 subsys_vendor;
173	u32 subsys_device;	173	u32 subsys_device;
174	u32 px_quirk_flags;	174	u32 px_quirk_flags;
175	};	175	};
176		176
177	static struct radeon_px_quirk radeon_px_quirk_list[] = {	177	static struct radeon_px_quirk radeon_px_quirk_list[] = {
178	/* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)	178	/* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
179	* https://bugzilla.kernel.org/show_bug.cgi?id=74551	179	* https://bugzilla.kernel.org/show_bug.cgi?id=74551
180	*/	180	*/
181	{ PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },	181	{ PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
182	/* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU	182	/* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
183	* https://bugzilla.kernel.org/show_bug.cgi?id=51381	183	* https://bugzilla.kernel.org/show_bug.cgi?id=51381
184	*/	184	*/
185	{ PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },	185	{ PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
186	/* macbook pro 8.2 */	186	/* macbook pro 8.2 */
187	{ PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP },	187	{ PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP },
188	{ 0, 0, 0, 0, 0 },	188	{ 0, 0, 0, 0, 0 },
189	};	189	};
190		190
191	bool radeon_is_px(struct drm_device *dev)	191	bool radeon_is_px(struct drm_device *dev)
192	{	192	{
193	struct radeon_device *rdev = dev->dev_private;	193	struct radeon_device *rdev = dev->dev_private;
194		194
195	if (rdev->flags & RADEON_IS_PX)	195	if (rdev->flags & RADEON_IS_PX)
196	return true;	196	return true;
197	return false;	197	return false;
198	}	198	}
199		199
200	static void radeon_device_handle_px_quirks(struct radeon_device *rdev)	200	static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
201	{	201	{
202	struct radeon_px_quirk *p = radeon_px_quirk_list;	202	struct radeon_px_quirk *p = radeon_px_quirk_list;
203		203
204	/* Apply PX quirks */	204	/* Apply PX quirks */
205	while (p && p->chip_device != 0) {	205	while (p && p->chip_device != 0) {
206	if (rdev->pdev->vendor == p->chip_vendor &&	206	if (rdev->pdev->vendor == p->chip_vendor &&
207	rdev->pdev->device == p->chip_device &&	207	rdev->pdev->device == p->chip_device &&
208	rdev->pdev->subsystem_vendor == p->subsys_vendor &&	208	rdev->pdev->subsystem_vendor == p->subsys_vendor &&
209	rdev->pdev->subsystem_device == p->subsys_device) {	209	rdev->pdev->subsystem_device == p->subsys_device) {
210	rdev->px_quirk_flags = p->px_quirk_flags;	210	rdev->px_quirk_flags = p->px_quirk_flags;
211	break;	211	break;
212	}	212	}
213	++p;	213	++p;
214	}	214	}
215		215
216	if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)	216	if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
217	rdev->flags &= ~RADEON_IS_PX;	217	rdev->flags &= ~RADEON_IS_PX;
218	}	218	}
219		219
220	/**	220	/**
221	* radeon_program_register_sequence - program an array of registers.	221	* radeon_program_register_sequence - program an array of registers.
222	*	222	*
223	* @rdev: radeon_device pointer	223	* @rdev: radeon_device pointer
224	* @registers: pointer to the register array	224	* @registers: pointer to the register array
225	* @array_size: size of the register array	225	* @array_size: size of the register array
226	*	226	*
227	* Programs an array or registers with and and or masks.	227	* Programs an array or registers with and and or masks.
228	* This is a helper for setting golden registers.	228	* This is a helper for setting golden registers.
229	*/	229	*/
230	void radeon_program_register_sequence(struct radeon_device *rdev,	230	void radeon_program_register_sequence(struct radeon_device *rdev,
231	const u32 *registers,	231	const u32 *registers,
232	const u32 array_size)	232	const u32 array_size)
233	{	233	{
234	u32 tmp, reg, and_mask, or_mask;	234	u32 tmp, reg, and_mask, or_mask;
235	int i;	235	int i;
236		236
237	if (array_size % 3)	237	if (array_size % 3)
238	return;	238	return;
239		239
240	for (i = 0; i < array_size; i +=3) {	240	for (i = 0; i < array_size; i +=3) {
241	reg = registers[i + 0];	241	reg = registers[i + 0];
242	and_mask = registers[i + 1];	242	and_mask = registers[i + 1];
243	or_mask = registers[i + 2];	243	or_mask = registers[i + 2];
244		244
245	if (and_mask == 0xffffffff) {	245	if (and_mask == 0xffffffff) {
246	tmp = or_mask;	246	tmp = or_mask;
247	} else {	247	} else {
248	tmp = RREG32(reg);	248	tmp = RREG32(reg);
249	tmp &= ~and_mask;	249	tmp &= ~and_mask;
250	tmp \|= or_mask;	250	tmp \|= or_mask;
251	}	251	}
252	WREG32(reg, tmp);	252	WREG32(reg, tmp);
253	}	253	}
254	}	254	}
255		255
256	void radeon_pci_config_reset(struct radeon_device *rdev)	256	void radeon_pci_config_reset(struct radeon_device *rdev)
257	{	257	{
258	pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);	258	pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
259	}	259	}
260		260
261	/**	261	/**
262	* radeon_surface_init - Clear GPU surface registers.	262	* radeon_surface_init - Clear GPU surface registers.
263	*	263	*
264	* @rdev: radeon_device pointer	264	* @rdev: radeon_device pointer
265	*	265	*
266	* Clear GPU surface registers (r1xx-r5xx).	266	* Clear GPU surface registers (r1xx-r5xx).
267	*/	267	*/
268	void radeon_surface_init(struct radeon_device *rdev)	268	void radeon_surface_init(struct radeon_device *rdev)
269	{	269	{
270	/* FIXME: check this out */	270	/* FIXME: check this out */
271	if (rdev->family < CHIP_R600) {	271	if (rdev->family < CHIP_R600) {
272	int i;	272	int i;
273		273
274	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {	274	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
275	if (rdev->surface_regs[i].bo)	275	if (rdev->surface_regs[i].bo)
276	radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);	276	radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
277	else	277	else
278	radeon_clear_surface_reg(rdev, i);	278	radeon_clear_surface_reg(rdev, i);
279	}	279	}
280	/* enable surfaces */	280	/* enable surfaces */
281	WREG32(RADEON_SURFACE_CNTL, 0);	281	WREG32(RADEON_SURFACE_CNTL, 0);
282	}	282	}
283	}	283	}
284		284
285	/*	285	/*
286	* GPU scratch registers helpers function.	286	* GPU scratch registers helpers function.
287	*/	287	*/
288	/**	288	/**
289	* radeon_scratch_init - Init scratch register driver information.	289	* radeon_scratch_init - Init scratch register driver information.
290	*	290	*
291	* @rdev: radeon_device pointer	291	* @rdev: radeon_device pointer
292	*	292	*
293	* Init CP scratch register driver information (r1xx-r5xx)	293	* Init CP scratch register driver information (r1xx-r5xx)
294	*/	294	*/
295	void radeon_scratch_init(struct radeon_device *rdev)	295	void radeon_scratch_init(struct radeon_device *rdev)
296	{	296	{
297	int i;	297	int i;
298		298
299	/* FIXME: check this out */	299	/* FIXME: check this out */
300	if (rdev->family < CHIP_R300) {	300	if (rdev->family < CHIP_R300) {
301	rdev->scratch.num_reg = 5;	301	rdev->scratch.num_reg = 5;
302	} else {	302	} else {
303	rdev->scratch.num_reg = 7;	303	rdev->scratch.num_reg = 7;
304	}	304	}
305	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;	305	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
306	for (i = 0; i < rdev->scratch.num_reg; i++) {	306	for (i = 0; i < rdev->scratch.num_reg; i++) {
307	rdev->scratch.free[i] = true;	307	rdev->scratch.free[i] = true;
308	rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);	308	rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
309	}	309	}
310	}	310	}
311		311
312	/**	312	/**
313	* radeon_scratch_get - Allocate a scratch register	313	* radeon_scratch_get - Allocate a scratch register
314	*	314	*
315	* @rdev: radeon_device pointer	315	* @rdev: radeon_device pointer
316	* @reg: scratch register mmio offset	316	* @reg: scratch register mmio offset
317	*	317	*
318	* Allocate a CP scratch register for use by the driver (all asics).	318	* Allocate a CP scratch register for use by the driver (all asics).
319	* Returns 0 on success or -EINVAL on failure.	319	* Returns 0 on success or -EINVAL on failure.
320	*/	320	*/
321	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)	321	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)
322	{	322	{
323	int i;	323	int i;
324		324
325	for (i = 0; i < rdev->scratch.num_reg; i++) {	325	for (i = 0; i < rdev->scratch.num_reg; i++) {
326	if (rdev->scratch.free[i]) {	326	if (rdev->scratch.free[i]) {
327	rdev->scratch.free[i] = false;	327	rdev->scratch.free[i] = false;
328	*reg = rdev->scratch.reg[i];	328	*reg = rdev->scratch.reg[i];
329	return 0;	329	return 0;
330	}	330	}
331	}	331	}
332	return -EINVAL;	332	return -EINVAL;
333	}	333	}
334		334
335	/**	335	/**
336	* radeon_scratch_free - Free a scratch register	336	* radeon_scratch_free - Free a scratch register
337	*	337	*
338	* @rdev: radeon_device pointer	338	* @rdev: radeon_device pointer
339	* @reg: scratch register mmio offset	339	* @reg: scratch register mmio offset
340	*	340	*
341	* Free a CP scratch register allocated for use by the driver (all asics)	341	* Free a CP scratch register allocated for use by the driver (all asics)
342	*/	342	*/
343	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)	343	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
344	{	344	{
345	int i;	345	int i;
346		346
347	for (i = 0; i < rdev->scratch.num_reg; i++) {	347	for (i = 0; i < rdev->scratch.num_reg; i++) {
348	if (rdev->scratch.reg[i] == reg) {	348	if (rdev->scratch.reg[i] == reg) {
349	rdev->scratch.free[i] = true;	349	rdev->scratch.free[i] = true;
350	return;	350	return;
351	}	351	}
352	}	352	}
353	}	353	}
354		354
355	/*	355	/*
356	* GPU doorbell aperture helpers function.	356	* GPU doorbell aperture helpers function.
357	*/	357	*/
358	/**	358	/**
359	* radeon_doorbell_init - Init doorbell driver information.	359	* radeon_doorbell_init - Init doorbell driver information.
360	*	360	*
361	* @rdev: radeon_device pointer	361	* @rdev: radeon_device pointer
362	*	362	*
363	* Init doorbell driver information (CIK)	363	* Init doorbell driver information (CIK)
364	* Returns 0 on success, error on failure.	364	* Returns 0 on success, error on failure.
365	*/	365	*/
366	static int radeon_doorbell_init(struct radeon_device *rdev)	366	static int radeon_doorbell_init(struct radeon_device *rdev)
367	{	367	{
368	/* doorbell bar mapping */	368	/* doorbell bar mapping */
369	rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);	369	rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
370	rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);	370	rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
371		371
372	rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);	372	rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
373	if (rdev->doorbell.num_doorbells == 0)	373	if (rdev->doorbell.num_doorbells == 0)
374	return -EINVAL;	374	return -EINVAL;
375		375
376	rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));	376	rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
377	if (rdev->doorbell.ptr == NULL) {	377	if (rdev->doorbell.ptr == NULL) {
378	return -ENOMEM;	378	return -ENOMEM;
379	}	379	}
380	DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);	380	DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
381	DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);	381	DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
382		382
383	memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));	383	memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
384		384
385	return 0;	385	return 0;
386	}	386	}
387		387
388	/**	388	/**
389	* radeon_doorbell_fini - Tear down doorbell driver information.	389	* radeon_doorbell_fini - Tear down doorbell driver information.
390	*	390	*
391	* @rdev: radeon_device pointer	391	* @rdev: radeon_device pointer
392	*	392	*
393	* Tear down doorbell driver information (CIK)	393	* Tear down doorbell driver information (CIK)
394	*/	394	*/
395	static void radeon_doorbell_fini(struct radeon_device *rdev)	395	static void radeon_doorbell_fini(struct radeon_device *rdev)
396	{	396	{
397	iounmap(rdev->doorbell.ptr);	397	iounmap(rdev->doorbell.ptr);
398	rdev->doorbell.ptr = NULL;	398	rdev->doorbell.ptr = NULL;
399	}	399	}
400		400
401	/**	401	/**
402	* radeon_doorbell_get - Allocate a doorbell entry	402	* radeon_doorbell_get - Allocate a doorbell entry
403	*	403	*
404	* @rdev: radeon_device pointer	404	* @rdev: radeon_device pointer
405	* @doorbell: doorbell index	405	* @doorbell: doorbell index
406	*	406	*
407	* Allocate a doorbell for use by the driver (all asics).	407	* Allocate a doorbell for use by the driver (all asics).
408	* Returns 0 on success or -EINVAL on failure.	408	* Returns 0 on success or -EINVAL on failure.
409	*/	409	*/
410	int radeon_doorbell_get(struct radeon_device rdev, u32 doorbell)	410	int radeon_doorbell_get(struct radeon_device rdev, u32 doorbell)
411	{	411	{
412	unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);	412	unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
413	if (offset < rdev->doorbell.num_doorbells) {	413	if (offset < rdev->doorbell.num_doorbells) {
414	__set_bit(offset, rdev->doorbell.used);	414	__set_bit(offset, rdev->doorbell.used);
415	*doorbell = offset;	415	*doorbell = offset;
416	return 0;	416	return 0;
417	} else {	417	} else {
418	return -EINVAL;	418	return -EINVAL;
419	}	419	}
420	}	420	}
421		421
422	/**	422	/**
423	* radeon_doorbell_free - Free a doorbell entry	423	* radeon_doorbell_free - Free a doorbell entry
424	*	424	*
425	* @rdev: radeon_device pointer	425	* @rdev: radeon_device pointer
426	* @doorbell: doorbell index	426	* @doorbell: doorbell index
427	*	427	*
428	* Free a doorbell allocated for use by the driver (all asics)	428	* Free a doorbell allocated for use by the driver (all asics)
429	*/	429	*/
430	void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)	430	void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
431	{	431	{
432	if (doorbell < rdev->doorbell.num_doorbells)	432	if (doorbell < rdev->doorbell.num_doorbells)
433	__clear_bit(doorbell, rdev->doorbell.used);	433	__clear_bit(doorbell, rdev->doorbell.used);
434	}	434	}
435		435
436	/*	436	/*
437	* radeon_wb_*()	437	* radeon_wb_*()
438	* Writeback is the the method by which the the GPU updates special pages	438	* Writeback is the the method by which the the GPU updates special pages
439	* in memory with the status of certain GPU events (fences, ring pointers,	439	* in memory with the status of certain GPU events (fences, ring pointers,
440	* etc.).	440	* etc.).
441	*/	441	*/
442		442
443	/**	443	/**
444	* radeon_wb_disable - Disable Writeback	444	* radeon_wb_disable - Disable Writeback
445	*	445	*
446	* @rdev: radeon_device pointer	446	* @rdev: radeon_device pointer
447	*	447	*
448	* Disables Writeback (all asics). Used for suspend.	448	* Disables Writeback (all asics). Used for suspend.
449	*/	449	*/
450	void radeon_wb_disable(struct radeon_device *rdev)	450	void radeon_wb_disable(struct radeon_device *rdev)
451	{	451	{
452	rdev->wb.enabled = false;	452	rdev->wb.enabled = false;
453	}	453	}
454		454
455	/**	455	/**
456	* radeon_wb_fini - Disable Writeback and free memory	456	* radeon_wb_fini - Disable Writeback and free memory
457	*	457	*
458	* @rdev: radeon_device pointer	458	* @rdev: radeon_device pointer
459	*	459	*
460	* Disables Writeback and frees the Writeback memory (all asics).	460	* Disables Writeback and frees the Writeback memory (all asics).
461	* Used at driver shutdown.	461	* Used at driver shutdown.
462	*/	462	*/
463	void radeon_wb_fini(struct radeon_device *rdev)	463	void radeon_wb_fini(struct radeon_device *rdev)
464	{	464	{
465	radeon_wb_disable(rdev);	465	radeon_wb_disable(rdev);
466	if (rdev->wb.wb_obj) {	466	if (rdev->wb.wb_obj) {
467	if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {	467	if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
468	radeon_bo_kunmap(rdev->wb.wb_obj);	468	radeon_bo_kunmap(rdev->wb.wb_obj);
469	radeon_bo_unpin(rdev->wb.wb_obj);	469	radeon_bo_unpin(rdev->wb.wb_obj);
470	radeon_bo_unreserve(rdev->wb.wb_obj);	470	radeon_bo_unreserve(rdev->wb.wb_obj);
471	}	471	}
472	radeon_bo_unref(&rdev->wb.wb_obj);	472	radeon_bo_unref(&rdev->wb.wb_obj);
473	rdev->wb.wb = NULL;	473	rdev->wb.wb = NULL;
474	rdev->wb.wb_obj = NULL;	474	rdev->wb.wb_obj = NULL;
475	}	475	}
476	}	476	}
477		477
478	/**	478	/**
479	* radeon_wb_init- Init Writeback driver info and allocate memory	479	* radeon_wb_init- Init Writeback driver info and allocate memory
480	*	480	*
481	* @rdev: radeon_device pointer	481	* @rdev: radeon_device pointer
482	*	482	*
483	* Disables Writeback and frees the Writeback memory (all asics).	483	* Disables Writeback and frees the Writeback memory (all asics).
484	* Used at driver startup.	484	* Used at driver startup.
485	* Returns 0 on success or an -error on failure.	485	* Returns 0 on success or an -error on failure.
486	*/	486	*/
487	int radeon_wb_init(struct radeon_device *rdev)	487	int radeon_wb_init(struct radeon_device *rdev)
488	{	488	{
489	int r;	489	int r;
490		490
491	if (rdev->wb.wb_obj == NULL) {	491	if (rdev->wb.wb_obj == NULL) {
492	r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,	492	r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
493	RADEON_GEM_DOMAIN_GTT, 0, NULL,	493	RADEON_GEM_DOMAIN_GTT, 0, NULL,
494	&rdev->wb.wb_obj);	494	&rdev->wb.wb_obj);
495	if (r) {	495	if (r) {
496	dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);	496	dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
497	return r;	497	return r;
498	}	498	}
499	r = radeon_bo_reserve(rdev->wb.wb_obj, false);	499	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
500	if (unlikely(r != 0)) {	500	if (unlikely(r != 0)) {

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(root)/drivers/video/drm/radeon/radeon_device.c – Rev 5078 → 5097