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1 
/*
 1 
/*
2 
 * Copyright 2009 Advanced Micro Devices, Inc.
 2 
 * Copyright 2009 Advanced Micro Devices, Inc.
3 
 * Copyright 2009 Red Hat Inc.
 3 
 * Copyright 2009 Red Hat Inc.
4 
 *
 4 
 *
5 
 * Permission is hereby granted, free of charge, to any person obtaining a
 5 
 * Permission is hereby granted, free of charge, to any person obtaining a
6 
 * copy of this software and associated documentation files (the "Software"),
 6 
 * copy of this software and associated documentation files (the "Software"),
7 
 * to deal in the Software without restriction, including without limitation
 7 
 * to deal in the Software without restriction, including without limitation
8 
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 
 * and/or sell copies of the Software, and to permit persons to whom the
 9 
 * and/or sell copies of the Software, and to permit persons to whom the
10 
 * Software is furnished to do so, subject to the following conditions:
 10 
 * Software is furnished to do so, subject to the following conditions:
11 
 *
 11 
 *
12 
 * The above copyright notice and this permission notice (including the next
 12 
 * The above copyright notice and this permission notice (including the next
13 
 * paragraph) shall be included in all copies or substantial portions of the
 13 
 * paragraph) shall be included in all copies or substantial portions of the
14 
 * Software.
 14 
 * Software.
15 
 *
 15 
 *
16 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 
 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 
 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 
 * DEALINGS IN THE SOFTWARE.
 22 
 * DEALINGS IN THE SOFTWARE.
23 
 *
 23 
 *
24 
 */
 24 
 */
25 
 
 25 
 
26 
#include "drmP.h"
 26 
#include "drmP.h"
27 
#include "drm.h"
 27 
#include "drm.h"
28 
#include "radeon_drm.h"
 28 
#include "radeon_drm.h"
29 
#include "radeon.h"
 29 
#include "radeon.h"
30 
 
 30 
 
31 
#include "r600d.h"
 31 
#include "r600d.h"
32 
#include "r600_blit_shaders.h"
 32 
#include "r600_blit_shaders.h"
33 
 
 33 
 
34 
#define DI_PT_RECTLIST        0x11
 34 
#define DI_PT_RECTLIST        0x11
35 
#define DI_INDEX_SIZE_16_BIT  0x0
 35 
#define DI_INDEX_SIZE_16_BIT  0x0
36 
#define DI_SRC_SEL_AUTO_INDEX 0x2
 36 
#define DI_SRC_SEL_AUTO_INDEX 0x2
37 
 
 37 
 
38 
#define FMT_8                 0x1
 38 
#define FMT_8                 0x1
39 
#define FMT_5_6_5             0x8
 39 
#define FMT_5_6_5             0x8
40 
#define FMT_8_8_8_8           0x1a
 40 
#define FMT_8_8_8_8           0x1a
41 
#define COLOR_8               0x1
 41 
#define COLOR_8               0x1
42 
#define COLOR_5_6_5           0x8
 42 
#define COLOR_5_6_5           0x8
43 
#define COLOR_8_8_8_8         0x1a
 43 
#define COLOR_8_8_8_8         0x1a
44 
 
 44 
 
45 
/* emits 21 on rv770+, 23 on r600 */
 45 
/* emits 21 on rv770+, 23 on r600 */
46 
static void
 46 
static void
47 
set_render_target(struct radeon_device *rdev, int format,
 47 
set_render_target(struct radeon_device *rdev, int format,
48 
		  int w, int h, u64 gpu_addr)
 48 
		  int w, int h, u64 gpu_addr)
49 
{
 49 
{
50 
	u32 cb_color_info;
 50 
	u32 cb_color_info;
51 
	int pitch, slice;
 51 
	int pitch, slice;
52 
 
 52 
 
53 
	h = ALIGN(h, 8);
 53 
	h = ALIGN(h, 8);
54 
	if (h < 8)
 54 
	if (h < 8)
55 
		h = 8;
 55 
		h = 8;
56 
 
 56 
 
57 
	cb_color_info = ((format << 2) | (1 << 27) | (1 << 8));
 57 
	cb_color_info = ((format << 2) | (1 << 27) | (1 << 8));
58 
	pitch = (w / 8) - 1;
 58 
	pitch = (w / 8) - 1;
59 
	slice = ((w * h) / 64) - 1;
 59 
	slice = ((w * h) / 64) - 1;
60 
 
 60 
 
61 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 61 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
62 
	radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 62 
	radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
63 
	radeon_ring_write(rdev, gpu_addr >> 8);
 63 
	radeon_ring_write(rdev, gpu_addr >> 8);
64 
 
 64 
 
65 
	if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
 65 
	if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
66 
		radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
 66 
		radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
67 
		radeon_ring_write(rdev, 2 << 0);
 67 
		radeon_ring_write(rdev, 2 << 0);
68 
	}
 68 
	}
69 
 
 69 
 
70 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 70 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
71 
	radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 71 
	radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
72 
	radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
 72 
	radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
73 
 
 73 
 
74 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 74 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
75 
	radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 75 
	radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
76 
	radeon_ring_write(rdev, 0);
 76 
	radeon_ring_write(rdev, 0);
77 
 
 77 
 
78 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 78 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
79 
	radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 79 
	radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
80 
	radeon_ring_write(rdev, cb_color_info);
 80 
	radeon_ring_write(rdev, cb_color_info);
81 
 
 81 
 
82 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 82 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
83 
	radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 83 
	radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
84 
	radeon_ring_write(rdev, 0);
 84 
	radeon_ring_write(rdev, 0);
85 
 
 85 
 
86 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 86 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
87 
	radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 87 
	radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
88 
	radeon_ring_write(rdev, 0);
 88 
	radeon_ring_write(rdev, 0);
89 
 
 89 
 
90 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 90 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
91 
	radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 91 
	radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
92 
	radeon_ring_write(rdev, 0);
 92 
	radeon_ring_write(rdev, 0);
93 
}
 93 
}
94 
 
 94 
 
95 
/* emits 5dw */
 95 
/* emits 5dw */
96 
static void
 96 
static void
97 
cp_set_surface_sync(struct radeon_device *rdev,
 97 
cp_set_surface_sync(struct radeon_device *rdev,
98 
		    u32 sync_type, u32 size,
 98 
		    u32 sync_type, u32 size,
99 
		    u64 mc_addr)
 99 
		    u64 mc_addr)
100 
{
 100 
{
101 
	u32 cp_coher_size;
 101 
	u32 cp_coher_size;
102 
 
 102 
 
103 
	if (size == 0xffffffff)
 103 
	if (size == 0xffffffff)
104 
		cp_coher_size = 0xffffffff;
 104 
		cp_coher_size = 0xffffffff;
105 
	else
 105 
	else
106 
		cp_coher_size = ((size + 255) >> 8);
 106 
		cp_coher_size = ((size + 255) >> 8);
107 
 
 107 
 
108 
	radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
 108 
	radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
109 
	radeon_ring_write(rdev, sync_type);
 109 
	radeon_ring_write(rdev, sync_type);
110 
	radeon_ring_write(rdev, cp_coher_size);
 110 
	radeon_ring_write(rdev, cp_coher_size);
111 
	radeon_ring_write(rdev, mc_addr >> 8);
 111 
	radeon_ring_write(rdev, mc_addr >> 8);
112 
	radeon_ring_write(rdev, 10); /* poll interval */
 112 
	radeon_ring_write(rdev, 10); /* poll interval */
113 
}
 113 
}
114 
 
 114 
 
115 
/* emits 21dw + 1 surface sync = 26dw */
 115 
/* emits 21dw + 1 surface sync = 26dw */
116 
static void
 116 
static void
117 
set_shaders(struct radeon_device *rdev)
 117 
set_shaders(struct radeon_device *rdev)
118 
{
 118 
{
119 
	u64 gpu_addr;
 119 
	u64 gpu_addr;
120 
	u32 sq_pgm_resources;
 120 
	u32 sq_pgm_resources;
121 
 
 121 
 
122 
	/* setup shader regs */
 122 
	/* setup shader regs */
123 
	sq_pgm_resources = (1 << 0);
 123 
	sq_pgm_resources = (1 << 0);
124 
 
 124 
 
125 
	/* VS */
 125 
	/* VS */
126 
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 126 
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
127 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 127 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
128 
	radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 128 
	radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
129 
	radeon_ring_write(rdev, gpu_addr >> 8);
 129 
	radeon_ring_write(rdev, gpu_addr >> 8);
130 
 
 130 
 
131 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 131 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
132 
	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 132 
	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
133 
	radeon_ring_write(rdev, sq_pgm_resources);
 133 
	radeon_ring_write(rdev, sq_pgm_resources);
134 
 
 134 
 
135 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 135 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
136 
	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 136 
	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
137 
	radeon_ring_write(rdev, 0);
 137 
	radeon_ring_write(rdev, 0);
138 
 
 138 
 
139 
	/* PS */
 139 
	/* PS */
140 
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 140 
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
141 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 141 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
142 
	radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 142 
	radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
143 
	radeon_ring_write(rdev, gpu_addr >> 8);
 143 
	radeon_ring_write(rdev, gpu_addr >> 8);
144 
 
 144 
 
145 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 145 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
146 
	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 146 
	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
147 
	radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
 147 
	radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
148 
 
 148 
 
149 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 149 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
150 
	radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 150 
	radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
151 
	radeon_ring_write(rdev, 2);
 151 
	radeon_ring_write(rdev, 2);
152 
 
 152 
 
153 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 153 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
154 
	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 154 
	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
155 
	radeon_ring_write(rdev, 0);
 155 
	radeon_ring_write(rdev, 0);
156 
 
 156 
 
157 
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 157 
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
158 
	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 158 
	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
159 
}
 159 
}
160 
 
 160 
 
161 
/* emits 9 + 1 sync (5) = 14*/
 161 
/* emits 9 + 1 sync (5) = 14*/
162 
static void
 162 
static void
163 
set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 163 
set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
164 
{
 164 
{
165 
	u32 sq_vtx_constant_word2;
 165 
	u32 sq_vtx_constant_word2;
166 
 
 166 
 
167 
	sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
 167 
	sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
168 
#ifdef __BIG_ENDIAN
 168 
#ifdef __BIG_ENDIAN
169 
	sq_vtx_constant_word2 |= (2 << 30);
 169 
	sq_vtx_constant_word2 |= (2 << 30);
170 
#endif
 170 
#endif
171 
 
 171 
 
172 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
 172 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
173 
	radeon_ring_write(rdev, 0x460);
 173 
	radeon_ring_write(rdev, 0x460);
174 
	radeon_ring_write(rdev, gpu_addr & 0xffffffff);
 174 
	radeon_ring_write(rdev, gpu_addr & 0xffffffff);
175 
	radeon_ring_write(rdev, 48 - 1);
 175 
	radeon_ring_write(rdev, 48 - 1);
176 
	radeon_ring_write(rdev, sq_vtx_constant_word2);
 176 
	radeon_ring_write(rdev, sq_vtx_constant_word2);
177 
	radeon_ring_write(rdev, 1 << 0);
 177 
	radeon_ring_write(rdev, 1 << 0);
178 
	radeon_ring_write(rdev, 0);
 178 
	radeon_ring_write(rdev, 0);
179 
	radeon_ring_write(rdev, 0);
 179 
	radeon_ring_write(rdev, 0);
180 
	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
 180 
	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
181 
 
 181 
 
182 
	if ((rdev->family == CHIP_RV610) ||
 182 
	if ((rdev->family == CHIP_RV610) ||
183 
	    (rdev->family == CHIP_RV620) ||
 183 
	    (rdev->family == CHIP_RV620) ||
184 
	    (rdev->family == CHIP_RS780) ||
 184 
	    (rdev->family == CHIP_RS780) ||
185 
	    (rdev->family == CHIP_RS880) ||
 185 
	    (rdev->family == CHIP_RS880) ||
186 
	    (rdev->family == CHIP_RV710))
 186 
	    (rdev->family == CHIP_RV710))
187 
		cp_set_surface_sync(rdev,
 187 
		cp_set_surface_sync(rdev,
188 
				    PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 188 
				    PACKET3_TC_ACTION_ENA, 48, gpu_addr);
189 
	else
 189 
	else
190 
		cp_set_surface_sync(rdev,
 190 
		cp_set_surface_sync(rdev,
191 
				    PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 191 
				    PACKET3_VC_ACTION_ENA, 48, gpu_addr);
192 
}
 192 
}
193 
 
 193 
 
194 
/* emits 9 */
 194 
/* emits 9 */
195 
static void
 195 
static void
196 
set_tex_resource(struct radeon_device *rdev,
 196 
set_tex_resource(struct radeon_device *rdev,
197 
		 int format, int w, int h, int pitch,
 197 
		 int format, int w, int h, int pitch,
198 
		 u64 gpu_addr)
 198 
		 u64 gpu_addr)
199 
{
 199 
{
200 
	uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
 200 
	uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
201 
 
 201 
 
202 
	if (h < 1)
 202 
	if (h < 1)
203 
		h = 1;
 203 
		h = 1;
204 
 
 204 
 
205 
	sq_tex_resource_word0 = (1 << 0) | (1 << 3);
 205 
	sq_tex_resource_word0 = (1 << 0) | (1 << 3);
206 
	sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
 206 
	sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
207 
				  ((w - 1) << 19));
 207 
				  ((w - 1) << 19));
208 
 
 208 
 
209 
	sq_tex_resource_word1 = (format << 26);
 209 
	sq_tex_resource_word1 = (format << 26);
210 
	sq_tex_resource_word1 |= ((h - 1) << 0);
 210 
	sq_tex_resource_word1 |= ((h - 1) << 0);
211 
 
 211 
 
212 
	sq_tex_resource_word4 = ((1 << 14) |
 212 
	sq_tex_resource_word4 = ((1 << 14) |
213 
				 (0 << 16) |
 213 
				 (0 << 16) |
214 
				 (1 << 19) |
 214 
				 (1 << 19) |
215 
				 (2 << 22) |
 215 
				 (2 << 22) |
216 
				 (3 << 25));
 216 
				 (3 << 25));
217 
 
 217 
 
218 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
 218 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
219 
	radeon_ring_write(rdev, 0);
 219 
	radeon_ring_write(rdev, 0);
220 
	radeon_ring_write(rdev, sq_tex_resource_word0);
 220 
	radeon_ring_write(rdev, sq_tex_resource_word0);
221 
	radeon_ring_write(rdev, sq_tex_resource_word1);
 221 
	radeon_ring_write(rdev, sq_tex_resource_word1);
222 
	radeon_ring_write(rdev, gpu_addr >> 8);
 222 
	radeon_ring_write(rdev, gpu_addr >> 8);
223 
	radeon_ring_write(rdev, gpu_addr >> 8);
 223 
	radeon_ring_write(rdev, gpu_addr >> 8);
224 
	radeon_ring_write(rdev, sq_tex_resource_word4);
 224 
	radeon_ring_write(rdev, sq_tex_resource_word4);
225 
	radeon_ring_write(rdev, 0);
 225 
	radeon_ring_write(rdev, 0);
226 
	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
 226 
	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
227 
}
 227 
}
228 
 
 228 
 
229 
/* emits 12 */
 229 
/* emits 12 */
230 
static void
 230 
static void
231 
set_scissors(struct radeon_device *rdev, int x1, int y1,
 231 
set_scissors(struct radeon_device *rdev, int x1, int y1,
232 
	     int x2, int y2)
 232 
	     int x2, int y2)
233 
{
 233 
{
234 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 234 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
235 
	radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 235 
	radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
236 
	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
 236 
	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
237 
	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 237 
	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
238 
 
 238 
 
239 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 239 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
240 
	radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 240 
	radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
241 
	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 241 
	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
242 
	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 242 
	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
243 
 
 243 
 
244 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 244 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
245 
	radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 245 
	radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
246 
	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 246 
	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
247 
	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 247 
	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
248 
}
 248 
}
249 
 
 249 
 
250 
/* emits 10 */
 250 
/* emits 10 */
251 
static void
 251 
static void
252 
draw_auto(struct radeon_device *rdev)
 252 
draw_auto(struct radeon_device *rdev)
253 
{
 253 
{
254 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 254 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
255 
	radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 255 
	radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
256 
	radeon_ring_write(rdev, DI_PT_RECTLIST);
 256 
	radeon_ring_write(rdev, DI_PT_RECTLIST);
257 
 
 257 
 
258 
	radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
 258 
	radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
259 
	radeon_ring_write(rdev,
 259 
	radeon_ring_write(rdev,
260 
#ifdef __BIG_ENDIAN
 260 
#ifdef __BIG_ENDIAN
261 
			  (2 << 2) |
 261 
			  (2 << 2) |
262 
#endif
 262 
#endif
263 
			  DI_INDEX_SIZE_16_BIT);
 263 
			  DI_INDEX_SIZE_16_BIT);
264 
 
 264 
 
265 
	radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
 265 
	radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
266 
	radeon_ring_write(rdev, 1);
 266 
	radeon_ring_write(rdev, 1);
267 
 
 267 
 
268 
	radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 268 
	radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
269 
	radeon_ring_write(rdev, 3);
 269 
	radeon_ring_write(rdev, 3);
270 
	radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
 270 
	radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
271 
 
 271 
 
272 
}
 272 
}
273 
 
 273 
 
274 
/* emits 14 */
 274 
/* emits 14 */
275 
static void
 275 
static void
276 
set_default_state(struct radeon_device *rdev)
 276 
set_default_state(struct radeon_device *rdev)
277 
{
 277 
{
278 
	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
 278 
	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
279 
	u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
 279 
	u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
280 
	int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
 280 
	int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
281 
	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 281 
	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
282 
	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 282 
	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
283 
	u64 gpu_addr;
 283 
	u64 gpu_addr;
284 
	int dwords;
 284 
	int dwords;
285 
 
 285 
 
286 
	switch (rdev->family) {
 286 
	switch (rdev->family) {
287 
	case CHIP_R600:
 287 
	case CHIP_R600:
288 
		num_ps_gprs = 192;
 288 
		num_ps_gprs = 192;
289 
		num_vs_gprs = 56;
 289 
		num_vs_gprs = 56;
290 
		num_temp_gprs = 4;
 290 
		num_temp_gprs = 4;
291 
		num_gs_gprs = 0;
 291 
		num_gs_gprs = 0;
292 
		num_es_gprs = 0;
 292 
		num_es_gprs = 0;
293 
		num_ps_threads = 136;
 293 
		num_ps_threads = 136;
294 
		num_vs_threads = 48;
 294 
		num_vs_threads = 48;
295 
		num_gs_threads = 4;
 295 
		num_gs_threads = 4;
296 
		num_es_threads = 4;
 296 
		num_es_threads = 4;
297 
		num_ps_stack_entries = 128;
 297 
		num_ps_stack_entries = 128;
298 
		num_vs_stack_entries = 128;
 298 
		num_vs_stack_entries = 128;
299 
		num_gs_stack_entries = 0;
 299 
		num_gs_stack_entries = 0;
300 
		num_es_stack_entries = 0;
 300 
		num_es_stack_entries = 0;
301 
		break;
 301 
		break;
302 
	case CHIP_RV630:
 302 
	case CHIP_RV630:
303 
	case CHIP_RV635:
 303 
	case CHIP_RV635:
304 
		num_ps_gprs = 84;
 304 
		num_ps_gprs = 84;
305 
		num_vs_gprs = 36;
 305 
		num_vs_gprs = 36;
306 
		num_temp_gprs = 4;
 306 
		num_temp_gprs = 4;
307 
		num_gs_gprs = 0;
 307 
		num_gs_gprs = 0;
308 
		num_es_gprs = 0;
 308 
		num_es_gprs = 0;
309 
		num_ps_threads = 144;
 309 
		num_ps_threads = 144;
310 
		num_vs_threads = 40;
 310 
		num_vs_threads = 40;
311 
		num_gs_threads = 4;
 311 
		num_gs_threads = 4;
312 
		num_es_threads = 4;
 312 
		num_es_threads = 4;
313 
		num_ps_stack_entries = 40;
 313 
		num_ps_stack_entries = 40;
314 
		num_vs_stack_entries = 40;
 314 
		num_vs_stack_entries = 40;
315 
		num_gs_stack_entries = 32;
 315 
		num_gs_stack_entries = 32;
316 
		num_es_stack_entries = 16;
 316 
		num_es_stack_entries = 16;
317 
		break;
 317 
		break;
318 
	case CHIP_RV610:
 318 
	case CHIP_RV610:
319 
	case CHIP_RV620:
 319 
	case CHIP_RV620:
320 
	case CHIP_RS780:
 320 
	case CHIP_RS780:
321 
	case CHIP_RS880:
 321 
	case CHIP_RS880:
322 
	default:
 322 
	default:
323 
		num_ps_gprs = 84;
 323 
		num_ps_gprs = 84;
324 
		num_vs_gprs = 36;
 324 
		num_vs_gprs = 36;
325 
		num_temp_gprs = 4;
 325 
		num_temp_gprs = 4;
326 
		num_gs_gprs = 0;
 326 
		num_gs_gprs = 0;
327 
		num_es_gprs = 0;
 327 
		num_es_gprs = 0;
328 
		num_ps_threads = 136;
 328 
		num_ps_threads = 136;
329 
		num_vs_threads = 48;
 329 
		num_vs_threads = 48;
330 
		num_gs_threads = 4;
 330 
		num_gs_threads = 4;
331 
		num_es_threads = 4;
 331 
		num_es_threads = 4;
332 
		num_ps_stack_entries = 40;
 332 
		num_ps_stack_entries = 40;
333 
		num_vs_stack_entries = 40;
 333 
		num_vs_stack_entries = 40;
334 
		num_gs_stack_entries = 32;
 334 
		num_gs_stack_entries = 32;
335 
		num_es_stack_entries = 16;
 335 
		num_es_stack_entries = 16;
336 
		break;
 336 
		break;
337 
	case CHIP_RV670:
 337 
	case CHIP_RV670:
338 
		num_ps_gprs = 144;
 338 
		num_ps_gprs = 144;
339 
		num_vs_gprs = 40;
 339 
		num_vs_gprs = 40;
340 
		num_temp_gprs = 4;
 340 
		num_temp_gprs = 4;
341 
		num_gs_gprs = 0;
 341 
		num_gs_gprs = 0;
342 
		num_es_gprs = 0;
 342 
		num_es_gprs = 0;
343 
		num_ps_threads = 136;
 343 
		num_ps_threads = 136;
344 
		num_vs_threads = 48;
 344 
		num_vs_threads = 48;
345 
		num_gs_threads = 4;
 345 
		num_gs_threads = 4;
346 
		num_es_threads = 4;
 346 
		num_es_threads = 4;
347 
		num_ps_stack_entries = 40;
 347 
		num_ps_stack_entries = 40;
348 
		num_vs_stack_entries = 40;
 348 
		num_vs_stack_entries = 40;
349 
		num_gs_stack_entries = 32;
 349 
		num_gs_stack_entries = 32;
350 
		num_es_stack_entries = 16;
 350 
		num_es_stack_entries = 16;
351 
		break;
 351 
		break;
352 
	case CHIP_RV770:
 352 
	case CHIP_RV770:
353 
		num_ps_gprs = 192;
 353 
		num_ps_gprs = 192;
354 
		num_vs_gprs = 56;
 354 
		num_vs_gprs = 56;
355 
		num_temp_gprs = 4;
 355 
		num_temp_gprs = 4;
356 
		num_gs_gprs = 0;
 356 
		num_gs_gprs = 0;
357 
		num_es_gprs = 0;
 357 
		num_es_gprs = 0;
358 
		num_ps_threads = 188;
 358 
		num_ps_threads = 188;
359 
		num_vs_threads = 60;
 359 
		num_vs_threads = 60;
360 
		num_gs_threads = 0;
 360 
		num_gs_threads = 0;
361 
		num_es_threads = 0;
 361 
		num_es_threads = 0;
362 
		num_ps_stack_entries = 256;
 362 
		num_ps_stack_entries = 256;
363 
		num_vs_stack_entries = 256;
 363 
		num_vs_stack_entries = 256;
364 
		num_gs_stack_entries = 0;
 364 
		num_gs_stack_entries = 0;
365 
		num_es_stack_entries = 0;
 365 
		num_es_stack_entries = 0;
366 
		break;
 366 
		break;
367 
	case CHIP_RV730:
 367 
	case CHIP_RV730:
368 
	case CHIP_RV740:
 368 
	case CHIP_RV740:
369 
		num_ps_gprs = 84;
 369 
		num_ps_gprs = 84;
370 
		num_vs_gprs = 36;
 370 
		num_vs_gprs = 36;
371 
		num_temp_gprs = 4;
 371 
		num_temp_gprs = 4;
372 
		num_gs_gprs = 0;
 372 
		num_gs_gprs = 0;
373 
		num_es_gprs = 0;
 373 
		num_es_gprs = 0;
374 
		num_ps_threads = 188;
 374 
		num_ps_threads = 188;
375 
		num_vs_threads = 60;
 375 
		num_vs_threads = 60;
376 
		num_gs_threads = 0;
 376 
		num_gs_threads = 0;
377 
		num_es_threads = 0;
 377 
		num_es_threads = 0;
378 
		num_ps_stack_entries = 128;
 378 
		num_ps_stack_entries = 128;
379 
		num_vs_stack_entries = 128;
 379 
		num_vs_stack_entries = 128;
380 
		num_gs_stack_entries = 0;
 380 
		num_gs_stack_entries = 0;
381 
		num_es_stack_entries = 0;
 381 
		num_es_stack_entries = 0;
382 
		break;
 382 
		break;
383 
	case CHIP_RV710:
 383 
	case CHIP_RV710:
384 
		num_ps_gprs = 192;
 384 
		num_ps_gprs = 192;
385 
		num_vs_gprs = 56;
 385 
		num_vs_gprs = 56;
386 
		num_temp_gprs = 4;
 386 
		num_temp_gprs = 4;
387 
		num_gs_gprs = 0;
 387 
		num_gs_gprs = 0;
388 
		num_es_gprs = 0;
 388 
		num_es_gprs = 0;
389 
		num_ps_threads = 144;
 389 
		num_ps_threads = 144;
390 
		num_vs_threads = 48;
 390 
		num_vs_threads = 48;
391 
		num_gs_threads = 0;
 391 
		num_gs_threads = 0;
392 
		num_es_threads = 0;
 392 
		num_es_threads = 0;
393 
		num_ps_stack_entries = 128;
 393 
		num_ps_stack_entries = 128;
394 
		num_vs_stack_entries = 128;
 394 
		num_vs_stack_entries = 128;
395 
		num_gs_stack_entries = 0;
 395 
		num_gs_stack_entries = 0;
396 
		num_es_stack_entries = 0;
 396 
		num_es_stack_entries = 0;
397 
		break;
 397 
		break;
398 
	}
 398 
	}
399 
 
 399 
 
400 
	if ((rdev->family == CHIP_RV610) ||
 400 
	if ((rdev->family == CHIP_RV610) ||
401 
	    (rdev->family == CHIP_RV620) ||
 401 
	    (rdev->family == CHIP_RV620) ||
402 
	    (rdev->family == CHIP_RS780) ||
 402 
	    (rdev->family == CHIP_RS780) ||
403 
	    (rdev->family == CHIP_RS880) ||
 403 
	    (rdev->family == CHIP_RS880) ||
404 
	    (rdev->family == CHIP_RV710))
 404 
	    (rdev->family == CHIP_RV710))
405 
		sq_config = 0;
 405 
		sq_config = 0;
406 
	else
 406 
	else
407 
		sq_config = VC_ENABLE;
 407 
		sq_config = VC_ENABLE;
408 
 
 408 
 
409 
	sq_config |= (DX9_CONSTS |
 409 
	sq_config |= (DX9_CONSTS |
410 
		      ALU_INST_PREFER_VECTOR |
 410 
		      ALU_INST_PREFER_VECTOR |
411 
		      PS_PRIO(0) |
 411 
		      PS_PRIO(0) |
412 
		      VS_PRIO(1) |
 412 
		      VS_PRIO(1) |
413 
		      GS_PRIO(2) |
 413 
		      GS_PRIO(2) |
414 
		      ES_PRIO(3));
 414 
		      ES_PRIO(3));
415 
 
 415 
 
416 
	sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 416 
	sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
417 
				  NUM_VS_GPRS(num_vs_gprs) |
 417 
				  NUM_VS_GPRS(num_vs_gprs) |
418 
				  NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 418 
				  NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
419 
	sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 419 
	sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
420 
				  NUM_ES_GPRS(num_es_gprs));
 420 
				  NUM_ES_GPRS(num_es_gprs));
421 
	sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 421 
	sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
422 
				   NUM_VS_THREADS(num_vs_threads) |
 422 
				   NUM_VS_THREADS(num_vs_threads) |
423 
				   NUM_GS_THREADS(num_gs_threads) |
 423 
				   NUM_GS_THREADS(num_gs_threads) |
424 
				   NUM_ES_THREADS(num_es_threads));
 424 
				   NUM_ES_THREADS(num_es_threads));
425 
	sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 425 
	sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
426 
				    NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 426 
				    NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
427 
	sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 427 
	sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
428 
				    NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 428 
				    NUM_ES_STACK_ENTRIES(num_es_stack_entries));
429 
 
 429 
 
430 
	/* emit an IB pointing at default state */
 430 
	/* emit an IB pointing at default state */
431 
	dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
 431 
	dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
432 
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
 432 
	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
433 
	radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 433 
	radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
434 
	radeon_ring_write(rdev,
 434 
	radeon_ring_write(rdev,
435 
#ifdef __BIG_ENDIAN
 435 
#ifdef __BIG_ENDIAN
436 
			  (2 << 0) |
 436 
			  (2 << 0) |
437 
#endif
 437 
#endif
438 
			  (gpu_addr & 0xFFFFFFFC));
 438 
			  (gpu_addr & 0xFFFFFFFC));
439 
	radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
 439 
	radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
440 
	radeon_ring_write(rdev, dwords);
 440 
	radeon_ring_write(rdev, dwords);
441 
 
 441 
 
442 
	/* SQ config */
 442 
	/* SQ config */
443 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
 443 
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
444 
	radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 444 
	radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
445 
	radeon_ring_write(rdev, sq_config);
 445 
	radeon_ring_write(rdev, sq_config);
446 
	radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
 446 
	radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
447 
	radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
 447 
	radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
448 
	radeon_ring_write(rdev, sq_thread_resource_mgmt);
 448 
	radeon_ring_write(rdev, sq_thread_resource_mgmt);
449 
	radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
 449 
	radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
450 
	radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
 450 
	radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
451 
}
 451 
}
452 
 
 452 
 
453 
static inline uint32_t i2f(uint32_t input)
 453 
static inline uint32_t i2f(uint32_t input)
454 
{
 454 
{
455 
	u32 result, i, exponent, fraction;
 455 
	u32 result, i, exponent, fraction;
456 
 
 456 
 
457 
	if ((input & 0x3fff) == 0)
 457 
	if ((input & 0x3fff) == 0)
458 
		result = 0; /* 0 is a special case */
 458 
		result = 0; /* 0 is a special case */
459 
	else {
 459 
	else {
460 
		exponent = 140; /* exponent biased by 127; */
 460 
		exponent = 140; /* exponent biased by 127; */
461 
		fraction = (input & 0x3fff) << 10; /* cheat and only
 461 
		fraction = (input & 0x3fff) << 10; /* cheat and only
462 
						      handle numbers below 2^^15 */
 462 
						      handle numbers below 2^^15 */
463 
		for (i = 0; i < 14; i++) {
 463 
		for (i = 0; i < 14; i++) {
464 
			if (fraction & 0x800000)
 464 
			if (fraction & 0x800000)
465 
				break;
 465 
				break;
466 
			else {
 466 
			else {
467 
				fraction = fraction << 1; /* keep
 467 
				fraction = fraction << 1; /* keep
468 
							     shifting left until top bit = 1 */
 468 
							     shifting left until top bit = 1 */
469 
				exponent = exponent - 1;
 469 
				exponent = exponent - 1;
470 
			}
 470 
			}
471 
		}
 471 
		}
472 
		result = exponent << 23 | (fraction & 0x7fffff); /* mask
 472 
		result = exponent << 23 | (fraction & 0x7fffff); /* mask
473 
								    off top bit; assumed 1 */
 473 
								    off top bit; assumed 1 */
474 
	}
 474 
	}
475 
	return result;
 475 
	return result;
476 
}
 476 
}
477 
 
 477 
 
478 
int r600_blit_init(struct radeon_device *rdev)
 478 
int r600_blit_init(struct radeon_device *rdev)
479 
{
 479 
{
480 
	u32 obj_size;
 480 
	u32 obj_size;
481 
	int i, r, dwords;
 481 
	int i, r, dwords;
482 
	void *ptr;
 482 
	void *ptr;
483 
	u32 packet2s[16];
 483 
	u32 packet2s[16];
484 
	int num_packet2s = 0;
 484 
	int num_packet2s = 0;
485 
 
 485 
 
486 
	/* pin copy shader into vram if already initialized */
 486 
	/* pin copy shader into vram if already initialized */
487 
	if (rdev->r600_blit.shader_obj)
 487 
	if (rdev->r600_blit.shader_obj)
488 
		goto done;
 488 
		goto done;
489 
 
 489 
 
490 
	mutex_init(&rdev->r600_blit.mutex);
 490 
	mutex_init(&rdev->r600_blit.mutex);
491 
	rdev->r600_blit.state_offset = 0;
 491 
	rdev->r600_blit.state_offset = 0;
492 
 
 492 
 
493 
	if (rdev->family >= CHIP_RV770)
 493 
	if (rdev->family >= CHIP_RV770)
494 
		rdev->r600_blit.state_len = r7xx_default_size;
 494 
		rdev->r600_blit.state_len = r7xx_default_size;
495 
	else
 495 
	else
496 
		rdev->r600_blit.state_len = r6xx_default_size;
 496 
		rdev->r600_blit.state_len = r6xx_default_size;
497 
 
 497 
 
498 
	dwords = rdev->r600_blit.state_len;
 498 
	dwords = rdev->r600_blit.state_len;
499 
	while (dwords & 0xf) {
 499 
	while (dwords & 0xf) {
500 
		packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
 500 
		packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
501 
		dwords++;
 501 
		dwords++;
502 
	}
 502 
	}
503 
 
 503 
 
504 
	obj_size = dwords * 4;
 504 
	obj_size = dwords * 4;
505 
	obj_size = ALIGN(obj_size, 256);
 505 
	obj_size = ALIGN(obj_size, 256);
506 
 
 506 
 
507 
	rdev->r600_blit.vs_offset = obj_size;
 507 
	rdev->r600_blit.vs_offset = obj_size;
508 
	obj_size += r6xx_vs_size * 4;
 508 
	obj_size += r6xx_vs_size * 4;
509 
	obj_size = ALIGN(obj_size, 256);
 509 
	obj_size = ALIGN(obj_size, 256);
510 
 
 510 
 
511 
	rdev->r600_blit.ps_offset = obj_size;
 511 
	rdev->r600_blit.ps_offset = obj_size;
512 
	obj_size += r6xx_ps_size * 4;
 512 
	obj_size += r6xx_ps_size * 4;
513 
	obj_size = ALIGN(obj_size, 256);
 513 
	obj_size = ALIGN(obj_size, 256);
514 
 
 514 
 
515 
	r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 515 
	r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
516 
				&rdev->r600_blit.shader_obj);
 516 
				&rdev->r600_blit.shader_obj);
517 
	if (r) {
 517 
	if (r) {
518 
		DRM_ERROR("r600 failed to allocate shader\n");
 518 
		DRM_ERROR("r600 failed to allocate shader\n");
519 
		return r;
 519 
		return r;
520 
	}
 520 
	}
521 
 
 521 
 
522 
	DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
 522 
	DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
523 
		  obj_size,
 523 
		  obj_size,
524 
		  rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 524 
		  rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
525 
 
 525 
 
526 
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 526 
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
527 
	if (unlikely(r != 0))
 527 
	if (unlikely(r != 0))
528 
		return r;
 528 
		return r;
529 
	r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 529 
	r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
530 
	if (r) {
 530 
	if (r) {
531 
		DRM_ERROR("failed to map blit object %d\n", r);
 531 
		DRM_ERROR("failed to map blit object %d\n", r);
532 
		return r;
 532 
		return r;
533 
	}
 533 
	}
534 
	if (rdev->family >= CHIP_RV770)
 534 
	if (rdev->family >= CHIP_RV770)
535 
        memcpy(ptr + rdev->r600_blit.state_offset,
 535 
        memcpy(ptr + rdev->r600_blit.state_offset,
536 
			    r7xx_default_state, rdev->r600_blit.state_len * 4);
 536 
			    r7xx_default_state, rdev->r600_blit.state_len * 4);
537 
	else
 537 
	else
538 
        memcpy(ptr + rdev->r600_blit.state_offset,
 538 
        memcpy(ptr + rdev->r600_blit.state_offset,
539 
			    r6xx_default_state, rdev->r600_blit.state_len * 4);
 539 
			    r6xx_default_state, rdev->r600_blit.state_len * 4);
540 
	if (num_packet2s)
 540 
	if (num_packet2s)
541 
        memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 541 
        memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
542 
			    packet2s, num_packet2s * 4);
 542 
			    packet2s, num_packet2s * 4);
543 
	for (i = 0; i < r6xx_vs_size; i++)
 543 
	for (i = 0; i < r6xx_vs_size; i++)
544 
		*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
 544 
		*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
545 
	for (i = 0; i < r6xx_ps_size; i++)
 545 
	for (i = 0; i < r6xx_ps_size; i++)
546 
		*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
 546 
		*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
547 
	radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 547 
	radeon_bo_kunmap(rdev->r600_blit.shader_obj);
548 
	radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 548 
	radeon_bo_unreserve(rdev->r600_blit.shader_obj);
549 
 
 549 
 
550 
done:
 550 
done:
551 
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 551 
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
552 
	if (unlikely(r != 0))
 552 
	if (unlikely(r != 0))
553 
		return r;
 553 
		return r;
554 
	r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 554 
	r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
555 
			  &rdev->r600_blit.shader_gpu_addr);
 555 
			  &rdev->r600_blit.shader_gpu_addr);
556 
	radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 556 
	radeon_bo_unreserve(rdev->r600_blit.shader_obj);
557 
	if (r) {
 557 
	if (r) {
558 
		dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 558 
		dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
559 
		return r;
 559 
		return r;
560 
	}
 560 
	}
561 
//   radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 561 
//   radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
562 
 
 562 
 
563 
 
 563 
 
564 
	return 0;
 564 
	return 0;
565 
}
 565 
}
566 
 
 566 
 
567 
void r600_blit_fini(struct radeon_device *rdev)
 567 
void r600_blit_fini(struct radeon_device *rdev)
568 
{
 568 
{
569 
	int r;
 569 
	int r;
570 
 
 570 
 
571 
//   radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 571 
//   radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
572 
	if (rdev->r600_blit.shader_obj == NULL)
 572 
	if (rdev->r600_blit.shader_obj == NULL)
573 
		return;
 573 
		return;
574 
	/* If we can't reserve the bo, unref should be enough to destroy
 574 
	/* If we can't reserve the bo, unref should be enough to destroy
575 
	 * it when it becomes idle.
 575 
	 * it when it becomes idle.
576 
	 */
 576 
	 */
577 
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 577 
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
578 
	if (!r) {
 578 
	if (!r) {
579 
		radeon_bo_unpin(rdev->r600_blit.shader_obj);
 579 
		radeon_bo_unpin(rdev->r600_blit.shader_obj);
580 
		radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 580 
		radeon_bo_unreserve(rdev->r600_blit.shader_obj);
581 
	}
 581 
	}
582 
	radeon_bo_unref(&rdev->r600_blit.shader_obj);
 582 
	radeon_bo_unref(&rdev->r600_blit.shader_obj);
583 
}
 583 
}
584 
 
 584 
 
585 
static int r600_vb_ib_get(struct radeon_device *rdev)
 585 
static int r600_vb_ib_get(struct radeon_device *rdev)
586 
{
 586 
{
587 
	int r;
 587 
	int r;
588 
	r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
 588 
	r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
589 
	if (r) {
 589 
	if (r) {
590 
		DRM_ERROR("failed to get IB for vertex buffer\n");
 590 
		DRM_ERROR("failed to get IB for vertex buffer\n");
591 
		return r;
 591 
		return r;
592 
	}
 592 
	}
593 
 
 593 
 
594 
	rdev->r600_blit.vb_total = 64*1024;
 594 
	rdev->r600_blit.vb_total = 64*1024;
595 
	rdev->r600_blit.vb_used = 0;
 595 
	rdev->r600_blit.vb_used = 0;
596 
	return 0;
 596 
	return 0;
597 
}
 597 
}
598 
 
 598 
 
599 
static void r600_vb_ib_put(struct radeon_device *rdev)
 599 
static void r600_vb_ib_put(struct radeon_device *rdev)
600 
{
 600 
{
601 
	radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
 601 
	radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
602 
	radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
 602 
	radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
603 
}
 603 
}
604 
 
 604 
 
605 
int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
 605 
int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
606 
{
 606 
{
607 
	int r;
 607 
	int r;
608 
	int ring_size, line_size;
 608 
	int ring_size, line_size;
609 
	int max_size;
 609 
	int max_size;
610 
	/* loops of emits 64 + fence emit possible */
 610 
	/* loops of emits 64 + fence emit possible */
611 
	int dwords_per_loop = 76, num_loops;
 611 
	int dwords_per_loop = 76, num_loops;
612 
 
 612 
 
613 
	r = r600_vb_ib_get(rdev);
 613 
	r = r600_vb_ib_get(rdev);
614 
	if (r)
 614 
	if (r)
615 
		return r;
 615 
		return r;
616 
 
 616 
 
617 
	/* set_render_target emits 2 extra dwords on rv6xx */
 617 
	/* set_render_target emits 2 extra dwords on rv6xx */
618 
	if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
 618 
	if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
619 
		dwords_per_loop += 2;
 619 
		dwords_per_loop += 2;
620 
 
 620 
 
621 
	/* 8 bpp vs 32 bpp for xfer unit */
 621 
	/* 8 bpp vs 32 bpp for xfer unit */
622 
	if (size_bytes & 3)
 622 
	if (size_bytes & 3)
623 
		line_size = 8192;
 623 
		line_size = 8192;
624 
	else
 624 
	else
625 
		line_size = 8192*4;
 625 
		line_size = 8192*4;
626 
 
 626 
 
627 
	max_size = 8192 * line_size;
 627 
	max_size = 8192 * line_size;
628 
 
 628 
 
629 
	/* major loops cover the max size transfer */
 629 
	/* major loops cover the max size transfer */
630 
	num_loops = ((size_bytes + max_size) / max_size);
 630 
	num_loops = ((size_bytes + max_size) / max_size);
631 
	/* minor loops cover the extra non aligned bits */
 631 
	/* minor loops cover the extra non aligned bits */
632 
	num_loops += ((size_bytes % line_size) ? 1 : 0);
 632 
	num_loops += ((size_bytes % line_size) ? 1 : 0);
633 
	/* calculate number of loops correctly */
 633 
	/* calculate number of loops correctly */
634 
	ring_size = num_loops * dwords_per_loop;
 634 
	ring_size = num_loops * dwords_per_loop;
635 
	/* set default  + shaders */
 635 
	/* set default  + shaders */
636 
	ring_size += 40; /* shaders + def state */
 636 
	ring_size += 40; /* shaders + def state */
637 
	ring_size += 10; /* fence emit for VB IB */
 637 
	ring_size += 10; /* fence emit for VB IB */
638 
	ring_size += 5; /* done copy */
 638 
	ring_size += 5; /* done copy */
639 
	ring_size += 10; /* fence emit for done copy */
 639 
	ring_size += 10; /* fence emit for done copy */
640 
	r = radeon_ring_lock(rdev, ring_size);
 640 
	r = radeon_ring_lock(rdev, ring_size);
641 
	if (r)
 641 
	if (r)
642 
		return r;
 642 
		return r;
643 
 
 643 
 
644 
	set_default_state(rdev); /* 14 */
 644 
	set_default_state(rdev); /* 14 */
645 
	set_shaders(rdev); /* 26 */
 645 
	set_shaders(rdev); /* 26 */
646 
	return 0;
 646 
	return 0;
647 
}
 647 
}
648 
 
 648 
 
649 
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
 649 
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
650 
{
 650 
{
651 
	int r;
 651 
	int r;
652 
 
 652 
 
653 
	if (rdev->r600_blit.vb_ib)
 653 
	if (rdev->r600_blit.vb_ib)
654 
		r600_vb_ib_put(rdev);
 654 
		r600_vb_ib_put(rdev);
655 
 
 655 
 
656 
	if (fence)
 656 
	if (fence)
657 
		r = radeon_fence_emit(rdev, fence);
 657 
		r = radeon_fence_emit(rdev, fence);
658 
 
 658 
 
659 
	radeon_ring_unlock_commit(rdev);
 659 
	radeon_ring_unlock_commit(rdev);
660 
}
 660 
}
661 
 
 661 
 
662 
void r600_kms_blit_copy(struct radeon_device *rdev,
 662 
void r600_kms_blit_copy(struct radeon_device *rdev,
663 
			u64 src_gpu_addr, u64 dst_gpu_addr,
 663 
			u64 src_gpu_addr, u64 dst_gpu_addr,
664 
			int size_bytes)
 664 
			int size_bytes)
665 
{
 665 
{
666 
	int max_bytes;
 666 
	int max_bytes;
667 
	u64 vb_gpu_addr;
 667 
	u64 vb_gpu_addr;
668 
	u32 *vb;
 668 
	u32 *vb;
669 
 
 669 
 
670 
	DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
 670 
	DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
671 
		  size_bytes, rdev->r600_blit.vb_used);
 671 
		  size_bytes, rdev->r600_blit.vb_used);
672 
	vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
 672 
	vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
673 
	if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
 673 
	if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
674 
		max_bytes = 8192;
 674 
		max_bytes = 8192;
675 
 
 675 
 
676 
		while (size_bytes) {
 676 
		while (size_bytes) {
677 
			int cur_size = size_bytes;
 677 
			int cur_size = size_bytes;
678 
			int src_x = src_gpu_addr & 255;
 678 
			int src_x = src_gpu_addr & 255;
679 
			int dst_x = dst_gpu_addr & 255;
 679 
			int dst_x = dst_gpu_addr & 255;
680 
			int h = 1;
 680 
			int h = 1;
681 
			src_gpu_addr = src_gpu_addr & ~255ULL;
 681 
			src_gpu_addr = src_gpu_addr & ~255ULL;
682 
			dst_gpu_addr = dst_gpu_addr & ~255ULL;
 682 
			dst_gpu_addr = dst_gpu_addr & ~255ULL;
683 
 
 683 
 
684 
			if (!src_x && !dst_x) {
 684 
			if (!src_x && !dst_x) {
685 
				h = (cur_size / max_bytes);
 685 
				h = (cur_size / max_bytes);
686 
				if (h > 8192)
 686 
				if (h > 8192)
687 
					h = 8192;
 687 
					h = 8192;
688 
				if (h == 0)
 688 
				if (h == 0)
689 
					h = 1;
 689 
					h = 1;
690 
				else
 690 
				else
691 
					cur_size = max_bytes;
 691 
					cur_size = max_bytes;
692 
			} else {
 692 
			} else {
693 
				if (cur_size > max_bytes)
 693 
				if (cur_size > max_bytes)
694 
					cur_size = max_bytes;
 694 
					cur_size = max_bytes;
695 
				if (cur_size > (max_bytes - dst_x))
 695 
				if (cur_size > (max_bytes - dst_x))
696 
					cur_size = (max_bytes - dst_x);
 696 
					cur_size = (max_bytes - dst_x);
697 
				if (cur_size > (max_bytes - src_x))
 697 
				if (cur_size > (max_bytes - src_x))
698 
					cur_size = (max_bytes - src_x);
 698 
					cur_size = (max_bytes - src_x);
699 
			}
 699 
			}
700 
 
 700 
 
701 
			if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 701 
			if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
702 
             //  WARN_ON(1);
 702 
             //  WARN_ON(1);
703 
			}
 703 
			}
704 
 
 704 
 
705 
			vb[0] = i2f(dst_x);
 705 
			vb[0] = i2f(dst_x);
706 
			vb[1] = 0;
 706 
			vb[1] = 0;
707 
			vb[2] = i2f(src_x);
 707 
			vb[2] = i2f(src_x);
708 
			vb[3] = 0;
 708 
			vb[3] = 0;
709 
 
 709 
 
710 
			vb[4] = i2f(dst_x);
 710 
			vb[4] = i2f(dst_x);
711 
			vb[5] = i2f(h);
 711 
			vb[5] = i2f(h);
712 
			vb[6] = i2f(src_x);
 712 
			vb[6] = i2f(src_x);
713 
			vb[7] = i2f(h);
 713 
			vb[7] = i2f(h);
714 
 
 714 
 
715 
			vb[8] = i2f(dst_x + cur_size);
 715 
			vb[8] = i2f(dst_x + cur_size);
716 
			vb[9] = i2f(h);
 716 
			vb[9] = i2f(h);
717 
			vb[10] = i2f(src_x + cur_size);
 717 
			vb[10] = i2f(src_x + cur_size);
718 
			vb[11] = i2f(h);
 718 
			vb[11] = i2f(h);
719 
 
 719 
 
720 
			/* src 9 */
 720 
			/* src 9 */
721 
			set_tex_resource(rdev, FMT_8,
 721 
			set_tex_resource(rdev, FMT_8,
722 
					 src_x + cur_size, h, src_x + cur_size,
 722 
					 src_x + cur_size, h, src_x + cur_size,
723 
					 src_gpu_addr);
 723 
					 src_gpu_addr);
724 
 
 724 
 
725 
			/* 5 */
 725 
			/* 5 */
726 
			cp_set_surface_sync(rdev,
 726 
			cp_set_surface_sync(rdev,
727 
					    PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 727 
					    PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
728 
 
 728 
 
729 
			/* dst 23 */
 729 
			/* dst 23 */
730 
			set_render_target(rdev, COLOR_8,
 730 
			set_render_target(rdev, COLOR_8,
731 
					  dst_x + cur_size, h,
 731 
					  dst_x + cur_size, h,
732 
					  dst_gpu_addr);
 732 
					  dst_gpu_addr);
733 
 
 733 
 
734 
			/* scissors 12 */
 734 
			/* scissors 12 */
735 
			set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
 735 
			set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
736 
 
 736 
 
737 
			/* 14 */
 737 
			/* 14 */
738 
			vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 738 
			vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
739 
			set_vtx_resource(rdev, vb_gpu_addr);
 739 
			set_vtx_resource(rdev, vb_gpu_addr);
740 
 
 740 
 
741 
			/* draw 10 */
 741 
			/* draw 10 */
742 
			draw_auto(rdev);
 742 
			draw_auto(rdev);
743 
 
 743 
 
744 
			/* 5 */
 744 
			/* 5 */
745 
			cp_set_surface_sync(rdev,
 745 
			cp_set_surface_sync(rdev,
746 
					    PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 746 
					    PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
747 
					    cur_size * h, dst_gpu_addr);
 747 
					    cur_size * h, dst_gpu_addr);
748 
 
 748 
 
749 
			vb += 12;
 749 
			vb += 12;
750 
			rdev->r600_blit.vb_used += 12 * 4;
 750 
			rdev->r600_blit.vb_used += 12 * 4;
751 
 
 751 
 
752 
			src_gpu_addr += cur_size * h;
 752 
			src_gpu_addr += cur_size * h;
753 
			dst_gpu_addr += cur_size * h;
 753 
			dst_gpu_addr += cur_size * h;
754 
			size_bytes -= cur_size * h;
 754 
			size_bytes -= cur_size * h;
755 
		}
 755 
		}
756 
	} else {
 756 
	} else {
757 
		max_bytes = 8192 * 4;
 757 
		max_bytes = 8192 * 4;
758 
 
 758 
 
759 
		while (size_bytes) {
 759 
		while (size_bytes) {
760 
			int cur_size = size_bytes;
 760 
			int cur_size = size_bytes;
761 
			int src_x = (src_gpu_addr & 255);
 761 
			int src_x = (src_gpu_addr & 255);
762 
			int dst_x = (dst_gpu_addr & 255);
 762 
			int dst_x = (dst_gpu_addr & 255);
763 
			int h = 1;
 763 
			int h = 1;
764 
			src_gpu_addr = src_gpu_addr & ~255ULL;
 764 
			src_gpu_addr = src_gpu_addr & ~255ULL;
765 
			dst_gpu_addr = dst_gpu_addr & ~255ULL;
 765 
			dst_gpu_addr = dst_gpu_addr & ~255ULL;
766 
 
 766 
 
767 
			if (!src_x && !dst_x) {
 767 
			if (!src_x && !dst_x) {
768 
				h = (cur_size / max_bytes);
 768 
				h = (cur_size / max_bytes);
769 
				if (h > 8192)
 769 
				if (h > 8192)
770 
					h = 8192;
 770 
					h = 8192;
771 
				if (h == 0)
 771 
				if (h == 0)
772 
					h = 1;
 772 
					h = 1;
773 
				else
 773 
				else
774 
					cur_size = max_bytes;
 774 
					cur_size = max_bytes;
775 
			} else {
 775 
			} else {
776 
				if (cur_size > max_bytes)
 776 
				if (cur_size > max_bytes)
777 
					cur_size = max_bytes;
 777 
					cur_size = max_bytes;
778 
				if (cur_size > (max_bytes - dst_x))
 778 
				if (cur_size > (max_bytes - dst_x))
779 
					cur_size = (max_bytes - dst_x);
 779 
					cur_size = (max_bytes - dst_x);
780 
				if (cur_size > (max_bytes - src_x))
 780 
				if (cur_size > (max_bytes - src_x))
781 
					cur_size = (max_bytes - src_x);
 781 
					cur_size = (max_bytes - src_x);
782 
			}
 782 
			}
783 
 
 783 
 
784 
			if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 784 
			if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
785 
              // WARN_ON(1);
 785 
              // WARN_ON(1);
786 
			}
 786 
			}
787 
 
 787 
 
788 
			vb[0] = i2f(dst_x / 4);
 788 
			vb[0] = i2f(dst_x / 4);
789 
			vb[1] = 0;
 789 
			vb[1] = 0;
790 
			vb[2] = i2f(src_x / 4);
 790 
			vb[2] = i2f(src_x / 4);
791 
			vb[3] = 0;
 791 
			vb[3] = 0;
792 
 
 792 
 
793 
			vb[4] = i2f(dst_x / 4);
 793 
			vb[4] = i2f(dst_x / 4);
794 
			vb[5] = i2f(h);
 794 
			vb[5] = i2f(h);
795 
			vb[6] = i2f(src_x / 4);
 795 
			vb[6] = i2f(src_x / 4);
796 
			vb[7] = i2f(h);
 796 
			vb[7] = i2f(h);
797 
 
 797 
 
798 
			vb[8] = i2f((dst_x + cur_size) / 4);
 798 
			vb[8] = i2f((dst_x + cur_size) / 4);
799 
			vb[9] = i2f(h);
 799 
			vb[9] = i2f(h);
800 
			vb[10] = i2f((src_x + cur_size) / 4);
 800 
			vb[10] = i2f((src_x + cur_size) / 4);
801 
			vb[11] = i2f(h);
 801 
			vb[11] = i2f(h);
802 
 
 802 
 
803 
			/* src 9 */
 803 
			/* src 9 */
804 
			set_tex_resource(rdev, FMT_8_8_8_8,
 804 
			set_tex_resource(rdev, FMT_8_8_8_8,
805 
					 (src_x + cur_size) / 4,
 805 
					 (src_x + cur_size) / 4,
806 
					 h, (src_x + cur_size) / 4,
 806 
					 h, (src_x + cur_size) / 4,
807 
					 src_gpu_addr);
 807 
					 src_gpu_addr);
808 
			/* 5 */
 808 
			/* 5 */
809 
			cp_set_surface_sync(rdev,
 809 
			cp_set_surface_sync(rdev,
810 
					    PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 810 
					    PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
811 
 
 811 
 
812 
			/* dst 23 */
 812 
			/* dst 23 */
813 
			set_render_target(rdev, COLOR_8_8_8_8,
 813 
			set_render_target(rdev, COLOR_8_8_8_8,
814 
					  (dst_x + cur_size) / 4, h,
 814 
					  (dst_x + cur_size) / 4, h,
815 
					  dst_gpu_addr);
 815 
					  dst_gpu_addr);
816 
 
 816 
 
817 
			/* scissors 12  */
 817 
			/* scissors 12  */
818 
			set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
 818 
			set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
819 
 
 819 
 
820 
			/* Vertex buffer setup 14 */
 820 
			/* Vertex buffer setup 14 */
821 
			vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 821 
			vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
822 
			set_vtx_resource(rdev, vb_gpu_addr);
 822 
			set_vtx_resource(rdev, vb_gpu_addr);
823 
 
 823 
 
824 
			/* draw 10 */
 824 
			/* draw 10 */
825 
			draw_auto(rdev);
 825 
			draw_auto(rdev);
826 
 
 826 
 
827 
			/* 5 */
 827 
			/* 5 */
828 
			cp_set_surface_sync(rdev,
 828 
			cp_set_surface_sync(rdev,
829 
					    PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 829 
					    PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
830 
					    cur_size * h, dst_gpu_addr);
 830 
					    cur_size * h, dst_gpu_addr);
831 
 
 831 
 
832 
			/* 78 ring dwords per loop */
 832 
			/* 78 ring dwords per loop */
833 
			vb += 12;
 833 
			vb += 12;
834 
			rdev->r600_blit.vb_used += 12 * 4;
 834 
			rdev->r600_blit.vb_used += 12 * 4;
835 
 
 835 
 
836 
			src_gpu_addr += cur_size * h;
 836 
			src_gpu_addr += cur_size * h;
837 
			dst_gpu_addr += cur_size * h;
 837 
			dst_gpu_addr += cur_size * h;
838 
			size_bytes -= cur_size * h;
 838 
			size_bytes -= cur_size * h;
839 
		}
 839 
		}
840 
	}
 840 
	}
841 
}
 841 
}
842 
 
 842 

          

          

            843
            
 

            -
            
 

          

          

            844
            
void r600_kms_video_blit(struct radeon_device *rdev,

            -
            
 

          

          

            845
            
            u64 src_gpu_addr, int dstx, int dsty, int w, int h, int pitch)

            -
            
 

          

          

            846
            
{

            -
            
 

          

          

            847
            
    u64 vb_gpu_addr;

            -
            
 

          

          

            848
            
    u32 *vb;

            -
            
 

          

          

            849
            
 

            -
            
 

          

          

            850
            
//    DRM_DEBUG("emitting video copy\n");

            -
            
 

          

          

            851
            
    vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);

            -
            
 

          

          

            852
            
 

            -
            
 

          

          

            853
            
    if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {

            -
            
 

          

          

            854
            
              // WARN_ON(1);

            -
            
 

          

          

            855
            
    }

            -
            
 

          

          

            856
            
 

            -
            
 

          

          

            857
            
    vb[0] = i2f(dstx);

            -
            
 

          

          

            858
            
    vb[1] = i2f(dsty);

            -
            
 

          

          

            859
            
    vb[2] = 0;

            -
            
 

          

          

            860
            
    vb[3] = 0;

            -
            
 

          

          

            861
            
 

            -
            
 

          

          

            862
            
    vb[4] = i2f(dstx);

            -
            
 

          

          

            863
            
    vb[5] = i2f(dsty+h);

            -
            
 

          

          

            864
            
    vb[6] = 0;

            -
            
 

          

          

            865
            
    vb[7] = i2f(h);

            -
            
 

          

          

            866
            
 

            -
            
 

          

          

            867
            
    vb[8] = i2f(dstx + w);

            -
            
 

          

          

            868
            
    vb[9] = i2f(dsty + h);

            -
            
 

          

          

            869
            
    vb[10] = i2f(w);

            -
            
 

          

          

            870
            
    vb[11] = i2f(h);

            -
            
 

          

          

            871
            
 

            -
            
 

          

          

            872
            
    /* src 9 */

            -
            
 

          

          

            873
            
    set_tex_resource(rdev, FMT_8_8_8_8,

            -
            
 

          

          

            874
            
                     w, h, pitch/4, src_gpu_addr);

            -
            
 

          

          

            875
            
    /* 5 */

            -
            
 

          

          

            876
            
    cp_set_surface_sync(rdev,

            -
            
 

          

          

            877
            
                        PACKET3_TC_ACTION_ENA, pitch * h, src_gpu_addr);

            -
            
 

          

          

            878
            
 

            -
            
 

          

          

            879
            
    /* dst 23 */

            -
            
 

          

          

            880
            
    set_render_target(rdev, COLOR_8_8_8_8,

            -
            
 

          

          

            881
            
                     1024, 768, rdev->mc.vram_start);

            -
            
 

          

          

            882
            
 

            -
            
 

          

          

            883
            
            /* scissors 12  */

            -
            
 

          

          

            884
            
    set_scissors(rdev, 0, 0, 1024, 768);

            -
            
 

          

          

            885
            
 

            -
            
 

          

          

            886
            
    /* Vertex buffer setup 14 */

            -
            
 

          

          

            887
            
    vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;

            -
            
 

          

          

            888
            
    set_vtx_resource(rdev, vb_gpu_addr);

            -
            
 

          

          

            889
            
 

            -
            
 

          

          

            890
            
    /* draw 10 */

            -
            
 

          

          

            891
            
    draw_auto(rdev);

            -
            
 

          

          

            892
            
 

            -
            
 

          

          

            893
            
    /* 5 */

            -
            
 

          

          

            894
            
    cp_set_surface_sync(rdev,

            -
            
 

          

          

            895
            
                PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,

            -
            
 

          

          

            896
            
                1024*4*768, rdev->mc.vram_start);

            -
            
 

          

          

            897
            
 

            -
            
 

          

          

            898
            
    /* 78 ring dwords per loop */

            -
            
 

          

          

            899
            
    vb += 12;

            -
            
 

          

          

            900
            
    rdev->r600_blit.vb_used += 12 * 4;

            -
            
 

          

          

            901
            
 

            -
            
 

          

          

            902
            
}

            -
            
 

          

          

            903
            
 

            -
            
 

          

          

            904
            
extern struct radeon_device *main_device;

            -
            
 

          

          

            905
            
 

            -
            
 

          

          

            906
            
int r600_video_blit(uint64_t src_offset, int  x, int y,

            -
            
 

          

          

            907
            
                    int w, int h, int pitch)

            -
            
 

          

          

            908
            
{

            -
            
 

          

          

            909
            
    struct radeon_device *rdev = main_device;

            -
            
 

          

          

            910
            
    static struct radeon_fence *fence;

            -
            
 

          

          

            911
            
    unsigned long irq_flags;

            -
            
 

          

          

            912
            
 

            -
            
 

          

          

            913
            
    int r;

            -
            
 

          

          

            914
            
 

            -
            
 

          

          

            915
            
    if(fence == NULL)

            -
            
 

          

          

            916
            
    {

            -
            
 

          

          

            917
            
        r = radeon_fence_create(rdev, &fence);

            -
            
 

          

          

            918
            
        if (r) {

            -
            
 

          

          

            919
            
            printf("%s epic fail", __FUNCTION__);

            -
            
 

          

          

            920
            
            return r;

            -
            
 

          

          

            921
            
        }

            -
            
 

          

          

            922
            
    };

            -
            
 

          

          

            923
            
 

            -
            
 

          

          

            924
            
    fence->evnt = CreateEvent(NULL, 0);

            -
            
 

          

          

            925
            
 

            -
            
 

          

          

            926
            
    mutex_lock(&rdev->r600_blit.mutex);

            -
            
 

          

          

            927
            
    rdev->r600_blit.vb_ib = NULL;

            -
            
 

          

          

            928
            
    r = r600_blit_prepare_copy(rdev, h*pitch);

            -
            
 

          

          

            929
            
    if (r) {

            -
            
 

          

          

            930
            
//       if (rdev->r600_blit.vb_ib)

            -
            
 

          

          

            931
            
//           radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);

            -
            
 

          

          

            932
            
        mutex_unlock(&rdev->r600_blit.mutex);

            -
            
 

          

          

            933
            
        return r;

            -
            
 

          

          

            934
            
    }

            -
            
 

          

          

            935
            
 

            -
            
 

          

          

            936
            
    r600_kms_video_blit(rdev, src_offset,x,y,w,h,pitch);

            -
            
 

          

          

            937
            
    r600_blit_done_copy(rdev, fence);

            -
            
 

          

          

            938
            
    mutex_unlock(&rdev->r600_blit.mutex);

            -
            
 

          

          

            939
            
 

            -
            
 

          

          

            940
            
    r = radeon_fence_wait(fence, false);

            -
            
 

          

          

            941
            
 

            -
            
 

          

          

            942
            
    write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);

            -
            
 

          

          

            943
            
    list_del(&fence->list);

            -
            
 

          

          

            944
            
    fence->emited = false;

            -
            
 

          

          

            945
            
    fence->signaled = false;

            -
            
 

          

          

            946
            
    write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);

            -
            
 

          

          

            947
            
 

            -
            
 

          

          

            948
            
    return r;

            -
            
 

          

          

            949
            
};

            -
            
 

          

          

            950
            
 

            -
            
 

          

          

            951
            
int r600_create_video(int w, int h, u32_t *outp)

            -
            
 

          

          

            952
            
{

            -
            
 

          

          

            953
            
    int r;

            -
            
 

          

          

            954
            
    struct radeon_device *rdev = main_device;

            -
            
 

          

          

            955
            
    struct radeon_bo *sobj = NULL;

            -
            
 

          

          

            956
            
    uint64_t saddr;

            -
            
 

          

          

            957
            
    void   *uaddr;

            -
            
 

          

          

            958
            
 

            -
            
 

          

          

            959
            
    size_t size;

            -
            
 

          

          

            960
            
    size_t pitch;

            -
            
 

          

          

            961
            
 

            -
            
 

          

          

            962
            
    pitch = radeon_align_pitch(rdev, w, 32, false) * 4;

            -
            
 

          

          

            963
            
 

            -
            
 

          

          

            964
            
    size = pitch * h;

            -
            
 

          

          

            965
            
    r = radeon_bo_create(rdev, size, PAGE_SIZE, true,

            -
            
 

          

          

            966
            
                         RADEON_GEM_DOMAIN_GTT, &sobj);

            -
            
 

          

          

            967
            
    if (r) {

            -
            
 

          

          

            968
            
        goto fail;

            -
            
 

          

          

            969
            
    }

            -
            
 

          

          

            970
            
    r = radeon_bo_reserve(sobj, false);

            -
            
 

          

          

            971
            
    if (unlikely(r != 0))

            -
            
 

          

          

            972
            
        goto fail;

            -
            
 

          

          

            973
            
    r = radeon_bo_pin(sobj, RADEON_GEM_DOMAIN_GTT, &saddr);

            -
            
 

          

          

            974
            
//   radeon_bo_unreserve(sobj);

            -
            
 

          

          

            975
            
    if (r) {

            -
            
 

          

          

            976
            
        goto fail;

            -
            
 

          

          

            977
            
    }

            -
            
 

          

          

            978
            
 

            -
            
 

          

          

            979
            
    r = radeon_bo_user_map(sobj, &uaddr);

            -
            
 

          

          

            980
            
    if (r) {

            -
            
 

          

          

            981
            
        goto fail;

            -
            
 

          

          

            982
            
    }

            -
            
 

          

          

            983
            
 

            -
            
 

          

          

            984
            
    ((uint64_t*)outp)[0] = saddr;

            -
            
 

          

          

            985
            
    outp[2] = uaddr;

            -
            
 

          

          

            986
            
    outp[3] = pitch;

            -
            
 

          

          

            987
            
 

            -
            
 

          

          

            988
            
//    dbgprintf("Create video surface %x, mapped at %x pitch %d\n",

            -
            
 

          

          

            989
            
//              (uint32_t)saddr, uaddr, pitch);

            -
            
 

          

          

            990
            
    return 0;

            -
            
 

          

          

            991
            
 

            -
            
 

          

          

            992
            
fail:

            -
            
 

          

          

            993
            
    return -1;

            -
            
 

          

          

            994
            
};

            -