Rev 3764 | Go to most recent revision | Only display areas with differences | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 3764 | Rev 5078 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include "radeon_reg.h" |
31 | #include "radeon_reg.h" |
32 | #include "radeon.h" |
32 | #include "radeon.h" |
33 | #include "radeon_asic.h" |
33 | #include "radeon_asic.h" |
34 | #include "atom.h" |
34 | #include "atom.h" |
35 | #include "r100d.h" |
35 | #include "r100d.h" |
36 | #include "r420d.h" |
36 | #include "r420d.h" |
37 | #include "r420_reg_safe.h" |
37 | #include "r420_reg_safe.h" |
38 | 38 | ||
39 | void r420_pm_init_profile(struct radeon_device *rdev) |
39 | void r420_pm_init_profile(struct radeon_device *rdev) |
40 | { |
40 | { |
41 | /* default */ |
41 | /* default */ |
42 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
42 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
43 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
43 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
44 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
44 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
45 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
45 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
46 | /* low sh */ |
46 | /* low sh */ |
47 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; |
47 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; |
48 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; |
48 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; |
49 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
49 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
50 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
50 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
51 | /* mid sh */ |
51 | /* mid sh */ |
52 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; |
52 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; |
53 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; |
53 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; |
54 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
54 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
55 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
55 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
56 | /* high sh */ |
56 | /* high sh */ |
57 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; |
57 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; |
58 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
58 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
59 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
59 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
60 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
60 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
61 | /* low mh */ |
61 | /* low mh */ |
62 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; |
62 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; |
63 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
63 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
64 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
64 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
65 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
65 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
66 | /* mid mh */ |
66 | /* mid mh */ |
67 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; |
67 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; |
68 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
68 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
69 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
69 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
70 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
70 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
71 | /* high mh */ |
71 | /* high mh */ |
72 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; |
72 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; |
73 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
73 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
74 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
74 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
75 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
75 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
76 | } |
76 | } |
77 | 77 | ||
78 | static void r420_set_reg_safe(struct radeon_device *rdev) |
78 | static void r420_set_reg_safe(struct radeon_device *rdev) |
79 | { |
79 | { |
80 | rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; |
80 | rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; |
81 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); |
81 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); |
82 | } |
82 | } |
83 | 83 | ||
84 | void r420_pipes_init(struct radeon_device *rdev) |
84 | void r420_pipes_init(struct radeon_device *rdev) |
85 | { |
85 | { |
86 | unsigned tmp; |
86 | unsigned tmp; |
87 | unsigned gb_pipe_select; |
87 | unsigned gb_pipe_select; |
88 | unsigned num_pipes; |
88 | unsigned num_pipes; |
89 | 89 | ||
90 | /* GA_ENHANCE workaround TCL deadlock issue */ |
90 | /* GA_ENHANCE workaround TCL deadlock issue */ |
91 | WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | |
91 | WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | |
92 | (1 << 2) | (1 << 3)); |
92 | (1 << 2) | (1 << 3)); |
93 | /* add idle wait as per freedesktop.org bug 24041 */ |
93 | /* add idle wait as per freedesktop.org bug 24041 */ |
94 | if (r100_gui_wait_for_idle(rdev)) { |
94 | if (r100_gui_wait_for_idle(rdev)) { |
95 | printk(KERN_WARNING "Failed to wait GUI idle while " |
95 | printk(KERN_WARNING "Failed to wait GUI idle while " |
96 | "programming pipes. Bad things might happen.\n"); |
96 | "programming pipes. Bad things might happen.\n"); |
97 | } |
97 | } |
98 | /* get max number of pipes */ |
98 | /* get max number of pipes */ |
99 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
99 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
100 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
100 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
101 | 101 | ||
102 | /* SE chips have 1 pipe */ |
102 | /* SE chips have 1 pipe */ |
103 | if ((rdev->pdev->device == 0x5e4c) || |
103 | if ((rdev->pdev->device == 0x5e4c) || |
104 | (rdev->pdev->device == 0x5e4f)) |
104 | (rdev->pdev->device == 0x5e4f)) |
105 | num_pipes = 1; |
105 | num_pipes = 1; |
106 | 106 | ||
107 | rdev->num_gb_pipes = num_pipes; |
107 | rdev->num_gb_pipes = num_pipes; |
108 | tmp = 0; |
108 | tmp = 0; |
109 | switch (num_pipes) { |
109 | switch (num_pipes) { |
110 | default: |
110 | default: |
111 | /* force to 1 pipe */ |
111 | /* force to 1 pipe */ |
112 | num_pipes = 1; |
112 | num_pipes = 1; |
113 | case 1: |
113 | case 1: |
114 | tmp = (0 << 1); |
114 | tmp = (0 << 1); |
115 | break; |
115 | break; |
116 | case 2: |
116 | case 2: |
117 | tmp = (3 << 1); |
117 | tmp = (3 << 1); |
118 | break; |
118 | break; |
119 | case 3: |
119 | case 3: |
120 | tmp = (6 << 1); |
120 | tmp = (6 << 1); |
121 | break; |
121 | break; |
122 | case 4: |
122 | case 4: |
123 | tmp = (7 << 1); |
123 | tmp = (7 << 1); |
124 | break; |
124 | break; |
125 | } |
125 | } |
126 | WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); |
126 | WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); |
127 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
127 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
128 | tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; |
128 | tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; |
129 | WREG32(R300_GB_TILE_CONFIG, tmp); |
129 | WREG32(R300_GB_TILE_CONFIG, tmp); |
130 | if (r100_gui_wait_for_idle(rdev)) { |
130 | if (r100_gui_wait_for_idle(rdev)) { |
131 | printk(KERN_WARNING "Failed to wait GUI idle while " |
131 | printk(KERN_WARNING "Failed to wait GUI idle while " |
132 | "programming pipes. Bad things might happen.\n"); |
132 | "programming pipes. Bad things might happen.\n"); |
133 | } |
133 | } |
134 | 134 | ||
135 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
135 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
136 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); |
136 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); |
137 | 137 | ||
138 | WREG32(R300_RB2D_DSTCACHE_MODE, |
138 | WREG32(R300_RB2D_DSTCACHE_MODE, |
139 | RREG32(R300_RB2D_DSTCACHE_MODE) | |
139 | RREG32(R300_RB2D_DSTCACHE_MODE) | |
140 | R300_DC_AUTOFLUSH_ENABLE | |
140 | R300_DC_AUTOFLUSH_ENABLE | |
141 | R300_DC_DC_DISABLE_IGNORE_PE); |
141 | R300_DC_DC_DISABLE_IGNORE_PE); |
142 | 142 | ||
143 | if (r100_gui_wait_for_idle(rdev)) { |
143 | if (r100_gui_wait_for_idle(rdev)) { |
144 | printk(KERN_WARNING "Failed to wait GUI idle while " |
144 | printk(KERN_WARNING "Failed to wait GUI idle while " |
145 | "programming pipes. Bad things might happen.\n"); |
145 | "programming pipes. Bad things might happen.\n"); |
146 | } |
146 | } |
147 | 147 | ||
148 | if (rdev->family == CHIP_RV530) { |
148 | if (rdev->family == CHIP_RV530) { |
149 | tmp = RREG32(RV530_GB_PIPE_SELECT2); |
149 | tmp = RREG32(RV530_GB_PIPE_SELECT2); |
150 | if ((tmp & 3) == 3) |
150 | if ((tmp & 3) == 3) |
151 | rdev->num_z_pipes = 2; |
151 | rdev->num_z_pipes = 2; |
152 | else |
152 | else |
153 | rdev->num_z_pipes = 1; |
153 | rdev->num_z_pipes = 1; |
154 | } else |
154 | } else |
155 | rdev->num_z_pipes = 1; |
155 | rdev->num_z_pipes = 1; |
156 | 156 | ||
157 | DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", |
157 | DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", |
158 | rdev->num_gb_pipes, rdev->num_z_pipes); |
158 | rdev->num_gb_pipes, rdev->num_z_pipes); |
159 | } |
159 | } |
160 | 160 | ||
161 | u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) |
161 | u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) |
162 | { |
162 | { |
- | 163 | unsigned long flags; |
|
163 | u32 r; |
164 | u32 r; |
- | 165 | ||
164 | 166 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
|
165 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); |
167 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); |
- | 168 | r = RREG32(R_0001FC_MC_IND_DATA); |
|
166 | r = RREG32(R_0001FC_MC_IND_DATA); |
169 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
167 | return r; |
170 | return r; |
168 | } |
171 | } |
169 | 172 | ||
170 | void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
173 | void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
171 | { |
174 | { |
- | 175 | unsigned long flags; |
|
- | 176 | ||
- | 177 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
|
172 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | |
178 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | |
173 | S_0001F8_MC_IND_WR_EN(1)); |
179 | S_0001F8_MC_IND_WR_EN(1)); |
174 | WREG32(R_0001FC_MC_IND_DATA, v); |
180 | WREG32(R_0001FC_MC_IND_DATA, v); |
- | 181 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
|
175 | } |
182 | } |
176 | 183 | ||
177 | static void r420_debugfs(struct radeon_device *rdev) |
184 | static void r420_debugfs(struct radeon_device *rdev) |
178 | { |
185 | { |
179 | if (r100_debugfs_rbbm_init(rdev)) { |
186 | if (r100_debugfs_rbbm_init(rdev)) { |
180 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
187 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
181 | } |
188 | } |
182 | if (r420_debugfs_pipes_info_init(rdev)) { |
189 | if (r420_debugfs_pipes_info_init(rdev)) { |
183 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
190 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
184 | } |
191 | } |
185 | } |
192 | } |
186 | 193 | ||
187 | static void r420_clock_resume(struct radeon_device *rdev) |
194 | static void r420_clock_resume(struct radeon_device *rdev) |
188 | { |
195 | { |
189 | u32 sclk_cntl; |
196 | u32 sclk_cntl; |
190 | 197 | ||
191 | if (radeon_dynclks != -1 && radeon_dynclks) |
198 | if (radeon_dynclks != -1 && radeon_dynclks) |
192 | radeon_atom_set_clock_gating(rdev, 1); |
199 | radeon_atom_set_clock_gating(rdev, 1); |
193 | sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); |
200 | sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); |
194 | sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
201 | sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
195 | if (rdev->family == CHIP_R420) |
202 | if (rdev->family == CHIP_R420) |
196 | sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); |
203 | sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); |
197 | WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); |
204 | WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); |
198 | } |
205 | } |
199 | 206 | ||
200 | static void r420_cp_errata_init(struct radeon_device *rdev) |
207 | static void r420_cp_errata_init(struct radeon_device *rdev) |
201 | { |
208 | { |
202 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
209 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
203 | 210 | ||
204 | /* RV410 and R420 can lock up if CP DMA to host memory happens |
211 | /* RV410 and R420 can lock up if CP DMA to host memory happens |
205 | * while the 2D engine is busy. |
212 | * while the 2D engine is busy. |
206 | * |
213 | * |
207 | * The proper workaround is to queue a RESYNC at the beginning |
214 | * The proper workaround is to queue a RESYNC at the beginning |
208 | * of the CP init, apparently. |
215 | * of the CP init, apparently. |
209 | */ |
216 | */ |
210 | radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); |
217 | radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); |
211 | radeon_ring_lock(rdev, ring, 8); |
218 | radeon_ring_lock(rdev, ring, 8); |
212 | radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); |
219 | radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); |
213 | radeon_ring_write(ring, rdev->config.r300.resync_scratch); |
220 | radeon_ring_write(ring, rdev->config.r300.resync_scratch); |
214 | radeon_ring_write(ring, 0xDEADBEEF); |
221 | radeon_ring_write(ring, 0xDEADBEEF); |
215 | radeon_ring_unlock_commit(rdev, ring); |
222 | radeon_ring_unlock_commit(rdev, ring, false); |
216 | } |
223 | } |
217 | 224 | ||
218 | static void r420_cp_errata_fini(struct radeon_device *rdev) |
225 | static void r420_cp_errata_fini(struct radeon_device *rdev) |
219 | { |
226 | { |
220 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
227 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
221 | 228 | ||
222 | /* Catch the RESYNC we dispatched all the way back, |
229 | /* Catch the RESYNC we dispatched all the way back, |
223 | * at the very beginning of the CP init. |
230 | * at the very beginning of the CP init. |
224 | */ |
231 | */ |
225 | radeon_ring_lock(rdev, ring, 8); |
232 | radeon_ring_lock(rdev, ring, 8); |
226 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
233 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
227 | radeon_ring_write(ring, R300_RB3D_DC_FINISH); |
234 | radeon_ring_write(ring, R300_RB3D_DC_FINISH); |
228 | radeon_ring_unlock_commit(rdev, ring); |
235 | radeon_ring_unlock_commit(rdev, ring, false); |
229 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); |
236 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); |
230 | } |
237 | } |
231 | 238 | ||
232 | static int r420_startup(struct radeon_device *rdev) |
239 | static int r420_startup(struct radeon_device *rdev) |
233 | { |
240 | { |
234 | int r; |
241 | int r; |
235 | 242 | ||
236 | /* set common regs */ |
243 | /* set common regs */ |
237 | r100_set_common_regs(rdev); |
244 | r100_set_common_regs(rdev); |
238 | /* program mc */ |
245 | /* program mc */ |
239 | r300_mc_program(rdev); |
246 | r300_mc_program(rdev); |
240 | /* Resume clock */ |
247 | /* Resume clock */ |
241 | r420_clock_resume(rdev); |
248 | r420_clock_resume(rdev); |
242 | /* Initialize GART (initialize after TTM so we can allocate |
249 | /* Initialize GART (initialize after TTM so we can allocate |
243 | * memory through TTM but finalize after TTM) */ |
250 | * memory through TTM but finalize after TTM) */ |
244 | if (rdev->flags & RADEON_IS_PCIE) { |
251 | if (rdev->flags & RADEON_IS_PCIE) { |
245 | r = rv370_pcie_gart_enable(rdev); |
252 | r = rv370_pcie_gart_enable(rdev); |
246 | if (r) |
253 | if (r) |
247 | return r; |
254 | return r; |
248 | } |
255 | } |
249 | if (rdev->flags & RADEON_IS_PCI) { |
256 | if (rdev->flags & RADEON_IS_PCI) { |
250 | r = r100_pci_gart_enable(rdev); |
257 | r = r100_pci_gart_enable(rdev); |
251 | if (r) |
258 | if (r) |
252 | return r; |
259 | return r; |
253 | } |
260 | } |
254 | r420_pipes_init(rdev); |
261 | r420_pipes_init(rdev); |
255 | 262 | ||
256 | /* allocate wb buffer */ |
263 | /* allocate wb buffer */ |
257 | r = radeon_wb_init(rdev); |
264 | r = radeon_wb_init(rdev); |
258 | if (r) |
265 | if (r) |
259 | return r; |
266 | return r; |
260 | 267 | ||
261 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
268 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
262 | if (r) { |
269 | if (r) { |
263 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
270 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
264 | return r; |
271 | return r; |
265 | } |
272 | } |
266 | 273 | ||
267 | /* Enable IRQ */ |
274 | /* Enable IRQ */ |
268 | if (!rdev->irq.installed) { |
275 | if (!rdev->irq.installed) { |
269 | r = radeon_irq_kms_init(rdev); |
276 | r = radeon_irq_kms_init(rdev); |
270 | if (r) |
277 | if (r) |
271 | return r; |
278 | return r; |
272 | } |
279 | } |
273 | 280 | ||
274 | r100_irq_set(rdev); |
281 | r100_irq_set(rdev); |
275 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
282 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
276 | /* 1M ring buffer */ |
283 | /* 1M ring buffer */ |
277 | r = r100_cp_init(rdev, 1024 * 1024); |
284 | r = r100_cp_init(rdev, 1024 * 1024); |
278 | if (r) { |
285 | if (r) { |
279 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
286 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
280 | return r; |
287 | return r; |
281 | } |
288 | } |
282 | r420_cp_errata_init(rdev); |
289 | r420_cp_errata_init(rdev); |
283 | 290 | ||
284 | r = radeon_ib_pool_init(rdev); |
291 | r = radeon_ib_pool_init(rdev); |
285 | if (r) { |
292 | if (r) { |
286 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
293 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
287 | return r; |
294 | return r; |
288 | } |
295 | } |
289 | 296 | ||
290 | return 0; |
297 | return 0; |
291 | } |
298 | } |
292 | 299 | ||
293 | 300 | ||
294 | 301 | ||
295 | 302 | ||
296 | 303 | ||
297 | 304 | ||
298 | int r420_init(struct radeon_device *rdev) |
305 | int r420_init(struct radeon_device *rdev) |
299 | { |
306 | { |
300 | int r; |
307 | int r; |
301 | 308 | ||
302 | /* Initialize scratch registers */ |
309 | /* Initialize scratch registers */ |
303 | radeon_scratch_init(rdev); |
310 | radeon_scratch_init(rdev); |
304 | /* Initialize surface registers */ |
311 | /* Initialize surface registers */ |
305 | radeon_surface_init(rdev); |
312 | radeon_surface_init(rdev); |
306 | /* TODO: disable VGA need to use VGA request */ |
313 | /* TODO: disable VGA need to use VGA request */ |
307 | /* restore some register to sane defaults */ |
314 | /* restore some register to sane defaults */ |
308 | r100_restore_sanity(rdev); |
315 | r100_restore_sanity(rdev); |
309 | /* BIOS*/ |
316 | /* BIOS*/ |
310 | if (!radeon_get_bios(rdev)) { |
317 | if (!radeon_get_bios(rdev)) { |
311 | if (ASIC_IS_AVIVO(rdev)) |
318 | if (ASIC_IS_AVIVO(rdev)) |
312 | return -EINVAL; |
319 | return -EINVAL; |
313 | } |
320 | } |
314 | if (rdev->is_atom_bios) { |
321 | if (rdev->is_atom_bios) { |
315 | r = radeon_atombios_init(rdev); |
322 | r = radeon_atombios_init(rdev); |
316 | if (r) { |
323 | if (r) { |
317 | return r; |
324 | return r; |
318 | } |
325 | } |
319 | } else { |
326 | } else { |
320 | r = radeon_combios_init(rdev); |
327 | r = radeon_combios_init(rdev); |
321 | if (r) { |
328 | if (r) { |
322 | return r; |
329 | return r; |
323 | } |
330 | } |
324 | } |
331 | } |
325 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
332 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
326 | if (radeon_asic_reset(rdev)) { |
333 | if (radeon_asic_reset(rdev)) { |
327 | dev_warn(rdev->dev, |
334 | dev_warn(rdev->dev, |
328 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
335 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
329 | RREG32(R_000E40_RBBM_STATUS), |
336 | RREG32(R_000E40_RBBM_STATUS), |
330 | RREG32(R_0007C0_CP_STAT)); |
337 | RREG32(R_0007C0_CP_STAT)); |
331 | } |
338 | } |
332 | /* check if cards are posted or not */ |
339 | /* check if cards are posted or not */ |
333 | if (radeon_boot_test_post_card(rdev) == false) |
340 | if (radeon_boot_test_post_card(rdev) == false) |
334 | return -EINVAL; |
341 | return -EINVAL; |
335 | 342 | ||
336 | /* Initialize clocks */ |
343 | /* Initialize clocks */ |
337 | radeon_get_clock_info(rdev->ddev); |
344 | radeon_get_clock_info(rdev->ddev); |
338 | /* initialize AGP */ |
345 | /* initialize AGP */ |
339 | if (rdev->flags & RADEON_IS_AGP) { |
346 | if (rdev->flags & RADEON_IS_AGP) { |
340 | r = radeon_agp_init(rdev); |
347 | r = radeon_agp_init(rdev); |
341 | if (r) { |
348 | if (r) { |
342 | radeon_agp_disable(rdev); |
349 | radeon_agp_disable(rdev); |
343 | } |
350 | } |
344 | } |
351 | } |
345 | /* initialize memory controller */ |
352 | /* initialize memory controller */ |
346 | r300_mc_init(rdev); |
353 | r300_mc_init(rdev); |
347 | r420_debugfs(rdev); |
354 | r420_debugfs(rdev); |
348 | /* Fence driver */ |
355 | /* Fence driver */ |
349 | r = radeon_fence_driver_init(rdev); |
356 | r = radeon_fence_driver_init(rdev); |
350 | if (r) { |
357 | if (r) { |
351 | return r; |
358 | return r; |
352 | } |
359 | } |
353 | /* Memory manager */ |
360 | /* Memory manager */ |
354 | r = radeon_bo_init(rdev); |
361 | r = radeon_bo_init(rdev); |
355 | if (r) { |
362 | if (r) { |
356 | return r; |
363 | return r; |
357 | } |
364 | } |
358 | if (rdev->family == CHIP_R420) |
365 | if (rdev->family == CHIP_R420) |
359 | r100_enable_bm(rdev); |
366 | r100_enable_bm(rdev); |
360 | 367 | ||
361 | if (rdev->flags & RADEON_IS_PCIE) { |
368 | if (rdev->flags & RADEON_IS_PCIE) { |
362 | r = rv370_pcie_gart_init(rdev); |
369 | r = rv370_pcie_gart_init(rdev); |
363 | if (r) |
370 | if (r) |
364 | return r; |
371 | return r; |
365 | } |
372 | } |
366 | if (rdev->flags & RADEON_IS_PCI) { |
373 | if (rdev->flags & RADEON_IS_PCI) { |
367 | r = r100_pci_gart_init(rdev); |
374 | r = r100_pci_gart_init(rdev); |
368 | if (r) |
375 | if (r) |
369 | return r; |
376 | return r; |
370 | } |
377 | } |
371 | r420_set_reg_safe(rdev); |
378 | r420_set_reg_safe(rdev); |
- | 379 | ||
- | 380 | /* Initialize power management */ |
|
- | 381 | radeon_pm_init(rdev); |
|
372 | 382 | ||
373 | rdev->accel_working = true; |
383 | rdev->accel_working = true; |
374 | r = r420_startup(rdev); |
384 | r = r420_startup(rdev); |
375 | if (r) { |
385 | if (r) { |
376 | /* Somethings want wront with the accel init stop accel */ |
386 | /* Somethings want wront with the accel init stop accel */ |
377 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
387 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
378 | if (rdev->flags & RADEON_IS_PCIE) |
388 | if (rdev->flags & RADEON_IS_PCIE) |
379 | rv370_pcie_gart_fini(rdev); |
389 | rv370_pcie_gart_fini(rdev); |
380 | if (rdev->flags & RADEON_IS_PCI) |
390 | if (rdev->flags & RADEON_IS_PCI) |
381 | r100_pci_gart_fini(rdev); |
391 | r100_pci_gart_fini(rdev); |
382 | rdev->accel_working = false; |
392 | rdev->accel_working = false; |
383 | } |
393 | } |
384 | return 0; |
394 | return 0; |
385 | } |
395 | } |
386 | 396 | ||
387 | /* |
397 | /* |
388 | * Debugfs info |
398 | * Debugfs info |
389 | */ |
399 | */ |
390 | #if defined(CONFIG_DEBUG_FS) |
400 | #if defined(CONFIG_DEBUG_FS) |
391 | static int r420_debugfs_pipes_info(struct seq_file *m, void *data) |
401 | static int r420_debugfs_pipes_info(struct seq_file *m, void *data) |
392 | { |
402 | { |
393 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
403 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
394 | struct drm_device *dev = node->minor->dev; |
404 | struct drm_device *dev = node->minor->dev; |
395 | struct radeon_device *rdev = dev->dev_private; |
405 | struct radeon_device *rdev = dev->dev_private; |
396 | uint32_t tmp; |
406 | uint32_t tmp; |
397 | 407 | ||
398 | tmp = RREG32(R400_GB_PIPE_SELECT); |
408 | tmp = RREG32(R400_GB_PIPE_SELECT); |
399 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
409 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
400 | tmp = RREG32(R300_GB_TILE_CONFIG); |
410 | tmp = RREG32(R300_GB_TILE_CONFIG); |
401 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
411 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
402 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
412 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
403 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
413 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
404 | return 0; |
414 | return 0; |
405 | } |
415 | } |
406 | 416 | ||
407 | static struct drm_info_list r420_pipes_info_list[] = { |
417 | static struct drm_info_list r420_pipes_info_list[] = { |
408 | {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, |
418 | {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, |
409 | }; |
419 | }; |
410 | #endif |
420 | #endif |
411 | 421 | ||
412 | int r420_debugfs_pipes_info_init(struct radeon_device *rdev) |
422 | int r420_debugfs_pipes_info_init(struct radeon_device *rdev) |
413 | { |
423 | { |
414 | #if defined(CONFIG_DEBUG_FS) |
424 | #if defined(CONFIG_DEBUG_FS) |
415 | return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); |
425 | return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); |
416 | #else |
426 | #else |
417 | return 0; |
427 | return 0; |
418 | #endif |
428 | #endif |
419 | }><>><>><>><>><>><>><> |
429 | }><>><>><>><>><>><>><> |