WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_ringbuffer.h


#ifndef _INTEL_RINGBUFFER_H_
#define _INTEL_RINGBUFFER_H_
 
/*
 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
 *
 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
 * cacheline, the Head Pointer must not be greater than the Tail
 * Pointer."
 */
#define I915_RING_FREE_SPACE 64
 
struct  intel_hw_status_page {
	u32		*page_addr;
	unsigned int	gfx_addr;
	struct		drm_i915_gem_object *obj;
};
 
#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
 
#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
 
#define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
 
#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
 
#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
 
#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
 
struct  intel_ring_buffer {
	const char	*name;
	enum intel_ring_id {
		RCS = 0x0,
		VCS,
		BCS,
	} id;
#define I915_NUM_RINGS 3
	u32		mmio_base;
	void		__iomem *virtual_start;
	struct		drm_device *dev;
	struct		drm_i915_gem_object *obj;
 
	u32		head;
	u32		tail;
	int		space;
	int		size;
	int		effective_size;
	struct intel_hw_status_page status_page;
 
	/** We track the position of the requests in the ring buffer, and
	 * when each is retired we increment last_retired_head as the GPU
	 * must have finished processing the request and so we know we
	 * can advance the ringbuffer up to that position.
	 *
	 * last_retired_head is set to -1 after the value is consumed so
	 * we can detect new retirements.
	 */
	u32		last_retired_head;
 
	u32		irq_refcount;		/* protected by dev_priv->irq_lock */
	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
	u32		trace_irq_seqno;
	u32		sync_seqno[I915_NUM_RINGS-1];
	bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
	void		(*irq_put)(struct intel_ring_buffer *ring);
 
	int		(*init)(struct intel_ring_buffer *ring);
 
	void		(*write_tail)(struct intel_ring_buffer *ring,
				      u32 value);
	int __must_check (*flush)(struct intel_ring_buffer *ring,
				  u32	invalidate_domains,
				  u32	flush_domains);
	int		(*add_request)(struct intel_ring_buffer *ring);
 
	/* Some chipsets are not quite as coherent as advertised and need
	 * an expensive kick to force a true read of the up-to-date seqno.
	 * However, the up-to-date seqno is not always required and the last
	 * seen value is good enough. Note that the seqno will always be
	 * monotonic, even if not coherent.
	 */
	u32		(*get_seqno)(struct intel_ring_buffer *ring,
				     bool lazy_coherency);
	int		(*dispatch_execbuffer)(struct intel_ring_buffer *ring,
					       u32 offset, u32 length,
					       unsigned flags);
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
	void		(*cleanup)(struct intel_ring_buffer *ring);
	int		(*sync_to)(struct intel_ring_buffer *ring,
				   struct intel_ring_buffer *to,
				   u32 seqno);
 
	u32		semaphore_register[3]; /*our mbox written by others */
	u32		signal_mbox[2]; /* mboxes this ring signals to */
	/**
	 * List of objects currently involved in rendering from the
	 * ringbuffer.
	 *
	 * Includes buffers having the contents of their GPU caches
	 * flushed, not necessarily primitives.  last_rendering_seqno
	 * represents when the rendering involved will be completed.
	 *
	 * A reference is held on the buffer while on this list.
	 */
	struct list_head active_list;
 
	/**
	 * List of breadcrumbs associated with GPU requests currently
	 * outstanding.
	 */
	struct list_head request_list;
 
	/**
	 * Do we have some not yet emitted requests outstanding?
	 */
	u32 outstanding_lazy_request;
	bool gpu_caches_dirty;
 
	wait_queue_head_t irq_queue;
 
	/**
	 * Do an explicit TLB flush before MI_SET_CONTEXT
	 */
	bool itlb_before_ctx_switch;
	struct i915_hw_context *default_context;
	struct drm_i915_gem_object *last_context_obj;
 
	void *private;
};
 
static inline bool
intel_ring_initialized(struct intel_ring_buffer *ring)
{
	return ring->obj != NULL;
}
 
static inline unsigned
intel_ring_flag(struct intel_ring_buffer *ring)
{
	return 1 << ring->id;
}
 
static inline u32
intel_ring_sync_index(struct intel_ring_buffer *ring,
		      struct intel_ring_buffer *other)
{
	int idx;
 
	/*
	 * cs -> 0 = vcs, 1 = bcs
	 * vcs -> 0 = bcs, 1 = cs,
	 * bcs -> 0 = cs, 1 = vcs.
	 */
 
	idx = (other - ring) - 1;
	if (idx < 0)
		idx += I915_NUM_RINGS;
 
	return idx;
}
 
static inline u32
intel_read_status_page(struct intel_ring_buffer *ring,
		       int reg)
{
	/* Ensure that the compiler doesn't optimize away the load. */
	barrier();
	return ring->status_page.page_addr[reg];
}
 
/**
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 0x04: ring 0 head pointer
 * 0x05: ring 1 head pointer (915-class)
 * 0x06: ring 2 head pointer (915-class)
 * 0x10-0x1b: Context status DWords (GM45)
 * 0x1f: Last written status offset. (GM45)
 *
 * The area from dword 0x20 to 0x3ff is available for driver usage.
 */
#define I915_GEM_HWS_INDEX		0x20
#define I915_GEM_HWS_SCRATCH_INDEX	0x30
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 
 
 
 
 
 
 
 
int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
static inline void intel_ring_emit(struct intel_ring_buffer *ring,
				   u32 data)
{
	iowrite32(data, ring->virtual_start + ring->tail);
	ring->tail += 4;
}
 
void intel_ring_advance(struct intel_ring_buffer *ring);
int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
 
 
int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
 
int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev);
 
u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
 
static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
{
	return ring->tail;
}
 
static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
{
	BUG_ON(ring->outstanding_lazy_request == 0);
	return ring->outstanding_lazy_request;
}
 
static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
{
	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
		ring->trace_irq_seqno = seqno;
}
 
/* DRI warts */
int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 
#endif /* _INTEL_RINGBUFFER_H_ */

Rev 3031	Rev 3243
1	#ifndef _INTEL_RINGBUFFER_H_	1	#ifndef _INTEL_RINGBUFFER_H_
2	#define _INTEL_RINGBUFFER_H_	2	#define _INTEL_RINGBUFFER_H_
-		3
-		4	/*
-		5	* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
-		6	* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
-		7	* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
-		8	*
-		9	* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
-		10	* cacheline, the Head Pointer must not be greater than the Tail
-		11	* Pointer."
-		12	*/
-		13	#define I915_RING_FREE_SPACE 64
3		14
4	struct intel_hw_status_page {	15	struct intel_hw_status_page {
5	u32 *page_addr;	16	u32 *page_addr;
6	unsigned int gfx_addr;	17	unsigned int gfx_addr;
7	struct drm_i915_gem_object *obj;	18	struct drm_i915_gem_object *obj;
8	};	19	};
9		20
10	#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))	21	#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
11	#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)	22	#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
12		23
13	#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))	24	#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
14	#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)	25	#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
15		26
16	#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))	27	#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
17	#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)	28	#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
18		29
19	#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))	30	#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
20	#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)	31	#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
21		32
22	#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))	33	#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
23	#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)	34	#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
24		35
25	#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))	36	#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
26	#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))	37	#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
27	#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))	38	#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
28		39
29	struct intel_ring_buffer {	40	struct intel_ring_buffer {
30	const char *name;	41	const char *name;
31	enum intel_ring_id {	42	enum intel_ring_id {
32	RCS = 0x0,	43	RCS = 0x0,
33	VCS,	44	VCS,
34	BCS,	45	BCS,
35	} id;	46	} id;
36	#define I915_NUM_RINGS 3	47	#define I915_NUM_RINGS 3
37	u32 mmio_base;	48	u32 mmio_base;
38	void __iomem *virtual_start;	49	void __iomem *virtual_start;
39	struct drm_device *dev;	50	struct drm_device *dev;
40	struct drm_i915_gem_object *obj;	51	struct drm_i915_gem_object *obj;
41		52
42	u32 head;	53	u32 head;
43	u32 tail;	54	u32 tail;
44	int space;	55	int space;
45	int size;	56	int size;
46	int effective_size;	57	int effective_size;
47	struct intel_hw_status_page status_page;	58	struct intel_hw_status_page status_page;
48		59
49	/** We track the position of the requests in the ring buffer, and	60	/** We track the position of the requests in the ring buffer, and
50	* when each is retired we increment last_retired_head as the GPU	61	* when each is retired we increment last_retired_head as the GPU
51	* must have finished processing the request and so we know we	62	* must have finished processing the request and so we know we
52	* can advance the ringbuffer up to that position.	63	* can advance the ringbuffer up to that position.
53	*	64	*
54	* last_retired_head is set to -1 after the value is consumed so	65	* last_retired_head is set to -1 after the value is consumed so
55	* we can detect new retirements.	66	* we can detect new retirements.
56	*/	67	*/
57	u32 last_retired_head;	68	u32 last_retired_head;
58		69
59	u32 irq_refcount; /* protected by dev_priv->irq_lock */	70	u32 irq_refcount; /* protected by dev_priv->irq_lock */
60	u32 irq_enable_mask; /* bitmask to enable ring interrupt */	71	u32 irq_enable_mask; /* bitmask to enable ring interrupt */
61	u32 trace_irq_seqno;	72	u32 trace_irq_seqno;
62	u32 sync_seqno[I915_NUM_RINGS-1];	73	u32 sync_seqno[I915_NUM_RINGS-1];
63	bool __must_check (irq_get)(struct intel_ring_buffer ring);	74	bool __must_check (irq_get)(struct intel_ring_buffer ring);
64	void (irq_put)(struct intel_ring_buffer ring);	75	void (irq_put)(struct intel_ring_buffer ring);
65		76
66	int (init)(struct intel_ring_buffer ring);	77	int (init)(struct intel_ring_buffer ring);
67		78
68	void (write_tail)(struct intel_ring_buffer ring,	79	void (write_tail)(struct intel_ring_buffer ring,
69	u32 value);	80	u32 value);
70	int __must_check (flush)(struct intel_ring_buffer ring,	81	int __must_check (flush)(struct intel_ring_buffer ring,
71	u32 invalidate_domains,	82	u32 invalidate_domains,
72	u32 flush_domains);	83	u32 flush_domains);
73	int (add_request)(struct intel_ring_buffer ring,	84	int (add_request)(struct intel_ring_buffer ring);
74	u32 *seqno);	-
75	/* Some chipsets are not quite as coherent as advertised and need	85	/* Some chipsets are not quite as coherent as advertised and need
76	* an expensive kick to force a true read of the up-to-date seqno.	86	* an expensive kick to force a true read of the up-to-date seqno.
77	* However, the up-to-date seqno is not always required and the last	87	* However, the up-to-date seqno is not always required and the last
78	* seen value is good enough. Note that the seqno will always be	88	* seen value is good enough. Note that the seqno will always be
79	* monotonic, even if not coherent.	89	* monotonic, even if not coherent.
80	*/	90	*/
81	u32 (get_seqno)(struct intel_ring_buffer ring,	91	u32 (get_seqno)(struct intel_ring_buffer ring,
82	bool lazy_coherency);	92	bool lazy_coherency);
83	int (dispatch_execbuffer)(struct intel_ring_buffer ring,	93	int (dispatch_execbuffer)(struct intel_ring_buffer ring,
84	u32 offset, u32 length);	94	u32 offset, u32 length,
-		95	unsigned flags);
-		96	#define I915_DISPATCH_SECURE 0x1
-		97	#define I915_DISPATCH_PINNED 0x2
85	void (cleanup)(struct intel_ring_buffer ring);	98	void (cleanup)(struct intel_ring_buffer ring);
86	int (sync_to)(struct intel_ring_buffer ring,	99	int (sync_to)(struct intel_ring_buffer ring,
87	struct intel_ring_buffer *to,	100	struct intel_ring_buffer *to,
88	u32 seqno);	101	u32 seqno);
89		102
90	u32 semaphore_register[3]; /our mbox written by others /	103	u32 semaphore_register[3]; /our mbox written by others /
91	u32 signal_mbox[2]; /* mboxes this ring signals to */	104	u32 signal_mbox[2]; /* mboxes this ring signals to */
92	/**	105	/**
93	* List of objects currently involved in rendering from the	106	* List of objects currently involved in rendering from the
94	* ringbuffer.	107	* ringbuffer.
95	*	108	*
96	* Includes buffers having the contents of their GPU caches	109	* Includes buffers having the contents of their GPU caches
97	* flushed, not necessarily primitives. last_rendering_seqno	110	* flushed, not necessarily primitives. last_rendering_seqno
98	* represents when the rendering involved will be completed.	111	* represents when the rendering involved will be completed.
99	*	112	*
100	* A reference is held on the buffer while on this list.	113	* A reference is held on the buffer while on this list.
101	*/	114	*/
102	struct list_head active_list;	115	struct list_head active_list;
103		116
104	/**	117	/**
105	* List of breadcrumbs associated with GPU requests currently	118	* List of breadcrumbs associated with GPU requests currently
106	* outstanding.	119	* outstanding.
107	*/	120	*/
108	struct list_head request_list;	121	struct list_head request_list;
109		122
110	/**	123	/**
111	* Do we have some not yet emitted requests outstanding?	124	* Do we have some not yet emitted requests outstanding?
112	*/	125	*/
113	u32 outstanding_lazy_request;	126	u32 outstanding_lazy_request;
114	bool gpu_caches_dirty;	127	bool gpu_caches_dirty;
115		128
116	wait_queue_head_t irq_queue;	129	wait_queue_head_t irq_queue;
117		130
118	/**	131	/**
119	* Do an explicit TLB flush before MI_SET_CONTEXT	132	* Do an explicit TLB flush before MI_SET_CONTEXT
120	*/	133	*/
121	bool itlb_before_ctx_switch;	134	bool itlb_before_ctx_switch;
122	struct i915_hw_context *default_context;	135	struct i915_hw_context *default_context;
123	struct drm_i915_gem_object *last_context_obj;	136	struct drm_i915_gem_object *last_context_obj;
124		137
125	void *private;	138	void *private;
126	};	139	};
127		140
128	static inline bool	141	static inline bool
129	intel_ring_initialized(struct intel_ring_buffer *ring)	142	intel_ring_initialized(struct intel_ring_buffer *ring)
130	{	143	{
131	return ring->obj != NULL;	144	return ring->obj != NULL;
132	}	145	}
133		146
134	static inline unsigned	147	static inline unsigned
135	intel_ring_flag(struct intel_ring_buffer *ring)	148	intel_ring_flag(struct intel_ring_buffer *ring)
136	{	149	{
137	return 1 << ring->id;	150	return 1 << ring->id;
138	}	151	}
139		152
140	static inline u32	153	static inline u32
141	intel_ring_sync_index(struct intel_ring_buffer *ring,	154	intel_ring_sync_index(struct intel_ring_buffer *ring,
142	struct intel_ring_buffer *other)	155	struct intel_ring_buffer *other)
143	{	156	{
144	int idx;	157	int idx;
145		158
146	/*	159	/*
147	* cs -> 0 = vcs, 1 = bcs	160	* cs -> 0 = vcs, 1 = bcs
148	* vcs -> 0 = bcs, 1 = cs,	161	* vcs -> 0 = bcs, 1 = cs,
149	* bcs -> 0 = cs, 1 = vcs.	162	* bcs -> 0 = cs, 1 = vcs.
150	*/	163	*/
151		164
152	idx = (other - ring) - 1;	165	idx = (other - ring) - 1;
153	if (idx < 0)	166	if (idx < 0)
154	idx += I915_NUM_RINGS;	167	idx += I915_NUM_RINGS;
155		168
156	return idx;	169	return idx;
157	}	170	}
158		171
159	static inline u32	172	static inline u32
160	intel_read_status_page(struct intel_ring_buffer *ring,	173	intel_read_status_page(struct intel_ring_buffer *ring,
161	int reg)	174	int reg)
162	{	175	{
163	/* Ensure that the compiler doesn't optimize away the load. */	176	/* Ensure that the compiler doesn't optimize away the load. */
164	barrier();	177	barrier();
165	return ring->status_page.page_addr[reg];	178	return ring->status_page.page_addr[reg];
166	}	179	}
167		180
168	/**	181	/**
169	* Reads a dword out of the status page, which is written to from the command	182	* Reads a dword out of the status page, which is written to from the command
170	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or	183	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
171	* MI_STORE_DATA_IMM.	184	* MI_STORE_DATA_IMM.
172	*	185	*
173	* The following dwords have a reserved meaning:	186	* The following dwords have a reserved meaning:
174	* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.	187	* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
175	* 0x04: ring 0 head pointer	188	* 0x04: ring 0 head pointer
176	* 0x05: ring 1 head pointer (915-class)	189	* 0x05: ring 1 head pointer (915-class)
177	* 0x06: ring 2 head pointer (915-class)	190	* 0x06: ring 2 head pointer (915-class)
178	* 0x10-0x1b: Context status DWords (GM45)	191	* 0x10-0x1b: Context status DWords (GM45)
179	* 0x1f: Last written status offset. (GM45)	192	* 0x1f: Last written status offset. (GM45)
180	*	193	*
181	* The area from dword 0x20 to 0x3ff is available for driver usage.	194	* The area from dword 0x20 to 0x3ff is available for driver usage.
182	*/	195	*/
183	#define I915_GEM_HWS_INDEX 0x20	196	#define I915_GEM_HWS_INDEX 0x20
-		197	#define I915_GEM_HWS_SCRATCH_INDEX 0x30
-		198	#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
184		199
185	void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);	200	void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
186		-
187	int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);	-
188	static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring)	-
189	{	-
190	return intel_wait_ring_buffer(ring, ring->size - 8);	-
191	}	-
192		201
193	int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);	-
194		202	int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
195	static inline void intel_ring_emit(struct intel_ring_buffer *ring,	203	static inline void intel_ring_emit(struct intel_ring_buffer *ring,
196	u32 data)	204	u32 data)
197	{	205	{
198	iowrite32(data, ring->virtual_start + ring->tail);	206	iowrite32(data, ring->virtual_start + ring->tail);
199	ring->tail += 4;	207	ring->tail += 4;
200	}	208	}
201		-
202	void intel_ring_advance(struct intel_ring_buffer *ring);	209	void intel_ring_advance(struct intel_ring_buffer *ring);
-		210	int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
203		-
204	u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);	211
205	int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);	212	int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
206	int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);	213	int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
207		214
208	int intel_init_render_ring_buffer(struct drm_device *dev);	215	int intel_init_render_ring_buffer(struct drm_device *dev);
209	int intel_init_bsd_ring_buffer(struct drm_device *dev);	216	int intel_init_bsd_ring_buffer(struct drm_device *dev);
210	int intel_init_blt_ring_buffer(struct drm_device *dev);	217	int intel_init_blt_ring_buffer(struct drm_device *dev);
211		218
212	u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);	219	u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
213	void intel_ring_setup_status_page(struct intel_ring_buffer *ring);	220	void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
214		221
215	static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)	222	static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
216	{	223	{
217	return ring->tail;	224	return ring->tail;
218	}	225	}
-		226
-		227	static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
-		228	{
-		229	BUG_ON(ring->outstanding_lazy_request == 0);
-		230	return ring->outstanding_lazy_request;
-		231	}
219		232
220	static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)	233	static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
221	{	234	{
222	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))	235	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
223	ring->trace_irq_seqno = seqno;	236	ring->trace_irq_seqno = seqno;
224	}	237	}
225		238
226	/* DRI warts */	239	/* DRI warts */
227	int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);	240	int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
228		241
229	#endif /* _INTEL_RINGBUFFER_H_ */	242	#endif /* _INTEL_RINGBUFFER_H_ */

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_ringbuffer.h – Rev 3031 → 3243