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1 | /* |
1 | /* |
2 | * Copyright © 2008 Intel Corporation |
2 | * Copyright © 2008 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Keith Packard |
24 | * Keith Packard |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | #include |
33 | #include |
34 | #include |
34 | #include |
35 | #include "intel_drv.h" |
35 | #include "intel_drv.h" |
36 | #include |
36 | #include |
37 | #include "i915_drv.h" |
37 | #include "i915_drv.h" |
38 | 38 | ||
39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
40 | 40 | ||
41 | struct dp_link_dpll { |
41 | struct dp_link_dpll { |
42 | int link_bw; |
42 | int link_bw; |
43 | struct dpll dpll; |
43 | struct dpll dpll; |
44 | }; |
44 | }; |
45 | 45 | ||
46 | static const struct dp_link_dpll gen4_dpll[] = { |
46 | static const struct dp_link_dpll gen4_dpll[] = { |
47 | { DP_LINK_BW_1_62, |
47 | { DP_LINK_BW_1_62, |
48 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
48 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
49 | { DP_LINK_BW_2_7, |
49 | { DP_LINK_BW_2_7, |
50 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
50 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
51 | }; |
51 | }; |
52 | 52 | ||
53 | static const struct dp_link_dpll pch_dpll[] = { |
53 | static const struct dp_link_dpll pch_dpll[] = { |
54 | { DP_LINK_BW_1_62, |
54 | { DP_LINK_BW_1_62, |
55 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
55 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
56 | { DP_LINK_BW_2_7, |
56 | { DP_LINK_BW_2_7, |
57 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
57 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
58 | }; |
58 | }; |
59 | 59 | ||
60 | static const struct dp_link_dpll vlv_dpll[] = { |
60 | static const struct dp_link_dpll vlv_dpll[] = { |
61 | { DP_LINK_BW_1_62, |
61 | { DP_LINK_BW_1_62, |
62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
63 | { DP_LINK_BW_2_7, |
63 | { DP_LINK_BW_2_7, |
64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
65 | }; |
65 | }; |
- | 66 | ||
- | 67 | /* |
|
- | 68 | * CHV supports eDP 1.4 that have more link rates. |
|
- | 69 | * Below only provides the fixed rate but exclude variable rate. |
|
- | 70 | */ |
|
- | 71 | static const struct dp_link_dpll chv_dpll[] = { |
|
- | 72 | /* |
|
- | 73 | * CHV requires to program fractional division for m2. |
|
- | 74 | * m2 is stored in fixed point format using formula below |
|
- | 75 | * (m2_int << 22) | m2_fraction |
|
- | 76 | */ |
|
- | 77 | { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ |
|
- | 78 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
|
- | 79 | { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ |
|
- | 80 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
|
- | 81 | { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ |
|
- | 82 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
|
- | 83 | }; |
|
66 | 84 | ||
67 | /** |
85 | /** |
68 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
86 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
69 | * @intel_dp: DP struct |
87 | * @intel_dp: DP struct |
70 | * |
88 | * |
71 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
89 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
72 | * will return true, and false otherwise. |
90 | * will return true, and false otherwise. |
73 | */ |
91 | */ |
74 | static bool is_edp(struct intel_dp *intel_dp) |
92 | static bool is_edp(struct intel_dp *intel_dp) |
75 | { |
93 | { |
76 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
94 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
77 | 95 | ||
78 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
96 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
79 | } |
97 | } |
80 | 98 | ||
81 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
99 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
82 | { |
100 | { |
83 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
101 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
84 | 102 | ||
85 | return intel_dig_port->base.base.dev; |
103 | return intel_dig_port->base.base.dev; |
86 | } |
104 | } |
87 | 105 | ||
88 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
106 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
89 | { |
107 | { |
90 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
108 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
91 | } |
109 | } |
92 | 110 | ||
93 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
111 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
- | 112 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); |
|
- | 113 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
|
94 | 114 | ||
95 | static int |
115 | int |
96 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
116 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
97 | { |
117 | { |
98 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
118 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
- | 119 | struct drm_device *dev = intel_dp->attached_connector->base.dev; |
|
99 | 120 | ||
100 | switch (max_link_bw) { |
121 | switch (max_link_bw) { |
101 | case DP_LINK_BW_1_62: |
122 | case DP_LINK_BW_1_62: |
102 | case DP_LINK_BW_2_7: |
123 | case DP_LINK_BW_2_7: |
103 | break; |
124 | break; |
104 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
125 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
- | 126 | if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || |
|
- | 127 | INTEL_INFO(dev)->gen >= 8) && |
|
- | 128 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) |
|
- | 129 | max_link_bw = DP_LINK_BW_5_4; |
|
- | 130 | else |
|
105 | max_link_bw = DP_LINK_BW_2_7; |
131 | max_link_bw = DP_LINK_BW_2_7; |
106 | break; |
132 | break; |
107 | default: |
133 | default: |
108 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
134 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
109 | max_link_bw); |
135 | max_link_bw); |
110 | max_link_bw = DP_LINK_BW_1_62; |
136 | max_link_bw = DP_LINK_BW_1_62; |
111 | break; |
137 | break; |
112 | } |
138 | } |
113 | return max_link_bw; |
139 | return max_link_bw; |
114 | } |
140 | } |
- | 141 | ||
- | 142 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
|
- | 143 | { |
|
- | 144 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 145 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 146 | u8 source_max, sink_max; |
|
- | 147 | ||
- | 148 | source_max = 4; |
|
- | 149 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && |
|
- | 150 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) |
|
- | 151 | source_max = 2; |
|
- | 152 | ||
- | 153 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
|
- | 154 | ||
- | 155 | return min(source_max, sink_max); |
|
- | 156 | } |
|
115 | 157 | ||
116 | /* |
158 | /* |
117 | * The units on the numbers in the next two are... bizarre. Examples will |
159 | * The units on the numbers in the next two are... bizarre. Examples will |
118 | * make it clearer; this one parallels an example in the eDP spec. |
160 | * make it clearer; this one parallels an example in the eDP spec. |
119 | * |
161 | * |
120 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
162 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
121 | * |
163 | * |
122 | * 270000 * 1 * 8 / 10 == 216000 |
164 | * 270000 * 1 * 8 / 10 == 216000 |
123 | * |
165 | * |
124 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
166 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
125 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
167 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
126 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
168 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
127 | * 119000. At 18bpp that's 2142000 kilobits per second. |
169 | * 119000. At 18bpp that's 2142000 kilobits per second. |
128 | * |
170 | * |
129 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
171 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
130 | * get the result in decakilobits instead of kilobits. |
172 | * get the result in decakilobits instead of kilobits. |
131 | */ |
173 | */ |
132 | 174 | ||
133 | static int |
175 | static int |
134 | intel_dp_link_required(int pixel_clock, int bpp) |
176 | intel_dp_link_required(int pixel_clock, int bpp) |
135 | { |
177 | { |
136 | return (pixel_clock * bpp + 9) / 10; |
178 | return (pixel_clock * bpp + 9) / 10; |
137 | } |
179 | } |
138 | 180 | ||
139 | static int |
181 | static int |
140 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
182 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
141 | { |
183 | { |
142 | return (max_link_clock * max_lanes * 8) / 10; |
184 | return (max_link_clock * max_lanes * 8) / 10; |
143 | } |
185 | } |
144 | 186 | ||
145 | static enum drm_mode_status |
187 | static enum drm_mode_status |
146 | intel_dp_mode_valid(struct drm_connector *connector, |
188 | intel_dp_mode_valid(struct drm_connector *connector, |
147 | struct drm_display_mode *mode) |
189 | struct drm_display_mode *mode) |
148 | { |
190 | { |
149 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
191 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
150 | struct intel_connector *intel_connector = to_intel_connector(connector); |
192 | struct intel_connector *intel_connector = to_intel_connector(connector); |
151 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
193 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
152 | int target_clock = mode->clock; |
194 | int target_clock = mode->clock; |
153 | int max_rate, mode_rate, max_lanes, max_link_clock; |
195 | int max_rate, mode_rate, max_lanes, max_link_clock; |
154 | 196 | ||
155 | if (is_edp(intel_dp) && fixed_mode) { |
197 | if (is_edp(intel_dp) && fixed_mode) { |
156 | if (mode->hdisplay > fixed_mode->hdisplay) |
198 | if (mode->hdisplay > fixed_mode->hdisplay) |
157 | return MODE_PANEL; |
199 | return MODE_PANEL; |
158 | 200 | ||
159 | if (mode->vdisplay > fixed_mode->vdisplay) |
201 | if (mode->vdisplay > fixed_mode->vdisplay) |
160 | return MODE_PANEL; |
202 | return MODE_PANEL; |
161 | 203 | ||
162 | target_clock = fixed_mode->clock; |
204 | target_clock = fixed_mode->clock; |
163 | } |
205 | } |
164 | 206 | ||
165 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
207 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
166 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); |
208 | max_lanes = intel_dp_max_lane_count(intel_dp); |
167 | 209 | ||
168 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
210 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
169 | mode_rate = intel_dp_link_required(target_clock, 18); |
211 | mode_rate = intel_dp_link_required(target_clock, 18); |
170 | 212 | ||
171 | if (mode_rate > max_rate) |
213 | if (mode_rate > max_rate) |
172 | return MODE_CLOCK_HIGH; |
214 | return MODE_CLOCK_HIGH; |
173 | 215 | ||
174 | if (mode->clock < 10000) |
216 | if (mode->clock < 10000) |
175 | return MODE_CLOCK_LOW; |
217 | return MODE_CLOCK_LOW; |
176 | 218 | ||
177 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
219 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
178 | return MODE_H_ILLEGAL; |
220 | return MODE_H_ILLEGAL; |
179 | 221 | ||
180 | return MODE_OK; |
222 | return MODE_OK; |
181 | } |
223 | } |
182 | 224 | ||
183 | static uint32_t |
225 | static uint32_t |
184 | pack_aux(uint8_t *src, int src_bytes) |
226 | pack_aux(uint8_t *src, int src_bytes) |
185 | { |
227 | { |
186 | int i; |
228 | int i; |
187 | uint32_t v = 0; |
229 | uint32_t v = 0; |
188 | 230 | ||
189 | if (src_bytes > 4) |
231 | if (src_bytes > 4) |
190 | src_bytes = 4; |
232 | src_bytes = 4; |
191 | for (i = 0; i < src_bytes; i++) |
233 | for (i = 0; i < src_bytes; i++) |
192 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
234 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
193 | return v; |
235 | return v; |
194 | } |
236 | } |
195 | 237 | ||
196 | static void |
238 | static void |
197 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
239 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
198 | { |
240 | { |
199 | int i; |
241 | int i; |
200 | if (dst_bytes > 4) |
242 | if (dst_bytes > 4) |
201 | dst_bytes = 4; |
243 | dst_bytes = 4; |
202 | for (i = 0; i < dst_bytes; i++) |
244 | for (i = 0; i < dst_bytes; i++) |
203 | dst[i] = src >> ((3-i) * 8); |
245 | dst[i] = src >> ((3-i) * 8); |
204 | } |
246 | } |
205 | 247 | ||
206 | /* hrawclock is 1/4 the FSB frequency */ |
248 | /* hrawclock is 1/4 the FSB frequency */ |
207 | static int |
249 | static int |
208 | intel_hrawclk(struct drm_device *dev) |
250 | intel_hrawclk(struct drm_device *dev) |
209 | { |
251 | { |
210 | struct drm_i915_private *dev_priv = dev->dev_private; |
252 | struct drm_i915_private *dev_priv = dev->dev_private; |
211 | uint32_t clkcfg; |
253 | uint32_t clkcfg; |
212 | 254 | ||
213 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
255 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
214 | if (IS_VALLEYVIEW(dev)) |
256 | if (IS_VALLEYVIEW(dev)) |
215 | return 200; |
257 | return 200; |
216 | 258 | ||
217 | clkcfg = I915_READ(CLKCFG); |
259 | clkcfg = I915_READ(CLKCFG); |
218 | switch (clkcfg & CLKCFG_FSB_MASK) { |
260 | switch (clkcfg & CLKCFG_FSB_MASK) { |
219 | case CLKCFG_FSB_400: |
261 | case CLKCFG_FSB_400: |
220 | return 100; |
262 | return 100; |
221 | case CLKCFG_FSB_533: |
263 | case CLKCFG_FSB_533: |
222 | return 133; |
264 | return 133; |
223 | case CLKCFG_FSB_667: |
265 | case CLKCFG_FSB_667: |
224 | return 166; |
266 | return 166; |
225 | case CLKCFG_FSB_800: |
267 | case CLKCFG_FSB_800: |
226 | return 200; |
268 | return 200; |
227 | case CLKCFG_FSB_1067: |
269 | case CLKCFG_FSB_1067: |
228 | return 266; |
270 | return 266; |
229 | case CLKCFG_FSB_1333: |
271 | case CLKCFG_FSB_1333: |
230 | return 333; |
272 | return 333; |
231 | /* these two are just a guess; one of them might be right */ |
273 | /* these two are just a guess; one of them might be right */ |
232 | case CLKCFG_FSB_1600: |
274 | case CLKCFG_FSB_1600: |
233 | case CLKCFG_FSB_1600_ALT: |
275 | case CLKCFG_FSB_1600_ALT: |
234 | return 400; |
276 | return 400; |
235 | default: |
277 | default: |
236 | return 133; |
278 | return 133; |
237 | } |
279 | } |
238 | } |
280 | } |
239 | 281 | ||
240 | static void |
282 | static void |
241 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
283 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
242 | struct intel_dp *intel_dp, |
284 | struct intel_dp *intel_dp, |
243 | struct edp_power_seq *out); |
285 | struct edp_power_seq *out); |
244 | static void |
286 | static void |
245 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
287 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
246 | struct intel_dp *intel_dp, |
288 | struct intel_dp *intel_dp, |
247 | struct edp_power_seq *out); |
289 | struct edp_power_seq *out); |
248 | 290 | ||
249 | static enum pipe |
291 | static enum pipe |
250 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
292 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
251 | { |
293 | { |
252 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
294 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
253 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
295 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
254 | struct drm_device *dev = intel_dig_port->base.base.dev; |
296 | struct drm_device *dev = intel_dig_port->base.base.dev; |
255 | struct drm_i915_private *dev_priv = dev->dev_private; |
297 | struct drm_i915_private *dev_priv = dev->dev_private; |
256 | enum port port = intel_dig_port->port; |
298 | enum port port = intel_dig_port->port; |
257 | enum pipe pipe; |
299 | enum pipe pipe; |
258 | 300 | ||
259 | /* modeset should have pipe */ |
301 | /* modeset should have pipe */ |
260 | if (crtc) |
302 | if (crtc) |
261 | return to_intel_crtc(crtc)->pipe; |
303 | return to_intel_crtc(crtc)->pipe; |
262 | 304 | ||
263 | /* init time, try to find a pipe with this port selected */ |
305 | /* init time, try to find a pipe with this port selected */ |
264 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
306 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
265 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
307 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
266 | PANEL_PORT_SELECT_MASK; |
308 | PANEL_PORT_SELECT_MASK; |
267 | if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) |
309 | if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) |
268 | return pipe; |
310 | return pipe; |
269 | if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) |
311 | if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) |
270 | return pipe; |
312 | return pipe; |
271 | } |
313 | } |
272 | 314 | ||
273 | /* shrug */ |
315 | /* shrug */ |
274 | return PIPE_A; |
316 | return PIPE_A; |
275 | } |
317 | } |
276 | 318 | ||
277 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) |
319 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) |
278 | { |
320 | { |
279 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
321 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
280 | 322 | ||
281 | if (HAS_PCH_SPLIT(dev)) |
323 | if (HAS_PCH_SPLIT(dev)) |
282 | return PCH_PP_CONTROL; |
324 | return PCH_PP_CONTROL; |
283 | else |
325 | else |
284 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
326 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
285 | } |
327 | } |
286 | 328 | ||
287 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) |
329 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) |
288 | { |
330 | { |
289 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
331 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
290 | 332 | ||
291 | if (HAS_PCH_SPLIT(dev)) |
333 | if (HAS_PCH_SPLIT(dev)) |
292 | return PCH_PP_STATUS; |
334 | return PCH_PP_STATUS; |
293 | else |
335 | else |
294 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
336 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
295 | } |
337 | } |
- | 338 | ||
296 | 339 | ||
297 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
340 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
298 | { |
341 | { |
299 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
342 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
300 | struct drm_i915_private *dev_priv = dev->dev_private; |
343 | struct drm_i915_private *dev_priv = dev->dev_private; |
301 | 344 | ||
302 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
345 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
303 | } |
346 | } |
304 | 347 | ||
305 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) |
348 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
306 | { |
349 | { |
307 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
350 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
308 | struct drm_i915_private *dev_priv = dev->dev_private; |
351 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 352 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 353 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
- | 354 | enum intel_display_power_domain power_domain; |
|
- | 355 | ||
- | 356 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
309 | 357 | return intel_display_power_enabled(dev_priv, power_domain) && |
|
310 | return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; |
358 | (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; |
311 | } |
359 | } |
312 | 360 | ||
313 | static void |
361 | static void |
314 | intel_dp_check_edp(struct intel_dp *intel_dp) |
362 | intel_dp_check_edp(struct intel_dp *intel_dp) |
315 | { |
363 | { |
316 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
364 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
317 | struct drm_i915_private *dev_priv = dev->dev_private; |
365 | struct drm_i915_private *dev_priv = dev->dev_private; |
318 | 366 | ||
319 | if (!is_edp(intel_dp)) |
367 | if (!is_edp(intel_dp)) |
320 | return; |
368 | return; |
321 | 369 | ||
322 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
370 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
323 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
371 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
324 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
372 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
325 | I915_READ(_pp_stat_reg(intel_dp)), |
373 | I915_READ(_pp_stat_reg(intel_dp)), |
326 | I915_READ(_pp_ctrl_reg(intel_dp))); |
374 | I915_READ(_pp_ctrl_reg(intel_dp))); |
327 | } |
375 | } |
328 | } |
376 | } |
329 | 377 | ||
330 | static uint32_t |
378 | static uint32_t |
331 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
379 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
332 | { |
380 | { |
333 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
381 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
334 | struct drm_device *dev = intel_dig_port->base.base.dev; |
382 | struct drm_device *dev = intel_dig_port->base.base.dev; |
335 | struct drm_i915_private *dev_priv = dev->dev_private; |
383 | struct drm_i915_private *dev_priv = dev->dev_private; |
336 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
384 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
337 | uint32_t status; |
385 | uint32_t status; |
338 | bool done; |
386 | bool done; |
339 | 387 | ||
340 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
388 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
341 | if (has_aux_irq) |
389 | if (has_aux_irq) |
342 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
390 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
343 | msecs_to_jiffies_timeout(10)); |
391 | msecs_to_jiffies_timeout(10)); |
344 | else |
392 | else |
345 | done = wait_for_atomic(C, 10) == 0; |
393 | done = wait_for_atomic(C, 10) == 0; |
346 | if (!done) |
394 | if (!done) |
347 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
395 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
348 | has_aux_irq); |
396 | has_aux_irq); |
349 | #undef C |
397 | #undef C |
350 | 398 | ||
351 | return status; |
399 | return status; |
352 | } |
400 | } |
353 | 401 | ||
354 | static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp, |
- | |
355 | int index) |
402 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
356 | { |
403 | { |
357 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
404 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
358 | struct drm_device *dev = intel_dig_port->base.base.dev; |
405 | struct drm_device *dev = intel_dig_port->base.base.dev; |
359 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
360 | - | ||
361 | /* The clock divider is based off the hrawclk, |
- | |
362 | * and would like to run at 2MHz. So, take the |
- | |
363 | * hrawclk value and divide by 2 and use that |
406 | |
364 | * |
407 | /* |
365 | * Note that PCH attached eDP panels should use a 125MHz input |
408 | * The clock divider is based off the hrawclk, and would like to run at |
366 | * clock divider. |
409 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
367 | */ |
410 | */ |
- | 411 | return index ? 0 : intel_hrawclk(dev) / 2; |
|
- | 412 | } |
|
- | 413 | ||
- | 414 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
|
368 | if (IS_VALLEYVIEW(dev)) { |
415 | { |
369 | return index ? 0 : 100; |
416 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | 417 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
370 | } else if (intel_dig_port->port == PORT_A) { |
418 | |
371 | if (index) |
419 | if (index) |
372 | return 0; |
- | |
- | 420 | return 0; |
|
373 | if (HAS_DDI(dev)) |
421 | |
374 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); |
422 | if (intel_dig_port->port == PORT_A) { |
375 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
423 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
376 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
424 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
377 | else |
425 | else |
378 | return 225; /* eDP input clock at 450Mhz */ |
426 | return 225; /* eDP input clock at 450Mhz */ |
- | 427 | } else { |
|
- | 428 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
|
- | 429 | } |
|
- | 430 | } |
|
- | 431 | ||
- | 432 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
|
- | 433 | { |
|
- | 434 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 435 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 436 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 437 | ||
- | 438 | if (intel_dig_port->port == PORT_A) { |
|
- | 439 | if (index) |
|
- | 440 | return 0; |
|
- | 441 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); |
|
379 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
442 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
380 | /* Workaround for non-ULT HSW */ |
443 | /* Workaround for non-ULT HSW */ |
381 | switch (index) { |
444 | switch (index) { |
382 | case 0: return 63; |
445 | case 0: return 63; |
383 | case 1: return 72; |
446 | case 1: return 72; |
384 | default: return 0; |
447 | default: return 0; |
385 | } |
448 | } |
386 | } else if (HAS_PCH_SPLIT(dev)) { |
- | |
387 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
- | |
388 | } else { |
449 | } else { |
389 | return index ? 0 :intel_hrawclk(dev) / 2; |
450 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
390 | } |
451 | } |
391 | } |
452 | } |
- | 453 | ||
- | 454 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
|
- | 455 | { |
|
- | 456 | return index ? 0 : 100; |
|
- | 457 | } |
|
- | 458 | ||
- | 459 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
|
- | 460 | bool has_aux_irq, |
|
- | 461 | int send_bytes, |
|
- | 462 | uint32_t aux_clock_divider) |
|
- | 463 | { |
|
- | 464 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 465 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 466 | uint32_t precharge, timeout; |
|
- | 467 | ||
- | 468 | if (IS_GEN6(dev)) |
|
- | 469 | precharge = 3; |
|
- | 470 | else |
|
- | 471 | precharge = 5; |
|
- | 472 | ||
- | 473 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) |
|
- | 474 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
|
- | 475 | else |
|
- | 476 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
|
- | 477 | ||
- | 478 | return DP_AUX_CH_CTL_SEND_BUSY | |
|
- | 479 | DP_AUX_CH_CTL_DONE | |
|
- | 480 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
|
- | 481 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
|
- | 482 | timeout | |
|
- | 483 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
|
- | 484 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
|
- | 485 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
|
- | 486 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
|
- | 487 | } |
|
392 | 488 | ||
393 | static int |
489 | static int |
394 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
490 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
395 | uint8_t *send, int send_bytes, |
491 | uint8_t *send, int send_bytes, |
396 | uint8_t *recv, int recv_size) |
492 | uint8_t *recv, int recv_size) |
397 | { |
493 | { |
398 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
494 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
399 | struct drm_device *dev = intel_dig_port->base.base.dev; |
495 | struct drm_device *dev = intel_dig_port->base.base.dev; |
400 | struct drm_i915_private *dev_priv = dev->dev_private; |
496 | struct drm_i915_private *dev_priv = dev->dev_private; |
401 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
497 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
402 | uint32_t ch_data = ch_ctl + 4; |
498 | uint32_t ch_data = ch_ctl + 4; |
403 | uint32_t aux_clock_divider; |
499 | uint32_t aux_clock_divider; |
404 | int i, ret, recv_bytes; |
500 | int i, ret, recv_bytes; |
405 | uint32_t status; |
501 | uint32_t status; |
406 | int try, precharge, clock = 0; |
502 | int try, clock = 0; |
407 | bool has_aux_irq = true; |
503 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
408 | uint32_t timeout; |
504 | bool vdd; |
- | 505 | ||
- | 506 | vdd = _edp_panel_vdd_on(intel_dp); |
|
409 | 507 | ||
410 | /* dp aux is extremely sensitive to irq latency, hence request the |
508 | /* dp aux is extremely sensitive to irq latency, hence request the |
411 | * lowest possible wakeup latency and so prevent the cpu from going into |
509 | * lowest possible wakeup latency and so prevent the cpu from going into |
412 | * deep sleep states. |
510 | * deep sleep states. |
413 | */ |
511 | */ |
414 | // pm_qos_update_request(&dev_priv->pm_qos, 0); |
- | |
415 | 512 | ||
416 | intel_dp_check_edp(intel_dp); |
513 | intel_dp_check_edp(intel_dp); |
417 | - | ||
418 | if (IS_GEN6(dev)) |
- | |
419 | precharge = 3; |
- | |
420 | else |
- | |
421 | precharge = 5; |
- | |
422 | - | ||
423 | if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL) |
- | |
424 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
- | |
425 | else |
- | |
426 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
- | |
427 | 514 | ||
428 | intel_aux_display_runtime_get(dev_priv); |
515 | intel_aux_display_runtime_get(dev_priv); |
429 | 516 | ||
430 | /* Try to wait for any previous AUX channel activity */ |
517 | /* Try to wait for any previous AUX channel activity */ |
431 | for (try = 0; try < 3; try++) { |
518 | for (try = 0; try < 3; try++) { |
432 | status = I915_READ_NOTRACE(ch_ctl); |
519 | status = I915_READ_NOTRACE(ch_ctl); |
433 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
520 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
434 | break; |
521 | break; |
435 | msleep(1); |
522 | msleep(1); |
436 | } |
523 | } |
437 | 524 | ||
438 | if (try == 3) { |
525 | if (try == 3) { |
439 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
526 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
440 | I915_READ(ch_ctl)); |
527 | I915_READ(ch_ctl)); |
441 | ret = -EBUSY; |
528 | ret = -EBUSY; |
442 | goto out; |
529 | goto out; |
443 | } |
530 | } |
444 | 531 | ||
445 | /* Only 5 data registers! */ |
532 | /* Only 5 data registers! */ |
446 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
533 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
447 | ret = -E2BIG; |
534 | ret = -E2BIG; |
448 | goto out; |
535 | goto out; |
449 | } |
536 | } |
450 | 537 | ||
- | 538 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
|
- | 539 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
|
- | 540 | has_aux_irq, |
|
- | 541 | send_bytes, |
|
- | 542 | aux_clock_divider); |
|
451 | while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) { |
543 | |
452 | /* Must try at least 3 times according to DP spec */ |
544 | /* Must try at least 3 times according to DP spec */ |
453 | for (try = 0; try < 5; try++) { |
545 | for (try = 0; try < 5; try++) { |
454 | /* Load the send data into the aux channel data registers */ |
546 | /* Load the send data into the aux channel data registers */ |
455 | for (i = 0; i < send_bytes; i += 4) |
547 | for (i = 0; i < send_bytes; i += 4) |
456 | I915_WRITE(ch_data + i, |
548 | I915_WRITE(ch_data + i, |
457 | pack_aux(send + i, send_bytes - i)); |
549 | pack_aux(send + i, send_bytes - i)); |
458 | 550 | ||
459 | /* Send the command and wait for it to complete */ |
551 | /* Send the command and wait for it to complete */ |
460 | I915_WRITE(ch_ctl, |
552 | I915_WRITE(ch_ctl, send_ctl); |
461 | DP_AUX_CH_CTL_SEND_BUSY | |
- | |
462 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
- | |
463 | timeout | |
- | |
464 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
- | |
465 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
- | |
466 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
- | |
467 | DP_AUX_CH_CTL_DONE | |
- | |
468 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
- | |
469 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
- | |
470 | 553 | ||
471 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
554 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
472 | 555 | ||
473 | /* Clear done status and any errors */ |
556 | /* Clear done status and any errors */ |
474 | I915_WRITE(ch_ctl, |
557 | I915_WRITE(ch_ctl, |
475 | status | |
558 | status | |
476 | DP_AUX_CH_CTL_DONE | |
559 | DP_AUX_CH_CTL_DONE | |
477 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
560 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
478 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
561 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
479 | 562 | ||
480 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | |
563 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | |
481 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
564 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
482 | continue; |
565 | continue; |
483 | if (status & DP_AUX_CH_CTL_DONE) |
566 | if (status & DP_AUX_CH_CTL_DONE) |
484 | break; |
567 | break; |
485 | } |
568 | } |
486 | if (status & DP_AUX_CH_CTL_DONE) |
569 | if (status & DP_AUX_CH_CTL_DONE) |
487 | break; |
570 | break; |
488 | } |
571 | } |
489 | 572 | ||
490 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
573 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
491 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
574 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
492 | ret = -EBUSY; |
575 | ret = -EBUSY; |
493 | goto out; |
576 | goto out; |
494 | } |
577 | } |
495 | 578 | ||
496 | /* Check for timeout or receive error. |
579 | /* Check for timeout or receive error. |
497 | * Timeouts occur when the sink is not connected |
580 | * Timeouts occur when the sink is not connected |
498 | */ |
581 | */ |
499 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
582 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
500 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
583 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
501 | ret = -EIO; |
584 | ret = -EIO; |
502 | goto out; |
585 | goto out; |
503 | } |
586 | } |
504 | 587 | ||
505 | /* Timeouts occur when the device isn't connected, so they're |
588 | /* Timeouts occur when the device isn't connected, so they're |
506 | * "normal" -- don't fill the kernel log with these */ |
589 | * "normal" -- don't fill the kernel log with these */ |
507 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
590 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
508 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
591 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
509 | ret = -ETIMEDOUT; |
592 | ret = -ETIMEDOUT; |
510 | goto out; |
593 | goto out; |
511 | } |
594 | } |
512 | 595 | ||
513 | /* Unload any bytes sent back from the other side */ |
596 | /* Unload any bytes sent back from the other side */ |
514 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
597 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
515 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
598 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
516 | if (recv_bytes > recv_size) |
599 | if (recv_bytes > recv_size) |
517 | recv_bytes = recv_size; |
600 | recv_bytes = recv_size; |
518 | 601 | ||
519 | for (i = 0; i < recv_bytes; i += 4) |
602 | for (i = 0; i < recv_bytes; i += 4) |
520 | unpack_aux(I915_READ(ch_data + i), |
603 | unpack_aux(I915_READ(ch_data + i), |
521 | recv + i, recv_bytes - i); |
604 | recv + i, recv_bytes - i); |
522 | 605 | ||
523 | ret = recv_bytes; |
606 | ret = recv_bytes; |
524 | out: |
607 | out: |
525 | // pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
608 | // pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
526 | intel_aux_display_runtime_put(dev_priv); |
609 | intel_aux_display_runtime_put(dev_priv); |
- | 610 | ||
- | 611 | if (vdd) |
|
- | 612 | edp_panel_vdd_off(intel_dp, false); |
|
527 | 613 | ||
528 | return ret; |
614 | return ret; |
529 | } |
615 | } |
- | 616 | ||
530 | 617 | #define BARE_ADDRESS_SIZE 3 |
|
531 | /* Write data to the aux channel in native mode */ |
618 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
532 | static int |
619 | static ssize_t |
533 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
- | |
534 | uint16_t address, uint8_t *send, int send_bytes) |
620 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
- | 621 | { |
|
- | 622 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
|
- | 623 | uint8_t txbuf[20], rxbuf[20]; |
|
535 | { |
624 | size_t txsize, rxsize; |
536 | int ret; |
- | |
537 | uint8_t msg[20]; |
- | |
538 | int msg_bytes; |
- | |
- | 625 | int ret; |
|
- | 626 | ||
- | 627 | txbuf[0] = msg->request << 4; |
|
- | 628 | txbuf[1] = msg->address >> 8; |
|
- | 629 | txbuf[2] = msg->address & 0xff; |
|
- | 630 | txbuf[3] = msg->size - 1; |
|
- | 631 | ||
- | 632 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
|
- | 633 | case DP_AUX_NATIVE_WRITE: |
|
- | 634 | case DP_AUX_I2C_WRITE: |
|
- | 635 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
|
539 | uint8_t ack; |
636 | rxsize = 1; |
540 | 637 | ||
541 | if (WARN_ON(send_bytes > 16)) |
- | |
542 | return -E2BIG; |
- | |
543 | - | ||
544 | intel_dp_check_edp(intel_dp); |
- | |
545 | msg[0] = DP_AUX_NATIVE_WRITE << 4; |
- | |
546 | msg[1] = address >> 8; |
- | |
547 | msg[2] = address & 0xff; |
- | |
548 | msg[3] = send_bytes - 1; |
- | |
549 | memcpy(&msg[4], send, send_bytes); |
638 | if (WARN_ON(txsize > 20)) |
550 | msg_bytes = send_bytes + 4; |
- | |
551 | for (;;) { |
- | |
552 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
- | |
553 | if (ret < 0) |
- | |
554 | return ret; |
- | |
555 | ack >>= 4; |
- | |
556 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) |
- | |
557 | break; |
- | |
558 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
- | |
559 | udelay(100); |
- | |
560 | else |
- | |
561 | return -EIO; |
- | |
562 | } |
639 | return -E2BIG; |
563 | return send_bytes; |
640 | |
564 | } |
- | |
565 | 641 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
|
566 | /* Write a single byte to the aux channel in native mode */ |
642 | |
567 | static int |
643 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
- | 644 | if (ret > 0) { |
|
568 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
645 | msg->reply = rxbuf[0] >> 4; |
- | 646 | ||
569 | uint16_t address, uint8_t byte) |
647 | /* Return payload size. */ |
570 | { |
648 | ret = msg->size; |
571 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
- | |
572 | } |
649 | } |
573 | - | ||
574 | /* read bytes from a native aux channel */ |
- | |
575 | static int |
650 | break; |
576 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
- | |
577 | uint16_t address, uint8_t *recv, int recv_bytes) |
- | |
578 | { |
- | |
579 | uint8_t msg[4]; |
- | |
580 | int msg_bytes; |
651 | |
581 | uint8_t reply[20]; |
652 | case DP_AUX_NATIVE_READ: |
582 | int reply_bytes; |
653 | case DP_AUX_I2C_READ: |
583 | uint8_t ack; |
654 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
584 | int ret; |
655 | rxsize = msg->size + 1; |
- | 656 | ||
- | 657 | if (WARN_ON(rxsize > 20)) |
|
- | 658 | return -E2BIG; |
|
- | 659 | ||
585 | 660 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
|
- | 661 | if (ret > 0) { |
|
- | 662 | msg->reply = rxbuf[0] >> 4; |
|
586 | if (WARN_ON(recv_bytes > 19)) |
663 | /* |
- | 664 | * Assume happy day, and copy the data. The caller is |
|
- | 665 | * expected to check msg->reply before touching it. |
|
587 | return -E2BIG; |
666 | * |
588 | 667 | * Return payload size. |
|
- | 668 | */ |
|
- | 669 | ret--; |
|
589 | intel_dp_check_edp(intel_dp); |
- | |
590 | msg[0] = DP_AUX_NATIVE_READ << 4; |
- | |
591 | msg[1] = address >> 8; |
- | |
592 | msg[2] = address & 0xff; |
- | |
593 | msg[3] = recv_bytes - 1; |
- | |
594 | - | ||
595 | msg_bytes = 4; |
670 | memcpy(msg->buffer, rxbuf + 1, ret); |
596 | reply_bytes = recv_bytes + 1; |
- | |
597 | - | ||
598 | for (;;) { |
- | |
599 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
- | |
600 | reply, reply_bytes); |
- | |
601 | if (ret == 0) |
- | |
602 | return -EPROTO; |
- | |
603 | if (ret < 0) |
- | |
604 | return ret; |
- | |
605 | ack = reply[0] >> 4; |
- | |
606 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) { |
671 | } |
607 | memcpy(recv, reply + 1, ret - 1); |
672 | break; |
608 | return ret - 1; |
673 | |
609 | } |
- | |
610 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
674 | default: |
611 | udelay(100); |
675 | ret = -EINVAL; |
612 | else |
676 | break; |
613 | return -EIO; |
- | |
614 | } |
- | |
615 | } |
677 | } |
616 | - | ||
617 | static int |
678 | |
618 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
- | |
619 | uint8_t write_byte, uint8_t *read_byte) |
- | |
620 | { |
- | |
621 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
679 | return ret; |
622 | struct intel_dp *intel_dp = container_of(adapter, |
- | |
623 | struct intel_dp, |
- | |
624 | adapter); |
- | |
625 | uint16_t address = algo_data->address; |
- | |
626 | uint8_t msg[5]; |
- | |
627 | uint8_t reply[2]; |
- | |
628 | unsigned retry; |
- | |
629 | int msg_bytes; |
- | |
630 | int reply_bytes; |
- | |
631 | int ret; |
- | |
632 | - | ||
633 | ironlake_edp_panel_vdd_on(intel_dp); |
- | |
634 | intel_dp_check_edp(intel_dp); |
- | |
635 | /* Set up the command byte */ |
- | |
636 | if (mode & MODE_I2C_READ) |
680 | } |
637 | msg[0] = DP_AUX_I2C_READ << 4; |
681 | |
638 | else |
- | |
639 | msg[0] = DP_AUX_I2C_WRITE << 4; |
682 | static void |
640 | 683 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
|
641 | if (!(mode & MODE_I2C_STOP)) |
- | |
642 | msg[0] |= DP_AUX_I2C_MOT << 4; |
684 | { |
643 | 685 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
644 | msg[1] = address >> 8; |
- | |
645 | msg[2] = address; |
686 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
646 | 687 | enum port port = intel_dig_port->port; |
|
647 | switch (mode) { |
688 | const char *name = NULL; |
648 | case MODE_I2C_WRITE: |
689 | int ret; |
649 | msg[3] = 0; |
690 | |
650 | msg[4] = write_byte; |
691 | switch (port) { |
651 | msg_bytes = 5; |
692 | case PORT_A: |
652 | reply_bytes = 1; |
- | |
653 | break; |
- | |
654 | case MODE_I2C_READ: |
- | |
655 | msg[3] = 0; |
- | |
656 | msg_bytes = 4; |
- | |
657 | reply_bytes = 2; |
- | |
658 | break; |
- | |
659 | default: |
- | |
660 | msg_bytes = 3; |
- | |
661 | reply_bytes = 1; |
- | |
662 | break; |
- | |
663 | } |
693 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
664 | 694 | name = "DPDDC-A"; |
|
665 | /* |
695 | break; |
666 | * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is |
- | |
667 | * required to retry at least seven times upon receiving AUX_DEFER |
- | |
668 | * before giving up the AUX transaction. |
- | |
669 | */ |
- | |
670 | for (retry = 0; retry < 7; retry++) { |
- | |
671 | ret = intel_dp_aux_ch(intel_dp, |
- | |
672 | msg, msg_bytes, |
- | |
673 | reply, reply_bytes); |
696 | case PORT_B: |
674 | if (ret < 0) { |
- | |
675 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
- | |
676 | goto out; |
- | |
677 | } |
- | |
678 | - | ||
679 | switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { |
- | |
680 | case DP_AUX_NATIVE_REPLY_ACK: |
- | |
681 | /* I2C-over-AUX Reply field is only valid |
- | |
682 | * when paired with AUX ACK. |
- | |
683 | */ |
- | |
684 | break; |
- | |
685 | case DP_AUX_NATIVE_REPLY_NACK: |
- | |
686 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
- | |
687 | ret = -EREMOTEIO; |
- | |
688 | goto out; |
697 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
689 | case DP_AUX_NATIVE_REPLY_DEFER: |
- | |
690 | /* |
- | |
691 | * For now, just give more slack to branch devices. We |
- | |
692 | * could check the DPCD for I2C bit rate capabilities, |
698 | name = "DPDDC-B"; |
693 | * and if available, adjust the interval. We could also |
699 | break; |
694 | * be more careful with DP-to-Legacy adapters where a |
- | |
695 | * long legacy cable may force very low I2C bit rates. |
- | |
696 | */ |
- | |
697 | udelay(400); |
- | |
698 | continue; |
- | |
699 | default: |
- | |
700 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", |
- | |
701 | reply[0]); |
- | |
702 | ret = -EREMOTEIO; |
- | |
703 | goto out; |
- | |
704 | } |
- | |
705 | - | ||
706 | switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { |
- | |
707 | case DP_AUX_I2C_REPLY_ACK: |
700 | case PORT_C: |
708 | if (mode == MODE_I2C_READ) { |
- | |
709 | *read_byte = reply[1]; |
- | |
710 | } |
701 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
711 | ret = reply_bytes - 1; |
- | |
712 | goto out; |
- | |
713 | case DP_AUX_I2C_REPLY_NACK: |
- | |
714 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
- | |
715 | ret = -EREMOTEIO; |
702 | name = "DPDDC-C"; |
716 | goto out; |
703 | break; |
- | 704 | case PORT_D: |
|
717 | case DP_AUX_I2C_REPLY_DEFER: |
705 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
718 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
706 | name = "DPDDC-D"; |
- | 707 | break; |
|
- | 708 | default: |
|
- | 709 | BUG(); |
|
719 | udelay(100); |
710 | } |
- | 711 | ||
720 | break; |
712 | if (!HAS_DDI(dev)) |
721 | default: |
713 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
722 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
714 | |
723 | ret = -EREMOTEIO; |
- | |
724 | goto out; |
715 | intel_dp->aux.name = name; |
725 | } |
716 | intel_dp->aux.dev = dev->dev; |
726 | } |
- | |
727 | - | ||
728 | DRM_ERROR("too many retries, giving up\n"); |
- | |
729 | ret = -EREMOTEIO; |
717 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
730 | 718 | ||
731 | out: |
- | |
732 | ironlake_edp_panel_vdd_off(intel_dp, false); |
- | |
733 | return ret; |
- | |
734 | } |
- | |
735 | - | ||
736 | static int |
- | |
737 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
- | |
- | 719 | ||
- | 720 | ret = drm_dp_aux_register(&intel_dp->aux); |
|
- | 721 | if (ret < 0) { |
|
- | 722 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
|
- | 723 | name, ret); |
|
738 | struct intel_connector *intel_connector, const char *name) |
724 | return; |
- | 725 | } |
|
- | 726 | } |
|
- | 727 | ||
- | 728 | static void |
|
- | 729 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
|
- | 730 | { |
|
739 | { |
731 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
- | 732 | ||
740 | int ret; |
733 | intel_connector_unregister(intel_connector); |
741 | 734 | } |
|
742 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
735 | |
743 | intel_dp->algo.running = false; |
736 | static void |
744 | intel_dp->algo.address = 0; |
737 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) |
745 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; |
738 | { |
746 | 739 | switch (link_bw) { |
|
747 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
740 | case DP_LINK_BW_1_62: |
748 | intel_dp->adapter.owner = THIS_MODULE; |
741 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
749 | intel_dp->adapter.class = I2C_CLASS_DDC; |
742 | break; |
750 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
743 | case DP_LINK_BW_2_7: |
751 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
744 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
752 | intel_dp->adapter.algo_data = &intel_dp->algo; |
745 | break; |
753 | intel_dp->adapter.dev.parent = intel_connector->base.kdev; |
746 | case DP_LINK_BW_5_4: |
754 | 747 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
|
755 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
748 | break; |
756 | return ret; |
749 | } |
757 | } |
750 | } |
758 | 751 | ||
759 | static void |
752 | static void |
760 | intel_dp_set_clock(struct intel_encoder *encoder, |
753 | intel_dp_set_clock(struct intel_encoder *encoder, |
761 | struct intel_crtc_config *pipe_config, int link_bw) |
754 | struct intel_crtc_config *pipe_config, int link_bw) |
762 | { |
755 | { |
763 | struct drm_device *dev = encoder->base.dev; |
756 | struct drm_device *dev = encoder->base.dev; |
764 | const struct dp_link_dpll *divisor = NULL; |
757 | const struct dp_link_dpll *divisor = NULL; |
765 | int i, count = 0; |
758 | int i, count = 0; |
766 | 759 | ||
767 | if (IS_G4X(dev)) { |
760 | if (IS_G4X(dev)) { |
768 | divisor = gen4_dpll; |
761 | divisor = gen4_dpll; |
769 | count = ARRAY_SIZE(gen4_dpll); |
762 | count = ARRAY_SIZE(gen4_dpll); |
770 | } else if (IS_HASWELL(dev)) { |
- | |
771 | /* Haswell has special-purpose DP DDI clocks. */ |
- | |
772 | } else if (HAS_PCH_SPLIT(dev)) { |
763 | } else if (HAS_PCH_SPLIT(dev)) { |
773 | divisor = pch_dpll; |
764 | divisor = pch_dpll; |
774 | count = ARRAY_SIZE(pch_dpll); |
765 | count = ARRAY_SIZE(pch_dpll); |
- | 766 | } else if (IS_CHERRYVIEW(dev)) { |
|
- | 767 | divisor = chv_dpll; |
|
- | 768 | count = ARRAY_SIZE(chv_dpll); |
|
775 | } else if (IS_VALLEYVIEW(dev)) { |
769 | } else if (IS_VALLEYVIEW(dev)) { |
776 | divisor = vlv_dpll; |
770 | divisor = vlv_dpll; |
777 | count = ARRAY_SIZE(vlv_dpll); |
771 | count = ARRAY_SIZE(vlv_dpll); |
778 | } |
772 | } |
779 | 773 | ||
780 | if (divisor && count) { |
774 | if (divisor && count) { |
781 | for (i = 0; i < count; i++) { |
775 | for (i = 0; i < count; i++) { |
782 | if (link_bw == divisor[i].link_bw) { |
776 | if (link_bw == divisor[i].link_bw) { |
783 | pipe_config->dpll = divisor[i].dpll; |
777 | pipe_config->dpll = divisor[i].dpll; |
784 | pipe_config->clock_set = true; |
778 | pipe_config->clock_set = true; |
785 | break; |
779 | break; |
786 | } |
780 | } |
787 | } |
781 | } |
788 | } |
782 | } |
789 | } |
783 | } |
- | 784 | ||
- | 785 | static void |
|
- | 786 | intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) |
|
- | 787 | { |
|
- | 788 | struct drm_device *dev = crtc->base.dev; |
|
- | 789 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 790 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
|
- | 791 | ||
- | 792 | I915_WRITE(PIPE_DATA_M2(transcoder), |
|
- | 793 | TU_SIZE(m_n->tu) | m_n->gmch_m); |
|
- | 794 | I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); |
|
- | 795 | I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); |
|
- | 796 | I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); |
|
- | 797 | } |
|
790 | 798 | ||
791 | bool |
799 | bool |
792 | intel_dp_compute_config(struct intel_encoder *encoder, |
800 | intel_dp_compute_config(struct intel_encoder *encoder, |
793 | struct intel_crtc_config *pipe_config) |
801 | struct intel_crtc_config *pipe_config) |
794 | { |
802 | { |
795 | struct drm_device *dev = encoder->base.dev; |
803 | struct drm_device *dev = encoder->base.dev; |
796 | struct drm_i915_private *dev_priv = dev->dev_private; |
804 | struct drm_i915_private *dev_priv = dev->dev_private; |
797 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
805 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
798 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
806 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
799 | enum port port = dp_to_dig_port(intel_dp)->port; |
807 | enum port port = dp_to_dig_port(intel_dp)->port; |
800 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
808 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
801 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
809 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
802 | int lane_count, clock; |
810 | int lane_count, clock; |
- | 811 | int min_lane_count = 1; |
|
803 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
812 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
- | 813 | /* Conveniently, the link BW constants become indices with a shift...*/ |
|
- | 814 | int min_clock = 0; |
|
804 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
815 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; |
805 | int bpp, mode_rate; |
816 | int bpp, mode_rate; |
806 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
817 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
807 | int link_avail, link_clock; |
818 | int link_avail, link_clock; |
808 | 819 | ||
809 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
820 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
810 | pipe_config->has_pch_encoder = true; |
821 | pipe_config->has_pch_encoder = true; |
811 | 822 | ||
812 | pipe_config->has_dp_encoder = true; |
823 | pipe_config->has_dp_encoder = true; |
- | 824 | pipe_config->has_audio = intel_dp->has_audio; |
|
813 | 825 | ||
814 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
826 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
815 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
827 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
816 | adjusted_mode); |
828 | adjusted_mode); |
817 | if (!HAS_PCH_SPLIT(dev)) |
829 | if (!HAS_PCH_SPLIT(dev)) |
818 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
830 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
819 | intel_connector->panel.fitting_mode); |
831 | intel_connector->panel.fitting_mode); |
820 | else |
832 | else |
821 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
833 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
822 | intel_connector->panel.fitting_mode); |
834 | intel_connector->panel.fitting_mode); |
823 | } |
835 | } |
824 | 836 | ||
825 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
837 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
826 | return false; |
838 | return false; |
827 | 839 | ||
828 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
840 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
829 | "max bw %02x pixel clock %iKHz\n", |
841 | "max bw %02x pixel clock %iKHz\n", |
830 | max_lane_count, bws[max_clock], |
842 | max_lane_count, bws[max_clock], |
831 | adjusted_mode->crtc_clock); |
843 | adjusted_mode->crtc_clock); |
832 | 844 | ||
833 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
845 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
834 | * bpc in between. */ |
846 | * bpc in between. */ |
835 | bpp = pipe_config->pipe_bpp; |
847 | bpp = pipe_config->pipe_bpp; |
836 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
848 | if (is_edp(intel_dp)) { |
837 | dev_priv->vbt.edp_bpp < bpp) { |
849 | if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { |
838 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
850 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
839 | dev_priv->vbt.edp_bpp); |
851 | dev_priv->vbt.edp_bpp); |
840 | bpp = dev_priv->vbt.edp_bpp; |
852 | bpp = dev_priv->vbt.edp_bpp; |
841 | } |
853 | } |
- | 854 | ||
- | 855 | if (IS_BROADWELL(dev)) { |
|
- | 856 | /* Yes, it's an ugly hack. */ |
|
- | 857 | min_lane_count = max_lane_count; |
|
- | 858 | DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", |
|
- | 859 | min_lane_count); |
|
- | 860 | } else if (dev_priv->vbt.edp_lanes) { |
|
- | 861 | min_lane_count = min(dev_priv->vbt.edp_lanes, |
|
- | 862 | max_lane_count); |
|
- | 863 | DRM_DEBUG_KMS("using min %u lanes per VBT\n", |
|
- | 864 | min_lane_count); |
|
- | 865 | } |
|
- | 866 | ||
- | 867 | if (dev_priv->vbt.edp_rate) { |
|
- | 868 | min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); |
|
- | 869 | DRM_DEBUG_KMS("using min %02x link bw per VBT\n", |
|
- | 870 | bws[min_clock]); |
|
- | 871 | } |
|
- | 872 | } |
|
842 | 873 | ||
843 | for (; bpp >= 6*3; bpp -= 2*3) { |
874 | for (; bpp >= 6*3; bpp -= 2*3) { |
844 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
875 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
845 | bpp); |
876 | bpp); |
846 | 877 | ||
847 | for (clock = 0; clock <= max_clock; clock++) { |
878 | for (clock = min_clock; clock <= max_clock; clock++) { |
848 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
879 | for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { |
849 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
880 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
850 | link_avail = intel_dp_max_data_rate(link_clock, |
881 | link_avail = intel_dp_max_data_rate(link_clock, |
851 | lane_count); |
882 | lane_count); |
852 | 883 | ||
853 | if (mode_rate <= link_avail) { |
884 | if (mode_rate <= link_avail) { |
854 | goto found; |
885 | goto found; |
855 | } |
886 | } |
856 | } |
887 | } |
857 | } |
888 | } |
858 | } |
889 | } |
859 | 890 | ||
860 | return false; |
891 | return false; |
861 | 892 | ||
862 | found: |
893 | found: |
863 | if (intel_dp->color_range_auto) { |
894 | if (intel_dp->color_range_auto) { |
864 | /* |
895 | /* |
865 | * See: |
896 | * See: |
866 | * CEA-861-E - 5.1 Default Encoding Parameters |
897 | * CEA-861-E - 5.1 Default Encoding Parameters |
867 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
898 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
868 | */ |
899 | */ |
869 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
900 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
870 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
901 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
871 | else |
902 | else |
872 | intel_dp->color_range = 0; |
903 | intel_dp->color_range = 0; |
873 | } |
904 | } |
874 | 905 | ||
875 | if (intel_dp->color_range) |
906 | if (intel_dp->color_range) |
876 | pipe_config->limited_color_range = true; |
907 | pipe_config->limited_color_range = true; |
877 | 908 | ||
878 | intel_dp->link_bw = bws[clock]; |
909 | intel_dp->link_bw = bws[clock]; |
879 | intel_dp->lane_count = lane_count; |
910 | intel_dp->lane_count = lane_count; |
880 | pipe_config->pipe_bpp = bpp; |
911 | pipe_config->pipe_bpp = bpp; |
881 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
912 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
882 | 913 | ||
883 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
914 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
884 | intel_dp->link_bw, intel_dp->lane_count, |
915 | intel_dp->link_bw, intel_dp->lane_count, |
885 | pipe_config->port_clock, bpp); |
916 | pipe_config->port_clock, bpp); |
886 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
917 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
887 | mode_rate, link_avail); |
918 | mode_rate, link_avail); |
888 | 919 | ||
889 | intel_link_compute_m_n(bpp, lane_count, |
920 | intel_link_compute_m_n(bpp, lane_count, |
890 | adjusted_mode->crtc_clock, |
921 | adjusted_mode->crtc_clock, |
891 | pipe_config->port_clock, |
922 | pipe_config->port_clock, |
892 | &pipe_config->dp_m_n); |
923 | &pipe_config->dp_m_n); |
- | 924 | ||
- | 925 | if (intel_connector->panel.downclock_mode != NULL && |
|
- | 926 | intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { |
|
- | 927 | intel_link_compute_m_n(bpp, lane_count, |
|
- | 928 | intel_connector->panel.downclock_mode->clock, |
|
- | 929 | pipe_config->port_clock, |
|
- | 930 | &pipe_config->dp_m2_n2); |
|
- | 931 | } |
|
- | 932 | ||
- | 933 | if (HAS_DDI(dev)) |
|
- | 934 | hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); |
|
893 | 935 | else |
|
894 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
936 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
895 | 937 | ||
896 | return true; |
938 | return true; |
897 | } |
939 | } |
898 | 940 | ||
899 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
941 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
900 | { |
942 | { |
901 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
943 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
902 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
944 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
903 | struct drm_device *dev = crtc->base.dev; |
945 | struct drm_device *dev = crtc->base.dev; |
904 | struct drm_i915_private *dev_priv = dev->dev_private; |
946 | struct drm_i915_private *dev_priv = dev->dev_private; |
905 | u32 dpa_ctl; |
947 | u32 dpa_ctl; |
906 | 948 | ||
907 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
949 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
908 | dpa_ctl = I915_READ(DP_A); |
950 | dpa_ctl = I915_READ(DP_A); |
909 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
951 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
910 | 952 | ||
911 | if (crtc->config.port_clock == 162000) { |
953 | if (crtc->config.port_clock == 162000) { |
912 | /* For a long time we've carried around a ILK-DevA w/a for the |
954 | /* For a long time we've carried around a ILK-DevA w/a for the |
913 | * 160MHz clock. If we're really unlucky, it's still required. |
955 | * 160MHz clock. If we're really unlucky, it's still required. |
914 | */ |
956 | */ |
915 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
957 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
916 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
958 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
917 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
959 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
918 | } else { |
960 | } else { |
919 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
961 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
920 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
962 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
921 | } |
963 | } |
922 | 964 | ||
923 | I915_WRITE(DP_A, dpa_ctl); |
965 | I915_WRITE(DP_A, dpa_ctl); |
924 | 966 | ||
925 | POSTING_READ(DP_A); |
967 | POSTING_READ(DP_A); |
926 | udelay(500); |
968 | udelay(500); |
927 | } |
969 | } |
928 | 970 | ||
929 | static void intel_dp_mode_set(struct intel_encoder *encoder) |
971 | static void intel_dp_prepare(struct intel_encoder *encoder) |
930 | { |
972 | { |
931 | struct drm_device *dev = encoder->base.dev; |
973 | struct drm_device *dev = encoder->base.dev; |
932 | struct drm_i915_private *dev_priv = dev->dev_private; |
974 | struct drm_i915_private *dev_priv = dev->dev_private; |
933 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
975 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
934 | enum port port = dp_to_dig_port(intel_dp)->port; |
976 | enum port port = dp_to_dig_port(intel_dp)->port; |
935 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
977 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
936 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
978 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
937 | 979 | ||
938 | /* |
980 | /* |
939 | * There are four kinds of DP registers: |
981 | * There are four kinds of DP registers: |
940 | * |
982 | * |
941 | * IBX PCH |
983 | * IBX PCH |
942 | * SNB CPU |
984 | * SNB CPU |
943 | * IVB CPU |
985 | * IVB CPU |
944 | * CPT PCH |
986 | * CPT PCH |
945 | * |
987 | * |
946 | * IBX PCH and CPU are the same for almost everything, |
988 | * IBX PCH and CPU are the same for almost everything, |
947 | * except that the CPU DP PLL is configured in this |
989 | * except that the CPU DP PLL is configured in this |
948 | * register |
990 | * register |
949 | * |
991 | * |
950 | * CPT PCH is quite different, having many bits moved |
992 | * CPT PCH is quite different, having many bits moved |
951 | * to the TRANS_DP_CTL register instead. That |
993 | * to the TRANS_DP_CTL register instead. That |
952 | * configuration happens (oddly) in ironlake_pch_enable |
994 | * configuration happens (oddly) in ironlake_pch_enable |
953 | */ |
995 | */ |
954 | 996 | ||
955 | /* Preserve the BIOS-computed detected bit. This is |
997 | /* Preserve the BIOS-computed detected bit. This is |
956 | * supposed to be read-only. |
998 | * supposed to be read-only. |
957 | */ |
999 | */ |
958 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
1000 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
959 | 1001 | ||
960 | /* Handle DP bits in common between all three register formats */ |
1002 | /* Handle DP bits in common between all three register formats */ |
961 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
1003 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
962 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
1004 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
963 | 1005 | ||
964 | if (intel_dp->has_audio) { |
1006 | if (crtc->config.has_audio) { |
965 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
1007 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
966 | pipe_name(crtc->pipe)); |
1008 | pipe_name(crtc->pipe)); |
967 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
1009 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
968 | intel_write_eld(&encoder->base, adjusted_mode); |
1010 | intel_write_eld(&encoder->base, adjusted_mode); |
969 | } |
1011 | } |
970 | 1012 | ||
971 | /* Split out the IBX/CPU vs CPT settings */ |
1013 | /* Split out the IBX/CPU vs CPT settings */ |
972 | 1014 | ||
973 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1015 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
974 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1016 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
975 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1017 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
976 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1018 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
977 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1019 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
978 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1020 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
979 | 1021 | ||
980 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1022 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
981 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1023 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
982 | 1024 | ||
983 | intel_dp->DP |= crtc->pipe << 29; |
1025 | intel_dp->DP |= crtc->pipe << 29; |
984 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
1026 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
985 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
1027 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
986 | intel_dp->DP |= intel_dp->color_range; |
1028 | intel_dp->DP |= intel_dp->color_range; |
987 | 1029 | ||
988 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1030 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
989 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1031 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
990 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1032 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
991 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1033 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
992 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
1034 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
993 | 1035 | ||
994 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1036 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
995 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1037 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
- | 1038 | ||
996 | 1039 | if (!IS_CHERRYVIEW(dev)) { |
|
997 | if (crtc->pipe == 1) |
1040 | if (crtc->pipe == 1) |
998 | intel_dp->DP |= DP_PIPEB_SELECT; |
1041 | intel_dp->DP |= DP_PIPEB_SELECT; |
999 | } else { |
1042 | } else { |
- | 1043 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
|
- | 1044 | } |
|
- | 1045 | } else { |
|
1000 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1046 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1001 | } |
1047 | } |
1002 | - | ||
1003 | if (port == PORT_A && !IS_VALLEYVIEW(dev)) |
- | |
1004 | ironlake_set_pll_cpu_edp(intel_dp); |
- | |
1005 | } |
1048 | } |
1006 | 1049 | ||
1007 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1050 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1008 | #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
1051 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
1009 | 1052 | ||
1010 | #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1053 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1011 | #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1054 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
1012 | 1055 | ||
1013 | #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1056 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1014 | #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1057 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1015 | 1058 | ||
1016 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, |
1059 | static void wait_panel_status(struct intel_dp *intel_dp, |
1017 | u32 mask, |
1060 | u32 mask, |
1018 | u32 value) |
1061 | u32 value) |
1019 | { |
1062 | { |
1020 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1063 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1021 | struct drm_i915_private *dev_priv = dev->dev_private; |
1064 | struct drm_i915_private *dev_priv = dev->dev_private; |
1022 | u32 pp_stat_reg, pp_ctrl_reg; |
1065 | u32 pp_stat_reg, pp_ctrl_reg; |
1023 | 1066 | ||
1024 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1067 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1025 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1068 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1026 | 1069 | ||
1027 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
1070 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
1028 | mask, value, |
1071 | mask, value, |
1029 | I915_READ(pp_stat_reg), |
1072 | I915_READ(pp_stat_reg), |
1030 | I915_READ(pp_ctrl_reg)); |
1073 | I915_READ(pp_ctrl_reg)); |
1031 | 1074 | ||
1032 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
1075 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
1033 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
1076 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
1034 | I915_READ(pp_stat_reg), |
1077 | I915_READ(pp_stat_reg), |
1035 | I915_READ(pp_ctrl_reg)); |
1078 | I915_READ(pp_ctrl_reg)); |
1036 | } |
1079 | } |
1037 | 1080 | ||
1038 | DRM_DEBUG_KMS("Wait complete\n"); |
1081 | DRM_DEBUG_KMS("Wait complete\n"); |
1039 | } |
1082 | } |
1040 | 1083 | ||
1041 | static void ironlake_wait_panel_on(struct intel_dp *intel_dp) |
1084 | static void wait_panel_on(struct intel_dp *intel_dp) |
1042 | { |
1085 | { |
1043 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
1086 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
1044 | ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
1087 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
1045 | } |
1088 | } |
1046 | 1089 | ||
1047 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
1090 | static void wait_panel_off(struct intel_dp *intel_dp) |
1048 | { |
1091 | { |
1049 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
1092 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
1050 | ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
1093 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
1051 | } |
1094 | } |
1052 | 1095 | ||
- | 1096 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
|
- | 1097 | { |
|
- | 1098 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
|
- | 1099 | ||
- | 1100 | /* When we disable the VDD override bit last we have to do the manual |
|
- | 1101 | * wait. */ |
|
1053 | static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) |
1102 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
1054 | { |
1103 | intel_dp->panel_power_cycle_delay); |
- | 1104 | ||
- | 1105 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
|
- | 1106 | } |
|
- | 1107 | ||
- | 1108 | static void wait_backlight_on(struct intel_dp *intel_dp) |
|
- | 1109 | { |
|
- | 1110 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
|
- | 1111 | intel_dp->backlight_on_delay); |
|
- | 1112 | } |
|
- | 1113 | ||
- | 1114 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
|
1055 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
1115 | { |
1056 | ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
1116 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
1057 | } |
1117 | intel_dp->backlight_off_delay); |
1058 | 1118 | } |
|
1059 | 1119 | ||
1060 | /* Read the current pp_control value, unlocking the register if it |
1120 | /* Read the current pp_control value, unlocking the register if it |
1061 | * is locked |
1121 | * is locked |
1062 | */ |
1122 | */ |
1063 | 1123 | ||
1064 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
1124 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
1065 | { |
1125 | { |
1066 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1126 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1067 | struct drm_i915_private *dev_priv = dev->dev_private; |
1127 | struct drm_i915_private *dev_priv = dev->dev_private; |
1068 | u32 control; |
1128 | u32 control; |
1069 | 1129 | ||
1070 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
1130 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
1071 | control &= ~PANEL_UNLOCK_MASK; |
1131 | control &= ~PANEL_UNLOCK_MASK; |
1072 | control |= PANEL_UNLOCK_REGS; |
1132 | control |= PANEL_UNLOCK_REGS; |
1073 | return control; |
1133 | return control; |
1074 | } |
1134 | } |
1075 | 1135 | ||
1076 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1136 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) |
1077 | { |
1137 | { |
- | 1138 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 1139 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
1078 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1140 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
- | 1141 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
1079 | struct drm_i915_private *dev_priv = dev->dev_private; |
1142 | enum intel_display_power_domain power_domain; |
1080 | u32 pp; |
1143 | u32 pp; |
- | 1144 | u32 pp_stat_reg, pp_ctrl_reg; |
|
1081 | u32 pp_stat_reg, pp_ctrl_reg; |
1145 | bool need_to_disable = !intel_dp->want_panel_vdd; |
1082 | 1146 | ||
1083 | if (!is_edp(intel_dp)) |
- | |
1084 | return; |
- | |
1085 | - | ||
1086 | WARN(intel_dp->want_panel_vdd, |
1147 | if (!is_edp(intel_dp)) |
1087 | "eDP VDD already requested on\n"); |
1148 | return false; |
1088 | 1149 | ||
1089 | intel_dp->want_panel_vdd = true; |
1150 | intel_dp->want_panel_vdd = true; |
1090 | 1151 | ||
1091 | if (ironlake_edp_have_panel_vdd(intel_dp)) |
1152 | if (edp_have_panel_vdd(intel_dp)) |
- | 1153 | return need_to_disable; |
|
1092 | return; |
1154 | |
1093 | 1155 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
1094 | intel_runtime_pm_get(dev_priv); |
1156 | intel_display_power_get(dev_priv, power_domain); |
1095 | 1157 | ||
1096 | DRM_DEBUG_KMS("Turning eDP VDD on\n"); |
1158 | DRM_DEBUG_KMS("Turning eDP VDD on\n"); |
1097 | 1159 | ||
1098 | if (!ironlake_edp_have_panel_power(intel_dp)) |
1160 | if (!edp_have_panel_power(intel_dp)) |
1099 | ironlake_wait_panel_power_cycle(intel_dp); |
1161 | wait_panel_power_cycle(intel_dp); |
1100 | 1162 | ||
1101 | pp = ironlake_get_pp_control(intel_dp); |
1163 | pp = ironlake_get_pp_control(intel_dp); |
1102 | pp |= EDP_FORCE_VDD; |
1164 | pp |= EDP_FORCE_VDD; |
1103 | 1165 | ||
1104 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1166 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1105 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1167 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1106 | 1168 | ||
1107 | I915_WRITE(pp_ctrl_reg, pp); |
1169 | I915_WRITE(pp_ctrl_reg, pp); |
1108 | POSTING_READ(pp_ctrl_reg); |
1170 | POSTING_READ(pp_ctrl_reg); |
1109 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1171 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1110 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1172 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1111 | /* |
1173 | /* |
1112 | * If the panel wasn't on, delay before accessing aux channel |
1174 | * If the panel wasn't on, delay before accessing aux channel |
1113 | */ |
1175 | */ |
1114 | if (!ironlake_edp_have_panel_power(intel_dp)) { |
1176 | if (!edp_have_panel_power(intel_dp)) { |
1115 | DRM_DEBUG_KMS("eDP was not running\n"); |
1177 | DRM_DEBUG_KMS("eDP was not running\n"); |
1116 | msleep(intel_dp->panel_power_up_delay); |
1178 | msleep(intel_dp->panel_power_up_delay); |
1117 | } |
1179 | } |
- | 1180 | ||
- | 1181 | return need_to_disable; |
|
1118 | } |
1182 | } |
- | 1183 | ||
- | 1184 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
|
- | 1185 | { |
|
- | 1186 | if (is_edp(intel_dp)) { |
|
- | 1187 | bool vdd = _edp_panel_vdd_on(intel_dp); |
|
- | 1188 | ||
- | 1189 | WARN(!vdd, "eDP VDD already requested on\n"); |
|
- | 1190 | } |
|
- | 1191 | } |
|
1119 | 1192 | ||
1120 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1193 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1121 | { |
1194 | { |
1122 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1195 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1123 | struct drm_i915_private *dev_priv = dev->dev_private; |
1196 | struct drm_i915_private *dev_priv = dev->dev_private; |
1124 | u32 pp; |
1197 | u32 pp; |
1125 | u32 pp_stat_reg, pp_ctrl_reg; |
1198 | u32 pp_stat_reg, pp_ctrl_reg; |
1126 | 1199 | ||
- | 1200 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
|
- | 1201 | ||
- | 1202 | if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { |
|
- | 1203 | struct intel_digital_port *intel_dig_port = |
|
- | 1204 | dp_to_dig_port(intel_dp); |
|
- | 1205 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
1127 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
- | |
1128 | 1206 | enum intel_display_power_domain power_domain; |
|
1129 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
1207 | |
1130 | DRM_DEBUG_KMS("Turning eDP VDD off\n"); |
1208 | DRM_DEBUG_KMS("Turning eDP VDD off\n"); |
1131 | 1209 | ||
1132 | pp = ironlake_get_pp_control(intel_dp); |
1210 | pp = ironlake_get_pp_control(intel_dp); |
1133 | pp &= ~EDP_FORCE_VDD; |
1211 | pp &= ~EDP_FORCE_VDD; |
1134 | 1212 | ||
1135 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1213 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1136 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1214 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1137 | 1215 | ||
1138 | I915_WRITE(pp_ctrl_reg, pp); |
1216 | I915_WRITE(pp_ctrl_reg, pp); |
1139 | POSTING_READ(pp_ctrl_reg); |
1217 | POSTING_READ(pp_ctrl_reg); |
1140 | 1218 | ||
1141 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1219 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1142 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1220 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1143 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1221 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1144 | 1222 | ||
1145 | if ((pp & POWER_TARGET_ON) == 0) |
1223 | if ((pp & POWER_TARGET_ON) == 0) |
1146 | msleep(intel_dp->panel_power_cycle_delay); |
1224 | intel_dp->last_power_cycle = jiffies; |
- | 1225 | ||
1147 | 1226 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
1148 | intel_runtime_pm_put(dev_priv); |
1227 | intel_display_power_put(dev_priv, power_domain); |
1149 | } |
1228 | } |
1150 | } |
1229 | } |
1151 | 1230 | ||
1152 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
1231 | static void edp_panel_vdd_work(struct work_struct *__work) |
1153 | { |
1232 | { |
1154 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
1233 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
1155 | struct intel_dp, panel_vdd_work); |
1234 | struct intel_dp, panel_vdd_work); |
1156 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1235 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1157 | 1236 | ||
1158 | mutex_lock(&dev->mode_config.mutex); |
1237 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
1159 | ironlake_panel_vdd_off_sync(intel_dp); |
1238 | edp_panel_vdd_off_sync(intel_dp); |
- | 1239 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
|
- | 1240 | } |
|
- | 1241 | ||
- | 1242 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
|
- | 1243 | { |
|
- | 1244 | unsigned long delay; |
|
- | 1245 | ||
- | 1246 | /* |
|
- | 1247 | * Queue the timer to fire a long time from now (relative to the power |
|
- | 1248 | * down delay) to keep the panel power up across a sequence of |
|
- | 1249 | * operations. |
|
- | 1250 | */ |
|
- | 1251 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
|
1160 | mutex_unlock(&dev->mode_config.mutex); |
1252 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
1161 | } |
1253 | } |
1162 | 1254 | ||
1163 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
1255 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
1164 | { |
1256 | { |
1165 | if (!is_edp(intel_dp)) |
1257 | if (!is_edp(intel_dp)) |
1166 | return; |
1258 | return; |
1167 | 1259 | ||
1168 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
1260 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
1169 | 1261 | ||
1170 | intel_dp->want_panel_vdd = false; |
1262 | intel_dp->want_panel_vdd = false; |
1171 | 1263 | ||
1172 | if (sync) { |
1264 | if (sync) |
1173 | ironlake_panel_vdd_off_sync(intel_dp); |
1265 | edp_panel_vdd_off_sync(intel_dp); |
1174 | } else { |
- | |
1175 | /* |
- | |
1176 | * Queue the timer to fire a long |
- | |
1177 | * time from now (relative to the power down delay) |
- | |
1178 | * to keep the panel power up across a sequence of operations |
- | |
1179 | */ |
1266 | else |
1180 | schedule_delayed_work(&intel_dp->panel_vdd_work, |
- | |
1181 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
- | |
1182 | } |
1267 | edp_panel_vdd_schedule_off(intel_dp); |
1183 | } |
1268 | } |
1184 | 1269 | ||
1185 | void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
1270 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
1186 | { |
1271 | { |
1187 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1272 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1188 | struct drm_i915_private *dev_priv = dev->dev_private; |
1273 | struct drm_i915_private *dev_priv = dev->dev_private; |
1189 | u32 pp; |
1274 | u32 pp; |
1190 | u32 pp_ctrl_reg; |
1275 | u32 pp_ctrl_reg; |
1191 | 1276 | ||
1192 | if (!is_edp(intel_dp)) |
1277 | if (!is_edp(intel_dp)) |
1193 | return; |
1278 | return; |
1194 | 1279 | ||
1195 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
1280 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
1196 | 1281 | ||
1197 | if (ironlake_edp_have_panel_power(intel_dp)) { |
1282 | if (edp_have_panel_power(intel_dp)) { |
1198 | DRM_DEBUG_KMS("eDP power already on\n"); |
1283 | DRM_DEBUG_KMS("eDP power already on\n"); |
1199 | return; |
1284 | return; |
1200 | } |
1285 | } |
1201 | 1286 | ||
1202 | ironlake_wait_panel_power_cycle(intel_dp); |
1287 | wait_panel_power_cycle(intel_dp); |
1203 | 1288 | ||
1204 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1289 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1205 | pp = ironlake_get_pp_control(intel_dp); |
1290 | pp = ironlake_get_pp_control(intel_dp); |
1206 | if (IS_GEN5(dev)) { |
1291 | if (IS_GEN5(dev)) { |
1207 | /* ILK workaround: disable reset around power sequence */ |
1292 | /* ILK workaround: disable reset around power sequence */ |
1208 | pp &= ~PANEL_POWER_RESET; |
1293 | pp &= ~PANEL_POWER_RESET; |
1209 | I915_WRITE(pp_ctrl_reg, pp); |
1294 | I915_WRITE(pp_ctrl_reg, pp); |
1210 | POSTING_READ(pp_ctrl_reg); |
1295 | POSTING_READ(pp_ctrl_reg); |
1211 | } |
1296 | } |
1212 | 1297 | ||
1213 | pp |= POWER_TARGET_ON; |
1298 | pp |= POWER_TARGET_ON; |
1214 | if (!IS_GEN5(dev)) |
1299 | if (!IS_GEN5(dev)) |
1215 | pp |= PANEL_POWER_RESET; |
1300 | pp |= PANEL_POWER_RESET; |
1216 | 1301 | ||
1217 | I915_WRITE(pp_ctrl_reg, pp); |
1302 | I915_WRITE(pp_ctrl_reg, pp); |
1218 | POSTING_READ(pp_ctrl_reg); |
1303 | POSTING_READ(pp_ctrl_reg); |
1219 | 1304 | ||
- | 1305 | wait_panel_on(intel_dp); |
|
1220 | ironlake_wait_panel_on(intel_dp); |
1306 | intel_dp->last_power_on = jiffies; |
1221 | 1307 | ||
1222 | if (IS_GEN5(dev)) { |
1308 | if (IS_GEN5(dev)) { |
1223 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1309 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1224 | I915_WRITE(pp_ctrl_reg, pp); |
1310 | I915_WRITE(pp_ctrl_reg, pp); |
1225 | POSTING_READ(pp_ctrl_reg); |
1311 | POSTING_READ(pp_ctrl_reg); |
1226 | } |
1312 | } |
1227 | } |
1313 | } |
1228 | 1314 | ||
1229 | void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
1315 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
- | 1316 | { |
|
- | 1317 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
1230 | { |
1318 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1231 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1319 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | 1320 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
1232 | struct drm_i915_private *dev_priv = dev->dev_private; |
1321 | enum intel_display_power_domain power_domain; |
1233 | u32 pp; |
1322 | u32 pp; |
1234 | u32 pp_ctrl_reg; |
1323 | u32 pp_ctrl_reg; |
1235 | 1324 | ||
1236 | if (!is_edp(intel_dp)) |
1325 | if (!is_edp(intel_dp)) |
1237 | return; |
1326 | return; |
1238 | 1327 | ||
1239 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
1328 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
- | 1329 | ||
- | 1330 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
|
1240 | 1331 | ||
1241 | pp = ironlake_get_pp_control(intel_dp); |
1332 | pp = ironlake_get_pp_control(intel_dp); |
1242 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1333 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1243 | * panels get very unhappy and cease to work. */ |
1334 | * panels get very unhappy and cease to work. */ |
1244 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE); |
1335 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
- | 1336 | EDP_BLC_ENABLE); |
|
1245 | 1337 | ||
1246 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1338 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
- | 1339 | ||
- | 1340 | intel_dp->want_panel_vdd = false; |
|
1247 | 1341 | ||
1248 | I915_WRITE(pp_ctrl_reg, pp); |
1342 | I915_WRITE(pp_ctrl_reg, pp); |
1249 | POSTING_READ(pp_ctrl_reg); |
1343 | POSTING_READ(pp_ctrl_reg); |
- | 1344 | ||
1250 | 1345 | intel_dp->last_power_cycle = jiffies; |
|
- | 1346 | wait_panel_off(intel_dp); |
|
- | 1347 | ||
- | 1348 | /* We got a reference when we enabled the VDD. */ |
|
- | 1349 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
1251 | ironlake_wait_panel_off(intel_dp); |
1350 | intel_display_power_put(dev_priv, power_domain); |
1252 | } |
1351 | } |
1253 | 1352 | ||
1254 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
1353 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
1255 | { |
1354 | { |
1256 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1355 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1257 | struct drm_device *dev = intel_dig_port->base.base.dev; |
1356 | struct drm_device *dev = intel_dig_port->base.base.dev; |
1258 | struct drm_i915_private *dev_priv = dev->dev_private; |
1357 | struct drm_i915_private *dev_priv = dev->dev_private; |
1259 | u32 pp; |
1358 | u32 pp; |
1260 | u32 pp_ctrl_reg; |
1359 | u32 pp_ctrl_reg; |
1261 | 1360 | ||
1262 | if (!is_edp(intel_dp)) |
1361 | if (!is_edp(intel_dp)) |
1263 | return; |
1362 | return; |
1264 | 1363 | ||
1265 | DRM_DEBUG_KMS("\n"); |
1364 | DRM_DEBUG_KMS("\n"); |
- | 1365 | ||
- | 1366 | intel_panel_enable_backlight(intel_dp->attached_connector); |
|
- | 1367 | ||
1266 | /* |
1368 | /* |
1267 | * If we enable the backlight right away following a panel power |
1369 | * If we enable the backlight right away following a panel power |
1268 | * on, we may see slight flicker as the panel syncs with the eDP |
1370 | * on, we may see slight flicker as the panel syncs with the eDP |
1269 | * link. So delay a bit to make sure the image is solid before |
1371 | * link. So delay a bit to make sure the image is solid before |
1270 | * allowing it to appear. |
1372 | * allowing it to appear. |
1271 | */ |
1373 | */ |
1272 | msleep(intel_dp->backlight_on_delay); |
1374 | wait_backlight_on(intel_dp); |
1273 | pp = ironlake_get_pp_control(intel_dp); |
1375 | pp = ironlake_get_pp_control(intel_dp); |
1274 | pp |= EDP_BLC_ENABLE; |
1376 | pp |= EDP_BLC_ENABLE; |
1275 | 1377 | ||
1276 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1378 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1277 | 1379 | ||
1278 | I915_WRITE(pp_ctrl_reg, pp); |
1380 | I915_WRITE(pp_ctrl_reg, pp); |
1279 | POSTING_READ(pp_ctrl_reg); |
1381 | POSTING_READ(pp_ctrl_reg); |
1280 | - | ||
1281 | intel_panel_enable_backlight(intel_dp->attached_connector); |
- | |
1282 | } |
1382 | } |
1283 | 1383 | ||
1284 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
1384 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
1285 | { |
1385 | { |
1286 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1386 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1287 | struct drm_i915_private *dev_priv = dev->dev_private; |
1387 | struct drm_i915_private *dev_priv = dev->dev_private; |
1288 | u32 pp; |
1388 | u32 pp; |
1289 | u32 pp_ctrl_reg; |
1389 | u32 pp_ctrl_reg; |
1290 | 1390 | ||
1291 | if (!is_edp(intel_dp)) |
1391 | if (!is_edp(intel_dp)) |
1292 | return; |
1392 | return; |
1293 | - | ||
1294 | intel_panel_disable_backlight(intel_dp->attached_connector); |
- | |
1295 | 1393 | ||
1296 | DRM_DEBUG_KMS("\n"); |
1394 | DRM_DEBUG_KMS("\n"); |
1297 | pp = ironlake_get_pp_control(intel_dp); |
1395 | pp = ironlake_get_pp_control(intel_dp); |
1298 | pp &= ~EDP_BLC_ENABLE; |
1396 | pp &= ~EDP_BLC_ENABLE; |
1299 | 1397 | ||
1300 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1398 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1301 | 1399 | ||
1302 | I915_WRITE(pp_ctrl_reg, pp); |
1400 | I915_WRITE(pp_ctrl_reg, pp); |
1303 | POSTING_READ(pp_ctrl_reg); |
1401 | POSTING_READ(pp_ctrl_reg); |
1304 | msleep(intel_dp->backlight_off_delay); |
1402 | intel_dp->last_backlight_off = jiffies; |
- | 1403 | ||
- | 1404 | edp_wait_backlight_off(intel_dp); |
|
- | 1405 | ||
- | 1406 | intel_panel_disable_backlight(intel_dp->attached_connector); |
|
1305 | } |
1407 | } |
1306 | 1408 | ||
1307 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
1409 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
1308 | { |
1410 | { |
1309 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1411 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1310 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
1412 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
1311 | struct drm_device *dev = crtc->dev; |
1413 | struct drm_device *dev = crtc->dev; |
1312 | struct drm_i915_private *dev_priv = dev->dev_private; |
1414 | struct drm_i915_private *dev_priv = dev->dev_private; |
1313 | u32 dpa_ctl; |
1415 | u32 dpa_ctl; |
1314 | 1416 | ||
1315 | assert_pipe_disabled(dev_priv, |
1417 | assert_pipe_disabled(dev_priv, |
1316 | to_intel_crtc(crtc)->pipe); |
1418 | to_intel_crtc(crtc)->pipe); |
1317 | 1419 | ||
1318 | DRM_DEBUG_KMS("\n"); |
1420 | DRM_DEBUG_KMS("\n"); |
1319 | dpa_ctl = I915_READ(DP_A); |
1421 | dpa_ctl = I915_READ(DP_A); |
1320 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1422 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1321 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
1423 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
1322 | 1424 | ||
1323 | /* We don't adjust intel_dp->DP while tearing down the link, to |
1425 | /* We don't adjust intel_dp->DP while tearing down the link, to |
1324 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
1426 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
1325 | * enable bits here to ensure that we don't enable too much. */ |
1427 | * enable bits here to ensure that we don't enable too much. */ |
1326 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
1428 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
1327 | intel_dp->DP |= DP_PLL_ENABLE; |
1429 | intel_dp->DP |= DP_PLL_ENABLE; |
1328 | I915_WRITE(DP_A, intel_dp->DP); |
1430 | I915_WRITE(DP_A, intel_dp->DP); |
1329 | POSTING_READ(DP_A); |
1431 | POSTING_READ(DP_A); |
1330 | udelay(200); |
1432 | udelay(200); |
1331 | } |
1433 | } |
1332 | 1434 | ||
1333 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
1435 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
1334 | { |
1436 | { |
1335 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1437 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1336 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
1438 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
1337 | struct drm_device *dev = crtc->dev; |
1439 | struct drm_device *dev = crtc->dev; |
1338 | struct drm_i915_private *dev_priv = dev->dev_private; |
1440 | struct drm_i915_private *dev_priv = dev->dev_private; |
1339 | u32 dpa_ctl; |
1441 | u32 dpa_ctl; |
1340 | 1442 | ||
1341 | assert_pipe_disabled(dev_priv, |
1443 | assert_pipe_disabled(dev_priv, |
1342 | to_intel_crtc(crtc)->pipe); |
1444 | to_intel_crtc(crtc)->pipe); |
1343 | 1445 | ||
1344 | dpa_ctl = I915_READ(DP_A); |
1446 | dpa_ctl = I915_READ(DP_A); |
1345 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1447 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1346 | "dp pll off, should be on\n"); |
1448 | "dp pll off, should be on\n"); |
1347 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
1449 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
1348 | 1450 | ||
1349 | /* We can't rely on the value tracked for the DP register in |
1451 | /* We can't rely on the value tracked for the DP register in |
1350 | * intel_dp->DP because link_down must not change that (otherwise link |
1452 | * intel_dp->DP because link_down must not change that (otherwise link |
1351 | * re-training will fail. */ |
1453 | * re-training will fail. */ |
1352 | dpa_ctl &= ~DP_PLL_ENABLE; |
1454 | dpa_ctl &= ~DP_PLL_ENABLE; |
1353 | I915_WRITE(DP_A, dpa_ctl); |
1455 | I915_WRITE(DP_A, dpa_ctl); |
1354 | POSTING_READ(DP_A); |
1456 | POSTING_READ(DP_A); |
1355 | udelay(200); |
1457 | udelay(200); |
1356 | } |
1458 | } |
1357 | 1459 | ||
1358 | /* If the sink supports it, try to set the power state appropriately */ |
1460 | /* If the sink supports it, try to set the power state appropriately */ |
1359 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
1461 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
1360 | { |
1462 | { |
1361 | int ret, i; |
1463 | int ret, i; |
1362 | 1464 | ||
1363 | /* Should have a valid DPCD by this point */ |
1465 | /* Should have a valid DPCD by this point */ |
1364 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
1466 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
1365 | return; |
1467 | return; |
1366 | 1468 | ||
1367 | if (mode != DRM_MODE_DPMS_ON) { |
1469 | if (mode != DRM_MODE_DPMS_ON) { |
1368 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, |
1470 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1369 | DP_SET_POWER_D3); |
1471 | DP_SET_POWER_D3); |
1370 | if (ret != 1) |
1472 | if (ret != 1) |
1371 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
1473 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
1372 | } else { |
1474 | } else { |
1373 | /* |
1475 | /* |
1374 | * When turning on, we need to retry for 1ms to give the sink |
1476 | * When turning on, we need to retry for 1ms to give the sink |
1375 | * time to wake up. |
1477 | * time to wake up. |
1376 | */ |
1478 | */ |
1377 | for (i = 0; i < 3; i++) { |
1479 | for (i = 0; i < 3; i++) { |
1378 | ret = intel_dp_aux_native_write_1(intel_dp, |
1480 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1379 | DP_SET_POWER, |
- | |
1380 | DP_SET_POWER_D0); |
1481 | DP_SET_POWER_D0); |
1381 | if (ret == 1) |
1482 | if (ret == 1) |
1382 | break; |
1483 | break; |
1383 | msleep(1); |
1484 | msleep(1); |
1384 | } |
1485 | } |
1385 | } |
1486 | } |
1386 | } |
1487 | } |
1387 | 1488 | ||
1388 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1489 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1389 | enum pipe *pipe) |
1490 | enum pipe *pipe) |
1390 | { |
1491 | { |
1391 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1492 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1392 | enum port port = dp_to_dig_port(intel_dp)->port; |
1493 | enum port port = dp_to_dig_port(intel_dp)->port; |
1393 | struct drm_device *dev = encoder->base.dev; |
1494 | struct drm_device *dev = encoder->base.dev; |
1394 | struct drm_i915_private *dev_priv = dev->dev_private; |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 1496 | enum intel_display_power_domain power_domain; |
|
- | 1497 | u32 tmp; |
|
- | 1498 | ||
- | 1499 | power_domain = intel_display_port_power_domain(encoder); |
|
- | 1500 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
|
- | 1501 | return false; |
|
- | 1502 | ||
1395 | u32 tmp = I915_READ(intel_dp->output_reg); |
1503 | tmp = I915_READ(intel_dp->output_reg); |
1396 | 1504 | ||
1397 | if (!(tmp & DP_PORT_EN)) |
1505 | if (!(tmp & DP_PORT_EN)) |
1398 | return false; |
1506 | return false; |
1399 | 1507 | ||
1400 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1508 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1401 | *pipe = PORT_TO_PIPE_CPT(tmp); |
1509 | *pipe = PORT_TO_PIPE_CPT(tmp); |
- | 1510 | } else if (IS_CHERRYVIEW(dev)) { |
|
- | 1511 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
|
1402 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
1512 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
1403 | *pipe = PORT_TO_PIPE(tmp); |
1513 | *pipe = PORT_TO_PIPE(tmp); |
1404 | } else { |
1514 | } else { |
1405 | u32 trans_sel; |
1515 | u32 trans_sel; |
1406 | u32 trans_dp; |
1516 | u32 trans_dp; |
1407 | int i; |
1517 | int i; |
1408 | 1518 | ||
1409 | switch (intel_dp->output_reg) { |
1519 | switch (intel_dp->output_reg) { |
1410 | case PCH_DP_B: |
1520 | case PCH_DP_B: |
1411 | trans_sel = TRANS_DP_PORT_SEL_B; |
1521 | trans_sel = TRANS_DP_PORT_SEL_B; |
1412 | break; |
1522 | break; |
1413 | case PCH_DP_C: |
1523 | case PCH_DP_C: |
1414 | trans_sel = TRANS_DP_PORT_SEL_C; |
1524 | trans_sel = TRANS_DP_PORT_SEL_C; |
1415 | break; |
1525 | break; |
1416 | case PCH_DP_D: |
1526 | case PCH_DP_D: |
1417 | trans_sel = TRANS_DP_PORT_SEL_D; |
1527 | trans_sel = TRANS_DP_PORT_SEL_D; |
1418 | break; |
1528 | break; |
1419 | default: |
1529 | default: |
1420 | return true; |
1530 | return true; |
1421 | } |
1531 | } |
1422 | 1532 | ||
1423 | for_each_pipe(i) { |
1533 | for_each_pipe(i) { |
1424 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
1534 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
1425 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
1535 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
1426 | *pipe = i; |
1536 | *pipe = i; |
1427 | return true; |
1537 | return true; |
1428 | } |
1538 | } |
1429 | } |
1539 | } |
1430 | 1540 | ||
1431 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
1541 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
1432 | intel_dp->output_reg); |
1542 | intel_dp->output_reg); |
1433 | } |
1543 | } |
1434 | 1544 | ||
1435 | return true; |
1545 | return true; |
1436 | } |
1546 | } |
1437 | 1547 | ||
1438 | static void intel_dp_get_config(struct intel_encoder *encoder, |
1548 | static void intel_dp_get_config(struct intel_encoder *encoder, |
1439 | struct intel_crtc_config *pipe_config) |
1549 | struct intel_crtc_config *pipe_config) |
1440 | { |
1550 | { |
1441 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1551 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1442 | u32 tmp, flags = 0; |
1552 | u32 tmp, flags = 0; |
1443 | struct drm_device *dev = encoder->base.dev; |
1553 | struct drm_device *dev = encoder->base.dev; |
1444 | struct drm_i915_private *dev_priv = dev->dev_private; |
1554 | struct drm_i915_private *dev_priv = dev->dev_private; |
1445 | enum port port = dp_to_dig_port(intel_dp)->port; |
1555 | enum port port = dp_to_dig_port(intel_dp)->port; |
1446 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1556 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1447 | int dotclock; |
1557 | int dotclock; |
1448 | - | ||
1449 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
1558 | |
- | 1559 | tmp = I915_READ(intel_dp->output_reg); |
|
- | 1560 | if (tmp & DP_AUDIO_OUTPUT_ENABLE) |
|
- | 1561 | pipe_config->has_audio = true; |
|
- | 1562 | ||
1450 | tmp = I915_READ(intel_dp->output_reg); |
1563 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
1451 | if (tmp & DP_SYNC_HS_HIGH) |
1564 | if (tmp & DP_SYNC_HS_HIGH) |
1452 | flags |= DRM_MODE_FLAG_PHSYNC; |
1565 | flags |= DRM_MODE_FLAG_PHSYNC; |
1453 | else |
1566 | else |
1454 | flags |= DRM_MODE_FLAG_NHSYNC; |
1567 | flags |= DRM_MODE_FLAG_NHSYNC; |
1455 | 1568 | ||
1456 | if (tmp & DP_SYNC_VS_HIGH) |
1569 | if (tmp & DP_SYNC_VS_HIGH) |
1457 | flags |= DRM_MODE_FLAG_PVSYNC; |
1570 | flags |= DRM_MODE_FLAG_PVSYNC; |
1458 | else |
1571 | else |
1459 | flags |= DRM_MODE_FLAG_NVSYNC; |
1572 | flags |= DRM_MODE_FLAG_NVSYNC; |
1460 | } else { |
1573 | } else { |
1461 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
1574 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
1462 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
1575 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
1463 | flags |= DRM_MODE_FLAG_PHSYNC; |
1576 | flags |= DRM_MODE_FLAG_PHSYNC; |
1464 | else |
1577 | else |
1465 | flags |= DRM_MODE_FLAG_NHSYNC; |
1578 | flags |= DRM_MODE_FLAG_NHSYNC; |
1466 | 1579 | ||
1467 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
1580 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
1468 | flags |= DRM_MODE_FLAG_PVSYNC; |
1581 | flags |= DRM_MODE_FLAG_PVSYNC; |
1469 | else |
1582 | else |
1470 | flags |= DRM_MODE_FLAG_NVSYNC; |
1583 | flags |= DRM_MODE_FLAG_NVSYNC; |
1471 | } |
1584 | } |
1472 | 1585 | ||
1473 | pipe_config->adjusted_mode.flags |= flags; |
1586 | pipe_config->adjusted_mode.flags |= flags; |
1474 | 1587 | ||
1475 | pipe_config->has_dp_encoder = true; |
1588 | pipe_config->has_dp_encoder = true; |
1476 | 1589 | ||
1477 | intel_dp_get_m_n(crtc, pipe_config); |
1590 | intel_dp_get_m_n(crtc, pipe_config); |
1478 | 1591 | ||
1479 | if (port == PORT_A) { |
1592 | if (port == PORT_A) { |
1480 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
1593 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
1481 | pipe_config->port_clock = 162000; |
1594 | pipe_config->port_clock = 162000; |
1482 | else |
1595 | else |
1483 | pipe_config->port_clock = 270000; |
1596 | pipe_config->port_clock = 270000; |
1484 | } |
1597 | } |
1485 | 1598 | ||
1486 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
1599 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
1487 | &pipe_config->dp_m_n); |
1600 | &pipe_config->dp_m_n); |
1488 | 1601 | ||
1489 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
1602 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
1490 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
1603 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
1491 | 1604 | ||
1492 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
1605 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
1493 | 1606 | ||
1494 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
1607 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
1495 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
1608 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
1496 | /* |
1609 | /* |
1497 | * This is a big fat ugly hack. |
1610 | * This is a big fat ugly hack. |
1498 | * |
1611 | * |
1499 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
1612 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
1500 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
1613 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
1501 | * unknown we fail to light up. Yet the same BIOS boots up with |
1614 | * unknown we fail to light up. Yet the same BIOS boots up with |
1502 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
1615 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
1503 | * max, not what it tells us to use. |
1616 | * max, not what it tells us to use. |
1504 | * |
1617 | * |
1505 | * Note: This will still be broken if the eDP panel is not lit |
1618 | * Note: This will still be broken if the eDP panel is not lit |
1506 | * up by the BIOS, and thus we can't get the mode at module |
1619 | * up by the BIOS, and thus we can't get the mode at module |
1507 | * load. |
1620 | * load. |
1508 | */ |
1621 | */ |
1509 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
1622 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
1510 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
1623 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
1511 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
1624 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
1512 | } |
1625 | } |
1513 | } |
1626 | } |
1514 | 1627 | ||
1515 | static bool is_edp_psr(struct drm_device *dev) |
1628 | static bool is_edp_psr(struct intel_dp *intel_dp) |
1516 | { |
- | |
1517 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
1518 | 1629 | { |
|
1519 | return dev_priv->psr.sink_support; |
1630 | return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; |
1520 | } |
1631 | } |
1521 | 1632 | ||
1522 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
1633 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
1523 | { |
1634 | { |
1524 | struct drm_i915_private *dev_priv = dev->dev_private; |
1635 | struct drm_i915_private *dev_priv = dev->dev_private; |
1525 | 1636 | ||
1526 | if (!HAS_PSR(dev)) |
1637 | if (!HAS_PSR(dev)) |
1527 | return false; |
1638 | return false; |
1528 | 1639 | ||
1529 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
1640 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
1530 | } |
1641 | } |
1531 | 1642 | ||
1532 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, |
1643 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, |
1533 | struct edp_vsc_psr *vsc_psr) |
1644 | struct edp_vsc_psr *vsc_psr) |
1534 | { |
1645 | { |
1535 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1646 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1536 | struct drm_device *dev = dig_port->base.base.dev; |
1647 | struct drm_device *dev = dig_port->base.base.dev; |
1537 | struct drm_i915_private *dev_priv = dev->dev_private; |
1648 | struct drm_i915_private *dev_priv = dev->dev_private; |
1538 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
1649 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
1539 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); |
1650 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); |
1540 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); |
1651 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); |
1541 | uint32_t *data = (uint32_t *) vsc_psr; |
1652 | uint32_t *data = (uint32_t *) vsc_psr; |
1542 | unsigned int i; |
1653 | unsigned int i; |
1543 | 1654 | ||
1544 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable |
1655 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable |
1545 | the video DIP being updated before program video DIP data buffer |
1656 | the video DIP being updated before program video DIP data buffer |
1546 | registers for DIP being updated. */ |
1657 | registers for DIP being updated. */ |
1547 | I915_WRITE(ctl_reg, 0); |
1658 | I915_WRITE(ctl_reg, 0); |
1548 | POSTING_READ(ctl_reg); |
1659 | POSTING_READ(ctl_reg); |
1549 | 1660 | ||
1550 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { |
1661 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { |
1551 | if (i < sizeof(struct edp_vsc_psr)) |
1662 | if (i < sizeof(struct edp_vsc_psr)) |
1552 | I915_WRITE(data_reg + i, *data++); |
1663 | I915_WRITE(data_reg + i, *data++); |
1553 | else |
1664 | else |
1554 | I915_WRITE(data_reg + i, 0); |
1665 | I915_WRITE(data_reg + i, 0); |
1555 | } |
1666 | } |
1556 | 1667 | ||
1557 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); |
1668 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); |
1558 | POSTING_READ(ctl_reg); |
1669 | POSTING_READ(ctl_reg); |
1559 | } |
1670 | } |
1560 | 1671 | ||
1561 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) |
1672 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) |
1562 | { |
1673 | { |
1563 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1674 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1564 | struct drm_i915_private *dev_priv = dev->dev_private; |
1675 | struct drm_i915_private *dev_priv = dev->dev_private; |
1565 | struct edp_vsc_psr psr_vsc; |
1676 | struct edp_vsc_psr psr_vsc; |
1566 | - | ||
1567 | if (intel_dp->psr_setup_done) |
- | |
1568 | return; |
- | |
1569 | 1677 | ||
1570 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
1678 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
1571 | memset(&psr_vsc, 0, sizeof(psr_vsc)); |
1679 | memset(&psr_vsc, 0, sizeof(psr_vsc)); |
1572 | psr_vsc.sdp_header.HB0 = 0; |
1680 | psr_vsc.sdp_header.HB0 = 0; |
1573 | psr_vsc.sdp_header.HB1 = 0x7; |
1681 | psr_vsc.sdp_header.HB1 = 0x7; |
1574 | psr_vsc.sdp_header.HB2 = 0x2; |
1682 | psr_vsc.sdp_header.HB2 = 0x2; |
1575 | psr_vsc.sdp_header.HB3 = 0x8; |
1683 | psr_vsc.sdp_header.HB3 = 0x8; |
1576 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); |
1684 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); |
1577 | 1685 | ||
1578 | /* Avoid continuous PSR exit by masking memup and hpd */ |
1686 | /* Avoid continuous PSR exit by masking memup and hpd */ |
1579 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
1687 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
1580 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
1688 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
1581 | - | ||
1582 | intel_dp->psr_setup_done = true; |
- | |
1583 | } |
1689 | } |
1584 | 1690 | ||
1585 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) |
1691 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) |
1586 | { |
1692 | { |
- | 1693 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
|
1587 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1694 | struct drm_device *dev = dig_port->base.base.dev; |
1588 | struct drm_i915_private *dev_priv = dev->dev_private; |
1695 | struct drm_i915_private *dev_priv = dev->dev_private; |
1589 | uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0); |
1696 | uint32_t aux_clock_divider; |
1590 | int precharge = 0x3; |
1697 | int precharge = 0x3; |
1591 | int msg_size = 5; /* Header(4) + Message(1) */ |
1698 | int msg_size = 5; /* Header(4) + Message(1) */ |
- | 1699 | bool only_standby = false; |
|
- | 1700 | ||
- | 1701 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
|
- | 1702 | ||
- | 1703 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) |
|
- | 1704 | only_standby = true; |
|
1592 | 1705 | ||
1593 | /* Enable PSR in sink */ |
1706 | /* Enable PSR in sink */ |
1594 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) |
1707 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) |
1595 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, |
- | |
1596 | DP_PSR_ENABLE & |
1708 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
1597 | ~DP_PSR_MAIN_LINK_ACTIVE); |
1709 | DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); |
1598 | else |
1710 | else |
1599 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, |
- | |
1600 | DP_PSR_ENABLE | |
1711 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
1601 | DP_PSR_MAIN_LINK_ACTIVE); |
1712 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
1602 | 1713 | ||
1603 | /* Setup AUX registers */ |
1714 | /* Setup AUX registers */ |
1604 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
1715 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
1605 | I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); |
1716 | I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); |
1606 | I915_WRITE(EDP_PSR_AUX_CTL(dev), |
1717 | I915_WRITE(EDP_PSR_AUX_CTL(dev), |
1607 | DP_AUX_CH_CTL_TIME_OUT_400us | |
1718 | DP_AUX_CH_CTL_TIME_OUT_400us | |
1608 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
1719 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
1609 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
1720 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
1610 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
1721 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
1611 | } |
1722 | } |
1612 | 1723 | ||
1613 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) |
1724 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) |
1614 | { |
1725 | { |
- | 1726 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
|
1615 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1727 | struct drm_device *dev = dig_port->base.base.dev; |
1616 | struct drm_i915_private *dev_priv = dev->dev_private; |
1728 | struct drm_i915_private *dev_priv = dev->dev_private; |
1617 | uint32_t max_sleep_time = 0x1f; |
1729 | uint32_t max_sleep_time = 0x1f; |
1618 | uint32_t idle_frames = 1; |
1730 | uint32_t idle_frames = 1; |
1619 | uint32_t val = 0x0; |
1731 | uint32_t val = 0x0; |
1620 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
1732 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
- | 1733 | bool only_standby = false; |
|
- | 1734 | ||
- | 1735 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) |
|
- | 1736 | only_standby = true; |
|
1621 | 1737 | ||
1622 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { |
1738 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) { |
1623 | val |= EDP_PSR_LINK_STANDBY; |
1739 | val |= EDP_PSR_LINK_STANDBY; |
1624 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
1740 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
1625 | val |= EDP_PSR_TP1_TIME_0us; |
1741 | val |= EDP_PSR_TP1_TIME_0us; |
1626 | val |= EDP_PSR_SKIP_AUX_EXIT; |
1742 | val |= EDP_PSR_SKIP_AUX_EXIT; |
- | 1743 | val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0; |
|
1627 | } else |
1744 | } else |
1628 | val |= EDP_PSR_LINK_DISABLE; |
1745 | val |= EDP_PSR_LINK_DISABLE; |
1629 | 1746 | ||
1630 | I915_WRITE(EDP_PSR_CTL(dev), val | |
1747 | I915_WRITE(EDP_PSR_CTL(dev), val | |
1631 | IS_BROADWELL(dev) ? 0 : link_entry_time | |
1748 | (IS_BROADWELL(dev) ? 0 : link_entry_time) | |
1632 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
1749 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
1633 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | |
1750 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | |
1634 | EDP_PSR_ENABLE); |
1751 | EDP_PSR_ENABLE); |
1635 | } |
1752 | } |
1636 | 1753 | ||
1637 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
1754 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
1638 | { |
1755 | { |
1639 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1756 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1640 | struct drm_device *dev = dig_port->base.base.dev; |
1757 | struct drm_device *dev = dig_port->base.base.dev; |
1641 | struct drm_i915_private *dev_priv = dev->dev_private; |
1758 | struct drm_i915_private *dev_priv = dev->dev_private; |
1642 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
1759 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
1643 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1644 | struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; |
- | |
1645 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
- | |
1646 | 1761 | ||
- | 1762 | lockdep_assert_held(&dev_priv->psr.lock); |
|
- | 1763 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
|
1647 | dev_priv->psr.source_ok = false; |
- | |
1648 | - | ||
1649 | if (!HAS_PSR(dev)) { |
1764 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
1650 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
- | |
1651 | return false; |
- | |
1652 | } |
1765 | |
1653 | 1766 | dev_priv->psr.source_ok = false; |
|
1654 | if ((intel_encoder->type != INTEL_OUTPUT_EDP) || |
1767 | |
1655 | (dig_port->port != PORT_A)) { |
1768 | if (IS_HASWELL(dev) && dig_port->port != PORT_A) { |
1656 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
1769 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
1657 | return false; |
1770 | return false; |
1658 | } |
1771 | } |
1659 | 1772 | ||
1660 | if (!i915_enable_psr) { |
1773 | if (!i915.enable_psr) { |
1661 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
1774 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
1662 | return false; |
1775 | return false; |
1663 | } |
1776 | } |
1664 | - | ||
1665 | crtc = dig_port->base.base.crtc; |
- | |
1666 | if (crtc == NULL) { |
1777 | |
1667 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
- | |
1668 | return false; |
- | |
1669 | } |
- | |
1670 | - | ||
1671 | intel_crtc = to_intel_crtc(crtc); |
1778 | /* Below limitations aren't valid for Broadwell */ |
1672 | if (!intel_crtc_active(crtc)) { |
- | |
1673 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
- | |
1674 | return false; |
- | |
1675 | } |
- | |
1676 | - | ||
1677 | obj = to_intel_framebuffer(crtc->fb)->obj; |
- | |
1678 | if (obj->tiling_mode != I915_TILING_X || |
- | |
1679 | obj->fence_reg == I915_FENCE_REG_NONE) { |
- | |
1680 | DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); |
- | |
1681 | return false; |
- | |
1682 | } |
- | |
1683 | - | ||
1684 | if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { |
- | |
1685 | DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); |
1779 | if (IS_BROADWELL(dev)) |
1686 | return false; |
- | |
1687 | } |
1780 | goto out; |
1688 | 1781 | ||
1689 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & |
1782 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & |
1690 | S3D_ENABLE) { |
1783 | S3D_ENABLE) { |
1691 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
1784 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
1692 | return false; |
1785 | return false; |
1693 | } |
1786 | } |
1694 | 1787 | ||
1695 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
1788 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
1696 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
1789 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
1697 | return false; |
1790 | return false; |
1698 | } |
1791 | } |
- | 1792 | ||
1699 | 1793 | out: |
|
1700 | dev_priv->psr.source_ok = true; |
1794 | dev_priv->psr.source_ok = true; |
1701 | return true; |
1795 | return true; |
1702 | } |
1796 | } |
1703 | 1797 | ||
1704 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
1798 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
1705 | { |
1799 | { |
1706 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1800 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1707 | - | ||
1708 | if (!intel_edp_psr_match_conditions(intel_dp) || |
1801 | struct drm_device *dev = intel_dig_port->base.base.dev; |
1709 | intel_edp_is_psr_enabled(dev)) |
1802 | struct drm_i915_private *dev_priv = dev->dev_private; |
1710 | return; |
- | |
- | 1803 | ||
1711 | 1804 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); |
|
1712 | /* Setup PSR once */ |
1805 | WARN_ON(dev_priv->psr.active); |
1713 | intel_edp_psr_setup(intel_dp); |
1806 | lockdep_assert_held(&dev_priv->psr.lock); |
1714 | 1807 | ||
1715 | /* Enable PSR on the panel */ |
1808 | /* Enable PSR on the panel */ |
1716 | intel_edp_psr_enable_sink(intel_dp); |
1809 | intel_edp_psr_enable_sink(intel_dp); |
1717 | 1810 | ||
1718 | /* Enable PSR on the host */ |
1811 | /* Enable PSR on the host */ |
1719 | intel_edp_psr_enable_source(intel_dp); |
1812 | intel_edp_psr_enable_source(intel_dp); |
- | 1813 | ||
- | 1814 | dev_priv->psr.active = true; |
|
1720 | } |
1815 | } |
1721 | 1816 | ||
1722 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
1817 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
1723 | { |
1818 | { |
1724 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1819 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | 1820 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1821 | ||
- | 1822 | if (!HAS_PSR(dev)) { |
|
- | 1823 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
|
- | 1824 | return; |
|
- | 1825 | } |
|
1725 | 1826 | ||
- | 1827 | if (!is_edp_psr(intel_dp)) { |
|
- | 1828 | DRM_DEBUG_KMS("PSR not supported by this panel\n"); |
|
- | 1829 | return; |
|
- | 1830 | } |
|
- | 1831 | ||
1726 | if (intel_edp_psr_match_conditions(intel_dp) && |
1832 | mutex_lock(&dev_priv->psr.lock); |
- | 1833 | if (dev_priv->psr.enabled) { |
|
- | 1834 | DRM_DEBUG_KMS("PSR already in use\n"); |
|
- | 1835 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1836 | return; |
|
- | 1837 | } |
|
- | 1838 | ||
- | 1839 | dev_priv->psr.busy_frontbuffer_bits = 0; |
|
- | 1840 | ||
1727 | !intel_edp_is_psr_enabled(dev)) |
1841 | /* Setup PSR once */ |
- | 1842 | intel_edp_psr_setup(intel_dp); |
|
- | 1843 | ||
- | 1844 | if (intel_edp_psr_match_conditions(intel_dp)) |
|
- | 1845 | dev_priv->psr.enabled = intel_dp; |
|
1728 | intel_edp_psr_do_enable(intel_dp); |
1846 | mutex_unlock(&dev_priv->psr.lock); |
1729 | } |
1847 | } |
1730 | 1848 | ||
1731 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
1849 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
1732 | { |
1850 | { |
1733 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1851 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1734 | struct drm_i915_private *dev_priv = dev->dev_private; |
1852 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 1853 | ||
1735 | 1854 | mutex_lock(&dev_priv->psr.lock); |
|
- | 1855 | if (!dev_priv->psr.enabled) { |
|
1736 | if (!intel_edp_is_psr_enabled(dev)) |
1856 | mutex_unlock(&dev_priv->psr.lock); |
- | 1857 | return; |
|
- | 1858 | } |
|
1737 | return; |
1859 | |
1738 | 1860 | if (dev_priv->psr.active) { |
|
1739 | I915_WRITE(EDP_PSR_CTL(dev), |
1861 | I915_WRITE(EDP_PSR_CTL(dev), |
1740 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); |
1862 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); |
1741 | 1863 | ||
1742 | /* Wait till PSR is idle */ |
1864 | /* Wait till PSR is idle */ |
1743 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
1865 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
1744 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
1866 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
1745 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); |
1867 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); |
- | 1868 | ||
- | 1869 | dev_priv->psr.active = false; |
|
- | 1870 | } else { |
|
- | 1871 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); |
|
1746 | } |
1872 | } |
- | 1873 | ||
- | 1874 | dev_priv->psr.enabled = NULL; |
|
- | 1875 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1876 | ||
- | 1877 | cancel_delayed_work_sync(&dev_priv->psr.work); |
|
- | 1878 | } |
|
1747 | 1879 | ||
1748 | void intel_edp_psr_update(struct drm_device *dev) |
1880 | static void intel_edp_psr_work(struct work_struct *work) |
1749 | { |
1881 | { |
- | 1882 | struct drm_i915_private *dev_priv = |
|
1750 | struct intel_encoder *encoder; |
1883 | container_of(work, typeof(*dev_priv), psr.work.work); |
1751 | struct intel_dp *intel_dp = NULL; |
- | |
1752 | 1884 | struct intel_dp *intel_dp = dev_priv->psr.enabled; |
|
1753 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) |
1885 | |
1754 | if (encoder->type == INTEL_OUTPUT_EDP) { |
1886 | mutex_lock(&dev_priv->psr.lock); |
1755 | intel_dp = enc_to_intel_dp(&encoder->base); |
1887 | intel_dp = dev_priv->psr.enabled; |
- | 1888 | ||
- | 1889 | if (!intel_dp) |
|
- | 1890 | goto unlock; |
|
- | 1891 | ||
- | 1892 | /* |
|
- | 1893 | * The delayed work can race with an invalidate hence we need to |
|
- | 1894 | * recheck. Since psr_flush first clears this and then reschedules we |
|
- | 1895 | * won't ever miss a flush when bailing out here. |
|
1756 | - | ||
1757 | if (!is_edp_psr(dev)) |
- | |
1758 | return; |
- | |
1759 | - | ||
1760 | if (!intel_edp_psr_match_conditions(intel_dp)) |
1896 | */ |
- | 1897 | if (dev_priv->psr.busy_frontbuffer_bits) |
|
- | 1898 | goto unlock; |
|
1761 | intel_edp_psr_disable(intel_dp); |
1899 | |
- | 1900 | intel_edp_psr_do_enable(intel_dp); |
|
- | 1901 | unlock: |
|
- | 1902 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1903 | } |
|
- | 1904 | ||
- | 1905 | static void intel_edp_psr_do_exit(struct drm_device *dev) |
|
- | 1906 | { |
|
- | 1907 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1908 | ||
- | 1909 | if (dev_priv->psr.active) { |
|
- | 1910 | u32 val = I915_READ(EDP_PSR_CTL(dev)); |
|
- | 1911 | ||
- | 1912 | WARN_ON(!(val & EDP_PSR_ENABLE)); |
|
- | 1913 | ||
- | 1914 | I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); |
|
- | 1915 | ||
- | 1916 | dev_priv->psr.active = false; |
|
- | 1917 | } |
|
- | 1918 | ||
- | 1919 | } |
|
- | 1920 | ||
- | 1921 | void intel_edp_psr_invalidate(struct drm_device *dev, |
|
- | 1922 | unsigned frontbuffer_bits) |
|
- | 1923 | { |
|
- | 1924 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1925 | struct drm_crtc *crtc; |
|
- | 1926 | enum pipe pipe; |
|
- | 1927 | ||
- | 1928 | mutex_lock(&dev_priv->psr.lock); |
|
- | 1929 | if (!dev_priv->psr.enabled) { |
|
- | 1930 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1931 | return; |
|
- | 1932 | } |
|
- | 1933 | ||
- | 1934 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; |
|
- | 1935 | pipe = to_intel_crtc(crtc)->pipe; |
|
- | 1936 | ||
- | 1937 | intel_edp_psr_do_exit(dev); |
|
- | 1938 | ||
- | 1939 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
|
- | 1940 | ||
- | 1941 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
|
- | 1942 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1943 | } |
|
- | 1944 | ||
- | 1945 | void intel_edp_psr_flush(struct drm_device *dev, |
|
- | 1946 | unsigned frontbuffer_bits) |
|
- | 1947 | { |
|
- | 1948 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 1949 | struct drm_crtc *crtc; |
|
- | 1950 | enum pipe pipe; |
|
- | 1951 | ||
- | 1952 | mutex_lock(&dev_priv->psr.lock); |
|
- | 1953 | if (!dev_priv->psr.enabled) { |
|
- | 1954 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1955 | return; |
|
- | 1956 | } |
|
- | 1957 | ||
- | 1958 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; |
|
- | 1959 | pipe = to_intel_crtc(crtc)->pipe; |
|
- | 1960 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
|
- | 1961 | ||
- | 1962 | /* |
|
- | 1963 | * On Haswell sprite plane updates don't result in a psr invalidating |
|
- | 1964 | * signal in the hardware. Which means we need to manually fake this in |
|
- | 1965 | * software for all flushes, not just when we've seen a preceding |
|
- | 1966 | * invalidation through frontbuffer rendering. |
|
- | 1967 | */ |
|
- | 1968 | if (IS_HASWELL(dev) && |
|
- | 1969 | (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) |
|
- | 1970 | intel_edp_psr_do_exit(dev); |
|
- | 1971 | ||
- | 1972 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
|
- | 1973 | schedule_delayed_work(&dev_priv->psr.work, |
|
- | 1974 | msecs_to_jiffies(100)); |
|
- | 1975 | mutex_unlock(&dev_priv->psr.lock); |
|
- | 1976 | } |
|
- | 1977 | ||
- | 1978 | void intel_edp_psr_init(struct drm_device *dev) |
|
- | 1979 | { |
|
1762 | else |
1980 | struct drm_i915_private *dev_priv = dev->dev_private; |
1763 | if (!intel_edp_is_psr_enabled(dev)) |
1981 | |
1764 | intel_edp_psr_do_enable(intel_dp); |
1982 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work); |
1765 | } |
1983 | mutex_init(&dev_priv->psr.lock); |
1766 | } |
1984 | } |
1767 | 1985 | ||
1768 | static void intel_disable_dp(struct intel_encoder *encoder) |
1986 | static void intel_disable_dp(struct intel_encoder *encoder) |
1769 | { |
1987 | { |
1770 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1988 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1771 | enum port port = dp_to_dig_port(intel_dp)->port; |
1989 | enum port port = dp_to_dig_port(intel_dp)->port; |
1772 | struct drm_device *dev = encoder->base.dev; |
1990 | struct drm_device *dev = encoder->base.dev; |
1773 | 1991 | ||
1774 | /* Make sure the panel is off before trying to change the mode. But also |
1992 | /* Make sure the panel is off before trying to change the mode. But also |
1775 | * ensure that we have vdd while we switch off the panel. */ |
1993 | * ensure that we have vdd while we switch off the panel. */ |
- | 1994 | intel_edp_panel_vdd_on(intel_dp); |
|
1776 | ironlake_edp_backlight_off(intel_dp); |
1995 | intel_edp_backlight_off(intel_dp); |
1777 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
1996 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
1778 | ironlake_edp_panel_off(intel_dp); |
1997 | intel_edp_panel_off(intel_dp); |
1779 | 1998 | ||
1780 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
1999 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
1781 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
2000 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
1782 | intel_dp_link_down(intel_dp); |
2001 | intel_dp_link_down(intel_dp); |
1783 | } |
2002 | } |
1784 | 2003 | ||
1785 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
2004 | static void g4x_post_disable_dp(struct intel_encoder *encoder) |
1786 | { |
2005 | { |
1787 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2006 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1788 | enum port port = dp_to_dig_port(intel_dp)->port; |
2007 | enum port port = dp_to_dig_port(intel_dp)->port; |
1789 | struct drm_device *dev = encoder->base.dev; |
- | |
1790 | 2008 | ||
- | 2009 | if (port != PORT_A) |
|
- | 2010 | return; |
|
1791 | if (port == PORT_A || IS_VALLEYVIEW(dev)) { |
2011 | |
1792 | intel_dp_link_down(intel_dp); |
- | |
1793 | if (!IS_VALLEYVIEW(dev)) |
2012 | intel_dp_link_down(intel_dp); |
1794 | ironlake_edp_pll_off(intel_dp); |
2013 | ironlake_edp_pll_off(intel_dp); |
- | 2014 | } |
|
- | 2015 | ||
- | 2016 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
|
- | 2017 | { |
|
- | 2018 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 2019 | ||
- | 2020 | intel_dp_link_down(intel_dp); |
|
- | 2021 | } |
|
- | 2022 | ||
- | 2023 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
|
- | 2024 | { |
|
- | 2025 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 2026 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
|
- | 2027 | struct drm_device *dev = encoder->base.dev; |
|
- | 2028 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2029 | struct intel_crtc *intel_crtc = |
|
- | 2030 | to_intel_crtc(encoder->base.crtc); |
|
- | 2031 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
|
- | 2032 | enum pipe pipe = intel_crtc->pipe; |
|
- | 2033 | u32 val; |
|
- | 2034 | ||
- | 2035 | intel_dp_link_down(intel_dp); |
|
- | 2036 | ||
- | 2037 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 2038 | ||
- | 2039 | /* Propagate soft reset to data lane reset */ |
|
- | 2040 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
|
- | 2041 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
|
- | 2042 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
|
- | 2043 | ||
- | 2044 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
|
- | 2045 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
|
- | 2046 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
|
- | 2047 | ||
- | 2048 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
|
- | 2049 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
|
- | 2050 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
|
- | 2051 | ||
- | 2052 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
|
- | 2053 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
|
- | 2054 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
|
- | 2055 | ||
1795 | } |
2056 | mutex_unlock(&dev_priv->dpio_lock); |
1796 | } |
2057 | } |
1797 | 2058 | ||
1798 | static void intel_enable_dp(struct intel_encoder *encoder) |
2059 | static void intel_enable_dp(struct intel_encoder *encoder) |
1799 | { |
2060 | { |
1800 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2061 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1801 | struct drm_device *dev = encoder->base.dev; |
2062 | struct drm_device *dev = encoder->base.dev; |
1802 | struct drm_i915_private *dev_priv = dev->dev_private; |
2063 | struct drm_i915_private *dev_priv = dev->dev_private; |
1803 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
2064 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
1804 | 2065 | ||
1805 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2066 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
1806 | return; |
2067 | return; |
1807 | 2068 | ||
1808 | ironlake_edp_panel_vdd_on(intel_dp); |
2069 | intel_edp_panel_vdd_on(intel_dp); |
1809 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2070 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
1810 | intel_dp_start_link_train(intel_dp); |
2071 | intel_dp_start_link_train(intel_dp); |
1811 | ironlake_edp_panel_on(intel_dp); |
2072 | intel_edp_panel_on(intel_dp); |
1812 | ironlake_edp_panel_vdd_off(intel_dp, true); |
2073 | edp_panel_vdd_off(intel_dp, true); |
1813 | intel_dp_complete_link_train(intel_dp); |
2074 | intel_dp_complete_link_train(intel_dp); |
1814 | intel_dp_stop_link_train(intel_dp); |
2075 | intel_dp_stop_link_train(intel_dp); |
1815 | } |
2076 | } |
1816 | 2077 | ||
1817 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2078 | static void g4x_enable_dp(struct intel_encoder *encoder) |
1818 | { |
2079 | { |
1819 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2080 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1820 | 2081 | ||
1821 | intel_enable_dp(encoder); |
2082 | intel_enable_dp(encoder); |
1822 | ironlake_edp_backlight_on(intel_dp); |
2083 | intel_edp_backlight_on(intel_dp); |
1823 | } |
2084 | } |
1824 | 2085 | ||
1825 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2086 | static void vlv_enable_dp(struct intel_encoder *encoder) |
1826 | { |
2087 | { |
1827 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2088 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1828 | 2089 | ||
1829 | ironlake_edp_backlight_on(intel_dp); |
2090 | intel_edp_backlight_on(intel_dp); |
1830 | } |
2091 | } |
1831 | 2092 | ||
1832 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
2093 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
1833 | { |
2094 | { |
1834 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2095 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1835 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2096 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
- | 2097 | ||
- | 2098 | intel_dp_prepare(encoder); |
|
- | 2099 | ||
1836 | 2100 | /* Only ilk+ has port A */ |
|
- | 2101 | if (dport->port == PORT_A) { |
|
1837 | if (dport->port == PORT_A) |
2102 | ironlake_set_pll_cpu_edp(intel_dp); |
1838 | ironlake_edp_pll_on(intel_dp); |
2103 | ironlake_edp_pll_on(intel_dp); |
- | 2104 | } |
|
1839 | } |
2105 | } |
1840 | 2106 | ||
1841 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
2107 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
1842 | { |
2108 | { |
1843 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2109 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1844 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2110 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
1845 | struct drm_device *dev = encoder->base.dev; |
2111 | struct drm_device *dev = encoder->base.dev; |
1846 | struct drm_i915_private *dev_priv = dev->dev_private; |
2112 | struct drm_i915_private *dev_priv = dev->dev_private; |
1847 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
2113 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
1848 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2114 | enum dpio_channel port = vlv_dport_to_channel(dport); |
1849 | int pipe = intel_crtc->pipe; |
2115 | int pipe = intel_crtc->pipe; |
1850 | struct edp_power_seq power_seq; |
2116 | struct edp_power_seq power_seq; |
1851 | u32 val; |
2117 | u32 val; |
1852 | 2118 | ||
1853 | mutex_lock(&dev_priv->dpio_lock); |
2119 | mutex_lock(&dev_priv->dpio_lock); |
1854 | 2120 | ||
1855 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
2121 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
1856 | val = 0; |
2122 | val = 0; |
1857 | if (pipe) |
2123 | if (pipe) |
1858 | val |= (1<<21); |
2124 | val |= (1<<21); |
1859 | else |
2125 | else |
1860 | val &= ~(1<<21); |
2126 | val &= ~(1<<21); |
1861 | val |= 0x001000c4; |
2127 | val |= 0x001000c4; |
1862 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
2128 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
1863 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
2129 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1864 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
2130 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
1865 | 2131 | ||
1866 | mutex_unlock(&dev_priv->dpio_lock); |
2132 | mutex_unlock(&dev_priv->dpio_lock); |
- | 2133 | ||
1867 | 2134 | if (is_edp(intel_dp)) { |
|
1868 | /* init power sequencer on this pipe and port */ |
2135 | /* init power sequencer on this pipe and port */ |
1869 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
2136 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
1870 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
2137 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
1871 | &power_seq); |
2138 | &power_seq); |
- | 2139 | } |
|
1872 | 2140 | ||
1873 | intel_enable_dp(encoder); |
2141 | intel_enable_dp(encoder); |
1874 | 2142 | ||
1875 | vlv_wait_port_ready(dev_priv, dport); |
2143 | vlv_wait_port_ready(dev_priv, dport); |
1876 | } |
2144 | } |
1877 | 2145 | ||
1878 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2146 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
1879 | { |
2147 | { |
1880 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
2148 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1881 | struct drm_device *dev = encoder->base.dev; |
2149 | struct drm_device *dev = encoder->base.dev; |
1882 | struct drm_i915_private *dev_priv = dev->dev_private; |
2150 | struct drm_i915_private *dev_priv = dev->dev_private; |
1883 | struct intel_crtc *intel_crtc = |
2151 | struct intel_crtc *intel_crtc = |
1884 | to_intel_crtc(encoder->base.crtc); |
2152 | to_intel_crtc(encoder->base.crtc); |
1885 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2153 | enum dpio_channel port = vlv_dport_to_channel(dport); |
1886 | int pipe = intel_crtc->pipe; |
2154 | int pipe = intel_crtc->pipe; |
- | 2155 | ||
- | 2156 | intel_dp_prepare(encoder); |
|
1887 | 2157 | ||
1888 | /* Program Tx lane resets to default */ |
2158 | /* Program Tx lane resets to default */ |
1889 | mutex_lock(&dev_priv->dpio_lock); |
2159 | mutex_lock(&dev_priv->dpio_lock); |
1890 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
2160 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
1891 | DPIO_PCS_TX_LANE2_RESET | |
2161 | DPIO_PCS_TX_LANE2_RESET | |
1892 | DPIO_PCS_TX_LANE1_RESET); |
2162 | DPIO_PCS_TX_LANE1_RESET); |
1893 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
2163 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
1894 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2164 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1895 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
2165 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
1896 | (1< |
2166 | (1< |
1897 | DPIO_PCS_CLK_SOFT_RESET); |
2167 | DPIO_PCS_CLK_SOFT_RESET); |
1898 | 2168 | ||
1899 | /* Fix up inter-pair skew failure */ |
2169 | /* Fix up inter-pair skew failure */ |
1900 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2170 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1901 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
2171 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
1902 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
2172 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
1903 | mutex_unlock(&dev_priv->dpio_lock); |
2173 | mutex_unlock(&dev_priv->dpio_lock); |
1904 | } |
2174 | } |
- | 2175 | ||
- | 2176 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
|
- | 2177 | { |
|
- | 2178 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 2179 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
|
- | 2180 | struct drm_device *dev = encoder->base.dev; |
|
- | 2181 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2182 | struct edp_power_seq power_seq; |
|
- | 2183 | struct intel_crtc *intel_crtc = |
|
- | 2184 | to_intel_crtc(encoder->base.crtc); |
|
- | 2185 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
|
- | 2186 | int pipe = intel_crtc->pipe; |
|
- | 2187 | int data, i; |
|
- | 2188 | u32 val; |
|
- | 2189 | ||
- | 2190 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 2191 | ||
- | 2192 | /* Deassert soft data lane reset*/ |
|
- | 2193 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
|
- | 2194 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
|
- | 2195 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
|
- | 2196 | ||
- | 2197 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
|
- | 2198 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
|
- | 2199 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
|
- | 2200 | ||
- | 2201 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
|
- | 2202 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
|
- | 2203 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
|
- | 2204 | ||
- | 2205 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
|
- | 2206 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
|
- | 2207 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
|
- | 2208 | ||
- | 2209 | /* Program Tx lane latency optimal setting*/ |
|
- | 2210 | for (i = 0; i < 4; i++) { |
|
- | 2211 | /* Set the latency optimal bit */ |
|
- | 2212 | data = (i == 1) ? 0x0 : 0x6; |
|
- | 2213 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), |
|
- | 2214 | data << DPIO_FRC_LATENCY_SHFIT); |
|
- | 2215 | ||
- | 2216 | /* Set the upar bit */ |
|
- | 2217 | data = (i == 1) ? 0x0 : 0x1; |
|
- | 2218 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
|
- | 2219 | data << DPIO_UPAR_SHIFT); |
|
- | 2220 | } |
|
- | 2221 | ||
- | 2222 | /* Data lane stagger programming */ |
|
- | 2223 | /* FIXME: Fix up value only after power analysis */ |
|
- | 2224 | ||
- | 2225 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 2226 | ||
- | 2227 | if (is_edp(intel_dp)) { |
|
- | 2228 | /* init power sequencer on this pipe and port */ |
|
- | 2229 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
|
- | 2230 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
|
- | 2231 | &power_seq); |
|
- | 2232 | } |
|
- | 2233 | ||
- | 2234 | intel_enable_dp(encoder); |
|
- | 2235 | ||
- | 2236 | vlv_wait_port_ready(dev_priv, dport); |
|
- | 2237 | } |
|
- | 2238 | ||
- | 2239 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
|
- | 2240 | { |
|
- | 2241 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
|
- | 2242 | struct drm_device *dev = encoder->base.dev; |
|
- | 2243 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2244 | struct intel_crtc *intel_crtc = |
|
- | 2245 | to_intel_crtc(encoder->base.crtc); |
|
- | 2246 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
|
- | 2247 | enum pipe pipe = intel_crtc->pipe; |
|
- | 2248 | u32 val; |
|
- | 2249 | ||
- | 2250 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 2251 | ||
- | 2252 | /* program left/right clock distribution */ |
|
- | 2253 | if (pipe != PIPE_B) { |
|
- | 2254 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
|
- | 2255 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
|
- | 2256 | if (ch == DPIO_CH0) |
|
- | 2257 | val |= CHV_BUFLEFTENA1_FORCE; |
|
- | 2258 | if (ch == DPIO_CH1) |
|
- | 2259 | val |= CHV_BUFRIGHTENA1_FORCE; |
|
- | 2260 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
|
- | 2261 | } else { |
|
- | 2262 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
|
- | 2263 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
|
- | 2264 | if (ch == DPIO_CH0) |
|
- | 2265 | val |= CHV_BUFLEFTENA2_FORCE; |
|
- | 2266 | if (ch == DPIO_CH1) |
|
- | 2267 | val |= CHV_BUFRIGHTENA2_FORCE; |
|
- | 2268 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
|
- | 2269 | } |
|
- | 2270 | ||
- | 2271 | /* program clock channel usage */ |
|
- | 2272 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
|
- | 2273 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
|
- | 2274 | if (pipe != PIPE_B) |
|
- | 2275 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
|
- | 2276 | else |
|
- | 2277 | val |= CHV_PCS_USEDCLKCHANNEL; |
|
- | 2278 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
|
- | 2279 | ||
- | 2280 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
|
- | 2281 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
|
- | 2282 | if (pipe != PIPE_B) |
|
- | 2283 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
|
- | 2284 | else |
|
- | 2285 | val |= CHV_PCS_USEDCLKCHANNEL; |
|
- | 2286 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
|
- | 2287 | ||
- | 2288 | /* |
|
- | 2289 | * This a a bit weird since generally CL |
|
- | 2290 | * matches the pipe, but here we need to |
|
- | 2291 | * pick the CL based on the port. |
|
- | 2292 | */ |
|
- | 2293 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
|
- | 2294 | if (pipe != PIPE_B) |
|
- | 2295 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
|
- | 2296 | else |
|
- | 2297 | val |= CHV_CMN_USEDCLKCHANNEL; |
|
- | 2298 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
|
- | 2299 | ||
- | 2300 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 2301 | } |
|
1905 | 2302 | ||
1906 | /* |
2303 | /* |
1907 | * Native read with retry for link status and receiver capability reads for |
2304 | * Native read with retry for link status and receiver capability reads for |
1908 | * cases where the sink may still be asleep. |
2305 | * cases where the sink may still be asleep. |
- | 2306 | * |
|
- | 2307 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
|
- | 2308 | * supposed to retry 3 times per the spec. |
|
1909 | */ |
2309 | */ |
1910 | static bool |
2310 | static ssize_t |
1911 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
2311 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
1912 | uint8_t *recv, int recv_bytes) |
2312 | void *buffer, size_t size) |
1913 | { |
2313 | { |
- | 2314 | ssize_t ret; |
|
1914 | int ret, i; |
2315 | int i; |
1915 | - | ||
1916 | /* |
- | |
1917 | * Sinks are *supposed* to come up within 1ms from an off state, |
- | |
1918 | * but we're also supposed to retry 3 times per the spec. |
- | |
1919 | */ |
2316 | |
1920 | for (i = 0; i < 3; i++) { |
2317 | for (i = 0; i < 3; i++) { |
1921 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
- | |
1922 | recv_bytes); |
2318 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
1923 | if (ret == recv_bytes) |
2319 | if (ret == size) |
1924 | return true; |
2320 | return ret; |
1925 | msleep(1); |
2321 | msleep(1); |
1926 | } |
2322 | } |
1927 | 2323 | ||
1928 | return false; |
2324 | return ret; |
1929 | } |
2325 | } |
1930 | 2326 | ||
1931 | /* |
2327 | /* |
1932 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
2328 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
1933 | * link status information |
2329 | * link status information |
1934 | */ |
2330 | */ |
1935 | static bool |
2331 | static bool |
1936 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2332 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
1937 | { |
2333 | { |
1938 | return intel_dp_aux_native_read_retry(intel_dp, |
2334 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
1939 | DP_LANE0_1_STATUS, |
2335 | DP_LANE0_1_STATUS, |
1940 | link_status, |
2336 | link_status, |
1941 | DP_LINK_STATUS_SIZE); |
2337 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
1942 | } |
2338 | } |
1943 | - | ||
1944 | /* |
2339 | |
1945 | * These are source-specific values; current Intel hardware supports |
- | |
1946 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB |
- | |
1947 | */ |
- | |
1948 | 2340 | /* These are source-specific values. */ |
|
1949 | static uint8_t |
2341 | static uint8_t |
1950 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
2342 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
1951 | { |
2343 | { |
1952 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2344 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1953 | enum port port = dp_to_dig_port(intel_dp)->port; |
2345 | enum port port = dp_to_dig_port(intel_dp)->port; |
1954 | 2346 | ||
1955 | if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) |
2347 | if (IS_VALLEYVIEW(dev)) |
1956 | return DP_TRAIN_VOLTAGE_SWING_1200; |
2348 | return DP_TRAIN_VOLTAGE_SWING_1200; |
1957 | else if (IS_GEN7(dev) && port == PORT_A) |
2349 | else if (IS_GEN7(dev) && port == PORT_A) |
1958 | return DP_TRAIN_VOLTAGE_SWING_800; |
2350 | return DP_TRAIN_VOLTAGE_SWING_800; |
1959 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
2351 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
1960 | return DP_TRAIN_VOLTAGE_SWING_1200; |
2352 | return DP_TRAIN_VOLTAGE_SWING_1200; |
1961 | else |
2353 | else |
1962 | return DP_TRAIN_VOLTAGE_SWING_800; |
2354 | return DP_TRAIN_VOLTAGE_SWING_800; |
1963 | } |
2355 | } |
1964 | 2356 | ||
1965 | static uint8_t |
2357 | static uint8_t |
1966 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
2358 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
1967 | { |
2359 | { |
1968 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2360 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1969 | enum port port = dp_to_dig_port(intel_dp)->port; |
2361 | enum port port = dp_to_dig_port(intel_dp)->port; |
1970 | 2362 | ||
1971 | if (IS_BROADWELL(dev)) { |
- | |
1972 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
- | |
1973 | case DP_TRAIN_VOLTAGE_SWING_400: |
- | |
1974 | case DP_TRAIN_VOLTAGE_SWING_600: |
- | |
1975 | return DP_TRAIN_PRE_EMPHASIS_6; |
- | |
1976 | case DP_TRAIN_VOLTAGE_SWING_800: |
- | |
1977 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
- | |
1978 | case DP_TRAIN_VOLTAGE_SWING_1200: |
- | |
1979 | default: |
- | |
1980 | return DP_TRAIN_PRE_EMPHASIS_0; |
- | |
1981 | } |
- | |
1982 | } else if (IS_HASWELL(dev)) { |
2363 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1983 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2364 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1984 | case DP_TRAIN_VOLTAGE_SWING_400: |
2365 | case DP_TRAIN_VOLTAGE_SWING_400: |
1985 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
2366 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
1986 | case DP_TRAIN_VOLTAGE_SWING_600: |
2367 | case DP_TRAIN_VOLTAGE_SWING_600: |
1987 | return DP_TRAIN_PRE_EMPHASIS_6; |
2368 | return DP_TRAIN_PRE_EMPHASIS_6; |
1988 | case DP_TRAIN_VOLTAGE_SWING_800: |
2369 | case DP_TRAIN_VOLTAGE_SWING_800: |
1989 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
2370 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
1990 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2371 | case DP_TRAIN_VOLTAGE_SWING_1200: |
1991 | default: |
2372 | default: |
1992 | return DP_TRAIN_PRE_EMPHASIS_0; |
2373 | return DP_TRAIN_PRE_EMPHASIS_0; |
1993 | } |
2374 | } |
1994 | } else if (IS_VALLEYVIEW(dev)) { |
2375 | } else if (IS_VALLEYVIEW(dev)) { |
1995 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2376 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1996 | case DP_TRAIN_VOLTAGE_SWING_400: |
2377 | case DP_TRAIN_VOLTAGE_SWING_400: |
1997 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
2378 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
1998 | case DP_TRAIN_VOLTAGE_SWING_600: |
2379 | case DP_TRAIN_VOLTAGE_SWING_600: |
1999 | return DP_TRAIN_PRE_EMPHASIS_6; |
2380 | return DP_TRAIN_PRE_EMPHASIS_6; |
2000 | case DP_TRAIN_VOLTAGE_SWING_800: |
2381 | case DP_TRAIN_VOLTAGE_SWING_800: |
2001 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
2382 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
2002 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2383 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2003 | default: |
2384 | default: |
2004 | return DP_TRAIN_PRE_EMPHASIS_0; |
2385 | return DP_TRAIN_PRE_EMPHASIS_0; |
2005 | } |
2386 | } |
2006 | } else if (IS_GEN7(dev) && port == PORT_A) { |
2387 | } else if (IS_GEN7(dev) && port == PORT_A) { |
2007 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2388 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2008 | case DP_TRAIN_VOLTAGE_SWING_400: |
2389 | case DP_TRAIN_VOLTAGE_SWING_400: |
2009 | return DP_TRAIN_PRE_EMPHASIS_6; |
2390 | return DP_TRAIN_PRE_EMPHASIS_6; |
2010 | case DP_TRAIN_VOLTAGE_SWING_600: |
2391 | case DP_TRAIN_VOLTAGE_SWING_600: |
2011 | case DP_TRAIN_VOLTAGE_SWING_800: |
2392 | case DP_TRAIN_VOLTAGE_SWING_800: |
2012 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
2393 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
2013 | default: |
2394 | default: |
2014 | return DP_TRAIN_PRE_EMPHASIS_0; |
2395 | return DP_TRAIN_PRE_EMPHASIS_0; |
2015 | } |
2396 | } |
2016 | } else { |
2397 | } else { |
2017 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2398 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2018 | case DP_TRAIN_VOLTAGE_SWING_400: |
2399 | case DP_TRAIN_VOLTAGE_SWING_400: |
2019 | return DP_TRAIN_PRE_EMPHASIS_6; |
2400 | return DP_TRAIN_PRE_EMPHASIS_6; |
2020 | case DP_TRAIN_VOLTAGE_SWING_600: |
2401 | case DP_TRAIN_VOLTAGE_SWING_600: |
2021 | return DP_TRAIN_PRE_EMPHASIS_6; |
2402 | return DP_TRAIN_PRE_EMPHASIS_6; |
2022 | case DP_TRAIN_VOLTAGE_SWING_800: |
2403 | case DP_TRAIN_VOLTAGE_SWING_800: |
2023 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
2404 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
2024 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2405 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2025 | default: |
2406 | default: |
2026 | return DP_TRAIN_PRE_EMPHASIS_0; |
2407 | return DP_TRAIN_PRE_EMPHASIS_0; |
2027 | } |
2408 | } |
2028 | } |
2409 | } |
2029 | } |
2410 | } |
2030 | 2411 | ||
2031 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
2412 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
2032 | { |
2413 | { |
2033 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2414 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2034 | struct drm_i915_private *dev_priv = dev->dev_private; |
2415 | struct drm_i915_private *dev_priv = dev->dev_private; |
2035 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2416 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2036 | struct intel_crtc *intel_crtc = |
2417 | struct intel_crtc *intel_crtc = |
2037 | to_intel_crtc(dport->base.base.crtc); |
2418 | to_intel_crtc(dport->base.base.crtc); |
2038 | unsigned long demph_reg_value, preemph_reg_value, |
2419 | unsigned long demph_reg_value, preemph_reg_value, |
2039 | uniqtranscale_reg_value; |
2420 | uniqtranscale_reg_value; |
2040 | uint8_t train_set = intel_dp->train_set[0]; |
2421 | uint8_t train_set = intel_dp->train_set[0]; |
2041 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2422 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2042 | int pipe = intel_crtc->pipe; |
2423 | int pipe = intel_crtc->pipe; |
2043 | 2424 | ||
2044 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
2425 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
2045 | case DP_TRAIN_PRE_EMPHASIS_0: |
2426 | case DP_TRAIN_PRE_EMPHASIS_0: |
2046 | preemph_reg_value = 0x0004000; |
2427 | preemph_reg_value = 0x0004000; |
2047 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2428 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2048 | case DP_TRAIN_VOLTAGE_SWING_400: |
2429 | case DP_TRAIN_VOLTAGE_SWING_400: |
2049 | demph_reg_value = 0x2B405555; |
2430 | demph_reg_value = 0x2B405555; |
2050 | uniqtranscale_reg_value = 0x552AB83A; |
2431 | uniqtranscale_reg_value = 0x552AB83A; |
2051 | break; |
2432 | break; |
2052 | case DP_TRAIN_VOLTAGE_SWING_600: |
2433 | case DP_TRAIN_VOLTAGE_SWING_600: |
2053 | demph_reg_value = 0x2B404040; |
2434 | demph_reg_value = 0x2B404040; |
2054 | uniqtranscale_reg_value = 0x5548B83A; |
2435 | uniqtranscale_reg_value = 0x5548B83A; |
2055 | break; |
2436 | break; |
2056 | case DP_TRAIN_VOLTAGE_SWING_800: |
2437 | case DP_TRAIN_VOLTAGE_SWING_800: |
2057 | demph_reg_value = 0x2B245555; |
2438 | demph_reg_value = 0x2B245555; |
2058 | uniqtranscale_reg_value = 0x5560B83A; |
2439 | uniqtranscale_reg_value = 0x5560B83A; |
2059 | break; |
2440 | break; |
2060 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2441 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2061 | demph_reg_value = 0x2B405555; |
2442 | demph_reg_value = 0x2B405555; |
2062 | uniqtranscale_reg_value = 0x5598DA3A; |
2443 | uniqtranscale_reg_value = 0x5598DA3A; |
2063 | break; |
2444 | break; |
2064 | default: |
2445 | default: |
2065 | return 0; |
2446 | return 0; |
2066 | } |
2447 | } |
2067 | break; |
2448 | break; |
2068 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
2449 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
2069 | preemph_reg_value = 0x0002000; |
2450 | preemph_reg_value = 0x0002000; |
2070 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2451 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2071 | case DP_TRAIN_VOLTAGE_SWING_400: |
2452 | case DP_TRAIN_VOLTAGE_SWING_400: |
2072 | demph_reg_value = 0x2B404040; |
2453 | demph_reg_value = 0x2B404040; |
2073 | uniqtranscale_reg_value = 0x5552B83A; |
2454 | uniqtranscale_reg_value = 0x5552B83A; |
2074 | break; |
2455 | break; |
2075 | case DP_TRAIN_VOLTAGE_SWING_600: |
2456 | case DP_TRAIN_VOLTAGE_SWING_600: |
2076 | demph_reg_value = 0x2B404848; |
2457 | demph_reg_value = 0x2B404848; |
2077 | uniqtranscale_reg_value = 0x5580B83A; |
2458 | uniqtranscale_reg_value = 0x5580B83A; |
2078 | break; |
2459 | break; |
2079 | case DP_TRAIN_VOLTAGE_SWING_800: |
2460 | case DP_TRAIN_VOLTAGE_SWING_800: |
2080 | demph_reg_value = 0x2B404040; |
2461 | demph_reg_value = 0x2B404040; |
2081 | uniqtranscale_reg_value = 0x55ADDA3A; |
2462 | uniqtranscale_reg_value = 0x55ADDA3A; |
2082 | break; |
2463 | break; |
2083 | default: |
2464 | default: |
2084 | return 0; |
2465 | return 0; |
2085 | } |
2466 | } |
2086 | break; |
2467 | break; |
2087 | case DP_TRAIN_PRE_EMPHASIS_6: |
2468 | case DP_TRAIN_PRE_EMPHASIS_6: |
2088 | preemph_reg_value = 0x0000000; |
2469 | preemph_reg_value = 0x0000000; |
2089 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2470 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2090 | case DP_TRAIN_VOLTAGE_SWING_400: |
2471 | case DP_TRAIN_VOLTAGE_SWING_400: |
2091 | demph_reg_value = 0x2B305555; |
2472 | demph_reg_value = 0x2B305555; |
2092 | uniqtranscale_reg_value = 0x5570B83A; |
2473 | uniqtranscale_reg_value = 0x5570B83A; |
2093 | break; |
2474 | break; |
2094 | case DP_TRAIN_VOLTAGE_SWING_600: |
2475 | case DP_TRAIN_VOLTAGE_SWING_600: |
2095 | demph_reg_value = 0x2B2B4040; |
2476 | demph_reg_value = 0x2B2B4040; |
2096 | uniqtranscale_reg_value = 0x55ADDA3A; |
2477 | uniqtranscale_reg_value = 0x55ADDA3A; |
2097 | break; |
2478 | break; |
2098 | default: |
2479 | default: |
2099 | return 0; |
2480 | return 0; |
2100 | } |
2481 | } |
2101 | break; |
2482 | break; |
2102 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
2483 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
2103 | preemph_reg_value = 0x0006000; |
2484 | preemph_reg_value = 0x0006000; |
2104 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2485 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2105 | case DP_TRAIN_VOLTAGE_SWING_400: |
2486 | case DP_TRAIN_VOLTAGE_SWING_400: |
2106 | demph_reg_value = 0x1B405555; |
2487 | demph_reg_value = 0x1B405555; |
2107 | uniqtranscale_reg_value = 0x55ADDA3A; |
2488 | uniqtranscale_reg_value = 0x55ADDA3A; |
2108 | break; |
2489 | break; |
2109 | default: |
2490 | default: |
2110 | return 0; |
2491 | return 0; |
2111 | } |
2492 | } |
2112 | break; |
2493 | break; |
2113 | default: |
2494 | default: |
2114 | return 0; |
2495 | return 0; |
2115 | } |
2496 | } |
2116 | 2497 | ||
2117 | mutex_lock(&dev_priv->dpio_lock); |
2498 | mutex_lock(&dev_priv->dpio_lock); |
2118 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
2499 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
2119 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
2500 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
2120 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
2501 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
2121 | uniqtranscale_reg_value); |
2502 | uniqtranscale_reg_value); |
2122 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
2503 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
2123 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
2504 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
2124 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
2505 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
2125 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
2506 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
2126 | mutex_unlock(&dev_priv->dpio_lock); |
2507 | mutex_unlock(&dev_priv->dpio_lock); |
2127 | 2508 | ||
2128 | return 0; |
2509 | return 0; |
2129 | } |
2510 | } |
- | 2511 | ||
- | 2512 | static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) |
|
- | 2513 | { |
|
- | 2514 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 2515 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 2516 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
|
- | 2517 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
|
- | 2518 | u32 deemph_reg_value, margin_reg_value, val; |
|
- | 2519 | uint8_t train_set = intel_dp->train_set[0]; |
|
- | 2520 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
|
- | 2521 | enum pipe pipe = intel_crtc->pipe; |
|
- | 2522 | int i; |
|
- | 2523 | ||
- | 2524 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
|
- | 2525 | case DP_TRAIN_PRE_EMPHASIS_0: |
|
- | 2526 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 2527 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 2528 | deemph_reg_value = 128; |
|
- | 2529 | margin_reg_value = 52; |
|
- | 2530 | break; |
|
- | 2531 | case DP_TRAIN_VOLTAGE_SWING_600: |
|
- | 2532 | deemph_reg_value = 128; |
|
- | 2533 | margin_reg_value = 77; |
|
- | 2534 | break; |
|
- | 2535 | case DP_TRAIN_VOLTAGE_SWING_800: |
|
- | 2536 | deemph_reg_value = 128; |
|
- | 2537 | margin_reg_value = 102; |
|
- | 2538 | break; |
|
- | 2539 | case DP_TRAIN_VOLTAGE_SWING_1200: |
|
- | 2540 | deemph_reg_value = 128; |
|
- | 2541 | margin_reg_value = 154; |
|
- | 2542 | /* FIXME extra to set for 1200 */ |
|
- | 2543 | break; |
|
- | 2544 | default: |
|
- | 2545 | return 0; |
|
- | 2546 | } |
|
- | 2547 | break; |
|
- | 2548 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
|
- | 2549 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 2550 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 2551 | deemph_reg_value = 85; |
|
- | 2552 | margin_reg_value = 78; |
|
- | 2553 | break; |
|
- | 2554 | case DP_TRAIN_VOLTAGE_SWING_600: |
|
- | 2555 | deemph_reg_value = 85; |
|
- | 2556 | margin_reg_value = 116; |
|
- | 2557 | break; |
|
- | 2558 | case DP_TRAIN_VOLTAGE_SWING_800: |
|
- | 2559 | deemph_reg_value = 85; |
|
- | 2560 | margin_reg_value = 154; |
|
- | 2561 | break; |
|
- | 2562 | default: |
|
- | 2563 | return 0; |
|
- | 2564 | } |
|
- | 2565 | break; |
|
- | 2566 | case DP_TRAIN_PRE_EMPHASIS_6: |
|
- | 2567 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 2568 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 2569 | deemph_reg_value = 64; |
|
- | 2570 | margin_reg_value = 104; |
|
- | 2571 | break; |
|
- | 2572 | case DP_TRAIN_VOLTAGE_SWING_600: |
|
- | 2573 | deemph_reg_value = 64; |
|
- | 2574 | margin_reg_value = 154; |
|
- | 2575 | break; |
|
- | 2576 | default: |
|
- | 2577 | return 0; |
|
- | 2578 | } |
|
- | 2579 | break; |
|
- | 2580 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
|
- | 2581 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
|
- | 2582 | case DP_TRAIN_VOLTAGE_SWING_400: |
|
- | 2583 | deemph_reg_value = 43; |
|
- | 2584 | margin_reg_value = 154; |
|
- | 2585 | break; |
|
- | 2586 | default: |
|
- | 2587 | return 0; |
|
- | 2588 | } |
|
- | 2589 | break; |
|
- | 2590 | default: |
|
- | 2591 | return 0; |
|
- | 2592 | } |
|
- | 2593 | ||
- | 2594 | mutex_lock(&dev_priv->dpio_lock); |
|
- | 2595 | ||
- | 2596 | /* Clear calc init */ |
|
- | 2597 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
|
- | 2598 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
|
- | 2599 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
|
- | 2600 | ||
- | 2601 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
|
- | 2602 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
|
- | 2603 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
|
- | 2604 | ||
- | 2605 | /* Program swing deemph */ |
|
- | 2606 | for (i = 0; i < 4; i++) { |
|
- | 2607 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
|
- | 2608 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
|
- | 2609 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
|
- | 2610 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
|
- | 2611 | } |
|
- | 2612 | ||
- | 2613 | /* Program swing margin */ |
|
- | 2614 | for (i = 0; i < 4; i++) { |
|
- | 2615 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
|
- | 2616 | val &= ~DPIO_SWING_MARGIN_MASK; |
|
- | 2617 | val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; |
|
- | 2618 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
|
- | 2619 | } |
|
- | 2620 | ||
- | 2621 | /* Disable unique transition scale */ |
|
- | 2622 | for (i = 0; i < 4; i++) { |
|
- | 2623 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
|
- | 2624 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
|
- | 2625 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
|
- | 2626 | } |
|
- | 2627 | ||
- | 2628 | if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) |
|
- | 2629 | == DP_TRAIN_PRE_EMPHASIS_0) && |
|
- | 2630 | ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) |
|
- | 2631 | == DP_TRAIN_VOLTAGE_SWING_1200)) { |
|
- | 2632 | ||
- | 2633 | /* |
|
- | 2634 | * The document said it needs to set bit 27 for ch0 and bit 26 |
|
- | 2635 | * for ch1. Might be a typo in the doc. |
|
- | 2636 | * For now, for this unique transition scale selection, set bit |
|
- | 2637 | * 27 for ch0 and ch1. |
|
- | 2638 | */ |
|
- | 2639 | for (i = 0; i < 4; i++) { |
|
- | 2640 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
|
- | 2641 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
|
- | 2642 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
|
- | 2643 | } |
|
- | 2644 | ||
- | 2645 | for (i = 0; i < 4; i++) { |
|
- | 2646 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
|
- | 2647 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
|
- | 2648 | val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
|
- | 2649 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
|
- | 2650 | } |
|
- | 2651 | } |
|
- | 2652 | ||
- | 2653 | /* Start swing calculation */ |
|
- | 2654 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
|
- | 2655 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
|
- | 2656 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
|
- | 2657 | ||
- | 2658 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
|
- | 2659 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
|
- | 2660 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
|
- | 2661 | ||
- | 2662 | /* LRC Bypass */ |
|
- | 2663 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); |
|
- | 2664 | val |= DPIO_LRC_BYPASS; |
|
- | 2665 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); |
|
- | 2666 | ||
- | 2667 | mutex_unlock(&dev_priv->dpio_lock); |
|
- | 2668 | ||
- | 2669 | return 0; |
|
- | 2670 | } |
|
2130 | 2671 | ||
2131 | static void |
2672 | static void |
2132 | intel_get_adjust_train(struct intel_dp *intel_dp, |
2673 | intel_get_adjust_train(struct intel_dp *intel_dp, |
2133 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2674 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2134 | { |
2675 | { |
2135 | uint8_t v = 0; |
2676 | uint8_t v = 0; |
2136 | uint8_t p = 0; |
2677 | uint8_t p = 0; |
2137 | int lane; |
2678 | int lane; |
2138 | uint8_t voltage_max; |
2679 | uint8_t voltage_max; |
2139 | uint8_t preemph_max; |
2680 | uint8_t preemph_max; |
2140 | 2681 | ||
2141 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
2682 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
2142 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
2683 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
2143 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
2684 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
2144 | 2685 | ||
2145 | if (this_v > v) |
2686 | if (this_v > v) |
2146 | v = this_v; |
2687 | v = this_v; |
2147 | if (this_p > p) |
2688 | if (this_p > p) |
2148 | p = this_p; |
2689 | p = this_p; |
2149 | } |
2690 | } |
2150 | 2691 | ||
2151 | voltage_max = intel_dp_voltage_max(intel_dp); |
2692 | voltage_max = intel_dp_voltage_max(intel_dp); |
2152 | if (v >= voltage_max) |
2693 | if (v >= voltage_max) |
2153 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
2694 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
2154 | 2695 | ||
2155 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
2696 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
2156 | if (p >= preemph_max) |
2697 | if (p >= preemph_max) |
2157 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
2698 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
2158 | 2699 | ||
2159 | for (lane = 0; lane < 4; lane++) |
2700 | for (lane = 0; lane < 4; lane++) |
2160 | intel_dp->train_set[lane] = v | p; |
2701 | intel_dp->train_set[lane] = v | p; |
2161 | } |
2702 | } |
2162 | 2703 | ||
2163 | static uint32_t |
2704 | static uint32_t |
2164 | intel_gen4_signal_levels(uint8_t train_set) |
2705 | intel_gen4_signal_levels(uint8_t train_set) |
2165 | { |
2706 | { |
2166 | uint32_t signal_levels = 0; |
2707 | uint32_t signal_levels = 0; |
2167 | 2708 | ||
2168 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2709 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2169 | case DP_TRAIN_VOLTAGE_SWING_400: |
2710 | case DP_TRAIN_VOLTAGE_SWING_400: |
2170 | default: |
2711 | default: |
2171 | signal_levels |= DP_VOLTAGE_0_4; |
2712 | signal_levels |= DP_VOLTAGE_0_4; |
2172 | break; |
2713 | break; |
2173 | case DP_TRAIN_VOLTAGE_SWING_600: |
2714 | case DP_TRAIN_VOLTAGE_SWING_600: |
2174 | signal_levels |= DP_VOLTAGE_0_6; |
2715 | signal_levels |= DP_VOLTAGE_0_6; |
2175 | break; |
2716 | break; |
2176 | case DP_TRAIN_VOLTAGE_SWING_800: |
2717 | case DP_TRAIN_VOLTAGE_SWING_800: |
2177 | signal_levels |= DP_VOLTAGE_0_8; |
2718 | signal_levels |= DP_VOLTAGE_0_8; |
2178 | break; |
2719 | break; |
2179 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2720 | case DP_TRAIN_VOLTAGE_SWING_1200: |
2180 | signal_levels |= DP_VOLTAGE_1_2; |
2721 | signal_levels |= DP_VOLTAGE_1_2; |
2181 | break; |
2722 | break; |
2182 | } |
2723 | } |
2183 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
2724 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
2184 | case DP_TRAIN_PRE_EMPHASIS_0: |
2725 | case DP_TRAIN_PRE_EMPHASIS_0: |
2185 | default: |
2726 | default: |
2186 | signal_levels |= DP_PRE_EMPHASIS_0; |
2727 | signal_levels |= DP_PRE_EMPHASIS_0; |
2187 | break; |
2728 | break; |
2188 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
2729 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
2189 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
2730 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
2190 | break; |
2731 | break; |
2191 | case DP_TRAIN_PRE_EMPHASIS_6: |
2732 | case DP_TRAIN_PRE_EMPHASIS_6: |
2192 | signal_levels |= DP_PRE_EMPHASIS_6; |
2733 | signal_levels |= DP_PRE_EMPHASIS_6; |
2193 | break; |
2734 | break; |
2194 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
2735 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
2195 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
2736 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
2196 | break; |
2737 | break; |
2197 | } |
2738 | } |
2198 | return signal_levels; |
2739 | return signal_levels; |
2199 | } |
2740 | } |
2200 | 2741 | ||
2201 | /* Gen6's DP voltage swing and pre-emphasis control */ |
2742 | /* Gen6's DP voltage swing and pre-emphasis control */ |
2202 | static uint32_t |
2743 | static uint32_t |
2203 | intel_gen6_edp_signal_levels(uint8_t train_set) |
2744 | intel_gen6_edp_signal_levels(uint8_t train_set) |
2204 | { |
2745 | { |
2205 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2746 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2206 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2747 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2207 | switch (signal_levels) { |
2748 | switch (signal_levels) { |
2208 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
2749 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
2209 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2750 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2210 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
2751 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
2211 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2752 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2212 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
2753 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
2213 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
2754 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
2214 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
2755 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
2215 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
2756 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
2216 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2757 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2217 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2758 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2218 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
2759 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
2219 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2760 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2220 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
2761 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
2221 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
2762 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
2222 | default: |
2763 | default: |
2223 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2764 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2224 | "0x%x\n", signal_levels); |
2765 | "0x%x\n", signal_levels); |
2225 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
2766 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
2226 | } |
2767 | } |
2227 | } |
2768 | } |
2228 | 2769 | ||
2229 | /* Gen7's DP voltage swing and pre-emphasis control */ |
2770 | /* Gen7's DP voltage swing and pre-emphasis control */ |
2230 | static uint32_t |
2771 | static uint32_t |
2231 | intel_gen7_edp_signal_levels(uint8_t train_set) |
2772 | intel_gen7_edp_signal_levels(uint8_t train_set) |
2232 | { |
2773 | { |
2233 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2774 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2234 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2775 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2235 | switch (signal_levels) { |
2776 | switch (signal_levels) { |
2236 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
2777 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
2237 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
2778 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
2238 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2779 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2239 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
2780 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
2240 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
2781 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
2241 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
2782 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
2242 | 2783 | ||
2243 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2784 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2244 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
2785 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
2245 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2786 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2246 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
2787 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
2247 | 2788 | ||
2248 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2789 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2249 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
2790 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
2250 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2791 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2251 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
2792 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
2252 | 2793 | ||
2253 | default: |
2794 | default: |
2254 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2795 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2255 | "0x%x\n", signal_levels); |
2796 | "0x%x\n", signal_levels); |
2256 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
2797 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
2257 | } |
2798 | } |
2258 | } |
2799 | } |
2259 | 2800 | ||
2260 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
2801 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
2261 | static uint32_t |
2802 | static uint32_t |
2262 | intel_hsw_signal_levels(uint8_t train_set) |
2803 | intel_hsw_signal_levels(uint8_t train_set) |
2263 | { |
2804 | { |
2264 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2805 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2265 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2806 | DP_TRAIN_PRE_EMPHASIS_MASK); |
2266 | switch (signal_levels) { |
2807 | switch (signal_levels) { |
2267 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
2808 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
2268 | return DDI_BUF_EMP_400MV_0DB_HSW; |
2809 | return DDI_BUF_EMP_400MV_0DB_HSW; |
2269 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2810 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2270 | return DDI_BUF_EMP_400MV_3_5DB_HSW; |
2811 | return DDI_BUF_EMP_400MV_3_5DB_HSW; |
2271 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
2812 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
2272 | return DDI_BUF_EMP_400MV_6DB_HSW; |
2813 | return DDI_BUF_EMP_400MV_6DB_HSW; |
2273 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: |
2814 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: |
2274 | return DDI_BUF_EMP_400MV_9_5DB_HSW; |
2815 | return DDI_BUF_EMP_400MV_9_5DB_HSW; |
2275 | 2816 | ||
2276 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2817 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2277 | return DDI_BUF_EMP_600MV_0DB_HSW; |
2818 | return DDI_BUF_EMP_600MV_0DB_HSW; |
2278 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2819 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2279 | return DDI_BUF_EMP_600MV_3_5DB_HSW; |
2820 | return DDI_BUF_EMP_600MV_3_5DB_HSW; |
2280 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
2821 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
2281 | return DDI_BUF_EMP_600MV_6DB_HSW; |
2822 | return DDI_BUF_EMP_600MV_6DB_HSW; |
2282 | 2823 | ||
2283 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2824 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2284 | return DDI_BUF_EMP_800MV_0DB_HSW; |
2825 | return DDI_BUF_EMP_800MV_0DB_HSW; |
2285 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2826 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2286 | return DDI_BUF_EMP_800MV_3_5DB_HSW; |
2827 | return DDI_BUF_EMP_800MV_3_5DB_HSW; |
2287 | default: |
2828 | default: |
2288 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2829 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2289 | "0x%x\n", signal_levels); |
2830 | "0x%x\n", signal_levels); |
2290 | return DDI_BUF_EMP_400MV_0DB_HSW; |
2831 | return DDI_BUF_EMP_400MV_0DB_HSW; |
2291 | } |
2832 | } |
2292 | } |
2833 | } |
2293 | - | ||
2294 | static uint32_t |
- | |
2295 | intel_bdw_signal_levels(uint8_t train_set) |
- | |
2296 | { |
- | |
2297 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
- | |
2298 | DP_TRAIN_PRE_EMPHASIS_MASK); |
- | |
2299 | switch (signal_levels) { |
- | |
2300 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
- | |
2301 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ |
- | |
2302 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
- | |
2303 | return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ |
- | |
2304 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
- | |
2305 | return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ |
- | |
2306 | - | ||
2307 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
- | |
2308 | return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ |
- | |
2309 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
- | |
2310 | return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ |
- | |
2311 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
- | |
2312 | return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ |
- | |
2313 | - | ||
2314 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
- | |
2315 | return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ |
- | |
2316 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
- | |
2317 | return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ |
- | |
2318 | - | ||
2319 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
- | |
2320 | return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ |
- | |
2321 | - | ||
2322 | default: |
- | |
2323 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
- | |
2324 | "0x%x\n", signal_levels); |
- | |
2325 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ |
- | |
2326 | } |
- | |
2327 | } |
- | |
2328 | 2834 | ||
2329 | /* Properly updates "DP" with the correct signal levels. */ |
2835 | /* Properly updates "DP" with the correct signal levels. */ |
2330 | static void |
2836 | static void |
2331 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
2837 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
2332 | { |
2838 | { |
2333 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2839 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2334 | enum port port = intel_dig_port->port; |
2840 | enum port port = intel_dig_port->port; |
2335 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2841 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2336 | uint32_t signal_levels, mask; |
2842 | uint32_t signal_levels, mask; |
2337 | uint8_t train_set = intel_dp->train_set[0]; |
2843 | uint8_t train_set = intel_dp->train_set[0]; |
2338 | 2844 | ||
2339 | if (IS_BROADWELL(dev)) { |
- | |
2340 | signal_levels = intel_bdw_signal_levels(train_set); |
- | |
2341 | mask = DDI_BUF_EMP_MASK; |
- | |
2342 | } else if (IS_HASWELL(dev)) { |
2845 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2343 | signal_levels = intel_hsw_signal_levels(train_set); |
2846 | signal_levels = intel_hsw_signal_levels(train_set); |
- | 2847 | mask = DDI_BUF_EMP_MASK; |
|
- | 2848 | } else if (IS_CHERRYVIEW(dev)) { |
|
- | 2849 | signal_levels = intel_chv_signal_levels(intel_dp); |
|
2344 | mask = DDI_BUF_EMP_MASK; |
2850 | mask = 0; |
2345 | } else if (IS_VALLEYVIEW(dev)) { |
2851 | } else if (IS_VALLEYVIEW(dev)) { |
2346 | signal_levels = intel_vlv_signal_levels(intel_dp); |
2852 | signal_levels = intel_vlv_signal_levels(intel_dp); |
2347 | mask = 0; |
2853 | mask = 0; |
2348 | } else if (IS_GEN7(dev) && port == PORT_A) { |
2854 | } else if (IS_GEN7(dev) && port == PORT_A) { |
2349 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
2855 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
2350 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
2856 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
2351 | } else if (IS_GEN6(dev) && port == PORT_A) { |
2857 | } else if (IS_GEN6(dev) && port == PORT_A) { |
2352 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
2858 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
2353 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
2859 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
2354 | } else { |
2860 | } else { |
2355 | signal_levels = intel_gen4_signal_levels(train_set); |
2861 | signal_levels = intel_gen4_signal_levels(train_set); |
2356 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
2862 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
2357 | } |
2863 | } |
2358 | 2864 | ||
2359 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
2865 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
2360 | 2866 | ||
2361 | *DP = (*DP & ~mask) | signal_levels; |
2867 | *DP = (*DP & ~mask) | signal_levels; |
2362 | } |
2868 | } |
2363 | 2869 | ||
2364 | static bool |
2870 | static bool |
2365 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
2871 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
2366 | uint32_t *DP, |
2872 | uint32_t *DP, |
2367 | uint8_t dp_train_pat) |
2873 | uint8_t dp_train_pat) |
2368 | { |
2874 | { |
2369 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2875 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2370 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2876 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2371 | struct drm_i915_private *dev_priv = dev->dev_private; |
2877 | struct drm_i915_private *dev_priv = dev->dev_private; |
2372 | enum port port = intel_dig_port->port; |
2878 | enum port port = intel_dig_port->port; |
2373 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
2879 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
2374 | int ret, len; |
2880 | int ret, len; |
2375 | 2881 | ||
2376 | if (HAS_DDI(dev)) { |
2882 | if (HAS_DDI(dev)) { |
2377 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2883 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2378 | 2884 | ||
2379 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
2885 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
2380 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
2886 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
2381 | else |
2887 | else |
2382 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
2888 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
2383 | 2889 | ||
2384 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
2890 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
2385 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2891 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2386 | case DP_TRAINING_PATTERN_DISABLE: |
2892 | case DP_TRAINING_PATTERN_DISABLE: |
2387 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2893 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2388 | 2894 | ||
2389 | break; |
2895 | break; |
2390 | case DP_TRAINING_PATTERN_1: |
2896 | case DP_TRAINING_PATTERN_1: |
2391 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
2897 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
2392 | break; |
2898 | break; |
2393 | case DP_TRAINING_PATTERN_2: |
2899 | case DP_TRAINING_PATTERN_2: |
2394 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
2900 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
2395 | break; |
2901 | break; |
2396 | case DP_TRAINING_PATTERN_3: |
2902 | case DP_TRAINING_PATTERN_3: |
2397 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
2903 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
2398 | break; |
2904 | break; |
2399 | } |
2905 | } |
2400 | I915_WRITE(DP_TP_CTL(port), temp); |
2906 | I915_WRITE(DP_TP_CTL(port), temp); |
2401 | 2907 | ||
2402 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
2908 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
2403 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2909 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2404 | 2910 | ||
2405 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2911 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2406 | case DP_TRAINING_PATTERN_DISABLE: |
2912 | case DP_TRAINING_PATTERN_DISABLE: |
2407 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
2913 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
2408 | break; |
2914 | break; |
2409 | case DP_TRAINING_PATTERN_1: |
2915 | case DP_TRAINING_PATTERN_1: |
2410 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
2916 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
2411 | break; |
2917 | break; |
2412 | case DP_TRAINING_PATTERN_2: |
2918 | case DP_TRAINING_PATTERN_2: |
2413 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2919 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2414 | break; |
2920 | break; |
2415 | case DP_TRAINING_PATTERN_3: |
2921 | case DP_TRAINING_PATTERN_3: |
2416 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2922 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2417 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2923 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2418 | break; |
2924 | break; |
2419 | } |
2925 | } |
2420 | 2926 | ||
2421 | } else { |
2927 | } else { |
2422 | *DP &= ~DP_LINK_TRAIN_MASK; |
2928 | *DP &= ~DP_LINK_TRAIN_MASK; |
2423 | 2929 | ||
2424 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2930 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2425 | case DP_TRAINING_PATTERN_DISABLE: |
2931 | case DP_TRAINING_PATTERN_DISABLE: |
2426 | *DP |= DP_LINK_TRAIN_OFF; |
2932 | *DP |= DP_LINK_TRAIN_OFF; |
2427 | break; |
2933 | break; |
2428 | case DP_TRAINING_PATTERN_1: |
2934 | case DP_TRAINING_PATTERN_1: |
2429 | *DP |= DP_LINK_TRAIN_PAT_1; |
2935 | *DP |= DP_LINK_TRAIN_PAT_1; |
2430 | break; |
2936 | break; |
2431 | case DP_TRAINING_PATTERN_2: |
2937 | case DP_TRAINING_PATTERN_2: |
2432 | *DP |= DP_LINK_TRAIN_PAT_2; |
2938 | *DP |= DP_LINK_TRAIN_PAT_2; |
2433 | break; |
2939 | break; |
2434 | case DP_TRAINING_PATTERN_3: |
2940 | case DP_TRAINING_PATTERN_3: |
2435 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2941 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2436 | *DP |= DP_LINK_TRAIN_PAT_2; |
2942 | *DP |= DP_LINK_TRAIN_PAT_2; |
2437 | break; |
2943 | break; |
2438 | } |
2944 | } |
2439 | } |
2945 | } |
2440 | 2946 | ||
2441 | I915_WRITE(intel_dp->output_reg, *DP); |
2947 | I915_WRITE(intel_dp->output_reg, *DP); |
2442 | POSTING_READ(intel_dp->output_reg); |
2948 | POSTING_READ(intel_dp->output_reg); |
2443 | 2949 | ||
2444 | buf[0] = dp_train_pat; |
2950 | buf[0] = dp_train_pat; |
2445 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == |
2951 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == |
2446 | DP_TRAINING_PATTERN_DISABLE) { |
2952 | DP_TRAINING_PATTERN_DISABLE) { |
2447 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
2953 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
2448 | len = 1; |
2954 | len = 1; |
2449 | } else { |
2955 | } else { |
2450 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
2956 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
2451 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
2957 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
2452 | len = intel_dp->lane_count + 1; |
2958 | len = intel_dp->lane_count + 1; |
2453 | } |
2959 | } |
2454 | 2960 | ||
2455 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET, |
2961 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
2456 | buf, len); |
2962 | buf, len); |
2457 | 2963 | ||
2458 | return ret == len; |
2964 | return ret == len; |
2459 | } |
2965 | } |
2460 | 2966 | ||
2461 | static bool |
2967 | static bool |
2462 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
2968 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
2463 | uint8_t dp_train_pat) |
2969 | uint8_t dp_train_pat) |
2464 | { |
2970 | { |
2465 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
2971 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
2466 | intel_dp_set_signal_levels(intel_dp, DP); |
2972 | intel_dp_set_signal_levels(intel_dp, DP); |
2467 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
2973 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
2468 | } |
2974 | } |
2469 | 2975 | ||
2470 | static bool |
2976 | static bool |
2471 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
2977 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
2472 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2978 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2473 | { |
2979 | { |
2474 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2980 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2475 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2981 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2476 | struct drm_i915_private *dev_priv = dev->dev_private; |
2982 | struct drm_i915_private *dev_priv = dev->dev_private; |
2477 | int ret; |
2983 | int ret; |
2478 | 2984 | ||
2479 | intel_get_adjust_train(intel_dp, link_status); |
2985 | intel_get_adjust_train(intel_dp, link_status); |
2480 | intel_dp_set_signal_levels(intel_dp, DP); |
2986 | intel_dp_set_signal_levels(intel_dp, DP); |
2481 | 2987 | ||
2482 | I915_WRITE(intel_dp->output_reg, *DP); |
2988 | I915_WRITE(intel_dp->output_reg, *DP); |
2483 | POSTING_READ(intel_dp->output_reg); |
2989 | POSTING_READ(intel_dp->output_reg); |
2484 | 2990 | ||
2485 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET, |
- | |
2486 | intel_dp->train_set, |
2991 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
2487 | intel_dp->lane_count); |
2992 | intel_dp->train_set, intel_dp->lane_count); |
2488 | 2993 | ||
2489 | return ret == intel_dp->lane_count; |
2994 | return ret == intel_dp->lane_count; |
2490 | } |
2995 | } |
2491 | 2996 | ||
2492 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
2997 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
2493 | { |
2998 | { |
2494 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2999 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2495 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3000 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2496 | struct drm_i915_private *dev_priv = dev->dev_private; |
3001 | struct drm_i915_private *dev_priv = dev->dev_private; |
2497 | enum port port = intel_dig_port->port; |
3002 | enum port port = intel_dig_port->port; |
2498 | uint32_t val; |
3003 | uint32_t val; |
2499 | 3004 | ||
2500 | if (!HAS_DDI(dev)) |
3005 | if (!HAS_DDI(dev)) |
2501 | return; |
3006 | return; |
2502 | 3007 | ||
2503 | val = I915_READ(DP_TP_CTL(port)); |
3008 | val = I915_READ(DP_TP_CTL(port)); |
2504 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
3009 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
2505 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
3010 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
2506 | I915_WRITE(DP_TP_CTL(port), val); |
3011 | I915_WRITE(DP_TP_CTL(port), val); |
2507 | 3012 | ||
2508 | /* |
3013 | /* |
2509 | * On PORT_A we can have only eDP in SST mode. There the only reason |
3014 | * On PORT_A we can have only eDP in SST mode. There the only reason |
2510 | * we need to set idle transmission mode is to work around a HW issue |
3015 | * we need to set idle transmission mode is to work around a HW issue |
2511 | * where we enable the pipe while not in idle link-training mode. |
3016 | * where we enable the pipe while not in idle link-training mode. |
2512 | * In this case there is requirement to wait for a minimum number of |
3017 | * In this case there is requirement to wait for a minimum number of |
2513 | * idle patterns to be sent. |
3018 | * idle patterns to be sent. |
2514 | */ |
3019 | */ |
2515 | if (port == PORT_A) |
3020 | if (port == PORT_A) |
2516 | return; |
3021 | return; |
2517 | 3022 | ||
2518 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
3023 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
2519 | 1)) |
3024 | 1)) |
2520 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3025 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
2521 | } |
3026 | } |
2522 | 3027 | ||
2523 | /* Enable corresponding port and start training pattern 1 */ |
3028 | /* Enable corresponding port and start training pattern 1 */ |
2524 | void |
3029 | void |
2525 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
3030 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
2526 | { |
3031 | { |
2527 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
3032 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
2528 | struct drm_device *dev = encoder->dev; |
3033 | struct drm_device *dev = encoder->dev; |
2529 | int i; |
3034 | int i; |
2530 | uint8_t voltage; |
3035 | uint8_t voltage; |
2531 | int voltage_tries, loop_tries; |
3036 | int voltage_tries, loop_tries; |
2532 | uint32_t DP = intel_dp->DP; |
3037 | uint32_t DP = intel_dp->DP; |
2533 | uint8_t link_config[2]; |
3038 | uint8_t link_config[2]; |
2534 | 3039 | ||
2535 | if (HAS_DDI(dev)) |
3040 | if (HAS_DDI(dev)) |
2536 | intel_ddi_prepare_link_retrain(encoder); |
3041 | intel_ddi_prepare_link_retrain(encoder); |
2537 | 3042 | ||
2538 | /* Write the link configuration data */ |
3043 | /* Write the link configuration data */ |
2539 | link_config[0] = intel_dp->link_bw; |
3044 | link_config[0] = intel_dp->link_bw; |
2540 | link_config[1] = intel_dp->lane_count; |
3045 | link_config[1] = intel_dp->lane_count; |
2541 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
3046 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
2542 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
3047 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
2543 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2); |
3048 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
2544 | 3049 | ||
2545 | link_config[0] = 0; |
3050 | link_config[0] = 0; |
2546 | link_config[1] = DP_SET_ANSI_8B10B; |
3051 | link_config[1] = DP_SET_ANSI_8B10B; |
2547 | intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2); |
3052 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
2548 | 3053 | ||
2549 | DP |= DP_PORT_EN; |
3054 | DP |= DP_PORT_EN; |
2550 | 3055 | ||
2551 | /* clock recovery */ |
3056 | /* clock recovery */ |
2552 | if (!intel_dp_reset_link_train(intel_dp, &DP, |
3057 | if (!intel_dp_reset_link_train(intel_dp, &DP, |
2553 | DP_TRAINING_PATTERN_1 | |
3058 | DP_TRAINING_PATTERN_1 | |
2554 | DP_LINK_SCRAMBLING_DISABLE)) { |
3059 | DP_LINK_SCRAMBLING_DISABLE)) { |
2555 | DRM_ERROR("failed to enable link training\n"); |
3060 | DRM_ERROR("failed to enable link training\n"); |
2556 | return; |
3061 | return; |
2557 | } |
3062 | } |
2558 | 3063 | ||
2559 | voltage = 0xff; |
3064 | voltage = 0xff; |
2560 | voltage_tries = 0; |
3065 | voltage_tries = 0; |
2561 | loop_tries = 0; |
3066 | loop_tries = 0; |
2562 | for (;;) { |
3067 | for (;;) { |
2563 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
3068 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
2564 | 3069 | ||
2565 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
3070 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
2566 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3071 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2567 | DRM_ERROR("failed to get link status\n"); |
3072 | DRM_ERROR("failed to get link status\n"); |
2568 | break; |
3073 | break; |
2569 | } |
3074 | } |
2570 | 3075 | ||
2571 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
3076 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
2572 | DRM_DEBUG_KMS("clock recovery OK\n"); |
3077 | DRM_DEBUG_KMS("clock recovery OK\n"); |
2573 | break; |
3078 | break; |
2574 | } |
3079 | } |
2575 | 3080 | ||
2576 | /* Check to see if we've tried the max voltage */ |
3081 | /* Check to see if we've tried the max voltage */ |
2577 | for (i = 0; i < intel_dp->lane_count; i++) |
3082 | for (i = 0; i < intel_dp->lane_count; i++) |
2578 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
3083 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
2579 | break; |
3084 | break; |
2580 | if (i == intel_dp->lane_count) { |
3085 | if (i == intel_dp->lane_count) { |
2581 | ++loop_tries; |
3086 | ++loop_tries; |
2582 | if (loop_tries == 5) { |
3087 | if (loop_tries == 5) { |
2583 | DRM_ERROR("too many full retries, give up\n"); |
3088 | DRM_ERROR("too many full retries, give up\n"); |
2584 | break; |
3089 | break; |
2585 | } |
3090 | } |
2586 | intel_dp_reset_link_train(intel_dp, &DP, |
3091 | intel_dp_reset_link_train(intel_dp, &DP, |
2587 | DP_TRAINING_PATTERN_1 | |
3092 | DP_TRAINING_PATTERN_1 | |
2588 | DP_LINK_SCRAMBLING_DISABLE); |
3093 | DP_LINK_SCRAMBLING_DISABLE); |
2589 | voltage_tries = 0; |
3094 | voltage_tries = 0; |
2590 | continue; |
3095 | continue; |
2591 | } |
3096 | } |
2592 | 3097 | ||
2593 | /* Check to see if we've tried the same voltage 5 times */ |
3098 | /* Check to see if we've tried the same voltage 5 times */ |
2594 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
3099 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
2595 | ++voltage_tries; |
3100 | ++voltage_tries; |
2596 | if (voltage_tries == 5) { |
3101 | if (voltage_tries == 5) { |
2597 | DRM_ERROR("too many voltage retries, give up\n"); |
3102 | DRM_ERROR("too many voltage retries, give up\n"); |
2598 | break; |
3103 | break; |
2599 | } |
3104 | } |
2600 | } else |
3105 | } else |
2601 | voltage_tries = 0; |
3106 | voltage_tries = 0; |
2602 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
3107 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
2603 | 3108 | ||
2604 | /* Update training set as requested by target */ |
3109 | /* Update training set as requested by target */ |
2605 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
3110 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
2606 | DRM_ERROR("failed to update link training\n"); |
3111 | DRM_ERROR("failed to update link training\n"); |
2607 | break; |
3112 | break; |
2608 | } |
3113 | } |
2609 | } |
3114 | } |
2610 | 3115 | ||
2611 | intel_dp->DP = DP; |
3116 | intel_dp->DP = DP; |
2612 | } |
3117 | } |
2613 | 3118 | ||
2614 | void |
3119 | void |
2615 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
3120 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
2616 | { |
3121 | { |
2617 | bool channel_eq = false; |
3122 | bool channel_eq = false; |
2618 | int tries, cr_tries; |
3123 | int tries, cr_tries; |
2619 | uint32_t DP = intel_dp->DP; |
3124 | uint32_t DP = intel_dp->DP; |
- | 3125 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
|
- | 3126 | ||
- | 3127 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ |
|
- | 3128 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) |
|
- | 3129 | training_pattern = DP_TRAINING_PATTERN_3; |
|
2620 | 3130 | ||
2621 | /* channel equalization */ |
3131 | /* channel equalization */ |
2622 | if (!intel_dp_set_link_train(intel_dp, &DP, |
3132 | if (!intel_dp_set_link_train(intel_dp, &DP, |
2623 | DP_TRAINING_PATTERN_2 | |
3133 | training_pattern | |
2624 | DP_LINK_SCRAMBLING_DISABLE)) { |
3134 | DP_LINK_SCRAMBLING_DISABLE)) { |
2625 | DRM_ERROR("failed to start channel equalization\n"); |
3135 | DRM_ERROR("failed to start channel equalization\n"); |
2626 | return; |
3136 | return; |
2627 | } |
3137 | } |
2628 | 3138 | ||
2629 | tries = 0; |
3139 | tries = 0; |
2630 | cr_tries = 0; |
3140 | cr_tries = 0; |
2631 | channel_eq = false; |
3141 | channel_eq = false; |
2632 | for (;;) { |
3142 | for (;;) { |
2633 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
3143 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
2634 | 3144 | ||
2635 | if (cr_tries > 5) { |
3145 | if (cr_tries > 5) { |
2636 | DRM_ERROR("failed to train DP, aborting\n"); |
3146 | DRM_ERROR("failed to train DP, aborting\n"); |
2637 | break; |
3147 | break; |
2638 | } |
3148 | } |
2639 | 3149 | ||
2640 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
3150 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
2641 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3151 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2642 | DRM_ERROR("failed to get link status\n"); |
3152 | DRM_ERROR("failed to get link status\n"); |
2643 | break; |
3153 | break; |
2644 | } |
3154 | } |
2645 | 3155 | ||
2646 | /* Make sure clock is still ok */ |
3156 | /* Make sure clock is still ok */ |
2647 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
3157 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
2648 | intel_dp_start_link_train(intel_dp); |
3158 | intel_dp_start_link_train(intel_dp); |
2649 | intel_dp_set_link_train(intel_dp, &DP, |
3159 | intel_dp_set_link_train(intel_dp, &DP, |
2650 | DP_TRAINING_PATTERN_2 | |
3160 | training_pattern | |
2651 | DP_LINK_SCRAMBLING_DISABLE); |
3161 | DP_LINK_SCRAMBLING_DISABLE); |
2652 | cr_tries++; |
3162 | cr_tries++; |
2653 | continue; |
3163 | continue; |
2654 | } |
3164 | } |
2655 | 3165 | ||
2656 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
3166 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
2657 | channel_eq = true; |
3167 | channel_eq = true; |
2658 | break; |
3168 | break; |
2659 | } |
3169 | } |
2660 | 3170 | ||
2661 | /* Try 5 times, then try clock recovery if that fails */ |
3171 | /* Try 5 times, then try clock recovery if that fails */ |
2662 | if (tries > 5) { |
3172 | if (tries > 5) { |
2663 | intel_dp_link_down(intel_dp); |
3173 | intel_dp_link_down(intel_dp); |
2664 | intel_dp_start_link_train(intel_dp); |
3174 | intel_dp_start_link_train(intel_dp); |
2665 | intel_dp_set_link_train(intel_dp, &DP, |
3175 | intel_dp_set_link_train(intel_dp, &DP, |
2666 | DP_TRAINING_PATTERN_2 | |
3176 | training_pattern | |
2667 | DP_LINK_SCRAMBLING_DISABLE); |
3177 | DP_LINK_SCRAMBLING_DISABLE); |
2668 | tries = 0; |
3178 | tries = 0; |
2669 | cr_tries++; |
3179 | cr_tries++; |
2670 | continue; |
3180 | continue; |
2671 | } |
3181 | } |
2672 | 3182 | ||
2673 | /* Update training set as requested by target */ |
3183 | /* Update training set as requested by target */ |
2674 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
3184 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
2675 | DRM_ERROR("failed to update link training\n"); |
3185 | DRM_ERROR("failed to update link training\n"); |
2676 | break; |
3186 | break; |
2677 | } |
3187 | } |
2678 | ++tries; |
3188 | ++tries; |
2679 | } |
3189 | } |
2680 | 3190 | ||
2681 | intel_dp_set_idle_link_train(intel_dp); |
3191 | intel_dp_set_idle_link_train(intel_dp); |
2682 | 3192 | ||
2683 | intel_dp->DP = DP; |
3193 | intel_dp->DP = DP; |
2684 | 3194 | ||
2685 | if (channel_eq) |
3195 | if (channel_eq) |
2686 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
3196 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
2687 | 3197 | ||
2688 | } |
3198 | } |
2689 | 3199 | ||
2690 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) |
3200 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) |
2691 | { |
3201 | { |
2692 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
3202 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
2693 | DP_TRAINING_PATTERN_DISABLE); |
3203 | DP_TRAINING_PATTERN_DISABLE); |
2694 | } |
3204 | } |
2695 | 3205 | ||
2696 | static void |
3206 | static void |
2697 | intel_dp_link_down(struct intel_dp *intel_dp) |
3207 | intel_dp_link_down(struct intel_dp *intel_dp) |
2698 | { |
3208 | { |
2699 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3209 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2700 | enum port port = intel_dig_port->port; |
3210 | enum port port = intel_dig_port->port; |
2701 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3211 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2702 | struct drm_i915_private *dev_priv = dev->dev_private; |
3212 | struct drm_i915_private *dev_priv = dev->dev_private; |
2703 | struct intel_crtc *intel_crtc = |
3213 | struct intel_crtc *intel_crtc = |
2704 | to_intel_crtc(intel_dig_port->base.base.crtc); |
3214 | to_intel_crtc(intel_dig_port->base.base.crtc); |
2705 | uint32_t DP = intel_dp->DP; |
3215 | uint32_t DP = intel_dp->DP; |
2706 | - | ||
2707 | /* |
- | |
2708 | * DDI code has a strict mode set sequence and we should try to respect |
- | |
2709 | * it, otherwise we might hang the machine in many different ways. So we |
- | |
2710 | * really should be disabling the port only on a complete crtc_disable |
- | |
2711 | * sequence. This function is just called under two conditions on DDI |
- | |
2712 | * code: |
- | |
2713 | * - Link train failed while doing crtc_enable, and on this case we |
- | |
2714 | * really should respect the mode set sequence and wait for a |
- | |
2715 | * crtc_disable. |
- | |
2716 | * - Someone turned the monitor off and intel_dp_check_link_status |
- | |
2717 | * called us. We don't need to disable the whole port on this case, so |
- | |
2718 | * when someone turns the monitor on again, |
- | |
2719 | * intel_ddi_prepare_link_retrain will take care of redoing the link |
- | |
2720 | * train. |
- | |
2721 | */ |
3216 | |
2722 | if (HAS_DDI(dev)) |
3217 | if (WARN_ON(HAS_DDI(dev))) |
2723 | return; |
3218 | return; |
2724 | 3219 | ||
2725 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
3220 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
2726 | return; |
3221 | return; |
2727 | 3222 | ||
2728 | DRM_DEBUG_KMS("\n"); |
3223 | DRM_DEBUG_KMS("\n"); |
2729 | 3224 | ||
2730 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
3225 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
2731 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3226 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2732 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
3227 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
2733 | } else { |
3228 | } else { |
2734 | DP &= ~DP_LINK_TRAIN_MASK; |
3229 | DP &= ~DP_LINK_TRAIN_MASK; |
2735 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
3230 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
2736 | } |
3231 | } |
2737 | POSTING_READ(intel_dp->output_reg); |
3232 | POSTING_READ(intel_dp->output_reg); |
2738 | - | ||
2739 | /* We don't really know why we're doing this */ |
- | |
2740 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
- | |
2741 | 3233 | ||
2742 | if (HAS_PCH_IBX(dev) && |
3234 | if (HAS_PCH_IBX(dev) && |
2743 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
3235 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
2744 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
3236 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
2745 | 3237 | ||
2746 | /* Hardware workaround: leaving our transcoder select |
3238 | /* Hardware workaround: leaving our transcoder select |
2747 | * set to transcoder B while it's off will prevent the |
3239 | * set to transcoder B while it's off will prevent the |
2748 | * corresponding HDMI output on transcoder A. |
3240 | * corresponding HDMI output on transcoder A. |
2749 | * |
3241 | * |
2750 | * Combine this with another hardware workaround: |
3242 | * Combine this with another hardware workaround: |
2751 | * transcoder select bit can only be cleared while the |
3243 | * transcoder select bit can only be cleared while the |
2752 | * port is enabled. |
3244 | * port is enabled. |
2753 | */ |
3245 | */ |
2754 | DP &= ~DP_PIPEB_SELECT; |
3246 | DP &= ~DP_PIPEB_SELECT; |
2755 | I915_WRITE(intel_dp->output_reg, DP); |
3247 | I915_WRITE(intel_dp->output_reg, DP); |
2756 | 3248 | ||
2757 | /* Changes to enable or select take place the vblank |
3249 | /* Changes to enable or select take place the vblank |
2758 | * after being written. |
3250 | * after being written. |
2759 | */ |
3251 | */ |
2760 | if (WARN_ON(crtc == NULL)) { |
3252 | if (WARN_ON(crtc == NULL)) { |
2761 | /* We should never try to disable a port without a crtc |
3253 | /* We should never try to disable a port without a crtc |
2762 | * attached. For paranoia keep the code around for a |
3254 | * attached. For paranoia keep the code around for a |
2763 | * bit. */ |
3255 | * bit. */ |
2764 | POSTING_READ(intel_dp->output_reg); |
3256 | POSTING_READ(intel_dp->output_reg); |
2765 | msleep(50); |
3257 | msleep(50); |
2766 | } else |
3258 | } else |
2767 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3259 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2768 | } |
3260 | } |
2769 | 3261 | ||
2770 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
3262 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
2771 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
3263 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
2772 | POSTING_READ(intel_dp->output_reg); |
3264 | POSTING_READ(intel_dp->output_reg); |
2773 | msleep(intel_dp->panel_power_down_delay); |
3265 | msleep(intel_dp->panel_power_down_delay); |
2774 | } |
3266 | } |
2775 | 3267 | ||
2776 | static bool |
3268 | static bool |
2777 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
3269 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
2778 | { |
3270 | { |
2779 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3271 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
2780 | struct drm_device *dev = dig_port->base.base.dev; |
3272 | struct drm_device *dev = dig_port->base.base.dev; |
2781 | struct drm_i915_private *dev_priv = dev->dev_private; |
3273 | struct drm_i915_private *dev_priv = dev->dev_private; |
2782 | 3274 | ||
2783 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
3275 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
2784 | 3276 | ||
2785 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
3277 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
2786 | sizeof(intel_dp->dpcd)) == 0) |
3278 | sizeof(intel_dp->dpcd)) < 0) |
2787 | return false; /* aux transfer failed */ |
3279 | return false; /* aux transfer failed */ |
2788 | 3280 | ||
2789 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
3281 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
2790 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
3282 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
2791 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
3283 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
2792 | 3284 | ||
2793 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3285 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
2794 | return false; /* DPCD not present */ |
3286 | return false; /* DPCD not present */ |
2795 | 3287 | ||
2796 | /* Check if the panel supports PSR */ |
3288 | /* Check if the panel supports PSR */ |
2797 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
3289 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
2798 | if (is_edp(intel_dp)) { |
3290 | if (is_edp(intel_dp)) { |
2799 | intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, |
3291 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
2800 | intel_dp->psr_dpcd, |
3292 | intel_dp->psr_dpcd, |
2801 | sizeof(intel_dp->psr_dpcd)); |
3293 | sizeof(intel_dp->psr_dpcd)); |
2802 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3294 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
2803 | dev_priv->psr.sink_support = true; |
3295 | dev_priv->psr.sink_support = true; |
2804 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
3296 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
2805 | } |
3297 | } |
2806 | } |
3298 | } |
- | 3299 | ||
- | 3300 | /* Training Pattern 3 support */ |
|
- | 3301 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && |
|
- | 3302 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { |
|
- | 3303 | intel_dp->use_tps3 = true; |
|
- | 3304 | DRM_DEBUG_KMS("Displayport TPS3 supported"); |
|
- | 3305 | } else |
|
- | 3306 | intel_dp->use_tps3 = false; |
|
2807 | 3307 | ||
2808 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3308 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
2809 | DP_DWN_STRM_PORT_PRESENT)) |
3309 | DP_DWN_STRM_PORT_PRESENT)) |
2810 | return true; /* native DP sink */ |
3310 | return true; /* native DP sink */ |
2811 | 3311 | ||
2812 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
3312 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
2813 | return true; /* no per-port downstream info */ |
3313 | return true; /* no per-port downstream info */ |
2814 | 3314 | ||
2815 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, |
3315 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
2816 | intel_dp->downstream_ports, |
3316 | intel_dp->downstream_ports, |
2817 | DP_MAX_DOWNSTREAM_PORTS) == 0) |
3317 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
2818 | return false; /* downstream port status fetch failed */ |
3318 | return false; /* downstream port status fetch failed */ |
2819 | 3319 | ||
2820 | return true; |
3320 | return true; |
2821 | } |
3321 | } |
2822 | 3322 | ||
2823 | static void |
3323 | static void |
2824 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
3324 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
2825 | { |
3325 | { |
2826 | u8 buf[3]; |
3326 | u8 buf[3]; |
2827 | 3327 | ||
2828 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
3328 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
2829 | return; |
3329 | return; |
2830 | 3330 | ||
2831 | ironlake_edp_panel_vdd_on(intel_dp); |
3331 | intel_edp_panel_vdd_on(intel_dp); |
2832 | 3332 | ||
2833 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
3333 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
2834 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3334 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
2835 | buf[0], buf[1], buf[2]); |
3335 | buf[0], buf[1], buf[2]); |
2836 | 3336 | ||
2837 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) |
3337 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
2838 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3338 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
2839 | buf[0], buf[1], buf[2]); |
3339 | buf[0], buf[1], buf[2]); |
2840 | 3340 | ||
- | 3341 | edp_panel_vdd_off(intel_dp, false); |
|
- | 3342 | } |
|
- | 3343 | ||
- | 3344 | static bool |
|
- | 3345 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
|
- | 3346 | { |
|
- | 3347 | u8 buf[1]; |
|
- | 3348 | ||
- | 3349 | if (!intel_dp->can_mst) |
|
- | 3350 | return false; |
|
- | 3351 | ||
- | 3352 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
|
- | 3353 | return false; |
|
- | 3354 | ||
- | 3355 | _edp_panel_vdd_on(intel_dp); |
|
- | 3356 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
|
- | 3357 | if (buf[0] & DP_MST_CAP) { |
|
- | 3358 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
|
- | 3359 | intel_dp->is_mst = true; |
|
- | 3360 | } else { |
|
- | 3361 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
|
- | 3362 | intel_dp->is_mst = false; |
|
- | 3363 | } |
|
- | 3364 | } |
|
- | 3365 | edp_panel_vdd_off(intel_dp, false); |
|
- | 3366 | ||
- | 3367 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
|
- | 3368 | return intel_dp->is_mst; |
|
- | 3369 | } |
|
- | 3370 | ||
- | 3371 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
|
- | 3372 | { |
|
- | 3373 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 3374 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 3375 | struct intel_crtc *intel_crtc = |
|
- | 3376 | to_intel_crtc(intel_dig_port->base.base.crtc); |
|
- | 3377 | u8 buf[1]; |
|
- | 3378 | ||
- | 3379 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) |
|
- | 3380 | return -EAGAIN; |
|
- | 3381 | ||
- | 3382 | if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) |
|
- | 3383 | return -ENOTTY; |
|
- | 3384 | ||
- | 3385 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
|
- | 3386 | DP_TEST_SINK_START) < 0) |
|
- | 3387 | return -EAGAIN; |
|
- | 3388 | ||
- | 3389 | /* Wait 2 vblanks to be sure we will have the correct CRC value */ |
|
- | 3390 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
|
- | 3391 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
|
- | 3392 | ||
- | 3393 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
|
- | 3394 | return -EAGAIN; |
|
- | 3395 | ||
- | 3396 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); |
|
2841 | ironlake_edp_panel_vdd_off(intel_dp, false); |
3397 | return 0; |
2842 | } |
3398 | } |
2843 | 3399 | ||
2844 | static bool |
3400 | static bool |
2845 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
3401 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
2846 | { |
3402 | { |
- | 3403 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
|
- | 3404 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
|
- | 3405 | sink_irq_vector, 1) == 1; |
|
- | 3406 | } |
|
- | 3407 | ||
- | 3408 | static bool |
|
- | 3409 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
|
- | 3410 | { |
|
2847 | int ret; |
3411 | int ret; |
2848 | 3412 | ||
2849 | ret = intel_dp_aux_native_read_retry(intel_dp, |
3413 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
2850 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3414 | DP_SINK_COUNT_ESI, |
2851 | sink_irq_vector, 1); |
3415 | sink_irq_vector, 14); |
2852 | if (!ret) |
3416 | if (ret != 14) |
2853 | return false; |
3417 | return false; |
2854 | 3418 | ||
2855 | return true; |
3419 | return true; |
2856 | } |
3420 | } |
2857 | 3421 | ||
2858 | static void |
3422 | static void |
2859 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
3423 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
2860 | { |
3424 | { |
2861 | /* NAK by default */ |
3425 | /* NAK by default */ |
2862 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
3426 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); |
- | 3427 | } |
|
- | 3428 | ||
- | 3429 | static int |
|
- | 3430 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
|
- | 3431 | { |
|
- | 3432 | bool bret; |
|
- | 3433 | ||
- | 3434 | if (intel_dp->is_mst) { |
|
- | 3435 | u8 esi[16] = { 0 }; |
|
- | 3436 | int ret = 0; |
|
- | 3437 | int retry; |
|
- | 3438 | bool handled; |
|
- | 3439 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
|
- | 3440 | go_again: |
|
- | 3441 | if (bret == true) { |
|
- | 3442 | ||
- | 3443 | /* check link status - esi[10] = 0x200c */ |
|
- | 3444 | if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
|
- | 3445 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
|
- | 3446 | intel_dp_start_link_train(intel_dp); |
|
- | 3447 | intel_dp_complete_link_train(intel_dp); |
|
- | 3448 | intel_dp_stop_link_train(intel_dp); |
|
- | 3449 | } |
|
- | 3450 | ||
- | 3451 | DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
|
- | 3452 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
|
- | 3453 | ||
- | 3454 | if (handled) { |
|
- | 3455 | for (retry = 0; retry < 3; retry++) { |
|
- | 3456 | int wret; |
|
- | 3457 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
|
- | 3458 | DP_SINK_COUNT_ESI+1, |
|
- | 3459 | &esi[1], 3); |
|
- | 3460 | if (wret == 3) { |
|
- | 3461 | break; |
|
- | 3462 | } |
|
- | 3463 | } |
|
- | 3464 | ||
- | 3465 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
|
- | 3466 | if (bret == true) { |
|
- | 3467 | DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
|
- | 3468 | goto go_again; |
|
- | 3469 | } |
|
- | 3470 | } else |
|
- | 3471 | ret = 0; |
|
- | 3472 | ||
- | 3473 | return ret; |
|
- | 3474 | } else { |
|
- | 3475 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 3476 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
|
- | 3477 | intel_dp->is_mst = false; |
|
- | 3478 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
|
- | 3479 | /* send a hotplug event */ |
|
- | 3480 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
|
- | 3481 | } |
|
- | 3482 | } |
|
- | 3483 | return -EINVAL; |
|
2863 | } |
3484 | } |
2864 | 3485 | ||
2865 | /* |
3486 | /* |
2866 | * According to DP spec |
3487 | * According to DP spec |
2867 | * 5.1.2: |
3488 | * 5.1.2: |
2868 | * 1. Read DPCD |
3489 | * 1. Read DPCD |
2869 | * 2. Configure link according to Receiver Capabilities |
3490 | * 2. Configure link according to Receiver Capabilities |
2870 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
3491 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
2871 | * 4. Check link status on receipt of hot-plug interrupt |
3492 | * 4. Check link status on receipt of hot-plug interrupt |
2872 | */ |
3493 | */ |
2873 | - | ||
2874 | void |
3494 | void |
2875 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
3495 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
2876 | { |
3496 | { |
- | 3497 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
2877 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
3498 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
2878 | u8 sink_irq_vector; |
3499 | u8 sink_irq_vector; |
2879 | u8 link_status[DP_LINK_STATUS_SIZE]; |
3500 | u8 link_status[DP_LINK_STATUS_SIZE]; |
- | 3501 | ||
- | 3502 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
|
2880 | 3503 | ||
2881 | if (!intel_encoder->connectors_active) |
3504 | if (!intel_encoder->connectors_active) |
2882 | return; |
3505 | return; |
2883 | 3506 | ||
2884 | if (WARN_ON(!intel_encoder->base.crtc)) |
3507 | if (WARN_ON(!intel_encoder->base.crtc)) |
2885 | return; |
3508 | return; |
- | 3509 | ||
- | 3510 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
|
- | 3511 | return; |
|
2886 | 3512 | ||
2887 | /* Try to read receiver status if the link appears to be up */ |
3513 | /* Try to read receiver status if the link appears to be up */ |
2888 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3514 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2889 | return; |
3515 | return; |
2890 | } |
3516 | } |
2891 | 3517 | ||
2892 | /* Now read the DPCD to see if it's actually running */ |
3518 | /* Now read the DPCD to see if it's actually running */ |
2893 | if (!intel_dp_get_dpcd(intel_dp)) { |
3519 | if (!intel_dp_get_dpcd(intel_dp)) { |
2894 | return; |
3520 | return; |
2895 | } |
3521 | } |
2896 | 3522 | ||
2897 | /* Try to read the source of the interrupt */ |
3523 | /* Try to read the source of the interrupt */ |
2898 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3524 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
2899 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
3525 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
2900 | /* Clear interrupt source */ |
3526 | /* Clear interrupt source */ |
2901 | intel_dp_aux_native_write_1(intel_dp, |
3527 | drm_dp_dpcd_writeb(&intel_dp->aux, |
2902 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3528 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
2903 | sink_irq_vector); |
3529 | sink_irq_vector); |
2904 | 3530 | ||
2905 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
3531 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
2906 | intel_dp_handle_test_request(intel_dp); |
3532 | intel_dp_handle_test_request(intel_dp); |
2907 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
3533 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
2908 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
3534 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
2909 | } |
3535 | } |
2910 | 3536 | ||
2911 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
3537 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
2912 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
3538 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
2913 | drm_get_encoder_name(&intel_encoder->base)); |
3539 | intel_encoder->base.name); |
2914 | intel_dp_start_link_train(intel_dp); |
3540 | intel_dp_start_link_train(intel_dp); |
2915 | intel_dp_complete_link_train(intel_dp); |
3541 | intel_dp_complete_link_train(intel_dp); |
2916 | intel_dp_stop_link_train(intel_dp); |
3542 | intel_dp_stop_link_train(intel_dp); |
2917 | } |
3543 | } |
2918 | } |
3544 | } |
2919 | 3545 | ||
2920 | /* XXX this is probably wrong for multiple downstream ports */ |
3546 | /* XXX this is probably wrong for multiple downstream ports */ |
2921 | static enum drm_connector_status |
3547 | static enum drm_connector_status |
2922 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
3548 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
2923 | { |
3549 | { |
2924 | uint8_t *dpcd = intel_dp->dpcd; |
3550 | uint8_t *dpcd = intel_dp->dpcd; |
2925 | uint8_t type; |
3551 | uint8_t type; |
2926 | 3552 | ||
2927 | if (!intel_dp_get_dpcd(intel_dp)) |
3553 | if (!intel_dp_get_dpcd(intel_dp)) |
2928 | return connector_status_disconnected; |
3554 | return connector_status_disconnected; |
2929 | 3555 | ||
2930 | /* if there's no downstream port, we're done */ |
3556 | /* if there's no downstream port, we're done */ |
2931 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
3557 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
2932 | return connector_status_connected; |
3558 | return connector_status_connected; |
2933 | 3559 | ||
2934 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
3560 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
2935 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3561 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
2936 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
3562 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
2937 | uint8_t reg; |
3563 | uint8_t reg; |
- | 3564 | ||
2938 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, |
3565 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
2939 | ®, 1)) |
3566 | ®, 1) < 0) |
2940 | return connector_status_unknown; |
3567 | return connector_status_unknown; |
- | 3568 | ||
2941 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
3569 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
2942 | : connector_status_disconnected; |
3570 | : connector_status_disconnected; |
2943 | } |
3571 | } |
2944 | 3572 | ||
2945 | /* If no HPD, poke DDC gently */ |
3573 | /* If no HPD, poke DDC gently */ |
2946 | if (drm_probe_ddc(&intel_dp->adapter)) |
3574 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
2947 | return connector_status_connected; |
3575 | return connector_status_connected; |
2948 | 3576 | ||
2949 | /* Well we tried, say unknown for unreliable port types */ |
3577 | /* Well we tried, say unknown for unreliable port types */ |
2950 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
3578 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
2951 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
3579 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
2952 | if (type == DP_DS_PORT_TYPE_VGA || |
3580 | if (type == DP_DS_PORT_TYPE_VGA || |
2953 | type == DP_DS_PORT_TYPE_NON_EDID) |
3581 | type == DP_DS_PORT_TYPE_NON_EDID) |
2954 | return connector_status_unknown; |
3582 | return connector_status_unknown; |
2955 | } else { |
3583 | } else { |
2956 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3584 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
2957 | DP_DWN_STRM_PORT_TYPE_MASK; |
3585 | DP_DWN_STRM_PORT_TYPE_MASK; |
2958 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
3586 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
2959 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
3587 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
2960 | return connector_status_unknown; |
3588 | return connector_status_unknown; |
2961 | } |
3589 | } |
2962 | 3590 | ||
2963 | /* Anything else is out of spec, warn and ignore */ |
3591 | /* Anything else is out of spec, warn and ignore */ |
2964 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
3592 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
2965 | return connector_status_disconnected; |
3593 | return connector_status_disconnected; |
2966 | } |
3594 | } |
2967 | 3595 | ||
2968 | static enum drm_connector_status |
3596 | static enum drm_connector_status |
2969 | ironlake_dp_detect(struct intel_dp *intel_dp) |
3597 | ironlake_dp_detect(struct intel_dp *intel_dp) |
2970 | { |
3598 | { |
2971 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3599 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2972 | struct drm_i915_private *dev_priv = dev->dev_private; |
3600 | struct drm_i915_private *dev_priv = dev->dev_private; |
2973 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3601 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2974 | enum drm_connector_status status; |
3602 | enum drm_connector_status status; |
2975 | 3603 | ||
2976 | /* Can't disconnect eDP, but you can close the lid... */ |
3604 | /* Can't disconnect eDP, but you can close the lid... */ |
2977 | if (is_edp(intel_dp)) { |
3605 | if (is_edp(intel_dp)) { |
2978 | status = intel_panel_detect(dev); |
3606 | status = intel_panel_detect(dev); |
2979 | if (status == connector_status_unknown) |
3607 | if (status == connector_status_unknown) |
2980 | status = connector_status_connected; |
3608 | status = connector_status_connected; |
2981 | return status; |
3609 | return status; |
2982 | } |
3610 | } |
2983 | 3611 | ||
2984 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
3612 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
2985 | return connector_status_disconnected; |
3613 | return connector_status_disconnected; |
2986 | 3614 | ||
2987 | return intel_dp_detect_dpcd(intel_dp); |
3615 | return intel_dp_detect_dpcd(intel_dp); |
2988 | } |
3616 | } |
2989 | 3617 | ||
2990 | static enum drm_connector_status |
3618 | static enum drm_connector_status |
2991 | g4x_dp_detect(struct intel_dp *intel_dp) |
3619 | g4x_dp_detect(struct intel_dp *intel_dp) |
2992 | { |
3620 | { |
2993 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3621 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2994 | struct drm_i915_private *dev_priv = dev->dev_private; |
3622 | struct drm_i915_private *dev_priv = dev->dev_private; |
2995 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3623 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2996 | uint32_t bit; |
3624 | uint32_t bit; |
2997 | 3625 | ||
2998 | /* Can't disconnect eDP, but you can close the lid... */ |
3626 | /* Can't disconnect eDP, but you can close the lid... */ |
2999 | if (is_edp(intel_dp)) { |
3627 | if (is_edp(intel_dp)) { |
3000 | enum drm_connector_status status; |
3628 | enum drm_connector_status status; |
3001 | 3629 | ||
3002 | status = intel_panel_detect(dev); |
3630 | status = intel_panel_detect(dev); |
3003 | if (status == connector_status_unknown) |
3631 | if (status == connector_status_unknown) |
3004 | status = connector_status_connected; |
3632 | status = connector_status_connected; |
3005 | return status; |
3633 | return status; |
3006 | } |
3634 | } |
3007 | 3635 | ||
3008 | if (IS_VALLEYVIEW(dev)) { |
3636 | if (IS_VALLEYVIEW(dev)) { |
3009 | switch (intel_dig_port->port) { |
3637 | switch (intel_dig_port->port) { |
3010 | case PORT_B: |
3638 | case PORT_B: |
3011 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; |
3639 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; |
3012 | break; |
3640 | break; |
3013 | case PORT_C: |
3641 | case PORT_C: |
3014 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; |
3642 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; |
3015 | break; |
3643 | break; |
3016 | case PORT_D: |
3644 | case PORT_D: |
3017 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; |
3645 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; |
3018 | break; |
3646 | break; |
3019 | default: |
3647 | default: |
3020 | return connector_status_unknown; |
3648 | return connector_status_unknown; |
3021 | } |
3649 | } |
3022 | } else { |
3650 | } else { |
3023 | switch (intel_dig_port->port) { |
3651 | switch (intel_dig_port->port) { |
3024 | case PORT_B: |
3652 | case PORT_B: |
3025 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
3653 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
3026 | break; |
3654 | break; |
3027 | case PORT_C: |
3655 | case PORT_C: |
3028 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
3656 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
3029 | break; |
3657 | break; |
3030 | case PORT_D: |
3658 | case PORT_D: |
3031 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
3659 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
3032 | break; |
3660 | break; |
3033 | default: |
3661 | default: |
3034 | return connector_status_unknown; |
3662 | return connector_status_unknown; |
3035 | } |
3663 | } |
3036 | } |
3664 | } |
3037 | 3665 | ||
3038 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
3666 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
3039 | return connector_status_disconnected; |
3667 | return connector_status_disconnected; |
3040 | 3668 | ||
3041 | return intel_dp_detect_dpcd(intel_dp); |
3669 | return intel_dp_detect_dpcd(intel_dp); |
3042 | } |
3670 | } |
3043 | 3671 | ||
3044 | static struct edid * |
3672 | static struct edid * |
3045 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
3673 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
3046 | { |
3674 | { |
3047 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3675 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3048 | 3676 | ||
3049 | /* use cached edid if we have one */ |
3677 | /* use cached edid if we have one */ |
3050 | if (intel_connector->edid) { |
3678 | if (intel_connector->edid) { |
3051 | /* invalid edid */ |
3679 | /* invalid edid */ |
3052 | if (IS_ERR(intel_connector->edid)) |
3680 | if (IS_ERR(intel_connector->edid)) |
3053 | return NULL; |
3681 | return NULL; |
3054 | 3682 | ||
3055 | return drm_edid_duplicate(intel_connector->edid); |
3683 | return drm_edid_duplicate(intel_connector->edid); |
3056 | } |
3684 | } |
3057 | 3685 | ||
3058 | return drm_get_edid(connector, adapter); |
3686 | return drm_get_edid(connector, adapter); |
3059 | } |
3687 | } |
3060 | 3688 | ||
3061 | static int |
3689 | static int |
3062 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
3690 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
3063 | { |
3691 | { |
3064 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3692 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3065 | 3693 | ||
3066 | /* use cached edid if we have one */ |
3694 | /* use cached edid if we have one */ |
3067 | if (intel_connector->edid) { |
3695 | if (intel_connector->edid) { |
3068 | /* invalid edid */ |
3696 | /* invalid edid */ |
3069 | if (IS_ERR(intel_connector->edid)) |
3697 | if (IS_ERR(intel_connector->edid)) |
3070 | return 0; |
3698 | return 0; |
3071 | 3699 | ||
3072 | return intel_connector_update_modes(connector, |
3700 | return intel_connector_update_modes(connector, |
3073 | intel_connector->edid); |
3701 | intel_connector->edid); |
3074 | } |
3702 | } |
3075 | 3703 | ||
3076 | return intel_ddc_get_modes(connector, adapter); |
3704 | return intel_ddc_get_modes(connector, adapter); |
3077 | } |
3705 | } |
3078 | 3706 | ||
3079 | static enum drm_connector_status |
3707 | static enum drm_connector_status |
3080 | intel_dp_detect(struct drm_connector *connector, bool force) |
3708 | intel_dp_detect(struct drm_connector *connector, bool force) |
3081 | { |
3709 | { |
3082 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
3710 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
3083 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3711 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3084 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
3712 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
3085 | struct drm_device *dev = connector->dev; |
3713 | struct drm_device *dev = connector->dev; |
3086 | struct drm_i915_private *dev_priv = dev->dev_private; |
3714 | struct drm_i915_private *dev_priv = dev->dev_private; |
3087 | enum drm_connector_status status; |
3715 | enum drm_connector_status status; |
- | 3716 | enum intel_display_power_domain power_domain; |
|
3088 | struct edid *edid = NULL; |
3717 | struct edid *edid = NULL; |
- | 3718 | bool ret; |
|
- | 3719 | ||
3089 | 3720 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
3090 | intel_runtime_pm_get(dev_priv); |
3721 | intel_display_power_get(dev_priv, power_domain); |
3091 | 3722 | ||
- | 3723 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
|
- | 3724 | connector->base.id, connector->name); |
|
- | 3725 | ||
- | 3726 | if (intel_dp->is_mst) { |
|
- | 3727 | /* MST devices are disconnected from a monitor POV */ |
|
- | 3728 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
|
- | 3729 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
|
- | 3730 | status = connector_status_disconnected; |
|
3092 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3731 | goto out; |
3093 | connector->base.id, drm_get_connector_name(connector)); |
3732 | } |
3094 | 3733 | ||
3095 | intel_dp->has_audio = false; |
3734 | intel_dp->has_audio = false; |
3096 | 3735 | ||
3097 | if (HAS_PCH_SPLIT(dev)) |
3736 | if (HAS_PCH_SPLIT(dev)) |
3098 | status = ironlake_dp_detect(intel_dp); |
3737 | status = ironlake_dp_detect(intel_dp); |
3099 | else |
3738 | else |
3100 | status = g4x_dp_detect(intel_dp); |
3739 | status = g4x_dp_detect(intel_dp); |
3101 | 3740 | ||
3102 | if (status != connector_status_connected) |
3741 | if (status != connector_status_connected) |
3103 | goto out; |
3742 | goto out; |
3104 | 3743 | ||
3105 | intel_dp_probe_oui(intel_dp); |
3744 | intel_dp_probe_oui(intel_dp); |
- | 3745 | ||
- | 3746 | ret = intel_dp_probe_mst(intel_dp); |
|
- | 3747 | if (ret) { |
|
- | 3748 | /* if we are in MST mode then this connector |
|
- | 3749 | won't appear connected or have anything with EDID on it */ |
|
- | 3750 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
|
- | 3751 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
|
- | 3752 | status = connector_status_disconnected; |
|
- | 3753 | goto out; |
|
- | 3754 | } |
|
3106 | 3755 | ||
3107 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
3756 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
3108 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
3757 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
3109 | } else { |
3758 | } else { |
3110 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
3759 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
3111 | if (edid) { |
3760 | if (edid) { |
3112 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
3761 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
3113 | kfree(edid); |
3762 | kfree(edid); |
3114 | } |
3763 | } |
3115 | } |
3764 | } |
3116 | 3765 | ||
3117 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
3766 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
3118 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
3767 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
3119 | status = connector_status_connected; |
3768 | status = connector_status_connected; |
3120 | 3769 | ||
3121 | out: |
3770 | out: |
3122 | intel_runtime_pm_put(dev_priv); |
3771 | intel_display_power_put(dev_priv, power_domain); |
3123 | return status; |
3772 | return status; |
3124 | } |
3773 | } |
3125 | 3774 | ||
3126 | static int intel_dp_get_modes(struct drm_connector *connector) |
3775 | static int intel_dp_get_modes(struct drm_connector *connector) |
3127 | { |
3776 | { |
3128 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
3777 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
- | 3778 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 3779 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
3129 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3780 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3130 | struct drm_device *dev = connector->dev; |
3781 | struct drm_device *dev = connector->dev; |
- | 3782 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3783 | enum intel_display_power_domain power_domain; |
|
3131 | int ret; |
3784 | int ret; |
3132 | 3785 | ||
3133 | /* We should parse the EDID data and find out if it has an audio sink |
3786 | /* We should parse the EDID data and find out if it has an audio sink |
3134 | */ |
3787 | */ |
- | 3788 | ||
- | 3789 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
- | 3790 | intel_display_power_get(dev_priv, power_domain); |
|
3135 | 3791 | ||
- | 3792 | ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); |
|
3136 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
3793 | intel_display_power_put(dev_priv, power_domain); |
3137 | if (ret) |
3794 | if (ret) |
3138 | return ret; |
3795 | return ret; |
3139 | 3796 | ||
3140 | /* if eDP has no EDID, fall back to fixed mode */ |
3797 | /* if eDP has no EDID, fall back to fixed mode */ |
3141 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
3798 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
3142 | struct drm_display_mode *mode; |
3799 | struct drm_display_mode *mode; |
3143 | mode = drm_mode_duplicate(dev, |
3800 | mode = drm_mode_duplicate(dev, |
3144 | intel_connector->panel.fixed_mode); |
3801 | intel_connector->panel.fixed_mode); |
3145 | if (mode) { |
3802 | if (mode) { |
3146 | drm_mode_probed_add(connector, mode); |
3803 | drm_mode_probed_add(connector, mode); |
3147 | return 1; |
3804 | return 1; |
3148 | } |
3805 | } |
3149 | } |
3806 | } |
3150 | return 0; |
3807 | return 0; |
3151 | } |
3808 | } |
3152 | 3809 | ||
3153 | static bool |
3810 | static bool |
3154 | intel_dp_detect_audio(struct drm_connector *connector) |
3811 | intel_dp_detect_audio(struct drm_connector *connector) |
3155 | { |
3812 | { |
3156 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
3813 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
- | 3814 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 3815 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
- | 3816 | struct drm_device *dev = connector->dev; |
|
- | 3817 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 3818 | enum intel_display_power_domain power_domain; |
|
3157 | struct edid *edid; |
3819 | struct edid *edid; |
3158 | bool has_audio = false; |
3820 | bool has_audio = false; |
- | 3821 | ||
- | 3822 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
- | 3823 | intel_display_power_get(dev_priv, power_domain); |
|
3159 | 3824 | ||
3160 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
3825 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
3161 | if (edid) { |
3826 | if (edid) { |
3162 | has_audio = drm_detect_monitor_audio(edid); |
3827 | has_audio = drm_detect_monitor_audio(edid); |
3163 | kfree(edid); |
3828 | kfree(edid); |
3164 | } |
3829 | } |
- | 3830 | ||
- | 3831 | intel_display_power_put(dev_priv, power_domain); |
|
3165 | 3832 | ||
3166 | return has_audio; |
3833 | return has_audio; |
3167 | } |
3834 | } |
3168 | 3835 | ||
3169 | static int |
3836 | static int |
3170 | intel_dp_set_property(struct drm_connector *connector, |
3837 | intel_dp_set_property(struct drm_connector *connector, |
3171 | struct drm_property *property, |
3838 | struct drm_property *property, |
3172 | uint64_t val) |
3839 | uint64_t val) |
3173 | { |
3840 | { |
3174 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
3841 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
3175 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3842 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3176 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
3843 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
3177 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
3844 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
3178 | int ret; |
3845 | int ret; |
3179 | 3846 | ||
3180 | ret = drm_object_property_set_value(&connector->base, property, val); |
3847 | ret = drm_object_property_set_value(&connector->base, property, val); |
3181 | if (ret) |
3848 | if (ret) |
3182 | return ret; |
3849 | return ret; |
3183 | 3850 | ||
3184 | if (property == dev_priv->force_audio_property) { |
3851 | if (property == dev_priv->force_audio_property) { |
3185 | int i = val; |
3852 | int i = val; |
3186 | bool has_audio; |
3853 | bool has_audio; |
3187 | 3854 | ||
3188 | if (i == intel_dp->force_audio) |
3855 | if (i == intel_dp->force_audio) |
3189 | return 0; |
3856 | return 0; |
3190 | 3857 | ||
3191 | intel_dp->force_audio = i; |
3858 | intel_dp->force_audio = i; |
3192 | 3859 | ||
3193 | if (i == HDMI_AUDIO_AUTO) |
3860 | if (i == HDMI_AUDIO_AUTO) |
3194 | has_audio = intel_dp_detect_audio(connector); |
3861 | has_audio = intel_dp_detect_audio(connector); |
3195 | else |
3862 | else |
3196 | has_audio = (i == HDMI_AUDIO_ON); |
3863 | has_audio = (i == HDMI_AUDIO_ON); |
3197 | 3864 | ||
3198 | if (has_audio == intel_dp->has_audio) |
3865 | if (has_audio == intel_dp->has_audio) |
3199 | return 0; |
3866 | return 0; |
3200 | 3867 | ||
3201 | intel_dp->has_audio = has_audio; |
3868 | intel_dp->has_audio = has_audio; |
3202 | goto done; |
3869 | goto done; |
3203 | } |
3870 | } |
3204 | 3871 | ||
3205 | if (property == dev_priv->broadcast_rgb_property) { |
3872 | if (property == dev_priv->broadcast_rgb_property) { |
3206 | bool old_auto = intel_dp->color_range_auto; |
3873 | bool old_auto = intel_dp->color_range_auto; |
3207 | uint32_t old_range = intel_dp->color_range; |
3874 | uint32_t old_range = intel_dp->color_range; |
3208 | 3875 | ||
3209 | switch (val) { |
3876 | switch (val) { |
3210 | case INTEL_BROADCAST_RGB_AUTO: |
3877 | case INTEL_BROADCAST_RGB_AUTO: |
3211 | intel_dp->color_range_auto = true; |
3878 | intel_dp->color_range_auto = true; |
3212 | break; |
3879 | break; |
3213 | case INTEL_BROADCAST_RGB_FULL: |
3880 | case INTEL_BROADCAST_RGB_FULL: |
3214 | intel_dp->color_range_auto = false; |
3881 | intel_dp->color_range_auto = false; |
3215 | intel_dp->color_range = 0; |
3882 | intel_dp->color_range = 0; |
3216 | break; |
3883 | break; |
3217 | case INTEL_BROADCAST_RGB_LIMITED: |
3884 | case INTEL_BROADCAST_RGB_LIMITED: |
3218 | intel_dp->color_range_auto = false; |
3885 | intel_dp->color_range_auto = false; |
3219 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
3886 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
3220 | break; |
3887 | break; |
3221 | default: |
3888 | default: |
3222 | return -EINVAL; |
3889 | return -EINVAL; |
3223 | } |
3890 | } |
3224 | 3891 | ||
3225 | if (old_auto == intel_dp->color_range_auto && |
3892 | if (old_auto == intel_dp->color_range_auto && |
3226 | old_range == intel_dp->color_range) |
3893 | old_range == intel_dp->color_range) |
3227 | return 0; |
3894 | return 0; |
3228 | 3895 | ||
3229 | goto done; |
3896 | goto done; |
3230 | } |
3897 | } |
3231 | 3898 | ||
3232 | if (is_edp(intel_dp) && |
3899 | if (is_edp(intel_dp) && |
3233 | property == connector->dev->mode_config.scaling_mode_property) { |
3900 | property == connector->dev->mode_config.scaling_mode_property) { |
3234 | if (val == DRM_MODE_SCALE_NONE) { |
3901 | if (val == DRM_MODE_SCALE_NONE) { |
3235 | DRM_DEBUG_KMS("no scaling not supported\n"); |
3902 | DRM_DEBUG_KMS("no scaling not supported\n"); |
3236 | return -EINVAL; |
3903 | return -EINVAL; |
3237 | } |
3904 | } |
3238 | 3905 | ||
3239 | if (intel_connector->panel.fitting_mode == val) { |
3906 | if (intel_connector->panel.fitting_mode == val) { |
3240 | /* the eDP scaling property is not changed */ |
3907 | /* the eDP scaling property is not changed */ |
3241 | return 0; |
3908 | return 0; |
3242 | } |
3909 | } |
3243 | intel_connector->panel.fitting_mode = val; |
3910 | intel_connector->panel.fitting_mode = val; |
3244 | 3911 | ||
3245 | goto done; |
3912 | goto done; |
3246 | } |
3913 | } |
3247 | 3914 | ||
3248 | return -EINVAL; |
3915 | return -EINVAL; |
3249 | 3916 | ||
3250 | done: |
3917 | done: |
3251 | if (intel_encoder->base.crtc) |
3918 | if (intel_encoder->base.crtc) |
3252 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
3919 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
3253 | 3920 | ||
3254 | return 0; |
3921 | return 0; |
3255 | } |
3922 | } |
3256 | 3923 | ||
3257 | static void |
3924 | static void |
3258 | intel_dp_connector_destroy(struct drm_connector *connector) |
3925 | intel_dp_connector_destroy(struct drm_connector *connector) |
3259 | { |
3926 | { |
3260 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3927 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3261 | 3928 | ||
3262 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
3929 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
3263 | kfree(intel_connector->edid); |
3930 | kfree(intel_connector->edid); |
3264 | 3931 | ||
3265 | /* Can't call is_edp() since the encoder may have been destroyed |
3932 | /* Can't call is_edp() since the encoder may have been destroyed |
3266 | * already. */ |
3933 | * already. */ |
3267 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
3934 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
3268 | intel_panel_fini(&intel_connector->panel); |
3935 | intel_panel_fini(&intel_connector->panel); |
3269 | 3936 | ||
3270 | drm_connector_cleanup(connector); |
3937 | drm_connector_cleanup(connector); |
3271 | kfree(connector); |
3938 | kfree(connector); |
3272 | } |
3939 | } |
3273 | 3940 | ||
3274 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
3941 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
3275 | { |
3942 | { |
3276 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3943 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3277 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
3944 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
3278 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3945 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3279 | 3946 | ||
- | 3947 | drm_dp_aux_unregister(&intel_dp->aux); |
|
3280 | i2c_del_adapter(&intel_dp->adapter); |
3948 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
3281 | drm_encoder_cleanup(encoder); |
3949 | drm_encoder_cleanup(encoder); |
3282 | if (is_edp(intel_dp)) { |
3950 | if (is_edp(intel_dp)) { |
3283 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
3951 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
3284 | mutex_lock(&dev->mode_config.mutex); |
3952 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
3285 | ironlake_panel_vdd_off_sync(intel_dp); |
3953 | edp_panel_vdd_off_sync(intel_dp); |
3286 | mutex_unlock(&dev->mode_config.mutex); |
3954 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
3287 | } |
3955 | } |
3288 | kfree(intel_dig_port); |
3956 | kfree(intel_dig_port); |
3289 | } |
3957 | } |
- | 3958 | ||
- | 3959 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
|
- | 3960 | { |
|
- | 3961 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
|
- | 3962 | ||
- | 3963 | if (!is_edp(intel_dp)) |
|
- | 3964 | return; |
|
- | 3965 | ||
- | 3966 | edp_panel_vdd_off_sync(intel_dp); |
|
- | 3967 | } |
|
- | 3968 | ||
- | 3969 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
|
- | 3970 | { |
|
- | 3971 | intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); |
|
- | 3972 | } |
|
3290 | 3973 | ||
3291 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
3974 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
3292 | .dpms = intel_connector_dpms, |
3975 | .dpms = intel_connector_dpms, |
3293 | .detect = intel_dp_detect, |
3976 | .detect = intel_dp_detect, |
3294 | .fill_modes = drm_helper_probe_single_connector_modes, |
3977 | .fill_modes = drm_helper_probe_single_connector_modes, |
3295 | .set_property = intel_dp_set_property, |
3978 | .set_property = intel_dp_set_property, |
3296 | .destroy = intel_dp_connector_destroy, |
3979 | .destroy = intel_dp_connector_destroy, |
3297 | }; |
3980 | }; |
3298 | 3981 | ||
3299 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
3982 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
3300 | .get_modes = intel_dp_get_modes, |
3983 | .get_modes = intel_dp_get_modes, |
3301 | .mode_valid = intel_dp_mode_valid, |
3984 | .mode_valid = intel_dp_mode_valid, |
3302 | .best_encoder = intel_best_encoder, |
3985 | .best_encoder = intel_best_encoder, |
3303 | }; |
3986 | }; |
3304 | 3987 | ||
3305 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
3988 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
- | 3989 | .reset = intel_dp_encoder_reset, |
|
3306 | .destroy = intel_dp_encoder_destroy, |
3990 | .destroy = intel_dp_encoder_destroy, |
3307 | }; |
3991 | }; |
3308 | 3992 | ||
3309 | static void |
3993 | void |
3310 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
3994 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
- | 3995 | { |
|
- | 3996 | return; |
|
- | 3997 | } |
|
- | 3998 | ||
- | 3999 | bool |
|
- | 4000 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
|
3311 | { |
4001 | { |
- | 4002 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
|
- | 4003 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
- | 4004 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 4005 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4006 | enum intel_display_power_domain power_domain; |
|
- | 4007 | bool ret = true; |
|
- | 4008 | ||
- | 4009 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) |
|
- | 4010 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
|
- | 4011 | ||
- | 4012 | DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port, |
|
- | 4013 | long_hpd ? "long" : "short"); |
|
- | 4014 | ||
- | 4015 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
- | 4016 | intel_display_power_get(dev_priv, power_domain); |
|
- | 4017 | ||
- | 4018 | if (long_hpd) { |
|
- | 4019 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
|
- | 4020 | goto mst_fail; |
|
- | 4021 | ||
- | 4022 | if (!intel_dp_get_dpcd(intel_dp)) { |
|
- | 4023 | goto mst_fail; |
|
- | 4024 | } |
|
- | 4025 | ||
- | 4026 | intel_dp_probe_oui(intel_dp); |
|
- | 4027 | ||
- | 4028 | if (!intel_dp_probe_mst(intel_dp)) |
|
- | 4029 | goto mst_fail; |
|
- | 4030 | ||
- | 4031 | } else { |
|
- | 4032 | if (intel_dp->is_mst) { |
|
- | 4033 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
|
- | 4034 | goto mst_fail; |
|
- | 4035 | } |
|
- | 4036 | ||
- | 4037 | if (!intel_dp->is_mst) { |
|
- | 4038 | /* |
|
- | 4039 | * we'll check the link status via the normal hot plug path later - |
|
- | 4040 | * but for short hpds we should check it now |
|
3312 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4041 | */ |
- | 4042 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
|
- | 4043 | intel_dp_check_link_status(intel_dp); |
|
- | 4044 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
|
- | 4045 | } |
|
- | 4046 | } |
|
- | 4047 | ret = false; |
|
- | 4048 | goto put_power; |
|
- | 4049 | mst_fail: |
|
- | 4050 | /* if we were in MST mode, and device is not there get out of MST mode */ |
|
- | 4051 | if (intel_dp->is_mst) { |
|
- | 4052 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
|
- | 4053 | intel_dp->is_mst = false; |
|
- | 4054 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
|
- | 4055 | } |
|
- | 4056 | put_power: |
|
- | 4057 | intel_display_power_put(dev_priv, power_domain); |
|
3313 | 4058 | ||
3314 | intel_dp_check_link_status(intel_dp); |
4059 | return ret; |
3315 | } |
4060 | } |
3316 | 4061 | ||
3317 | /* Return which DP Port should be selected for Transcoder DP control */ |
4062 | /* Return which DP Port should be selected for Transcoder DP control */ |
3318 | int |
4063 | int |
3319 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
4064 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
3320 | { |
4065 | { |
3321 | struct drm_device *dev = crtc->dev; |
4066 | struct drm_device *dev = crtc->dev; |
3322 | struct intel_encoder *intel_encoder; |
4067 | struct intel_encoder *intel_encoder; |
3323 | struct intel_dp *intel_dp; |
4068 | struct intel_dp *intel_dp; |
3324 | 4069 | ||
3325 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
4070 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
3326 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4071 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
3327 | 4072 | ||
3328 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
4073 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
3329 | intel_encoder->type == INTEL_OUTPUT_EDP) |
4074 | intel_encoder->type == INTEL_OUTPUT_EDP) |
3330 | return intel_dp->output_reg; |
4075 | return intel_dp->output_reg; |
3331 | } |
4076 | } |
3332 | 4077 | ||
3333 | return -1; |
4078 | return -1; |
3334 | } |
4079 | } |
3335 | 4080 | ||
3336 | /* check the VBT to see whether the eDP is on DP-D port */ |
4081 | /* check the VBT to see whether the eDP is on DP-D port */ |
3337 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
4082 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
3338 | { |
4083 | { |
3339 | struct drm_i915_private *dev_priv = dev->dev_private; |
4084 | struct drm_i915_private *dev_priv = dev->dev_private; |
3340 | union child_device_config *p_child; |
4085 | union child_device_config *p_child; |
3341 | int i; |
4086 | int i; |
3342 | static const short port_mapping[] = { |
4087 | static const short port_mapping[] = { |
3343 | [PORT_B] = PORT_IDPB, |
4088 | [PORT_B] = PORT_IDPB, |
3344 | [PORT_C] = PORT_IDPC, |
4089 | [PORT_C] = PORT_IDPC, |
3345 | [PORT_D] = PORT_IDPD, |
4090 | [PORT_D] = PORT_IDPD, |
3346 | }; |
4091 | }; |
3347 | 4092 | ||
3348 | if (port == PORT_A) |
4093 | if (port == PORT_A) |
3349 | return true; |
4094 | return true; |
3350 | 4095 | ||
3351 | if (!dev_priv->vbt.child_dev_num) |
4096 | if (!dev_priv->vbt.child_dev_num) |
3352 | return false; |
4097 | return false; |
3353 | 4098 | ||
3354 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
4099 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
3355 | p_child = dev_priv->vbt.child_dev + i; |
4100 | p_child = dev_priv->vbt.child_dev + i; |
3356 | 4101 | ||
3357 | if (p_child->common.dvo_port == port_mapping[port] && |
4102 | if (p_child->common.dvo_port == port_mapping[port] && |
3358 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
4103 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
3359 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
4104 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
3360 | return true; |
4105 | return true; |
3361 | } |
4106 | } |
3362 | return false; |
4107 | return false; |
3363 | } |
4108 | } |
3364 | 4109 | ||
3365 | static void |
4110 | void |
3366 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
4111 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
3367 | { |
4112 | { |
3368 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4113 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3369 | 4114 | ||
3370 | intel_attach_force_audio_property(connector); |
4115 | intel_attach_force_audio_property(connector); |
3371 | intel_attach_broadcast_rgb_property(connector); |
4116 | intel_attach_broadcast_rgb_property(connector); |
3372 | intel_dp->color_range_auto = true; |
4117 | intel_dp->color_range_auto = true; |
3373 | 4118 | ||
3374 | if (is_edp(intel_dp)) { |
4119 | if (is_edp(intel_dp)) { |
3375 | drm_mode_create_scaling_mode_property(connector->dev); |
4120 | drm_mode_create_scaling_mode_property(connector->dev); |
3376 | drm_object_attach_property( |
4121 | drm_object_attach_property( |
3377 | &connector->base, |
4122 | &connector->base, |
3378 | connector->dev->mode_config.scaling_mode_property, |
4123 | connector->dev->mode_config.scaling_mode_property, |
3379 | DRM_MODE_SCALE_ASPECT); |
4124 | DRM_MODE_SCALE_ASPECT); |
3380 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
4125 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
3381 | } |
4126 | } |
3382 | } |
4127 | } |
- | 4128 | ||
- | 4129 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
|
- | 4130 | { |
|
- | 4131 | intel_dp->last_power_cycle = jiffies; |
|
- | 4132 | intel_dp->last_power_on = jiffies; |
|
- | 4133 | intel_dp->last_backlight_off = jiffies; |
|
- | 4134 | } |
|
3383 | 4135 | ||
3384 | static void |
4136 | static void |
3385 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
4137 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
3386 | struct intel_dp *intel_dp, |
4138 | struct intel_dp *intel_dp, |
3387 | struct edp_power_seq *out) |
4139 | struct edp_power_seq *out) |
3388 | { |
4140 | { |
3389 | struct drm_i915_private *dev_priv = dev->dev_private; |
4141 | struct drm_i915_private *dev_priv = dev->dev_private; |
3390 | struct edp_power_seq cur, vbt, spec, final; |
4142 | struct edp_power_seq cur, vbt, spec, final; |
3391 | u32 pp_on, pp_off, pp_div, pp; |
4143 | u32 pp_on, pp_off, pp_div, pp; |
3392 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
4144 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
3393 | 4145 | ||
3394 | if (HAS_PCH_SPLIT(dev)) { |
4146 | if (HAS_PCH_SPLIT(dev)) { |
3395 | pp_ctrl_reg = PCH_PP_CONTROL; |
4147 | pp_ctrl_reg = PCH_PP_CONTROL; |
3396 | pp_on_reg = PCH_PP_ON_DELAYS; |
4148 | pp_on_reg = PCH_PP_ON_DELAYS; |
3397 | pp_off_reg = PCH_PP_OFF_DELAYS; |
4149 | pp_off_reg = PCH_PP_OFF_DELAYS; |
3398 | pp_div_reg = PCH_PP_DIVISOR; |
4150 | pp_div_reg = PCH_PP_DIVISOR; |
3399 | } else { |
4151 | } else { |
3400 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
4152 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3401 | 4153 | ||
3402 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
4154 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
3403 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
4155 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
3404 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
4156 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
3405 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
4157 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
3406 | } |
4158 | } |
3407 | 4159 | ||
3408 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
4160 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
3409 | * the very first thing. */ |
4161 | * the very first thing. */ |
3410 | pp = ironlake_get_pp_control(intel_dp); |
4162 | pp = ironlake_get_pp_control(intel_dp); |
3411 | I915_WRITE(pp_ctrl_reg, pp); |
4163 | I915_WRITE(pp_ctrl_reg, pp); |
3412 | 4164 | ||
3413 | pp_on = I915_READ(pp_on_reg); |
4165 | pp_on = I915_READ(pp_on_reg); |
3414 | pp_off = I915_READ(pp_off_reg); |
4166 | pp_off = I915_READ(pp_off_reg); |
3415 | pp_div = I915_READ(pp_div_reg); |
4167 | pp_div = I915_READ(pp_div_reg); |
3416 | 4168 | ||
3417 | /* Pull timing values out of registers */ |
4169 | /* Pull timing values out of registers */ |
3418 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
4170 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
3419 | PANEL_POWER_UP_DELAY_SHIFT; |
4171 | PANEL_POWER_UP_DELAY_SHIFT; |
3420 | 4172 | ||
3421 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
4173 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
3422 | PANEL_LIGHT_ON_DELAY_SHIFT; |
4174 | PANEL_LIGHT_ON_DELAY_SHIFT; |
3423 | 4175 | ||
3424 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
4176 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
3425 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
4177 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
3426 | 4178 | ||
3427 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
4179 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
3428 | PANEL_POWER_DOWN_DELAY_SHIFT; |
4180 | PANEL_POWER_DOWN_DELAY_SHIFT; |
3429 | 4181 | ||
3430 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
4182 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
3431 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
4183 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
3432 | 4184 | ||
3433 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
4185 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
3434 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
4186 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
3435 | 4187 | ||
3436 | vbt = dev_priv->vbt.edp_pps; |
4188 | vbt = dev_priv->vbt.edp_pps; |
3437 | 4189 | ||
3438 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
4190 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
3439 | * our hw here, which are all in 100usec. */ |
4191 | * our hw here, which are all in 100usec. */ |
3440 | spec.t1_t3 = 210 * 10; |
4192 | spec.t1_t3 = 210 * 10; |
3441 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
4193 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
3442 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
4194 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
3443 | spec.t10 = 500 * 10; |
4195 | spec.t10 = 500 * 10; |
3444 | /* This one is special and actually in units of 100ms, but zero |
4196 | /* This one is special and actually in units of 100ms, but zero |
3445 | * based in the hw (so we need to add 100 ms). But the sw vbt |
4197 | * based in the hw (so we need to add 100 ms). But the sw vbt |
3446 | * table multiplies it with 1000 to make it in units of 100usec, |
4198 | * table multiplies it with 1000 to make it in units of 100usec, |
3447 | * too. */ |
4199 | * too. */ |
3448 | spec.t11_t12 = (510 + 100) * 10; |
4200 | spec.t11_t12 = (510 + 100) * 10; |
3449 | 4201 | ||
3450 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
4202 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
3451 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
4203 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
3452 | 4204 | ||
3453 | /* Use the max of the register settings and vbt. If both are |
4205 | /* Use the max of the register settings and vbt. If both are |
3454 | * unset, fall back to the spec limits. */ |
4206 | * unset, fall back to the spec limits. */ |
3455 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ |
4207 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ |
3456 | spec.field : \ |
4208 | spec.field : \ |
3457 | max(cur.field, vbt.field)) |
4209 | max(cur.field, vbt.field)) |
3458 | assign_final(t1_t3); |
4210 | assign_final(t1_t3); |
3459 | assign_final(t8); |
4211 | assign_final(t8); |
3460 | assign_final(t9); |
4212 | assign_final(t9); |
3461 | assign_final(t10); |
4213 | assign_final(t10); |
3462 | assign_final(t11_t12); |
4214 | assign_final(t11_t12); |
3463 | #undef assign_final |
4215 | #undef assign_final |
3464 | 4216 | ||
3465 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) |
4217 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) |
3466 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
4218 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
3467 | intel_dp->backlight_on_delay = get_delay(t8); |
4219 | intel_dp->backlight_on_delay = get_delay(t8); |
3468 | intel_dp->backlight_off_delay = get_delay(t9); |
4220 | intel_dp->backlight_off_delay = get_delay(t9); |
3469 | intel_dp->panel_power_down_delay = get_delay(t10); |
4221 | intel_dp->panel_power_down_delay = get_delay(t10); |
3470 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
4222 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
3471 | #undef get_delay |
4223 | #undef get_delay |
3472 | 4224 | ||
3473 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
4225 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
3474 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
4226 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
3475 | intel_dp->panel_power_cycle_delay); |
4227 | intel_dp->panel_power_cycle_delay); |
3476 | 4228 | ||
3477 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
4229 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
3478 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
4230 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
3479 | 4231 | ||
3480 | if (out) |
4232 | if (out) |
3481 | *out = final; |
4233 | *out = final; |
3482 | } |
4234 | } |
3483 | 4235 | ||
3484 | static void |
4236 | static void |
3485 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
4237 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
3486 | struct intel_dp *intel_dp, |
4238 | struct intel_dp *intel_dp, |
3487 | struct edp_power_seq *seq) |
4239 | struct edp_power_seq *seq) |
3488 | { |
4240 | { |
3489 | struct drm_i915_private *dev_priv = dev->dev_private; |
4241 | struct drm_i915_private *dev_priv = dev->dev_private; |
3490 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
4242 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
3491 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
4243 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
3492 | int pp_on_reg, pp_off_reg, pp_div_reg; |
4244 | int pp_on_reg, pp_off_reg, pp_div_reg; |
3493 | 4245 | ||
3494 | if (HAS_PCH_SPLIT(dev)) { |
4246 | if (HAS_PCH_SPLIT(dev)) { |
3495 | pp_on_reg = PCH_PP_ON_DELAYS; |
4247 | pp_on_reg = PCH_PP_ON_DELAYS; |
3496 | pp_off_reg = PCH_PP_OFF_DELAYS; |
4248 | pp_off_reg = PCH_PP_OFF_DELAYS; |
3497 | pp_div_reg = PCH_PP_DIVISOR; |
4249 | pp_div_reg = PCH_PP_DIVISOR; |
3498 | } else { |
4250 | } else { |
3499 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
4251 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3500 | 4252 | ||
3501 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
4253 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
3502 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
4254 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
3503 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
4255 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
3504 | } |
4256 | } |
- | 4257 | ||
3505 | 4258 | /* |
|
- | 4259 | * And finally store the new values in the power sequencer. The |
|
- | 4260 | * backlight delays are set to 1 because we do manual waits on them. For |
|
- | 4261 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
|
- | 4262 | * we'll end up waiting for the backlight off delay twice: once when we |
|
- | 4263 | * do the manual sleep, and once when we disable the panel and wait for |
|
- | 4264 | * the PP_STATUS bit to become zero. |
|
3506 | /* And finally store the new values in the power sequencer. */ |
4265 | */ |
3507 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
4266 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
3508 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
4267 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
3509 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
4268 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
3510 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
4269 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
3511 | /* Compute the divisor for the pp clock, simply match the Bspec |
4270 | /* Compute the divisor for the pp clock, simply match the Bspec |
3512 | * formula. */ |
4271 | * formula. */ |
3513 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
4272 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
3514 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
4273 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
3515 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
4274 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
3516 | 4275 | ||
3517 | /* Haswell doesn't have any port selection bits for the panel |
4276 | /* Haswell doesn't have any port selection bits for the panel |
3518 | * power sequencer any more. */ |
4277 | * power sequencer any more. */ |
3519 | if (IS_VALLEYVIEW(dev)) { |
4278 | if (IS_VALLEYVIEW(dev)) { |
3520 | if (dp_to_dig_port(intel_dp)->port == PORT_B) |
4279 | if (dp_to_dig_port(intel_dp)->port == PORT_B) |
3521 | port_sel = PANEL_PORT_SELECT_DPB_VLV; |
4280 | port_sel = PANEL_PORT_SELECT_DPB_VLV; |
3522 | else |
4281 | else |
3523 | port_sel = PANEL_PORT_SELECT_DPC_VLV; |
4282 | port_sel = PANEL_PORT_SELECT_DPC_VLV; |
3524 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
4283 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
3525 | if (dp_to_dig_port(intel_dp)->port == PORT_A) |
4284 | if (dp_to_dig_port(intel_dp)->port == PORT_A) |
3526 | port_sel = PANEL_PORT_SELECT_DPA; |
4285 | port_sel = PANEL_PORT_SELECT_DPA; |
3527 | else |
4286 | else |
3528 | port_sel = PANEL_PORT_SELECT_DPD; |
4287 | port_sel = PANEL_PORT_SELECT_DPD; |
3529 | } |
4288 | } |
3530 | 4289 | ||
3531 | pp_on |= port_sel; |
4290 | pp_on |= port_sel; |
3532 | 4291 | ||
3533 | I915_WRITE(pp_on_reg, pp_on); |
4292 | I915_WRITE(pp_on_reg, pp_on); |
3534 | I915_WRITE(pp_off_reg, pp_off); |
4293 | I915_WRITE(pp_off_reg, pp_off); |
3535 | I915_WRITE(pp_div_reg, pp_div); |
4294 | I915_WRITE(pp_div_reg, pp_div); |
3536 | 4295 | ||
3537 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
4296 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
3538 | I915_READ(pp_on_reg), |
4297 | I915_READ(pp_on_reg), |
3539 | I915_READ(pp_off_reg), |
4298 | I915_READ(pp_off_reg), |
3540 | I915_READ(pp_div_reg)); |
4299 | I915_READ(pp_div_reg)); |
3541 | } |
4300 | } |
- | 4301 | ||
- | 4302 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
|
- | 4303 | { |
|
- | 4304 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4305 | struct intel_encoder *encoder; |
|
- | 4306 | struct intel_dp *intel_dp = NULL; |
|
- | 4307 | struct intel_crtc_config *config = NULL; |
|
- | 4308 | struct intel_crtc *intel_crtc = NULL; |
|
- | 4309 | struct intel_connector *intel_connector = dev_priv->drrs.connector; |
|
- | 4310 | u32 reg, val; |
|
- | 4311 | enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; |
|
- | 4312 | ||
- | 4313 | if (refresh_rate <= 0) { |
|
- | 4314 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
|
- | 4315 | return; |
|
- | 4316 | } |
|
- | 4317 | ||
- | 4318 | if (intel_connector == NULL) { |
|
- | 4319 | DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); |
|
- | 4320 | return; |
|
- | 4321 | } |
|
- | 4322 | ||
- | 4323 | /* |
|
- | 4324 | * FIXME: This needs proper synchronization with psr state. But really |
|
- | 4325 | * hard to tell without seeing the user of this function of this code. |
|
- | 4326 | * Check locking and ordering once that lands. |
|
- | 4327 | */ |
|
- | 4328 | if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { |
|
- | 4329 | DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); |
|
- | 4330 | return; |
|
- | 4331 | } |
|
- | 4332 | ||
- | 4333 | encoder = intel_attached_encoder(&intel_connector->base); |
|
- | 4334 | intel_dp = enc_to_intel_dp(&encoder->base); |
|
- | 4335 | intel_crtc = encoder->new_crtc; |
|
- | 4336 | ||
- | 4337 | if (!intel_crtc) { |
|
- | 4338 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
|
- | 4339 | return; |
|
- | 4340 | } |
|
- | 4341 | ||
- | 4342 | config = &intel_crtc->config; |
|
- | 4343 | ||
- | 4344 | if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { |
|
- | 4345 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
|
- | 4346 | return; |
|
- | 4347 | } |
|
- | 4348 | ||
- | 4349 | if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) |
|
- | 4350 | index = DRRS_LOW_RR; |
|
- | 4351 | ||
- | 4352 | if (index == intel_dp->drrs_state.refresh_rate_type) { |
|
- | 4353 | DRM_DEBUG_KMS( |
|
- | 4354 | "DRRS requested for previously set RR...ignoring\n"); |
|
- | 4355 | return; |
|
- | 4356 | } |
|
- | 4357 | ||
- | 4358 | if (!intel_crtc->active) { |
|
- | 4359 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
|
- | 4360 | return; |
|
- | 4361 | } |
|
- | 4362 | ||
- | 4363 | if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { |
|
- | 4364 | reg = PIPECONF(intel_crtc->config.cpu_transcoder); |
|
- | 4365 | val = I915_READ(reg); |
|
- | 4366 | if (index > DRRS_HIGH_RR) { |
|
- | 4367 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
|
- | 4368 | intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); |
|
- | 4369 | } else { |
|
- | 4370 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
|
- | 4371 | } |
|
- | 4372 | I915_WRITE(reg, val); |
|
- | 4373 | } |
|
- | 4374 | ||
- | 4375 | /* |
|
- | 4376 | * mutex taken to ensure that there is no race between differnt |
|
- | 4377 | * drrs calls trying to update refresh rate. This scenario may occur |
|
- | 4378 | * in future when idleness detection based DRRS in kernel and |
|
- | 4379 | * possible calls from user space to set differnt RR are made. |
|
- | 4380 | */ |
|
- | 4381 | ||
- | 4382 | mutex_lock(&intel_dp->drrs_state.mutex); |
|
- | 4383 | ||
- | 4384 | intel_dp->drrs_state.refresh_rate_type = index; |
|
- | 4385 | ||
- | 4386 | mutex_unlock(&intel_dp->drrs_state.mutex); |
|
- | 4387 | ||
- | 4388 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
|
- | 4389 | } |
|
- | 4390 | ||
- | 4391 | static struct drm_display_mode * |
|
- | 4392 | intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, |
|
- | 4393 | struct intel_connector *intel_connector, |
|
- | 4394 | struct drm_display_mode *fixed_mode) |
|
- | 4395 | { |
|
- | 4396 | struct drm_connector *connector = &intel_connector->base; |
|
- | 4397 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
|
- | 4398 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 4399 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4400 | struct drm_display_mode *downclock_mode = NULL; |
|
- | 4401 | ||
- | 4402 | if (INTEL_INFO(dev)->gen <= 6) { |
|
- | 4403 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
|
- | 4404 | return NULL; |
|
- | 4405 | } |
|
- | 4406 | ||
- | 4407 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
|
- | 4408 | DRM_INFO("VBT doesn't support DRRS\n"); |
|
- | 4409 | return NULL; |
|
- | 4410 | } |
|
- | 4411 | ||
- | 4412 | downclock_mode = intel_find_panel_downclock |
|
- | 4413 | (dev, fixed_mode, connector); |
|
- | 4414 | ||
- | 4415 | if (!downclock_mode) { |
|
- | 4416 | DRM_INFO("DRRS not supported\n"); |
|
- | 4417 | return NULL; |
|
- | 4418 | } |
|
- | 4419 | ||
- | 4420 | dev_priv->drrs.connector = intel_connector; |
|
- | 4421 | ||
- | 4422 | mutex_init(&intel_dp->drrs_state.mutex); |
|
- | 4423 | ||
- | 4424 | intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; |
|
- | 4425 | ||
- | 4426 | intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; |
|
- | 4427 | DRM_INFO("seamless DRRS supported for eDP panel.\n"); |
|
- | 4428 | return downclock_mode; |
|
- | 4429 | } |
|
- | 4430 | ||
- | 4431 | void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder) |
|
- | 4432 | { |
|
- | 4433 | struct drm_device *dev = intel_encoder->base.dev; |
|
- | 4434 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4435 | struct intel_dp *intel_dp; |
|
- | 4436 | enum intel_display_power_domain power_domain; |
|
- | 4437 | ||
- | 4438 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
|
- | 4439 | return; |
|
- | 4440 | ||
- | 4441 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
|
- | 4442 | if (!edp_have_panel_vdd(intel_dp)) |
|
- | 4443 | return; |
|
- | 4444 | /* |
|
- | 4445 | * The VDD bit needs a power domain reference, so if the bit is |
|
- | 4446 | * already enabled when we boot or resume, grab this reference and |
|
- | 4447 | * schedule a vdd off, so we don't hold on to the reference |
|
- | 4448 | * indefinitely. |
|
- | 4449 | */ |
|
- | 4450 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
|
- | 4451 | power_domain = intel_display_port_power_domain(intel_encoder); |
|
- | 4452 | intel_display_power_get(dev_priv, power_domain); |
|
- | 4453 | ||
- | 4454 | edp_panel_vdd_schedule_off(intel_dp); |
|
- | 4455 | } |
|
3542 | 4456 | ||
3543 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
4457 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
- | 4458 | struct intel_connector *intel_connector, |
|
3544 | struct intel_connector *intel_connector) |
4459 | struct edp_power_seq *power_seq) |
3545 | { |
4460 | { |
3546 | struct drm_connector *connector = &intel_connector->base; |
4461 | struct drm_connector *connector = &intel_connector->base; |
3547 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4462 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
- | 4463 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
|
3548 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4464 | struct drm_device *dev = intel_encoder->base.dev; |
3549 | struct drm_i915_private *dev_priv = dev->dev_private; |
4465 | struct drm_i915_private *dev_priv = dev->dev_private; |
3550 | struct drm_display_mode *fixed_mode = NULL; |
4466 | struct drm_display_mode *fixed_mode = NULL; |
3551 | struct edp_power_seq power_seq = { 0 }; |
4467 | struct drm_display_mode *downclock_mode = NULL; |
3552 | bool has_dpcd; |
4468 | bool has_dpcd; |
3553 | struct drm_display_mode *scan; |
4469 | struct drm_display_mode *scan; |
3554 | struct edid *edid; |
4470 | struct edid *edid; |
- | 4471 | ||
- | 4472 | intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; |
|
3555 | 4473 | ||
3556 | if (!is_edp(intel_dp)) |
4474 | if (!is_edp(intel_dp)) |
3557 | return true; |
4475 | return true; |
3558 | 4476 | ||
3559 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
4477 | intel_edp_panel_vdd_sanitize(intel_encoder); |
3560 | 4478 | ||
3561 | /* Cache DPCD and EDID for edp. */ |
4479 | /* Cache DPCD and EDID for edp. */ |
3562 | ironlake_edp_panel_vdd_on(intel_dp); |
4480 | intel_edp_panel_vdd_on(intel_dp); |
3563 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
4481 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
3564 | ironlake_edp_panel_vdd_off(intel_dp, false); |
4482 | edp_panel_vdd_off(intel_dp, false); |
3565 | 4483 | ||
3566 | if (has_dpcd) { |
4484 | if (has_dpcd) { |
3567 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
4485 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
3568 | dev_priv->no_aux_handshake = |
4486 | dev_priv->no_aux_handshake = |
3569 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
4487 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
3570 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
4488 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
3571 | } else { |
4489 | } else { |
3572 | /* if this fails, presume the device is a ghost */ |
4490 | /* if this fails, presume the device is a ghost */ |
3573 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
4491 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3574 | return false; |
4492 | return false; |
3575 | } |
4493 | } |
3576 | 4494 | ||
3577 | /* We now know it's not a ghost, init power sequence regs. */ |
4495 | /* We now know it's not a ghost, init power sequence regs. */ |
3578 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
4496 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
3579 | &power_seq); |
- | |
- | 4497 | ||
3580 | 4498 | mutex_lock(&dev->mode_config.mutex); |
|
3581 | edid = drm_get_edid(connector, &intel_dp->adapter); |
4499 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
3582 | if (edid) { |
4500 | if (edid) { |
3583 | if (drm_add_edid_modes(connector, edid)) { |
4501 | if (drm_add_edid_modes(connector, edid)) { |
3584 | drm_mode_connector_update_edid_property(connector, |
4502 | drm_mode_connector_update_edid_property(connector, |
3585 | edid); |
4503 | edid); |
3586 | drm_edid_to_eld(connector, edid); |
4504 | drm_edid_to_eld(connector, edid); |
3587 | } else { |
4505 | } else { |
3588 | kfree(edid); |
4506 | kfree(edid); |
3589 | edid = ERR_PTR(-EINVAL); |
4507 | edid = ERR_PTR(-EINVAL); |
3590 | } |
4508 | } |
3591 | } else { |
4509 | } else { |
3592 | edid = ERR_PTR(-ENOENT); |
4510 | edid = ERR_PTR(-ENOENT); |
3593 | } |
4511 | } |
3594 | intel_connector->edid = edid; |
4512 | intel_connector->edid = edid; |
3595 | 4513 | ||
3596 | /* prefer fixed mode from EDID if available */ |
4514 | /* prefer fixed mode from EDID if available */ |
3597 | list_for_each_entry(scan, &connector->probed_modes, head) { |
4515 | list_for_each_entry(scan, &connector->probed_modes, head) { |
3598 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
4516 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
3599 | fixed_mode = drm_mode_duplicate(dev, scan); |
4517 | fixed_mode = drm_mode_duplicate(dev, scan); |
- | 4518 | downclock_mode = intel_dp_drrs_init( |
|
- | 4519 | intel_dig_port, |
|
- | 4520 | intel_connector, fixed_mode); |
|
3600 | break; |
4521 | break; |
3601 | } |
4522 | } |
3602 | } |
4523 | } |
3603 | 4524 | ||
3604 | /* fallback to VBT if available for eDP */ |
4525 | /* fallback to VBT if available for eDP */ |
3605 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
4526 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
3606 | fixed_mode = drm_mode_duplicate(dev, |
4527 | fixed_mode = drm_mode_duplicate(dev, |
3607 | dev_priv->vbt.lfp_lvds_vbt_mode); |
4528 | dev_priv->vbt.lfp_lvds_vbt_mode); |
3608 | if (fixed_mode) |
4529 | if (fixed_mode) |
3609 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
4530 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
3610 | } |
4531 | } |
- | 4532 | mutex_unlock(&dev->mode_config.mutex); |
|
3611 | 4533 | ||
3612 | intel_panel_init(&intel_connector->panel, fixed_mode); |
4534 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
3613 | intel_panel_setup_backlight(connector); |
4535 | intel_panel_setup_backlight(connector); |
3614 | 4536 | ||
3615 | return true; |
4537 | return true; |
3616 | } |
4538 | } |
3617 | 4539 | ||
3618 | bool |
4540 | bool |
3619 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
4541 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
3620 | struct intel_connector *intel_connector) |
4542 | struct intel_connector *intel_connector) |
3621 | { |
4543 | { |
3622 | struct drm_connector *connector = &intel_connector->base; |
4544 | struct drm_connector *connector = &intel_connector->base; |
3623 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4545 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
3624 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4546 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
3625 | struct drm_device *dev = intel_encoder->base.dev; |
4547 | struct drm_device *dev = intel_encoder->base.dev; |
3626 | struct drm_i915_private *dev_priv = dev->dev_private; |
4548 | struct drm_i915_private *dev_priv = dev->dev_private; |
3627 | enum port port = intel_dig_port->port; |
4549 | enum port port = intel_dig_port->port; |
3628 | const char *name = NULL; |
4550 | struct edp_power_seq power_seq = { 0 }; |
3629 | int type, error; |
4551 | int type; |
- | 4552 | ||
- | 4553 | /* intel_dp vfuncs */ |
|
- | 4554 | if (IS_VALLEYVIEW(dev)) |
|
- | 4555 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
|
- | 4556 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
|
- | 4557 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
|
- | 4558 | else if (HAS_PCH_SPLIT(dev)) |
|
- | 4559 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
|
- | 4560 | else |
|
- | 4561 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
|
- | 4562 | ||
- | 4563 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
|
3630 | 4564 | ||
3631 | /* Preserve the current hw state. */ |
4565 | /* Preserve the current hw state. */ |
3632 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
4566 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
3633 | intel_dp->attached_connector = intel_connector; |
4567 | intel_dp->attached_connector = intel_connector; |
3634 | 4568 | ||
3635 | if (intel_dp_is_edp(dev, port)) |
4569 | if (intel_dp_is_edp(dev, port)) |
3636 | type = DRM_MODE_CONNECTOR_eDP; |
4570 | type = DRM_MODE_CONNECTOR_eDP; |
3637 | else |
4571 | else |
3638 | type = DRM_MODE_CONNECTOR_DisplayPort; |
4572 | type = DRM_MODE_CONNECTOR_DisplayPort; |
3639 | 4573 | ||
3640 | /* |
4574 | /* |
3641 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
4575 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
3642 | * for DP the encoder type can be set by the caller to |
4576 | * for DP the encoder type can be set by the caller to |
3643 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
4577 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
3644 | */ |
4578 | */ |
3645 | if (type == DRM_MODE_CONNECTOR_eDP) |
4579 | if (type == DRM_MODE_CONNECTOR_eDP) |
3646 | intel_encoder->type = INTEL_OUTPUT_EDP; |
4580 | intel_encoder->type = INTEL_OUTPUT_EDP; |
3647 | 4581 | ||
3648 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
4582 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
3649 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
4583 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
3650 | port_name(port)); |
4584 | port_name(port)); |
3651 | 4585 | ||
3652 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
4586 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
3653 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
4587 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
3654 | 4588 | ||
3655 | connector->interlace_allowed = true; |
4589 | connector->interlace_allowed = true; |
3656 | connector->doublescan_allowed = 0; |
4590 | connector->doublescan_allowed = 0; |
3657 | 4591 | ||
3658 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4592 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
3659 | ironlake_panel_vdd_work); |
4593 | edp_panel_vdd_work); |
3660 | 4594 | ||
3661 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
4595 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
3662 | drm_sysfs_connector_add(connector); |
4596 | drm_connector_register(connector); |
3663 | 4597 | ||
3664 | if (HAS_DDI(dev)) |
4598 | if (HAS_DDI(dev)) |
3665 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
4599 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
3666 | else |
4600 | else |
3667 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
4601 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
- | 4602 | intel_connector->unregister = intel_dp_connector_unregister; |
|
3668 | - | ||
3669 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
- | |
3670 | if (HAS_DDI(dev)) { |
- | |
3671 | switch (intel_dig_port->port) { |
- | |
3672 | case PORT_A: |
- | |
3673 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
- | |
3674 | break; |
- | |
3675 | case PORT_B: |
- | |
3676 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
- | |
3677 | break; |
- | |
3678 | case PORT_C: |
- | |
3679 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
- | |
3680 | break; |
- | |
3681 | case PORT_D: |
- | |
3682 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
- | |
3683 | break; |
- | |
3684 | default: |
- | |
3685 | BUG(); |
- | |
3686 | } |
- | |
3687 | } |
- | |
3688 | 4603 | ||
3689 | /* Set up the DDC bus. */ |
4604 | /* Set up the hotplug pin. */ |
3690 | switch (port) { |
4605 | switch (port) { |
3691 | case PORT_A: |
4606 | case PORT_A: |
3692 | intel_encoder->hpd_pin = HPD_PORT_A; |
4607 | intel_encoder->hpd_pin = HPD_PORT_A; |
3693 | name = "DPDDC-A"; |
- | |
3694 | break; |
4608 | break; |
3695 | case PORT_B: |
4609 | case PORT_B: |
3696 | intel_encoder->hpd_pin = HPD_PORT_B; |
4610 | intel_encoder->hpd_pin = HPD_PORT_B; |
3697 | name = "DPDDC-B"; |
- | |
3698 | break; |
4611 | break; |
3699 | case PORT_C: |
4612 | case PORT_C: |
3700 | intel_encoder->hpd_pin = HPD_PORT_C; |
4613 | intel_encoder->hpd_pin = HPD_PORT_C; |
3701 | name = "DPDDC-C"; |
- | |
3702 | break; |
4614 | break; |
3703 | case PORT_D: |
4615 | case PORT_D: |
3704 | intel_encoder->hpd_pin = HPD_PORT_D; |
4616 | intel_encoder->hpd_pin = HPD_PORT_D; |
3705 | name = "DPDDC-D"; |
- | |
3706 | break; |
4617 | break; |
3707 | default: |
4618 | default: |
3708 | BUG(); |
4619 | BUG(); |
3709 | } |
4620 | } |
3710 | 4621 | ||
3711 | error = intel_dp_i2c_init(intel_dp, intel_connector, name); |
4622 | if (is_edp(intel_dp)) { |
3712 | WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", |
4623 | intel_dp_init_panel_power_timestamps(intel_dp); |
- | 4624 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
|
3713 | error, port_name(port)); |
4625 | } |
- | 4626 | ||
- | 4627 | intel_dp_aux_init(intel_dp, intel_connector); |
|
- | 4628 | ||
- | 4629 | /* init MST on ports that can support it */ |
|
- | 4630 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
|
- | 4631 | if (port == PORT_B || port == PORT_C || port == PORT_D) { |
|
- | 4632 | intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id); |
|
3714 | 4633 | } |
|
3715 | intel_dp->psr_setup_done = false; |
4634 | } |
3716 | 4635 | ||
3717 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
4636 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
3718 | i2c_del_adapter(&intel_dp->adapter); |
4637 | drm_dp_aux_unregister(&intel_dp->aux); |
3719 | if (is_edp(intel_dp)) { |
4638 | if (is_edp(intel_dp)) { |
3720 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
4639 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
3721 | mutex_lock(&dev->mode_config.mutex); |
4640 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
3722 | ironlake_panel_vdd_off_sync(intel_dp); |
4641 | edp_panel_vdd_off_sync(intel_dp); |
3723 | mutex_unlock(&dev->mode_config.mutex); |
4642 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
3724 | } |
4643 | } |
3725 | drm_sysfs_connector_remove(connector); |
4644 | drm_connector_unregister(connector); |
3726 | drm_connector_cleanup(connector); |
4645 | drm_connector_cleanup(connector); |
3727 | return false; |
4646 | return false; |
3728 | } |
4647 | } |
3729 | 4648 | ||
3730 | intel_dp_add_properties(intel_dp, connector); |
4649 | intel_dp_add_properties(intel_dp, connector); |
3731 | 4650 | ||
3732 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
4651 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
3733 | * 0xd. Failure to do so will result in spurious interrupts being |
4652 | * 0xd. Failure to do so will result in spurious interrupts being |
3734 | * generated on the port when a cable is not attached. |
4653 | * generated on the port when a cable is not attached. |
3735 | */ |
4654 | */ |
3736 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
4655 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
3737 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
4656 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
3738 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
4657 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
3739 | } |
4658 | } |
3740 | 4659 | ||
3741 | return true; |
4660 | return true; |
3742 | } |
4661 | } |
3743 | 4662 | ||
3744 | void |
4663 | void |
3745 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
4664 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
3746 | { |
4665 | { |
- | 4666 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
3747 | struct intel_digital_port *intel_dig_port; |
4667 | struct intel_digital_port *intel_dig_port; |
3748 | struct intel_encoder *intel_encoder; |
4668 | struct intel_encoder *intel_encoder; |
3749 | struct drm_encoder *encoder; |
4669 | struct drm_encoder *encoder; |
3750 | struct intel_connector *intel_connector; |
4670 | struct intel_connector *intel_connector; |
3751 | 4671 | ||
3752 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
4672 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
3753 | if (!intel_dig_port) |
4673 | if (!intel_dig_port) |
3754 | return; |
4674 | return; |
3755 | 4675 | ||
3756 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
4676 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
3757 | if (!intel_connector) { |
4677 | if (!intel_connector) { |
3758 | kfree(intel_dig_port); |
4678 | kfree(intel_dig_port); |
3759 | return; |
4679 | return; |
3760 | } |
4680 | } |
3761 | 4681 | ||
3762 | intel_encoder = &intel_dig_port->base; |
4682 | intel_encoder = &intel_dig_port->base; |
3763 | encoder = &intel_encoder->base; |
4683 | encoder = &intel_encoder->base; |
3764 | 4684 | ||
3765 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
4685 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
3766 | DRM_MODE_ENCODER_TMDS); |
4686 | DRM_MODE_ENCODER_TMDS); |
3767 | 4687 | ||
3768 | intel_encoder->compute_config = intel_dp_compute_config; |
4688 | intel_encoder->compute_config = intel_dp_compute_config; |
3769 | intel_encoder->mode_set = intel_dp_mode_set; |
- | |
3770 | intel_encoder->disable = intel_disable_dp; |
4689 | intel_encoder->disable = intel_disable_dp; |
3771 | intel_encoder->post_disable = intel_post_disable_dp; |
- | |
3772 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
4690 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
3773 | intel_encoder->get_config = intel_dp_get_config; |
4691 | intel_encoder->get_config = intel_dp_get_config; |
- | 4692 | intel_encoder->suspend = intel_dp_encoder_suspend; |
|
3774 | if (IS_VALLEYVIEW(dev)) { |
4693 | if (IS_CHERRYVIEW(dev)) { |
- | 4694 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
|
- | 4695 | intel_encoder->pre_enable = chv_pre_enable_dp; |
|
- | 4696 | intel_encoder->enable = vlv_enable_dp; |
|
- | 4697 | intel_encoder->post_disable = chv_post_disable_dp; |
|
- | 4698 | } else if (IS_VALLEYVIEW(dev)) { |
|
3775 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
4699 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
3776 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
4700 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
3777 | intel_encoder->enable = vlv_enable_dp; |
4701 | intel_encoder->enable = vlv_enable_dp; |
- | 4702 | intel_encoder->post_disable = vlv_post_disable_dp; |
|
3778 | } else { |
4703 | } else { |
3779 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
4704 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
3780 | intel_encoder->enable = g4x_enable_dp; |
4705 | intel_encoder->enable = g4x_enable_dp; |
- | 4706 | intel_encoder->post_disable = g4x_post_disable_dp; |
|
3781 | } |
4707 | } |
3782 | 4708 | ||
3783 | intel_dig_port->port = port; |
4709 | intel_dig_port->port = port; |
3784 | intel_dig_port->dp.output_reg = output_reg; |
4710 | intel_dig_port->dp.output_reg = output_reg; |
3785 | 4711 | ||
3786 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4712 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
- | 4713 | if (IS_CHERRYVIEW(dev)) { |
|
- | 4714 | if (port == PORT_D) |
|
- | 4715 | intel_encoder->crtc_mask = 1 << 2; |
|
- | 4716 | else |
|
- | 4717 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
|
- | 4718 | } else { |
|
3787 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
4719 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
- | 4720 | } |
|
3788 | intel_encoder->cloneable = false; |
4721 | intel_encoder->cloneable = 0; |
3789 | intel_encoder->hot_plug = intel_dp_hot_plug; |
4722 | intel_encoder->hot_plug = intel_dp_hot_plug; |
- | 4723 | ||
- | 4724 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
|
- | 4725 | dev_priv->hpd_irq_port[port] = intel_dig_port; |
|
3790 | 4726 | ||
3791 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
4727 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
3792 | drm_encoder_cleanup(encoder); |
4728 | drm_encoder_cleanup(encoder); |
3793 | kfree(intel_dig_port); |
4729 | kfree(intel_dig_port); |
3794 | kfree(intel_connector); |
4730 | kfree(intel_connector); |
3795 | } |
4731 | } |
- | 4732 | } |
|
- | 4733 | ||
- | 4734 | void intel_dp_mst_suspend(struct drm_device *dev) |
|
- | 4735 | { |
|
- | 4736 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4737 | int i; |
|
- | 4738 | ||
- | 4739 | /* disable MST */ |
|
- | 4740 | for (i = 0; i < I915_MAX_PORTS; i++) { |
|
- | 4741 | struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; |
|
- | 4742 | if (!intel_dig_port) |
|
- | 4743 | continue; |
|
- | 4744 | ||
- | 4745 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
|
- | 4746 | if (!intel_dig_port->dp.can_mst) |
|
- | 4747 | continue; |
|
- | 4748 | if (intel_dig_port->dp.is_mst) |
|
- | 4749 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
|
- | 4750 | } |
|
- | 4751 | } |
|
- | 4752 | } |
|
- | 4753 | ||
- | 4754 | void intel_dp_mst_resume(struct drm_device *dev) |
|
- | 4755 | { |
|
- | 4756 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4757 | int i; |
|
- | 4758 | ||
- | 4759 | for (i = 0; i < I915_MAX_PORTS; i++) { |
|
- | 4760 | struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; |
|
- | 4761 | if (!intel_dig_port) |
|
- | 4762 | continue; |
|
- | 4763 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
|
- | 4764 | int ret; |
|
- | 4765 | ||
- | 4766 | if (!intel_dig_port->dp.can_mst) |
|
- | 4767 | continue; |
|
- | 4768 | ||
- | 4769 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
|
- | 4770 | if (ret != 0) { |
|
- | 4771 | intel_dp_check_mst_status(&intel_dig_port->dp); |
|
- | 4772 | } |
|
- | 4773 | } |
|
- | 4774 | } |
|
3796 | }><>><>><>><>><>><>><>><>><>>>>>> |
4775 | }>>><>><>><>><>><>><>=>>>>=>><>><>><>><>><>><>>>>>>>>>>>>>><>><>>>>><>>><>>>><>><>> |
3797 | ><21); |
4776 | ><21); |
3798 | >21); |
4777 | >21); |
3799 | ><21); |
4778 | ><21); |
3800 | >><>><>><>><>><>>>>>><>=>=><=>=>=>>>>>><>><>><>>><>>><>>><>><>><>>>>=>>><>>> |
4779 | >><>><>><>><>><>>>>>><>=>=><=>=>=>>>>><>>>>>><>><>><>=>>><>>>><> |