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1 | /* |
1 | /* |
2 | * Copyright © 2008 Intel Corporation |
2 | * Copyright © 2008 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Keith Packard |
24 | * Keith Packard |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | #include |
33 | #include |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | #include |
36 | #include |
37 | #include "intel_drv.h" |
37 | #include "intel_drv.h" |
38 | #include |
38 | #include |
39 | #include "i915_drv.h" |
39 | #include "i915_drv.h" |
40 | 40 | ||
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
42 | 42 | ||
43 | /* Compliance test status bits */ |
43 | /* Compliance test status bits */ |
44 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
44 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
45 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
45 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
46 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
46 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
47 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
47 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
48 | 48 | ||
49 | struct dp_link_dpll { |
49 | struct dp_link_dpll { |
50 | int clock; |
50 | int clock; |
51 | struct dpll dpll; |
51 | struct dpll dpll; |
52 | }; |
52 | }; |
53 | 53 | ||
54 | static const struct dp_link_dpll gen4_dpll[] = { |
54 | static const struct dp_link_dpll gen4_dpll[] = { |
55 | { 162000, |
55 | { 162000, |
56 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
56 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
57 | { 270000, |
57 | { 270000, |
58 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
58 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
59 | }; |
59 | }; |
60 | 60 | ||
61 | static const struct dp_link_dpll pch_dpll[] = { |
61 | static const struct dp_link_dpll pch_dpll[] = { |
62 | { 162000, |
62 | { 162000, |
63 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
63 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
64 | { 270000, |
64 | { 270000, |
65 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
65 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
66 | }; |
66 | }; |
67 | 67 | ||
68 | static const struct dp_link_dpll vlv_dpll[] = { |
68 | static const struct dp_link_dpll vlv_dpll[] = { |
69 | { 162000, |
69 | { 162000, |
70 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
70 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
71 | { 270000, |
71 | { 270000, |
72 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
72 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
73 | }; |
73 | }; |
74 | 74 | ||
75 | /* |
75 | /* |
76 | * CHV supports eDP 1.4 that have more link rates. |
76 | * CHV supports eDP 1.4 that have more link rates. |
77 | * Below only provides the fixed rate but exclude variable rate. |
77 | * Below only provides the fixed rate but exclude variable rate. |
78 | */ |
78 | */ |
79 | static const struct dp_link_dpll chv_dpll[] = { |
79 | static const struct dp_link_dpll chv_dpll[] = { |
80 | /* |
80 | /* |
81 | * CHV requires to program fractional division for m2. |
81 | * CHV requires to program fractional division for m2. |
82 | * m2 is stored in fixed point format using formula below |
82 | * m2 is stored in fixed point format using formula below |
83 | * (m2_int << 22) | m2_fraction |
83 | * (m2_int << 22) | m2_fraction |
84 | */ |
84 | */ |
85 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
85 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
86 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
86 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
87 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
87 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
88 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
88 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
89 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
89 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
90 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
90 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
91 | }; |
91 | }; |
92 | 92 | ||
93 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
93 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
94 | 324000, 432000, 540000 }; |
94 | 324000, 432000, 540000 }; |
95 | static const int skl_rates[] = { 162000, 216000, 270000, |
95 | static const int skl_rates[] = { 162000, 216000, 270000, |
96 | 324000, 432000, 540000 }; |
96 | 324000, 432000, 540000 }; |
97 | static const int default_rates[] = { 162000, 270000, 540000 }; |
97 | static const int default_rates[] = { 162000, 270000, 540000 }; |
98 | 98 | ||
99 | /** |
99 | /** |
100 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
100 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
101 | * @intel_dp: DP struct |
101 | * @intel_dp: DP struct |
102 | * |
102 | * |
103 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
103 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
104 | * will return true, and false otherwise. |
104 | * will return true, and false otherwise. |
105 | */ |
105 | */ |
106 | static bool is_edp(struct intel_dp *intel_dp) |
106 | static bool is_edp(struct intel_dp *intel_dp) |
107 | { |
107 | { |
108 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
108 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
109 | 109 | ||
110 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
110 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
111 | } |
111 | } |
112 | 112 | ||
113 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
113 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
114 | { |
114 | { |
115 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
115 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
116 | 116 | ||
117 | return intel_dig_port->base.base.dev; |
117 | return intel_dig_port->base.base.dev; |
118 | } |
118 | } |
119 | 119 | ||
120 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
120 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
121 | { |
121 | { |
122 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
122 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
123 | } |
123 | } |
124 | 124 | ||
125 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
125 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
126 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
126 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
127 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
127 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
128 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
128 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
129 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
129 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
130 | enum pipe pipe); |
130 | enum pipe pipe); |
131 | 131 | ||
132 | static unsigned int intel_dp_unused_lane_mask(int lane_count) |
132 | static unsigned int intel_dp_unused_lane_mask(int lane_count) |
133 | { |
133 | { |
134 | return ~((1 << lane_count) - 1) & 0xf; |
134 | return ~((1 << lane_count) - 1) & 0xf; |
135 | } |
135 | } |
136 | 136 | ||
137 | static int |
137 | static int |
138 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
138 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
139 | { |
139 | { |
140 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
140 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
141 | 141 | ||
142 | switch (max_link_bw) { |
142 | switch (max_link_bw) { |
143 | case DP_LINK_BW_1_62: |
143 | case DP_LINK_BW_1_62: |
144 | case DP_LINK_BW_2_7: |
144 | case DP_LINK_BW_2_7: |
145 | case DP_LINK_BW_5_4: |
145 | case DP_LINK_BW_5_4: |
146 | break; |
146 | break; |
147 | default: |
147 | default: |
148 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
148 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
149 | max_link_bw); |
149 | max_link_bw); |
150 | max_link_bw = DP_LINK_BW_1_62; |
150 | max_link_bw = DP_LINK_BW_1_62; |
151 | break; |
151 | break; |
152 | } |
152 | } |
153 | return max_link_bw; |
153 | return max_link_bw; |
154 | } |
154 | } |
155 | 155 | ||
156 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
156 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
157 | { |
157 | { |
158 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
158 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
159 | struct drm_device *dev = intel_dig_port->base.base.dev; |
- | |
160 | u8 source_max, sink_max; |
159 | u8 source_max, sink_max; |
161 | - | ||
162 | source_max = 4; |
160 | |
163 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && |
- | |
164 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) |
- | |
165 | source_max = 2; |
- | |
166 | 161 | source_max = intel_dig_port->max_lanes; |
|
167 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
162 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
168 | 163 | ||
169 | return min(source_max, sink_max); |
164 | return min(source_max, sink_max); |
170 | } |
165 | } |
171 | 166 | ||
172 | /* |
167 | /* |
173 | * The units on the numbers in the next two are... bizarre. Examples will |
168 | * The units on the numbers in the next two are... bizarre. Examples will |
174 | * make it clearer; this one parallels an example in the eDP spec. |
169 | * make it clearer; this one parallels an example in the eDP spec. |
175 | * |
170 | * |
176 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
171 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
177 | * |
172 | * |
178 | * 270000 * 1 * 8 / 10 == 216000 |
173 | * 270000 * 1 * 8 / 10 == 216000 |
179 | * |
174 | * |
180 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
175 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
181 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
176 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
182 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
177 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
183 | * 119000. At 18bpp that's 2142000 kilobits per second. |
178 | * 119000. At 18bpp that's 2142000 kilobits per second. |
184 | * |
179 | * |
185 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
180 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
186 | * get the result in decakilobits instead of kilobits. |
181 | * get the result in decakilobits instead of kilobits. |
187 | */ |
182 | */ |
188 | 183 | ||
189 | static int |
184 | static int |
190 | intel_dp_link_required(int pixel_clock, int bpp) |
185 | intel_dp_link_required(int pixel_clock, int bpp) |
191 | { |
186 | { |
192 | return (pixel_clock * bpp + 9) / 10; |
187 | return (pixel_clock * bpp + 9) / 10; |
193 | } |
188 | } |
194 | 189 | ||
195 | static int |
190 | static int |
196 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
191 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
197 | { |
192 | { |
198 | return (max_link_clock * max_lanes * 8) / 10; |
193 | return (max_link_clock * max_lanes * 8) / 10; |
199 | } |
194 | } |
200 | 195 | ||
201 | static enum drm_mode_status |
196 | static enum drm_mode_status |
202 | intel_dp_mode_valid(struct drm_connector *connector, |
197 | intel_dp_mode_valid(struct drm_connector *connector, |
203 | struct drm_display_mode *mode) |
198 | struct drm_display_mode *mode) |
204 | { |
199 | { |
205 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
200 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
206 | struct intel_connector *intel_connector = to_intel_connector(connector); |
201 | struct intel_connector *intel_connector = to_intel_connector(connector); |
207 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
202 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
208 | int target_clock = mode->clock; |
203 | int target_clock = mode->clock; |
209 | int max_rate, mode_rate, max_lanes, max_link_clock; |
204 | int max_rate, mode_rate, max_lanes, max_link_clock; |
- | 205 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
|
210 | 206 | ||
211 | if (is_edp(intel_dp) && fixed_mode) { |
207 | if (is_edp(intel_dp) && fixed_mode) { |
212 | if (mode->hdisplay > fixed_mode->hdisplay) |
208 | if (mode->hdisplay > fixed_mode->hdisplay) |
213 | return MODE_PANEL; |
209 | return MODE_PANEL; |
214 | 210 | ||
215 | if (mode->vdisplay > fixed_mode->vdisplay) |
211 | if (mode->vdisplay > fixed_mode->vdisplay) |
216 | return MODE_PANEL; |
212 | return MODE_PANEL; |
217 | 213 | ||
218 | target_clock = fixed_mode->clock; |
214 | target_clock = fixed_mode->clock; |
219 | } |
215 | } |
220 | 216 | ||
221 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
217 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
222 | max_lanes = intel_dp_max_lane_count(intel_dp); |
218 | max_lanes = intel_dp_max_lane_count(intel_dp); |
223 | 219 | ||
224 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
220 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
225 | mode_rate = intel_dp_link_required(target_clock, 18); |
221 | mode_rate = intel_dp_link_required(target_clock, 18); |
226 | 222 | ||
227 | if (mode_rate > max_rate) |
223 | if (mode_rate > max_rate || target_clock > max_dotclk) |
228 | return MODE_CLOCK_HIGH; |
224 | return MODE_CLOCK_HIGH; |
229 | 225 | ||
230 | if (mode->clock < 10000) |
226 | if (mode->clock < 10000) |
231 | return MODE_CLOCK_LOW; |
227 | return MODE_CLOCK_LOW; |
232 | 228 | ||
233 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
229 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
234 | return MODE_H_ILLEGAL; |
230 | return MODE_H_ILLEGAL; |
235 | 231 | ||
236 | return MODE_OK; |
232 | return MODE_OK; |
237 | } |
233 | } |
238 | 234 | ||
239 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
235 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
240 | { |
236 | { |
241 | int i; |
237 | int i; |
242 | uint32_t v = 0; |
238 | uint32_t v = 0; |
243 | 239 | ||
244 | if (src_bytes > 4) |
240 | if (src_bytes > 4) |
245 | src_bytes = 4; |
241 | src_bytes = 4; |
246 | for (i = 0; i < src_bytes; i++) |
242 | for (i = 0; i < src_bytes; i++) |
247 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
243 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
248 | return v; |
244 | return v; |
249 | } |
245 | } |
250 | 246 | ||
251 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
247 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
252 | { |
248 | { |
253 | int i; |
249 | int i; |
254 | if (dst_bytes > 4) |
250 | if (dst_bytes > 4) |
255 | dst_bytes = 4; |
251 | dst_bytes = 4; |
256 | for (i = 0; i < dst_bytes; i++) |
252 | for (i = 0; i < dst_bytes; i++) |
257 | dst[i] = src >> ((3-i) * 8); |
253 | dst[i] = src >> ((3-i) * 8); |
258 | } |
254 | } |
259 | 255 | ||
260 | static void |
256 | static void |
261 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
257 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
262 | struct intel_dp *intel_dp); |
258 | struct intel_dp *intel_dp); |
263 | static void |
259 | static void |
264 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
260 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
265 | struct intel_dp *intel_dp); |
261 | struct intel_dp *intel_dp); |
266 | 262 | ||
267 | static void pps_lock(struct intel_dp *intel_dp) |
263 | static void pps_lock(struct intel_dp *intel_dp) |
268 | { |
264 | { |
269 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
265 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
270 | struct intel_encoder *encoder = &intel_dig_port->base; |
266 | struct intel_encoder *encoder = &intel_dig_port->base; |
271 | struct drm_device *dev = encoder->base.dev; |
267 | struct drm_device *dev = encoder->base.dev; |
272 | struct drm_i915_private *dev_priv = dev->dev_private; |
268 | struct drm_i915_private *dev_priv = dev->dev_private; |
273 | enum intel_display_power_domain power_domain; |
269 | enum intel_display_power_domain power_domain; |
274 | 270 | ||
275 | /* |
271 | /* |
276 | * See vlv_power_sequencer_reset() why we need |
272 | * See vlv_power_sequencer_reset() why we need |
277 | * a power domain reference here. |
273 | * a power domain reference here. |
278 | */ |
274 | */ |
279 | power_domain = intel_display_port_aux_power_domain(encoder); |
275 | power_domain = intel_display_port_aux_power_domain(encoder); |
280 | intel_display_power_get(dev_priv, power_domain); |
276 | intel_display_power_get(dev_priv, power_domain); |
281 | 277 | ||
282 | mutex_lock(&dev_priv->pps_mutex); |
278 | mutex_lock(&dev_priv->pps_mutex); |
283 | } |
279 | } |
284 | 280 | ||
285 | static void pps_unlock(struct intel_dp *intel_dp) |
281 | static void pps_unlock(struct intel_dp *intel_dp) |
286 | { |
282 | { |
287 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
283 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
288 | struct intel_encoder *encoder = &intel_dig_port->base; |
284 | struct intel_encoder *encoder = &intel_dig_port->base; |
289 | struct drm_device *dev = encoder->base.dev; |
285 | struct drm_device *dev = encoder->base.dev; |
290 | struct drm_i915_private *dev_priv = dev->dev_private; |
286 | struct drm_i915_private *dev_priv = dev->dev_private; |
291 | enum intel_display_power_domain power_domain; |
287 | enum intel_display_power_domain power_domain; |
292 | 288 | ||
293 | mutex_unlock(&dev_priv->pps_mutex); |
289 | mutex_unlock(&dev_priv->pps_mutex); |
294 | 290 | ||
295 | power_domain = intel_display_port_aux_power_domain(encoder); |
291 | power_domain = intel_display_port_aux_power_domain(encoder); |
296 | intel_display_power_put(dev_priv, power_domain); |
292 | intel_display_power_put(dev_priv, power_domain); |
297 | } |
293 | } |
298 | 294 | ||
299 | static void |
295 | static void |
300 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
296 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
301 | { |
297 | { |
302 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
298 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
303 | struct drm_device *dev = intel_dig_port->base.base.dev; |
299 | struct drm_device *dev = intel_dig_port->base.base.dev; |
304 | struct drm_i915_private *dev_priv = dev->dev_private; |
300 | struct drm_i915_private *dev_priv = dev->dev_private; |
305 | enum pipe pipe = intel_dp->pps_pipe; |
301 | enum pipe pipe = intel_dp->pps_pipe; |
306 | bool pll_enabled, release_cl_override = false; |
302 | bool pll_enabled, release_cl_override = false; |
307 | enum dpio_phy phy = DPIO_PHY(pipe); |
303 | enum dpio_phy phy = DPIO_PHY(pipe); |
308 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
304 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
309 | uint32_t DP; |
305 | uint32_t DP; |
310 | 306 | ||
311 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
307 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
312 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
308 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
313 | pipe_name(pipe), port_name(intel_dig_port->port))) |
309 | pipe_name(pipe), port_name(intel_dig_port->port))) |
314 | return; |
310 | return; |
315 | 311 | ||
316 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
312 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
317 | pipe_name(pipe), port_name(intel_dig_port->port)); |
313 | pipe_name(pipe), port_name(intel_dig_port->port)); |
318 | 314 | ||
319 | /* Preserve the BIOS-computed detected bit. This is |
315 | /* Preserve the BIOS-computed detected bit. This is |
320 | * supposed to be read-only. |
316 | * supposed to be read-only. |
321 | */ |
317 | */ |
322 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
318 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
323 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
319 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
324 | DP |= DP_PORT_WIDTH(1); |
320 | DP |= DP_PORT_WIDTH(1); |
325 | DP |= DP_LINK_TRAIN_PAT_1; |
321 | DP |= DP_LINK_TRAIN_PAT_1; |
326 | 322 | ||
327 | if (IS_CHERRYVIEW(dev)) |
323 | if (IS_CHERRYVIEW(dev)) |
328 | DP |= DP_PIPE_SELECT_CHV(pipe); |
324 | DP |= DP_PIPE_SELECT_CHV(pipe); |
329 | else if (pipe == PIPE_B) |
325 | else if (pipe == PIPE_B) |
330 | DP |= DP_PIPEB_SELECT; |
326 | DP |= DP_PIPEB_SELECT; |
331 | 327 | ||
332 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
328 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
333 | 329 | ||
334 | /* |
330 | /* |
335 | * The DPLL for the pipe must be enabled for this to work. |
331 | * The DPLL for the pipe must be enabled for this to work. |
336 | * So enable temporarily it if it's not already enabled. |
332 | * So enable temporarily it if it's not already enabled. |
337 | */ |
333 | */ |
338 | if (!pll_enabled) { |
334 | if (!pll_enabled) { |
339 | release_cl_override = IS_CHERRYVIEW(dev) && |
335 | release_cl_override = IS_CHERRYVIEW(dev) && |
340 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
336 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
341 | 337 | ||
342 | vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
338 | if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
- | 339 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
|
- | 340 | DRM_ERROR("Failed to force on pll for pipe %c!\n", |
|
- | 341 | pipe_name(pipe)); |
|
- | 342 | return; |
|
343 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll); |
343 | } |
344 | } |
344 | } |
345 | 345 | ||
346 | /* |
346 | /* |
347 | * Similar magic as in intel_dp_enable_port(). |
347 | * Similar magic as in intel_dp_enable_port(). |
348 | * We _must_ do this port enable + disable trick |
348 | * We _must_ do this port enable + disable trick |
349 | * to make this power seqeuencer lock onto the port. |
349 | * to make this power seqeuencer lock onto the port. |
350 | * Otherwise even VDD force bit won't work. |
350 | * Otherwise even VDD force bit won't work. |
351 | */ |
351 | */ |
352 | I915_WRITE(intel_dp->output_reg, DP); |
352 | I915_WRITE(intel_dp->output_reg, DP); |
353 | POSTING_READ(intel_dp->output_reg); |
353 | POSTING_READ(intel_dp->output_reg); |
354 | 354 | ||
355 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
355 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
356 | POSTING_READ(intel_dp->output_reg); |
356 | POSTING_READ(intel_dp->output_reg); |
357 | 357 | ||
358 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
358 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
359 | POSTING_READ(intel_dp->output_reg); |
359 | POSTING_READ(intel_dp->output_reg); |
360 | 360 | ||
361 | if (!pll_enabled) { |
361 | if (!pll_enabled) { |
362 | vlv_force_pll_off(dev, pipe); |
362 | vlv_force_pll_off(dev, pipe); |
363 | 363 | ||
364 | if (release_cl_override) |
364 | if (release_cl_override) |
365 | chv_phy_powergate_ch(dev_priv, phy, ch, false); |
365 | chv_phy_powergate_ch(dev_priv, phy, ch, false); |
366 | } |
366 | } |
367 | } |
367 | } |
368 | 368 | ||
369 | static enum pipe |
369 | static enum pipe |
370 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
370 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
371 | { |
371 | { |
372 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
372 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
373 | struct drm_device *dev = intel_dig_port->base.base.dev; |
373 | struct drm_device *dev = intel_dig_port->base.base.dev; |
374 | struct drm_i915_private *dev_priv = dev->dev_private; |
374 | struct drm_i915_private *dev_priv = dev->dev_private; |
375 | struct intel_encoder *encoder; |
375 | struct intel_encoder *encoder; |
376 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
376 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
377 | enum pipe pipe; |
377 | enum pipe pipe; |
378 | 378 | ||
379 | lockdep_assert_held(&dev_priv->pps_mutex); |
379 | lockdep_assert_held(&dev_priv->pps_mutex); |
380 | 380 | ||
381 | /* We should never land here with regular DP ports */ |
381 | /* We should never land here with regular DP ports */ |
382 | WARN_ON(!is_edp(intel_dp)); |
382 | WARN_ON(!is_edp(intel_dp)); |
383 | 383 | ||
384 | if (intel_dp->pps_pipe != INVALID_PIPE) |
384 | if (intel_dp->pps_pipe != INVALID_PIPE) |
385 | return intel_dp->pps_pipe; |
385 | return intel_dp->pps_pipe; |
386 | 386 | ||
387 | /* |
387 | /* |
388 | * We don't have power sequencer currently. |
388 | * We don't have power sequencer currently. |
389 | * Pick one that's not used by other ports. |
389 | * Pick one that's not used by other ports. |
390 | */ |
390 | */ |
391 | for_each_intel_encoder(dev, encoder) { |
391 | for_each_intel_encoder(dev, encoder) { |
392 | struct intel_dp *tmp; |
392 | struct intel_dp *tmp; |
393 | 393 | ||
394 | if (encoder->type != INTEL_OUTPUT_EDP) |
394 | if (encoder->type != INTEL_OUTPUT_EDP) |
395 | continue; |
395 | continue; |
396 | 396 | ||
397 | tmp = enc_to_intel_dp(&encoder->base); |
397 | tmp = enc_to_intel_dp(&encoder->base); |
398 | 398 | ||
399 | if (tmp->pps_pipe != INVALID_PIPE) |
399 | if (tmp->pps_pipe != INVALID_PIPE) |
400 | pipes &= ~(1 << tmp->pps_pipe); |
400 | pipes &= ~(1 << tmp->pps_pipe); |
401 | } |
401 | } |
402 | 402 | ||
403 | /* |
403 | /* |
404 | * Didn't find one. This should not happen since there |
404 | * Didn't find one. This should not happen since there |
405 | * are two power sequencers and up to two eDP ports. |
405 | * are two power sequencers and up to two eDP ports. |
406 | */ |
406 | */ |
407 | if (WARN_ON(pipes == 0)) |
407 | if (WARN_ON(pipes == 0)) |
408 | pipe = PIPE_A; |
408 | pipe = PIPE_A; |
409 | else |
409 | else |
410 | pipe = ffs(pipes) - 1; |
410 | pipe = ffs(pipes) - 1; |
411 | 411 | ||
412 | vlv_steal_power_sequencer(dev, pipe); |
412 | vlv_steal_power_sequencer(dev, pipe); |
413 | intel_dp->pps_pipe = pipe; |
413 | intel_dp->pps_pipe = pipe; |
414 | 414 | ||
415 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
415 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
416 | pipe_name(intel_dp->pps_pipe), |
416 | pipe_name(intel_dp->pps_pipe), |
417 | port_name(intel_dig_port->port)); |
417 | port_name(intel_dig_port->port)); |
418 | 418 | ||
419 | /* init power sequencer on this pipe and port */ |
419 | /* init power sequencer on this pipe and port */ |
420 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
420 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
421 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
421 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
422 | 422 | ||
423 | /* |
423 | /* |
424 | * Even vdd force doesn't work until we've made |
424 | * Even vdd force doesn't work until we've made |
425 | * the power sequencer lock in on the port. |
425 | * the power sequencer lock in on the port. |
426 | */ |
426 | */ |
427 | vlv_power_sequencer_kick(intel_dp); |
427 | vlv_power_sequencer_kick(intel_dp); |
428 | 428 | ||
429 | return intel_dp->pps_pipe; |
429 | return intel_dp->pps_pipe; |
430 | } |
430 | } |
431 | 431 | ||
432 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
432 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
433 | enum pipe pipe); |
433 | enum pipe pipe); |
434 | 434 | ||
435 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
435 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
436 | enum pipe pipe) |
436 | enum pipe pipe) |
437 | { |
437 | { |
438 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; |
438 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; |
439 | } |
439 | } |
440 | 440 | ||
441 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
441 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
442 | enum pipe pipe) |
442 | enum pipe pipe) |
443 | { |
443 | { |
444 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
444 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
445 | } |
445 | } |
446 | 446 | ||
447 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
447 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
448 | enum pipe pipe) |
448 | enum pipe pipe) |
449 | { |
449 | { |
450 | return true; |
450 | return true; |
451 | } |
451 | } |
452 | 452 | ||
453 | static enum pipe |
453 | static enum pipe |
454 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
454 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
455 | enum port port, |
455 | enum port port, |
456 | vlv_pipe_check pipe_check) |
456 | vlv_pipe_check pipe_check) |
457 | { |
457 | { |
458 | enum pipe pipe; |
458 | enum pipe pipe; |
459 | 459 | ||
460 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
460 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
461 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
461 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
462 | PANEL_PORT_SELECT_MASK; |
462 | PANEL_PORT_SELECT_MASK; |
463 | 463 | ||
464 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
464 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
465 | continue; |
465 | continue; |
466 | 466 | ||
467 | if (!pipe_check(dev_priv, pipe)) |
467 | if (!pipe_check(dev_priv, pipe)) |
468 | continue; |
468 | continue; |
469 | 469 | ||
470 | return pipe; |
470 | return pipe; |
471 | } |
471 | } |
472 | 472 | ||
473 | return INVALID_PIPE; |
473 | return INVALID_PIPE; |
474 | } |
474 | } |
475 | 475 | ||
476 | static void |
476 | static void |
477 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
477 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
478 | { |
478 | { |
479 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
479 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
480 | struct drm_device *dev = intel_dig_port->base.base.dev; |
480 | struct drm_device *dev = intel_dig_port->base.base.dev; |
481 | struct drm_i915_private *dev_priv = dev->dev_private; |
481 | struct drm_i915_private *dev_priv = dev->dev_private; |
482 | enum port port = intel_dig_port->port; |
482 | enum port port = intel_dig_port->port; |
483 | 483 | ||
484 | lockdep_assert_held(&dev_priv->pps_mutex); |
484 | lockdep_assert_held(&dev_priv->pps_mutex); |
485 | 485 | ||
486 | /* try to find a pipe with this port selected */ |
486 | /* try to find a pipe with this port selected */ |
487 | /* first pick one where the panel is on */ |
487 | /* first pick one where the panel is on */ |
488 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
488 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
489 | vlv_pipe_has_pp_on); |
489 | vlv_pipe_has_pp_on); |
490 | /* didn't find one? pick one where vdd is on */ |
490 | /* didn't find one? pick one where vdd is on */ |
491 | if (intel_dp->pps_pipe == INVALID_PIPE) |
491 | if (intel_dp->pps_pipe == INVALID_PIPE) |
492 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
492 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
493 | vlv_pipe_has_vdd_on); |
493 | vlv_pipe_has_vdd_on); |
494 | /* didn't find one? pick one with just the correct port */ |
494 | /* didn't find one? pick one with just the correct port */ |
495 | if (intel_dp->pps_pipe == INVALID_PIPE) |
495 | if (intel_dp->pps_pipe == INVALID_PIPE) |
496 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
496 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
497 | vlv_pipe_any); |
497 | vlv_pipe_any); |
498 | 498 | ||
499 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
499 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
500 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
500 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
501 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
501 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
502 | port_name(port)); |
502 | port_name(port)); |
503 | return; |
503 | return; |
504 | } |
504 | } |
505 | 505 | ||
506 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
506 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
507 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
507 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
508 | 508 | ||
509 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
509 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
510 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
510 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
511 | } |
511 | } |
512 | 512 | ||
513 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
513 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
514 | { |
514 | { |
515 | struct drm_device *dev = dev_priv->dev; |
515 | struct drm_device *dev = dev_priv->dev; |
516 | struct intel_encoder *encoder; |
516 | struct intel_encoder *encoder; |
517 | 517 | ||
518 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))) |
518 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))) |
519 | return; |
519 | return; |
520 | 520 | ||
521 | /* |
521 | /* |
522 | * We can't grab pps_mutex here due to deadlock with power_domain |
522 | * We can't grab pps_mutex here due to deadlock with power_domain |
523 | * mutex when power_domain functions are called while holding pps_mutex. |
523 | * mutex when power_domain functions are called while holding pps_mutex. |
524 | * That also means that in order to use pps_pipe the code needs to |
524 | * That also means that in order to use pps_pipe the code needs to |
525 | * hold both a power domain reference and pps_mutex, and the power domain |
525 | * hold both a power domain reference and pps_mutex, and the power domain |
526 | * reference get/put must be done while _not_ holding pps_mutex. |
526 | * reference get/put must be done while _not_ holding pps_mutex. |
527 | * pps_{lock,unlock}() do these steps in the correct order, so one |
527 | * pps_{lock,unlock}() do these steps in the correct order, so one |
528 | * should use them always. |
528 | * should use them always. |
529 | */ |
529 | */ |
530 | 530 | ||
531 | for_each_intel_encoder(dev, encoder) { |
531 | for_each_intel_encoder(dev, encoder) { |
532 | struct intel_dp *intel_dp; |
532 | struct intel_dp *intel_dp; |
533 | 533 | ||
534 | if (encoder->type != INTEL_OUTPUT_EDP) |
534 | if (encoder->type != INTEL_OUTPUT_EDP) |
535 | continue; |
535 | continue; |
536 | 536 | ||
537 | intel_dp = enc_to_intel_dp(&encoder->base); |
537 | intel_dp = enc_to_intel_dp(&encoder->base); |
538 | intel_dp->pps_pipe = INVALID_PIPE; |
538 | intel_dp->pps_pipe = INVALID_PIPE; |
539 | } |
539 | } |
540 | } |
540 | } |
541 | 541 | ||
542 | static i915_reg_t |
542 | static i915_reg_t |
543 | _pp_ctrl_reg(struct intel_dp *intel_dp) |
543 | _pp_ctrl_reg(struct intel_dp *intel_dp) |
544 | { |
544 | { |
545 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
545 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
546 | 546 | ||
547 | if (IS_BROXTON(dev)) |
547 | if (IS_BROXTON(dev)) |
548 | return BXT_PP_CONTROL(0); |
548 | return BXT_PP_CONTROL(0); |
549 | else if (HAS_PCH_SPLIT(dev)) |
549 | else if (HAS_PCH_SPLIT(dev)) |
550 | return PCH_PP_CONTROL; |
550 | return PCH_PP_CONTROL; |
551 | else |
551 | else |
552 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
552 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
553 | } |
553 | } |
554 | 554 | ||
555 | static i915_reg_t |
555 | static i915_reg_t |
556 | _pp_stat_reg(struct intel_dp *intel_dp) |
556 | _pp_stat_reg(struct intel_dp *intel_dp) |
557 | { |
557 | { |
558 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
558 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
559 | 559 | ||
560 | if (IS_BROXTON(dev)) |
560 | if (IS_BROXTON(dev)) |
561 | return BXT_PP_STATUS(0); |
561 | return BXT_PP_STATUS(0); |
562 | else if (HAS_PCH_SPLIT(dev)) |
562 | else if (HAS_PCH_SPLIT(dev)) |
563 | return PCH_PP_STATUS; |
563 | return PCH_PP_STATUS; |
564 | else |
564 | else |
565 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
565 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
566 | } |
566 | } |
567 | 567 | ||
568 | #if 0 |
568 | #if 0 |
569 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
569 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
570 | This function only applicable when panel PM state is not to be tracked */ |
570 | This function only applicable when panel PM state is not to be tracked */ |
571 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
571 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
572 | void *unused) |
572 | void *unused) |
573 | { |
573 | { |
574 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
574 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
575 | edp_notifier); |
575 | edp_notifier); |
576 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
576 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
577 | struct drm_i915_private *dev_priv = dev->dev_private; |
577 | struct drm_i915_private *dev_priv = dev->dev_private; |
578 | 578 | ||
579 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
579 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
580 | return 0; |
580 | return 0; |
581 | 581 | ||
582 | pps_lock(intel_dp); |
582 | pps_lock(intel_dp); |
583 | 583 | ||
584 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
584 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
585 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
585 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
586 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
586 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
587 | u32 pp_div; |
587 | u32 pp_div; |
588 | 588 | ||
589 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
589 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
590 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
590 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
591 | pp_div = I915_READ(pp_div_reg); |
591 | pp_div = I915_READ(pp_div_reg); |
592 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
592 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
593 | 593 | ||
594 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
594 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
595 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
595 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
596 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
596 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
597 | msleep(intel_dp->panel_power_cycle_delay); |
597 | msleep(intel_dp->panel_power_cycle_delay); |
598 | } |
598 | } |
599 | 599 | ||
600 | pps_unlock(intel_dp); |
600 | pps_unlock(intel_dp); |
601 | 601 | ||
602 | return 0; |
602 | return 0; |
603 | } |
603 | } |
604 | #endif |
604 | #endif |
605 | 605 | ||
606 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
606 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
607 | { |
607 | { |
608 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
608 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
609 | struct drm_i915_private *dev_priv = dev->dev_private; |
609 | struct drm_i915_private *dev_priv = dev->dev_private; |
610 | 610 | ||
611 | lockdep_assert_held(&dev_priv->pps_mutex); |
611 | lockdep_assert_held(&dev_priv->pps_mutex); |
612 | 612 | ||
613 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
613 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
614 | intel_dp->pps_pipe == INVALID_PIPE) |
614 | intel_dp->pps_pipe == INVALID_PIPE) |
615 | return false; |
615 | return false; |
616 | 616 | ||
617 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
617 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
618 | } |
618 | } |
619 | 619 | ||
620 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
620 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
621 | { |
621 | { |
622 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
622 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
623 | struct drm_i915_private *dev_priv = dev->dev_private; |
623 | struct drm_i915_private *dev_priv = dev->dev_private; |
624 | 624 | ||
625 | lockdep_assert_held(&dev_priv->pps_mutex); |
625 | lockdep_assert_held(&dev_priv->pps_mutex); |
626 | 626 | ||
627 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
627 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
628 | intel_dp->pps_pipe == INVALID_PIPE) |
628 | intel_dp->pps_pipe == INVALID_PIPE) |
629 | return false; |
629 | return false; |
630 | 630 | ||
631 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
631 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
632 | } |
632 | } |
633 | 633 | ||
634 | static void |
634 | static void |
635 | intel_dp_check_edp(struct intel_dp *intel_dp) |
635 | intel_dp_check_edp(struct intel_dp *intel_dp) |
636 | { |
636 | { |
637 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
637 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
638 | struct drm_i915_private *dev_priv = dev->dev_private; |
638 | struct drm_i915_private *dev_priv = dev->dev_private; |
639 | 639 | ||
640 | if (!is_edp(intel_dp)) |
640 | if (!is_edp(intel_dp)) |
641 | return; |
641 | return; |
642 | 642 | ||
643 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
643 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
644 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
644 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
645 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
645 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
646 | I915_READ(_pp_stat_reg(intel_dp)), |
646 | I915_READ(_pp_stat_reg(intel_dp)), |
647 | I915_READ(_pp_ctrl_reg(intel_dp))); |
647 | I915_READ(_pp_ctrl_reg(intel_dp))); |
648 | } |
648 | } |
649 | } |
649 | } |
650 | 650 | ||
651 | static uint32_t |
651 | static uint32_t |
652 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
652 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
653 | { |
653 | { |
654 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
654 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
655 | struct drm_device *dev = intel_dig_port->base.base.dev; |
655 | struct drm_device *dev = intel_dig_port->base.base.dev; |
656 | struct drm_i915_private *dev_priv = dev->dev_private; |
656 | struct drm_i915_private *dev_priv = dev->dev_private; |
657 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
657 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
658 | uint32_t status; |
658 | uint32_t status; |
659 | bool done; |
659 | bool done; |
660 | 660 | ||
661 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
661 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
662 | if (has_aux_irq) |
662 | if (has_aux_irq) |
663 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
663 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
664 | msecs_to_jiffies_timeout(10)); |
664 | msecs_to_jiffies_timeout(10)); |
665 | else |
665 | else |
666 | done = wait_for_atomic(C, 10) == 0; |
666 | done = wait_for_atomic(C, 10) == 0; |
667 | if (!done) |
667 | if (!done) |
668 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
668 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
669 | has_aux_irq); |
669 | has_aux_irq); |
670 | #undef C |
670 | #undef C |
671 | 671 | ||
672 | return status; |
672 | return status; |
673 | } |
673 | } |
674 | 674 | ||
675 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
675 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
676 | { |
676 | { |
677 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
677 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
678 | struct drm_device *dev = intel_dig_port->base.base.dev; |
678 | struct drm_device *dev = intel_dig_port->base.base.dev; |
679 | 679 | ||
680 | /* |
680 | /* |
681 | * The clock divider is based off the hrawclk, and would like to run at |
681 | * The clock divider is based off the hrawclk, and would like to run at |
682 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
682 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
683 | */ |
683 | */ |
684 | return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2); |
684 | return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2); |
685 | } |
685 | } |
686 | 686 | ||
687 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
687 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
688 | { |
688 | { |
689 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
689 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
690 | struct drm_device *dev = intel_dig_port->base.base.dev; |
690 | struct drm_device *dev = intel_dig_port->base.base.dev; |
691 | struct drm_i915_private *dev_priv = dev->dev_private; |
691 | struct drm_i915_private *dev_priv = dev->dev_private; |
692 | 692 | ||
693 | if (index) |
693 | if (index) |
694 | return 0; |
694 | return 0; |
695 | 695 | ||
696 | if (intel_dig_port->port == PORT_A) { |
696 | if (intel_dig_port->port == PORT_A) { |
697 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
697 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
698 | 698 | ||
699 | } else { |
699 | } else { |
700 | return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); |
700 | return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); |
701 | } |
701 | } |
702 | } |
702 | } |
703 | 703 | ||
704 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
704 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
705 | { |
705 | { |
706 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
706 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
707 | struct drm_device *dev = intel_dig_port->base.base.dev; |
707 | struct drm_device *dev = intel_dig_port->base.base.dev; |
708 | struct drm_i915_private *dev_priv = dev->dev_private; |
708 | struct drm_i915_private *dev_priv = dev->dev_private; |
709 | 709 | ||
710 | if (intel_dig_port->port == PORT_A) { |
710 | if (intel_dig_port->port == PORT_A) { |
711 | if (index) |
711 | if (index) |
712 | return 0; |
712 | return 0; |
713 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
713 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
714 | } else if (HAS_PCH_LPT_H(dev_priv)) { |
714 | } else if (HAS_PCH_LPT_H(dev_priv)) { |
715 | /* Workaround for non-ULT HSW */ |
715 | /* Workaround for non-ULT HSW */ |
716 | switch (index) { |
716 | switch (index) { |
717 | case 0: return 63; |
717 | case 0: return 63; |
718 | case 1: return 72; |
718 | case 1: return 72; |
719 | default: return 0; |
719 | default: return 0; |
720 | } |
720 | } |
721 | } else { |
721 | } else { |
722 | return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); |
722 | return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); |
723 | } |
723 | } |
724 | } |
724 | } |
725 | 725 | ||
726 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
726 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
727 | { |
727 | { |
728 | return index ? 0 : 100; |
728 | return index ? 0 : 100; |
729 | } |
729 | } |
730 | 730 | ||
731 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
731 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
732 | { |
732 | { |
733 | /* |
733 | /* |
734 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
734 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
735 | * derive the clock from CDCLK automatically). We still implement the |
735 | * derive the clock from CDCLK automatically). We still implement the |
736 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
736 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
737 | */ |
737 | */ |
738 | return index ? 0 : 1; |
738 | return index ? 0 : 1; |
739 | } |
739 | } |
740 | 740 | ||
741 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
741 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
742 | bool has_aux_irq, |
742 | bool has_aux_irq, |
743 | int send_bytes, |
743 | int send_bytes, |
744 | uint32_t aux_clock_divider) |
744 | uint32_t aux_clock_divider) |
745 | { |
745 | { |
746 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
746 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
747 | struct drm_device *dev = intel_dig_port->base.base.dev; |
747 | struct drm_device *dev = intel_dig_port->base.base.dev; |
748 | uint32_t precharge, timeout; |
748 | uint32_t precharge, timeout; |
749 | 749 | ||
750 | if (IS_GEN6(dev)) |
750 | if (IS_GEN6(dev)) |
751 | precharge = 3; |
751 | precharge = 3; |
752 | else |
752 | else |
753 | precharge = 5; |
753 | precharge = 5; |
754 | 754 | ||
755 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
755 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
756 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
756 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
757 | else |
757 | else |
758 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
758 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
759 | 759 | ||
760 | return DP_AUX_CH_CTL_SEND_BUSY | |
760 | return DP_AUX_CH_CTL_SEND_BUSY | |
761 | DP_AUX_CH_CTL_DONE | |
761 | DP_AUX_CH_CTL_DONE | |
762 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
762 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
763 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
763 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
764 | timeout | |
764 | timeout | |
765 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
765 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
766 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
766 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
767 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
767 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
768 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
768 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
769 | } |
769 | } |
770 | 770 | ||
771 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
771 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
772 | bool has_aux_irq, |
772 | bool has_aux_irq, |
773 | int send_bytes, |
773 | int send_bytes, |
774 | uint32_t unused) |
774 | uint32_t unused) |
775 | { |
775 | { |
776 | return DP_AUX_CH_CTL_SEND_BUSY | |
776 | return DP_AUX_CH_CTL_SEND_BUSY | |
777 | DP_AUX_CH_CTL_DONE | |
777 | DP_AUX_CH_CTL_DONE | |
778 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
778 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
779 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
779 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
780 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
780 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
781 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
781 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
782 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
782 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
783 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
783 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
784 | } |
784 | } |
785 | 785 | ||
786 | static int |
786 | static int |
787 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
787 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
788 | const uint8_t *send, int send_bytes, |
788 | const uint8_t *send, int send_bytes, |
789 | uint8_t *recv, int recv_size) |
789 | uint8_t *recv, int recv_size) |
790 | { |
790 | { |
791 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
791 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
792 | struct drm_device *dev = intel_dig_port->base.base.dev; |
792 | struct drm_device *dev = intel_dig_port->base.base.dev; |
793 | struct drm_i915_private *dev_priv = dev->dev_private; |
793 | struct drm_i915_private *dev_priv = dev->dev_private; |
794 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
794 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
795 | uint32_t aux_clock_divider; |
795 | uint32_t aux_clock_divider; |
796 | int i, ret, recv_bytes; |
796 | int i, ret, recv_bytes; |
797 | uint32_t status; |
797 | uint32_t status; |
798 | int try, clock = 0; |
798 | int try, clock = 0; |
799 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
799 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
800 | bool vdd; |
800 | bool vdd; |
801 | 801 | ||
802 | pps_lock(intel_dp); |
802 | pps_lock(intel_dp); |
803 | 803 | ||
804 | /* |
804 | /* |
805 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
805 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
806 | * In such cases we want to leave VDD enabled and it's up to upper layers |
806 | * In such cases we want to leave VDD enabled and it's up to upper layers |
807 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
807 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
808 | * ourselves. |
808 | * ourselves. |
809 | */ |
809 | */ |
810 | vdd = edp_panel_vdd_on(intel_dp); |
810 | vdd = edp_panel_vdd_on(intel_dp); |
811 | 811 | ||
812 | /* dp aux is extremely sensitive to irq latency, hence request the |
812 | /* dp aux is extremely sensitive to irq latency, hence request the |
813 | * lowest possible wakeup latency and so prevent the cpu from going into |
813 | * lowest possible wakeup latency and so prevent the cpu from going into |
814 | * deep sleep states. |
814 | * deep sleep states. |
815 | */ |
815 | */ |
816 | 816 | ||
817 | intel_dp_check_edp(intel_dp); |
817 | intel_dp_check_edp(intel_dp); |
818 | 818 | ||
819 | /* Try to wait for any previous AUX channel activity */ |
819 | /* Try to wait for any previous AUX channel activity */ |
820 | for (try = 0; try < 3; try++) { |
820 | for (try = 0; try < 3; try++) { |
821 | status = I915_READ_NOTRACE(ch_ctl); |
821 | status = I915_READ_NOTRACE(ch_ctl); |
822 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
822 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
823 | break; |
823 | break; |
824 | msleep(1); |
824 | msleep(1); |
825 | } |
825 | } |
826 | 826 | ||
827 | if (try == 3) { |
827 | if (try == 3) { |
828 | static u32 last_status = -1; |
828 | static u32 last_status = -1; |
829 | const u32 status = I915_READ(ch_ctl); |
829 | const u32 status = I915_READ(ch_ctl); |
830 | 830 | ||
831 | if (status != last_status) { |
831 | if (status != last_status) { |
832 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
832 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
833 | status); |
833 | status); |
834 | last_status = status; |
834 | last_status = status; |
835 | } |
835 | } |
836 | 836 | ||
837 | ret = -EBUSY; |
837 | ret = -EBUSY; |
838 | goto out; |
838 | goto out; |
839 | } |
839 | } |
840 | 840 | ||
841 | /* Only 5 data registers! */ |
841 | /* Only 5 data registers! */ |
842 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
842 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
843 | ret = -E2BIG; |
843 | ret = -E2BIG; |
844 | goto out; |
844 | goto out; |
845 | } |
845 | } |
846 | 846 | ||
847 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
847 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
848 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
848 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
849 | has_aux_irq, |
849 | has_aux_irq, |
850 | send_bytes, |
850 | send_bytes, |
851 | aux_clock_divider); |
851 | aux_clock_divider); |
852 | 852 | ||
853 | /* Must try at least 3 times according to DP spec */ |
853 | /* Must try at least 3 times according to DP spec */ |
854 | for (try = 0; try < 5; try++) { |
854 | for (try = 0; try < 5; try++) { |
855 | /* Load the send data into the aux channel data registers */ |
855 | /* Load the send data into the aux channel data registers */ |
856 | for (i = 0; i < send_bytes; i += 4) |
856 | for (i = 0; i < send_bytes; i += 4) |
857 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
857 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
858 | intel_dp_pack_aux(send + i, |
858 | intel_dp_pack_aux(send + i, |
859 | send_bytes - i)); |
859 | send_bytes - i)); |
860 | 860 | ||
861 | /* Send the command and wait for it to complete */ |
861 | /* Send the command and wait for it to complete */ |
862 | I915_WRITE(ch_ctl, send_ctl); |
862 | I915_WRITE(ch_ctl, send_ctl); |
863 | 863 | ||
864 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
864 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
865 | 865 | ||
866 | /* Clear done status and any errors */ |
866 | /* Clear done status and any errors */ |
867 | I915_WRITE(ch_ctl, |
867 | I915_WRITE(ch_ctl, |
868 | status | |
868 | status | |
869 | DP_AUX_CH_CTL_DONE | |
869 | DP_AUX_CH_CTL_DONE | |
870 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
870 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
871 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
871 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
872 | 872 | ||
873 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
873 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
874 | continue; |
874 | continue; |
875 | 875 | ||
876 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
876 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
877 | * 400us delay required for errors and timeouts |
877 | * 400us delay required for errors and timeouts |
878 | * Timeout errors from the HW already meet this |
878 | * Timeout errors from the HW already meet this |
879 | * requirement so skip to next iteration |
879 | * requirement so skip to next iteration |
880 | */ |
880 | */ |
881 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
881 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
882 | usleep_range(400, 500); |
882 | usleep_range(400, 500); |
883 | continue; |
883 | continue; |
884 | } |
884 | } |
885 | if (status & DP_AUX_CH_CTL_DONE) |
885 | if (status & DP_AUX_CH_CTL_DONE) |
886 | goto done; |
886 | goto done; |
887 | } |
887 | } |
888 | } |
888 | } |
889 | 889 | ||
890 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
890 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
891 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
891 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
892 | ret = -EBUSY; |
892 | ret = -EBUSY; |
893 | goto out; |
893 | goto out; |
894 | } |
894 | } |
895 | 895 | ||
896 | done: |
896 | done: |
897 | /* Check for timeout or receive error. |
897 | /* Check for timeout or receive error. |
898 | * Timeouts occur when the sink is not connected |
898 | * Timeouts occur when the sink is not connected |
899 | */ |
899 | */ |
900 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
900 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
901 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
901 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
902 | ret = -EIO; |
902 | ret = -EIO; |
903 | goto out; |
903 | goto out; |
904 | } |
904 | } |
905 | 905 | ||
906 | /* Timeouts occur when the device isn't connected, so they're |
906 | /* Timeouts occur when the device isn't connected, so they're |
907 | * "normal" -- don't fill the kernel log with these */ |
907 | * "normal" -- don't fill the kernel log with these */ |
908 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
908 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
909 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
909 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
910 | ret = -ETIMEDOUT; |
910 | ret = -ETIMEDOUT; |
911 | goto out; |
911 | goto out; |
912 | } |
912 | } |
913 | 913 | ||
914 | /* Unload any bytes sent back from the other side */ |
914 | /* Unload any bytes sent back from the other side */ |
915 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
915 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
916 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
916 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
917 | 917 | ||
918 | /* |
918 | /* |
919 | * By BSpec: "Message sizes of 0 or >20 are not allowed." |
919 | * By BSpec: "Message sizes of 0 or >20 are not allowed." |
920 | * We have no idea of what happened so we return -EBUSY so |
920 | * We have no idea of what happened so we return -EBUSY so |
921 | * drm layer takes care for the necessary retries. |
921 | * drm layer takes care for the necessary retries. |
922 | */ |
922 | */ |
923 | if (recv_bytes == 0 || recv_bytes > 20) { |
923 | if (recv_bytes == 0 || recv_bytes > 20) { |
924 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", |
924 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", |
925 | recv_bytes); |
925 | recv_bytes); |
926 | /* |
926 | /* |
927 | * FIXME: This patch was created on top of a series that |
927 | * FIXME: This patch was created on top of a series that |
928 | * organize the retries at drm level. There EBUSY should |
928 | * organize the retries at drm level. There EBUSY should |
929 | * also take care for 1ms wait before retrying. |
929 | * also take care for 1ms wait before retrying. |
930 | * That aux retries re-org is still needed and after that is |
930 | * That aux retries re-org is still needed and after that is |
931 | * merged we remove this sleep from here. |
931 | * merged we remove this sleep from here. |
932 | */ |
932 | */ |
933 | usleep_range(1000, 1500); |
933 | usleep_range(1000, 1500); |
934 | ret = -EBUSY; |
934 | ret = -EBUSY; |
935 | goto out; |
935 | goto out; |
936 | } |
936 | } |
937 | 937 | ||
938 | if (recv_bytes > recv_size) |
938 | if (recv_bytes > recv_size) |
939 | recv_bytes = recv_size; |
939 | recv_bytes = recv_size; |
940 | 940 | ||
941 | for (i = 0; i < recv_bytes; i += 4) |
941 | for (i = 0; i < recv_bytes; i += 4) |
942 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
942 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
943 | recv + i, recv_bytes - i); |
943 | recv + i, recv_bytes - i); |
944 | 944 | ||
945 | ret = recv_bytes; |
945 | ret = recv_bytes; |
946 | out: |
946 | out: |
947 | 947 | ||
948 | if (vdd) |
948 | if (vdd) |
949 | edp_panel_vdd_off(intel_dp, false); |
949 | edp_panel_vdd_off(intel_dp, false); |
950 | 950 | ||
951 | pps_unlock(intel_dp); |
951 | pps_unlock(intel_dp); |
952 | 952 | ||
953 | return ret; |
953 | return ret; |
954 | } |
954 | } |
955 | 955 | ||
956 | #define BARE_ADDRESS_SIZE 3 |
956 | #define BARE_ADDRESS_SIZE 3 |
957 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
957 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
958 | static ssize_t |
958 | static ssize_t |
959 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
959 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
960 | { |
960 | { |
961 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
961 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
962 | uint8_t txbuf[20], rxbuf[20]; |
962 | uint8_t txbuf[20], rxbuf[20]; |
963 | size_t txsize, rxsize; |
963 | size_t txsize, rxsize; |
964 | int ret; |
964 | int ret; |
965 | 965 | ||
966 | txbuf[0] = (msg->request << 4) | |
966 | txbuf[0] = (msg->request << 4) | |
967 | ((msg->address >> 16) & 0xf); |
967 | ((msg->address >> 16) & 0xf); |
968 | txbuf[1] = (msg->address >> 8) & 0xff; |
968 | txbuf[1] = (msg->address >> 8) & 0xff; |
969 | txbuf[2] = msg->address & 0xff; |
969 | txbuf[2] = msg->address & 0xff; |
970 | txbuf[3] = msg->size - 1; |
970 | txbuf[3] = msg->size - 1; |
971 | 971 | ||
972 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
972 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
973 | case DP_AUX_NATIVE_WRITE: |
973 | case DP_AUX_NATIVE_WRITE: |
974 | case DP_AUX_I2C_WRITE: |
974 | case DP_AUX_I2C_WRITE: |
975 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
975 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
976 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
976 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
977 | rxsize = 2; /* 0 or 1 data bytes */ |
977 | rxsize = 2; /* 0 or 1 data bytes */ |
978 | 978 | ||
979 | if (WARN_ON(txsize > 20)) |
979 | if (WARN_ON(txsize > 20)) |
980 | return -E2BIG; |
980 | return -E2BIG; |
- | 981 | ||
981 | 982 | if (msg->buffer) |
|
- | 983 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
|
- | 984 | else |
|
982 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
985 | WARN_ON(msg->size); |
983 | 986 | ||
984 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
987 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
985 | if (ret > 0) { |
988 | if (ret > 0) { |
986 | msg->reply = rxbuf[0] >> 4; |
989 | msg->reply = rxbuf[0] >> 4; |
987 | 990 | ||
988 | if (ret > 1) { |
991 | if (ret > 1) { |
989 | /* Number of bytes written in a short write. */ |
992 | /* Number of bytes written in a short write. */ |
990 | ret = clamp_t(int, rxbuf[1], 0, msg->size); |
993 | ret = clamp_t(int, rxbuf[1], 0, msg->size); |
991 | } else { |
994 | } else { |
992 | /* Return payload size. */ |
995 | /* Return payload size. */ |
993 | ret = msg->size; |
996 | ret = msg->size; |
994 | } |
997 | } |
995 | } |
998 | } |
996 | break; |
999 | break; |
997 | 1000 | ||
998 | case DP_AUX_NATIVE_READ: |
1001 | case DP_AUX_NATIVE_READ: |
999 | case DP_AUX_I2C_READ: |
1002 | case DP_AUX_I2C_READ: |
1000 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
1003 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
1001 | rxsize = msg->size + 1; |
1004 | rxsize = msg->size + 1; |
1002 | 1005 | ||
1003 | if (WARN_ON(rxsize > 20)) |
1006 | if (WARN_ON(rxsize > 20)) |
1004 | return -E2BIG; |
1007 | return -E2BIG; |
1005 | 1008 | ||
1006 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1009 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1007 | if (ret > 0) { |
1010 | if (ret > 0) { |
1008 | msg->reply = rxbuf[0] >> 4; |
1011 | msg->reply = rxbuf[0] >> 4; |
1009 | /* |
1012 | /* |
1010 | * Assume happy day, and copy the data. The caller is |
1013 | * Assume happy day, and copy the data. The caller is |
1011 | * expected to check msg->reply before touching it. |
1014 | * expected to check msg->reply before touching it. |
1012 | * |
1015 | * |
1013 | * Return payload size. |
1016 | * Return payload size. |
1014 | */ |
1017 | */ |
1015 | ret--; |
1018 | ret--; |
1016 | memcpy(msg->buffer, rxbuf + 1, ret); |
1019 | memcpy(msg->buffer, rxbuf + 1, ret); |
1017 | } |
1020 | } |
1018 | break; |
1021 | break; |
1019 | 1022 | ||
1020 | default: |
1023 | default: |
1021 | ret = -EINVAL; |
1024 | ret = -EINVAL; |
1022 | break; |
1025 | break; |
1023 | } |
1026 | } |
1024 | 1027 | ||
1025 | return ret; |
1028 | return ret; |
1026 | } |
1029 | } |
1027 | 1030 | ||
1028 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1031 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1029 | enum port port) |
1032 | enum port port) |
1030 | { |
1033 | { |
1031 | switch (port) { |
1034 | switch (port) { |
1032 | case PORT_B: |
1035 | case PORT_B: |
1033 | case PORT_C: |
1036 | case PORT_C: |
1034 | case PORT_D: |
1037 | case PORT_D: |
1035 | return DP_AUX_CH_CTL(port); |
1038 | return DP_AUX_CH_CTL(port); |
1036 | default: |
1039 | default: |
1037 | MISSING_CASE(port); |
1040 | MISSING_CASE(port); |
1038 | return DP_AUX_CH_CTL(PORT_B); |
1041 | return DP_AUX_CH_CTL(PORT_B); |
1039 | } |
1042 | } |
1040 | } |
1043 | } |
1041 | 1044 | ||
1042 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
1045 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
1043 | enum port port, int index) |
1046 | enum port port, int index) |
1044 | { |
1047 | { |
1045 | switch (port) { |
1048 | switch (port) { |
1046 | case PORT_B: |
1049 | case PORT_B: |
1047 | case PORT_C: |
1050 | case PORT_C: |
1048 | case PORT_D: |
1051 | case PORT_D: |
1049 | return DP_AUX_CH_DATA(port, index); |
1052 | return DP_AUX_CH_DATA(port, index); |
1050 | default: |
1053 | default: |
1051 | MISSING_CASE(port); |
1054 | MISSING_CASE(port); |
1052 | return DP_AUX_CH_DATA(PORT_B, index); |
1055 | return DP_AUX_CH_DATA(PORT_B, index); |
1053 | } |
1056 | } |
1054 | } |
1057 | } |
1055 | 1058 | ||
1056 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1059 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1057 | enum port port) |
1060 | enum port port) |
1058 | { |
1061 | { |
1059 | switch (port) { |
1062 | switch (port) { |
1060 | case PORT_A: |
1063 | case PORT_A: |
1061 | return DP_AUX_CH_CTL(port); |
1064 | return DP_AUX_CH_CTL(port); |
1062 | case PORT_B: |
1065 | case PORT_B: |
1063 | case PORT_C: |
1066 | case PORT_C: |
1064 | case PORT_D: |
1067 | case PORT_D: |
1065 | return PCH_DP_AUX_CH_CTL(port); |
1068 | return PCH_DP_AUX_CH_CTL(port); |
1066 | default: |
1069 | default: |
1067 | MISSING_CASE(port); |
1070 | MISSING_CASE(port); |
1068 | return DP_AUX_CH_CTL(PORT_A); |
1071 | return DP_AUX_CH_CTL(PORT_A); |
1069 | } |
1072 | } |
1070 | } |
1073 | } |
1071 | 1074 | ||
1072 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
1075 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
1073 | enum port port, int index) |
1076 | enum port port, int index) |
1074 | { |
1077 | { |
1075 | switch (port) { |
1078 | switch (port) { |
1076 | case PORT_A: |
1079 | case PORT_A: |
1077 | return DP_AUX_CH_DATA(port, index); |
1080 | return DP_AUX_CH_DATA(port, index); |
1078 | case PORT_B: |
1081 | case PORT_B: |
1079 | case PORT_C: |
1082 | case PORT_C: |
1080 | case PORT_D: |
1083 | case PORT_D: |
1081 | return PCH_DP_AUX_CH_DATA(port, index); |
1084 | return PCH_DP_AUX_CH_DATA(port, index); |
1082 | default: |
1085 | default: |
1083 | MISSING_CASE(port); |
1086 | MISSING_CASE(port); |
1084 | return DP_AUX_CH_DATA(PORT_A, index); |
1087 | return DP_AUX_CH_DATA(PORT_A, index); |
1085 | } |
1088 | } |
1086 | } |
1089 | } |
1087 | 1090 | ||
1088 | /* |
1091 | /* |
1089 | * On SKL we don't have Aux for port E so we rely |
1092 | * On SKL we don't have Aux for port E so we rely |
1090 | * on VBT to set a proper alternate aux channel. |
1093 | * on VBT to set a proper alternate aux channel. |
1091 | */ |
1094 | */ |
1092 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) |
1095 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) |
1093 | { |
1096 | { |
1094 | const struct ddi_vbt_port_info *info = |
1097 | const struct ddi_vbt_port_info *info = |
1095 | &dev_priv->vbt.ddi_port_info[PORT_E]; |
1098 | &dev_priv->vbt.ddi_port_info[PORT_E]; |
1096 | 1099 | ||
1097 | switch (info->alternate_aux_channel) { |
1100 | switch (info->alternate_aux_channel) { |
1098 | case DP_AUX_A: |
1101 | case DP_AUX_A: |
1099 | return PORT_A; |
1102 | return PORT_A; |
1100 | case DP_AUX_B: |
1103 | case DP_AUX_B: |
1101 | return PORT_B; |
1104 | return PORT_B; |
1102 | case DP_AUX_C: |
1105 | case DP_AUX_C: |
1103 | return PORT_C; |
1106 | return PORT_C; |
1104 | case DP_AUX_D: |
1107 | case DP_AUX_D: |
1105 | return PORT_D; |
1108 | return PORT_D; |
1106 | default: |
1109 | default: |
1107 | MISSING_CASE(info->alternate_aux_channel); |
1110 | MISSING_CASE(info->alternate_aux_channel); |
1108 | return PORT_A; |
1111 | return PORT_A; |
1109 | } |
1112 | } |
1110 | } |
1113 | } |
1111 | 1114 | ||
1112 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1115 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1113 | enum port port) |
1116 | enum port port) |
1114 | { |
1117 | { |
1115 | if (port == PORT_E) |
1118 | if (port == PORT_E) |
1116 | port = skl_porte_aux_port(dev_priv); |
1119 | port = skl_porte_aux_port(dev_priv); |
1117 | 1120 | ||
1118 | switch (port) { |
1121 | switch (port) { |
1119 | case PORT_A: |
1122 | case PORT_A: |
1120 | case PORT_B: |
1123 | case PORT_B: |
1121 | case PORT_C: |
1124 | case PORT_C: |
1122 | case PORT_D: |
1125 | case PORT_D: |
1123 | return DP_AUX_CH_CTL(port); |
1126 | return DP_AUX_CH_CTL(port); |
1124 | default: |
1127 | default: |
1125 | MISSING_CASE(port); |
1128 | MISSING_CASE(port); |
1126 | return DP_AUX_CH_CTL(PORT_A); |
1129 | return DP_AUX_CH_CTL(PORT_A); |
1127 | } |
1130 | } |
1128 | } |
1131 | } |
1129 | 1132 | ||
1130 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
1133 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
1131 | enum port port, int index) |
1134 | enum port port, int index) |
1132 | { |
1135 | { |
1133 | if (port == PORT_E) |
1136 | if (port == PORT_E) |
1134 | port = skl_porte_aux_port(dev_priv); |
1137 | port = skl_porte_aux_port(dev_priv); |
1135 | 1138 | ||
1136 | switch (port) { |
1139 | switch (port) { |
1137 | case PORT_A: |
1140 | case PORT_A: |
1138 | case PORT_B: |
1141 | case PORT_B: |
1139 | case PORT_C: |
1142 | case PORT_C: |
1140 | case PORT_D: |
1143 | case PORT_D: |
1141 | return DP_AUX_CH_DATA(port, index); |
1144 | return DP_AUX_CH_DATA(port, index); |
1142 | default: |
1145 | default: |
1143 | MISSING_CASE(port); |
1146 | MISSING_CASE(port); |
1144 | return DP_AUX_CH_DATA(PORT_A, index); |
1147 | return DP_AUX_CH_DATA(PORT_A, index); |
1145 | } |
1148 | } |
1146 | } |
1149 | } |
1147 | 1150 | ||
1148 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1151 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1149 | enum port port) |
1152 | enum port port) |
1150 | { |
1153 | { |
1151 | if (INTEL_INFO(dev_priv)->gen >= 9) |
1154 | if (INTEL_INFO(dev_priv)->gen >= 9) |
1152 | return skl_aux_ctl_reg(dev_priv, port); |
1155 | return skl_aux_ctl_reg(dev_priv, port); |
1153 | else if (HAS_PCH_SPLIT(dev_priv)) |
1156 | else if (HAS_PCH_SPLIT(dev_priv)) |
1154 | return ilk_aux_ctl_reg(dev_priv, port); |
1157 | return ilk_aux_ctl_reg(dev_priv, port); |
1155 | else |
1158 | else |
1156 | return g4x_aux_ctl_reg(dev_priv, port); |
1159 | return g4x_aux_ctl_reg(dev_priv, port); |
1157 | } |
1160 | } |
1158 | 1161 | ||
1159 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
1162 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
1160 | enum port port, int index) |
1163 | enum port port, int index) |
1161 | { |
1164 | { |
1162 | if (INTEL_INFO(dev_priv)->gen >= 9) |
1165 | if (INTEL_INFO(dev_priv)->gen >= 9) |
1163 | return skl_aux_data_reg(dev_priv, port, index); |
1166 | return skl_aux_data_reg(dev_priv, port, index); |
1164 | else if (HAS_PCH_SPLIT(dev_priv)) |
1167 | else if (HAS_PCH_SPLIT(dev_priv)) |
1165 | return ilk_aux_data_reg(dev_priv, port, index); |
1168 | return ilk_aux_data_reg(dev_priv, port, index); |
1166 | else |
1169 | else |
1167 | return g4x_aux_data_reg(dev_priv, port, index); |
1170 | return g4x_aux_data_reg(dev_priv, port, index); |
1168 | } |
1171 | } |
1169 | 1172 | ||
1170 | static void intel_aux_reg_init(struct intel_dp *intel_dp) |
1173 | static void intel_aux_reg_init(struct intel_dp *intel_dp) |
1171 | { |
1174 | { |
1172 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
1175 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
1173 | enum port port = dp_to_dig_port(intel_dp)->port; |
1176 | enum port port = dp_to_dig_port(intel_dp)->port; |
1174 | int i; |
1177 | int i; |
1175 | 1178 | ||
1176 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); |
1179 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); |
1177 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) |
1180 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) |
1178 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); |
1181 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); |
1179 | } |
1182 | } |
1180 | 1183 | ||
1181 | static void |
1184 | static void |
1182 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1185 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1183 | { |
1186 | { |
1184 | drm_dp_aux_unregister(&intel_dp->aux); |
1187 | drm_dp_aux_unregister(&intel_dp->aux); |
1185 | kfree(intel_dp->aux.name); |
1188 | kfree(intel_dp->aux.name); |
1186 | } |
1189 | } |
1187 | 1190 | ||
1188 | static int |
1191 | static int |
1189 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
1192 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
1190 | { |
1193 | { |
1191 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
- | |
1192 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1194 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1193 | enum port port = intel_dig_port->port; |
1195 | enum port port = intel_dig_port->port; |
1194 | int ret; |
1196 | int ret; |
1195 | 1197 | ||
1196 | intel_aux_reg_init(intel_dp); |
1198 | intel_aux_reg_init(intel_dp); |
1197 | 1199 | ||
1198 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
1200 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
1199 | if (!intel_dp->aux.name) |
1201 | if (!intel_dp->aux.name) |
1200 | return -ENOMEM; |
1202 | return -ENOMEM; |
1201 | 1203 | ||
1202 | intel_dp->aux.dev = dev->dev; |
1204 | intel_dp->aux.dev = connector->base.kdev; |
1203 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
- | |
1204 | - | ||
1205 | DRM_DEBUG_KMS("registering %s bus for %s\n", |
- | |
1206 | intel_dp->aux.name, |
- | |
1207 | connector->base.kdev->kobj.name); |
1205 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
1208 | 1206 | ||
1209 | ret = drm_dp_aux_register(&intel_dp->aux); |
1207 | ret = drm_dp_aux_register(&intel_dp->aux); |
1210 | if (ret < 0) { |
1208 | if (ret < 0) { |
1211 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
1209 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
1212 | intel_dp->aux.name, ret); |
1210 | intel_dp->aux.name, ret); |
1213 | kfree(intel_dp->aux.name); |
1211 | kfree(intel_dp->aux.name); |
1214 | return ret; |
1212 | return ret; |
1215 | } |
1213 | } |
1216 | - | ||
1217 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
- | |
1218 | &intel_dp->aux.ddc.dev.kobj, |
- | |
1219 | intel_dp->aux.ddc.dev.kobj.name); |
- | |
1220 | if (ret < 0) { |
- | |
1221 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", |
- | |
1222 | intel_dp->aux.name, ret); |
- | |
1223 | intel_dp_aux_fini(intel_dp); |
- | |
1224 | return ret; |
- | |
1225 | } |
- | |
1226 | 1214 | ||
1227 | return 0; |
1215 | return 0; |
1228 | } |
1216 | } |
1229 | 1217 | ||
1230 | static void |
1218 | static void |
1231 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
1219 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
1232 | { |
1220 | { |
1233 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
1221 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
1234 | - | ||
1235 | if (!intel_connector->mst_port) |
- | |
1236 | sysfs_remove_link(&intel_connector->base.kdev->kobj, |
1222 | |
1237 | intel_dp->aux.ddc.dev.kobj.name); |
1223 | intel_dp_aux_fini(intel_dp); |
1238 | intel_connector_unregister(intel_connector); |
1224 | intel_connector_unregister(intel_connector); |
1239 | } |
1225 | } |
1240 | 1226 | ||
1241 | static void |
1227 | static void |
1242 | skl_edp_set_pll_config(struct intel_crtc_state *pipe_config) |
1228 | skl_edp_set_pll_config(struct intel_crtc_state *pipe_config) |
1243 | { |
1229 | { |
1244 | u32 ctrl1; |
1230 | u32 ctrl1; |
1245 | 1231 | ||
1246 | memset(&pipe_config->dpll_hw_state, 0, |
1232 | memset(&pipe_config->dpll_hw_state, 0, |
1247 | sizeof(pipe_config->dpll_hw_state)); |
1233 | sizeof(pipe_config->dpll_hw_state)); |
1248 | 1234 | ||
1249 | pipe_config->ddi_pll_sel = SKL_DPLL0; |
1235 | pipe_config->ddi_pll_sel = SKL_DPLL0; |
1250 | pipe_config->dpll_hw_state.cfgcr1 = 0; |
1236 | pipe_config->dpll_hw_state.cfgcr1 = 0; |
1251 | pipe_config->dpll_hw_state.cfgcr2 = 0; |
1237 | pipe_config->dpll_hw_state.cfgcr2 = 0; |
1252 | 1238 | ||
1253 | ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
1239 | ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
1254 | switch (pipe_config->port_clock / 2) { |
1240 | switch (pipe_config->port_clock / 2) { |
1255 | case 81000: |
1241 | case 81000: |
1256 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
1242 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
1257 | SKL_DPLL0); |
1243 | SKL_DPLL0); |
1258 | break; |
1244 | break; |
1259 | case 135000: |
1245 | case 135000: |
1260 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, |
1246 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, |
1261 | SKL_DPLL0); |
1247 | SKL_DPLL0); |
1262 | break; |
1248 | break; |
1263 | case 270000: |
1249 | case 270000: |
1264 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, |
1250 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, |
1265 | SKL_DPLL0); |
1251 | SKL_DPLL0); |
1266 | break; |
1252 | break; |
1267 | case 162000: |
1253 | case 162000: |
1268 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, |
1254 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, |
1269 | SKL_DPLL0); |
1255 | SKL_DPLL0); |
1270 | break; |
1256 | break; |
1271 | /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which |
1257 | /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which |
1272 | results in CDCLK change. Need to handle the change of CDCLK by |
1258 | results in CDCLK change. Need to handle the change of CDCLK by |
1273 | disabling pipes and re-enabling them */ |
1259 | disabling pipes and re-enabling them */ |
1274 | case 108000: |
1260 | case 108000: |
1275 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
1261 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
1276 | SKL_DPLL0); |
1262 | SKL_DPLL0); |
1277 | break; |
1263 | break; |
1278 | case 216000: |
1264 | case 216000: |
1279 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, |
1265 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, |
1280 | SKL_DPLL0); |
1266 | SKL_DPLL0); |
1281 | break; |
1267 | break; |
1282 | 1268 | ||
1283 | } |
1269 | } |
1284 | pipe_config->dpll_hw_state.ctrl1 = ctrl1; |
1270 | pipe_config->dpll_hw_state.ctrl1 = ctrl1; |
1285 | } |
1271 | } |
1286 | 1272 | ||
1287 | void |
1273 | void |
1288 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config) |
1274 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config) |
1289 | { |
1275 | { |
1290 | memset(&pipe_config->dpll_hw_state, 0, |
1276 | memset(&pipe_config->dpll_hw_state, 0, |
1291 | sizeof(pipe_config->dpll_hw_state)); |
1277 | sizeof(pipe_config->dpll_hw_state)); |
1292 | 1278 | ||
1293 | switch (pipe_config->port_clock / 2) { |
1279 | switch (pipe_config->port_clock / 2) { |
1294 | case 81000: |
1280 | case 81000: |
1295 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
1281 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
1296 | break; |
1282 | break; |
1297 | case 135000: |
1283 | case 135000: |
1298 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
1284 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
1299 | break; |
1285 | break; |
1300 | case 270000: |
1286 | case 270000: |
1301 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
1287 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
1302 | break; |
1288 | break; |
1303 | } |
1289 | } |
1304 | } |
1290 | } |
1305 | 1291 | ||
1306 | static int |
1292 | static int |
1307 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
1293 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
1308 | { |
1294 | { |
1309 | if (intel_dp->num_sink_rates) { |
1295 | if (intel_dp->num_sink_rates) { |
1310 | *sink_rates = intel_dp->sink_rates; |
1296 | *sink_rates = intel_dp->sink_rates; |
1311 | return intel_dp->num_sink_rates; |
1297 | return intel_dp->num_sink_rates; |
1312 | } |
1298 | } |
1313 | 1299 | ||
1314 | *sink_rates = default_rates; |
1300 | *sink_rates = default_rates; |
1315 | 1301 | ||
1316 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; |
1302 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; |
1317 | } |
1303 | } |
1318 | 1304 | ||
1319 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
1305 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
1320 | { |
1306 | { |
1321 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1307 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1322 | struct drm_device *dev = dig_port->base.base.dev; |
1308 | struct drm_device *dev = dig_port->base.base.dev; |
1323 | 1309 | ||
1324 | /* WaDisableHBR2:skl */ |
1310 | /* WaDisableHBR2:skl */ |
1325 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
1311 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
1326 | return false; |
1312 | return false; |
1327 | 1313 | ||
1328 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || |
1314 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || |
1329 | (INTEL_INFO(dev)->gen >= 9)) |
1315 | (INTEL_INFO(dev)->gen >= 9)) |
1330 | return true; |
1316 | return true; |
1331 | else |
1317 | else |
1332 | return false; |
1318 | return false; |
1333 | } |
1319 | } |
1334 | 1320 | ||
1335 | static int |
1321 | static int |
1336 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
1322 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
1337 | { |
1323 | { |
1338 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1324 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1339 | struct drm_device *dev = dig_port->base.base.dev; |
1325 | struct drm_device *dev = dig_port->base.base.dev; |
1340 | int size; |
1326 | int size; |
1341 | 1327 | ||
1342 | if (IS_BROXTON(dev)) { |
1328 | if (IS_BROXTON(dev)) { |
1343 | *source_rates = bxt_rates; |
1329 | *source_rates = bxt_rates; |
1344 | size = ARRAY_SIZE(bxt_rates); |
1330 | size = ARRAY_SIZE(bxt_rates); |
1345 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
1331 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
1346 | *source_rates = skl_rates; |
1332 | *source_rates = skl_rates; |
1347 | size = ARRAY_SIZE(skl_rates); |
1333 | size = ARRAY_SIZE(skl_rates); |
1348 | } else { |
1334 | } else { |
1349 | *source_rates = default_rates; |
1335 | *source_rates = default_rates; |
1350 | size = ARRAY_SIZE(default_rates); |
1336 | size = ARRAY_SIZE(default_rates); |
1351 | } |
1337 | } |
1352 | 1338 | ||
1353 | /* This depends on the fact that 5.4 is last value in the array */ |
1339 | /* This depends on the fact that 5.4 is last value in the array */ |
1354 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
1340 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
1355 | size--; |
1341 | size--; |
1356 | 1342 | ||
1357 | return size; |
1343 | return size; |
1358 | } |
1344 | } |
1359 | 1345 | ||
1360 | static void |
1346 | static void |
1361 | intel_dp_set_clock(struct intel_encoder *encoder, |
1347 | intel_dp_set_clock(struct intel_encoder *encoder, |
1362 | struct intel_crtc_state *pipe_config) |
1348 | struct intel_crtc_state *pipe_config) |
1363 | { |
1349 | { |
1364 | struct drm_device *dev = encoder->base.dev; |
1350 | struct drm_device *dev = encoder->base.dev; |
1365 | const struct dp_link_dpll *divisor = NULL; |
1351 | const struct dp_link_dpll *divisor = NULL; |
1366 | int i, count = 0; |
1352 | int i, count = 0; |
1367 | 1353 | ||
1368 | if (IS_G4X(dev)) { |
1354 | if (IS_G4X(dev)) { |
1369 | divisor = gen4_dpll; |
1355 | divisor = gen4_dpll; |
1370 | count = ARRAY_SIZE(gen4_dpll); |
1356 | count = ARRAY_SIZE(gen4_dpll); |
1371 | } else if (HAS_PCH_SPLIT(dev)) { |
1357 | } else if (HAS_PCH_SPLIT(dev)) { |
1372 | divisor = pch_dpll; |
1358 | divisor = pch_dpll; |
1373 | count = ARRAY_SIZE(pch_dpll); |
1359 | count = ARRAY_SIZE(pch_dpll); |
1374 | } else if (IS_CHERRYVIEW(dev)) { |
1360 | } else if (IS_CHERRYVIEW(dev)) { |
1375 | divisor = chv_dpll; |
1361 | divisor = chv_dpll; |
1376 | count = ARRAY_SIZE(chv_dpll); |
1362 | count = ARRAY_SIZE(chv_dpll); |
1377 | } else if (IS_VALLEYVIEW(dev)) { |
1363 | } else if (IS_VALLEYVIEW(dev)) { |
1378 | divisor = vlv_dpll; |
1364 | divisor = vlv_dpll; |
1379 | count = ARRAY_SIZE(vlv_dpll); |
1365 | count = ARRAY_SIZE(vlv_dpll); |
1380 | } |
1366 | } |
1381 | 1367 | ||
1382 | if (divisor && count) { |
1368 | if (divisor && count) { |
1383 | for (i = 0; i < count; i++) { |
1369 | for (i = 0; i < count; i++) { |
1384 | if (pipe_config->port_clock == divisor[i].clock) { |
1370 | if (pipe_config->port_clock == divisor[i].clock) { |
1385 | pipe_config->dpll = divisor[i].dpll; |
1371 | pipe_config->dpll = divisor[i].dpll; |
1386 | pipe_config->clock_set = true; |
1372 | pipe_config->clock_set = true; |
1387 | break; |
1373 | break; |
1388 | } |
1374 | } |
1389 | } |
1375 | } |
1390 | } |
1376 | } |
1391 | } |
1377 | } |
1392 | 1378 | ||
1393 | static int intersect_rates(const int *source_rates, int source_len, |
1379 | static int intersect_rates(const int *source_rates, int source_len, |
1394 | const int *sink_rates, int sink_len, |
1380 | const int *sink_rates, int sink_len, |
1395 | int *common_rates) |
1381 | int *common_rates) |
1396 | { |
1382 | { |
1397 | int i = 0, j = 0, k = 0; |
1383 | int i = 0, j = 0, k = 0; |
1398 | 1384 | ||
1399 | while (i < source_len && j < sink_len) { |
1385 | while (i < source_len && j < sink_len) { |
1400 | if (source_rates[i] == sink_rates[j]) { |
1386 | if (source_rates[i] == sink_rates[j]) { |
1401 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
1387 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
1402 | return k; |
1388 | return k; |
1403 | common_rates[k] = source_rates[i]; |
1389 | common_rates[k] = source_rates[i]; |
1404 | ++k; |
1390 | ++k; |
1405 | ++i; |
1391 | ++i; |
1406 | ++j; |
1392 | ++j; |
1407 | } else if (source_rates[i] < sink_rates[j]) { |
1393 | } else if (source_rates[i] < sink_rates[j]) { |
1408 | ++i; |
1394 | ++i; |
1409 | } else { |
1395 | } else { |
1410 | ++j; |
1396 | ++j; |
1411 | } |
1397 | } |
1412 | } |
1398 | } |
1413 | return k; |
1399 | return k; |
1414 | } |
1400 | } |
1415 | 1401 | ||
1416 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
1402 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
1417 | int *common_rates) |
1403 | int *common_rates) |
1418 | { |
1404 | { |
1419 | const int *source_rates, *sink_rates; |
1405 | const int *source_rates, *sink_rates; |
1420 | int source_len, sink_len; |
1406 | int source_len, sink_len; |
1421 | 1407 | ||
1422 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1408 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1423 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
1409 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
1424 | 1410 | ||
1425 | return intersect_rates(source_rates, source_len, |
1411 | return intersect_rates(source_rates, source_len, |
1426 | sink_rates, sink_len, |
1412 | sink_rates, sink_len, |
1427 | common_rates); |
1413 | common_rates); |
1428 | } |
1414 | } |
1429 | 1415 | ||
1430 | static void snprintf_int_array(char *str, size_t len, |
1416 | static void snprintf_int_array(char *str, size_t len, |
1431 | const int *array, int nelem) |
1417 | const int *array, int nelem) |
1432 | { |
1418 | { |
1433 | int i; |
1419 | int i; |
1434 | 1420 | ||
1435 | str[0] = '\0'; |
1421 | str[0] = '\0'; |
1436 | 1422 | ||
1437 | for (i = 0; i < nelem; i++) { |
1423 | for (i = 0; i < nelem; i++) { |
1438 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
1424 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
1439 | if (r >= len) |
1425 | if (r >= len) |
1440 | return; |
1426 | return; |
1441 | str += r; |
1427 | str += r; |
1442 | len -= r; |
1428 | len -= r; |
1443 | } |
1429 | } |
1444 | } |
1430 | } |
1445 | 1431 | ||
1446 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
1432 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
1447 | { |
1433 | { |
1448 | const int *source_rates, *sink_rates; |
1434 | const int *source_rates, *sink_rates; |
1449 | int source_len, sink_len, common_len; |
1435 | int source_len, sink_len, common_len; |
1450 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
1436 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
1451 | char str[128]; /* FIXME: too big for stack? */ |
1437 | char str[128]; /* FIXME: too big for stack? */ |
1452 | 1438 | ||
1453 | if ((drm_debug & DRM_UT_KMS) == 0) |
1439 | if ((drm_debug & DRM_UT_KMS) == 0) |
1454 | return; |
1440 | return; |
1455 | 1441 | ||
1456 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
1442 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
1457 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1443 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1458 | DRM_DEBUG_KMS("source rates: %s\n", str); |
1444 | DRM_DEBUG_KMS("source rates: %s\n", str); |
1459 | 1445 | ||
1460 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1446 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1461 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); |
1447 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); |
1462 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
1448 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
1463 | 1449 | ||
1464 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1450 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1465 | snprintf_int_array(str, sizeof(str), common_rates, common_len); |
1451 | snprintf_int_array(str, sizeof(str), common_rates, common_len); |
1466 | DRM_DEBUG_KMS("common rates: %s\n", str); |
1452 | DRM_DEBUG_KMS("common rates: %s\n", str); |
1467 | } |
1453 | } |
1468 | 1454 | ||
1469 | static int rate_to_index(int find, const int *rates) |
1455 | static int rate_to_index(int find, const int *rates) |
1470 | { |
1456 | { |
1471 | int i = 0; |
1457 | int i = 0; |
1472 | 1458 | ||
1473 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) |
1459 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) |
1474 | if (find == rates[i]) |
1460 | if (find == rates[i]) |
1475 | break; |
1461 | break; |
1476 | 1462 | ||
1477 | return i; |
1463 | return i; |
1478 | } |
1464 | } |
1479 | 1465 | ||
1480 | int |
1466 | int |
1481 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
1467 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
1482 | { |
1468 | { |
1483 | int rates[DP_MAX_SUPPORTED_RATES] = {}; |
1469 | int rates[DP_MAX_SUPPORTED_RATES] = {}; |
1484 | int len; |
1470 | int len; |
1485 | 1471 | ||
1486 | len = intel_dp_common_rates(intel_dp, rates); |
1472 | len = intel_dp_common_rates(intel_dp, rates); |
1487 | if (WARN_ON(len <= 0)) |
1473 | if (WARN_ON(len <= 0)) |
1488 | return 162000; |
1474 | return 162000; |
1489 | 1475 | ||
1490 | return rates[rate_to_index(0, rates) - 1]; |
1476 | return rates[rate_to_index(0, rates) - 1]; |
1491 | } |
1477 | } |
1492 | 1478 | ||
1493 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1479 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1494 | { |
1480 | { |
1495 | return rate_to_index(rate, intel_dp->sink_rates); |
1481 | return rate_to_index(rate, intel_dp->sink_rates); |
1496 | } |
1482 | } |
1497 | 1483 | ||
1498 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1484 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1499 | uint8_t *link_bw, uint8_t *rate_select) |
1485 | uint8_t *link_bw, uint8_t *rate_select) |
1500 | { |
1486 | { |
1501 | if (intel_dp->num_sink_rates) { |
1487 | if (intel_dp->num_sink_rates) { |
1502 | *link_bw = 0; |
1488 | *link_bw = 0; |
1503 | *rate_select = |
1489 | *rate_select = |
1504 | intel_dp_rate_select(intel_dp, port_clock); |
1490 | intel_dp_rate_select(intel_dp, port_clock); |
1505 | } else { |
1491 | } else { |
1506 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
1492 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
1507 | *rate_select = 0; |
1493 | *rate_select = 0; |
1508 | } |
1494 | } |
1509 | } |
1495 | } |
1510 | 1496 | ||
1511 | bool |
1497 | bool |
1512 | intel_dp_compute_config(struct intel_encoder *encoder, |
1498 | intel_dp_compute_config(struct intel_encoder *encoder, |
1513 | struct intel_crtc_state *pipe_config) |
1499 | struct intel_crtc_state *pipe_config) |
1514 | { |
1500 | { |
1515 | struct drm_device *dev = encoder->base.dev; |
1501 | struct drm_device *dev = encoder->base.dev; |
1516 | struct drm_i915_private *dev_priv = dev->dev_private; |
1502 | struct drm_i915_private *dev_priv = dev->dev_private; |
1517 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1503 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1518 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1504 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1519 | enum port port = dp_to_dig_port(intel_dp)->port; |
1505 | enum port port = dp_to_dig_port(intel_dp)->port; |
1520 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
1506 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
1521 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
1507 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
1522 | int lane_count, clock; |
1508 | int lane_count, clock; |
1523 | int min_lane_count = 1; |
1509 | int min_lane_count = 1; |
1524 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
1510 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
1525 | /* Conveniently, the link BW constants become indices with a shift...*/ |
1511 | /* Conveniently, the link BW constants become indices with a shift...*/ |
1526 | int min_clock = 0; |
1512 | int min_clock = 0; |
1527 | int max_clock; |
1513 | int max_clock; |
1528 | int bpp, mode_rate; |
1514 | int bpp, mode_rate; |
1529 | int link_avail, link_clock; |
1515 | int link_avail, link_clock; |
1530 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1516 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1531 | int common_len; |
1517 | int common_len; |
1532 | uint8_t link_bw, rate_select; |
1518 | uint8_t link_bw, rate_select; |
1533 | 1519 | ||
1534 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1520 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1535 | 1521 | ||
1536 | /* No common link rates between source and sink */ |
1522 | /* No common link rates between source and sink */ |
1537 | WARN_ON(common_len <= 0); |
1523 | WARN_ON(common_len <= 0); |
1538 | 1524 | ||
1539 | max_clock = common_len - 1; |
1525 | max_clock = common_len - 1; |
1540 | 1526 | ||
1541 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
1527 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
1542 | pipe_config->has_pch_encoder = true; |
1528 | pipe_config->has_pch_encoder = true; |
1543 | 1529 | ||
1544 | pipe_config->has_dp_encoder = true; |
1530 | pipe_config->has_dp_encoder = true; |
1545 | pipe_config->has_drrs = false; |
1531 | pipe_config->has_drrs = false; |
1546 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
1532 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
1547 | 1533 | ||
1548 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1534 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1549 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
1535 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
1550 | adjusted_mode); |
1536 | adjusted_mode); |
1551 | 1537 | ||
1552 | if (INTEL_INFO(dev)->gen >= 9) { |
1538 | if (INTEL_INFO(dev)->gen >= 9) { |
1553 | int ret; |
1539 | int ret; |
1554 | ret = skl_update_scaler_crtc(pipe_config); |
1540 | ret = skl_update_scaler_crtc(pipe_config); |
1555 | if (ret) |
1541 | if (ret) |
1556 | return ret; |
1542 | return ret; |
1557 | } |
1543 | } |
1558 | 1544 | ||
1559 | if (HAS_GMCH_DISPLAY(dev)) |
1545 | if (HAS_GMCH_DISPLAY(dev)) |
1560 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1546 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1561 | intel_connector->panel.fitting_mode); |
1547 | intel_connector->panel.fitting_mode); |
1562 | else |
1548 | else |
1563 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1549 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1564 | intel_connector->panel.fitting_mode); |
1550 | intel_connector->panel.fitting_mode); |
1565 | } |
1551 | } |
1566 | 1552 | ||
1567 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
1553 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
1568 | return false; |
1554 | return false; |
1569 | 1555 | ||
1570 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
1556 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
1571 | "max bw %d pixel clock %iKHz\n", |
1557 | "max bw %d pixel clock %iKHz\n", |
1572 | max_lane_count, common_rates[max_clock], |
1558 | max_lane_count, common_rates[max_clock], |
1573 | adjusted_mode->crtc_clock); |
1559 | adjusted_mode->crtc_clock); |
1574 | 1560 | ||
1575 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1561 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1576 | * bpc in between. */ |
1562 | * bpc in between. */ |
1577 | bpp = pipe_config->pipe_bpp; |
1563 | bpp = pipe_config->pipe_bpp; |
1578 | if (is_edp(intel_dp)) { |
1564 | if (is_edp(intel_dp)) { |
1579 | 1565 | ||
1580 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
1566 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
1581 | if (intel_connector->base.display_info.bpc == 0 && |
1567 | if (intel_connector->base.display_info.bpc == 0 && |
1582 | (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) { |
1568 | (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) { |
1583 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
1569 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
1584 | dev_priv->vbt.edp_bpp); |
1570 | dev_priv->vbt.edp_bpp); |
1585 | bpp = dev_priv->vbt.edp_bpp; |
1571 | bpp = dev_priv->vbt.edp_bpp; |
1586 | } |
1572 | } |
1587 | 1573 | ||
1588 | /* |
1574 | /* |
1589 | * Use the maximum clock and number of lanes the eDP panel |
1575 | * Use the maximum clock and number of lanes the eDP panel |
1590 | * advertizes being capable of. The panels are generally |
1576 | * advertizes being capable of. The panels are generally |
1591 | * designed to support only a single clock and lane |
1577 | * designed to support only a single clock and lane |
1592 | * configuration, and typically these values correspond to the |
1578 | * configuration, and typically these values correspond to the |
1593 | * native resolution of the panel. |
1579 | * native resolution of the panel. |
1594 | */ |
1580 | */ |
1595 | min_lane_count = max_lane_count; |
1581 | min_lane_count = max_lane_count; |
1596 | min_clock = max_clock; |
1582 | min_clock = max_clock; |
1597 | } |
1583 | } |
1598 | 1584 | ||
1599 | for (; bpp >= 6*3; bpp -= 2*3) { |
1585 | for (; bpp >= 6*3; bpp -= 2*3) { |
1600 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1586 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1601 | bpp); |
1587 | bpp); |
1602 | 1588 | ||
1603 | for (clock = min_clock; clock <= max_clock; clock++) { |
1589 | for (clock = min_clock; clock <= max_clock; clock++) { |
1604 | for (lane_count = min_lane_count; |
1590 | for (lane_count = min_lane_count; |
1605 | lane_count <= max_lane_count; |
1591 | lane_count <= max_lane_count; |
1606 | lane_count <<= 1) { |
1592 | lane_count <<= 1) { |
1607 | 1593 | ||
1608 | link_clock = common_rates[clock]; |
1594 | link_clock = common_rates[clock]; |
1609 | link_avail = intel_dp_max_data_rate(link_clock, |
1595 | link_avail = intel_dp_max_data_rate(link_clock, |
1610 | lane_count); |
1596 | lane_count); |
1611 | 1597 | ||
1612 | if (mode_rate <= link_avail) { |
1598 | if (mode_rate <= link_avail) { |
1613 | goto found; |
1599 | goto found; |
1614 | } |
1600 | } |
1615 | } |
1601 | } |
1616 | } |
1602 | } |
1617 | } |
1603 | } |
1618 | 1604 | ||
1619 | return false; |
1605 | return false; |
1620 | 1606 | ||
1621 | found: |
1607 | found: |
1622 | if (intel_dp->color_range_auto) { |
1608 | if (intel_dp->color_range_auto) { |
1623 | /* |
1609 | /* |
1624 | * See: |
1610 | * See: |
1625 | * CEA-861-E - 5.1 Default Encoding Parameters |
1611 | * CEA-861-E - 5.1 Default Encoding Parameters |
1626 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
1612 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
1627 | */ |
1613 | */ |
1628 | pipe_config->limited_color_range = |
1614 | pipe_config->limited_color_range = |
1629 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; |
1615 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; |
1630 | } else { |
1616 | } else { |
1631 | pipe_config->limited_color_range = |
1617 | pipe_config->limited_color_range = |
1632 | intel_dp->limited_color_range; |
1618 | intel_dp->limited_color_range; |
1633 | } |
1619 | } |
1634 | 1620 | ||
1635 | pipe_config->lane_count = lane_count; |
1621 | pipe_config->lane_count = lane_count; |
1636 | 1622 | ||
1637 | pipe_config->pipe_bpp = bpp; |
1623 | pipe_config->pipe_bpp = bpp; |
1638 | pipe_config->port_clock = common_rates[clock]; |
1624 | pipe_config->port_clock = common_rates[clock]; |
1639 | 1625 | ||
1640 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1626 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1641 | &link_bw, &rate_select); |
1627 | &link_bw, &rate_select); |
1642 | 1628 | ||
1643 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", |
1629 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", |
1644 | link_bw, rate_select, pipe_config->lane_count, |
1630 | link_bw, rate_select, pipe_config->lane_count, |
1645 | pipe_config->port_clock, bpp); |
1631 | pipe_config->port_clock, bpp); |
1646 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1632 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1647 | mode_rate, link_avail); |
1633 | mode_rate, link_avail); |
1648 | 1634 | ||
1649 | intel_link_compute_m_n(bpp, lane_count, |
1635 | intel_link_compute_m_n(bpp, lane_count, |
1650 | adjusted_mode->crtc_clock, |
1636 | adjusted_mode->crtc_clock, |
1651 | pipe_config->port_clock, |
1637 | pipe_config->port_clock, |
1652 | &pipe_config->dp_m_n); |
1638 | &pipe_config->dp_m_n); |
1653 | 1639 | ||
1654 | if (intel_connector->panel.downclock_mode != NULL && |
1640 | if (intel_connector->panel.downclock_mode != NULL && |
1655 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
1641 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
1656 | pipe_config->has_drrs = true; |
1642 | pipe_config->has_drrs = true; |
1657 | intel_link_compute_m_n(bpp, lane_count, |
1643 | intel_link_compute_m_n(bpp, lane_count, |
1658 | intel_connector->panel.downclock_mode->clock, |
1644 | intel_connector->panel.downclock_mode->clock, |
1659 | pipe_config->port_clock, |
1645 | pipe_config->port_clock, |
1660 | &pipe_config->dp_m2_n2); |
1646 | &pipe_config->dp_m2_n2); |
1661 | } |
1647 | } |
1662 | 1648 | ||
1663 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp)) |
1649 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp)) |
1664 | skl_edp_set_pll_config(pipe_config); |
1650 | skl_edp_set_pll_config(pipe_config); |
1665 | else if (IS_BROXTON(dev)) |
1651 | else if (IS_BROXTON(dev)) |
1666 | /* handled in ddi */; |
1652 | /* handled in ddi */; |
1667 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1653 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1668 | hsw_dp_set_ddi_pll_sel(pipe_config); |
1654 | hsw_dp_set_ddi_pll_sel(pipe_config); |
1669 | else |
1655 | else |
1670 | intel_dp_set_clock(encoder, pipe_config); |
1656 | intel_dp_set_clock(encoder, pipe_config); |
1671 | 1657 | ||
1672 | return true; |
1658 | return true; |
1673 | } |
1659 | } |
1674 | 1660 | ||
1675 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1661 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1676 | const struct intel_crtc_state *pipe_config) |
1662 | const struct intel_crtc_state *pipe_config) |
1677 | { |
1663 | { |
1678 | intel_dp->link_rate = pipe_config->port_clock; |
1664 | intel_dp->link_rate = pipe_config->port_clock; |
1679 | intel_dp->lane_count = pipe_config->lane_count; |
1665 | intel_dp->lane_count = pipe_config->lane_count; |
1680 | } |
1666 | } |
1681 | 1667 | ||
1682 | static void intel_dp_prepare(struct intel_encoder *encoder) |
1668 | static void intel_dp_prepare(struct intel_encoder *encoder) |
1683 | { |
1669 | { |
1684 | struct drm_device *dev = encoder->base.dev; |
1670 | struct drm_device *dev = encoder->base.dev; |
1685 | struct drm_i915_private *dev_priv = dev->dev_private; |
1671 | struct drm_i915_private *dev_priv = dev->dev_private; |
1686 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1672 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1687 | enum port port = dp_to_dig_port(intel_dp)->port; |
1673 | enum port port = dp_to_dig_port(intel_dp)->port; |
1688 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1674 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1689 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
1675 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
1690 | 1676 | ||
1691 | intel_dp_set_link_params(intel_dp, crtc->config); |
1677 | intel_dp_set_link_params(intel_dp, crtc->config); |
1692 | 1678 | ||
1693 | /* |
1679 | /* |
1694 | * There are four kinds of DP registers: |
1680 | * There are four kinds of DP registers: |
1695 | * |
1681 | * |
1696 | * IBX PCH |
1682 | * IBX PCH |
1697 | * SNB CPU |
1683 | * SNB CPU |
1698 | * IVB CPU |
1684 | * IVB CPU |
1699 | * CPT PCH |
1685 | * CPT PCH |
1700 | * |
1686 | * |
1701 | * IBX PCH and CPU are the same for almost everything, |
1687 | * IBX PCH and CPU are the same for almost everything, |
1702 | * except that the CPU DP PLL is configured in this |
1688 | * except that the CPU DP PLL is configured in this |
1703 | * register |
1689 | * register |
1704 | * |
1690 | * |
1705 | * CPT PCH is quite different, having many bits moved |
1691 | * CPT PCH is quite different, having many bits moved |
1706 | * to the TRANS_DP_CTL register instead. That |
1692 | * to the TRANS_DP_CTL register instead. That |
1707 | * configuration happens (oddly) in ironlake_pch_enable |
1693 | * configuration happens (oddly) in ironlake_pch_enable |
1708 | */ |
1694 | */ |
1709 | 1695 | ||
1710 | /* Preserve the BIOS-computed detected bit. This is |
1696 | /* Preserve the BIOS-computed detected bit. This is |
1711 | * supposed to be read-only. |
1697 | * supposed to be read-only. |
1712 | */ |
1698 | */ |
1713 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
1699 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
1714 | 1700 | ||
1715 | /* Handle DP bits in common between all three register formats */ |
1701 | /* Handle DP bits in common between all three register formats */ |
1716 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
1702 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
1717 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
1703 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
1718 | 1704 | ||
1719 | /* Split out the IBX/CPU vs CPT settings */ |
1705 | /* Split out the IBX/CPU vs CPT settings */ |
1720 | 1706 | ||
1721 | if (IS_GEN7(dev) && port == PORT_A) { |
1707 | if (IS_GEN7(dev) && port == PORT_A) { |
1722 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1708 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1723 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1709 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1724 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1710 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1725 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1711 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1726 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1712 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1727 | 1713 | ||
1728 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1714 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1729 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1715 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1730 | 1716 | ||
1731 | intel_dp->DP |= crtc->pipe << 29; |
1717 | intel_dp->DP |= crtc->pipe << 29; |
1732 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
1718 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
1733 | u32 trans_dp; |
1719 | u32 trans_dp; |
1734 | 1720 | ||
1735 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1721 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1736 | 1722 | ||
1737 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
1723 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
1738 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1724 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1739 | trans_dp |= TRANS_DP_ENH_FRAMING; |
1725 | trans_dp |= TRANS_DP_ENH_FRAMING; |
1740 | else |
1726 | else |
1741 | trans_dp &= ~TRANS_DP_ENH_FRAMING; |
1727 | trans_dp &= ~TRANS_DP_ENH_FRAMING; |
1742 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
1728 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
1743 | } else { |
1729 | } else { |
1744 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
1730 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
1745 | !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) |
1731 | !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) |
1746 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
1732 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
1747 | 1733 | ||
1748 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1734 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1749 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1735 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1750 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1736 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1751 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1737 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1752 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
1738 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
1753 | 1739 | ||
1754 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1740 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1755 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1741 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1756 | 1742 | ||
1757 | if (IS_CHERRYVIEW(dev)) |
1743 | if (IS_CHERRYVIEW(dev)) |
1758 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
1744 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
1759 | else if (crtc->pipe == PIPE_B) |
1745 | else if (crtc->pipe == PIPE_B) |
1760 | intel_dp->DP |= DP_PIPEB_SELECT; |
1746 | intel_dp->DP |= DP_PIPEB_SELECT; |
1761 | } |
1747 | } |
1762 | } |
1748 | } |
1763 | 1749 | ||
1764 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1750 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1765 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
1751 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
1766 | 1752 | ||
1767 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1753 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1768 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
1754 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
1769 | 1755 | ||
1770 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1756 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1771 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1757 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1772 | 1758 | ||
1773 | static void wait_panel_status(struct intel_dp *intel_dp, |
1759 | static void wait_panel_status(struct intel_dp *intel_dp, |
1774 | u32 mask, |
1760 | u32 mask, |
1775 | u32 value) |
1761 | u32 value) |
1776 | { |
1762 | { |
1777 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1763 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1778 | struct drm_i915_private *dev_priv = dev->dev_private; |
1764 | struct drm_i915_private *dev_priv = dev->dev_private; |
1779 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
1765 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
1780 | 1766 | ||
1781 | lockdep_assert_held(&dev_priv->pps_mutex); |
1767 | lockdep_assert_held(&dev_priv->pps_mutex); |
1782 | 1768 | ||
1783 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1769 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1784 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1770 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1785 | 1771 | ||
1786 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
1772 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
1787 | mask, value, |
1773 | mask, value, |
1788 | I915_READ(pp_stat_reg), |
1774 | I915_READ(pp_stat_reg), |
1789 | I915_READ(pp_ctrl_reg)); |
1775 | I915_READ(pp_ctrl_reg)); |
1790 | 1776 | ||
1791 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
1777 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
1792 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
1778 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
1793 | I915_READ(pp_stat_reg), |
1779 | I915_READ(pp_stat_reg), |
1794 | I915_READ(pp_ctrl_reg)); |
1780 | I915_READ(pp_ctrl_reg)); |
1795 | } |
1781 | } |
1796 | 1782 | ||
1797 | DRM_DEBUG_KMS("Wait complete\n"); |
1783 | DRM_DEBUG_KMS("Wait complete\n"); |
1798 | } |
1784 | } |
1799 | 1785 | ||
1800 | static void wait_panel_on(struct intel_dp *intel_dp) |
1786 | static void wait_panel_on(struct intel_dp *intel_dp) |
1801 | { |
1787 | { |
1802 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
1788 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
1803 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
1789 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
1804 | } |
1790 | } |
1805 | 1791 | ||
1806 | static void wait_panel_off(struct intel_dp *intel_dp) |
1792 | static void wait_panel_off(struct intel_dp *intel_dp) |
1807 | { |
1793 | { |
1808 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
1794 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
1809 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
1795 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
1810 | } |
1796 | } |
1811 | 1797 | ||
1812 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
1798 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
1813 | { |
1799 | { |
- | 1800 | ktime_t panel_power_on_time; |
|
- | 1801 | s64 panel_power_off_duration; |
|
- | 1802 | ||
1814 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
1803 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
- | 1804 | ||
- | 1805 | /* take the difference of currrent time and panel power off time |
|
- | 1806 | * and then make panel wait for t11_t12 if needed. */ |
|
- | 1807 | panel_power_on_time = ktime_get(); |
|
- | 1808 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); |
|
1815 | 1809 | ||
1816 | /* When we disable the VDD override bit last we have to do the manual |
1810 | /* When we disable the VDD override bit last we have to do the manual |
- | 1811 | * wait. */ |
|
1817 | * wait. */ |
1812 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
1818 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
1813 | wait_remaining_ms_from_jiffies(jiffies, |
1819 | intel_dp->panel_power_cycle_delay); |
1814 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); |
1820 | 1815 | ||
1821 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
1816 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
1822 | } |
1817 | } |
1823 | 1818 | ||
1824 | static void wait_backlight_on(struct intel_dp *intel_dp) |
1819 | static void wait_backlight_on(struct intel_dp *intel_dp) |
1825 | { |
1820 | { |
1826 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
1821 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
1827 | intel_dp->backlight_on_delay); |
1822 | intel_dp->backlight_on_delay); |
1828 | } |
1823 | } |
1829 | 1824 | ||
1830 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
1825 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
1831 | { |
1826 | { |
1832 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
1827 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
1833 | intel_dp->backlight_off_delay); |
1828 | intel_dp->backlight_off_delay); |
1834 | } |
1829 | } |
1835 | 1830 | ||
1836 | /* Read the current pp_control value, unlocking the register if it |
1831 | /* Read the current pp_control value, unlocking the register if it |
1837 | * is locked |
1832 | * is locked |
1838 | */ |
1833 | */ |
1839 | 1834 | ||
1840 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
1835 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
1841 | { |
1836 | { |
1842 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1837 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1843 | struct drm_i915_private *dev_priv = dev->dev_private; |
1838 | struct drm_i915_private *dev_priv = dev->dev_private; |
1844 | u32 control; |
1839 | u32 control; |
1845 | 1840 | ||
1846 | lockdep_assert_held(&dev_priv->pps_mutex); |
1841 | lockdep_assert_held(&dev_priv->pps_mutex); |
1847 | 1842 | ||
1848 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
1843 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
1849 | if (!IS_BROXTON(dev)) { |
1844 | if (!IS_BROXTON(dev)) { |
1850 | control &= ~PANEL_UNLOCK_MASK; |
1845 | control &= ~PANEL_UNLOCK_MASK; |
1851 | control |= PANEL_UNLOCK_REGS; |
1846 | control |= PANEL_UNLOCK_REGS; |
1852 | } |
1847 | } |
1853 | return control; |
1848 | return control; |
1854 | } |
1849 | } |
1855 | 1850 | ||
1856 | /* |
1851 | /* |
1857 | * Must be paired with edp_panel_vdd_off(). |
1852 | * Must be paired with edp_panel_vdd_off(). |
1858 | * Must hold pps_mutex around the whole on/off sequence. |
1853 | * Must hold pps_mutex around the whole on/off sequence. |
1859 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
1854 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
1860 | */ |
1855 | */ |
1861 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
1856 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
1862 | { |
1857 | { |
1863 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1858 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1864 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1859 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1865 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1860 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1866 | struct drm_i915_private *dev_priv = dev->dev_private; |
1861 | struct drm_i915_private *dev_priv = dev->dev_private; |
1867 | enum intel_display_power_domain power_domain; |
1862 | enum intel_display_power_domain power_domain; |
1868 | u32 pp; |
1863 | u32 pp; |
1869 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
1864 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
1870 | bool need_to_disable = !intel_dp->want_panel_vdd; |
1865 | bool need_to_disable = !intel_dp->want_panel_vdd; |
1871 | 1866 | ||
1872 | lockdep_assert_held(&dev_priv->pps_mutex); |
1867 | lockdep_assert_held(&dev_priv->pps_mutex); |
1873 | 1868 | ||
1874 | if (!is_edp(intel_dp)) |
1869 | if (!is_edp(intel_dp)) |
1875 | return false; |
1870 | return false; |
1876 | 1871 | ||
1877 | // cancel_delayed_work(&intel_dp->panel_vdd_work); |
1872 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
1878 | intel_dp->want_panel_vdd = true; |
1873 | intel_dp->want_panel_vdd = true; |
1879 | 1874 | ||
1880 | if (edp_have_panel_vdd(intel_dp)) |
1875 | if (edp_have_panel_vdd(intel_dp)) |
1881 | return need_to_disable; |
1876 | return need_to_disable; |
1882 | 1877 | ||
1883 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1878 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1884 | intel_display_power_get(dev_priv, power_domain); |
1879 | intel_display_power_get(dev_priv, power_domain); |
1885 | 1880 | ||
1886 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1881 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1887 | port_name(intel_dig_port->port)); |
1882 | port_name(intel_dig_port->port)); |
1888 | 1883 | ||
1889 | if (!edp_have_panel_power(intel_dp)) |
1884 | if (!edp_have_panel_power(intel_dp)) |
1890 | wait_panel_power_cycle(intel_dp); |
1885 | wait_panel_power_cycle(intel_dp); |
1891 | 1886 | ||
1892 | pp = ironlake_get_pp_control(intel_dp); |
1887 | pp = ironlake_get_pp_control(intel_dp); |
1893 | pp |= EDP_FORCE_VDD; |
1888 | pp |= EDP_FORCE_VDD; |
1894 | 1889 | ||
1895 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1890 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1896 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1891 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1897 | 1892 | ||
1898 | I915_WRITE(pp_ctrl_reg, pp); |
1893 | I915_WRITE(pp_ctrl_reg, pp); |
1899 | POSTING_READ(pp_ctrl_reg); |
1894 | POSTING_READ(pp_ctrl_reg); |
1900 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1895 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1901 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1896 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1902 | /* |
1897 | /* |
1903 | * If the panel wasn't on, delay before accessing aux channel |
1898 | * If the panel wasn't on, delay before accessing aux channel |
1904 | */ |
1899 | */ |
1905 | if (!edp_have_panel_power(intel_dp)) { |
1900 | if (!edp_have_panel_power(intel_dp)) { |
1906 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1901 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1907 | port_name(intel_dig_port->port)); |
1902 | port_name(intel_dig_port->port)); |
1908 | msleep(intel_dp->panel_power_up_delay); |
1903 | msleep(intel_dp->panel_power_up_delay); |
1909 | } |
1904 | } |
1910 | 1905 | ||
1911 | return need_to_disable; |
1906 | return need_to_disable; |
1912 | } |
1907 | } |
1913 | 1908 | ||
1914 | /* |
1909 | /* |
1915 | * Must be paired with intel_edp_panel_vdd_off() or |
1910 | * Must be paired with intel_edp_panel_vdd_off() or |
1916 | * intel_edp_panel_off(). |
1911 | * intel_edp_panel_off(). |
1917 | * Nested calls to these functions are not allowed since |
1912 | * Nested calls to these functions are not allowed since |
1918 | * we drop the lock. Caller must use some higher level |
1913 | * we drop the lock. Caller must use some higher level |
1919 | * locking to prevent nested calls from other threads. |
1914 | * locking to prevent nested calls from other threads. |
1920 | */ |
1915 | */ |
1921 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1916 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1922 | { |
1917 | { |
1923 | bool vdd; |
1918 | bool vdd; |
1924 | 1919 | ||
1925 | if (!is_edp(intel_dp)) |
1920 | if (!is_edp(intel_dp)) |
1926 | return; |
1921 | return; |
1927 | 1922 | ||
1928 | pps_lock(intel_dp); |
1923 | pps_lock(intel_dp); |
1929 | vdd = edp_panel_vdd_on(intel_dp); |
1924 | vdd = edp_panel_vdd_on(intel_dp); |
1930 | pps_unlock(intel_dp); |
1925 | pps_unlock(intel_dp); |
1931 | 1926 | ||
1932 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
1927 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
1933 | port_name(dp_to_dig_port(intel_dp)->port)); |
1928 | port_name(dp_to_dig_port(intel_dp)->port)); |
1934 | } |
1929 | } |
1935 | 1930 | ||
1936 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1931 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1937 | { |
1932 | { |
1938 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1933 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1939 | struct drm_i915_private *dev_priv = dev->dev_private; |
1934 | struct drm_i915_private *dev_priv = dev->dev_private; |
1940 | struct intel_digital_port *intel_dig_port = |
1935 | struct intel_digital_port *intel_dig_port = |
1941 | dp_to_dig_port(intel_dp); |
1936 | dp_to_dig_port(intel_dp); |
1942 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1937 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1943 | enum intel_display_power_domain power_domain; |
1938 | enum intel_display_power_domain power_domain; |
1944 | u32 pp; |
1939 | u32 pp; |
1945 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
1940 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
1946 | 1941 | ||
1947 | lockdep_assert_held(&dev_priv->pps_mutex); |
1942 | lockdep_assert_held(&dev_priv->pps_mutex); |
1948 | 1943 | ||
1949 | WARN_ON(intel_dp->want_panel_vdd); |
1944 | WARN_ON(intel_dp->want_panel_vdd); |
1950 | 1945 | ||
1951 | if (!edp_have_panel_vdd(intel_dp)) |
1946 | if (!edp_have_panel_vdd(intel_dp)) |
1952 | return; |
1947 | return; |
1953 | 1948 | ||
1954 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1949 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1955 | port_name(intel_dig_port->port)); |
1950 | port_name(intel_dig_port->port)); |
1956 | 1951 | ||
1957 | pp = ironlake_get_pp_control(intel_dp); |
1952 | pp = ironlake_get_pp_control(intel_dp); |
1958 | pp &= ~EDP_FORCE_VDD; |
1953 | pp &= ~EDP_FORCE_VDD; |
1959 | 1954 | ||
1960 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1955 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1961 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1956 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1962 | 1957 | ||
1963 | I915_WRITE(pp_ctrl_reg, pp); |
1958 | I915_WRITE(pp_ctrl_reg, pp); |
1964 | POSTING_READ(pp_ctrl_reg); |
1959 | POSTING_READ(pp_ctrl_reg); |
1965 | 1960 | ||
1966 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1961 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1967 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1962 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1968 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1963 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1969 | 1964 | ||
1970 | if ((pp & POWER_TARGET_ON) == 0) |
1965 | if ((pp & POWER_TARGET_ON) == 0) |
1971 | intel_dp->last_power_cycle = jiffies; |
1966 | intel_dp->panel_power_off_time = ktime_get(); |
1972 | 1967 | ||
1973 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1968 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1974 | intel_display_power_put(dev_priv, power_domain); |
1969 | intel_display_power_put(dev_priv, power_domain); |
1975 | } |
1970 | } |
1976 | 1971 | ||
1977 | static void edp_panel_vdd_work(struct work_struct *__work) |
1972 | static void edp_panel_vdd_work(struct work_struct *__work) |
1978 | { |
1973 | { |
1979 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
1974 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
1980 | struct intel_dp, panel_vdd_work); |
1975 | struct intel_dp, panel_vdd_work); |
1981 | 1976 | ||
1982 | pps_lock(intel_dp); |
1977 | pps_lock(intel_dp); |
1983 | if (!intel_dp->want_panel_vdd) |
1978 | if (!intel_dp->want_panel_vdd) |
1984 | edp_panel_vdd_off_sync(intel_dp); |
1979 | edp_panel_vdd_off_sync(intel_dp); |
1985 | pps_unlock(intel_dp); |
1980 | pps_unlock(intel_dp); |
1986 | } |
1981 | } |
1987 | 1982 | ||
1988 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1983 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1989 | { |
1984 | { |
1990 | unsigned long delay; |
1985 | unsigned long delay; |
1991 | 1986 | ||
1992 | /* |
1987 | /* |
1993 | * Queue the timer to fire a long time from now (relative to the power |
1988 | * Queue the timer to fire a long time from now (relative to the power |
1994 | * down delay) to keep the panel power up across a sequence of |
1989 | * down delay) to keep the panel power up across a sequence of |
1995 | * operations. |
1990 | * operations. |
1996 | */ |
1991 | */ |
1997 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
1992 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
1998 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
1993 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
1999 | } |
1994 | } |
2000 | 1995 | ||
2001 | /* |
1996 | /* |
2002 | * Must be paired with edp_panel_vdd_on(). |
1997 | * Must be paired with edp_panel_vdd_on(). |
2003 | * Must hold pps_mutex around the whole on/off sequence. |
1998 | * Must hold pps_mutex around the whole on/off sequence. |
2004 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
1999 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
2005 | */ |
2000 | */ |
2006 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
2001 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
2007 | { |
2002 | { |
2008 | struct drm_i915_private *dev_priv = |
2003 | struct drm_i915_private *dev_priv = |
2009 | intel_dp_to_dev(intel_dp)->dev_private; |
2004 | intel_dp_to_dev(intel_dp)->dev_private; |
2010 | 2005 | ||
2011 | lockdep_assert_held(&dev_priv->pps_mutex); |
2006 | lockdep_assert_held(&dev_priv->pps_mutex); |
2012 | 2007 | ||
2013 | if (!is_edp(intel_dp)) |
2008 | if (!is_edp(intel_dp)) |
2014 | return; |
2009 | return; |
2015 | 2010 | ||
2016 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
2011 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
2017 | port_name(dp_to_dig_port(intel_dp)->port)); |
2012 | port_name(dp_to_dig_port(intel_dp)->port)); |
2018 | 2013 | ||
2019 | intel_dp->want_panel_vdd = false; |
2014 | intel_dp->want_panel_vdd = false; |
2020 | 2015 | ||
2021 | if (sync) |
2016 | if (sync) |
2022 | edp_panel_vdd_off_sync(intel_dp); |
2017 | edp_panel_vdd_off_sync(intel_dp); |
2023 | else |
2018 | else |
2024 | edp_panel_vdd_schedule_off(intel_dp); |
2019 | edp_panel_vdd_schedule_off(intel_dp); |
2025 | } |
2020 | } |
2026 | 2021 | ||
2027 | static void edp_panel_on(struct intel_dp *intel_dp) |
2022 | static void edp_panel_on(struct intel_dp *intel_dp) |
2028 | { |
2023 | { |
2029 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2024 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2030 | struct drm_i915_private *dev_priv = dev->dev_private; |
2025 | struct drm_i915_private *dev_priv = dev->dev_private; |
2031 | u32 pp; |
2026 | u32 pp; |
2032 | i915_reg_t pp_ctrl_reg; |
2027 | i915_reg_t pp_ctrl_reg; |
2033 | 2028 | ||
2034 | lockdep_assert_held(&dev_priv->pps_mutex); |
2029 | lockdep_assert_held(&dev_priv->pps_mutex); |
2035 | 2030 | ||
2036 | if (!is_edp(intel_dp)) |
2031 | if (!is_edp(intel_dp)) |
2037 | return; |
2032 | return; |
2038 | 2033 | ||
2039 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
2034 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
2040 | port_name(dp_to_dig_port(intel_dp)->port)); |
2035 | port_name(dp_to_dig_port(intel_dp)->port)); |
2041 | 2036 | ||
2042 | if (WARN(edp_have_panel_power(intel_dp), |
2037 | if (WARN(edp_have_panel_power(intel_dp), |
2043 | "eDP port %c panel power already on\n", |
2038 | "eDP port %c panel power already on\n", |
2044 | port_name(dp_to_dig_port(intel_dp)->port))) |
2039 | port_name(dp_to_dig_port(intel_dp)->port))) |
2045 | return; |
2040 | return; |
2046 | 2041 | ||
2047 | wait_panel_power_cycle(intel_dp); |
2042 | wait_panel_power_cycle(intel_dp); |
2048 | 2043 | ||
2049 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2044 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2050 | pp = ironlake_get_pp_control(intel_dp); |
2045 | pp = ironlake_get_pp_control(intel_dp); |
2051 | if (IS_GEN5(dev)) { |
2046 | if (IS_GEN5(dev)) { |
2052 | /* ILK workaround: disable reset around power sequence */ |
2047 | /* ILK workaround: disable reset around power sequence */ |
2053 | pp &= ~PANEL_POWER_RESET; |
2048 | pp &= ~PANEL_POWER_RESET; |
2054 | I915_WRITE(pp_ctrl_reg, pp); |
2049 | I915_WRITE(pp_ctrl_reg, pp); |
2055 | POSTING_READ(pp_ctrl_reg); |
2050 | POSTING_READ(pp_ctrl_reg); |
2056 | } |
2051 | } |
2057 | 2052 | ||
2058 | pp |= POWER_TARGET_ON; |
2053 | pp |= POWER_TARGET_ON; |
2059 | if (!IS_GEN5(dev)) |
2054 | if (!IS_GEN5(dev)) |
2060 | pp |= PANEL_POWER_RESET; |
2055 | pp |= PANEL_POWER_RESET; |
2061 | 2056 | ||
2062 | I915_WRITE(pp_ctrl_reg, pp); |
2057 | I915_WRITE(pp_ctrl_reg, pp); |
2063 | POSTING_READ(pp_ctrl_reg); |
2058 | POSTING_READ(pp_ctrl_reg); |
2064 | 2059 | ||
2065 | wait_panel_on(intel_dp); |
2060 | wait_panel_on(intel_dp); |
2066 | intel_dp->last_power_on = jiffies; |
2061 | intel_dp->last_power_on = jiffies; |
2067 | 2062 | ||
2068 | if (IS_GEN5(dev)) { |
2063 | if (IS_GEN5(dev)) { |
2069 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
2064 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
2070 | I915_WRITE(pp_ctrl_reg, pp); |
2065 | I915_WRITE(pp_ctrl_reg, pp); |
2071 | POSTING_READ(pp_ctrl_reg); |
2066 | POSTING_READ(pp_ctrl_reg); |
2072 | } |
2067 | } |
2073 | } |
2068 | } |
2074 | 2069 | ||
2075 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2070 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2076 | { |
2071 | { |
2077 | if (!is_edp(intel_dp)) |
2072 | if (!is_edp(intel_dp)) |
2078 | return; |
2073 | return; |
2079 | 2074 | ||
2080 | pps_lock(intel_dp); |
2075 | pps_lock(intel_dp); |
2081 | edp_panel_on(intel_dp); |
2076 | edp_panel_on(intel_dp); |
2082 | pps_unlock(intel_dp); |
2077 | pps_unlock(intel_dp); |
2083 | } |
2078 | } |
2084 | 2079 | ||
2085 | 2080 | ||
2086 | static void edp_panel_off(struct intel_dp *intel_dp) |
2081 | static void edp_panel_off(struct intel_dp *intel_dp) |
2087 | { |
2082 | { |
2088 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2083 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2089 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2084 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2090 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2085 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2091 | struct drm_i915_private *dev_priv = dev->dev_private; |
2086 | struct drm_i915_private *dev_priv = dev->dev_private; |
2092 | enum intel_display_power_domain power_domain; |
2087 | enum intel_display_power_domain power_domain; |
2093 | u32 pp; |
2088 | u32 pp; |
2094 | i915_reg_t pp_ctrl_reg; |
2089 | i915_reg_t pp_ctrl_reg; |
2095 | 2090 | ||
2096 | lockdep_assert_held(&dev_priv->pps_mutex); |
2091 | lockdep_assert_held(&dev_priv->pps_mutex); |
2097 | 2092 | ||
2098 | if (!is_edp(intel_dp)) |
2093 | if (!is_edp(intel_dp)) |
2099 | return; |
2094 | return; |
2100 | 2095 | ||
2101 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2096 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2102 | port_name(dp_to_dig_port(intel_dp)->port)); |
2097 | port_name(dp_to_dig_port(intel_dp)->port)); |
2103 | 2098 | ||
2104 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2099 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2105 | port_name(dp_to_dig_port(intel_dp)->port)); |
2100 | port_name(dp_to_dig_port(intel_dp)->port)); |
2106 | 2101 | ||
2107 | pp = ironlake_get_pp_control(intel_dp); |
2102 | pp = ironlake_get_pp_control(intel_dp); |
2108 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2103 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2109 | * panels get very unhappy and cease to work. */ |
2104 | * panels get very unhappy and cease to work. */ |
2110 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
2105 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
2111 | EDP_BLC_ENABLE); |
2106 | EDP_BLC_ENABLE); |
2112 | 2107 | ||
2113 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2108 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2114 | 2109 | ||
2115 | intel_dp->want_panel_vdd = false; |
2110 | intel_dp->want_panel_vdd = false; |
2116 | 2111 | ||
2117 | I915_WRITE(pp_ctrl_reg, pp); |
2112 | I915_WRITE(pp_ctrl_reg, pp); |
2118 | POSTING_READ(pp_ctrl_reg); |
2113 | POSTING_READ(pp_ctrl_reg); |
2119 | 2114 | ||
2120 | intel_dp->last_power_cycle = jiffies; |
2115 | intel_dp->panel_power_off_time = ktime_get(); |
2121 | wait_panel_off(intel_dp); |
2116 | wait_panel_off(intel_dp); |
2122 | 2117 | ||
2123 | /* We got a reference when we enabled the VDD. */ |
2118 | /* We got a reference when we enabled the VDD. */ |
2124 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
2119 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
2125 | intel_display_power_put(dev_priv, power_domain); |
2120 | intel_display_power_put(dev_priv, power_domain); |
2126 | } |
2121 | } |
2127 | 2122 | ||
2128 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2123 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2129 | { |
2124 | { |
2130 | if (!is_edp(intel_dp)) |
2125 | if (!is_edp(intel_dp)) |
2131 | return; |
2126 | return; |
2132 | 2127 | ||
2133 | pps_lock(intel_dp); |
2128 | pps_lock(intel_dp); |
2134 | edp_panel_off(intel_dp); |
2129 | edp_panel_off(intel_dp); |
2135 | pps_unlock(intel_dp); |
2130 | pps_unlock(intel_dp); |
2136 | } |
2131 | } |
2137 | 2132 | ||
2138 | /* Enable backlight in the panel power control. */ |
2133 | /* Enable backlight in the panel power control. */ |
2139 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
2134 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
2140 | { |
2135 | { |
2141 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2136 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2142 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2137 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2143 | struct drm_i915_private *dev_priv = dev->dev_private; |
2138 | struct drm_i915_private *dev_priv = dev->dev_private; |
2144 | u32 pp; |
2139 | u32 pp; |
2145 | i915_reg_t pp_ctrl_reg; |
2140 | i915_reg_t pp_ctrl_reg; |
2146 | 2141 | ||
2147 | /* |
2142 | /* |
2148 | * If we enable the backlight right away following a panel power |
2143 | * If we enable the backlight right away following a panel power |
2149 | * on, we may see slight flicker as the panel syncs with the eDP |
2144 | * on, we may see slight flicker as the panel syncs with the eDP |
2150 | * link. So delay a bit to make sure the image is solid before |
2145 | * link. So delay a bit to make sure the image is solid before |
2151 | * allowing it to appear. |
2146 | * allowing it to appear. |
2152 | */ |
2147 | */ |
2153 | wait_backlight_on(intel_dp); |
2148 | wait_backlight_on(intel_dp); |
2154 | 2149 | ||
2155 | pps_lock(intel_dp); |
2150 | pps_lock(intel_dp); |
2156 | 2151 | ||
2157 | pp = ironlake_get_pp_control(intel_dp); |
2152 | pp = ironlake_get_pp_control(intel_dp); |
2158 | pp |= EDP_BLC_ENABLE; |
2153 | pp |= EDP_BLC_ENABLE; |
2159 | 2154 | ||
2160 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2155 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2161 | 2156 | ||
2162 | I915_WRITE(pp_ctrl_reg, pp); |
2157 | I915_WRITE(pp_ctrl_reg, pp); |
2163 | POSTING_READ(pp_ctrl_reg); |
2158 | POSTING_READ(pp_ctrl_reg); |
2164 | 2159 | ||
2165 | pps_unlock(intel_dp); |
2160 | pps_unlock(intel_dp); |
2166 | } |
2161 | } |
2167 | 2162 | ||
2168 | /* Enable backlight PWM and backlight PP control. */ |
2163 | /* Enable backlight PWM and backlight PP control. */ |
2169 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
2164 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
2170 | { |
2165 | { |
2171 | if (!is_edp(intel_dp)) |
2166 | if (!is_edp(intel_dp)) |
2172 | return; |
2167 | return; |
2173 | 2168 | ||
2174 | DRM_DEBUG_KMS("\n"); |
2169 | DRM_DEBUG_KMS("\n"); |
2175 | 2170 | ||
2176 | intel_panel_enable_backlight(intel_dp->attached_connector); |
2171 | intel_panel_enable_backlight(intel_dp->attached_connector); |
2177 | _intel_edp_backlight_on(intel_dp); |
2172 | _intel_edp_backlight_on(intel_dp); |
2178 | } |
2173 | } |
2179 | 2174 | ||
2180 | /* Disable backlight in the panel power control. */ |
2175 | /* Disable backlight in the panel power control. */ |
2181 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
2176 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
2182 | { |
2177 | { |
2183 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2178 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2184 | struct drm_i915_private *dev_priv = dev->dev_private; |
2179 | struct drm_i915_private *dev_priv = dev->dev_private; |
2185 | u32 pp; |
2180 | u32 pp; |
2186 | i915_reg_t pp_ctrl_reg; |
2181 | i915_reg_t pp_ctrl_reg; |
2187 | 2182 | ||
2188 | if (!is_edp(intel_dp)) |
2183 | if (!is_edp(intel_dp)) |
2189 | return; |
2184 | return; |
2190 | 2185 | ||
2191 | pps_lock(intel_dp); |
2186 | pps_lock(intel_dp); |
2192 | 2187 | ||
2193 | pp = ironlake_get_pp_control(intel_dp); |
2188 | pp = ironlake_get_pp_control(intel_dp); |
2194 | pp &= ~EDP_BLC_ENABLE; |
2189 | pp &= ~EDP_BLC_ENABLE; |
2195 | 2190 | ||
2196 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2191 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2197 | 2192 | ||
2198 | I915_WRITE(pp_ctrl_reg, pp); |
2193 | I915_WRITE(pp_ctrl_reg, pp); |
2199 | POSTING_READ(pp_ctrl_reg); |
2194 | POSTING_READ(pp_ctrl_reg); |
2200 | 2195 | ||
2201 | pps_unlock(intel_dp); |
2196 | pps_unlock(intel_dp); |
2202 | 2197 | ||
2203 | intel_dp->last_backlight_off = jiffies; |
2198 | intel_dp->last_backlight_off = jiffies; |
2204 | edp_wait_backlight_off(intel_dp); |
2199 | edp_wait_backlight_off(intel_dp); |
2205 | } |
2200 | } |
2206 | 2201 | ||
2207 | /* Disable backlight PP control and backlight PWM. */ |
2202 | /* Disable backlight PP control and backlight PWM. */ |
2208 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
2203 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
2209 | { |
2204 | { |
2210 | if (!is_edp(intel_dp)) |
2205 | if (!is_edp(intel_dp)) |
2211 | return; |
2206 | return; |
2212 | 2207 | ||
2213 | DRM_DEBUG_KMS("\n"); |
2208 | DRM_DEBUG_KMS("\n"); |
2214 | 2209 | ||
2215 | _intel_edp_backlight_off(intel_dp); |
2210 | _intel_edp_backlight_off(intel_dp); |
2216 | intel_panel_disable_backlight(intel_dp->attached_connector); |
2211 | intel_panel_disable_backlight(intel_dp->attached_connector); |
2217 | } |
2212 | } |
2218 | 2213 | ||
2219 | /* |
2214 | /* |
2220 | * Hook for controlling the panel power control backlight through the bl_power |
2215 | * Hook for controlling the panel power control backlight through the bl_power |
2221 | * sysfs attribute. Take care to handle multiple calls. |
2216 | * sysfs attribute. Take care to handle multiple calls. |
2222 | */ |
2217 | */ |
2223 | static void intel_edp_backlight_power(struct intel_connector *connector, |
2218 | static void intel_edp_backlight_power(struct intel_connector *connector, |
2224 | bool enable) |
2219 | bool enable) |
2225 | { |
2220 | { |
2226 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
2221 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
2227 | bool is_enabled; |
2222 | bool is_enabled; |
2228 | 2223 | ||
2229 | pps_lock(intel_dp); |
2224 | pps_lock(intel_dp); |
2230 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
2225 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
2231 | pps_unlock(intel_dp); |
2226 | pps_unlock(intel_dp); |
2232 | 2227 | ||
2233 | if (is_enabled == enable) |
2228 | if (is_enabled == enable) |
2234 | return; |
2229 | return; |
2235 | 2230 | ||
2236 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2231 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2237 | enable ? "enable" : "disable"); |
2232 | enable ? "enable" : "disable"); |
2238 | 2233 | ||
2239 | if (enable) |
2234 | if (enable) |
2240 | _intel_edp_backlight_on(intel_dp); |
2235 | _intel_edp_backlight_on(intel_dp); |
2241 | else |
2236 | else |
2242 | _intel_edp_backlight_off(intel_dp); |
2237 | _intel_edp_backlight_off(intel_dp); |
2243 | } |
2238 | } |
2244 | - | ||
2245 | static const char *state_string(bool enabled) |
- | |
2246 | { |
- | |
2247 | return enabled ? "on" : "off"; |
- | |
2248 | } |
- | |
2249 | 2239 | ||
2250 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2240 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2251 | { |
2241 | { |
2252 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
2242 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
2253 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
2243 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
2254 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; |
2244 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; |
2255 | 2245 | ||
2256 | I915_STATE_WARN(cur_state != state, |
2246 | I915_STATE_WARN(cur_state != state, |
2257 | "DP port %c state assertion failure (expected %s, current %s)\n", |
2247 | "DP port %c state assertion failure (expected %s, current %s)\n", |
2258 | port_name(dig_port->port), |
2248 | port_name(dig_port->port), |
2259 | state_string(state), state_string(cur_state)); |
2249 | onoff(state), onoff(cur_state)); |
2260 | } |
2250 | } |
2261 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) |
2251 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) |
2262 | 2252 | ||
2263 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) |
2253 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) |
2264 | { |
2254 | { |
2265 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; |
2255 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; |
2266 | 2256 | ||
2267 | I915_STATE_WARN(cur_state != state, |
2257 | I915_STATE_WARN(cur_state != state, |
2268 | "eDP PLL state assertion failure (expected %s, current %s)\n", |
2258 | "eDP PLL state assertion failure (expected %s, current %s)\n", |
2269 | state_string(state), state_string(cur_state)); |
2259 | onoff(state), onoff(cur_state)); |
2270 | } |
2260 | } |
2271 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) |
2261 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) |
2272 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) |
2262 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) |
2273 | 2263 | ||
2274 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
2264 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
2275 | { |
2265 | { |
2276 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2266 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2277 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2267 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2278 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2268 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2279 | 2269 | ||
2280 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2270 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2281 | assert_dp_port_disabled(intel_dp); |
2271 | assert_dp_port_disabled(intel_dp); |
2282 | assert_edp_pll_disabled(dev_priv); |
2272 | assert_edp_pll_disabled(dev_priv); |
2283 | 2273 | ||
2284 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
2274 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
2285 | crtc->config->port_clock); |
2275 | crtc->config->port_clock); |
2286 | 2276 | ||
2287 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; |
2277 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; |
2288 | 2278 | ||
2289 | if (crtc->config->port_clock == 162000) |
2279 | if (crtc->config->port_clock == 162000) |
2290 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
2280 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
2291 | else |
2281 | else |
2292 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
2282 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
2293 | 2283 | ||
2294 | I915_WRITE(DP_A, intel_dp->DP); |
2284 | I915_WRITE(DP_A, intel_dp->DP); |
2295 | POSTING_READ(DP_A); |
2285 | POSTING_READ(DP_A); |
2296 | udelay(500); |
2286 | udelay(500); |
2297 | 2287 | ||
2298 | intel_dp->DP |= DP_PLL_ENABLE; |
2288 | intel_dp->DP |= DP_PLL_ENABLE; |
2299 | 2289 | ||
2300 | I915_WRITE(DP_A, intel_dp->DP); |
2290 | I915_WRITE(DP_A, intel_dp->DP); |
2301 | POSTING_READ(DP_A); |
2291 | POSTING_READ(DP_A); |
2302 | udelay(200); |
2292 | udelay(200); |
2303 | } |
2293 | } |
2304 | 2294 | ||
2305 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
2295 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
2306 | { |
2296 | { |
2307 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2297 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2308 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2298 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2309 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2299 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2310 | 2300 | ||
2311 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2301 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2312 | assert_dp_port_disabled(intel_dp); |
2302 | assert_dp_port_disabled(intel_dp); |
2313 | assert_edp_pll_enabled(dev_priv); |
2303 | assert_edp_pll_enabled(dev_priv); |
2314 | 2304 | ||
2315 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2305 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2316 | 2306 | ||
2317 | intel_dp->DP &= ~DP_PLL_ENABLE; |
2307 | intel_dp->DP &= ~DP_PLL_ENABLE; |
2318 | 2308 | ||
2319 | I915_WRITE(DP_A, intel_dp->DP); |
2309 | I915_WRITE(DP_A, intel_dp->DP); |
2320 | POSTING_READ(DP_A); |
2310 | POSTING_READ(DP_A); |
2321 | udelay(200); |
2311 | udelay(200); |
2322 | } |
2312 | } |
2323 | 2313 | ||
2324 | /* If the sink supports it, try to set the power state appropriately */ |
2314 | /* If the sink supports it, try to set the power state appropriately */ |
2325 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
2315 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
2326 | { |
2316 | { |
2327 | int ret, i; |
2317 | int ret, i; |
2328 | 2318 | ||
2329 | /* Should have a valid DPCD by this point */ |
2319 | /* Should have a valid DPCD by this point */ |
2330 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
2320 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
2331 | return; |
2321 | return; |
2332 | 2322 | ||
2333 | if (mode != DRM_MODE_DPMS_ON) { |
2323 | if (mode != DRM_MODE_DPMS_ON) { |
2334 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2324 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2335 | DP_SET_POWER_D3); |
2325 | DP_SET_POWER_D3); |
2336 | } else { |
2326 | } else { |
2337 | /* |
2327 | /* |
2338 | * When turning on, we need to retry for 1ms to give the sink |
2328 | * When turning on, we need to retry for 1ms to give the sink |
2339 | * time to wake up. |
2329 | * time to wake up. |
2340 | */ |
2330 | */ |
2341 | for (i = 0; i < 3; i++) { |
2331 | for (i = 0; i < 3; i++) { |
2342 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2332 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2343 | DP_SET_POWER_D0); |
2333 | DP_SET_POWER_D0); |
2344 | if (ret == 1) |
2334 | if (ret == 1) |
2345 | break; |
2335 | break; |
2346 | msleep(1); |
2336 | msleep(1); |
2347 | } |
2337 | } |
2348 | } |
2338 | } |
2349 | 2339 | ||
2350 | if (ret != 1) |
2340 | if (ret != 1) |
2351 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
2341 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
2352 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
2342 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
2353 | } |
2343 | } |
2354 | 2344 | ||
2355 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2345 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2356 | enum pipe *pipe) |
2346 | enum pipe *pipe) |
2357 | { |
2347 | { |
2358 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2348 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2359 | enum port port = dp_to_dig_port(intel_dp)->port; |
2349 | enum port port = dp_to_dig_port(intel_dp)->port; |
2360 | struct drm_device *dev = encoder->base.dev; |
2350 | struct drm_device *dev = encoder->base.dev; |
2361 | struct drm_i915_private *dev_priv = dev->dev_private; |
2351 | struct drm_i915_private *dev_priv = dev->dev_private; |
2362 | enum intel_display_power_domain power_domain; |
2352 | enum intel_display_power_domain power_domain; |
2363 | u32 tmp; |
2353 | u32 tmp; |
2364 | bool ret; |
2354 | bool ret; |
2365 | 2355 | ||
2366 | power_domain = intel_display_port_power_domain(encoder); |
2356 | power_domain = intel_display_port_power_domain(encoder); |
2367 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
2357 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
2368 | return false; |
2358 | return false; |
2369 | 2359 | ||
2370 | ret = false; |
2360 | ret = false; |
2371 | 2361 | ||
2372 | tmp = I915_READ(intel_dp->output_reg); |
2362 | tmp = I915_READ(intel_dp->output_reg); |
2373 | 2363 | ||
2374 | if (!(tmp & DP_PORT_EN)) |
2364 | if (!(tmp & DP_PORT_EN)) |
2375 | goto out; |
2365 | goto out; |
2376 | 2366 | ||
2377 | if (IS_GEN7(dev) && port == PORT_A) { |
2367 | if (IS_GEN7(dev) && port == PORT_A) { |
2378 | *pipe = PORT_TO_PIPE_CPT(tmp); |
2368 | *pipe = PORT_TO_PIPE_CPT(tmp); |
2379 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2369 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2380 | enum pipe p; |
2370 | enum pipe p; |
2381 | 2371 | ||
2382 | for_each_pipe(dev_priv, p) { |
2372 | for_each_pipe(dev_priv, p) { |
2383 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); |
2373 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); |
2384 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { |
2374 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { |
2385 | *pipe = p; |
2375 | *pipe = p; |
2386 | ret = true; |
2376 | ret = true; |
2387 | 2377 | ||
2388 | goto out; |
2378 | goto out; |
2389 | } |
2379 | } |
2390 | } |
2380 | } |
2391 | 2381 | ||
2392 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
2382 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
2393 | i915_mmio_reg_offset(intel_dp->output_reg)); |
2383 | i915_mmio_reg_offset(intel_dp->output_reg)); |
2394 | } else if (IS_CHERRYVIEW(dev)) { |
2384 | } else if (IS_CHERRYVIEW(dev)) { |
2395 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2385 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2396 | } else { |
2386 | } else { |
2397 | *pipe = PORT_TO_PIPE(tmp); |
2387 | *pipe = PORT_TO_PIPE(tmp); |
2398 | } |
2388 | } |
2399 | 2389 | ||
2400 | ret = true; |
2390 | ret = true; |
2401 | 2391 | ||
2402 | out: |
2392 | out: |
2403 | intel_display_power_put(dev_priv, power_domain); |
2393 | intel_display_power_put(dev_priv, power_domain); |
2404 | 2394 | ||
2405 | return ret; |
2395 | return ret; |
2406 | } |
2396 | } |
2407 | 2397 | ||
2408 | static void intel_dp_get_config(struct intel_encoder *encoder, |
2398 | static void intel_dp_get_config(struct intel_encoder *encoder, |
2409 | struct intel_crtc_state *pipe_config) |
2399 | struct intel_crtc_state *pipe_config) |
2410 | { |
2400 | { |
2411 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2401 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2412 | u32 tmp, flags = 0; |
2402 | u32 tmp, flags = 0; |
2413 | struct drm_device *dev = encoder->base.dev; |
2403 | struct drm_device *dev = encoder->base.dev; |
2414 | struct drm_i915_private *dev_priv = dev->dev_private; |
2404 | struct drm_i915_private *dev_priv = dev->dev_private; |
2415 | enum port port = dp_to_dig_port(intel_dp)->port; |
2405 | enum port port = dp_to_dig_port(intel_dp)->port; |
2416 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2406 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2417 | int dotclock; |
2407 | int dotclock; |
2418 | 2408 | ||
2419 | tmp = I915_READ(intel_dp->output_reg); |
2409 | tmp = I915_READ(intel_dp->output_reg); |
2420 | 2410 | ||
2421 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; |
2411 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; |
2422 | 2412 | ||
2423 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2413 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2424 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2414 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2425 | 2415 | ||
2426 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
2416 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
2427 | flags |= DRM_MODE_FLAG_PHSYNC; |
2417 | flags |= DRM_MODE_FLAG_PHSYNC; |
2428 | else |
2418 | else |
2429 | flags |= DRM_MODE_FLAG_NHSYNC; |
2419 | flags |= DRM_MODE_FLAG_NHSYNC; |
2430 | 2420 | ||
2431 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
2421 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
2432 | flags |= DRM_MODE_FLAG_PVSYNC; |
2422 | flags |= DRM_MODE_FLAG_PVSYNC; |
2433 | else |
2423 | else |
2434 | flags |= DRM_MODE_FLAG_NVSYNC; |
2424 | flags |= DRM_MODE_FLAG_NVSYNC; |
2435 | } else { |
2425 | } else { |
2436 | if (tmp & DP_SYNC_HS_HIGH) |
2426 | if (tmp & DP_SYNC_HS_HIGH) |
2437 | flags |= DRM_MODE_FLAG_PHSYNC; |
2427 | flags |= DRM_MODE_FLAG_PHSYNC; |
2438 | else |
2428 | else |
2439 | flags |= DRM_MODE_FLAG_NHSYNC; |
2429 | flags |= DRM_MODE_FLAG_NHSYNC; |
2440 | 2430 | ||
2441 | if (tmp & DP_SYNC_VS_HIGH) |
2431 | if (tmp & DP_SYNC_VS_HIGH) |
2442 | flags |= DRM_MODE_FLAG_PVSYNC; |
2432 | flags |= DRM_MODE_FLAG_PVSYNC; |
2443 | else |
2433 | else |
2444 | flags |= DRM_MODE_FLAG_NVSYNC; |
2434 | flags |= DRM_MODE_FLAG_NVSYNC; |
2445 | } |
2435 | } |
2446 | 2436 | ||
2447 | pipe_config->base.adjusted_mode.flags |= flags; |
2437 | pipe_config->base.adjusted_mode.flags |= flags; |
2448 | 2438 | ||
2449 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
2439 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
2450 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
2440 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
2451 | pipe_config->limited_color_range = true; |
2441 | pipe_config->limited_color_range = true; |
2452 | 2442 | ||
2453 | pipe_config->has_dp_encoder = true; |
2443 | pipe_config->has_dp_encoder = true; |
2454 | 2444 | ||
2455 | pipe_config->lane_count = |
2445 | pipe_config->lane_count = |
2456 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; |
2446 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; |
2457 | 2447 | ||
2458 | intel_dp_get_m_n(crtc, pipe_config); |
2448 | intel_dp_get_m_n(crtc, pipe_config); |
2459 | 2449 | ||
2460 | if (port == PORT_A) { |
2450 | if (port == PORT_A) { |
2461 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
2451 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
2462 | pipe_config->port_clock = 162000; |
2452 | pipe_config->port_clock = 162000; |
2463 | else |
2453 | else |
2464 | pipe_config->port_clock = 270000; |
2454 | pipe_config->port_clock = 270000; |
2465 | } |
2455 | } |
2466 | 2456 | ||
2467 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
2457 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
2468 | &pipe_config->dp_m_n); |
2458 | &pipe_config->dp_m_n); |
2469 | 2459 | ||
2470 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
2460 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
2471 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
2461 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
2472 | 2462 | ||
2473 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
2463 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
2474 | 2464 | ||
2475 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
2465 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
2476 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
2466 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
2477 | /* |
2467 | /* |
2478 | * This is a big fat ugly hack. |
2468 | * This is a big fat ugly hack. |
2479 | * |
2469 | * |
2480 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
2470 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
2481 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
2471 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
2482 | * unknown we fail to light up. Yet the same BIOS boots up with |
2472 | * unknown we fail to light up. Yet the same BIOS boots up with |
2483 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
2473 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
2484 | * max, not what it tells us to use. |
2474 | * max, not what it tells us to use. |
2485 | * |
2475 | * |
2486 | * Note: This will still be broken if the eDP panel is not lit |
2476 | * Note: This will still be broken if the eDP panel is not lit |
2487 | * up by the BIOS, and thus we can't get the mode at module |
2477 | * up by the BIOS, and thus we can't get the mode at module |
2488 | * load. |
2478 | * load. |
2489 | */ |
2479 | */ |
2490 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
2480 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
2491 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
2481 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
2492 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
2482 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
2493 | } |
2483 | } |
2494 | } |
2484 | } |
2495 | 2485 | ||
2496 | static void intel_disable_dp(struct intel_encoder *encoder) |
2486 | static void intel_disable_dp(struct intel_encoder *encoder) |
2497 | { |
2487 | { |
2498 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2488 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2499 | struct drm_device *dev = encoder->base.dev; |
2489 | struct drm_device *dev = encoder->base.dev; |
2500 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2490 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2501 | 2491 | ||
2502 | if (crtc->config->has_audio) |
2492 | if (crtc->config->has_audio) |
2503 | intel_audio_codec_disable(encoder); |
2493 | intel_audio_codec_disable(encoder); |
2504 | 2494 | ||
2505 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
2495 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
2506 | intel_psr_disable(intel_dp); |
2496 | intel_psr_disable(intel_dp); |
2507 | 2497 | ||
2508 | /* Make sure the panel is off before trying to change the mode. But also |
2498 | /* Make sure the panel is off before trying to change the mode. But also |
2509 | * ensure that we have vdd while we switch off the panel. */ |
2499 | * ensure that we have vdd while we switch off the panel. */ |
2510 | intel_edp_panel_vdd_on(intel_dp); |
2500 | intel_edp_panel_vdd_on(intel_dp); |
2511 | intel_edp_backlight_off(intel_dp); |
2501 | intel_edp_backlight_off(intel_dp); |
2512 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2502 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2513 | intel_edp_panel_off(intel_dp); |
2503 | intel_edp_panel_off(intel_dp); |
2514 | 2504 | ||
2515 | /* disable the port before the pipe on g4x */ |
2505 | /* disable the port before the pipe on g4x */ |
2516 | if (INTEL_INFO(dev)->gen < 5) |
2506 | if (INTEL_INFO(dev)->gen < 5) |
2517 | intel_dp_link_down(intel_dp); |
2507 | intel_dp_link_down(intel_dp); |
2518 | } |
2508 | } |
2519 | 2509 | ||
2520 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
2510 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
2521 | { |
2511 | { |
2522 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2512 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2523 | enum port port = dp_to_dig_port(intel_dp)->port; |
2513 | enum port port = dp_to_dig_port(intel_dp)->port; |
2524 | 2514 | ||
2525 | intel_dp_link_down(intel_dp); |
2515 | intel_dp_link_down(intel_dp); |
2526 | 2516 | ||
2527 | /* Only ilk+ has port A */ |
2517 | /* Only ilk+ has port A */ |
2528 | if (port == PORT_A) |
2518 | if (port == PORT_A) |
2529 | ironlake_edp_pll_off(intel_dp); |
2519 | ironlake_edp_pll_off(intel_dp); |
2530 | } |
2520 | } |
2531 | 2521 | ||
2532 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
2522 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
2533 | { |
2523 | { |
2534 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2524 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2535 | 2525 | ||
2536 | intel_dp_link_down(intel_dp); |
2526 | intel_dp_link_down(intel_dp); |
2537 | } |
2527 | } |
2538 | 2528 | ||
2539 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
2529 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
2540 | bool reset) |
2530 | bool reset) |
2541 | { |
2531 | { |
2542 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2532 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2543 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
2533 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
2544 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2534 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2545 | enum pipe pipe = crtc->pipe; |
2535 | enum pipe pipe = crtc->pipe; |
2546 | uint32_t val; |
2536 | uint32_t val; |
2547 | 2537 | ||
2548 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
2538 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
2549 | if (reset) |
2539 | if (reset) |
2550 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2540 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2551 | else |
2541 | else |
2552 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2542 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2553 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
2543 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
2554 | 2544 | ||
2555 | if (crtc->config->lane_count > 2) { |
2545 | if (crtc->config->lane_count > 2) { |
2556 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
2546 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
2557 | if (reset) |
2547 | if (reset) |
2558 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2548 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2559 | else |
2549 | else |
2560 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2550 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2561 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
2551 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
2562 | } |
2552 | } |
2563 | 2553 | ||
2564 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
2554 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
2565 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2555 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2566 | if (reset) |
2556 | if (reset) |
2567 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2557 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2568 | else |
2558 | else |
2569 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2559 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2570 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
2560 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
2571 | 2561 | ||
2572 | if (crtc->config->lane_count > 2) { |
2562 | if (crtc->config->lane_count > 2) { |
2573 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
2563 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
2574 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2564 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2575 | if (reset) |
2565 | if (reset) |
2576 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2566 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2577 | else |
2567 | else |
2578 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2568 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2579 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
2569 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
2580 | } |
2570 | } |
2581 | } |
2571 | } |
2582 | 2572 | ||
2583 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
2573 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
2584 | { |
2574 | { |
2585 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2575 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2586 | struct drm_device *dev = encoder->base.dev; |
2576 | struct drm_device *dev = encoder->base.dev; |
2587 | struct drm_i915_private *dev_priv = dev->dev_private; |
2577 | struct drm_i915_private *dev_priv = dev->dev_private; |
2588 | 2578 | ||
2589 | intel_dp_link_down(intel_dp); |
2579 | intel_dp_link_down(intel_dp); |
2590 | 2580 | ||
2591 | mutex_lock(&dev_priv->sb_lock); |
2581 | mutex_lock(&dev_priv->sb_lock); |
2592 | 2582 | ||
2593 | /* Assert data lane reset */ |
2583 | /* Assert data lane reset */ |
2594 | chv_data_lane_soft_reset(encoder, true); |
2584 | chv_data_lane_soft_reset(encoder, true); |
2595 | 2585 | ||
2596 | mutex_unlock(&dev_priv->sb_lock); |
2586 | mutex_unlock(&dev_priv->sb_lock); |
2597 | } |
2587 | } |
2598 | 2588 | ||
2599 | static void |
2589 | static void |
2600 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
2590 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
2601 | uint32_t *DP, |
2591 | uint32_t *DP, |
2602 | uint8_t dp_train_pat) |
2592 | uint8_t dp_train_pat) |
2603 | { |
2593 | { |
2604 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2594 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2605 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2595 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2606 | struct drm_i915_private *dev_priv = dev->dev_private; |
2596 | struct drm_i915_private *dev_priv = dev->dev_private; |
2607 | enum port port = intel_dig_port->port; |
2597 | enum port port = intel_dig_port->port; |
2608 | 2598 | ||
2609 | if (HAS_DDI(dev)) { |
2599 | if (HAS_DDI(dev)) { |
2610 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2600 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2611 | 2601 | ||
2612 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
2602 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
2613 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
2603 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
2614 | else |
2604 | else |
2615 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
2605 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
2616 | 2606 | ||
2617 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
2607 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
2618 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2608 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2619 | case DP_TRAINING_PATTERN_DISABLE: |
2609 | case DP_TRAINING_PATTERN_DISABLE: |
2620 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2610 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2621 | 2611 | ||
2622 | break; |
2612 | break; |
2623 | case DP_TRAINING_PATTERN_1: |
2613 | case DP_TRAINING_PATTERN_1: |
2624 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
2614 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
2625 | break; |
2615 | break; |
2626 | case DP_TRAINING_PATTERN_2: |
2616 | case DP_TRAINING_PATTERN_2: |
2627 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
2617 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
2628 | break; |
2618 | break; |
2629 | case DP_TRAINING_PATTERN_3: |
2619 | case DP_TRAINING_PATTERN_3: |
2630 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
2620 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
2631 | break; |
2621 | break; |
2632 | } |
2622 | } |
2633 | I915_WRITE(DP_TP_CTL(port), temp); |
2623 | I915_WRITE(DP_TP_CTL(port), temp); |
2634 | 2624 | ||
2635 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
2625 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
2636 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
2626 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
2637 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2627 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2638 | 2628 | ||
2639 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2629 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2640 | case DP_TRAINING_PATTERN_DISABLE: |
2630 | case DP_TRAINING_PATTERN_DISABLE: |
2641 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
2631 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
2642 | break; |
2632 | break; |
2643 | case DP_TRAINING_PATTERN_1: |
2633 | case DP_TRAINING_PATTERN_1: |
2644 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
2634 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
2645 | break; |
2635 | break; |
2646 | case DP_TRAINING_PATTERN_2: |
2636 | case DP_TRAINING_PATTERN_2: |
2647 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2637 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2648 | break; |
2638 | break; |
2649 | case DP_TRAINING_PATTERN_3: |
2639 | case DP_TRAINING_PATTERN_3: |
2650 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2640 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2651 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2641 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2652 | break; |
2642 | break; |
2653 | } |
2643 | } |
2654 | 2644 | ||
2655 | } else { |
2645 | } else { |
2656 | if (IS_CHERRYVIEW(dev)) |
2646 | if (IS_CHERRYVIEW(dev)) |
2657 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2647 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2658 | else |
2648 | else |
2659 | *DP &= ~DP_LINK_TRAIN_MASK; |
2649 | *DP &= ~DP_LINK_TRAIN_MASK; |
2660 | 2650 | ||
2661 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2651 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2662 | case DP_TRAINING_PATTERN_DISABLE: |
2652 | case DP_TRAINING_PATTERN_DISABLE: |
2663 | *DP |= DP_LINK_TRAIN_OFF; |
2653 | *DP |= DP_LINK_TRAIN_OFF; |
2664 | break; |
2654 | break; |
2665 | case DP_TRAINING_PATTERN_1: |
2655 | case DP_TRAINING_PATTERN_1: |
2666 | *DP |= DP_LINK_TRAIN_PAT_1; |
2656 | *DP |= DP_LINK_TRAIN_PAT_1; |
2667 | break; |
2657 | break; |
2668 | case DP_TRAINING_PATTERN_2: |
2658 | case DP_TRAINING_PATTERN_2: |
2669 | *DP |= DP_LINK_TRAIN_PAT_2; |
2659 | *DP |= DP_LINK_TRAIN_PAT_2; |
2670 | break; |
2660 | break; |
2671 | case DP_TRAINING_PATTERN_3: |
2661 | case DP_TRAINING_PATTERN_3: |
2672 | if (IS_CHERRYVIEW(dev)) { |
2662 | if (IS_CHERRYVIEW(dev)) { |
2673 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2663 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2674 | } else { |
2664 | } else { |
2675 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2665 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2676 | *DP |= DP_LINK_TRAIN_PAT_2; |
2666 | *DP |= DP_LINK_TRAIN_PAT_2; |
2677 | } |
2667 | } |
2678 | break; |
2668 | break; |
2679 | } |
2669 | } |
2680 | } |
2670 | } |
2681 | } |
2671 | } |
2682 | 2672 | ||
2683 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
2673 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
2684 | { |
2674 | { |
2685 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2675 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2686 | struct drm_i915_private *dev_priv = dev->dev_private; |
2676 | struct drm_i915_private *dev_priv = dev->dev_private; |
2687 | struct intel_crtc *crtc = |
2677 | struct intel_crtc *crtc = |
2688 | to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); |
2678 | to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); |
2689 | 2679 | ||
2690 | /* enable with pattern 1 (as per spec) */ |
2680 | /* enable with pattern 1 (as per spec) */ |
2691 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
2681 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
2692 | DP_TRAINING_PATTERN_1); |
2682 | DP_TRAINING_PATTERN_1); |
2693 | 2683 | ||
2694 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2684 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2695 | POSTING_READ(intel_dp->output_reg); |
2685 | POSTING_READ(intel_dp->output_reg); |
2696 | 2686 | ||
2697 | /* |
2687 | /* |
2698 | * Magic for VLV/CHV. We _must_ first set up the register |
2688 | * Magic for VLV/CHV. We _must_ first set up the register |
2699 | * without actually enabling the port, and then do another |
2689 | * without actually enabling the port, and then do another |
2700 | * write to enable the port. Otherwise link training will |
2690 | * write to enable the port. Otherwise link training will |
2701 | * fail when the power sequencer is freshly used for this port. |
2691 | * fail when the power sequencer is freshly used for this port. |
2702 | */ |
2692 | */ |
2703 | intel_dp->DP |= DP_PORT_EN; |
2693 | intel_dp->DP |= DP_PORT_EN; |
2704 | if (crtc->config->has_audio) |
2694 | if (crtc->config->has_audio) |
2705 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
2695 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
2706 | 2696 | ||
2707 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2697 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2708 | POSTING_READ(intel_dp->output_reg); |
2698 | POSTING_READ(intel_dp->output_reg); |
2709 | } |
2699 | } |
2710 | 2700 | ||
2711 | static void intel_enable_dp(struct intel_encoder *encoder) |
2701 | static void intel_enable_dp(struct intel_encoder *encoder) |
2712 | { |
2702 | { |
2713 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2703 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2714 | struct drm_device *dev = encoder->base.dev; |
2704 | struct drm_device *dev = encoder->base.dev; |
2715 | struct drm_i915_private *dev_priv = dev->dev_private; |
2705 | struct drm_i915_private *dev_priv = dev->dev_private; |
2716 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2706 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2717 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
2707 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
2718 | enum port port = dp_to_dig_port(intel_dp)->port; |
2708 | enum port port = dp_to_dig_port(intel_dp)->port; |
2719 | enum pipe pipe = crtc->pipe; |
2709 | enum pipe pipe = crtc->pipe; |
2720 | 2710 | ||
2721 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2711 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2722 | return; |
2712 | return; |
2723 | 2713 | ||
2724 | pps_lock(intel_dp); |
2714 | pps_lock(intel_dp); |
2725 | 2715 | ||
2726 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
2716 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
2727 | vlv_init_panel_power_sequencer(intel_dp); |
2717 | vlv_init_panel_power_sequencer(intel_dp); |
2728 | 2718 | ||
2729 | /* |
2719 | /* |
2730 | * We get an occasional spurious underrun between the port |
2720 | * We get an occasional spurious underrun between the port |
2731 | * enable and vdd enable, when enabling port A eDP. |
2721 | * enable and vdd enable, when enabling port A eDP. |
2732 | * |
2722 | * |
2733 | * FIXME: Not sure if this applies to (PCH) port D eDP as well |
2723 | * FIXME: Not sure if this applies to (PCH) port D eDP as well |
2734 | */ |
2724 | */ |
2735 | if (port == PORT_A) |
2725 | if (port == PORT_A) |
2736 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
2726 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
2737 | 2727 | ||
2738 | intel_dp_enable_port(intel_dp); |
2728 | intel_dp_enable_port(intel_dp); |
2739 | 2729 | ||
2740 | if (port == PORT_A && IS_GEN5(dev_priv)) { |
2730 | if (port == PORT_A && IS_GEN5(dev_priv)) { |
2741 | /* |
2731 | /* |
2742 | * Underrun reporting for the other pipe was disabled in |
2732 | * Underrun reporting for the other pipe was disabled in |
2743 | * g4x_pre_enable_dp(). The eDP PLL and port have now been |
2733 | * g4x_pre_enable_dp(). The eDP PLL and port have now been |
2744 | * enabled, so it's now safe to re-enable underrun reporting. |
2734 | * enabled, so it's now safe to re-enable underrun reporting. |
2745 | */ |
2735 | */ |
2746 | intel_wait_for_vblank_if_active(dev_priv->dev, !pipe); |
2736 | intel_wait_for_vblank_if_active(dev_priv->dev, !pipe); |
2747 | intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true); |
2737 | intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true); |
2748 | intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true); |
2738 | intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true); |
2749 | } |
2739 | } |
2750 | 2740 | ||
2751 | edp_panel_vdd_on(intel_dp); |
2741 | edp_panel_vdd_on(intel_dp); |
2752 | edp_panel_on(intel_dp); |
2742 | edp_panel_on(intel_dp); |
2753 | edp_panel_vdd_off(intel_dp, true); |
2743 | edp_panel_vdd_off(intel_dp, true); |
2754 | 2744 | ||
2755 | if (port == PORT_A) |
2745 | if (port == PORT_A) |
2756 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
2746 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
2757 | 2747 | ||
2758 | pps_unlock(intel_dp); |
2748 | pps_unlock(intel_dp); |
2759 | 2749 | ||
2760 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
2750 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
2761 | unsigned int lane_mask = 0x0; |
2751 | unsigned int lane_mask = 0x0; |
2762 | 2752 | ||
2763 | if (IS_CHERRYVIEW(dev)) |
2753 | if (IS_CHERRYVIEW(dev)) |
2764 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); |
2754 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); |
2765 | 2755 | ||
2766 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2756 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2767 | lane_mask); |
2757 | lane_mask); |
2768 | } |
2758 | } |
2769 | 2759 | ||
2770 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2760 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2771 | intel_dp_start_link_train(intel_dp); |
2761 | intel_dp_start_link_train(intel_dp); |
2772 | intel_dp_stop_link_train(intel_dp); |
2762 | intel_dp_stop_link_train(intel_dp); |
2773 | 2763 | ||
2774 | if (crtc->config->has_audio) { |
2764 | if (crtc->config->has_audio) { |
2775 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
2765 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
2776 | pipe_name(pipe)); |
2766 | pipe_name(pipe)); |
2777 | intel_audio_codec_enable(encoder); |
2767 | intel_audio_codec_enable(encoder); |
2778 | } |
2768 | } |
2779 | } |
2769 | } |
2780 | 2770 | ||
2781 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2771 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2782 | { |
2772 | { |
2783 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2773 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2784 | 2774 | ||
2785 | intel_enable_dp(encoder); |
2775 | intel_enable_dp(encoder); |
2786 | intel_edp_backlight_on(intel_dp); |
2776 | intel_edp_backlight_on(intel_dp); |
2787 | } |
2777 | } |
2788 | 2778 | ||
2789 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2779 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2790 | { |
2780 | { |
2791 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2781 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2792 | 2782 | ||
2793 | intel_edp_backlight_on(intel_dp); |
2783 | intel_edp_backlight_on(intel_dp); |
2794 | intel_psr_enable(intel_dp); |
2784 | intel_psr_enable(intel_dp); |
2795 | } |
2785 | } |
2796 | 2786 | ||
2797 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
2787 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
2798 | { |
2788 | { |
2799 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2789 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2800 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2790 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2801 | enum port port = dp_to_dig_port(intel_dp)->port; |
2791 | enum port port = dp_to_dig_port(intel_dp)->port; |
2802 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
2792 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
2803 | 2793 | ||
2804 | intel_dp_prepare(encoder); |
2794 | intel_dp_prepare(encoder); |
2805 | 2795 | ||
2806 | if (port == PORT_A && IS_GEN5(dev_priv)) { |
2796 | if (port == PORT_A && IS_GEN5(dev_priv)) { |
2807 | /* |
2797 | /* |
2808 | * We get FIFO underruns on the other pipe when |
2798 | * We get FIFO underruns on the other pipe when |
2809 | * enabling the CPU eDP PLL, and when enabling CPU |
2799 | * enabling the CPU eDP PLL, and when enabling CPU |
2810 | * eDP port. We could potentially avoid the PLL |
2800 | * eDP port. We could potentially avoid the PLL |
2811 | * underrun with a vblank wait just prior to enabling |
2801 | * underrun with a vblank wait just prior to enabling |
2812 | * the PLL, but that doesn't appear to help the port |
2802 | * the PLL, but that doesn't appear to help the port |
2813 | * enable case. Just sweep it all under the rug. |
2803 | * enable case. Just sweep it all under the rug. |
2814 | */ |
2804 | */ |
2815 | intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false); |
2805 | intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false); |
2816 | intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false); |
2806 | intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false); |
2817 | } |
2807 | } |
2818 | 2808 | ||
2819 | /* Only ilk+ has port A */ |
2809 | /* Only ilk+ has port A */ |
2820 | if (port == PORT_A) |
2810 | if (port == PORT_A) |
2821 | ironlake_edp_pll_on(intel_dp); |
2811 | ironlake_edp_pll_on(intel_dp); |
2822 | } |
2812 | } |
2823 | 2813 | ||
2824 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2814 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2825 | { |
2815 | { |
2826 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2816 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2827 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; |
2817 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; |
2828 | enum pipe pipe = intel_dp->pps_pipe; |
2818 | enum pipe pipe = intel_dp->pps_pipe; |
2829 | i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
2819 | i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
2830 | 2820 | ||
2831 | edp_panel_vdd_off_sync(intel_dp); |
2821 | edp_panel_vdd_off_sync(intel_dp); |
2832 | 2822 | ||
2833 | /* |
2823 | /* |
2834 | * VLV seems to get confused when multiple power seqeuencers |
2824 | * VLV seems to get confused when multiple power seqeuencers |
2835 | * have the same port selected (even if only one has power/vdd |
2825 | * have the same port selected (even if only one has power/vdd |
2836 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
2826 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
2837 | * CHV on the other hand doesn't seem to mind having the same port |
2827 | * CHV on the other hand doesn't seem to mind having the same port |
2838 | * selected in multiple power seqeuencers, but let's clear the |
2828 | * selected in multiple power seqeuencers, but let's clear the |
2839 | * port select always when logically disconnecting a power sequencer |
2829 | * port select always when logically disconnecting a power sequencer |
2840 | * from a port. |
2830 | * from a port. |
2841 | */ |
2831 | */ |
2842 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
2832 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
2843 | pipe_name(pipe), port_name(intel_dig_port->port)); |
2833 | pipe_name(pipe), port_name(intel_dig_port->port)); |
2844 | I915_WRITE(pp_on_reg, 0); |
2834 | I915_WRITE(pp_on_reg, 0); |
2845 | POSTING_READ(pp_on_reg); |
2835 | POSTING_READ(pp_on_reg); |
2846 | 2836 | ||
2847 | intel_dp->pps_pipe = INVALID_PIPE; |
2837 | intel_dp->pps_pipe = INVALID_PIPE; |
2848 | } |
2838 | } |
2849 | 2839 | ||
2850 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2840 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2851 | enum pipe pipe) |
2841 | enum pipe pipe) |
2852 | { |
2842 | { |
2853 | struct drm_i915_private *dev_priv = dev->dev_private; |
2843 | struct drm_i915_private *dev_priv = dev->dev_private; |
2854 | struct intel_encoder *encoder; |
2844 | struct intel_encoder *encoder; |
2855 | 2845 | ||
2856 | lockdep_assert_held(&dev_priv->pps_mutex); |
2846 | lockdep_assert_held(&dev_priv->pps_mutex); |
2857 | 2847 | ||
2858 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2848 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2859 | return; |
2849 | return; |
2860 | 2850 | ||
2861 | for_each_intel_encoder(dev, encoder) { |
2851 | for_each_intel_encoder(dev, encoder) { |
2862 | struct intel_dp *intel_dp; |
2852 | struct intel_dp *intel_dp; |
2863 | enum port port; |
2853 | enum port port; |
2864 | 2854 | ||
2865 | if (encoder->type != INTEL_OUTPUT_EDP) |
2855 | if (encoder->type != INTEL_OUTPUT_EDP) |
2866 | continue; |
2856 | continue; |
2867 | 2857 | ||
2868 | intel_dp = enc_to_intel_dp(&encoder->base); |
2858 | intel_dp = enc_to_intel_dp(&encoder->base); |
2869 | port = dp_to_dig_port(intel_dp)->port; |
2859 | port = dp_to_dig_port(intel_dp)->port; |
2870 | 2860 | ||
2871 | if (intel_dp->pps_pipe != pipe) |
2861 | if (intel_dp->pps_pipe != pipe) |
2872 | continue; |
2862 | continue; |
2873 | 2863 | ||
2874 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
2864 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
2875 | pipe_name(pipe), port_name(port)); |
2865 | pipe_name(pipe), port_name(port)); |
2876 | 2866 | ||
2877 | WARN(encoder->base.crtc, |
2867 | WARN(encoder->base.crtc, |
2878 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2868 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2879 | pipe_name(pipe), port_name(port)); |
2869 | pipe_name(pipe), port_name(port)); |
2880 | 2870 | ||
2881 | /* make sure vdd is off before we steal it */ |
2871 | /* make sure vdd is off before we steal it */ |
2882 | vlv_detach_power_sequencer(intel_dp); |
2872 | vlv_detach_power_sequencer(intel_dp); |
2883 | } |
2873 | } |
2884 | } |
2874 | } |
2885 | 2875 | ||
2886 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
2876 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
2887 | { |
2877 | { |
2888 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2878 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2889 | struct intel_encoder *encoder = &intel_dig_port->base; |
2879 | struct intel_encoder *encoder = &intel_dig_port->base; |
2890 | struct drm_device *dev = encoder->base.dev; |
2880 | struct drm_device *dev = encoder->base.dev; |
2891 | struct drm_i915_private *dev_priv = dev->dev_private; |
2881 | struct drm_i915_private *dev_priv = dev->dev_private; |
2892 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2882 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2893 | 2883 | ||
2894 | lockdep_assert_held(&dev_priv->pps_mutex); |
2884 | lockdep_assert_held(&dev_priv->pps_mutex); |
2895 | 2885 | ||
2896 | if (!is_edp(intel_dp)) |
2886 | if (!is_edp(intel_dp)) |
2897 | return; |
2887 | return; |
2898 | 2888 | ||
2899 | if (intel_dp->pps_pipe == crtc->pipe) |
2889 | if (intel_dp->pps_pipe == crtc->pipe) |
2900 | return; |
2890 | return; |
2901 | 2891 | ||
2902 | /* |
2892 | /* |
2903 | * If another power sequencer was being used on this |
2893 | * If another power sequencer was being used on this |
2904 | * port previously make sure to turn off vdd there while |
2894 | * port previously make sure to turn off vdd there while |
2905 | * we still have control of it. |
2895 | * we still have control of it. |
2906 | */ |
2896 | */ |
2907 | if (intel_dp->pps_pipe != INVALID_PIPE) |
2897 | if (intel_dp->pps_pipe != INVALID_PIPE) |
2908 | vlv_detach_power_sequencer(intel_dp); |
2898 | vlv_detach_power_sequencer(intel_dp); |
2909 | 2899 | ||
2910 | /* |
2900 | /* |
2911 | * We may be stealing the power |
2901 | * We may be stealing the power |
2912 | * sequencer from another port. |
2902 | * sequencer from another port. |
2913 | */ |
2903 | */ |
2914 | vlv_steal_power_sequencer(dev, crtc->pipe); |
2904 | vlv_steal_power_sequencer(dev, crtc->pipe); |
2915 | 2905 | ||
2916 | /* now it's all ours */ |
2906 | /* now it's all ours */ |
2917 | intel_dp->pps_pipe = crtc->pipe; |
2907 | intel_dp->pps_pipe = crtc->pipe; |
2918 | 2908 | ||
2919 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
2909 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
2920 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
2910 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
2921 | 2911 | ||
2922 | /* init power sequencer on this pipe and port */ |
2912 | /* init power sequencer on this pipe and port */ |
2923 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2913 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2924 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
2914 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
2925 | } |
2915 | } |
2926 | 2916 | ||
2927 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
2917 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
2928 | { |
2918 | { |
2929 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2919 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2930 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2920 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2931 | struct drm_device *dev = encoder->base.dev; |
2921 | struct drm_device *dev = encoder->base.dev; |
2932 | struct drm_i915_private *dev_priv = dev->dev_private; |
2922 | struct drm_i915_private *dev_priv = dev->dev_private; |
2933 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
2923 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
2934 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2924 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2935 | int pipe = intel_crtc->pipe; |
2925 | int pipe = intel_crtc->pipe; |
2936 | u32 val; |
2926 | u32 val; |
2937 | 2927 | ||
2938 | mutex_lock(&dev_priv->sb_lock); |
2928 | mutex_lock(&dev_priv->sb_lock); |
2939 | 2929 | ||
2940 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
2930 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
2941 | val = 0; |
2931 | val = 0; |
2942 | if (pipe) |
2932 | if (pipe) |
2943 | val |= (1<<21); |
2933 | val |= (1<<21); |
2944 | else |
2934 | else |
2945 | val &= ~(1<<21); |
2935 | val &= ~(1<<21); |
2946 | val |= 0x001000c4; |
2936 | val |= 0x001000c4; |
2947 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
2937 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
2948 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
2938 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
2949 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
2939 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
2950 | 2940 | ||
2951 | mutex_unlock(&dev_priv->sb_lock); |
2941 | mutex_unlock(&dev_priv->sb_lock); |
2952 | 2942 | ||
2953 | intel_enable_dp(encoder); |
2943 | intel_enable_dp(encoder); |
2954 | } |
2944 | } |
2955 | 2945 | ||
2956 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2946 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2957 | { |
2947 | { |
2958 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
2948 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
2959 | struct drm_device *dev = encoder->base.dev; |
2949 | struct drm_device *dev = encoder->base.dev; |
2960 | struct drm_i915_private *dev_priv = dev->dev_private; |
2950 | struct drm_i915_private *dev_priv = dev->dev_private; |
2961 | struct intel_crtc *intel_crtc = |
2951 | struct intel_crtc *intel_crtc = |
2962 | to_intel_crtc(encoder->base.crtc); |
2952 | to_intel_crtc(encoder->base.crtc); |
2963 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2953 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2964 | int pipe = intel_crtc->pipe; |
2954 | int pipe = intel_crtc->pipe; |
2965 | 2955 | ||
2966 | intel_dp_prepare(encoder); |
2956 | intel_dp_prepare(encoder); |
2967 | 2957 | ||
2968 | /* Program Tx lane resets to default */ |
2958 | /* Program Tx lane resets to default */ |
2969 | mutex_lock(&dev_priv->sb_lock); |
2959 | mutex_lock(&dev_priv->sb_lock); |
2970 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
2960 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
2971 | DPIO_PCS_TX_LANE2_RESET | |
2961 | DPIO_PCS_TX_LANE2_RESET | |
2972 | DPIO_PCS_TX_LANE1_RESET); |
2962 | DPIO_PCS_TX_LANE1_RESET); |
2973 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
2963 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
2974 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2964 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2975 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
2965 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
2976 | (1< |
2966 | (1< |
2977 | DPIO_PCS_CLK_SOFT_RESET); |
2967 | DPIO_PCS_CLK_SOFT_RESET); |
2978 | 2968 | ||
2979 | /* Fix up inter-pair skew failure */ |
2969 | /* Fix up inter-pair skew failure */ |
2980 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2970 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2981 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
2971 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
2982 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
2972 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
2983 | mutex_unlock(&dev_priv->sb_lock); |
2973 | mutex_unlock(&dev_priv->sb_lock); |
2984 | } |
2974 | } |
2985 | 2975 | ||
2986 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2976 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2987 | { |
2977 | { |
2988 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2978 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2989 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2979 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2990 | struct drm_device *dev = encoder->base.dev; |
2980 | struct drm_device *dev = encoder->base.dev; |
2991 | struct drm_i915_private *dev_priv = dev->dev_private; |
2981 | struct drm_i915_private *dev_priv = dev->dev_private; |
2992 | struct intel_crtc *intel_crtc = |
2982 | struct intel_crtc *intel_crtc = |
2993 | to_intel_crtc(encoder->base.crtc); |
2983 | to_intel_crtc(encoder->base.crtc); |
2994 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2984 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2995 | int pipe = intel_crtc->pipe; |
2985 | int pipe = intel_crtc->pipe; |
2996 | int data, i, stagger; |
2986 | int data, i, stagger; |
2997 | u32 val; |
2987 | u32 val; |
2998 | 2988 | ||
2999 | mutex_lock(&dev_priv->sb_lock); |
2989 | mutex_lock(&dev_priv->sb_lock); |
3000 | 2990 | ||
3001 | /* allow hardware to manage TX FIFO reset source */ |
2991 | /* allow hardware to manage TX FIFO reset source */ |
3002 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
2992 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
3003 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
2993 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
3004 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
2994 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
3005 | 2995 | ||
3006 | if (intel_crtc->config->lane_count > 2) { |
2996 | if (intel_crtc->config->lane_count > 2) { |
3007 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
2997 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
3008 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
2998 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
3009 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
2999 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
3010 | } |
3000 | } |
3011 | 3001 | ||
3012 | /* Program Tx lane latency optimal setting*/ |
3002 | /* Program Tx lane latency optimal setting*/ |
3013 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3003 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3014 | /* Set the upar bit */ |
3004 | /* Set the upar bit */ |
3015 | if (intel_crtc->config->lane_count == 1) |
3005 | if (intel_crtc->config->lane_count == 1) |
3016 | data = 0x0; |
3006 | data = 0x0; |
3017 | else |
3007 | else |
3018 | data = (i == 1) ? 0x0 : 0x1; |
3008 | data = (i == 1) ? 0x0 : 0x1; |
3019 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
3009 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
3020 | data << DPIO_UPAR_SHIFT); |
3010 | data << DPIO_UPAR_SHIFT); |
3021 | } |
3011 | } |
3022 | 3012 | ||
3023 | /* Data lane stagger programming */ |
3013 | /* Data lane stagger programming */ |
3024 | if (intel_crtc->config->port_clock > 270000) |
3014 | if (intel_crtc->config->port_clock > 270000) |
3025 | stagger = 0x18; |
3015 | stagger = 0x18; |
3026 | else if (intel_crtc->config->port_clock > 135000) |
3016 | else if (intel_crtc->config->port_clock > 135000) |
3027 | stagger = 0xd; |
3017 | stagger = 0xd; |
3028 | else if (intel_crtc->config->port_clock > 67500) |
3018 | else if (intel_crtc->config->port_clock > 67500) |
3029 | stagger = 0x7; |
3019 | stagger = 0x7; |
3030 | else if (intel_crtc->config->port_clock > 33750) |
3020 | else if (intel_crtc->config->port_clock > 33750) |
3031 | stagger = 0x4; |
3021 | stagger = 0x4; |
3032 | else |
3022 | else |
3033 | stagger = 0x2; |
3023 | stagger = 0x2; |
3034 | 3024 | ||
3035 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
3025 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
3036 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
3026 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
3037 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
3027 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
3038 | 3028 | ||
3039 | if (intel_crtc->config->lane_count > 2) { |
3029 | if (intel_crtc->config->lane_count > 2) { |
3040 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
3030 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
3041 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
3031 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
3042 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
3032 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
3043 | } |
3033 | } |
3044 | 3034 | ||
3045 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
3035 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
3046 | DPIO_LANESTAGGER_STRAP(stagger) | |
3036 | DPIO_LANESTAGGER_STRAP(stagger) | |
3047 | DPIO_LANESTAGGER_STRAP_OVRD | |
3037 | DPIO_LANESTAGGER_STRAP_OVRD | |
3048 | DPIO_TX1_STAGGER_MASK(0x1f) | |
3038 | DPIO_TX1_STAGGER_MASK(0x1f) | |
3049 | DPIO_TX1_STAGGER_MULT(6) | |
3039 | DPIO_TX1_STAGGER_MULT(6) | |
3050 | DPIO_TX2_STAGGER_MULT(0)); |
3040 | DPIO_TX2_STAGGER_MULT(0)); |
3051 | 3041 | ||
3052 | if (intel_crtc->config->lane_count > 2) { |
3042 | if (intel_crtc->config->lane_count > 2) { |
3053 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
3043 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
3054 | DPIO_LANESTAGGER_STRAP(stagger) | |
3044 | DPIO_LANESTAGGER_STRAP(stagger) | |
3055 | DPIO_LANESTAGGER_STRAP_OVRD | |
3045 | DPIO_LANESTAGGER_STRAP_OVRD | |
3056 | DPIO_TX1_STAGGER_MASK(0x1f) | |
3046 | DPIO_TX1_STAGGER_MASK(0x1f) | |
3057 | DPIO_TX1_STAGGER_MULT(7) | |
3047 | DPIO_TX1_STAGGER_MULT(7) | |
3058 | DPIO_TX2_STAGGER_MULT(5)); |
3048 | DPIO_TX2_STAGGER_MULT(5)); |
3059 | } |
3049 | } |
3060 | 3050 | ||
3061 | /* Deassert data lane reset */ |
3051 | /* Deassert data lane reset */ |
3062 | chv_data_lane_soft_reset(encoder, false); |
3052 | chv_data_lane_soft_reset(encoder, false); |
3063 | 3053 | ||
3064 | mutex_unlock(&dev_priv->sb_lock); |
3054 | mutex_unlock(&dev_priv->sb_lock); |
3065 | 3055 | ||
3066 | intel_enable_dp(encoder); |
3056 | intel_enable_dp(encoder); |
3067 | 3057 | ||
3068 | /* Second common lane will stay alive on its own now */ |
3058 | /* Second common lane will stay alive on its own now */ |
3069 | if (dport->release_cl2_override) { |
3059 | if (dport->release_cl2_override) { |
3070 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
3060 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
3071 | dport->release_cl2_override = false; |
3061 | dport->release_cl2_override = false; |
3072 | } |
3062 | } |
3073 | } |
3063 | } |
3074 | 3064 | ||
3075 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
3065 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
3076 | { |
3066 | { |
3077 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
3067 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
3078 | struct drm_device *dev = encoder->base.dev; |
3068 | struct drm_device *dev = encoder->base.dev; |
3079 | struct drm_i915_private *dev_priv = dev->dev_private; |
3069 | struct drm_i915_private *dev_priv = dev->dev_private; |
3080 | struct intel_crtc *intel_crtc = |
3070 | struct intel_crtc *intel_crtc = |
3081 | to_intel_crtc(encoder->base.crtc); |
3071 | to_intel_crtc(encoder->base.crtc); |
3082 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
3072 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
3083 | enum pipe pipe = intel_crtc->pipe; |
3073 | enum pipe pipe = intel_crtc->pipe; |
3084 | unsigned int lane_mask = |
3074 | unsigned int lane_mask = |
3085 | intel_dp_unused_lane_mask(intel_crtc->config->lane_count); |
3075 | intel_dp_unused_lane_mask(intel_crtc->config->lane_count); |
3086 | u32 val; |
3076 | u32 val; |
3087 | 3077 | ||
3088 | intel_dp_prepare(encoder); |
3078 | intel_dp_prepare(encoder); |
3089 | 3079 | ||
3090 | /* |
3080 | /* |
3091 | * Must trick the second common lane into life. |
3081 | * Must trick the second common lane into life. |
3092 | * Otherwise we can't even access the PLL. |
3082 | * Otherwise we can't even access the PLL. |
3093 | */ |
3083 | */ |
3094 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
3084 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
3095 | dport->release_cl2_override = |
3085 | dport->release_cl2_override = |
3096 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
3086 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
3097 | 3087 | ||
3098 | chv_phy_powergate_lanes(encoder, true, lane_mask); |
3088 | chv_phy_powergate_lanes(encoder, true, lane_mask); |
3099 | 3089 | ||
3100 | mutex_lock(&dev_priv->sb_lock); |
3090 | mutex_lock(&dev_priv->sb_lock); |
3101 | 3091 | ||
3102 | /* Assert data lane reset */ |
3092 | /* Assert data lane reset */ |
3103 | chv_data_lane_soft_reset(encoder, true); |
3093 | chv_data_lane_soft_reset(encoder, true); |
3104 | 3094 | ||
3105 | /* program left/right clock distribution */ |
3095 | /* program left/right clock distribution */ |
3106 | if (pipe != PIPE_B) { |
3096 | if (pipe != PIPE_B) { |
3107 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
3097 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
3108 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
3098 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
3109 | if (ch == DPIO_CH0) |
3099 | if (ch == DPIO_CH0) |
3110 | val |= CHV_BUFLEFTENA1_FORCE; |
3100 | val |= CHV_BUFLEFTENA1_FORCE; |
3111 | if (ch == DPIO_CH1) |
3101 | if (ch == DPIO_CH1) |
3112 | val |= CHV_BUFRIGHTENA1_FORCE; |
3102 | val |= CHV_BUFRIGHTENA1_FORCE; |
3113 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
3103 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
3114 | } else { |
3104 | } else { |
3115 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
3105 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
3116 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
3106 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
3117 | if (ch == DPIO_CH0) |
3107 | if (ch == DPIO_CH0) |
3118 | val |= CHV_BUFLEFTENA2_FORCE; |
3108 | val |= CHV_BUFLEFTENA2_FORCE; |
3119 | if (ch == DPIO_CH1) |
3109 | if (ch == DPIO_CH1) |
3120 | val |= CHV_BUFRIGHTENA2_FORCE; |
3110 | val |= CHV_BUFRIGHTENA2_FORCE; |
3121 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
3111 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
3122 | } |
3112 | } |
3123 | 3113 | ||
3124 | /* program clock channel usage */ |
3114 | /* program clock channel usage */ |
3125 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
3115 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
3126 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
3116 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
3127 | if (pipe != PIPE_B) |
3117 | if (pipe != PIPE_B) |
3128 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
3118 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
3129 | else |
3119 | else |
3130 | val |= CHV_PCS_USEDCLKCHANNEL; |
3120 | val |= CHV_PCS_USEDCLKCHANNEL; |
3131 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
3121 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
3132 | 3122 | ||
3133 | if (intel_crtc->config->lane_count > 2) { |
3123 | if (intel_crtc->config->lane_count > 2) { |
3134 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
3124 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
3135 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
3125 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
3136 | if (pipe != PIPE_B) |
3126 | if (pipe != PIPE_B) |
3137 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
3127 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
3138 | else |
3128 | else |
3139 | val |= CHV_PCS_USEDCLKCHANNEL; |
3129 | val |= CHV_PCS_USEDCLKCHANNEL; |
3140 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
3130 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
3141 | } |
3131 | } |
3142 | 3132 | ||
3143 | /* |
3133 | /* |
3144 | * This a a bit weird since generally CL |
3134 | * This a a bit weird since generally CL |
3145 | * matches the pipe, but here we need to |
3135 | * matches the pipe, but here we need to |
3146 | * pick the CL based on the port. |
3136 | * pick the CL based on the port. |
3147 | */ |
3137 | */ |
3148 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
3138 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
3149 | if (pipe != PIPE_B) |
3139 | if (pipe != PIPE_B) |
3150 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
3140 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
3151 | else |
3141 | else |
3152 | val |= CHV_CMN_USEDCLKCHANNEL; |
3142 | val |= CHV_CMN_USEDCLKCHANNEL; |
3153 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
3143 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
3154 | 3144 | ||
3155 | mutex_unlock(&dev_priv->sb_lock); |
3145 | mutex_unlock(&dev_priv->sb_lock); |
3156 | } |
3146 | } |
3157 | 3147 | ||
3158 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
3148 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
3159 | { |
3149 | { |
3160 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3150 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3161 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
3151 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
3162 | u32 val; |
3152 | u32 val; |
3163 | 3153 | ||
3164 | mutex_lock(&dev_priv->sb_lock); |
3154 | mutex_lock(&dev_priv->sb_lock); |
3165 | 3155 | ||
3166 | /* disable left/right clock distribution */ |
3156 | /* disable left/right clock distribution */ |
3167 | if (pipe != PIPE_B) { |
3157 | if (pipe != PIPE_B) { |
3168 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
3158 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
3169 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
3159 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
3170 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
3160 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
3171 | } else { |
3161 | } else { |
3172 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
3162 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
3173 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
3163 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
3174 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
3164 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
3175 | } |
3165 | } |
3176 | 3166 | ||
3177 | mutex_unlock(&dev_priv->sb_lock); |
3167 | mutex_unlock(&dev_priv->sb_lock); |
3178 | 3168 | ||
3179 | /* |
3169 | /* |
3180 | * Leave the power down bit cleared for at least one |
3170 | * Leave the power down bit cleared for at least one |
3181 | * lane so that chv_powergate_phy_ch() will power |
3171 | * lane so that chv_powergate_phy_ch() will power |
3182 | * on something when the channel is otherwise unused. |
3172 | * on something when the channel is otherwise unused. |
3183 | * When the port is off and the override is removed |
3173 | * When the port is off and the override is removed |
3184 | * the lanes power down anyway, so otherwise it doesn't |
3174 | * the lanes power down anyway, so otherwise it doesn't |
3185 | * really matter what the state of power down bits is |
3175 | * really matter what the state of power down bits is |
3186 | * after this. |
3176 | * after this. |
3187 | */ |
3177 | */ |
3188 | chv_phy_powergate_lanes(encoder, false, 0x0); |
3178 | chv_phy_powergate_lanes(encoder, false, 0x0); |
3189 | } |
3179 | } |
3190 | 3180 | ||
3191 | /* |
3181 | /* |
3192 | * Native read with retry for link status and receiver capability reads for |
3182 | * Native read with retry for link status and receiver capability reads for |
3193 | * cases where the sink may still be asleep. |
3183 | * cases where the sink may still be asleep. |
3194 | * |
3184 | * |
3195 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
3185 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
3196 | * supposed to retry 3 times per the spec. |
3186 | * supposed to retry 3 times per the spec. |
3197 | */ |
3187 | */ |
3198 | static ssize_t |
3188 | static ssize_t |
3199 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
3189 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
3200 | void *buffer, size_t size) |
3190 | void *buffer, size_t size) |
3201 | { |
3191 | { |
3202 | ssize_t ret; |
3192 | ssize_t ret; |
3203 | int i; |
3193 | int i; |
3204 | 3194 | ||
3205 | /* |
3195 | /* |
3206 | * Sometime we just get the same incorrect byte repeated |
3196 | * Sometime we just get the same incorrect byte repeated |
3207 | * over the entire buffer. Doing just one throw away read |
3197 | * over the entire buffer. Doing just one throw away read |
3208 | * initially seems to "solve" it. |
3198 | * initially seems to "solve" it. |
3209 | */ |
3199 | */ |
3210 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); |
3200 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); |
3211 | 3201 | ||
3212 | for (i = 0; i < 3; i++) { |
3202 | for (i = 0; i < 3; i++) { |
3213 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
3203 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
3214 | if (ret == size) |
3204 | if (ret == size) |
3215 | return ret; |
3205 | return ret; |
3216 | msleep(1); |
3206 | msleep(1); |
3217 | } |
3207 | } |
3218 | 3208 | ||
3219 | return ret; |
3209 | return ret; |
3220 | } |
3210 | } |
3221 | 3211 | ||
3222 | /* |
3212 | /* |
3223 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
3213 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
3224 | * link status information |
3214 | * link status information |
3225 | */ |
3215 | */ |
3226 | bool |
3216 | bool |
3227 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
3217 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
3228 | { |
3218 | { |
3229 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
3219 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
3230 | DP_LANE0_1_STATUS, |
3220 | DP_LANE0_1_STATUS, |
3231 | link_status, |
3221 | link_status, |
3232 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
3222 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
3233 | } |
3223 | } |
3234 | 3224 | ||
3235 | /* These are source-specific values. */ |
3225 | /* These are source-specific values. */ |
3236 | uint8_t |
3226 | uint8_t |
3237 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
3227 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
3238 | { |
3228 | { |
3239 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3229 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3240 | struct drm_i915_private *dev_priv = dev->dev_private; |
3230 | struct drm_i915_private *dev_priv = dev->dev_private; |
3241 | enum port port = dp_to_dig_port(intel_dp)->port; |
3231 | enum port port = dp_to_dig_port(intel_dp)->port; |
3242 | 3232 | ||
3243 | if (IS_BROXTON(dev)) |
3233 | if (IS_BROXTON(dev)) |
3244 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3234 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3245 | else if (INTEL_INFO(dev)->gen >= 9) { |
3235 | else if (INTEL_INFO(dev)->gen >= 9) { |
3246 | if (dev_priv->edp_low_vswing && port == PORT_A) |
3236 | if (dev_priv->edp_low_vswing && port == PORT_A) |
3247 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3237 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3248 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3238 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3249 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
3239 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
3250 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3240 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3251 | else if (IS_GEN7(dev) && port == PORT_A) |
3241 | else if (IS_GEN7(dev) && port == PORT_A) |
3252 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3242 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3253 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
3243 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
3254 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3244 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3255 | else |
3245 | else |
3256 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3246 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3257 | } |
3247 | } |
3258 | 3248 | ||
3259 | uint8_t |
3249 | uint8_t |
3260 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3250 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3261 | { |
3251 | { |
3262 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3252 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3263 | enum port port = dp_to_dig_port(intel_dp)->port; |
3253 | enum port port = dp_to_dig_port(intel_dp)->port; |
3264 | 3254 | ||
3265 | if (INTEL_INFO(dev)->gen >= 9) { |
3255 | if (INTEL_INFO(dev)->gen >= 9) { |
3266 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3256 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3267 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3257 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3268 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3258 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3269 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3259 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3270 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3260 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3271 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3261 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3272 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3262 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3273 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3263 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3274 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3264 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3275 | default: |
3265 | default: |
3276 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3266 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3277 | } |
3267 | } |
3278 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3268 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3279 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3269 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3280 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3270 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3281 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3271 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3282 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3272 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3283 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3273 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3284 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3274 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3285 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3275 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3286 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3276 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3287 | default: |
3277 | default: |
3288 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3278 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3289 | } |
3279 | } |
3290 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3280 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3291 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3281 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3292 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3282 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3293 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3283 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3294 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3284 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3295 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3285 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3296 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3286 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3297 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3287 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3298 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3288 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3299 | default: |
3289 | default: |
3300 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3290 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3301 | } |
3291 | } |
3302 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3292 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3303 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3293 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3304 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3294 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3305 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3295 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3306 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3296 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3307 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3297 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3308 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3298 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3309 | default: |
3299 | default: |
3310 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3300 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3311 | } |
3301 | } |
3312 | } else { |
3302 | } else { |
3313 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3303 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3314 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3304 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3315 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3305 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3316 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3306 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3317 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3307 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3318 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3308 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3319 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3309 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3320 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3310 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3321 | default: |
3311 | default: |
3322 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3312 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3323 | } |
3313 | } |
3324 | } |
3314 | } |
3325 | } |
3315 | } |
3326 | 3316 | ||
3327 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
3317 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
3328 | { |
3318 | { |
3329 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3319 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3330 | struct drm_i915_private *dev_priv = dev->dev_private; |
3320 | struct drm_i915_private *dev_priv = dev->dev_private; |
3331 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3321 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3332 | struct intel_crtc *intel_crtc = |
3322 | struct intel_crtc *intel_crtc = |
3333 | to_intel_crtc(dport->base.base.crtc); |
3323 | to_intel_crtc(dport->base.base.crtc); |
3334 | unsigned long demph_reg_value, preemph_reg_value, |
3324 | unsigned long demph_reg_value, preemph_reg_value, |
3335 | uniqtranscale_reg_value; |
3325 | uniqtranscale_reg_value; |
3336 | uint8_t train_set = intel_dp->train_set[0]; |
3326 | uint8_t train_set = intel_dp->train_set[0]; |
3337 | enum dpio_channel port = vlv_dport_to_channel(dport); |
3327 | enum dpio_channel port = vlv_dport_to_channel(dport); |
3338 | int pipe = intel_crtc->pipe; |
3328 | int pipe = intel_crtc->pipe; |
3339 | 3329 | ||
3340 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3330 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3341 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3331 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3342 | preemph_reg_value = 0x0004000; |
3332 | preemph_reg_value = 0x0004000; |
3343 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3333 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3344 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3334 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3345 | demph_reg_value = 0x2B405555; |
3335 | demph_reg_value = 0x2B405555; |
3346 | uniqtranscale_reg_value = 0x552AB83A; |
3336 | uniqtranscale_reg_value = 0x552AB83A; |
3347 | break; |
3337 | break; |
3348 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3338 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3349 | demph_reg_value = 0x2B404040; |
3339 | demph_reg_value = 0x2B404040; |
3350 | uniqtranscale_reg_value = 0x5548B83A; |
3340 | uniqtranscale_reg_value = 0x5548B83A; |
3351 | break; |
3341 | break; |
3352 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3342 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3353 | demph_reg_value = 0x2B245555; |
3343 | demph_reg_value = 0x2B245555; |
3354 | uniqtranscale_reg_value = 0x5560B83A; |
3344 | uniqtranscale_reg_value = 0x5560B83A; |
3355 | break; |
3345 | break; |
3356 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3346 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3357 | demph_reg_value = 0x2B405555; |
3347 | demph_reg_value = 0x2B405555; |
3358 | uniqtranscale_reg_value = 0x5598DA3A; |
3348 | uniqtranscale_reg_value = 0x5598DA3A; |
3359 | break; |
3349 | break; |
3360 | default: |
3350 | default: |
3361 | return 0; |
3351 | return 0; |
3362 | } |
3352 | } |
3363 | break; |
3353 | break; |
3364 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3354 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3365 | preemph_reg_value = 0x0002000; |
3355 | preemph_reg_value = 0x0002000; |
3366 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3356 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3367 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3357 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3368 | demph_reg_value = 0x2B404040; |
3358 | demph_reg_value = 0x2B404040; |
3369 | uniqtranscale_reg_value = 0x5552B83A; |
3359 | uniqtranscale_reg_value = 0x5552B83A; |
3370 | break; |
3360 | break; |
3371 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3361 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3372 | demph_reg_value = 0x2B404848; |
3362 | demph_reg_value = 0x2B404848; |
3373 | uniqtranscale_reg_value = 0x5580B83A; |
3363 | uniqtranscale_reg_value = 0x5580B83A; |
3374 | break; |
3364 | break; |
3375 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3365 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3376 | demph_reg_value = 0x2B404040; |
3366 | demph_reg_value = 0x2B404040; |
3377 | uniqtranscale_reg_value = 0x55ADDA3A; |
3367 | uniqtranscale_reg_value = 0x55ADDA3A; |
3378 | break; |
3368 | break; |
3379 | default: |
3369 | default: |
3380 | return 0; |
3370 | return 0; |
3381 | } |
3371 | } |
3382 | break; |
3372 | break; |
3383 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3373 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3384 | preemph_reg_value = 0x0000000; |
3374 | preemph_reg_value = 0x0000000; |
3385 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3375 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3386 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3376 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3387 | demph_reg_value = 0x2B305555; |
3377 | demph_reg_value = 0x2B305555; |
3388 | uniqtranscale_reg_value = 0x5570B83A; |
3378 | uniqtranscale_reg_value = 0x5570B83A; |
3389 | break; |
3379 | break; |
3390 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3380 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3391 | demph_reg_value = 0x2B2B4040; |
3381 | demph_reg_value = 0x2B2B4040; |
3392 | uniqtranscale_reg_value = 0x55ADDA3A; |
3382 | uniqtranscale_reg_value = 0x55ADDA3A; |
3393 | break; |
3383 | break; |
3394 | default: |
3384 | default: |
3395 | return 0; |
3385 | return 0; |
3396 | } |
3386 | } |
3397 | break; |
3387 | break; |
3398 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3388 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3399 | preemph_reg_value = 0x0006000; |
3389 | preemph_reg_value = 0x0006000; |
3400 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3390 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3401 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3391 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3402 | demph_reg_value = 0x1B405555; |
3392 | demph_reg_value = 0x1B405555; |
3403 | uniqtranscale_reg_value = 0x55ADDA3A; |
3393 | uniqtranscale_reg_value = 0x55ADDA3A; |
3404 | break; |
3394 | break; |
3405 | default: |
3395 | default: |
3406 | return 0; |
3396 | return 0; |
3407 | } |
3397 | } |
3408 | break; |
3398 | break; |
3409 | default: |
3399 | default: |
3410 | return 0; |
3400 | return 0; |
3411 | } |
3401 | } |
3412 | 3402 | ||
3413 | mutex_lock(&dev_priv->sb_lock); |
3403 | mutex_lock(&dev_priv->sb_lock); |
3414 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
3404 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
3415 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
3405 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
3416 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
3406 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
3417 | uniqtranscale_reg_value); |
3407 | uniqtranscale_reg_value); |
3418 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
3408 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
3419 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
3409 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
3420 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
3410 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
3421 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
3411 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
3422 | mutex_unlock(&dev_priv->sb_lock); |
3412 | mutex_unlock(&dev_priv->sb_lock); |
3423 | 3413 | ||
3424 | return 0; |
3414 | return 0; |
3425 | } |
3415 | } |
3426 | 3416 | ||
3427 | static bool chv_need_uniq_trans_scale(uint8_t train_set) |
3417 | static bool chv_need_uniq_trans_scale(uint8_t train_set) |
3428 | { |
3418 | { |
3429 | return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 && |
3419 | return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 && |
3430 | (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3420 | (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3431 | } |
3421 | } |
3432 | 3422 | ||
3433 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
3423 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
3434 | { |
3424 | { |
3435 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3425 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3436 | struct drm_i915_private *dev_priv = dev->dev_private; |
3426 | struct drm_i915_private *dev_priv = dev->dev_private; |
3437 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3427 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3438 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
3428 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
3439 | u32 deemph_reg_value, margin_reg_value, val; |
3429 | u32 deemph_reg_value, margin_reg_value, val; |
3440 | uint8_t train_set = intel_dp->train_set[0]; |
3430 | uint8_t train_set = intel_dp->train_set[0]; |
3441 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
3431 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
3442 | enum pipe pipe = intel_crtc->pipe; |
3432 | enum pipe pipe = intel_crtc->pipe; |
3443 | int i; |
3433 | int i; |
3444 | 3434 | ||
3445 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3435 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3446 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3436 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3447 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3437 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3448 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3438 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3449 | deemph_reg_value = 128; |
3439 | deemph_reg_value = 128; |
3450 | margin_reg_value = 52; |
3440 | margin_reg_value = 52; |
3451 | break; |
3441 | break; |
3452 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3442 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3453 | deemph_reg_value = 128; |
3443 | deemph_reg_value = 128; |
3454 | margin_reg_value = 77; |
3444 | margin_reg_value = 77; |
3455 | break; |
3445 | break; |
3456 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3446 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3457 | deemph_reg_value = 128; |
3447 | deemph_reg_value = 128; |
3458 | margin_reg_value = 102; |
3448 | margin_reg_value = 102; |
3459 | break; |
3449 | break; |
3460 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3450 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3461 | deemph_reg_value = 128; |
3451 | deemph_reg_value = 128; |
3462 | margin_reg_value = 154; |
3452 | margin_reg_value = 154; |
3463 | /* FIXME extra to set for 1200 */ |
3453 | /* FIXME extra to set for 1200 */ |
3464 | break; |
3454 | break; |
3465 | default: |
3455 | default: |
3466 | return 0; |
3456 | return 0; |
3467 | } |
3457 | } |
3468 | break; |
3458 | break; |
3469 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3459 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3470 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3460 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3471 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3461 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3472 | deemph_reg_value = 85; |
3462 | deemph_reg_value = 85; |
3473 | margin_reg_value = 78; |
3463 | margin_reg_value = 78; |
3474 | break; |
3464 | break; |
3475 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3465 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3476 | deemph_reg_value = 85; |
3466 | deemph_reg_value = 85; |
3477 | margin_reg_value = 116; |
3467 | margin_reg_value = 116; |
3478 | break; |
3468 | break; |
3479 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3469 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3480 | deemph_reg_value = 85; |
3470 | deemph_reg_value = 85; |
3481 | margin_reg_value = 154; |
3471 | margin_reg_value = 154; |
3482 | break; |
3472 | break; |
3483 | default: |
3473 | default: |
3484 | return 0; |
3474 | return 0; |
3485 | } |
3475 | } |
3486 | break; |
3476 | break; |
3487 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3477 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3488 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3478 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3489 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3479 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3490 | deemph_reg_value = 64; |
3480 | deemph_reg_value = 64; |
3491 | margin_reg_value = 104; |
3481 | margin_reg_value = 104; |
3492 | break; |
3482 | break; |
3493 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3483 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3494 | deemph_reg_value = 64; |
3484 | deemph_reg_value = 64; |
3495 | margin_reg_value = 154; |
3485 | margin_reg_value = 154; |
3496 | break; |
3486 | break; |
3497 | default: |
3487 | default: |
3498 | return 0; |
3488 | return 0; |
3499 | } |
3489 | } |
3500 | break; |
3490 | break; |
3501 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3491 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3502 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3492 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3503 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3493 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3504 | deemph_reg_value = 43; |
3494 | deemph_reg_value = 43; |
3505 | margin_reg_value = 154; |
3495 | margin_reg_value = 154; |
3506 | break; |
3496 | break; |
3507 | default: |
3497 | default: |
3508 | return 0; |
3498 | return 0; |
3509 | } |
3499 | } |
3510 | break; |
3500 | break; |
3511 | default: |
3501 | default: |
3512 | return 0; |
3502 | return 0; |
3513 | } |
3503 | } |
3514 | 3504 | ||
3515 | mutex_lock(&dev_priv->sb_lock); |
3505 | mutex_lock(&dev_priv->sb_lock); |
3516 | 3506 | ||
3517 | /* Clear calc init */ |
3507 | /* Clear calc init */ |
3518 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3508 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3519 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3509 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3520 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3510 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3521 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3511 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3522 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3512 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3523 | 3513 | ||
3524 | if (intel_crtc->config->lane_count > 2) { |
3514 | if (intel_crtc->config->lane_count > 2) { |
3525 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3515 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3526 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3516 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3527 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3517 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3528 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3518 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3529 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3519 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3530 | } |
3520 | } |
3531 | 3521 | ||
3532 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
3522 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
3533 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3523 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3534 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3524 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3535 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
3525 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
3536 | 3526 | ||
3537 | if (intel_crtc->config->lane_count > 2) { |
3527 | if (intel_crtc->config->lane_count > 2) { |
3538 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
3528 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
3539 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3529 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3540 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3530 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3541 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
3531 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
3542 | } |
3532 | } |
3543 | 3533 | ||
3544 | /* Program swing deemph */ |
3534 | /* Program swing deemph */ |
3545 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3535 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3546 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
3536 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
3547 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
3537 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
3548 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
3538 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
3549 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
3539 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
3550 | } |
3540 | } |
3551 | 3541 | ||
3552 | /* Program swing margin */ |
3542 | /* Program swing margin */ |
3553 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3543 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3554 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
3544 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
3555 | 3545 | ||
3556 | val &= ~DPIO_SWING_MARGIN000_MASK; |
3546 | val &= ~DPIO_SWING_MARGIN000_MASK; |
3557 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; |
3547 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; |
3558 | 3548 | ||
3559 | /* |
3549 | /* |
3560 | * Supposedly this value shouldn't matter when unique transition |
3550 | * Supposedly this value shouldn't matter when unique transition |
3561 | * scale is disabled, but in fact it does matter. Let's just |
3551 | * scale is disabled, but in fact it does matter. Let's just |
3562 | * always program the same value and hope it's OK. |
3552 | * always program the same value and hope it's OK. |
3563 | */ |
3553 | */ |
3564 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
3554 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
3565 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
3555 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
3566 | 3556 | ||
3567 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
3557 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
3568 | } |
3558 | } |
3569 | 3559 | ||
3570 | /* |
3560 | /* |
3571 | * The document said it needs to set bit 27 for ch0 and bit 26 |
3561 | * The document said it needs to set bit 27 for ch0 and bit 26 |
3572 | * for ch1. Might be a typo in the doc. |
3562 | * for ch1. Might be a typo in the doc. |
3573 | * For now, for this unique transition scale selection, set bit |
3563 | * For now, for this unique transition scale selection, set bit |
3574 | * 27 for ch0 and ch1. |
3564 | * 27 for ch0 and ch1. |
3575 | */ |
3565 | */ |
3576 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3566 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3577 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
3567 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
3578 | if (chv_need_uniq_trans_scale(train_set)) |
3568 | if (chv_need_uniq_trans_scale(train_set)) |
3579 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3569 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3580 | else |
3570 | else |
3581 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3571 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3582 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
3572 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
3583 | } |
3573 | } |
3584 | 3574 | ||
3585 | /* Start swing calculation */ |
3575 | /* Start swing calculation */ |
3586 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3576 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3587 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3577 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3588 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3578 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3589 | 3579 | ||
3590 | if (intel_crtc->config->lane_count > 2) { |
3580 | if (intel_crtc->config->lane_count > 2) { |
3591 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3581 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3592 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3582 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3593 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3583 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3594 | } |
3584 | } |
3595 | 3585 | ||
3596 | mutex_unlock(&dev_priv->sb_lock); |
3586 | mutex_unlock(&dev_priv->sb_lock); |
3597 | 3587 | ||
3598 | return 0; |
3588 | return 0; |
3599 | } |
3589 | } |
3600 | 3590 | ||
3601 | static uint32_t |
3591 | static uint32_t |
3602 | gen4_signal_levels(uint8_t train_set) |
3592 | gen4_signal_levels(uint8_t train_set) |
3603 | { |
3593 | { |
3604 | uint32_t signal_levels = 0; |
3594 | uint32_t signal_levels = 0; |
3605 | 3595 | ||
3606 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3596 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3607 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3597 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3608 | default: |
3598 | default: |
3609 | signal_levels |= DP_VOLTAGE_0_4; |
3599 | signal_levels |= DP_VOLTAGE_0_4; |
3610 | break; |
3600 | break; |
3611 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3601 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3612 | signal_levels |= DP_VOLTAGE_0_6; |
3602 | signal_levels |= DP_VOLTAGE_0_6; |
3613 | break; |
3603 | break; |
3614 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3604 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3615 | signal_levels |= DP_VOLTAGE_0_8; |
3605 | signal_levels |= DP_VOLTAGE_0_8; |
3616 | break; |
3606 | break; |
3617 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3607 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3618 | signal_levels |= DP_VOLTAGE_1_2; |
3608 | signal_levels |= DP_VOLTAGE_1_2; |
3619 | break; |
3609 | break; |
3620 | } |
3610 | } |
3621 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3611 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3622 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3612 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3623 | default: |
3613 | default: |
3624 | signal_levels |= DP_PRE_EMPHASIS_0; |
3614 | signal_levels |= DP_PRE_EMPHASIS_0; |
3625 | break; |
3615 | break; |
3626 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3616 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3627 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3617 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3628 | break; |
3618 | break; |
3629 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3619 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3630 | signal_levels |= DP_PRE_EMPHASIS_6; |
3620 | signal_levels |= DP_PRE_EMPHASIS_6; |
3631 | break; |
3621 | break; |
3632 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3622 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3633 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3623 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3634 | break; |
3624 | break; |
3635 | } |
3625 | } |
3636 | return signal_levels; |
3626 | return signal_levels; |
3637 | } |
3627 | } |
3638 | 3628 | ||
3639 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3629 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3640 | static uint32_t |
3630 | static uint32_t |
3641 | gen6_edp_signal_levels(uint8_t train_set) |
3631 | gen6_edp_signal_levels(uint8_t train_set) |
3642 | { |
3632 | { |
3643 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3633 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3644 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3634 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3645 | switch (signal_levels) { |
3635 | switch (signal_levels) { |
3646 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3636 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3647 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3637 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3648 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3638 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3649 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3639 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3650 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
3640 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
3651 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3641 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3652 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3642 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3653 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
3643 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
3654 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3644 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3655 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3645 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3656 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
3646 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
3657 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3647 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3658 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3648 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3659 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
3649 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
3660 | default: |
3650 | default: |
3661 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3651 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3662 | "0x%x\n", signal_levels); |
3652 | "0x%x\n", signal_levels); |
3663 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3653 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3664 | } |
3654 | } |
3665 | } |
3655 | } |
3666 | 3656 | ||
3667 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3657 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3668 | static uint32_t |
3658 | static uint32_t |
3669 | gen7_edp_signal_levels(uint8_t train_set) |
3659 | gen7_edp_signal_levels(uint8_t train_set) |
3670 | { |
3660 | { |
3671 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3661 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3672 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3662 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3673 | switch (signal_levels) { |
3663 | switch (signal_levels) { |
3674 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3664 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3675 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
3665 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
3676 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3666 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3677 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
3667 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
3678 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3668 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3679 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3669 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3680 | 3670 | ||
3681 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3671 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3682 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
3672 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
3683 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3673 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3684 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3674 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3685 | 3675 | ||
3686 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3676 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3687 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
3677 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
3688 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3678 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3689 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3679 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3690 | 3680 | ||
3691 | default: |
3681 | default: |
3692 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3682 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3693 | "0x%x\n", signal_levels); |
3683 | "0x%x\n", signal_levels); |
3694 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
3684 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
3695 | } |
3685 | } |
3696 | } |
3686 | } |
3697 | 3687 | ||
3698 | void |
3688 | void |
3699 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
3689 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
3700 | { |
3690 | { |
3701 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3691 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3702 | enum port port = intel_dig_port->port; |
3692 | enum port port = intel_dig_port->port; |
3703 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3693 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3704 | struct drm_i915_private *dev_priv = to_i915(dev); |
3694 | struct drm_i915_private *dev_priv = to_i915(dev); |
3705 | uint32_t signal_levels, mask = 0; |
3695 | uint32_t signal_levels, mask = 0; |
3706 | uint8_t train_set = intel_dp->train_set[0]; |
3696 | uint8_t train_set = intel_dp->train_set[0]; |
3707 | 3697 | ||
3708 | if (HAS_DDI(dev)) { |
3698 | if (HAS_DDI(dev)) { |
3709 | signal_levels = ddi_signal_levels(intel_dp); |
3699 | signal_levels = ddi_signal_levels(intel_dp); |
3710 | 3700 | ||
3711 | if (IS_BROXTON(dev)) |
3701 | if (IS_BROXTON(dev)) |
3712 | signal_levels = 0; |
3702 | signal_levels = 0; |
3713 | else |
3703 | else |
3714 | mask = DDI_BUF_EMP_MASK; |
3704 | mask = DDI_BUF_EMP_MASK; |
3715 | } else if (IS_CHERRYVIEW(dev)) { |
3705 | } else if (IS_CHERRYVIEW(dev)) { |
3716 | signal_levels = chv_signal_levels(intel_dp); |
3706 | signal_levels = chv_signal_levels(intel_dp); |
3717 | } else if (IS_VALLEYVIEW(dev)) { |
3707 | } else if (IS_VALLEYVIEW(dev)) { |
3718 | signal_levels = vlv_signal_levels(intel_dp); |
3708 | signal_levels = vlv_signal_levels(intel_dp); |
3719 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3709 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3720 | signal_levels = gen7_edp_signal_levels(train_set); |
3710 | signal_levels = gen7_edp_signal_levels(train_set); |
3721 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
3711 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
3722 | } else if (IS_GEN6(dev) && port == PORT_A) { |
3712 | } else if (IS_GEN6(dev) && port == PORT_A) { |
3723 | signal_levels = gen6_edp_signal_levels(train_set); |
3713 | signal_levels = gen6_edp_signal_levels(train_set); |
3724 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3714 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3725 | } else { |
3715 | } else { |
3726 | signal_levels = gen4_signal_levels(train_set); |
3716 | signal_levels = gen4_signal_levels(train_set); |
3727 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3717 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3728 | } |
3718 | } |
3729 | 3719 | ||
3730 | if (mask) |
3720 | if (mask) |
3731 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
3721 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
3732 | 3722 | ||
3733 | DRM_DEBUG_KMS("Using vswing level %d\n", |
3723 | DRM_DEBUG_KMS("Using vswing level %d\n", |
3734 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); |
3724 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); |
3735 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", |
3725 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", |
3736 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
3726 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
3737 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
3727 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
3738 | 3728 | ||
3739 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
3729 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
3740 | 3730 | ||
3741 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
3731 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
3742 | POSTING_READ(intel_dp->output_reg); |
3732 | POSTING_READ(intel_dp->output_reg); |
3743 | } |
3733 | } |
3744 | 3734 | ||
3745 | void |
3735 | void |
3746 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3736 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3747 | uint8_t dp_train_pat) |
3737 | uint8_t dp_train_pat) |
3748 | { |
3738 | { |
3749 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3739 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3750 | struct drm_i915_private *dev_priv = |
3740 | struct drm_i915_private *dev_priv = |
3751 | to_i915(intel_dig_port->base.base.dev); |
3741 | to_i915(intel_dig_port->base.base.dev); |
3752 | 3742 | ||
3753 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
3743 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
3754 | 3744 | ||
3755 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
3745 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
3756 | POSTING_READ(intel_dp->output_reg); |
3746 | POSTING_READ(intel_dp->output_reg); |
3757 | } |
3747 | } |
3758 | 3748 | ||
3759 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3749 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3760 | { |
3750 | { |
3761 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3751 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3762 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3752 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3763 | struct drm_i915_private *dev_priv = dev->dev_private; |
3753 | struct drm_i915_private *dev_priv = dev->dev_private; |
3764 | enum port port = intel_dig_port->port; |
3754 | enum port port = intel_dig_port->port; |
3765 | uint32_t val; |
3755 | uint32_t val; |
3766 | 3756 | ||
3767 | if (!HAS_DDI(dev)) |
3757 | if (!HAS_DDI(dev)) |
3768 | return; |
3758 | return; |
3769 | 3759 | ||
3770 | val = I915_READ(DP_TP_CTL(port)); |
3760 | val = I915_READ(DP_TP_CTL(port)); |
3771 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
3761 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
3772 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
3762 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
3773 | I915_WRITE(DP_TP_CTL(port), val); |
3763 | I915_WRITE(DP_TP_CTL(port), val); |
3774 | 3764 | ||
3775 | /* |
3765 | /* |
3776 | * On PORT_A we can have only eDP in SST mode. There the only reason |
3766 | * On PORT_A we can have only eDP in SST mode. There the only reason |
3777 | * we need to set idle transmission mode is to work around a HW issue |
3767 | * we need to set idle transmission mode is to work around a HW issue |
3778 | * where we enable the pipe while not in idle link-training mode. |
3768 | * where we enable the pipe while not in idle link-training mode. |
3779 | * In this case there is requirement to wait for a minimum number of |
3769 | * In this case there is requirement to wait for a minimum number of |
3780 | * idle patterns to be sent. |
3770 | * idle patterns to be sent. |
3781 | */ |
3771 | */ |
3782 | if (port == PORT_A) |
3772 | if (port == PORT_A) |
3783 | return; |
3773 | return; |
3784 | 3774 | ||
3785 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
3775 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
3786 | 1)) |
3776 | 1)) |
3787 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3777 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3788 | } |
3778 | } |
3789 | 3779 | ||
3790 | static void |
3780 | static void |
3791 | intel_dp_link_down(struct intel_dp *intel_dp) |
3781 | intel_dp_link_down(struct intel_dp *intel_dp) |
3792 | { |
3782 | { |
3793 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3783 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3794 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
3784 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
3795 | enum port port = intel_dig_port->port; |
3785 | enum port port = intel_dig_port->port; |
3796 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3786 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3797 | struct drm_i915_private *dev_priv = dev->dev_private; |
3787 | struct drm_i915_private *dev_priv = dev->dev_private; |
3798 | uint32_t DP = intel_dp->DP; |
3788 | uint32_t DP = intel_dp->DP; |
3799 | 3789 | ||
3800 | if (WARN_ON(HAS_DDI(dev))) |
3790 | if (WARN_ON(HAS_DDI(dev))) |
3801 | return; |
3791 | return; |
3802 | 3792 | ||
3803 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
3793 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
3804 | return; |
3794 | return; |
3805 | 3795 | ||
3806 | DRM_DEBUG_KMS("\n"); |
3796 | DRM_DEBUG_KMS("\n"); |
3807 | 3797 | ||
3808 | if ((IS_GEN7(dev) && port == PORT_A) || |
3798 | if ((IS_GEN7(dev) && port == PORT_A) || |
3809 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
3799 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
3810 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3800 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3811 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
3801 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
3812 | } else { |
3802 | } else { |
3813 | if (IS_CHERRYVIEW(dev)) |
3803 | if (IS_CHERRYVIEW(dev)) |
3814 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3804 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3815 | else |
3805 | else |
3816 | DP &= ~DP_LINK_TRAIN_MASK; |
3806 | DP &= ~DP_LINK_TRAIN_MASK; |
3817 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
3807 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
3818 | } |
3808 | } |
3819 | I915_WRITE(intel_dp->output_reg, DP); |
3809 | I915_WRITE(intel_dp->output_reg, DP); |
3820 | POSTING_READ(intel_dp->output_reg); |
3810 | POSTING_READ(intel_dp->output_reg); |
3821 | 3811 | ||
3822 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3812 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3823 | I915_WRITE(intel_dp->output_reg, DP); |
3813 | I915_WRITE(intel_dp->output_reg, DP); |
3824 | POSTING_READ(intel_dp->output_reg); |
3814 | POSTING_READ(intel_dp->output_reg); |
3825 | 3815 | ||
3826 | /* |
3816 | /* |
3827 | * HW workaround for IBX, we need to move the port |
3817 | * HW workaround for IBX, we need to move the port |
3828 | * to transcoder A after disabling it to allow the |
3818 | * to transcoder A after disabling it to allow the |
3829 | * matching HDMI port to be enabled on transcoder A. |
3819 | * matching HDMI port to be enabled on transcoder A. |
3830 | */ |
3820 | */ |
3831 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { |
3821 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { |
3832 | /* |
3822 | /* |
3833 | * We get CPU/PCH FIFO underruns on the other pipe when |
3823 | * We get CPU/PCH FIFO underruns on the other pipe when |
3834 | * doing the workaround. Sweep them under the rug. |
3824 | * doing the workaround. Sweep them under the rug. |
3835 | */ |
3825 | */ |
3836 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
3826 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
3837 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
3827 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
3838 | 3828 | ||
3839 | /* always enable with pattern 1 (as per spec) */ |
3829 | /* always enable with pattern 1 (as per spec) */ |
3840 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); |
3830 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); |
3841 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; |
3831 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; |
3842 | I915_WRITE(intel_dp->output_reg, DP); |
3832 | I915_WRITE(intel_dp->output_reg, DP); |
3843 | POSTING_READ(intel_dp->output_reg); |
3833 | POSTING_READ(intel_dp->output_reg); |
3844 | 3834 | ||
3845 | DP &= ~DP_PORT_EN; |
3835 | DP &= ~DP_PORT_EN; |
3846 | I915_WRITE(intel_dp->output_reg, DP); |
3836 | I915_WRITE(intel_dp->output_reg, DP); |
3847 | POSTING_READ(intel_dp->output_reg); |
3837 | POSTING_READ(intel_dp->output_reg); |
3848 | 3838 | ||
3849 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); |
3839 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); |
3850 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3840 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3851 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3841 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3852 | } |
3842 | } |
3853 | 3843 | ||
3854 | msleep(intel_dp->panel_power_down_delay); |
3844 | msleep(intel_dp->panel_power_down_delay); |
3855 | 3845 | ||
3856 | intel_dp->DP = DP; |
3846 | intel_dp->DP = DP; |
3857 | } |
3847 | } |
3858 | 3848 | ||
3859 | static bool |
3849 | static bool |
3860 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
3850 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
3861 | { |
3851 | { |
3862 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3852 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3863 | struct drm_device *dev = dig_port->base.base.dev; |
3853 | struct drm_device *dev = dig_port->base.base.dev; |
3864 | struct drm_i915_private *dev_priv = dev->dev_private; |
3854 | struct drm_i915_private *dev_priv = dev->dev_private; |
3865 | uint8_t rev; |
3855 | uint8_t rev; |
3866 | 3856 | ||
3867 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3857 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3868 | sizeof(intel_dp->dpcd)) < 0) |
3858 | sizeof(intel_dp->dpcd)) < 0) |
3869 | return false; /* aux transfer failed */ |
3859 | return false; /* aux transfer failed */ |
3870 | 3860 | ||
3871 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
3861 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
3872 | 3862 | ||
3873 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3863 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3874 | return false; /* DPCD not present */ |
3864 | return false; /* DPCD not present */ |
3875 | 3865 | ||
3876 | /* Check if the panel supports PSR */ |
3866 | /* Check if the panel supports PSR */ |
3877 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
3867 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
3878 | if (is_edp(intel_dp)) { |
3868 | if (is_edp(intel_dp)) { |
3879 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
3869 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
3880 | intel_dp->psr_dpcd, |
3870 | intel_dp->psr_dpcd, |
3881 | sizeof(intel_dp->psr_dpcd)); |
3871 | sizeof(intel_dp->psr_dpcd)); |
3882 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3872 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3883 | dev_priv->psr.sink_support = true; |
3873 | dev_priv->psr.sink_support = true; |
3884 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
3874 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
3885 | } |
3875 | } |
3886 | 3876 | ||
3887 | if (INTEL_INFO(dev)->gen >= 9 && |
3877 | if (INTEL_INFO(dev)->gen >= 9 && |
3888 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { |
3878 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { |
3889 | uint8_t frame_sync_cap; |
3879 | uint8_t frame_sync_cap; |
3890 | 3880 | ||
3891 | dev_priv->psr.sink_support = true; |
3881 | dev_priv->psr.sink_support = true; |
3892 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
3882 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
3893 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, |
3883 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, |
3894 | &frame_sync_cap, 1); |
3884 | &frame_sync_cap, 1); |
3895 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
3885 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
3896 | /* PSR2 needs frame sync as well */ |
3886 | /* PSR2 needs frame sync as well */ |
3897 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; |
3887 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; |
3898 | DRM_DEBUG_KMS("PSR2 %s on sink", |
3888 | DRM_DEBUG_KMS("PSR2 %s on sink", |
3899 | dev_priv->psr.psr2_support ? "supported" : "not supported"); |
3889 | dev_priv->psr.psr2_support ? "supported" : "not supported"); |
3900 | } |
3890 | } |
3901 | } |
3891 | } |
3902 | 3892 | ||
3903 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
3893 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
3904 | yesno(intel_dp_source_supports_hbr2(intel_dp)), |
3894 | yesno(intel_dp_source_supports_hbr2(intel_dp)), |
3905 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
3895 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
3906 | 3896 | ||
3907 | /* Intermediate frequency support */ |
3897 | /* Intermediate frequency support */ |
3908 | if (is_edp(intel_dp) && |
3898 | if (is_edp(intel_dp) && |
3909 | (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && |
3899 | (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && |
3910 | (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && |
3900 | (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && |
3911 | (rev >= 0x03)) { /* eDp v1.4 or higher */ |
3901 | (rev >= 0x03)) { /* eDp v1.4 or higher */ |
3912 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
3902 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
3913 | int i; |
3903 | int i; |
3914 | 3904 | ||
3915 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
3905 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
3916 | DP_SUPPORTED_LINK_RATES, |
3906 | DP_SUPPORTED_LINK_RATES, |
3917 | sink_rates, |
3907 | sink_rates, |
3918 | sizeof(sink_rates)); |
3908 | sizeof(sink_rates)); |
3919 | 3909 | ||
3920 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3910 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3921 | int val = le16_to_cpu(sink_rates[i]); |
3911 | int val = le16_to_cpu(sink_rates[i]); |
3922 | 3912 | ||
3923 | if (val == 0) |
3913 | if (val == 0) |
3924 | break; |
3914 | break; |
3925 | 3915 | ||
3926 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
3916 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
3927 | intel_dp->sink_rates[i] = (val * 200) / 10; |
3917 | intel_dp->sink_rates[i] = (val * 200) / 10; |
3928 | } |
3918 | } |
3929 | intel_dp->num_sink_rates = i; |
3919 | intel_dp->num_sink_rates = i; |
3930 | } |
3920 | } |
3931 | 3921 | ||
3932 | intel_dp_print_rates(intel_dp); |
3922 | intel_dp_print_rates(intel_dp); |
3933 | 3923 | ||
3934 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3924 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3935 | DP_DWN_STRM_PORT_PRESENT)) |
3925 | DP_DWN_STRM_PORT_PRESENT)) |
3936 | return true; /* native DP sink */ |
3926 | return true; /* native DP sink */ |
3937 | 3927 | ||
3938 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
3928 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
3939 | return true; /* no per-port downstream info */ |
3929 | return true; /* no per-port downstream info */ |
3940 | 3930 | ||
3941 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3931 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3942 | intel_dp->downstream_ports, |
3932 | intel_dp->downstream_ports, |
3943 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
3933 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
3944 | return false; /* downstream port status fetch failed */ |
3934 | return false; /* downstream port status fetch failed */ |
3945 | 3935 | ||
3946 | return true; |
3936 | return true; |
3947 | } |
3937 | } |
3948 | 3938 | ||
3949 | static void |
3939 | static void |
3950 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
3940 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
3951 | { |
3941 | { |
3952 | u8 buf[3]; |
3942 | u8 buf[3]; |
3953 | 3943 | ||
3954 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
3944 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
3955 | return; |
3945 | return; |
3956 | 3946 | ||
3957 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
3947 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
3958 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3948 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3959 | buf[0], buf[1], buf[2]); |
3949 | buf[0], buf[1], buf[2]); |
3960 | 3950 | ||
3961 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
3951 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
3962 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3952 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3963 | buf[0], buf[1], buf[2]); |
3953 | buf[0], buf[1], buf[2]); |
3964 | } |
3954 | } |
3965 | 3955 | ||
3966 | static bool |
3956 | static bool |
3967 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
3957 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
3968 | { |
3958 | { |
3969 | u8 buf[1]; |
3959 | u8 buf[1]; |
3970 | 3960 | ||
3971 | if (!intel_dp->can_mst) |
3961 | if (!intel_dp->can_mst) |
3972 | return false; |
3962 | return false; |
3973 | 3963 | ||
3974 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
3964 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
3975 | return false; |
3965 | return false; |
3976 | 3966 | ||
3977 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
3967 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
3978 | if (buf[0] & DP_MST_CAP) { |
3968 | if (buf[0] & DP_MST_CAP) { |
3979 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
3969 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
3980 | intel_dp->is_mst = true; |
3970 | intel_dp->is_mst = true; |
3981 | } else { |
3971 | } else { |
3982 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
3972 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
3983 | intel_dp->is_mst = false; |
3973 | intel_dp->is_mst = false; |
3984 | } |
3974 | } |
3985 | } |
3975 | } |
3986 | 3976 | ||
3987 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
3977 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
3988 | return intel_dp->is_mst; |
3978 | return intel_dp->is_mst; |
3989 | } |
3979 | } |
3990 | 3980 | ||
3991 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
3981 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
3992 | { |
3982 | { |
3993 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3983 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3994 | struct drm_device *dev = dig_port->base.base.dev; |
3984 | struct drm_device *dev = dig_port->base.base.dev; |
3995 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3985 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3996 | u8 buf; |
3986 | u8 buf; |
3997 | int ret = 0; |
3987 | int ret = 0; |
3998 | int count = 0; |
3988 | int count = 0; |
3999 | int attempts = 10; |
3989 | int attempts = 10; |
4000 | 3990 | ||
4001 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3991 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
4002 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
3992 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
4003 | ret = -EIO; |
3993 | ret = -EIO; |
4004 | goto out; |
3994 | goto out; |
4005 | } |
3995 | } |
4006 | 3996 | ||
4007 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
3997 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
4008 | buf & ~DP_TEST_SINK_START) < 0) { |
3998 | buf & ~DP_TEST_SINK_START) < 0) { |
4009 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
3999 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
4010 | ret = -EIO; |
4000 | ret = -EIO; |
4011 | goto out; |
4001 | goto out; |
4012 | } |
4002 | } |
4013 | 4003 | ||
4014 | do { |
4004 | do { |
4015 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4005 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4016 | 4006 | ||
4017 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4007 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4018 | DP_TEST_SINK_MISC, &buf) < 0) { |
4008 | DP_TEST_SINK_MISC, &buf) < 0) { |
4019 | ret = -EIO; |
4009 | ret = -EIO; |
4020 | goto out; |
4010 | goto out; |
4021 | } |
4011 | } |
4022 | count = buf & DP_TEST_COUNT_MASK; |
4012 | count = buf & DP_TEST_COUNT_MASK; |
4023 | } while (--attempts && count); |
4013 | } while (--attempts && count); |
4024 | 4014 | ||
4025 | if (attempts == 0) { |
4015 | if (attempts == 0) { |
4026 | DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n"); |
4016 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
4027 | ret = -ETIMEDOUT; |
4017 | ret = -ETIMEDOUT; |
4028 | } |
4018 | } |
4029 | 4019 | ||
4030 | out: |
4020 | out: |
4031 | hsw_enable_ips(intel_crtc); |
4021 | hsw_enable_ips(intel_crtc); |
4032 | return ret; |
4022 | return ret; |
4033 | } |
4023 | } |
4034 | 4024 | ||
4035 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) |
4025 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) |
4036 | { |
4026 | { |
4037 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4027 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4038 | struct drm_device *dev = dig_port->base.base.dev; |
4028 | struct drm_device *dev = dig_port->base.base.dev; |
4039 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4029 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4040 | u8 buf; |
4030 | u8 buf; |
4041 | int ret; |
4031 | int ret; |
4042 | 4032 | ||
4043 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
4033 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
4044 | return -EIO; |
4034 | return -EIO; |
4045 | 4035 | ||
4046 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
4036 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
4047 | return -ENOTTY; |
4037 | return -ENOTTY; |
4048 | 4038 | ||
4049 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
4039 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
4050 | return -EIO; |
4040 | return -EIO; |
4051 | 4041 | ||
4052 | if (buf & DP_TEST_SINK_START) { |
4042 | if (buf & DP_TEST_SINK_START) { |
4053 | ret = intel_dp_sink_crc_stop(intel_dp); |
4043 | ret = intel_dp_sink_crc_stop(intel_dp); |
4054 | if (ret) |
4044 | if (ret) |
4055 | return ret; |
4045 | return ret; |
4056 | } |
4046 | } |
4057 | 4047 | ||
4058 | hsw_disable_ips(intel_crtc); |
4048 | hsw_disable_ips(intel_crtc); |
4059 | 4049 | ||
4060 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
4050 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
4061 | buf | DP_TEST_SINK_START) < 0) { |
4051 | buf | DP_TEST_SINK_START) < 0) { |
4062 | hsw_enable_ips(intel_crtc); |
4052 | hsw_enable_ips(intel_crtc); |
4063 | return -EIO; |
4053 | return -EIO; |
4064 | } |
4054 | } |
4065 | 4055 | ||
4066 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4056 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4067 | return 0; |
4057 | return 0; |
4068 | } |
4058 | } |
4069 | 4059 | ||
4070 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
4060 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
4071 | { |
4061 | { |
4072 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4062 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4073 | struct drm_device *dev = dig_port->base.base.dev; |
4063 | struct drm_device *dev = dig_port->base.base.dev; |
4074 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4064 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4075 | u8 buf; |
4065 | u8 buf; |
4076 | int count, ret; |
4066 | int count, ret; |
4077 | int attempts = 6; |
4067 | int attempts = 6; |
4078 | 4068 | ||
4079 | ret = intel_dp_sink_crc_start(intel_dp); |
4069 | ret = intel_dp_sink_crc_start(intel_dp); |
4080 | if (ret) |
4070 | if (ret) |
4081 | return ret; |
4071 | return ret; |
4082 | 4072 | ||
4083 | do { |
4073 | do { |
4084 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4074 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4085 | 4075 | ||
4086 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4076 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4087 | DP_TEST_SINK_MISC, &buf) < 0) { |
4077 | DP_TEST_SINK_MISC, &buf) < 0) { |
4088 | ret = -EIO; |
4078 | ret = -EIO; |
4089 | goto stop; |
4079 | goto stop; |
4090 | } |
4080 | } |
4091 | count = buf & DP_TEST_COUNT_MASK; |
4081 | count = buf & DP_TEST_COUNT_MASK; |
4092 | 4082 | ||
4093 | } while (--attempts && count == 0); |
4083 | } while (--attempts && count == 0); |
4094 | 4084 | ||
4095 | if (attempts == 0) { |
4085 | if (attempts == 0) { |
4096 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
4086 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
4097 | ret = -ETIMEDOUT; |
4087 | ret = -ETIMEDOUT; |
4098 | goto stop; |
4088 | goto stop; |
4099 | } |
4089 | } |
4100 | 4090 | ||
4101 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { |
4091 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { |
4102 | ret = -EIO; |
4092 | ret = -EIO; |
4103 | goto stop; |
4093 | goto stop; |
4104 | } |
4094 | } |
4105 | 4095 | ||
4106 | stop: |
4096 | stop: |
4107 | intel_dp_sink_crc_stop(intel_dp); |
4097 | intel_dp_sink_crc_stop(intel_dp); |
4108 | return ret; |
4098 | return ret; |
4109 | } |
4099 | } |
4110 | 4100 | ||
4111 | static bool |
4101 | static bool |
4112 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4102 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4113 | { |
4103 | { |
4114 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
4104 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
4115 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4105 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4116 | sink_irq_vector, 1) == 1; |
4106 | sink_irq_vector, 1) == 1; |
4117 | } |
4107 | } |
4118 | 4108 | ||
4119 | static bool |
4109 | static bool |
4120 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4110 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4121 | { |
4111 | { |
4122 | int ret; |
4112 | int ret; |
4123 | 4113 | ||
4124 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
4114 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
4125 | DP_SINK_COUNT_ESI, |
4115 | DP_SINK_COUNT_ESI, |
4126 | sink_irq_vector, 14); |
4116 | sink_irq_vector, 14); |
4127 | if (ret != 14) |
4117 | if (ret != 14) |
4128 | return false; |
4118 | return false; |
4129 | 4119 | ||
4130 | return true; |
4120 | return true; |
4131 | } |
4121 | } |
4132 | 4122 | ||
4133 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
4123 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
4134 | { |
4124 | { |
4135 | uint8_t test_result = DP_TEST_ACK; |
4125 | uint8_t test_result = DP_TEST_ACK; |
4136 | return test_result; |
4126 | return test_result; |
4137 | } |
4127 | } |
4138 | 4128 | ||
4139 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
4129 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
4140 | { |
4130 | { |
4141 | uint8_t test_result = DP_TEST_NAK; |
4131 | uint8_t test_result = DP_TEST_NAK; |
4142 | return test_result; |
4132 | return test_result; |
4143 | } |
4133 | } |
4144 | 4134 | ||
4145 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) |
4135 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) |
4146 | { |
4136 | { |
4147 | uint8_t test_result = DP_TEST_NAK; |
4137 | uint8_t test_result = DP_TEST_NAK; |
4148 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4138 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4149 | struct drm_connector *connector = &intel_connector->base; |
4139 | struct drm_connector *connector = &intel_connector->base; |
4150 | 4140 | ||
4151 | if (intel_connector->detect_edid == NULL || |
4141 | if (intel_connector->detect_edid == NULL || |
4152 | connector->edid_corrupt || |
4142 | connector->edid_corrupt || |
4153 | intel_dp->aux.i2c_defer_count > 6) { |
4143 | intel_dp->aux.i2c_defer_count > 6) { |
4154 | /* Check EDID read for NACKs, DEFERs and corruption |
4144 | /* Check EDID read for NACKs, DEFERs and corruption |
4155 | * (DP CTS 1.2 Core r1.1) |
4145 | * (DP CTS 1.2 Core r1.1) |
4156 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
4146 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
4157 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
4147 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
4158 | * 4.2.2.6 : EDID corruption detected |
4148 | * 4.2.2.6 : EDID corruption detected |
4159 | * Use failsafe mode for all cases |
4149 | * Use failsafe mode for all cases |
4160 | */ |
4150 | */ |
4161 | if (intel_dp->aux.i2c_nack_count > 0 || |
4151 | if (intel_dp->aux.i2c_nack_count > 0 || |
4162 | intel_dp->aux.i2c_defer_count > 0) |
4152 | intel_dp->aux.i2c_defer_count > 0) |
4163 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", |
4153 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", |
4164 | intel_dp->aux.i2c_nack_count, |
4154 | intel_dp->aux.i2c_nack_count, |
4165 | intel_dp->aux.i2c_defer_count); |
4155 | intel_dp->aux.i2c_defer_count); |
4166 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; |
4156 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; |
4167 | } else { |
4157 | } else { |
4168 | struct edid *block = intel_connector->detect_edid; |
4158 | struct edid *block = intel_connector->detect_edid; |
4169 | 4159 | ||
4170 | /* We have to write the checksum |
4160 | /* We have to write the checksum |
4171 | * of the last block read |
4161 | * of the last block read |
4172 | */ |
4162 | */ |
4173 | block += intel_connector->detect_edid->extensions; |
4163 | block += intel_connector->detect_edid->extensions; |
4174 | 4164 | ||
4175 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
4165 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
4176 | DP_TEST_EDID_CHECKSUM, |
4166 | DP_TEST_EDID_CHECKSUM, |
4177 | &block->checksum, |
4167 | &block->checksum, |
4178 | 1)) |
4168 | 1)) |
4179 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4169 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4180 | 4170 | ||
4181 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; |
4171 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; |
4182 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; |
4172 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; |
4183 | } |
4173 | } |
4184 | 4174 | ||
4185 | /* Set test active flag here so userspace doesn't interrupt things */ |
4175 | /* Set test active flag here so userspace doesn't interrupt things */ |
4186 | intel_dp->compliance_test_active = 1; |
4176 | intel_dp->compliance_test_active = 1; |
4187 | 4177 | ||
4188 | return test_result; |
4178 | return test_result; |
4189 | } |
4179 | } |
4190 | 4180 | ||
4191 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
4181 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
4192 | { |
4182 | { |
4193 | uint8_t test_result = DP_TEST_NAK; |
4183 | uint8_t test_result = DP_TEST_NAK; |
4194 | return test_result; |
4184 | return test_result; |
4195 | } |
4185 | } |
4196 | 4186 | ||
4197 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) |
4187 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) |
4198 | { |
4188 | { |
4199 | uint8_t response = DP_TEST_NAK; |
4189 | uint8_t response = DP_TEST_NAK; |
4200 | uint8_t rxdata = 0; |
4190 | uint8_t rxdata = 0; |
4201 | int status = 0; |
4191 | int status = 0; |
4202 | 4192 | ||
4203 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
4193 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
4204 | if (status <= 0) { |
4194 | if (status <= 0) { |
4205 | DRM_DEBUG_KMS("Could not read test request from sink\n"); |
4195 | DRM_DEBUG_KMS("Could not read test request from sink\n"); |
4206 | goto update_status; |
4196 | goto update_status; |
4207 | } |
4197 | } |
4208 | 4198 | ||
4209 | switch (rxdata) { |
4199 | switch (rxdata) { |
4210 | case DP_TEST_LINK_TRAINING: |
4200 | case DP_TEST_LINK_TRAINING: |
4211 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); |
4201 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); |
4212 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; |
4202 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; |
4213 | response = intel_dp_autotest_link_training(intel_dp); |
4203 | response = intel_dp_autotest_link_training(intel_dp); |
4214 | break; |
4204 | break; |
4215 | case DP_TEST_LINK_VIDEO_PATTERN: |
4205 | case DP_TEST_LINK_VIDEO_PATTERN: |
4216 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); |
4206 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); |
4217 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; |
4207 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; |
4218 | response = intel_dp_autotest_video_pattern(intel_dp); |
4208 | response = intel_dp_autotest_video_pattern(intel_dp); |
4219 | break; |
4209 | break; |
4220 | case DP_TEST_LINK_EDID_READ: |
4210 | case DP_TEST_LINK_EDID_READ: |
4221 | DRM_DEBUG_KMS("EDID test requested\n"); |
4211 | DRM_DEBUG_KMS("EDID test requested\n"); |
4222 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; |
4212 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; |
4223 | response = intel_dp_autotest_edid(intel_dp); |
4213 | response = intel_dp_autotest_edid(intel_dp); |
4224 | break; |
4214 | break; |
4225 | case DP_TEST_LINK_PHY_TEST_PATTERN: |
4215 | case DP_TEST_LINK_PHY_TEST_PATTERN: |
4226 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); |
4216 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); |
4227 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; |
4217 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; |
4228 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4218 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4229 | break; |
4219 | break; |
4230 | default: |
4220 | default: |
4231 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); |
4221 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); |
4232 | break; |
4222 | break; |
4233 | } |
4223 | } |
4234 | 4224 | ||
4235 | update_status: |
4225 | update_status: |
4236 | status = drm_dp_dpcd_write(&intel_dp->aux, |
4226 | status = drm_dp_dpcd_write(&intel_dp->aux, |
4237 | DP_TEST_RESPONSE, |
4227 | DP_TEST_RESPONSE, |
4238 | &response, 1); |
4228 | &response, 1); |
4239 | if (status <= 0) |
4229 | if (status <= 0) |
4240 | DRM_DEBUG_KMS("Could not write test response to sink\n"); |
4230 | DRM_DEBUG_KMS("Could not write test response to sink\n"); |
4241 | } |
4231 | } |
4242 | 4232 | ||
4243 | static int |
4233 | static int |
4244 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
4234 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
4245 | { |
4235 | { |
4246 | bool bret; |
4236 | bool bret; |
4247 | 4237 | ||
4248 | if (intel_dp->is_mst) { |
4238 | if (intel_dp->is_mst) { |
4249 | u8 esi[16] = { 0 }; |
4239 | u8 esi[16] = { 0 }; |
4250 | int ret = 0; |
4240 | int ret = 0; |
4251 | int retry; |
4241 | int retry; |
4252 | bool handled; |
4242 | bool handled; |
4253 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4243 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4254 | go_again: |
4244 | go_again: |
4255 | if (bret == true) { |
4245 | if (bret == true) { |
4256 | 4246 | ||
4257 | /* check link status - esi[10] = 0x200c */ |
4247 | /* check link status - esi[10] = 0x200c */ |
4258 | if (intel_dp->active_mst_links && |
4248 | if (intel_dp->active_mst_links && |
4259 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
4249 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
4260 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
4250 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
4261 | intel_dp_start_link_train(intel_dp); |
4251 | intel_dp_start_link_train(intel_dp); |
4262 | intel_dp_stop_link_train(intel_dp); |
4252 | intel_dp_stop_link_train(intel_dp); |
4263 | } |
4253 | } |
4264 | 4254 | ||
4265 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
4255 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
4266 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4256 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4267 | 4257 | ||
4268 | if (handled) { |
4258 | if (handled) { |
4269 | for (retry = 0; retry < 3; retry++) { |
4259 | for (retry = 0; retry < 3; retry++) { |
4270 | int wret; |
4260 | int wret; |
4271 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
4261 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
4272 | DP_SINK_COUNT_ESI+1, |
4262 | DP_SINK_COUNT_ESI+1, |
4273 | &esi[1], 3); |
4263 | &esi[1], 3); |
4274 | if (wret == 3) { |
4264 | if (wret == 3) { |
4275 | break; |
4265 | break; |
4276 | } |
4266 | } |
4277 | } |
4267 | } |
4278 | 4268 | ||
4279 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4269 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4280 | if (bret == true) { |
4270 | if (bret == true) { |
4281 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
4271 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
4282 | goto go_again; |
4272 | goto go_again; |
4283 | } |
4273 | } |
4284 | } else |
4274 | } else |
4285 | ret = 0; |
4275 | ret = 0; |
4286 | 4276 | ||
4287 | return ret; |
4277 | return ret; |
4288 | } else { |
4278 | } else { |
4289 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4279 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4290 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
4280 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
4291 | intel_dp->is_mst = false; |
4281 | intel_dp->is_mst = false; |
4292 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
4282 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
4293 | /* send a hotplug event */ |
4283 | /* send a hotplug event */ |
4294 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
4284 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
4295 | } |
4285 | } |
4296 | } |
4286 | } |
4297 | return -EINVAL; |
4287 | return -EINVAL; |
4298 | } |
4288 | } |
4299 | 4289 | ||
4300 | /* |
4290 | /* |
4301 | * According to DP spec |
4291 | * According to DP spec |
4302 | * 5.1.2: |
4292 | * 5.1.2: |
4303 | * 1. Read DPCD |
4293 | * 1. Read DPCD |
4304 | * 2. Configure link according to Receiver Capabilities |
4294 | * 2. Configure link according to Receiver Capabilities |
4305 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
4295 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
4306 | * 4. Check link status on receipt of hot-plug interrupt |
4296 | * 4. Check link status on receipt of hot-plug interrupt |
4307 | */ |
4297 | */ |
4308 | static void |
4298 | static void |
4309 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
4299 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
4310 | { |
4300 | { |
4311 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4301 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4312 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4302 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4313 | u8 sink_irq_vector; |
4303 | u8 sink_irq_vector; |
4314 | u8 link_status[DP_LINK_STATUS_SIZE]; |
4304 | u8 link_status[DP_LINK_STATUS_SIZE]; |
4315 | 4305 | ||
4316 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
4306 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
4317 | 4307 | ||
4318 | /* |
4308 | /* |
4319 | * Clearing compliance test variables to allow capturing |
4309 | * Clearing compliance test variables to allow capturing |
4320 | * of values for next automated test request. |
4310 | * of values for next automated test request. |
4321 | */ |
4311 | */ |
4322 | intel_dp->compliance_test_active = 0; |
4312 | intel_dp->compliance_test_active = 0; |
4323 | intel_dp->compliance_test_type = 0; |
4313 | intel_dp->compliance_test_type = 0; |
4324 | intel_dp->compliance_test_data = 0; |
4314 | intel_dp->compliance_test_data = 0; |
4325 | 4315 | ||
4326 | if (!intel_encoder->base.crtc) |
4316 | if (!intel_encoder->base.crtc) |
4327 | return; |
4317 | return; |
4328 | 4318 | ||
4329 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
4319 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
4330 | return; |
4320 | return; |
4331 | 4321 | ||
4332 | /* Try to read receiver status if the link appears to be up */ |
4322 | /* Try to read receiver status if the link appears to be up */ |
4333 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
4323 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
4334 | return; |
4324 | return; |
4335 | } |
4325 | } |
4336 | 4326 | ||
4337 | /* Now read the DPCD to see if it's actually running */ |
4327 | /* Now read the DPCD to see if it's actually running */ |
4338 | if (!intel_dp_get_dpcd(intel_dp)) { |
4328 | if (!intel_dp_get_dpcd(intel_dp)) { |
4339 | return; |
4329 | return; |
4340 | } |
4330 | } |
4341 | 4331 | ||
4342 | /* Try to read the source of the interrupt */ |
4332 | /* Try to read the source of the interrupt */ |
4343 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4333 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4344 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4334 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4345 | /* Clear interrupt source */ |
4335 | /* Clear interrupt source */ |
4346 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4336 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4347 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4337 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4348 | sink_irq_vector); |
4338 | sink_irq_vector); |
4349 | 4339 | ||
4350 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4340 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4351 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
4341 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
4352 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4342 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4353 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4343 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4354 | } |
4344 | } |
4355 | 4345 | ||
4356 | /* if link training is requested we should perform it always */ |
4346 | /* if link training is requested we should perform it always */ |
4357 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || |
4347 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || |
4358 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { |
4348 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { |
4359 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
4349 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
4360 | intel_encoder->base.name); |
4350 | intel_encoder->base.name); |
4361 | intel_dp_start_link_train(intel_dp); |
4351 | intel_dp_start_link_train(intel_dp); |
4362 | intel_dp_stop_link_train(intel_dp); |
4352 | intel_dp_stop_link_train(intel_dp); |
4363 | } |
4353 | } |
4364 | } |
4354 | } |
4365 | 4355 | ||
4366 | /* XXX this is probably wrong for multiple downstream ports */ |
4356 | /* XXX this is probably wrong for multiple downstream ports */ |
4367 | static enum drm_connector_status |
4357 | static enum drm_connector_status |
4368 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
4358 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
4369 | { |
4359 | { |
4370 | uint8_t *dpcd = intel_dp->dpcd; |
4360 | uint8_t *dpcd = intel_dp->dpcd; |
4371 | uint8_t type; |
4361 | uint8_t type; |
4372 | 4362 | ||
4373 | if (!intel_dp_get_dpcd(intel_dp)) |
4363 | if (!intel_dp_get_dpcd(intel_dp)) |
4374 | return connector_status_disconnected; |
4364 | return connector_status_disconnected; |
4375 | 4365 | ||
4376 | /* if there's no downstream port, we're done */ |
4366 | /* if there's no downstream port, we're done */ |
4377 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
4367 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
4378 | return connector_status_connected; |
4368 | return connector_status_connected; |
4379 | 4369 | ||
4380 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
4370 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
4381 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4371 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4382 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
4372 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
4383 | uint8_t reg; |
4373 | uint8_t reg; |
4384 | 4374 | ||
4385 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
4375 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
4386 | ®, 1) < 0) |
4376 | ®, 1) < 0) |
4387 | return connector_status_unknown; |
4377 | return connector_status_unknown; |
4388 | 4378 | ||
4389 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
4379 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
4390 | : connector_status_disconnected; |
4380 | : connector_status_disconnected; |
4391 | } |
4381 | } |
4392 | 4382 | ||
4393 | /* If no HPD, poke DDC gently */ |
4383 | /* If no HPD, poke DDC gently */ |
4394 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
4384 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
4395 | return connector_status_connected; |
4385 | return connector_status_connected; |
4396 | 4386 | ||
4397 | /* Well we tried, say unknown for unreliable port types */ |
4387 | /* Well we tried, say unknown for unreliable port types */ |
4398 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4388 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4399 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
4389 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
4400 | if (type == DP_DS_PORT_TYPE_VGA || |
4390 | if (type == DP_DS_PORT_TYPE_VGA || |
4401 | type == DP_DS_PORT_TYPE_NON_EDID) |
4391 | type == DP_DS_PORT_TYPE_NON_EDID) |
4402 | return connector_status_unknown; |
4392 | return connector_status_unknown; |
4403 | } else { |
4393 | } else { |
4404 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
4394 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
4405 | DP_DWN_STRM_PORT_TYPE_MASK; |
4395 | DP_DWN_STRM_PORT_TYPE_MASK; |
4406 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
4396 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
4407 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
4397 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
4408 | return connector_status_unknown; |
4398 | return connector_status_unknown; |
4409 | } |
4399 | } |
4410 | 4400 | ||
4411 | /* Anything else is out of spec, warn and ignore */ |
4401 | /* Anything else is out of spec, warn and ignore */ |
4412 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
4402 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
4413 | return connector_status_disconnected; |
4403 | return connector_status_disconnected; |
4414 | } |
4404 | } |
4415 | 4405 | ||
4416 | static enum drm_connector_status |
4406 | static enum drm_connector_status |
4417 | edp_detect(struct intel_dp *intel_dp) |
4407 | edp_detect(struct intel_dp *intel_dp) |
4418 | { |
4408 | { |
4419 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4409 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4420 | enum drm_connector_status status; |
4410 | enum drm_connector_status status; |
4421 | 4411 | ||
4422 | status = intel_panel_detect(dev); |
4412 | status = intel_panel_detect(dev); |
4423 | if (status == connector_status_unknown) |
4413 | if (status == connector_status_unknown) |
4424 | status = connector_status_connected; |
4414 | status = connector_status_connected; |
4425 | 4415 | ||
4426 | return status; |
4416 | return status; |
4427 | } |
4417 | } |
4428 | 4418 | ||
4429 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4419 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4430 | struct intel_digital_port *port) |
4420 | struct intel_digital_port *port) |
4431 | { |
4421 | { |
4432 | u32 bit; |
4422 | u32 bit; |
4433 | 4423 | ||
4434 | switch (port->port) { |
4424 | switch (port->port) { |
4435 | case PORT_A: |
4425 | case PORT_A: |
4436 | return true; |
4426 | return true; |
4437 | case PORT_B: |
4427 | case PORT_B: |
4438 | bit = SDE_PORTB_HOTPLUG; |
4428 | bit = SDE_PORTB_HOTPLUG; |
4439 | break; |
4429 | break; |
4440 | case PORT_C: |
4430 | case PORT_C: |
4441 | bit = SDE_PORTC_HOTPLUG; |
4431 | bit = SDE_PORTC_HOTPLUG; |
4442 | break; |
4432 | break; |
4443 | case PORT_D: |
4433 | case PORT_D: |
4444 | bit = SDE_PORTD_HOTPLUG; |
4434 | bit = SDE_PORTD_HOTPLUG; |
4445 | break; |
4435 | break; |
4446 | default: |
4436 | default: |
4447 | MISSING_CASE(port->port); |
4437 | MISSING_CASE(port->port); |
4448 | return false; |
4438 | return false; |
4449 | } |
4439 | } |
4450 | 4440 | ||
4451 | return I915_READ(SDEISR) & bit; |
4441 | return I915_READ(SDEISR) & bit; |
4452 | } |
4442 | } |
4453 | 4443 | ||
4454 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, |
4444 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, |
4455 | struct intel_digital_port *port) |
4445 | struct intel_digital_port *port) |
4456 | { |
4446 | { |
4457 | u32 bit; |
4447 | u32 bit; |
4458 | 4448 | ||
4459 | switch (port->port) { |
4449 | switch (port->port) { |
4460 | case PORT_A: |
4450 | case PORT_A: |
4461 | return true; |
4451 | return true; |
4462 | case PORT_B: |
4452 | case PORT_B: |
4463 | bit = SDE_PORTB_HOTPLUG_CPT; |
4453 | bit = SDE_PORTB_HOTPLUG_CPT; |
4464 | break; |
4454 | break; |
4465 | case PORT_C: |
4455 | case PORT_C: |
4466 | bit = SDE_PORTC_HOTPLUG_CPT; |
4456 | bit = SDE_PORTC_HOTPLUG_CPT; |
4467 | break; |
4457 | break; |
4468 | case PORT_D: |
4458 | case PORT_D: |
4469 | bit = SDE_PORTD_HOTPLUG_CPT; |
4459 | bit = SDE_PORTD_HOTPLUG_CPT; |
4470 | break; |
4460 | break; |
4471 | case PORT_E: |
4461 | case PORT_E: |
4472 | bit = SDE_PORTE_HOTPLUG_SPT; |
4462 | bit = SDE_PORTE_HOTPLUG_SPT; |
4473 | break; |
4463 | break; |
4474 | default: |
4464 | default: |
4475 | MISSING_CASE(port->port); |
4465 | MISSING_CASE(port->port); |
4476 | return false; |
4466 | return false; |
4477 | } |
4467 | } |
4478 | 4468 | ||
4479 | return I915_READ(SDEISR) & bit; |
4469 | return I915_READ(SDEISR) & bit; |
4480 | } |
4470 | } |
4481 | 4471 | ||
4482 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
4472 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
4483 | struct intel_digital_port *port) |
4473 | struct intel_digital_port *port) |
4484 | { |
4474 | { |
4485 | u32 bit; |
4475 | u32 bit; |
4486 | 4476 | ||
4487 | switch (port->port) { |
4477 | switch (port->port) { |
4488 | case PORT_B: |
4478 | case PORT_B: |
4489 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
4479 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
4490 | break; |
4480 | break; |
4491 | case PORT_C: |
4481 | case PORT_C: |
4492 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
4482 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
4493 | break; |
4483 | break; |
4494 | case PORT_D: |
4484 | case PORT_D: |
4495 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
4485 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
4496 | break; |
4486 | break; |
4497 | default: |
4487 | default: |
4498 | MISSING_CASE(port->port); |
4488 | MISSING_CASE(port->port); |
4499 | return false; |
4489 | return false; |
4500 | } |
4490 | } |
4501 | 4491 | ||
4502 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4492 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4503 | } |
4493 | } |
4504 | 4494 | ||
4505 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4495 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4506 | struct intel_digital_port *port) |
4496 | struct intel_digital_port *port) |
4507 | { |
4497 | { |
4508 | u32 bit; |
4498 | u32 bit; |
4509 | 4499 | ||
4510 | switch (port->port) { |
4500 | switch (port->port) { |
4511 | case PORT_B: |
4501 | case PORT_B: |
4512 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
4502 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
4513 | break; |
4503 | break; |
4514 | case PORT_C: |
4504 | case PORT_C: |
4515 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
4505 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
4516 | break; |
4506 | break; |
4517 | case PORT_D: |
4507 | case PORT_D: |
4518 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
4508 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
4519 | break; |
4509 | break; |
4520 | default: |
4510 | default: |
4521 | MISSING_CASE(port->port); |
4511 | MISSING_CASE(port->port); |
4522 | return false; |
4512 | return false; |
4523 | } |
4513 | } |
4524 | 4514 | ||
4525 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4515 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4526 | } |
4516 | } |
4527 | 4517 | ||
4528 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
4518 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
4529 | struct intel_digital_port *intel_dig_port) |
4519 | struct intel_digital_port *intel_dig_port) |
4530 | { |
4520 | { |
4531 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4521 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4532 | enum port port; |
4522 | enum port port; |
4533 | u32 bit; |
4523 | u32 bit; |
4534 | 4524 | ||
4535 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4525 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4536 | switch (port) { |
4526 | switch (port) { |
4537 | case PORT_A: |
4527 | case PORT_A: |
4538 | bit = BXT_DE_PORT_HP_DDIA; |
4528 | bit = BXT_DE_PORT_HP_DDIA; |
4539 | break; |
4529 | break; |
4540 | case PORT_B: |
4530 | case PORT_B: |
4541 | bit = BXT_DE_PORT_HP_DDIB; |
4531 | bit = BXT_DE_PORT_HP_DDIB; |
4542 | break; |
4532 | break; |
4543 | case PORT_C: |
4533 | case PORT_C: |
4544 | bit = BXT_DE_PORT_HP_DDIC; |
4534 | bit = BXT_DE_PORT_HP_DDIC; |
4545 | break; |
4535 | break; |
4546 | default: |
4536 | default: |
4547 | MISSING_CASE(port); |
4537 | MISSING_CASE(port); |
4548 | return false; |
4538 | return false; |
4549 | } |
4539 | } |
4550 | 4540 | ||
4551 | return I915_READ(GEN8_DE_PORT_ISR) & bit; |
4541 | return I915_READ(GEN8_DE_PORT_ISR) & bit; |
4552 | } |
4542 | } |
4553 | 4543 | ||
4554 | /* |
4544 | /* |
4555 | * intel_digital_port_connected - is the specified port connected? |
4545 | * intel_digital_port_connected - is the specified port connected? |
4556 | * @dev_priv: i915 private structure |
4546 | * @dev_priv: i915 private structure |
4557 | * @port: the port to test |
4547 | * @port: the port to test |
4558 | * |
4548 | * |
4559 | * Return %true if @port is connected, %false otherwise. |
4549 | * Return %true if @port is connected, %false otherwise. |
4560 | */ |
4550 | */ |
4561 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
4551 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
4562 | struct intel_digital_port *port) |
4552 | struct intel_digital_port *port) |
4563 | { |
4553 | { |
4564 | if (HAS_PCH_IBX(dev_priv)) |
4554 | if (HAS_PCH_IBX(dev_priv)) |
4565 | return ibx_digital_port_connected(dev_priv, port); |
4555 | return ibx_digital_port_connected(dev_priv, port); |
4566 | if (HAS_PCH_SPLIT(dev_priv)) |
4556 | else if (HAS_PCH_SPLIT(dev_priv)) |
4567 | return cpt_digital_port_connected(dev_priv, port); |
4557 | return cpt_digital_port_connected(dev_priv, port); |
4568 | else if (IS_BROXTON(dev_priv)) |
4558 | else if (IS_BROXTON(dev_priv)) |
4569 | return bxt_digital_port_connected(dev_priv, port); |
4559 | return bxt_digital_port_connected(dev_priv, port); |
4570 | else if (IS_GM45(dev_priv)) |
4560 | else if (IS_GM45(dev_priv)) |
4571 | return gm45_digital_port_connected(dev_priv, port); |
4561 | return gm45_digital_port_connected(dev_priv, port); |
4572 | else |
4562 | else |
4573 | return g4x_digital_port_connected(dev_priv, port); |
4563 | return g4x_digital_port_connected(dev_priv, port); |
4574 | } |
4564 | } |
4575 | 4565 | ||
4576 | static struct edid * |
4566 | static struct edid * |
4577 | intel_dp_get_edid(struct intel_dp *intel_dp) |
4567 | intel_dp_get_edid(struct intel_dp *intel_dp) |
4578 | { |
4568 | { |
4579 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4569 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4580 | 4570 | ||
4581 | /* use cached edid if we have one */ |
4571 | /* use cached edid if we have one */ |
4582 | if (intel_connector->edid) { |
4572 | if (intel_connector->edid) { |
4583 | /* invalid edid */ |
4573 | /* invalid edid */ |
4584 | if (IS_ERR(intel_connector->edid)) |
4574 | if (IS_ERR(intel_connector->edid)) |
4585 | return NULL; |
4575 | return NULL; |
4586 | 4576 | ||
4587 | return drm_edid_duplicate(intel_connector->edid); |
4577 | return drm_edid_duplicate(intel_connector->edid); |
4588 | } else |
4578 | } else |
4589 | return drm_get_edid(&intel_connector->base, |
4579 | return drm_get_edid(&intel_connector->base, |
4590 | &intel_dp->aux.ddc); |
4580 | &intel_dp->aux.ddc); |
4591 | } |
4581 | } |
4592 | 4582 | ||
4593 | static void |
4583 | static void |
4594 | intel_dp_set_edid(struct intel_dp *intel_dp) |
4584 | intel_dp_set_edid(struct intel_dp *intel_dp) |
4595 | { |
4585 | { |
4596 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4586 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4597 | struct edid *edid; |
4587 | struct edid *edid; |
4598 | 4588 | ||
4599 | edid = intel_dp_get_edid(intel_dp); |
4589 | edid = intel_dp_get_edid(intel_dp); |
4600 | intel_connector->detect_edid = edid; |
4590 | intel_connector->detect_edid = edid; |
4601 | 4591 | ||
4602 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
4592 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
4603 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
4593 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
4604 | else |
4594 | else |
4605 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
4595 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
4606 | } |
4596 | } |
4607 | 4597 | ||
4608 | static void |
4598 | static void |
4609 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
4599 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
4610 | { |
4600 | { |
4611 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4601 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4612 | 4602 | ||
4613 | kfree(intel_connector->detect_edid); |
4603 | kfree(intel_connector->detect_edid); |
4614 | intel_connector->detect_edid = NULL; |
4604 | intel_connector->detect_edid = NULL; |
4615 | 4605 | ||
4616 | intel_dp->has_audio = false; |
4606 | intel_dp->has_audio = false; |
4617 | } |
4607 | } |
4618 | 4608 | ||
4619 | static enum drm_connector_status |
4609 | static enum drm_connector_status |
4620 | intel_dp_detect(struct drm_connector *connector, bool force) |
4610 | intel_dp_detect(struct drm_connector *connector, bool force) |
4621 | { |
4611 | { |
4622 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4612 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4623 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4613 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4624 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4614 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4625 | struct drm_device *dev = connector->dev; |
4615 | struct drm_device *dev = connector->dev; |
4626 | enum drm_connector_status status; |
4616 | enum drm_connector_status status; |
4627 | enum intel_display_power_domain power_domain; |
4617 | enum intel_display_power_domain power_domain; |
4628 | bool ret; |
4618 | bool ret; |
4629 | u8 sink_irq_vector; |
4619 | u8 sink_irq_vector; |
4630 | 4620 | ||
4631 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4621 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4632 | connector->base.id, connector->name); |
4622 | connector->base.id, connector->name); |
4633 | intel_dp_unset_edid(intel_dp); |
4623 | intel_dp_unset_edid(intel_dp); |
4634 | 4624 | ||
4635 | if (intel_dp->is_mst) { |
4625 | if (intel_dp->is_mst) { |
4636 | /* MST devices are disconnected from a monitor POV */ |
4626 | /* MST devices are disconnected from a monitor POV */ |
4637 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4627 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4638 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4628 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4639 | return connector_status_disconnected; |
4629 | return connector_status_disconnected; |
4640 | } |
4630 | } |
4641 | 4631 | ||
4642 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4632 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4643 | intel_display_power_get(to_i915(dev), power_domain); |
4633 | intel_display_power_get(to_i915(dev), power_domain); |
4644 | 4634 | ||
4645 | /* Can't disconnect eDP, but you can close the lid... */ |
4635 | /* Can't disconnect eDP, but you can close the lid... */ |
4646 | if (is_edp(intel_dp)) |
4636 | if (is_edp(intel_dp)) |
4647 | status = edp_detect(intel_dp); |
4637 | status = edp_detect(intel_dp); |
4648 | else if (intel_digital_port_connected(to_i915(dev), |
4638 | else if (intel_digital_port_connected(to_i915(dev), |
4649 | dp_to_dig_port(intel_dp))) |
4639 | dp_to_dig_port(intel_dp))) |
4650 | status = intel_dp_detect_dpcd(intel_dp); |
4640 | status = intel_dp_detect_dpcd(intel_dp); |
4651 | else |
4641 | else |
4652 | status = connector_status_disconnected; |
4642 | status = connector_status_disconnected; |
4653 | 4643 | ||
4654 | if (status != connector_status_connected) { |
4644 | if (status != connector_status_connected) { |
4655 | intel_dp->compliance_test_active = 0; |
4645 | intel_dp->compliance_test_active = 0; |
4656 | intel_dp->compliance_test_type = 0; |
4646 | intel_dp->compliance_test_type = 0; |
4657 | intel_dp->compliance_test_data = 0; |
4647 | intel_dp->compliance_test_data = 0; |
4658 | 4648 | ||
4659 | goto out; |
4649 | goto out; |
4660 | } |
4650 | } |
4661 | 4651 | ||
4662 | intel_dp_probe_oui(intel_dp); |
4652 | intel_dp_probe_oui(intel_dp); |
4663 | 4653 | ||
4664 | ret = intel_dp_probe_mst(intel_dp); |
4654 | ret = intel_dp_probe_mst(intel_dp); |
4665 | if (ret) { |
4655 | if (ret) { |
4666 | /* if we are in MST mode then this connector |
4656 | /* if we are in MST mode then this connector |
4667 | won't appear connected or have anything with EDID on it */ |
4657 | won't appear connected or have anything with EDID on it */ |
4668 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4658 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4669 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4659 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4670 | status = connector_status_disconnected; |
4660 | status = connector_status_disconnected; |
4671 | goto out; |
4661 | goto out; |
4672 | } |
4662 | } |
4673 | 4663 | ||
4674 | /* |
4664 | /* |
4675 | * Clearing NACK and defer counts to get their exact values |
4665 | * Clearing NACK and defer counts to get their exact values |
4676 | * while reading EDID which are required by Compliance tests |
4666 | * while reading EDID which are required by Compliance tests |
4677 | * 4.2.2.4 and 4.2.2.5 |
4667 | * 4.2.2.4 and 4.2.2.5 |
4678 | */ |
4668 | */ |
4679 | intel_dp->aux.i2c_nack_count = 0; |
4669 | intel_dp->aux.i2c_nack_count = 0; |
4680 | intel_dp->aux.i2c_defer_count = 0; |
4670 | intel_dp->aux.i2c_defer_count = 0; |
4681 | 4671 | ||
4682 | intel_dp_set_edid(intel_dp); |
4672 | intel_dp_set_edid(intel_dp); |
4683 | 4673 | ||
4684 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4674 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4685 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4675 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4686 | status = connector_status_connected; |
4676 | status = connector_status_connected; |
4687 | 4677 | ||
4688 | /* Try to read the source of the interrupt */ |
4678 | /* Try to read the source of the interrupt */ |
4689 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4679 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4690 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4680 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4691 | /* Clear interrupt source */ |
4681 | /* Clear interrupt source */ |
4692 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4682 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4693 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4683 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4694 | sink_irq_vector); |
4684 | sink_irq_vector); |
4695 | 4685 | ||
4696 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4686 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4697 | intel_dp_handle_test_request(intel_dp); |
4687 | intel_dp_handle_test_request(intel_dp); |
4698 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4688 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4699 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4689 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4700 | } |
4690 | } |
4701 | 4691 | ||
4702 | out: |
4692 | out: |
4703 | intel_display_power_put(to_i915(dev), power_domain); |
4693 | intel_display_power_put(to_i915(dev), power_domain); |
4704 | return status; |
4694 | return status; |
4705 | } |
4695 | } |
4706 | 4696 | ||
4707 | static void |
4697 | static void |
4708 | intel_dp_force(struct drm_connector *connector) |
4698 | intel_dp_force(struct drm_connector *connector) |
4709 | { |
4699 | { |
4710 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4700 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4711 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4701 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4712 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
4702 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
4713 | enum intel_display_power_domain power_domain; |
4703 | enum intel_display_power_domain power_domain; |
4714 | 4704 | ||
4715 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4705 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4716 | connector->base.id, connector->name); |
4706 | connector->base.id, connector->name); |
4717 | intel_dp_unset_edid(intel_dp); |
4707 | intel_dp_unset_edid(intel_dp); |
4718 | 4708 | ||
4719 | if (connector->status != connector_status_connected) |
4709 | if (connector->status != connector_status_connected) |
4720 | return; |
4710 | return; |
4721 | 4711 | ||
4722 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4712 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4723 | intel_display_power_get(dev_priv, power_domain); |
4713 | intel_display_power_get(dev_priv, power_domain); |
4724 | 4714 | ||
4725 | intel_dp_set_edid(intel_dp); |
4715 | intel_dp_set_edid(intel_dp); |
4726 | 4716 | ||
4727 | intel_display_power_put(dev_priv, power_domain); |
4717 | intel_display_power_put(dev_priv, power_domain); |
4728 | 4718 | ||
4729 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4719 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4730 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4720 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4731 | } |
4721 | } |
4732 | 4722 | ||
4733 | static int intel_dp_get_modes(struct drm_connector *connector) |
4723 | static int intel_dp_get_modes(struct drm_connector *connector) |
4734 | { |
4724 | { |
4735 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4725 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4736 | struct edid *edid; |
4726 | struct edid *edid; |
4737 | 4727 | ||
4738 | edid = intel_connector->detect_edid; |
4728 | edid = intel_connector->detect_edid; |
4739 | if (edid) { |
4729 | if (edid) { |
4740 | int ret = intel_connector_update_modes(connector, edid); |
4730 | int ret = intel_connector_update_modes(connector, edid); |
4741 | if (ret) |
4731 | if (ret) |
4742 | return ret; |
4732 | return ret; |
4743 | } |
4733 | } |
4744 | 4734 | ||
4745 | /* if eDP has no EDID, fall back to fixed mode */ |
4735 | /* if eDP has no EDID, fall back to fixed mode */ |
4746 | if (is_edp(intel_attached_dp(connector)) && |
4736 | if (is_edp(intel_attached_dp(connector)) && |
4747 | intel_connector->panel.fixed_mode) { |
4737 | intel_connector->panel.fixed_mode) { |
4748 | struct drm_display_mode *mode; |
4738 | struct drm_display_mode *mode; |
4749 | 4739 | ||
4750 | mode = drm_mode_duplicate(connector->dev, |
4740 | mode = drm_mode_duplicate(connector->dev, |
4751 | intel_connector->panel.fixed_mode); |
4741 | intel_connector->panel.fixed_mode); |
4752 | if (mode) { |
4742 | if (mode) { |
4753 | drm_mode_probed_add(connector, mode); |
4743 | drm_mode_probed_add(connector, mode); |
4754 | return 1; |
4744 | return 1; |
4755 | } |
4745 | } |
4756 | } |
4746 | } |
4757 | 4747 | ||
4758 | return 0; |
4748 | return 0; |
4759 | } |
4749 | } |
4760 | 4750 | ||
4761 | static bool |
4751 | static bool |
4762 | intel_dp_detect_audio(struct drm_connector *connector) |
4752 | intel_dp_detect_audio(struct drm_connector *connector) |
4763 | { |
4753 | { |
4764 | bool has_audio = false; |
4754 | bool has_audio = false; |
4765 | struct edid *edid; |
4755 | struct edid *edid; |
4766 | 4756 | ||
4767 | edid = to_intel_connector(connector)->detect_edid; |
4757 | edid = to_intel_connector(connector)->detect_edid; |
4768 | if (edid) |
4758 | if (edid) |
4769 | has_audio = drm_detect_monitor_audio(edid); |
4759 | has_audio = drm_detect_monitor_audio(edid); |
4770 | 4760 | ||
4771 | return has_audio; |
4761 | return has_audio; |
4772 | } |
4762 | } |
4773 | 4763 | ||
4774 | static int |
4764 | static int |
4775 | intel_dp_set_property(struct drm_connector *connector, |
4765 | intel_dp_set_property(struct drm_connector *connector, |
4776 | struct drm_property *property, |
4766 | struct drm_property *property, |
4777 | uint64_t val) |
4767 | uint64_t val) |
4778 | { |
4768 | { |
4779 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
4769 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
4780 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4770 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4781 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4771 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4782 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4772 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4783 | int ret; |
4773 | int ret; |
4784 | 4774 | ||
4785 | ret = drm_object_property_set_value(&connector->base, property, val); |
4775 | ret = drm_object_property_set_value(&connector->base, property, val); |
4786 | if (ret) |
4776 | if (ret) |
4787 | return ret; |
4777 | return ret; |
4788 | 4778 | ||
4789 | if (property == dev_priv->force_audio_property) { |
4779 | if (property == dev_priv->force_audio_property) { |
4790 | int i = val; |
4780 | int i = val; |
4791 | bool has_audio; |
4781 | bool has_audio; |
4792 | 4782 | ||
4793 | if (i == intel_dp->force_audio) |
4783 | if (i == intel_dp->force_audio) |
4794 | return 0; |
4784 | return 0; |
4795 | 4785 | ||
4796 | intel_dp->force_audio = i; |
4786 | intel_dp->force_audio = i; |
4797 | 4787 | ||
4798 | if (i == HDMI_AUDIO_AUTO) |
4788 | if (i == HDMI_AUDIO_AUTO) |
4799 | has_audio = intel_dp_detect_audio(connector); |
4789 | has_audio = intel_dp_detect_audio(connector); |
4800 | else |
4790 | else |
4801 | has_audio = (i == HDMI_AUDIO_ON); |
4791 | has_audio = (i == HDMI_AUDIO_ON); |
4802 | 4792 | ||
4803 | if (has_audio == intel_dp->has_audio) |
4793 | if (has_audio == intel_dp->has_audio) |
4804 | return 0; |
4794 | return 0; |
4805 | 4795 | ||
4806 | intel_dp->has_audio = has_audio; |
4796 | intel_dp->has_audio = has_audio; |
4807 | goto done; |
4797 | goto done; |
4808 | } |
4798 | } |
4809 | 4799 | ||
4810 | if (property == dev_priv->broadcast_rgb_property) { |
4800 | if (property == dev_priv->broadcast_rgb_property) { |
4811 | bool old_auto = intel_dp->color_range_auto; |
4801 | bool old_auto = intel_dp->color_range_auto; |
4812 | bool old_range = intel_dp->limited_color_range; |
4802 | bool old_range = intel_dp->limited_color_range; |
4813 | 4803 | ||
4814 | switch (val) { |
4804 | switch (val) { |
4815 | case INTEL_BROADCAST_RGB_AUTO: |
4805 | case INTEL_BROADCAST_RGB_AUTO: |
4816 | intel_dp->color_range_auto = true; |
4806 | intel_dp->color_range_auto = true; |
4817 | break; |
4807 | break; |
4818 | case INTEL_BROADCAST_RGB_FULL: |
4808 | case INTEL_BROADCAST_RGB_FULL: |
4819 | intel_dp->color_range_auto = false; |
4809 | intel_dp->color_range_auto = false; |
4820 | intel_dp->limited_color_range = false; |
4810 | intel_dp->limited_color_range = false; |
4821 | break; |
4811 | break; |
4822 | case INTEL_BROADCAST_RGB_LIMITED: |
4812 | case INTEL_BROADCAST_RGB_LIMITED: |
4823 | intel_dp->color_range_auto = false; |
4813 | intel_dp->color_range_auto = false; |
4824 | intel_dp->limited_color_range = true; |
4814 | intel_dp->limited_color_range = true; |
4825 | break; |
4815 | break; |
4826 | default: |
4816 | default: |
4827 | return -EINVAL; |
4817 | return -EINVAL; |
4828 | } |
4818 | } |
4829 | 4819 | ||
4830 | if (old_auto == intel_dp->color_range_auto && |
4820 | if (old_auto == intel_dp->color_range_auto && |
4831 | old_range == intel_dp->limited_color_range) |
4821 | old_range == intel_dp->limited_color_range) |
4832 | return 0; |
4822 | return 0; |
4833 | 4823 | ||
4834 | goto done; |
4824 | goto done; |
4835 | } |
4825 | } |
4836 | 4826 | ||
4837 | if (is_edp(intel_dp) && |
4827 | if (is_edp(intel_dp) && |
4838 | property == connector->dev->mode_config.scaling_mode_property) { |
4828 | property == connector->dev->mode_config.scaling_mode_property) { |
4839 | if (val == DRM_MODE_SCALE_NONE) { |
4829 | if (val == DRM_MODE_SCALE_NONE) { |
4840 | DRM_DEBUG_KMS("no scaling not supported\n"); |
4830 | DRM_DEBUG_KMS("no scaling not supported\n"); |
4841 | return -EINVAL; |
4831 | return -EINVAL; |
4842 | } |
4832 | } |
4843 | 4833 | ||
4844 | if (intel_connector->panel.fitting_mode == val) { |
4834 | if (intel_connector->panel.fitting_mode == val) { |
4845 | /* the eDP scaling property is not changed */ |
4835 | /* the eDP scaling property is not changed */ |
4846 | return 0; |
4836 | return 0; |
4847 | } |
4837 | } |
4848 | intel_connector->panel.fitting_mode = val; |
4838 | intel_connector->panel.fitting_mode = val; |
4849 | 4839 | ||
4850 | goto done; |
4840 | goto done; |
4851 | } |
4841 | } |
4852 | 4842 | ||
4853 | return -EINVAL; |
4843 | return -EINVAL; |
4854 | 4844 | ||
4855 | done: |
4845 | done: |
4856 | if (intel_encoder->base.crtc) |
4846 | if (intel_encoder->base.crtc) |
4857 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
4847 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
4858 | 4848 | ||
4859 | return 0; |
4849 | return 0; |
4860 | } |
4850 | } |
4861 | 4851 | ||
4862 | static void |
4852 | static void |
4863 | intel_dp_connector_destroy(struct drm_connector *connector) |
4853 | intel_dp_connector_destroy(struct drm_connector *connector) |
4864 | { |
4854 | { |
4865 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4855 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4866 | 4856 | ||
4867 | kfree(intel_connector->detect_edid); |
4857 | kfree(intel_connector->detect_edid); |
4868 | 4858 | ||
4869 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4859 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4870 | kfree(intel_connector->edid); |
4860 | kfree(intel_connector->edid); |
4871 | 4861 | ||
4872 | /* Can't call is_edp() since the encoder may have been destroyed |
4862 | /* Can't call is_edp() since the encoder may have been destroyed |
4873 | * already. */ |
4863 | * already. */ |
4874 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
4864 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
4875 | intel_panel_fini(&intel_connector->panel); |
4865 | intel_panel_fini(&intel_connector->panel); |
4876 | 4866 | ||
4877 | drm_connector_cleanup(connector); |
4867 | drm_connector_cleanup(connector); |
4878 | kfree(connector); |
4868 | kfree(connector); |
4879 | } |
4869 | } |
4880 | 4870 | ||
4881 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
4871 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
4882 | { |
4872 | { |
4883 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4873 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4884 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4874 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4885 | - | ||
4886 | intel_dp_aux_fini(intel_dp); |
4875 | |
4887 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
4876 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
4888 | if (is_edp(intel_dp)) { |
4877 | if (is_edp(intel_dp)) { |
4889 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
4878 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
4890 | /* |
4879 | /* |
4891 | * vdd might still be enabled do to the delayed vdd off. |
4880 | * vdd might still be enabled do to the delayed vdd off. |
4892 | * Make sure vdd is actually turned off here. |
4881 | * Make sure vdd is actually turned off here. |
4893 | */ |
4882 | */ |
4894 | pps_lock(intel_dp); |
4883 | pps_lock(intel_dp); |
4895 | edp_panel_vdd_off_sync(intel_dp); |
4884 | edp_panel_vdd_off_sync(intel_dp); |
4896 | pps_unlock(intel_dp); |
4885 | pps_unlock(intel_dp); |
4897 | 4886 | ||
4898 | if (intel_dp->edp_notifier.notifier_call) { |
4887 | if (intel_dp->edp_notifier.notifier_call) { |
4899 | intel_dp->edp_notifier.notifier_call = NULL; |
4888 | intel_dp->edp_notifier.notifier_call = NULL; |
4900 | } |
4889 | } |
4901 | } |
4890 | } |
4902 | drm_encoder_cleanup(encoder); |
4891 | drm_encoder_cleanup(encoder); |
4903 | kfree(intel_dig_port); |
4892 | kfree(intel_dig_port); |
4904 | } |
4893 | } |
4905 | 4894 | ||
4906 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
4895 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
4907 | { |
4896 | { |
4908 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4897 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4909 | 4898 | ||
4910 | if (!is_edp(intel_dp)) |
4899 | if (!is_edp(intel_dp)) |
4911 | return; |
4900 | return; |
4912 | 4901 | ||
4913 | /* |
4902 | /* |
4914 | * vdd might still be enabled do to the delayed vdd off. |
4903 | * vdd might still be enabled do to the delayed vdd off. |
4915 | * Make sure vdd is actually turned off here. |
4904 | * Make sure vdd is actually turned off here. |
4916 | */ |
4905 | */ |
4917 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
4906 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
4918 | pps_lock(intel_dp); |
4907 | pps_lock(intel_dp); |
4919 | edp_panel_vdd_off_sync(intel_dp); |
4908 | edp_panel_vdd_off_sync(intel_dp); |
4920 | pps_unlock(intel_dp); |
4909 | pps_unlock(intel_dp); |
4921 | } |
4910 | } |
4922 | 4911 | ||
4923 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4912 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4924 | { |
4913 | { |
4925 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4914 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4926 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4915 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4927 | struct drm_i915_private *dev_priv = dev->dev_private; |
4916 | struct drm_i915_private *dev_priv = dev->dev_private; |
4928 | enum intel_display_power_domain power_domain; |
4917 | enum intel_display_power_domain power_domain; |
4929 | 4918 | ||
4930 | lockdep_assert_held(&dev_priv->pps_mutex); |
4919 | lockdep_assert_held(&dev_priv->pps_mutex); |
4931 | 4920 | ||
4932 | if (!edp_have_panel_vdd(intel_dp)) |
4921 | if (!edp_have_panel_vdd(intel_dp)) |
4933 | return; |
4922 | return; |
4934 | 4923 | ||
4935 | /* |
4924 | /* |
4936 | * The VDD bit needs a power domain reference, so if the bit is |
4925 | * The VDD bit needs a power domain reference, so if the bit is |
4937 | * already enabled when we boot or resume, grab this reference and |
4926 | * already enabled when we boot or resume, grab this reference and |
4938 | * schedule a vdd off, so we don't hold on to the reference |
4927 | * schedule a vdd off, so we don't hold on to the reference |
4939 | * indefinitely. |
4928 | * indefinitely. |
4940 | */ |
4929 | */ |
4941 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
4930 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
4942 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
4931 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
4943 | intel_display_power_get(dev_priv, power_domain); |
4932 | intel_display_power_get(dev_priv, power_domain); |
4944 | 4933 | ||
4945 | edp_panel_vdd_schedule_off(intel_dp); |
4934 | edp_panel_vdd_schedule_off(intel_dp); |
4946 | } |
4935 | } |
4947 | 4936 | ||
4948 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
4937 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
4949 | { |
4938 | { |
- | 4939 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
|
4950 | struct intel_dp *intel_dp; |
4940 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
- | 4941 | ||
- | 4942 | if (!HAS_DDI(dev_priv)) |
|
- | 4943 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
|
4951 | 4944 | ||
4952 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
4945 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
4953 | return; |
4946 | return; |
4954 | - | ||
4955 | intel_dp = enc_to_intel_dp(encoder); |
- | |
4956 | 4947 | ||
4957 | pps_lock(intel_dp); |
4948 | pps_lock(intel_dp); |
4958 | 4949 | ||
4959 | /* |
4950 | /* |
4960 | * Read out the current power sequencer assignment, |
4951 | * Read out the current power sequencer assignment, |
4961 | * in case the BIOS did something with it. |
4952 | * in case the BIOS did something with it. |
4962 | */ |
4953 | */ |
4963 | if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) |
4954 | if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) |
4964 | vlv_initial_power_sequencer_setup(intel_dp); |
4955 | vlv_initial_power_sequencer_setup(intel_dp); |
4965 | 4956 | ||
4966 | intel_edp_panel_vdd_sanitize(intel_dp); |
4957 | intel_edp_panel_vdd_sanitize(intel_dp); |
4967 | 4958 | ||
4968 | pps_unlock(intel_dp); |
4959 | pps_unlock(intel_dp); |
4969 | } |
4960 | } |
4970 | 4961 | ||
4971 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4962 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4972 | .dpms = drm_atomic_helper_connector_dpms, |
4963 | .dpms = drm_atomic_helper_connector_dpms, |
4973 | .detect = intel_dp_detect, |
4964 | .detect = intel_dp_detect, |
4974 | .force = intel_dp_force, |
4965 | .force = intel_dp_force, |
4975 | .fill_modes = drm_helper_probe_single_connector_modes, |
4966 | .fill_modes = drm_helper_probe_single_connector_modes, |
4976 | .set_property = intel_dp_set_property, |
4967 | .set_property = intel_dp_set_property, |
4977 | .atomic_get_property = intel_connector_atomic_get_property, |
4968 | .atomic_get_property = intel_connector_atomic_get_property, |
4978 | .destroy = intel_dp_connector_destroy, |
4969 | .destroy = intel_dp_connector_destroy, |
4979 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
4970 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
4980 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4971 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4981 | }; |
4972 | }; |
4982 | 4973 | ||
4983 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
4974 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
4984 | .get_modes = intel_dp_get_modes, |
4975 | .get_modes = intel_dp_get_modes, |
4985 | .mode_valid = intel_dp_mode_valid, |
4976 | .mode_valid = intel_dp_mode_valid, |
4986 | .best_encoder = intel_best_encoder, |
4977 | .best_encoder = intel_best_encoder, |
4987 | }; |
4978 | }; |
4988 | 4979 | ||
4989 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
4980 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
4990 | .reset = intel_dp_encoder_reset, |
4981 | .reset = intel_dp_encoder_reset, |
4991 | .destroy = intel_dp_encoder_destroy, |
4982 | .destroy = intel_dp_encoder_destroy, |
4992 | }; |
4983 | }; |
4993 | 4984 | ||
4994 | enum irqreturn |
4985 | enum irqreturn |
4995 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
4986 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
4996 | { |
4987 | { |
4997 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4988 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
4998 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4989 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4999 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4990 | struct drm_device *dev = intel_dig_port->base.base.dev; |
5000 | struct drm_i915_private *dev_priv = dev->dev_private; |
4991 | struct drm_i915_private *dev_priv = dev->dev_private; |
5001 | enum intel_display_power_domain power_domain; |
4992 | enum intel_display_power_domain power_domain; |
5002 | enum irqreturn ret = IRQ_NONE; |
4993 | enum irqreturn ret = IRQ_NONE; |
5003 | 4994 | ||
5004 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
4995 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
5005 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) |
4996 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) |
5006 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
4997 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
5007 | 4998 | ||
5008 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
4999 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
5009 | /* |
5000 | /* |
5010 | * vdd off can generate a long pulse on eDP which |
5001 | * vdd off can generate a long pulse on eDP which |
5011 | * would require vdd on to handle it, and thus we |
5002 | * would require vdd on to handle it, and thus we |
5012 | * would end up in an endless cycle of |
5003 | * would end up in an endless cycle of |
5013 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
5004 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
5014 | */ |
5005 | */ |
5015 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
5006 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
5016 | port_name(intel_dig_port->port)); |
5007 | port_name(intel_dig_port->port)); |
5017 | return IRQ_HANDLED; |
5008 | return IRQ_HANDLED; |
5018 | } |
5009 | } |
5019 | 5010 | ||
5020 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
5011 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
5021 | port_name(intel_dig_port->port), |
5012 | port_name(intel_dig_port->port), |
5022 | long_hpd ? "long" : "short"); |
5013 | long_hpd ? "long" : "short"); |
5023 | 5014 | ||
5024 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
5015 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
5025 | intel_display_power_get(dev_priv, power_domain); |
5016 | intel_display_power_get(dev_priv, power_domain); |
5026 | 5017 | ||
5027 | if (long_hpd) { |
5018 | if (long_hpd) { |
5028 | /* indicate that we need to restart link training */ |
- | |
5029 | intel_dp->train_set_valid = false; |
- | |
5030 | - | ||
5031 | if (!intel_digital_port_connected(dev_priv, intel_dig_port)) |
5019 | if (!intel_digital_port_connected(dev_priv, intel_dig_port)) |
5032 | goto mst_fail; |
5020 | goto mst_fail; |
5033 | 5021 | ||
5034 | if (!intel_dp_get_dpcd(intel_dp)) { |
5022 | if (!intel_dp_get_dpcd(intel_dp)) { |
5035 | goto mst_fail; |
5023 | goto mst_fail; |
5036 | } |
5024 | } |
5037 | 5025 | ||
5038 | intel_dp_probe_oui(intel_dp); |
5026 | intel_dp_probe_oui(intel_dp); |
5039 | 5027 | ||
5040 | if (!intel_dp_probe_mst(intel_dp)) { |
5028 | if (!intel_dp_probe_mst(intel_dp)) { |
5041 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5029 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5042 | intel_dp_check_link_status(intel_dp); |
5030 | intel_dp_check_link_status(intel_dp); |
5043 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5031 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5044 | goto mst_fail; |
5032 | goto mst_fail; |
5045 | } |
5033 | } |
5046 | } else { |
5034 | } else { |
5047 | if (intel_dp->is_mst) { |
5035 | if (intel_dp->is_mst) { |
5048 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
5036 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
5049 | goto mst_fail; |
5037 | goto mst_fail; |
5050 | } |
5038 | } |
5051 | 5039 | ||
5052 | if (!intel_dp->is_mst) { |
5040 | if (!intel_dp->is_mst) { |
5053 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5041 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5054 | intel_dp_check_link_status(intel_dp); |
5042 | intel_dp_check_link_status(intel_dp); |
5055 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5043 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5056 | } |
5044 | } |
5057 | } |
5045 | } |
5058 | 5046 | ||
5059 | ret = IRQ_HANDLED; |
5047 | ret = IRQ_HANDLED; |
5060 | 5048 | ||
5061 | goto put_power; |
5049 | goto put_power; |
5062 | mst_fail: |
5050 | mst_fail: |
5063 | /* if we were in MST mode, and device is not there get out of MST mode */ |
5051 | /* if we were in MST mode, and device is not there get out of MST mode */ |
5064 | if (intel_dp->is_mst) { |
5052 | if (intel_dp->is_mst) { |
5065 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
5053 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
5066 | intel_dp->is_mst = false; |
5054 | intel_dp->is_mst = false; |
5067 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
5055 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
5068 | } |
5056 | } |
5069 | put_power: |
5057 | put_power: |
5070 | intel_display_power_put(dev_priv, power_domain); |
5058 | intel_display_power_put(dev_priv, power_domain); |
5071 | 5059 | ||
5072 | return ret; |
5060 | return ret; |
5073 | } |
5061 | } |
5074 | 5062 | ||
5075 | /* check the VBT to see whether the eDP is on another port */ |
5063 | /* check the VBT to see whether the eDP is on another port */ |
5076 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
5064 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
5077 | { |
5065 | { |
5078 | struct drm_i915_private *dev_priv = dev->dev_private; |
5066 | struct drm_i915_private *dev_priv = dev->dev_private; |
5079 | union child_device_config *p_child; |
5067 | union child_device_config *p_child; |
5080 | int i; |
5068 | int i; |
5081 | static const short port_mapping[] = { |
5069 | static const short port_mapping[] = { |
5082 | [PORT_B] = DVO_PORT_DPB, |
5070 | [PORT_B] = DVO_PORT_DPB, |
5083 | [PORT_C] = DVO_PORT_DPC, |
5071 | [PORT_C] = DVO_PORT_DPC, |
5084 | [PORT_D] = DVO_PORT_DPD, |
5072 | [PORT_D] = DVO_PORT_DPD, |
5085 | [PORT_E] = DVO_PORT_DPE, |
5073 | [PORT_E] = DVO_PORT_DPE, |
5086 | }; |
5074 | }; |
5087 | 5075 | ||
5088 | /* |
5076 | /* |
5089 | * eDP not supported on g4x. so bail out early just |
5077 | * eDP not supported on g4x. so bail out early just |
5090 | * for a bit extra safety in case the VBT is bonkers. |
5078 | * for a bit extra safety in case the VBT is bonkers. |
5091 | */ |
5079 | */ |
5092 | if (INTEL_INFO(dev)->gen < 5) |
5080 | if (INTEL_INFO(dev)->gen < 5) |
5093 | return false; |
5081 | return false; |
5094 | 5082 | ||
5095 | if (port == PORT_A) |
5083 | if (port == PORT_A) |
5096 | return true; |
5084 | return true; |
5097 | 5085 | ||
5098 | if (!dev_priv->vbt.child_dev_num) |
5086 | if (!dev_priv->vbt.child_dev_num) |
5099 | return false; |
5087 | return false; |
5100 | 5088 | ||
5101 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
5089 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
5102 | p_child = dev_priv->vbt.child_dev + i; |
5090 | p_child = dev_priv->vbt.child_dev + i; |
5103 | 5091 | ||
5104 | if (p_child->common.dvo_port == port_mapping[port] && |
5092 | if (p_child->common.dvo_port == port_mapping[port] && |
5105 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
5093 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
5106 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
5094 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
5107 | return true; |
5095 | return true; |
5108 | } |
5096 | } |
5109 | return false; |
5097 | return false; |
5110 | } |
5098 | } |
5111 | 5099 | ||
5112 | void |
5100 | void |
5113 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5101 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5114 | { |
5102 | { |
5115 | struct intel_connector *intel_connector = to_intel_connector(connector); |
5103 | struct intel_connector *intel_connector = to_intel_connector(connector); |
5116 | 5104 | ||
5117 | intel_attach_force_audio_property(connector); |
5105 | intel_attach_force_audio_property(connector); |
5118 | intel_attach_broadcast_rgb_property(connector); |
5106 | intel_attach_broadcast_rgb_property(connector); |
5119 | intel_dp->color_range_auto = true; |
5107 | intel_dp->color_range_auto = true; |
5120 | 5108 | ||
5121 | if (is_edp(intel_dp)) { |
5109 | if (is_edp(intel_dp)) { |
5122 | drm_mode_create_scaling_mode_property(connector->dev); |
5110 | drm_mode_create_scaling_mode_property(connector->dev); |
5123 | drm_object_attach_property( |
5111 | drm_object_attach_property( |
5124 | &connector->base, |
5112 | &connector->base, |
5125 | connector->dev->mode_config.scaling_mode_property, |
5113 | connector->dev->mode_config.scaling_mode_property, |
5126 | DRM_MODE_SCALE_ASPECT); |
5114 | DRM_MODE_SCALE_ASPECT); |
5127 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
5115 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
5128 | } |
5116 | } |
5129 | } |
5117 | } |
5130 | 5118 | ||
5131 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5119 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5132 | { |
5120 | { |
5133 | intel_dp->last_power_cycle = jiffies; |
5121 | intel_dp->panel_power_off_time = ktime_get(); |
5134 | intel_dp->last_power_on = jiffies; |
5122 | intel_dp->last_power_on = jiffies; |
5135 | intel_dp->last_backlight_off = jiffies; |
5123 | intel_dp->last_backlight_off = jiffies; |
5136 | } |
5124 | } |
5137 | 5125 | ||
5138 | static void |
5126 | static void |
5139 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
5127 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
5140 | struct intel_dp *intel_dp) |
5128 | struct intel_dp *intel_dp) |
5141 | { |
5129 | { |
5142 | struct drm_i915_private *dev_priv = dev->dev_private; |
5130 | struct drm_i915_private *dev_priv = dev->dev_private; |
5143 | struct edp_power_seq cur, vbt, spec, |
5131 | struct edp_power_seq cur, vbt, spec, |
5144 | *final = &intel_dp->pps_delays; |
5132 | *final = &intel_dp->pps_delays; |
5145 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
5133 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
5146 | i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
5134 | i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
5147 | 5135 | ||
5148 | lockdep_assert_held(&dev_priv->pps_mutex); |
5136 | lockdep_assert_held(&dev_priv->pps_mutex); |
5149 | 5137 | ||
5150 | /* already initialized? */ |
5138 | /* already initialized? */ |
5151 | if (final->t11_t12 != 0) |
5139 | if (final->t11_t12 != 0) |
5152 | return; |
5140 | return; |
5153 | 5141 | ||
5154 | if (IS_BROXTON(dev)) { |
5142 | if (IS_BROXTON(dev)) { |
5155 | /* |
5143 | /* |
5156 | * TODO: BXT has 2 sets of PPS registers. |
5144 | * TODO: BXT has 2 sets of PPS registers. |
5157 | * Correct Register for Broxton need to be identified |
5145 | * Correct Register for Broxton need to be identified |
5158 | * using VBT. hardcoding for now |
5146 | * using VBT. hardcoding for now |
5159 | */ |
5147 | */ |
5160 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5148 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5161 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5149 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5162 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5150 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5163 | } else if (HAS_PCH_SPLIT(dev)) { |
5151 | } else if (HAS_PCH_SPLIT(dev)) { |
5164 | pp_ctrl_reg = PCH_PP_CONTROL; |
5152 | pp_ctrl_reg = PCH_PP_CONTROL; |
5165 | pp_on_reg = PCH_PP_ON_DELAYS; |
5153 | pp_on_reg = PCH_PP_ON_DELAYS; |
5166 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5154 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5167 | pp_div_reg = PCH_PP_DIVISOR; |
5155 | pp_div_reg = PCH_PP_DIVISOR; |
5168 | } else { |
5156 | } else { |
5169 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5157 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5170 | 5158 | ||
5171 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
5159 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
5172 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5160 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5173 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5161 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5174 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5162 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5175 | } |
5163 | } |
5176 | 5164 | ||
5177 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
5165 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
5178 | * the very first thing. */ |
5166 | * the very first thing. */ |
5179 | pp_ctl = ironlake_get_pp_control(intel_dp); |
5167 | pp_ctl = ironlake_get_pp_control(intel_dp); |
5180 | 5168 | ||
5181 | pp_on = I915_READ(pp_on_reg); |
5169 | pp_on = I915_READ(pp_on_reg); |
5182 | pp_off = I915_READ(pp_off_reg); |
5170 | pp_off = I915_READ(pp_off_reg); |
5183 | if (!IS_BROXTON(dev)) { |
5171 | if (!IS_BROXTON(dev)) { |
5184 | I915_WRITE(pp_ctrl_reg, pp_ctl); |
5172 | I915_WRITE(pp_ctrl_reg, pp_ctl); |
5185 | pp_div = I915_READ(pp_div_reg); |
5173 | pp_div = I915_READ(pp_div_reg); |
5186 | } |
5174 | } |
5187 | 5175 | ||
5188 | /* Pull timing values out of registers */ |
5176 | /* Pull timing values out of registers */ |
5189 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
5177 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
5190 | PANEL_POWER_UP_DELAY_SHIFT; |
5178 | PANEL_POWER_UP_DELAY_SHIFT; |
5191 | 5179 | ||
5192 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
5180 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
5193 | PANEL_LIGHT_ON_DELAY_SHIFT; |
5181 | PANEL_LIGHT_ON_DELAY_SHIFT; |
5194 | 5182 | ||
5195 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
5183 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
5196 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
5184 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
5197 | 5185 | ||
5198 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
5186 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
5199 | PANEL_POWER_DOWN_DELAY_SHIFT; |
5187 | PANEL_POWER_DOWN_DELAY_SHIFT; |
5200 | 5188 | ||
5201 | if (IS_BROXTON(dev)) { |
5189 | if (IS_BROXTON(dev)) { |
5202 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
5190 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
5203 | BXT_POWER_CYCLE_DELAY_SHIFT; |
5191 | BXT_POWER_CYCLE_DELAY_SHIFT; |
5204 | if (tmp > 0) |
5192 | if (tmp > 0) |
5205 | cur.t11_t12 = (tmp - 1) * 1000; |
5193 | cur.t11_t12 = (tmp - 1) * 1000; |
5206 | else |
5194 | else |
5207 | cur.t11_t12 = 0; |
5195 | cur.t11_t12 = 0; |
5208 | } else { |
5196 | } else { |
5209 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
5197 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
5210 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
5198 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
5211 | } |
5199 | } |
5212 | 5200 | ||
5213 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5201 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5214 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
5202 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
5215 | 5203 | ||
5216 | vbt = dev_priv->vbt.edp_pps; |
5204 | vbt = dev_priv->vbt.edp_pps; |
5217 | 5205 | ||
5218 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
5206 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
5219 | * our hw here, which are all in 100usec. */ |
5207 | * our hw here, which are all in 100usec. */ |
5220 | spec.t1_t3 = 210 * 10; |
5208 | spec.t1_t3 = 210 * 10; |
5221 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
5209 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
5222 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
5210 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
5223 | spec.t10 = 500 * 10; |
5211 | spec.t10 = 500 * 10; |
5224 | /* This one is special and actually in units of 100ms, but zero |
5212 | /* This one is special and actually in units of 100ms, but zero |
5225 | * based in the hw (so we need to add 100 ms). But the sw vbt |
5213 | * based in the hw (so we need to add 100 ms). But the sw vbt |
5226 | * table multiplies it with 1000 to make it in units of 100usec, |
5214 | * table multiplies it with 1000 to make it in units of 100usec, |
5227 | * too. */ |
5215 | * too. */ |
5228 | spec.t11_t12 = (510 + 100) * 10; |
5216 | spec.t11_t12 = (510 + 100) * 10; |
5229 | 5217 | ||
5230 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5218 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5231 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
5219 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
5232 | 5220 | ||
5233 | /* Use the max of the register settings and vbt. If both are |
5221 | /* Use the max of the register settings and vbt. If both are |
5234 | * unset, fall back to the spec limits. */ |
5222 | * unset, fall back to the spec limits. */ |
5235 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
5223 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
5236 | spec.field : \ |
5224 | spec.field : \ |
5237 | max(cur.field, vbt.field)) |
5225 | max(cur.field, vbt.field)) |
5238 | assign_final(t1_t3); |
5226 | assign_final(t1_t3); |
5239 | assign_final(t8); |
5227 | assign_final(t8); |
5240 | assign_final(t9); |
5228 | assign_final(t9); |
5241 | assign_final(t10); |
5229 | assign_final(t10); |
5242 | assign_final(t11_t12); |
5230 | assign_final(t11_t12); |
5243 | #undef assign_final |
5231 | #undef assign_final |
5244 | 5232 | ||
5245 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
5233 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
5246 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5234 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5247 | intel_dp->backlight_on_delay = get_delay(t8); |
5235 | intel_dp->backlight_on_delay = get_delay(t8); |
5248 | intel_dp->backlight_off_delay = get_delay(t9); |
5236 | intel_dp->backlight_off_delay = get_delay(t9); |
5249 | intel_dp->panel_power_down_delay = get_delay(t10); |
5237 | intel_dp->panel_power_down_delay = get_delay(t10); |
5250 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
5238 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
5251 | #undef get_delay |
5239 | #undef get_delay |
5252 | 5240 | ||
5253 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5241 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5254 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
5242 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
5255 | intel_dp->panel_power_cycle_delay); |
5243 | intel_dp->panel_power_cycle_delay); |
5256 | 5244 | ||
5257 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
5245 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
5258 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
5246 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
5259 | } |
5247 | } |
5260 | 5248 | ||
5261 | static void |
5249 | static void |
5262 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
5250 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
5263 | struct intel_dp *intel_dp) |
5251 | struct intel_dp *intel_dp) |
5264 | { |
5252 | { |
5265 | struct drm_i915_private *dev_priv = dev->dev_private; |
5253 | struct drm_i915_private *dev_priv = dev->dev_private; |
5266 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
5254 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
5267 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
5255 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
5268 | i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg; |
5256 | i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg; |
5269 | enum port port = dp_to_dig_port(intel_dp)->port; |
5257 | enum port port = dp_to_dig_port(intel_dp)->port; |
5270 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
5258 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
5271 | 5259 | ||
5272 | lockdep_assert_held(&dev_priv->pps_mutex); |
5260 | lockdep_assert_held(&dev_priv->pps_mutex); |
5273 | 5261 | ||
5274 | if (IS_BROXTON(dev)) { |
5262 | if (IS_BROXTON(dev)) { |
5275 | /* |
5263 | /* |
5276 | * TODO: BXT has 2 sets of PPS registers. |
5264 | * TODO: BXT has 2 sets of PPS registers. |
5277 | * Correct Register for Broxton need to be identified |
5265 | * Correct Register for Broxton need to be identified |
5278 | * using VBT. hardcoding for now |
5266 | * using VBT. hardcoding for now |
5279 | */ |
5267 | */ |
5280 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5268 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5281 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5269 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5282 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5270 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5283 | 5271 | ||
5284 | } else if (HAS_PCH_SPLIT(dev)) { |
5272 | } else if (HAS_PCH_SPLIT(dev)) { |
5285 | pp_on_reg = PCH_PP_ON_DELAYS; |
5273 | pp_on_reg = PCH_PP_ON_DELAYS; |
5286 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5274 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5287 | pp_div_reg = PCH_PP_DIVISOR; |
5275 | pp_div_reg = PCH_PP_DIVISOR; |
5288 | } else { |
5276 | } else { |
5289 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5277 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5290 | 5278 | ||
5291 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5279 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5292 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5280 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5293 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5281 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5294 | } |
5282 | } |
5295 | 5283 | ||
5296 | /* |
5284 | /* |
5297 | * And finally store the new values in the power sequencer. The |
5285 | * And finally store the new values in the power sequencer. The |
5298 | * backlight delays are set to 1 because we do manual waits on them. For |
5286 | * backlight delays are set to 1 because we do manual waits on them. For |
5299 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
5287 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
5300 | * we'll end up waiting for the backlight off delay twice: once when we |
5288 | * we'll end up waiting for the backlight off delay twice: once when we |
5301 | * do the manual sleep, and once when we disable the panel and wait for |
5289 | * do the manual sleep, and once when we disable the panel and wait for |
5302 | * the PP_STATUS bit to become zero. |
5290 | * the PP_STATUS bit to become zero. |
5303 | */ |
5291 | */ |
5304 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
5292 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
5305 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5293 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5306 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
5294 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
5307 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
5295 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
5308 | /* Compute the divisor for the pp clock, simply match the Bspec |
5296 | /* Compute the divisor for the pp clock, simply match the Bspec |
5309 | * formula. */ |
5297 | * formula. */ |
5310 | if (IS_BROXTON(dev)) { |
5298 | if (IS_BROXTON(dev)) { |
5311 | pp_div = I915_READ(pp_ctrl_reg); |
5299 | pp_div = I915_READ(pp_ctrl_reg); |
5312 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5300 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5313 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) |
5301 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) |
5314 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
5302 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
5315 | } else { |
5303 | } else { |
5316 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
5304 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
5317 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
5305 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
5318 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
5306 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
5319 | } |
5307 | } |
5320 | 5308 | ||
5321 | /* Haswell doesn't have any port selection bits for the panel |
5309 | /* Haswell doesn't have any port selection bits for the panel |
5322 | * power sequencer any more. */ |
5310 | * power sequencer any more. */ |
5323 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
5311 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
5324 | port_sel = PANEL_PORT_SELECT_VLV(port); |
5312 | port_sel = PANEL_PORT_SELECT_VLV(port); |
5325 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
5313 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
5326 | if (port == PORT_A) |
5314 | if (port == PORT_A) |
5327 | port_sel = PANEL_PORT_SELECT_DPA; |
5315 | port_sel = PANEL_PORT_SELECT_DPA; |
5328 | else |
5316 | else |
5329 | port_sel = PANEL_PORT_SELECT_DPD; |
5317 | port_sel = PANEL_PORT_SELECT_DPD; |
5330 | } |
5318 | } |
5331 | 5319 | ||
5332 | pp_on |= port_sel; |
5320 | pp_on |= port_sel; |
5333 | 5321 | ||
5334 | I915_WRITE(pp_on_reg, pp_on); |
5322 | I915_WRITE(pp_on_reg, pp_on); |
5335 | I915_WRITE(pp_off_reg, pp_off); |
5323 | I915_WRITE(pp_off_reg, pp_off); |
5336 | if (IS_BROXTON(dev)) |
5324 | if (IS_BROXTON(dev)) |
5337 | I915_WRITE(pp_ctrl_reg, pp_div); |
5325 | I915_WRITE(pp_ctrl_reg, pp_div); |
5338 | else |
5326 | else |
5339 | I915_WRITE(pp_div_reg, pp_div); |
5327 | I915_WRITE(pp_div_reg, pp_div); |
5340 | 5328 | ||
5341 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
5329 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
5342 | I915_READ(pp_on_reg), |
5330 | I915_READ(pp_on_reg), |
5343 | I915_READ(pp_off_reg), |
5331 | I915_READ(pp_off_reg), |
5344 | IS_BROXTON(dev) ? |
5332 | IS_BROXTON(dev) ? |
5345 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : |
5333 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : |
5346 | I915_READ(pp_div_reg)); |
5334 | I915_READ(pp_div_reg)); |
5347 | } |
5335 | } |
5348 | 5336 | ||
5349 | /** |
5337 | /** |
5350 | * intel_dp_set_drrs_state - program registers for RR switch to take effect |
5338 | * intel_dp_set_drrs_state - program registers for RR switch to take effect |
5351 | * @dev: DRM device |
5339 | * @dev: DRM device |
5352 | * @refresh_rate: RR to be programmed |
5340 | * @refresh_rate: RR to be programmed |
5353 | * |
5341 | * |
5354 | * This function gets called when refresh rate (RR) has to be changed from |
5342 | * This function gets called when refresh rate (RR) has to be changed from |
5355 | * one frequency to another. Switches can be between high and low RR |
5343 | * one frequency to another. Switches can be between high and low RR |
5356 | * supported by the panel or to any other RR based on media playback (in |
5344 | * supported by the panel or to any other RR based on media playback (in |
5357 | * this case, RR value needs to be passed from user space). |
5345 | * this case, RR value needs to be passed from user space). |
5358 | * |
5346 | * |
5359 | * The caller of this function needs to take a lock on dev_priv->drrs. |
5347 | * The caller of this function needs to take a lock on dev_priv->drrs. |
5360 | */ |
5348 | */ |
5361 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
5349 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
5362 | { |
5350 | { |
5363 | struct drm_i915_private *dev_priv = dev->dev_private; |
5351 | struct drm_i915_private *dev_priv = dev->dev_private; |
5364 | struct intel_encoder *encoder; |
5352 | struct intel_encoder *encoder; |
5365 | struct intel_digital_port *dig_port = NULL; |
5353 | struct intel_digital_port *dig_port = NULL; |
5366 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
5354 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
5367 | struct intel_crtc_state *config = NULL; |
5355 | struct intel_crtc_state *config = NULL; |
5368 | struct intel_crtc *intel_crtc = NULL; |
5356 | struct intel_crtc *intel_crtc = NULL; |
5369 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
5357 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
5370 | 5358 | ||
5371 | if (refresh_rate <= 0) { |
5359 | if (refresh_rate <= 0) { |
5372 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
5360 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
5373 | return; |
5361 | return; |
5374 | } |
5362 | } |
5375 | 5363 | ||
5376 | if (intel_dp == NULL) { |
5364 | if (intel_dp == NULL) { |
5377 | DRM_DEBUG_KMS("DRRS not supported.\n"); |
5365 | DRM_DEBUG_KMS("DRRS not supported.\n"); |
5378 | return; |
5366 | return; |
5379 | } |
5367 | } |
5380 | 5368 | ||
5381 | /* |
5369 | /* |
5382 | * FIXME: This needs proper synchronization with psr state for some |
5370 | * FIXME: This needs proper synchronization with psr state for some |
5383 | * platforms that cannot have PSR and DRRS enabled at the same time. |
5371 | * platforms that cannot have PSR and DRRS enabled at the same time. |
5384 | */ |
5372 | */ |
5385 | 5373 | ||
5386 | dig_port = dp_to_dig_port(intel_dp); |
5374 | dig_port = dp_to_dig_port(intel_dp); |
5387 | encoder = &dig_port->base; |
5375 | encoder = &dig_port->base; |
5388 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
5376 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
5389 | 5377 | ||
5390 | if (!intel_crtc) { |
5378 | if (!intel_crtc) { |
5391 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
5379 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
5392 | return; |
5380 | return; |
5393 | } |
5381 | } |
5394 | 5382 | ||
5395 | config = intel_crtc->config; |
5383 | config = intel_crtc->config; |
5396 | 5384 | ||
5397 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
5385 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
5398 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5386 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5399 | return; |
5387 | return; |
5400 | } |
5388 | } |
5401 | 5389 | ||
5402 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5390 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5403 | refresh_rate) |
5391 | refresh_rate) |
5404 | index = DRRS_LOW_RR; |
5392 | index = DRRS_LOW_RR; |
5405 | 5393 | ||
5406 | if (index == dev_priv->drrs.refresh_rate_type) { |
5394 | if (index == dev_priv->drrs.refresh_rate_type) { |
5407 | DRM_DEBUG_KMS( |
5395 | DRM_DEBUG_KMS( |
5408 | "DRRS requested for previously set RR...ignoring\n"); |
5396 | "DRRS requested for previously set RR...ignoring\n"); |
5409 | return; |
5397 | return; |
5410 | } |
5398 | } |
5411 | 5399 | ||
5412 | if (!intel_crtc->active) { |
5400 | if (!intel_crtc->active) { |
5413 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5401 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5414 | return; |
5402 | return; |
5415 | } |
5403 | } |
5416 | 5404 | ||
5417 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
5405 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
5418 | switch (index) { |
5406 | switch (index) { |
5419 | case DRRS_HIGH_RR: |
5407 | case DRRS_HIGH_RR: |
5420 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5408 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5421 | break; |
5409 | break; |
5422 | case DRRS_LOW_RR: |
5410 | case DRRS_LOW_RR: |
5423 | intel_dp_set_m_n(intel_crtc, M2_N2); |
5411 | intel_dp_set_m_n(intel_crtc, M2_N2); |
5424 | break; |
5412 | break; |
5425 | case DRRS_MAX_RR: |
5413 | case DRRS_MAX_RR: |
5426 | default: |
5414 | default: |
5427 | DRM_ERROR("Unsupported refreshrate type\n"); |
5415 | DRM_ERROR("Unsupported refreshrate type\n"); |
5428 | } |
5416 | } |
5429 | } else if (INTEL_INFO(dev)->gen > 6) { |
5417 | } else if (INTEL_INFO(dev)->gen > 6) { |
5430 | i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
5418 | i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
5431 | u32 val; |
5419 | u32 val; |
5432 | 5420 | ||
5433 | val = I915_READ(reg); |
5421 | val = I915_READ(reg); |
5434 | if (index > DRRS_HIGH_RR) { |
5422 | if (index > DRRS_HIGH_RR) { |
5435 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5423 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5436 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5424 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5437 | else |
5425 | else |
5438 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
5426 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
5439 | } else { |
5427 | } else { |
5440 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5428 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5441 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5429 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5442 | else |
5430 | else |
5443 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
5431 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
5444 | } |
5432 | } |
5445 | I915_WRITE(reg, val); |
5433 | I915_WRITE(reg, val); |
5446 | } |
5434 | } |
5447 | 5435 | ||
5448 | dev_priv->drrs.refresh_rate_type = index; |
5436 | dev_priv->drrs.refresh_rate_type = index; |
5449 | 5437 | ||
5450 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
5438 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
5451 | } |
5439 | } |
5452 | 5440 | ||
5453 | /** |
5441 | /** |
5454 | * intel_edp_drrs_enable - init drrs struct if supported |
5442 | * intel_edp_drrs_enable - init drrs struct if supported |
5455 | * @intel_dp: DP struct |
5443 | * @intel_dp: DP struct |
5456 | * |
5444 | * |
5457 | * Initializes frontbuffer_bits and drrs.dp |
5445 | * Initializes frontbuffer_bits and drrs.dp |
5458 | */ |
5446 | */ |
5459 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
5447 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
5460 | { |
5448 | { |
5461 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5449 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5462 | struct drm_i915_private *dev_priv = dev->dev_private; |
5450 | struct drm_i915_private *dev_priv = dev->dev_private; |
5463 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5451 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5464 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5452 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5465 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5453 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5466 | 5454 | ||
5467 | if (!intel_crtc->config->has_drrs) { |
5455 | if (!intel_crtc->config->has_drrs) { |
5468 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5456 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5469 | return; |
5457 | return; |
5470 | } |
5458 | } |
5471 | 5459 | ||
5472 | mutex_lock(&dev_priv->drrs.mutex); |
5460 | mutex_lock(&dev_priv->drrs.mutex); |
5473 | if (WARN_ON(dev_priv->drrs.dp)) { |
5461 | if (WARN_ON(dev_priv->drrs.dp)) { |
5474 | DRM_ERROR("DRRS already enabled\n"); |
5462 | DRM_ERROR("DRRS already enabled\n"); |
5475 | goto unlock; |
5463 | goto unlock; |
5476 | } |
5464 | } |
5477 | 5465 | ||
5478 | dev_priv->drrs.busy_frontbuffer_bits = 0; |
5466 | dev_priv->drrs.busy_frontbuffer_bits = 0; |
5479 | 5467 | ||
5480 | dev_priv->drrs.dp = intel_dp; |
5468 | dev_priv->drrs.dp = intel_dp; |
5481 | 5469 | ||
5482 | unlock: |
5470 | unlock: |
5483 | mutex_unlock(&dev_priv->drrs.mutex); |
5471 | mutex_unlock(&dev_priv->drrs.mutex); |
5484 | } |
5472 | } |
5485 | 5473 | ||
5486 | /** |
5474 | /** |
5487 | * intel_edp_drrs_disable - Disable DRRS |
5475 | * intel_edp_drrs_disable - Disable DRRS |
5488 | * @intel_dp: DP struct |
5476 | * @intel_dp: DP struct |
5489 | * |
5477 | * |
5490 | */ |
5478 | */ |
5491 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
5479 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
5492 | { |
5480 | { |
5493 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5481 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5494 | struct drm_i915_private *dev_priv = dev->dev_private; |
5482 | struct drm_i915_private *dev_priv = dev->dev_private; |
5495 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5483 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5496 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5484 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5497 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5485 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5498 | 5486 | ||
5499 | if (!intel_crtc->config->has_drrs) |
5487 | if (!intel_crtc->config->has_drrs) |
5500 | return; |
5488 | return; |
5501 | 5489 | ||
5502 | mutex_lock(&dev_priv->drrs.mutex); |
5490 | mutex_lock(&dev_priv->drrs.mutex); |
5503 | if (!dev_priv->drrs.dp) { |
5491 | if (!dev_priv->drrs.dp) { |
5504 | mutex_unlock(&dev_priv->drrs.mutex); |
5492 | mutex_unlock(&dev_priv->drrs.mutex); |
5505 | return; |
5493 | return; |
5506 | } |
5494 | } |
5507 | 5495 | ||
5508 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5496 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5509 | intel_dp_set_drrs_state(dev_priv->dev, |
5497 | intel_dp_set_drrs_state(dev_priv->dev, |
5510 | intel_dp->attached_connector->panel. |
5498 | intel_dp->attached_connector->panel. |
5511 | fixed_mode->vrefresh); |
5499 | fixed_mode->vrefresh); |
5512 | 5500 | ||
5513 | dev_priv->drrs.dp = NULL; |
5501 | dev_priv->drrs.dp = NULL; |
5514 | mutex_unlock(&dev_priv->drrs.mutex); |
5502 | mutex_unlock(&dev_priv->drrs.mutex); |
5515 | 5503 | ||
5516 | // cancel_delayed_work_sync(&dev_priv->drrs.work); |
5504 | cancel_delayed_work_sync(&dev_priv->drrs.work); |
5517 | } |
5505 | } |
5518 | 5506 | ||
5519 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5507 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5520 | { |
5508 | { |
5521 | struct drm_i915_private *dev_priv = |
5509 | struct drm_i915_private *dev_priv = |
5522 | container_of(work, typeof(*dev_priv), drrs.work.work); |
5510 | container_of(work, typeof(*dev_priv), drrs.work.work); |
5523 | struct intel_dp *intel_dp; |
5511 | struct intel_dp *intel_dp; |
5524 | 5512 | ||
5525 | mutex_lock(&dev_priv->drrs.mutex); |
5513 | mutex_lock(&dev_priv->drrs.mutex); |
5526 | 5514 | ||
5527 | intel_dp = dev_priv->drrs.dp; |
5515 | intel_dp = dev_priv->drrs.dp; |
5528 | 5516 | ||
5529 | if (!intel_dp) |
5517 | if (!intel_dp) |
5530 | goto unlock; |
5518 | goto unlock; |
5531 | 5519 | ||
5532 | /* |
5520 | /* |
5533 | * The delayed work can race with an invalidate hence we need to |
5521 | * The delayed work can race with an invalidate hence we need to |
5534 | * recheck. |
5522 | * recheck. |
5535 | */ |
5523 | */ |
5536 | 5524 | ||
5537 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5525 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5538 | goto unlock; |
5526 | goto unlock; |
5539 | 5527 | ||
5540 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
5528 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
5541 | intel_dp_set_drrs_state(dev_priv->dev, |
5529 | intel_dp_set_drrs_state(dev_priv->dev, |
5542 | intel_dp->attached_connector->panel. |
5530 | intel_dp->attached_connector->panel. |
5543 | downclock_mode->vrefresh); |
5531 | downclock_mode->vrefresh); |
5544 | 5532 | ||
5545 | unlock: |
5533 | unlock: |
5546 | mutex_unlock(&dev_priv->drrs.mutex); |
5534 | mutex_unlock(&dev_priv->drrs.mutex); |
5547 | } |
5535 | } |
5548 | 5536 | ||
5549 | /** |
5537 | /** |
5550 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5538 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5551 | * @dev: DRM device |
5539 | * @dev: DRM device |
5552 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5540 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5553 | * |
5541 | * |
5554 | * This function gets called everytime rendering on the given planes start. |
5542 | * This function gets called everytime rendering on the given planes start. |
5555 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). |
5543 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). |
5556 | * |
5544 | * |
5557 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5545 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5558 | */ |
5546 | */ |
5559 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
5547 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
5560 | unsigned frontbuffer_bits) |
5548 | unsigned frontbuffer_bits) |
5561 | { |
5549 | { |
5562 | struct drm_i915_private *dev_priv = dev->dev_private; |
5550 | struct drm_i915_private *dev_priv = dev->dev_private; |
5563 | struct drm_crtc *crtc; |
5551 | struct drm_crtc *crtc; |
5564 | enum pipe pipe; |
5552 | enum pipe pipe; |
5565 | 5553 | ||
5566 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5554 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5567 | return; |
5555 | return; |
5568 | 5556 | ||
5569 | // cancel_delayed_work(&dev_priv->drrs.work); |
5557 | cancel_delayed_work(&dev_priv->drrs.work); |
5570 | 5558 | ||
5571 | mutex_lock(&dev_priv->drrs.mutex); |
5559 | mutex_lock(&dev_priv->drrs.mutex); |
5572 | if (!dev_priv->drrs.dp) { |
5560 | if (!dev_priv->drrs.dp) { |
5573 | mutex_unlock(&dev_priv->drrs.mutex); |
5561 | mutex_unlock(&dev_priv->drrs.mutex); |
5574 | return; |
5562 | return; |
5575 | } |
5563 | } |
5576 | 5564 | ||
5577 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5565 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5578 | pipe = to_intel_crtc(crtc)->pipe; |
5566 | pipe = to_intel_crtc(crtc)->pipe; |
5579 | 5567 | ||
5580 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5568 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5581 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; |
5569 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; |
5582 | 5570 | ||
5583 | /* invalidate means busy screen hence upclock */ |
5571 | /* invalidate means busy screen hence upclock */ |
5584 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5572 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5585 | intel_dp_set_drrs_state(dev_priv->dev, |
5573 | intel_dp_set_drrs_state(dev_priv->dev, |
5586 | dev_priv->drrs.dp->attached_connector->panel. |
5574 | dev_priv->drrs.dp->attached_connector->panel. |
5587 | fixed_mode->vrefresh); |
5575 | fixed_mode->vrefresh); |
5588 | 5576 | ||
5589 | mutex_unlock(&dev_priv->drrs.mutex); |
5577 | mutex_unlock(&dev_priv->drrs.mutex); |
5590 | } |
5578 | } |
5591 | 5579 | ||
5592 | /** |
5580 | /** |
5593 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5581 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5594 | * @dev: DRM device |
5582 | * @dev: DRM device |
5595 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5583 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5596 | * |
5584 | * |
5597 | * This function gets called every time rendering on the given planes has |
5585 | * This function gets called every time rendering on the given planes has |
5598 | * completed or flip on a crtc is completed. So DRRS should be upclocked |
5586 | * completed or flip on a crtc is completed. So DRRS should be upclocked |
5599 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, |
5587 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, |
5600 | * if no other planes are dirty. |
5588 | * if no other planes are dirty. |
5601 | * |
5589 | * |
5602 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5590 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5603 | */ |
5591 | */ |
5604 | void intel_edp_drrs_flush(struct drm_device *dev, |
5592 | void intel_edp_drrs_flush(struct drm_device *dev, |
5605 | unsigned frontbuffer_bits) |
5593 | unsigned frontbuffer_bits) |
5606 | { |
5594 | { |
5607 | struct drm_i915_private *dev_priv = dev->dev_private; |
5595 | struct drm_i915_private *dev_priv = dev->dev_private; |
5608 | struct drm_crtc *crtc; |
5596 | struct drm_crtc *crtc; |
5609 | enum pipe pipe; |
5597 | enum pipe pipe; |
5610 | 5598 | ||
5611 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5599 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5612 | return; |
5600 | return; |
5613 | 5601 | ||
5614 | // cancel_delayed_work(&dev_priv->drrs.work); |
5602 | cancel_delayed_work(&dev_priv->drrs.work); |
5615 | 5603 | ||
5616 | mutex_lock(&dev_priv->drrs.mutex); |
5604 | mutex_lock(&dev_priv->drrs.mutex); |
5617 | if (!dev_priv->drrs.dp) { |
5605 | if (!dev_priv->drrs.dp) { |
5618 | mutex_unlock(&dev_priv->drrs.mutex); |
5606 | mutex_unlock(&dev_priv->drrs.mutex); |
5619 | return; |
5607 | return; |
5620 | } |
5608 | } |
5621 | 5609 | ||
5622 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5610 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5623 | pipe = to_intel_crtc(crtc)->pipe; |
5611 | pipe = to_intel_crtc(crtc)->pipe; |
5624 | 5612 | ||
5625 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5613 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5626 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5614 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5627 | 5615 | ||
5628 | /* flush means busy screen hence upclock */ |
5616 | /* flush means busy screen hence upclock */ |
5629 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5617 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5630 | intel_dp_set_drrs_state(dev_priv->dev, |
5618 | intel_dp_set_drrs_state(dev_priv->dev, |
5631 | dev_priv->drrs.dp->attached_connector->panel. |
5619 | dev_priv->drrs.dp->attached_connector->panel. |
5632 | fixed_mode->vrefresh); |
5620 | fixed_mode->vrefresh); |
5633 | 5621 | ||
5634 | /* |
5622 | /* |
5635 | * flush also means no more activity hence schedule downclock, if all |
5623 | * flush also means no more activity hence schedule downclock, if all |
5636 | * other fbs are quiescent too |
5624 | * other fbs are quiescent too |
5637 | */ |
5625 | */ |
5638 | if (!dev_priv->drrs.busy_frontbuffer_bits) |
5626 | if (!dev_priv->drrs.busy_frontbuffer_bits) |
5639 | schedule_delayed_work(&dev_priv->drrs.work, |
5627 | schedule_delayed_work(&dev_priv->drrs.work, |
5640 | msecs_to_jiffies(1000)); |
5628 | msecs_to_jiffies(1000)); |
5641 | mutex_unlock(&dev_priv->drrs.mutex); |
5629 | mutex_unlock(&dev_priv->drrs.mutex); |
5642 | } |
5630 | } |
5643 | 5631 | ||
5644 | /** |
5632 | /** |
5645 | * DOC: Display Refresh Rate Switching (DRRS) |
5633 | * DOC: Display Refresh Rate Switching (DRRS) |
5646 | * |
5634 | * |
5647 | * Display Refresh Rate Switching (DRRS) is a power conservation feature |
5635 | * Display Refresh Rate Switching (DRRS) is a power conservation feature |
5648 | * which enables swtching between low and high refresh rates, |
5636 | * which enables swtching between low and high refresh rates, |
5649 | * dynamically, based on the usage scenario. This feature is applicable |
5637 | * dynamically, based on the usage scenario. This feature is applicable |
5650 | * for internal panels. |
5638 | * for internal panels. |
5651 | * |
5639 | * |
5652 | * Indication that the panel supports DRRS is given by the panel EDID, which |
5640 | * Indication that the panel supports DRRS is given by the panel EDID, which |
5653 | * would list multiple refresh rates for one resolution. |
5641 | * would list multiple refresh rates for one resolution. |
5654 | * |
5642 | * |
5655 | * DRRS is of 2 types - static and seamless. |
5643 | * DRRS is of 2 types - static and seamless. |
5656 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset |
5644 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset |
5657 | * (may appear as a blink on screen) and is used in dock-undock scenario. |
5645 | * (may appear as a blink on screen) and is used in dock-undock scenario. |
5658 | * Seamless DRRS involves changing RR without any visual effect to the user |
5646 | * Seamless DRRS involves changing RR without any visual effect to the user |
5659 | * and can be used during normal system usage. This is done by programming |
5647 | * and can be used during normal system usage. This is done by programming |
5660 | * certain registers. |
5648 | * certain registers. |
5661 | * |
5649 | * |
5662 | * Support for static/seamless DRRS may be indicated in the VBT based on |
5650 | * Support for static/seamless DRRS may be indicated in the VBT based on |
5663 | * inputs from the panel spec. |
5651 | * inputs from the panel spec. |
5664 | * |
5652 | * |
5665 | * DRRS saves power by switching to low RR based on usage scenarios. |
5653 | * DRRS saves power by switching to low RR based on usage scenarios. |
5666 | * |
5654 | * |
5667 | * eDP DRRS:- |
5655 | * eDP DRRS:- |
5668 | * The implementation is based on frontbuffer tracking implementation. |
5656 | * The implementation is based on frontbuffer tracking implementation. |
5669 | * When there is a disturbance on the screen triggered by user activity or a |
5657 | * When there is a disturbance on the screen triggered by user activity or a |
5670 | * periodic system activity, DRRS is disabled (RR is changed to high RR). |
5658 | * periodic system activity, DRRS is disabled (RR is changed to high RR). |
5671 | * When there is no movement on screen, after a timeout of 1 second, a switch |
5659 | * When there is no movement on screen, after a timeout of 1 second, a switch |
5672 | * to low RR is made. |
5660 | * to low RR is made. |
5673 | * For integration with frontbuffer tracking code, |
5661 | * For integration with frontbuffer tracking code, |
5674 | * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called. |
5662 | * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called. |
5675 | * |
5663 | * |
5676 | * DRRS can be further extended to support other internal panels and also |
5664 | * DRRS can be further extended to support other internal panels and also |
5677 | * the scenario of video playback wherein RR is set based on the rate |
5665 | * the scenario of video playback wherein RR is set based on the rate |
5678 | * requested by userspace. |
5666 | * requested by userspace. |
5679 | */ |
5667 | */ |
5680 | 5668 | ||
5681 | /** |
5669 | /** |
5682 | * intel_dp_drrs_init - Init basic DRRS work and mutex. |
5670 | * intel_dp_drrs_init - Init basic DRRS work and mutex. |
5683 | * @intel_connector: eDP connector |
5671 | * @intel_connector: eDP connector |
5684 | * @fixed_mode: preferred mode of panel |
5672 | * @fixed_mode: preferred mode of panel |
5685 | * |
5673 | * |
5686 | * This function is called only once at driver load to initialize basic |
5674 | * This function is called only once at driver load to initialize basic |
5687 | * DRRS stuff. |
5675 | * DRRS stuff. |
5688 | * |
5676 | * |
5689 | * Returns: |
5677 | * Returns: |
5690 | * Downclock mode if panel supports it, else return NULL. |
5678 | * Downclock mode if panel supports it, else return NULL. |
5691 | * DRRS support is determined by the presence of downclock mode (apart |
5679 | * DRRS support is determined by the presence of downclock mode (apart |
5692 | * from VBT setting). |
5680 | * from VBT setting). |
5693 | */ |
5681 | */ |
5694 | static struct drm_display_mode * |
5682 | static struct drm_display_mode * |
5695 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5683 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5696 | struct drm_display_mode *fixed_mode) |
5684 | struct drm_display_mode *fixed_mode) |
5697 | { |
5685 | { |
5698 | struct drm_connector *connector = &intel_connector->base; |
5686 | struct drm_connector *connector = &intel_connector->base; |
5699 | struct drm_device *dev = connector->dev; |
5687 | struct drm_device *dev = connector->dev; |
5700 | struct drm_i915_private *dev_priv = dev->dev_private; |
5688 | struct drm_i915_private *dev_priv = dev->dev_private; |
5701 | struct drm_display_mode *downclock_mode = NULL; |
5689 | struct drm_display_mode *downclock_mode = NULL; |
5702 | 5690 | ||
5703 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5691 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5704 | mutex_init(&dev_priv->drrs.mutex); |
5692 | mutex_init(&dev_priv->drrs.mutex); |
5705 | 5693 | ||
5706 | if (INTEL_INFO(dev)->gen <= 6) { |
5694 | if (INTEL_INFO(dev)->gen <= 6) { |
5707 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5695 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5708 | return NULL; |
5696 | return NULL; |
5709 | } |
5697 | } |
5710 | 5698 | ||
5711 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
5699 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
5712 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
5700 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
5713 | return NULL; |
5701 | return NULL; |
5714 | } |
5702 | } |
5715 | 5703 | ||
5716 | downclock_mode = intel_find_panel_downclock |
5704 | downclock_mode = intel_find_panel_downclock |
5717 | (dev, fixed_mode, connector); |
5705 | (dev, fixed_mode, connector); |
5718 | 5706 | ||
5719 | if (!downclock_mode) { |
5707 | if (!downclock_mode) { |
5720 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
5708 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
5721 | return NULL; |
5709 | return NULL; |
5722 | } |
5710 | } |
5723 | 5711 | ||
5724 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
5712 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
5725 | 5713 | ||
5726 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
5714 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
5727 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
5715 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
5728 | return downclock_mode; |
5716 | return downclock_mode; |
5729 | } |
5717 | } |
5730 | 5718 | ||
5731 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
5719 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
5732 | struct intel_connector *intel_connector) |
5720 | struct intel_connector *intel_connector) |
5733 | { |
5721 | { |
5734 | struct drm_connector *connector = &intel_connector->base; |
5722 | struct drm_connector *connector = &intel_connector->base; |
5735 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5723 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5736 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5724 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5737 | struct drm_device *dev = intel_encoder->base.dev; |
5725 | struct drm_device *dev = intel_encoder->base.dev; |
5738 | struct drm_i915_private *dev_priv = dev->dev_private; |
5726 | struct drm_i915_private *dev_priv = dev->dev_private; |
5739 | struct drm_display_mode *fixed_mode = NULL; |
5727 | struct drm_display_mode *fixed_mode = NULL; |
5740 | struct drm_display_mode *downclock_mode = NULL; |
5728 | struct drm_display_mode *downclock_mode = NULL; |
5741 | bool has_dpcd; |
5729 | bool has_dpcd; |
5742 | struct drm_display_mode *scan; |
5730 | struct drm_display_mode *scan; |
5743 | struct edid *edid; |
5731 | struct edid *edid; |
5744 | enum pipe pipe = INVALID_PIPE; |
5732 | enum pipe pipe = INVALID_PIPE; |
5745 | 5733 | ||
5746 | if (!is_edp(intel_dp)) |
5734 | if (!is_edp(intel_dp)) |
5747 | return true; |
5735 | return true; |
5748 | 5736 | ||
5749 | pps_lock(intel_dp); |
5737 | pps_lock(intel_dp); |
5750 | intel_edp_panel_vdd_sanitize(intel_dp); |
5738 | intel_edp_panel_vdd_sanitize(intel_dp); |
5751 | pps_unlock(intel_dp); |
5739 | pps_unlock(intel_dp); |
5752 | 5740 | ||
5753 | /* Cache DPCD and EDID for edp. */ |
5741 | /* Cache DPCD and EDID for edp. */ |
5754 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
5742 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
5755 | 5743 | ||
5756 | if (has_dpcd) { |
5744 | if (has_dpcd) { |
5757 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
5745 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
5758 | dev_priv->no_aux_handshake = |
5746 | dev_priv->no_aux_handshake = |
5759 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
5747 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
5760 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
5748 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
5761 | } else { |
5749 | } else { |
5762 | /* if this fails, presume the device is a ghost */ |
5750 | /* if this fails, presume the device is a ghost */ |
5763 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
5751 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
5764 | return false; |
5752 | return false; |
5765 | } |
5753 | } |
5766 | 5754 | ||
5767 | /* We now know it's not a ghost, init power sequence regs. */ |
5755 | /* We now know it's not a ghost, init power sequence regs. */ |
5768 | pps_lock(intel_dp); |
5756 | pps_lock(intel_dp); |
5769 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
5757 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
5770 | pps_unlock(intel_dp); |
5758 | pps_unlock(intel_dp); |
5771 | 5759 | ||
5772 | mutex_lock(&dev->mode_config.mutex); |
5760 | mutex_lock(&dev->mode_config.mutex); |
5773 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
5761 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
5774 | if (edid) { |
5762 | if (edid) { |
5775 | if (drm_add_edid_modes(connector, edid)) { |
5763 | if (drm_add_edid_modes(connector, edid)) { |
5776 | drm_mode_connector_update_edid_property(connector, |
5764 | drm_mode_connector_update_edid_property(connector, |
5777 | edid); |
5765 | edid); |
5778 | drm_edid_to_eld(connector, edid); |
5766 | drm_edid_to_eld(connector, edid); |
5779 | } else { |
5767 | } else { |
5780 | kfree(edid); |
5768 | kfree(edid); |
5781 | edid = ERR_PTR(-EINVAL); |
5769 | edid = ERR_PTR(-EINVAL); |
5782 | } |
5770 | } |
5783 | } else { |
5771 | } else { |
5784 | edid = ERR_PTR(-ENOENT); |
5772 | edid = ERR_PTR(-ENOENT); |
5785 | } |
5773 | } |
5786 | intel_connector->edid = edid; |
5774 | intel_connector->edid = edid; |
5787 | 5775 | ||
5788 | /* prefer fixed mode from EDID if available */ |
5776 | /* prefer fixed mode from EDID if available */ |
5789 | list_for_each_entry(scan, &connector->probed_modes, head) { |
5777 | list_for_each_entry(scan, &connector->probed_modes, head) { |
5790 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
5778 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
5791 | fixed_mode = drm_mode_duplicate(dev, scan); |
5779 | fixed_mode = drm_mode_duplicate(dev, scan); |
5792 | downclock_mode = intel_dp_drrs_init( |
5780 | downclock_mode = intel_dp_drrs_init( |
5793 | intel_connector, fixed_mode); |
5781 | intel_connector, fixed_mode); |
5794 | break; |
5782 | break; |
5795 | } |
5783 | } |
5796 | } |
5784 | } |
5797 | 5785 | ||
5798 | /* fallback to VBT if available for eDP */ |
5786 | /* fallback to VBT if available for eDP */ |
5799 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
5787 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
5800 | fixed_mode = drm_mode_duplicate(dev, |
5788 | fixed_mode = drm_mode_duplicate(dev, |
5801 | dev_priv->vbt.lfp_lvds_vbt_mode); |
5789 | dev_priv->vbt.lfp_lvds_vbt_mode); |
5802 | if (fixed_mode) |
5790 | if (fixed_mode) |
5803 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
5791 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
5804 | } |
5792 | } |
5805 | mutex_unlock(&dev->mode_config.mutex); |
5793 | mutex_unlock(&dev->mode_config.mutex); |
5806 | 5794 | ||
5807 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
5795 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
5808 | // intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5796 | // intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5809 | // register_reboot_notifier(&intel_dp->edp_notifier); |
5797 | // register_reboot_notifier(&intel_dp->edp_notifier); |
5810 | 5798 | ||
5811 | /* |
5799 | /* |
5812 | * Figure out the current pipe for the initial backlight setup. |
5800 | * Figure out the current pipe for the initial backlight setup. |
5813 | * If the current pipe isn't valid, try the PPS pipe, and if that |
5801 | * If the current pipe isn't valid, try the PPS pipe, and if that |
5814 | * fails just assume pipe A. |
5802 | * fails just assume pipe A. |
5815 | */ |
5803 | */ |
5816 | if (IS_CHERRYVIEW(dev)) |
5804 | if (IS_CHERRYVIEW(dev)) |
5817 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
5805 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
5818 | else |
5806 | else |
5819 | pipe = PORT_TO_PIPE(intel_dp->DP); |
5807 | pipe = PORT_TO_PIPE(intel_dp->DP); |
5820 | 5808 | ||
5821 | if (pipe != PIPE_A && pipe != PIPE_B) |
5809 | if (pipe != PIPE_A && pipe != PIPE_B) |
5822 | pipe = intel_dp->pps_pipe; |
5810 | pipe = intel_dp->pps_pipe; |
5823 | 5811 | ||
5824 | if (pipe != PIPE_A && pipe != PIPE_B) |
5812 | if (pipe != PIPE_A && pipe != PIPE_B) |
5825 | pipe = PIPE_A; |
5813 | pipe = PIPE_A; |
5826 | 5814 | ||
5827 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
5815 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
5828 | pipe_name(pipe)); |
5816 | pipe_name(pipe)); |
5829 | } |
5817 | } |
5830 | 5818 | ||
5831 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5819 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5832 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
5820 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
5833 | intel_panel_setup_backlight(connector, pipe); |
5821 | intel_panel_setup_backlight(connector, pipe); |
5834 | 5822 | ||
5835 | return true; |
5823 | return true; |
5836 | } |
5824 | } |
5837 | 5825 | ||
5838 | bool |
5826 | bool |
5839 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5827 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5840 | struct intel_connector *intel_connector) |
5828 | struct intel_connector *intel_connector) |
5841 | { |
5829 | { |
5842 | struct drm_connector *connector = &intel_connector->base; |
5830 | struct drm_connector *connector = &intel_connector->base; |
5843 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
5831 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
5844 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5832 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5845 | struct drm_device *dev = intel_encoder->base.dev; |
5833 | struct drm_device *dev = intel_encoder->base.dev; |
5846 | struct drm_i915_private *dev_priv = dev->dev_private; |
5834 | struct drm_i915_private *dev_priv = dev->dev_private; |
5847 | enum port port = intel_dig_port->port; |
5835 | enum port port = intel_dig_port->port; |
5848 | int type, ret; |
5836 | int type, ret; |
- | 5837 | ||
- | 5838 | if (WARN(intel_dig_port->max_lanes < 1, |
|
- | 5839 | "Not enough lanes (%d) for DP on port %c\n", |
|
- | 5840 | intel_dig_port->max_lanes, port_name(port))) |
|
- | 5841 | return false; |
|
5849 | 5842 | ||
5850 | intel_dp->pps_pipe = INVALID_PIPE; |
5843 | intel_dp->pps_pipe = INVALID_PIPE; |
5851 | 5844 | ||
5852 | /* intel_dp vfuncs */ |
5845 | /* intel_dp vfuncs */ |
5853 | if (INTEL_INFO(dev)->gen >= 9) |
5846 | if (INTEL_INFO(dev)->gen >= 9) |
5854 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
5847 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
5855 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5848 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5856 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
5849 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
5857 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
5850 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
5858 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
5851 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
5859 | else if (HAS_PCH_SPLIT(dev)) |
5852 | else if (HAS_PCH_SPLIT(dev)) |
5860 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
5853 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
5861 | else |
5854 | else |
5862 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
5855 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
5863 | 5856 | ||
5864 | if (INTEL_INFO(dev)->gen >= 9) |
5857 | if (INTEL_INFO(dev)->gen >= 9) |
5865 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
5858 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
5866 | else |
5859 | else |
5867 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
5860 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
5868 | 5861 | ||
5869 | if (HAS_DDI(dev)) |
5862 | if (HAS_DDI(dev)) |
5870 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
5863 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
5871 | 5864 | ||
5872 | /* Preserve the current hw state. */ |
5865 | /* Preserve the current hw state. */ |
5873 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
5866 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
5874 | intel_dp->attached_connector = intel_connector; |
5867 | intel_dp->attached_connector = intel_connector; |
5875 | 5868 | ||
5876 | if (intel_dp_is_edp(dev, port)) |
5869 | if (intel_dp_is_edp(dev, port)) |
5877 | type = DRM_MODE_CONNECTOR_eDP; |
5870 | type = DRM_MODE_CONNECTOR_eDP; |
5878 | else |
5871 | else |
5879 | type = DRM_MODE_CONNECTOR_DisplayPort; |
5872 | type = DRM_MODE_CONNECTOR_DisplayPort; |
5880 | 5873 | ||
5881 | /* |
5874 | /* |
5882 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
5875 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
5883 | * for DP the encoder type can be set by the caller to |
5876 | * for DP the encoder type can be set by the caller to |
5884 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
5877 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
5885 | */ |
5878 | */ |
5886 | if (type == DRM_MODE_CONNECTOR_eDP) |
5879 | if (type == DRM_MODE_CONNECTOR_eDP) |
5887 | intel_encoder->type = INTEL_OUTPUT_EDP; |
5880 | intel_encoder->type = INTEL_OUTPUT_EDP; |
5888 | 5881 | ||
5889 | /* eDP only on port B and/or C on vlv/chv */ |
5882 | /* eDP only on port B and/or C on vlv/chv */ |
5890 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
5883 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
5891 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
5884 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
5892 | return false; |
5885 | return false; |
5893 | 5886 | ||
5894 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5887 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5895 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
5888 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
5896 | port_name(port)); |
5889 | port_name(port)); |
5897 | 5890 | ||
5898 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
5891 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
5899 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5892 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5900 | 5893 | ||
5901 | connector->interlace_allowed = true; |
5894 | connector->interlace_allowed = true; |
5902 | connector->doublescan_allowed = 0; |
5895 | connector->doublescan_allowed = 0; |
5903 | 5896 | ||
5904 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
5897 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
5905 | edp_panel_vdd_work); |
5898 | edp_panel_vdd_work); |
5906 | 5899 | ||
5907 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
5900 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
5908 | drm_connector_register(connector); |
5901 | drm_connector_register(connector); |
5909 | 5902 | ||
5910 | if (HAS_DDI(dev)) |
5903 | if (HAS_DDI(dev)) |
5911 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5904 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5912 | else |
5905 | else |
5913 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5906 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5914 | intel_connector->unregister = intel_dp_connector_unregister; |
5907 | intel_connector->unregister = intel_dp_connector_unregister; |
5915 | 5908 | ||
5916 | /* Set up the hotplug pin. */ |
5909 | /* Set up the hotplug pin. */ |
5917 | switch (port) { |
5910 | switch (port) { |
5918 | case PORT_A: |
5911 | case PORT_A: |
5919 | intel_encoder->hpd_pin = HPD_PORT_A; |
5912 | intel_encoder->hpd_pin = HPD_PORT_A; |
5920 | break; |
5913 | break; |
5921 | case PORT_B: |
5914 | case PORT_B: |
5922 | intel_encoder->hpd_pin = HPD_PORT_B; |
5915 | intel_encoder->hpd_pin = HPD_PORT_B; |
5923 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
5916 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
5924 | intel_encoder->hpd_pin = HPD_PORT_A; |
5917 | intel_encoder->hpd_pin = HPD_PORT_A; |
5925 | break; |
5918 | break; |
5926 | case PORT_C: |
5919 | case PORT_C: |
5927 | intel_encoder->hpd_pin = HPD_PORT_C; |
5920 | intel_encoder->hpd_pin = HPD_PORT_C; |
5928 | break; |
5921 | break; |
5929 | case PORT_D: |
5922 | case PORT_D: |
5930 | intel_encoder->hpd_pin = HPD_PORT_D; |
5923 | intel_encoder->hpd_pin = HPD_PORT_D; |
5931 | break; |
5924 | break; |
5932 | case PORT_E: |
5925 | case PORT_E: |
5933 | intel_encoder->hpd_pin = HPD_PORT_E; |
5926 | intel_encoder->hpd_pin = HPD_PORT_E; |
5934 | break; |
5927 | break; |
5935 | default: |
5928 | default: |
5936 | BUG(); |
5929 | BUG(); |
5937 | } |
5930 | } |
5938 | 5931 | ||
5939 | if (is_edp(intel_dp)) { |
5932 | if (is_edp(intel_dp)) { |
5940 | pps_lock(intel_dp); |
5933 | pps_lock(intel_dp); |
5941 | intel_dp_init_panel_power_timestamps(intel_dp); |
5934 | intel_dp_init_panel_power_timestamps(intel_dp); |
5942 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5935 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5943 | vlv_initial_power_sequencer_setup(intel_dp); |
5936 | vlv_initial_power_sequencer_setup(intel_dp); |
5944 | else |
5937 | else |
5945 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5938 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5946 | pps_unlock(intel_dp); |
5939 | pps_unlock(intel_dp); |
5947 | } |
5940 | } |
5948 | 5941 | ||
5949 | ret = intel_dp_aux_init(intel_dp, intel_connector); |
5942 | ret = intel_dp_aux_init(intel_dp, intel_connector); |
5950 | if (ret) |
5943 | if (ret) |
5951 | goto fail; |
5944 | goto fail; |
5952 | 5945 | ||
5953 | /* init MST on ports that can support it */ |
5946 | /* init MST on ports that can support it */ |
5954 | if (HAS_DP_MST(dev) && |
5947 | if (HAS_DP_MST(dev) && |
5955 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
5948 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
5956 | intel_dp_mst_encoder_init(intel_dig_port, |
5949 | intel_dp_mst_encoder_init(intel_dig_port, |
5957 | intel_connector->base.base.id); |
5950 | intel_connector->base.base.id); |
5958 | 5951 | ||
5959 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
5952 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
5960 | intel_dp_aux_fini(intel_dp); |
5953 | intel_dp_aux_fini(intel_dp); |
5961 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
5954 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
5962 | goto fail; |
5955 | goto fail; |
5963 | } |
5956 | } |
5964 | 5957 | ||
5965 | intel_dp_add_properties(intel_dp, connector); |
5958 | intel_dp_add_properties(intel_dp, connector); |
5966 | 5959 | ||
5967 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
5960 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
5968 | * 0xd. Failure to do so will result in spurious interrupts being |
5961 | * 0xd. Failure to do so will result in spurious interrupts being |
5969 | * generated on the port when a cable is not attached. |
5962 | * generated on the port when a cable is not attached. |
5970 | */ |
5963 | */ |
5971 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
5964 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
5972 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
5965 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
5973 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
5966 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
5974 | } |
5967 | } |
5975 | 5968 | ||
5976 | i915_debugfs_connector_add(connector); |
5969 | i915_debugfs_connector_add(connector); |
5977 | 5970 | ||
5978 | return true; |
5971 | return true; |
5979 | 5972 | ||
5980 | fail: |
5973 | fail: |
5981 | if (is_edp(intel_dp)) { |
5974 | if (is_edp(intel_dp)) { |
5982 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
5975 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
5983 | /* |
5976 | /* |
5984 | * vdd might still be enabled do to the delayed vdd off. |
5977 | * vdd might still be enabled do to the delayed vdd off. |
5985 | * Make sure vdd is actually turned off here. |
5978 | * Make sure vdd is actually turned off here. |
5986 | */ |
5979 | */ |
5987 | pps_lock(intel_dp); |
5980 | pps_lock(intel_dp); |
5988 | edp_panel_vdd_off_sync(intel_dp); |
5981 | edp_panel_vdd_off_sync(intel_dp); |
5989 | pps_unlock(intel_dp); |
5982 | pps_unlock(intel_dp); |
5990 | } |
5983 | } |
5991 | drm_connector_unregister(connector); |
5984 | drm_connector_unregister(connector); |
5992 | drm_connector_cleanup(connector); |
5985 | drm_connector_cleanup(connector); |
5993 | 5986 | ||
5994 | return false; |
5987 | return false; |
5995 | } |
5988 | } |
5996 | 5989 | ||
5997 | void |
5990 | void |
5998 | intel_dp_init(struct drm_device *dev, |
5991 | intel_dp_init(struct drm_device *dev, |
5999 | i915_reg_t output_reg, enum port port) |
5992 | i915_reg_t output_reg, enum port port) |
6000 | { |
5993 | { |
6001 | struct drm_i915_private *dev_priv = dev->dev_private; |
5994 | struct drm_i915_private *dev_priv = dev->dev_private; |
6002 | struct intel_digital_port *intel_dig_port; |
5995 | struct intel_digital_port *intel_dig_port; |
6003 | struct intel_encoder *intel_encoder; |
5996 | struct intel_encoder *intel_encoder; |
6004 | struct drm_encoder *encoder; |
5997 | struct drm_encoder *encoder; |
6005 | struct intel_connector *intel_connector; |
5998 | struct intel_connector *intel_connector; |
6006 | 5999 | ||
6007 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
6000 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
6008 | if (!intel_dig_port) |
6001 | if (!intel_dig_port) |
6009 | return; |
6002 | return; |
6010 | 6003 | ||
6011 | intel_connector = intel_connector_alloc(); |
6004 | intel_connector = intel_connector_alloc(); |
6012 | if (!intel_connector) |
6005 | if (!intel_connector) |
6013 | goto err_connector_alloc; |
6006 | goto err_connector_alloc; |
6014 | 6007 | ||
6015 | intel_encoder = &intel_dig_port->base; |
6008 | intel_encoder = &intel_dig_port->base; |
6016 | encoder = &intel_encoder->base; |
6009 | encoder = &intel_encoder->base; |
6017 | 6010 | ||
6018 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
6011 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
6019 | DRM_MODE_ENCODER_TMDS, NULL)) |
6012 | DRM_MODE_ENCODER_TMDS, NULL)) |
6020 | goto err_encoder_init; |
6013 | goto err_encoder_init; |
6021 | 6014 | ||
6022 | intel_encoder->compute_config = intel_dp_compute_config; |
6015 | intel_encoder->compute_config = intel_dp_compute_config; |
6023 | intel_encoder->disable = intel_disable_dp; |
6016 | intel_encoder->disable = intel_disable_dp; |
6024 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
6017 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
6025 | intel_encoder->get_config = intel_dp_get_config; |
6018 | intel_encoder->get_config = intel_dp_get_config; |
6026 | intel_encoder->suspend = intel_dp_encoder_suspend; |
6019 | intel_encoder->suspend = intel_dp_encoder_suspend; |
6027 | if (IS_CHERRYVIEW(dev)) { |
6020 | if (IS_CHERRYVIEW(dev)) { |
6028 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
6021 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
6029 | intel_encoder->pre_enable = chv_pre_enable_dp; |
6022 | intel_encoder->pre_enable = chv_pre_enable_dp; |
6030 | intel_encoder->enable = vlv_enable_dp; |
6023 | intel_encoder->enable = vlv_enable_dp; |
6031 | intel_encoder->post_disable = chv_post_disable_dp; |
6024 | intel_encoder->post_disable = chv_post_disable_dp; |
6032 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
6025 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
6033 | } else if (IS_VALLEYVIEW(dev)) { |
6026 | } else if (IS_VALLEYVIEW(dev)) { |
6034 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
6027 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
6035 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
6028 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
6036 | intel_encoder->enable = vlv_enable_dp; |
6029 | intel_encoder->enable = vlv_enable_dp; |
6037 | intel_encoder->post_disable = vlv_post_disable_dp; |
6030 | intel_encoder->post_disable = vlv_post_disable_dp; |
6038 | } else { |
6031 | } else { |
6039 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
6032 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
6040 | intel_encoder->enable = g4x_enable_dp; |
6033 | intel_encoder->enable = g4x_enable_dp; |
6041 | if (INTEL_INFO(dev)->gen >= 5) |
6034 | if (INTEL_INFO(dev)->gen >= 5) |
6042 | intel_encoder->post_disable = ilk_post_disable_dp; |
6035 | intel_encoder->post_disable = ilk_post_disable_dp; |
6043 | } |
6036 | } |
6044 | 6037 | ||
6045 | intel_dig_port->port = port; |
6038 | intel_dig_port->port = port; |
6046 | intel_dig_port->dp.output_reg = output_reg; |
6039 | intel_dig_port->dp.output_reg = output_reg; |
- | 6040 | intel_dig_port->max_lanes = 4; |
|
6047 | 6041 | ||
6048 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
6042 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
6049 | if (IS_CHERRYVIEW(dev)) { |
6043 | if (IS_CHERRYVIEW(dev)) { |
6050 | if (port == PORT_D) |
6044 | if (port == PORT_D) |
6051 | intel_encoder->crtc_mask = 1 << 2; |
6045 | intel_encoder->crtc_mask = 1 << 2; |
6052 | else |
6046 | else |
6053 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
6047 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
6054 | } else { |
6048 | } else { |
6055 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
6049 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
6056 | } |
6050 | } |
6057 | intel_encoder->cloneable = 0; |
6051 | intel_encoder->cloneable = 0; |
6058 | 6052 | ||
6059 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
6053 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
6060 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
6054 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
6061 | 6055 | ||
6062 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
6056 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
6063 | goto err_init_connector; |
6057 | goto err_init_connector; |
6064 | 6058 | ||
6065 | return; |
6059 | return; |
6066 | 6060 | ||
6067 | err_init_connector: |
6061 | err_init_connector: |
6068 | drm_encoder_cleanup(encoder); |
6062 | drm_encoder_cleanup(encoder); |
6069 | err_encoder_init: |
6063 | err_encoder_init: |
6070 | kfree(intel_connector); |
6064 | kfree(intel_connector); |
6071 | err_connector_alloc: |
6065 | err_connector_alloc: |
6072 | kfree(intel_dig_port); |
6066 | kfree(intel_dig_port); |
6073 | 6067 | ||
6074 | return; |
6068 | return; |
6075 | } |
6069 | } |
6076 | 6070 | ||
6077 | void intel_dp_mst_suspend(struct drm_device *dev) |
6071 | void intel_dp_mst_suspend(struct drm_device *dev) |
6078 | { |
6072 | { |
6079 | struct drm_i915_private *dev_priv = dev->dev_private; |
6073 | struct drm_i915_private *dev_priv = dev->dev_private; |
6080 | int i; |
6074 | int i; |
6081 | 6075 | ||
6082 | /* disable MST */ |
6076 | /* disable MST */ |
6083 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6077 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6084 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6078 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6085 | if (!intel_dig_port) |
6079 | if (!intel_dig_port) |
6086 | continue; |
6080 | continue; |
6087 | 6081 | ||
6088 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6082 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6089 | if (!intel_dig_port->dp.can_mst) |
6083 | if (!intel_dig_port->dp.can_mst) |
6090 | continue; |
6084 | continue; |
6091 | if (intel_dig_port->dp.is_mst) |
6085 | if (intel_dig_port->dp.is_mst) |
6092 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
6086 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
6093 | } |
6087 | } |
6094 | } |
6088 | } |
6095 | } |
6089 | } |
6096 | 6090 | ||
6097 | void intel_dp_mst_resume(struct drm_device *dev) |
6091 | void intel_dp_mst_resume(struct drm_device *dev) |
6098 | { |
6092 | { |
6099 | struct drm_i915_private *dev_priv = dev->dev_private; |
6093 | struct drm_i915_private *dev_priv = dev->dev_private; |
6100 | int i; |
6094 | int i; |
6101 | 6095 | ||
6102 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6096 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6103 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6097 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6104 | if (!intel_dig_port) |
6098 | if (!intel_dig_port) |
6105 | continue; |
6099 | continue; |
6106 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6100 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6107 | int ret; |
6101 | int ret; |
6108 | 6102 | ||
6109 | if (!intel_dig_port->dp.can_mst) |
6103 | if (!intel_dig_port->dp.can_mst) |
6110 | continue; |
6104 | continue; |
6111 | 6105 | ||
6112 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
6106 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
6113 | if (ret != 0) { |
6107 | if (ret != 0) { |
6114 | intel_dp_check_mst_status(&intel_dig_port->dp); |
6108 | intel_dp_check_mst_status(&intel_dig_port->dp); |
6115 | } |
6109 | } |
6116 | } |
6110 | } |
6117 | } |
6111 | } |
6118 | }>>><>><>><>><>><>><>=>>=>><>><>><>><>><>><>><>>>>>=>=>>>>>>>>>>>>>>><>><>><>>><>>>><>> |
6112 | }>>><>><>><>><>><>><>>=>>=>><>><>><>><>><>><>><>>>>>=>=>>>>>>>>>>>>>>><>><>><>>><>>>><>> |
6119 | ><21); |
6113 | ><21); |
6120 | >21); |
6114 | >21); |
6121 | ><21); |
6115 | ><21); |
6122 | >>>>><>=>=><=>=>=>>=>=>>>>>>>>>>><>>>>>><>><>><>><>=>><>><>><>>><>>>><>><>><>><>><> |
6116 | >>>>>><>=>=><=>=>=>>=>=>>>>>>>>>><>>>>>><>><>><>><>=>><>><>><>>><>>>><>><>><>><>><> |