WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_irq.c


/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
 */
/*
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */
 
#define pr_fmt(fmt) ": " fmt
 
#include 
#include 
#include 
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
 
 
#define pr_err(fmt, ...) \
        printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
 
 
#define DRM_WAKEUP( queue ) wake_up( queue )
#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )
 
#define MAX_NOPID ((u32)~0)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/* For display hotplug interrupt */
static void
ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
{
    if ((dev_priv->irq_mask & mask) != 0) {
        dev_priv->irq_mask &= ~mask;
        I915_WRITE(DEIMR, dev_priv->irq_mask);
        POSTING_READ(DEIMR);
    }
}
 
static inline void
ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
{
    if ((dev_priv->irq_mask & mask) != mask) {
        dev_priv->irq_mask |= mask;
        I915_WRITE(DEIMR, dev_priv->irq_mask);
        POSTING_READ(DEIMR);
    }
}
 
void
i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
{
	if ((dev_priv->pipestat[pipe] & mask) != mask) {
		u32 reg = PIPESTAT(pipe);
 
		dev_priv->pipestat[pipe] |= mask;
		/* Enable the interrupt, clear any pending status */
		I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
		POSTING_READ(reg);
	}
}
 
void
i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
{
	if ((dev_priv->pipestat[pipe] & mask) != 0) {
		u32 reg = PIPESTAT(pipe);
 
		dev_priv->pipestat[pipe] &= ~mask;
		I915_WRITE(reg, dev_priv->pipestat[pipe]);
		POSTING_READ(reg);
	}
}
 
#if 0
/**
 * intel_enable_asle - enable ASLE interrupt for OpRegion
 */
void intel_enable_asle(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	unsigned long irqflags;
 
	/* FIXME: opregion/asle for VLV */
	if (IS_VALLEYVIEW(dev))
		return;
 
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 
	if (HAS_PCH_SPLIT(dev))
		ironlake_enable_display_irq(dev_priv, DE_GSE);
	else {
		i915_enable_pipestat(dev_priv, 1,
				     PIPE_LEGACY_BLC_EVENT_ENABLE);
		if (INTEL_INFO(dev)->gen >= 4)
			i915_enable_pipestat(dev_priv, 0,
					     PIPE_LEGACY_BLC_EVENT_ENABLE);
	}
 
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
#endif
 
/**
 * i915_pipe_enabled - check if a pipe is enabled
 * @dev: DRM device
 * @pipe: pipe to check
 *
 * Reading certain registers when the pipe is disabled can hang the chip.
 * Use this routine to make sure the PLL is running and the pipe is active
 * before reading such registers if unsure.
 */
static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
 
	return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
}
 
/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long high_frame;
	unsigned long low_frame;
	u32 high1, high2, low;
 
	if (!i915_pipe_enabled(dev, pipe)) {
		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
				"pipe %c\n", pipe_name(pipe));
		return 0;
	}
 
	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
 
	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
		low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
	} while (high1 != high2);
 
	high1 >>= PIPE_FRAME_HIGH_SHIFT;
	low >>= PIPE_FRAME_LOW_SHIFT;
	return (high1 << 8) | low;
}
 
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int reg = PIPE_FRMCOUNT_GM45(pipe);
 
	if (!i915_pipe_enabled(dev, pipe)) {
		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
				 "pipe %c\n", pipe_name(pipe));
		return 0;
	}
 
	return I915_READ(reg);
}
 
/*
 * Handle hotplug events outside the interrupt handler proper.
 */
static void i915_hotplug_work_func(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    hotplug_work);
	struct drm_device *dev = dev_priv->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
 
	/* HPD irq before everything is fully set up. */
	if (!dev_priv->enable_hotplug_processing)
		return;
 
	mutex_lock(&mode_config->mutex);
	DRM_DEBUG_KMS("running encoder hotplug functions\n");
 
	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
		if (encoder->hot_plug)
			encoder->hot_plug(encoder);
 
	mutex_unlock(&mode_config->mutex);
 
	/* Just fire off a uevent and let userspace tell us what to do */
	drm_helper_hpd_irq_event(dev);
}
 
static void notify_ring(struct drm_device *dev,
			struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	if (ring->obj == NULL)
		return;
 
	trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 
	wake_up_all(&ring->irq_queue);
//   if (i915_enable_hangcheck) {
//       dev_priv->hangcheck_count = 0;
//       mod_timer(&dev_priv->hangcheck_timer,
//             jiffies +
//             msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
//   }
}
 
#if 0
static void gen6_pm_rps_work(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    rps.work);
	u32 pm_iir, pm_imr;
	u8 new_delay;
 
	spin_lock_irq(&dev_priv->rps.lock);
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
	pm_imr = I915_READ(GEN6_PMIMR);
	I915_WRITE(GEN6_PMIMR, 0);
	spin_unlock_irq(&dev_priv->rps.lock);
 
	if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
		return;
 
	mutex_lock(&dev_priv->rps.hw_lock);
 
	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
		new_delay = dev_priv->rps.cur_delay + 1;
	else
		new_delay = dev_priv->rps.cur_delay - 1;
 
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
	if (!(new_delay > dev_priv->rps.max_delay ||
	      new_delay < dev_priv->rps.min_delay)) {
		gen6_set_rps(dev_priv->dev, new_delay);
	}
 
	mutex_unlock(&dev_priv->rps.hw_lock);
}
 
 
/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    l3_parity.error_work);
	u32 error_status, row, bank, subbank;
	char *parity_event[5];
	uint32_t misccpctl;
	unsigned long flags;
 
	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);
 
	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);
 
	error_status = I915_READ(GEN7_L3CDERRST1);
	row = GEN7_PARITY_ERROR_ROW(error_status);
	bank = GEN7_PARITY_ERROR_BANK(error_status);
	subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 
	I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
				    GEN7_L3CDERRST1_ENABLE);
	POSTING_READ(GEN7_L3CDERRST1);
 
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 
	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 
	mutex_unlock(&dev_priv->dev->struct_mutex);
 
	parity_event[0] = "L3_PARITY_ERROR=1";
	parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
	parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
	parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
	parity_event[4] = NULL;
 
	kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
			   KOBJ_CHANGE, parity_event);
 
	DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
		  row, bank, subbank);
 
	kfree(parity_event[3]);
	kfree(parity_event[2]);
	kfree(parity_event[1]);
}
 
static void ivybridge_handle_parity_error(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long flags;
 
	if (!HAS_L3_GPU_CACHE(dev))
		return;
 
	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
}
 
#endif
 
static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
//    printf("%s\n", __FUNCTION__);
 
	if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
		      GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
		notify_ring(dev, &dev_priv->ring[RCS]);
	if (gt_iir & GEN6_BSD_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[VCS]);
	if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[BCS]);
 
	if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
		      GT_GEN6_BSD_CS_ERROR_INTERRUPT |
		      GT_RENDER_CS_ERROR_INTERRUPT)) {
		DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
		i915_handle_error(dev, false);
	}
 
//	if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
//		ivybridge_handle_parity_error(dev);
}
 
static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
				u32 pm_iir)
{
	unsigned long flags;
 
	/*
	 * IIR bits should never already be set because IMR should
	 * prevent an interrupt from being shown in IIR. The warning
	 * displays a case where we've unsafely cleared
	 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
	 * type is not a problem, it displays a problem in the logic.
	 *
	 * The mask bit in IMR is cleared by dev_priv->rps.work.
	 */
 
	spin_lock_irqsave(&dev_priv->rps.lock, flags);
	dev_priv->rps.pm_iir |= pm_iir;
	I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
	POSTING_READ(GEN6_PMIMR);
	spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 
//   queue_work(dev_priv->wq, &dev_priv->rps.work);
}
 
static void gmbus_irq_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
	wake_up_all(&dev_priv->gmbus_wait_queue);
}
 
static void dp_aux_irq_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
	wake_up_all(&dev_priv->gmbus_wait_queue);
}
 
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;
	unsigned long irqflags;
	int pipe;
	u32 pipe_stats[I915_MAX_PIPES];
 
 
	atomic_inc(&dev_priv->irq_received);
 
	while (true) {
		iir = I915_READ(VLV_IIR);
		gt_iir = I915_READ(GTIIR);
		pm_iir = I915_READ(GEN6_PMIIR);
 
		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;
 
		ret = IRQ_HANDLED;
 
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
 
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);
 
			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
#if 0
		for_each_pipe(pipe) {
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
				drm_handle_vblank(dev, pipe);
 
			if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
				intel_prepare_page_flip(dev, pipe);
				intel_finish_page_flip(dev, pipe);
			}
		}
#endif
 
		/* Consume port.  Then clear IIR or we'll miss events */
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 
			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
					 hotplug_status);
			if (hotplug_status & dev_priv->hotplug_supported_mask)
				queue_work(dev_priv->wq,
					   &dev_priv->hotplug_work);
 
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}
 
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);
 
//        if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
//            gen6_queue_rps_work(dev_priv, pm_iir);
 
		I915_WRITE(GTIIR, gt_iir);
		I915_WRITE(GEN6_PMIIR, pm_iir);
		I915_WRITE(VLV_IIR, iir);
	}
 
out:
	return ret;
}
 
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
 
	if (pch_iir & SDE_HOTPLUG_MASK)
		queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 
	if (pch_iir & SDE_AUDIO_POWER_MASK)
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
				 (pch_iir & SDE_AUDIO_POWER_MASK) >>
				 SDE_AUDIO_POWER_SHIFT);
 
	if (pch_iir & SDE_AUX_MASK)
		dp_aux_irq_handler(dev);
 
	if (pch_iir & SDE_GMBUS)
		gmbus_irq_handler(dev);
 
	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 
	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 
	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");
 
	if (pch_iir & SDE_FDI_MASK)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
 
	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 
	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 
	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
		DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
		DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
}
 
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
 
	if (pch_iir & SDE_HOTPLUG_MASK_CPT)
		queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
				 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
				 SDE_AUDIO_POWER_SHIFT_CPT);
 
	if (pch_iir & SDE_AUX_MASK_CPT)
		dp_aux_irq_handler(dev);
 
	if (pch_iir & SDE_GMBUS_CPT)
		gmbus_irq_handler(dev);
 
	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 
	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 
	if (pch_iir & SDE_FDI_MASK_CPT)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
}
 
static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
	irqreturn_t ret = IRQ_NONE;
	int i;
 
	atomic_inc(&dev_priv->irq_received);
 
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
	sde_ier = I915_READ(SDEIER);
	I915_WRITE(SDEIER, 0);
	POSTING_READ(SDEIER);
 
	gt_iir = I915_READ(GTIIR);
	if (gt_iir) {
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
	}
 
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
		if (de_iir & DE_AUX_CHANNEL_A_IVB)
			dp_aux_irq_handler(dev);
#if 0
		if (de_iir & DE_GSE_IVB)
			intel_opregion_gse_intr(dev);
 
		for (i = 0; i < 3; i++) {
			if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
				drm_handle_vblank(dev, i);
			if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
				intel_prepare_page_flip(dev, i);
				intel_finish_page_flip_plane(dev, i);
			}
		}
#endif
		/* check event from PCH */
		if (de_iir & DE_PCH_EVENT_IVB) {
			u32 pch_iir = I915_READ(SDEIIR);
 
 
 
			cpt_irq_handler(dev, pch_iir);
 
			/* clear PCH hotplug event before clear CPU irq */
			I915_WRITE(SDEIIR, pch_iir);
		}
 
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
	}
 
	pm_iir = I915_READ(GEN6_PMIIR);
	if (pm_iir) {
//		if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
//			gen6_queue_rps_work(dev_priv, pm_iir);
		I915_WRITE(GEN6_PMIIR, pm_iir);
		ret = IRQ_HANDLED;
	}
 
	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
	I915_WRITE(SDEIER, sde_ier);
	POSTING_READ(SDEIER);
 
	return ret;
}
 
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
	if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
		notify_ring(dev, &dev_priv->ring[RCS]);
	if (gt_iir & GT_BSD_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[VCS]);
}
 
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = (struct drm_device *) arg;
    drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
    int ret = IRQ_NONE;
	u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
 
    atomic_inc(&dev_priv->irq_received);
 
    /* disable master interrupt before clearing iir  */
    de_ier = I915_READ(DEIER);
    I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
    POSTING_READ(DEIER);
 
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
	sde_ier = I915_READ(SDEIER);
	I915_WRITE(SDEIER, 0);
	POSTING_READ(SDEIER);
 
    de_iir = I915_READ(DEIIR);
 
    gt_iir = I915_READ(GTIIR);
    pm_iir = I915_READ(GEN6_PMIIR);
 
 
	if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
        goto done;
 
    ret = IRQ_HANDLED;
 
	if (IS_GEN5(dev))
		ilk_gt_irq_handler(dev, dev_priv, gt_iir);
	else
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
 
	if (de_iir & DE_AUX_CHANNEL_A)
		dp_aux_irq_handler(dev);
 
#if 0
	if (de_iir & DE_GSE)
		intel_opregion_gse_intr(dev);
 
	if (de_iir & DE_PIPEA_VBLANK)
		drm_handle_vblank(dev, 0);
 
	if (de_iir & DE_PIPEB_VBLANK)
		drm_handle_vblank(dev, 1);
 
	if (de_iir & DE_PLANEA_FLIP_DONE) {
		intel_prepare_page_flip(dev, 0);
		intel_finish_page_flip_plane(dev, 0);
	}
 
	if (de_iir & DE_PLANEB_FLIP_DONE) {
		intel_prepare_page_flip(dev, 1);
		intel_finish_page_flip_plane(dev, 1);
	}
#endif
 
	/* check event from PCH */
	if (de_iir & DE_PCH_EVENT) {
		u32 pch_iir = I915_READ(SDEIIR);
 
 
		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);
 
		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}
#if 0
	if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
		ironlake_handle_rps_change(dev);
 
	if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
		gen6_queue_rps_work(dev_priv, pm_iir);
#endif
 
 
    I915_WRITE(GTIIR, gt_iir);
    I915_WRITE(DEIIR, de_iir);
    I915_WRITE(GEN6_PMIIR, pm_iir);
 
done:
    I915_WRITE(DEIER, de_ier);
    POSTING_READ(DEIER);
	I915_WRITE(SDEIER, sde_ier);
	POSTING_READ(SDEIER);
 
    return ret;
}
 
 
 
 
/* NB: please notice the memset */
static void i915_get_extra_instdone(struct drm_device *dev,
				    uint32_t *instdone)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
 
	switch(INTEL_INFO(dev)->gen) {
	case 2:
	case 3:
		instdone[0] = I915_READ(INSTDONE);
		break;
	case 4:
	case 5:
	case 6:
		instdone[0] = I915_READ(INSTDONE_I965);
		instdone[1] = I915_READ(INSTDONE1);
		break;
	default:
		WARN_ONCE(1, "Unsupported platform\n");
	case 7:
		instdone[0] = I915_READ(GEN7_INSTDONE_1);
		instdone[1] = I915_READ(GEN7_SC_INSTDONE);
		instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
		instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
		break;
	}
}
 
#ifdef CONFIG_DEBUG_FS
static struct drm_i915_error_object *
i915_error_object_create(struct drm_i915_private *dev_priv,
			 struct drm_i915_gem_object *src)
{
	struct drm_i915_error_object *dst;
	int i, count;
	u32 reloc_offset;
 
	if (src == NULL || src->pages == NULL)
		return NULL;
 
	count = src->base.size / PAGE_SIZE;
 
	dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
	if (dst == NULL)
		return NULL;
 
	reloc_offset = src->gtt_offset;
	for (i = 0; i < count; i++) {
		unsigned long flags;
		void *d;
 
		d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
		if (d == NULL)
			goto unwind;
 
		local_irq_save(flags);
		if (reloc_offset < dev_priv->gtt.mappable_end &&
		    src->has_global_gtt_mapping) {
			void __iomem *s;
 
			/* Simply ignore tiling or any overlapping fence.
			 * It's part of the error state, and this hopefully
			 * captures what the GPU read.
			 */
 
			s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
						     reloc_offset);
			memcpy_fromio(d, s, PAGE_SIZE);
			io_mapping_unmap_atomic(s);
		} else if (src->stolen) {
			unsigned long offset;
 
			offset = dev_priv->mm.stolen_base;
			offset += src->stolen->start;
			offset += i << PAGE_SHIFT;
 
			memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
		} else {
			struct page *page;
			void *s;
 
			page = i915_gem_object_get_page(src, i);
 
			drm_clflush_pages(&page, 1);
 
			s = kmap_atomic(page);
			memcpy(d, s, PAGE_SIZE);
			kunmap_atomic(s);
 
			drm_clflush_pages(&page, 1);
		}
		local_irq_restore(flags);
 
		dst->pages[i] = d;
 
		reloc_offset += PAGE_SIZE;
	}
	dst->page_count = count;
	dst->gtt_offset = src->gtt_offset;
 
	return dst;
 
unwind:
	while (i--)
		kfree(dst->pages[i]);
	kfree(dst);
	return NULL;
}
 
static void
i915_error_object_free(struct drm_i915_error_object *obj)
{
	int page;
 
	if (obj == NULL)
		return;
 
	for (page = 0; page < obj->page_count; page++)
		kfree(obj->pages[page]);
 
	kfree(obj);
}
 
void
i915_error_state_free(struct kref *error_ref)
{
	struct drm_i915_error_state *error = container_of(error_ref,
							  typeof(*error), ref);
	int i;
 
	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		i915_error_object_free(error->ring[i].batchbuffer);
		i915_error_object_free(error->ring[i].ringbuffer);
		kfree(error->ring[i].requests);
	}
 
	kfree(error->active_bo);
	kfree(error->overlay);
	kfree(error);
}
static void capture_bo(struct drm_i915_error_buffer *err,
		       struct drm_i915_gem_object *obj)
{
	err->size = obj->base.size;
	err->name = obj->base.name;
	err->rseqno = obj->last_read_seqno;
	err->wseqno = obj->last_write_seqno;
	err->gtt_offset = obj->gtt_offset;
	err->read_domains = obj->base.read_domains;
	err->write_domain = obj->base.write_domain;
	err->fence_reg = obj->fence_reg;
	err->pinned = 0;
	if (obj->pin_count > 0)
		err->pinned = 1;
	if (obj->user_pin_count > 0)
		err->pinned = -1;
	err->tiling = obj->tiling_mode;
	err->dirty = obj->dirty;
	err->purgeable = obj->madv != I915_MADV_WILLNEED;
	err->ring = obj->ring ? obj->ring->id : -1;
	err->cache_level = obj->cache_level;
}
 
static u32 capture_active_bo(struct drm_i915_error_buffer *err,
			     int count, struct list_head *head)
{
	struct drm_i915_gem_object *obj;
	int i = 0;
 
	list_for_each_entry(obj, head, mm_list) {
		capture_bo(err++, obj);
		if (++i == count)
			break;
	}
 
	return i;
}
 
static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
			     int count, struct list_head *head)
{
	struct drm_i915_gem_object *obj;
	int i = 0;
 
	list_for_each_entry(obj, head, gtt_list) {
		if (obj->pin_count == 0)
			continue;
 
		capture_bo(err++, obj);
		if (++i == count)
			break;
	}
 
	return i;
}
 
static void i915_gem_record_fences(struct drm_device *dev,
				   struct drm_i915_error_state *error)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;
 
	/* Fences */
	switch (INTEL_INFO(dev)->gen) {
	case 7:
	case 6:
		for (i = 0; i < 16; i++)
			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
		break;
	case 5:
	case 4:
		for (i = 0; i < 16; i++)
			error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
		break;
	case 3:
		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
			for (i = 0; i < 8; i++)
				error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
	case 2:
		for (i = 0; i < 8; i++)
			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
		break;
 
	default:
		BUG();
	}
}
 
static struct drm_i915_error_object *
i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
			     struct intel_ring_buffer *ring)
{
	struct drm_i915_gem_object *obj;
	u32 seqno;
 
	if (!ring->get_seqno)
		return NULL;
 
	if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
		u32 acthd = I915_READ(ACTHD);
 
		if (WARN_ON(ring->id != RCS))
			return NULL;
 
		obj = ring->private;
		if (acthd >= obj->gtt_offset &&
		    acthd < obj->gtt_offset + obj->base.size)
			return i915_error_object_create(dev_priv, obj);
	}
 
	seqno = ring->get_seqno(ring, false);
	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
		if (obj->ring != ring)
			continue;
 
		if (i915_seqno_passed(seqno, obj->last_read_seqno))
			continue;
 
		if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
			continue;
 
		/* We need to copy these to an anonymous buffer as the simplest
		 * method to avoid being overwritten by userspace.
		 */
		return i915_error_object_create(dev_priv, obj);
	}
 
	return NULL;
}
 
static void i915_record_ring_state(struct drm_device *dev,
				   struct drm_i915_error_state *error,
				   struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	if (INTEL_INFO(dev)->gen >= 6) {
		error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
		error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
		error->semaphore_mboxes[ring->id][0]
			= I915_READ(RING_SYNC_0(ring->mmio_base));
		error->semaphore_mboxes[ring->id][1]
			= I915_READ(RING_SYNC_1(ring->mmio_base));
		error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
		error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
	}
 
	if (INTEL_INFO(dev)->gen >= 4) {
		error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
		error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
		error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
		error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
		error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
		if (ring->id == RCS)
			error->bbaddr = I915_READ64(BB_ADDR);
	} else {
		error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
		error->ipeir[ring->id] = I915_READ(IPEIR);
		error->ipehr[ring->id] = I915_READ(IPEHR);
		error->instdone[ring->id] = I915_READ(INSTDONE);
	}
 
	error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
	error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
	error->seqno[ring->id] = ring->get_seqno(ring, false);
	error->acthd[ring->id] = intel_ring_get_active_head(ring);
	error->head[ring->id] = I915_READ_HEAD(ring);
	error->tail[ring->id] = I915_READ_TAIL(ring);
	error->ctl[ring->id] = I915_READ_CTL(ring);
 
	error->cpu_ring_head[ring->id] = ring->head;
	error->cpu_ring_tail[ring->id] = ring->tail;
}
 
static void i915_gem_record_rings(struct drm_device *dev,
				  struct drm_i915_error_state *error)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring;
	struct drm_i915_gem_request *request;
	int i, count;
 
	for_each_ring(ring, dev_priv, i) {
		i915_record_ring_state(dev, error, ring);
 
		error->ring[i].batchbuffer =
			i915_error_first_batchbuffer(dev_priv, ring);
 
		error->ring[i].ringbuffer =
			i915_error_object_create(dev_priv, ring->obj);
 
		count = 0;
		list_for_each_entry(request, &ring->request_list, list)
			count++;
 
		error->ring[i].num_requests = count;
		error->ring[i].requests =
			kmalloc(count*sizeof(struct drm_i915_error_request),
				GFP_ATOMIC);
		if (error->ring[i].requests == NULL) {
			error->ring[i].num_requests = 0;
			continue;
		}
 
		count = 0;
		list_for_each_entry(request, &ring->request_list, list) {
			struct drm_i915_error_request *erq;
 
			erq = &error->ring[i].requests[count++];
			erq->seqno = request->seqno;
			erq->jiffies = request->emitted_jiffies;
			erq->tail = request->tail;
		}
	}
}
 
/**
 * i915_capture_error_state - capture an error record for later analysis
 * @dev: drm device
 *
 * Should be called when an error is detected (either a hang or an error
 * interrupt) to capture error state from the time of the error.  Fills
 * out a structure which becomes available in debugfs for user level tools
 * to pick up.
 */
static void i915_capture_error_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	struct drm_i915_error_state *error;
	unsigned long flags;
	int i, pipe;
 
	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
	error = dev_priv->gpu_error.first_error;
	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
	if (error)
		return;
 
	/* Account for pipe specific data like PIPE*STAT */
	error = kzalloc(sizeof(*error), GFP_ATOMIC);
	if (!error) {
		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		return;
	}
 
	DRM_INFO("capturing error event; look for more information in"
		 "/sys/kernel/debug/dri/%d/i915_error_state\n",
		 dev->primary->index);
 
	kref_init(&error->ref);
	error->eir = I915_READ(EIR);
	error->pgtbl_er = I915_READ(PGTBL_ER);
	error->ccid = I915_READ(CCID);
 
	if (HAS_PCH_SPLIT(dev))
		error->ier = I915_READ(DEIER) | I915_READ(GTIER);
	else if (IS_VALLEYVIEW(dev))
		error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
	else if (IS_GEN2(dev))
		error->ier = I915_READ16(IER);
	else
		error->ier = I915_READ(IER);
 
	if (INTEL_INFO(dev)->gen >= 6)
		error->derrmr = I915_READ(DERRMR);
 
	if (IS_VALLEYVIEW(dev))
		error->forcewake = I915_READ(FORCEWAKE_VLV);
	else if (INTEL_INFO(dev)->gen >= 7)
		error->forcewake = I915_READ(FORCEWAKE_MT);
	else if (INTEL_INFO(dev)->gen == 6)
		error->forcewake = I915_READ(FORCEWAKE);
 
	for_each_pipe(pipe)
		error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
 
	if (INTEL_INFO(dev)->gen >= 6) {
		error->error = I915_READ(ERROR_GEN6);
		error->done_reg = I915_READ(DONE_REG);
	}
 
	if (INTEL_INFO(dev)->gen == 7)
		error->err_int = I915_READ(GEN7_ERR_INT);
 
	i915_get_extra_instdone(dev, error->extra_instdone);
 
	i915_gem_record_fences(dev, error);
	i915_gem_record_rings(dev, error);
 
	/* Record buffers on the active and pinned lists. */
	error->active_bo = NULL;
	error->pinned_bo = NULL;
 
	i = 0;
	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
		i++;
	error->active_bo_count = i;
	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
		if (obj->pin_count)
			i++;
	error->pinned_bo_count = i - error->active_bo_count;
 
	error->active_bo = NULL;
	error->pinned_bo = NULL;
	if (i) {
		error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
					   GFP_ATOMIC);
		if (error->active_bo)
			error->pinned_bo =
				error->active_bo + error->active_bo_count;
	}
 
	if (error->active_bo)
		error->active_bo_count =
			capture_active_bo(error->active_bo,
					  error->active_bo_count,
					  &dev_priv->mm.active_list);
 
	if (error->pinned_bo)
		error->pinned_bo_count =
			capture_pinned_bo(error->pinned_bo,
					  error->pinned_bo_count,
					  &dev_priv->mm.bound_list);
 
	do_gettimeofday(&error->time);
 
	error->overlay = intel_overlay_capture_error_state(dev);
	error->display = intel_display_capture_error_state(dev);
 
	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
	if (dev_priv->gpu_error.first_error == NULL) {
		dev_priv->gpu_error.first_error = error;
		error = NULL;
	}
	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
 
	if (error)
		i915_error_state_free(&error->ref);
}
 
void i915_destroy_error_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_error_state *error;
	unsigned long flags;
 
	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
	error = dev_priv->gpu_error.first_error;
	dev_priv->gpu_error.first_error = NULL;
	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
 
	if (error)
		kref_put(&error->ref, i915_error_state_free);
}
#else
#define i915_capture_error_state(x)
#endif
 
static void i915_report_and_clear_eir(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t instdone[I915_NUM_INSTDONE_REG];
	u32 eir = I915_READ(EIR);
	int pipe, i;
 
	if (!eir)
		return;
 
	pr_err("render error detected, EIR: 0x%08x\n", eir);
 
	i915_get_extra_instdone(dev, instdone);
 
	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);
 
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
			I915_WRITE(IPEIR_I965, ipeir);
			POSTING_READ(IPEIR_I965);
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
			I915_WRITE(PGTBL_ER, pgtbl_err);
			POSTING_READ(PGTBL_ER);
		}
	}
 
	if (!IS_GEN2(dev)) {
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
			I915_WRITE(PGTBL_ER, pgtbl_err);
			POSTING_READ(PGTBL_ER);
		}
	}
 
	if (eir & I915_ERROR_MEMORY_REFRESH) {
		pr_err("memory refresh error:\n");
		for_each_pipe(pipe)
			pr_err("pipe %c stat: 0x%08x\n",
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
		if (INTEL_INFO(dev)->gen < 4) {
			u32 ipeir = I915_READ(IPEIR);
 
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
			I915_WRITE(IPEIR, ipeir);
			POSTING_READ(IPEIR);
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);
 
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
			I915_WRITE(IPEIR_I965, ipeir);
			POSTING_READ(IPEIR_I965);
		}
	}
 
	I915_WRITE(EIR, eir);
	POSTING_READ(EIR);
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
}
 
/**
 * i915_handle_error - handle an error interrupt
 * @dev: drm device
 *
 * Do some basic checking of regsiter state at error interrupt time and
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
void i915_handle_error(struct drm_device *dev, bool wedged)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring;
	int i;
 
	i915_capture_error_state(dev);
	i915_report_and_clear_eir(dev);
 
	if (wedged) {
		atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
				&dev_priv->gpu_error.reset_counter);
 
		/*
		 * Wakeup waiting processes so that the reset work item
		 * doesn't deadlock trying to grab various locks.
		 */
		for_each_ring(ring, dev_priv, i)
			wake_up_all(&ring->irq_queue);
	}
 
//	queue_work(dev_priv->wq, &dev_priv->error_work);
}
 
#if 0
 
 
static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_i915_gem_object *obj;
	struct intel_unpin_work *work;
	unsigned long flags;
	bool stall_detected;
 
	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;
 
	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
 
	if (work == NULL ||
	    atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
	    !work->enable_stall_check) {
		/* Either the pending flip IRQ arrived, or we're too early. Don't check */
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}
 
	/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
	obj = work->pending_flip_obj;
	if (INTEL_INFO(dev)->gen >= 4) {
		int dspsurf = DSPSURF(intel_crtc->plane);
		stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
					obj->gtt_offset;
	} else {
		int dspaddr = DSPADDR(intel_crtc->plane);
		stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
							crtc->y * crtc->fb->pitches[0] +
							crtc->x * crtc->fb->bits_per_pixel/8);
	}
 
	spin_unlock_irqrestore(&dev->event_lock, flags);
 
	if (stall_detected) {
		DRM_DEBUG_DRIVER("Pageflip stall detected\n");
		intel_prepare_page_flip(dev, intel_crtc->plane);
	}
}
 
#endif
 
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
static int i915_enable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
 
	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;
 
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	if (INTEL_INFO(dev)->gen >= 4)
		i915_enable_pipestat(dev_priv, pipe,
				     PIPE_START_VBLANK_INTERRUPT_ENABLE);
	else
		i915_enable_pipestat(dev_priv, pipe,
				     PIPE_VBLANK_INTERRUPT_ENABLE);
 
	/* maintain vblank delivery even in deep C-states */
	if (dev_priv->info->gen == 3)
		I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
	return 0;
}
 
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
 
	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;
 
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
				    DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
	return 0;
}
 
static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
 
	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;
 
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	ironlake_enable_display_irq(dev_priv,
				    DE_PIPEA_VBLANK_IVB << (5 * pipe));
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
	return 0;
}
 
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
	u32 imr;
 
	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;
 
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	imr = I915_READ(VLV_IMR);
	if (pipe == 0)
		imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
	else
		imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
	I915_WRITE(VLV_IMR, imr);
	i915_enable_pipestat(dev_priv, pipe,
			     PIPE_START_VBLANK_INTERRUPT_ENABLE);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
	return 0;
}
 
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
static void i915_disable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
 
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	if (dev_priv->info->gen == 3)
		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
 
	i915_disable_pipestat(dev_priv, pipe,
			      PIPE_VBLANK_INTERRUPT_ENABLE |
			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
 
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
 
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
				     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
 
static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
 
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	ironlake_disable_display_irq(dev_priv,
				     DE_PIPEA_VBLANK_IVB << (pipe * 5));
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
 
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
	u32 imr;
 
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	i915_disable_pipestat(dev_priv, pipe,
			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
	imr = I915_READ(VLV_IMR);
	if (pipe == 0)
		imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
	else
		imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
	I915_WRITE(VLV_IMR, imr);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
 
static u32
ring_last_seqno(struct intel_ring_buffer *ring)
{
	return list_entry(ring->request_list.prev,
			  struct drm_i915_gem_request, list)->seqno;
}
/* drm_dma.h hooks
*/
static void ironlake_irq_preinstall(struct drm_device *dev)
{
    drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
    atomic_set(&dev_priv->irq_received, 0);
 
    I915_WRITE(HWSTAM, 0xeffe);
 
    /* XXX hotplug from PCH */
 
    I915_WRITE(DEIMR, 0xffffffff);
    I915_WRITE(DEIER, 0x0);
    POSTING_READ(DEIER);
 
    /* and GT */
    I915_WRITE(GTIMR, 0xffffffff);
    I915_WRITE(GTIER, 0x0);
    POSTING_READ(GTIER);
 
    /* south display irq */
    I915_WRITE(SDEIMR, 0xffffffff);
    I915_WRITE(SDEIER, 0x0);
    POSTING_READ(SDEIER);
}
 
static void valleyview_irq_preinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
 
	atomic_set(&dev_priv->irq_received, 0);
 
	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
 
	/* and GT */
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	POSTING_READ(GTIER);
 
	I915_WRITE(DPINVGTT, 0xff);
 
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}
 
/*
 * Enable digital hotplug on the PCH, and configure the DP short pulse
 * duration to 2ms (which is the minimum in the Display Port spec)
 *
 * This register is the same on all known PCH chips.
 */
 
static void ibx_enable_hotplug(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32	hotplug;
 
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}
 
static void ibx_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 mask;
 
	if (HAS_PCH_IBX(dev))
		mask = SDE_HOTPLUG_MASK |
		       SDE_GMBUS |
		       SDE_AUX_MASK;
	else
		mask = SDE_HOTPLUG_MASK_CPT |
		       SDE_GMBUS_CPT |
		       SDE_AUX_MASK_CPT;
 
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
	I915_WRITE(SDEIMR, ~mask);
	I915_WRITE(SDEIER, mask);
	POSTING_READ(SDEIER);
 
	ibx_enable_hotplug(dev);
}
 
static int ironlake_irq_postinstall(struct drm_device *dev)
{
    drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
    /* enable kind of interrupts always enabled */
    u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
			   DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
			   DE_AUX_CHANNEL_A;
    u32 render_irqs;
 
 
    dev_priv->irq_mask = ~display_mask;
 
    /* should always can generate irq */
    I915_WRITE(DEIIR, I915_READ(DEIIR));
    I915_WRITE(DEIMR, dev_priv->irq_mask);
    I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
    POSTING_READ(DEIER);
 
	dev_priv->gt_irq_mask = ~0;
 
    I915_WRITE(GTIIR, I915_READ(GTIIR));
    I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 
    if (IS_GEN6(dev))
        render_irqs =
            GT_USER_INTERRUPT |
			GEN6_BSD_USER_INTERRUPT |
			GEN6_BLITTER_USER_INTERRUPT;
    else
        render_irqs =
            GT_USER_INTERRUPT |
            GT_PIPE_NOTIFY |
            GT_BSD_USER_INTERRUPT;
    I915_WRITE(GTIER, render_irqs);
    POSTING_READ(GTIER);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
	ibx_irq_postinstall(dev);
 
    if (IS_IRONLAKE_M(dev)) {
        /* Clear & enable PCU event interrupts */
        I915_WRITE(DEIIR, DE_PCU_EVENT);
        I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
    }
 
    return 0;
}
 
static int ivybridge_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	/* enable kind of interrupts always enabled */
	u32 display_mask =
		DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
		DE_PLANEC_FLIP_DONE_IVB |
		DE_PLANEB_FLIP_DONE_IVB |
		DE_PLANEA_FLIP_DONE_IVB |
		DE_AUX_CHANNEL_A_IVB;
	u32 render_irqs;
 
 
	dev_priv->irq_mask = ~display_mask;
 
	/* should always can generate irq */
	I915_WRITE(DEIIR, I915_READ(DEIIR));
	I915_WRITE(DEIMR, dev_priv->irq_mask);
	I915_WRITE(DEIER,
		   display_mask |
		   DE_PIPEC_VBLANK_IVB |
		   DE_PIPEB_VBLANK_IVB |
		   DE_PIPEA_VBLANK_IVB);
	POSTING_READ(DEIER);
 
	dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 
	render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
		GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
	I915_WRITE(GTIER, render_irqs);
	POSTING_READ(GTIER);
 
 
 
 
 
 
 
 
 
 
 
 
	ibx_irq_postinstall(dev);
 
	return 0;
}
 
static int valleyview_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 enable_mask;
 
	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
	u32 render_irqs;
	u16 msid;
 
	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
	enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 
	/*
	 *Leave vblank interrupts masked initially.  enable/disable will
	 * toggle them based on usage.
	 */
	dev_priv->irq_mask = (~enable_mask) |
		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 
	dev_priv->pipestat[0] = 0;
	dev_priv->pipestat[1] = 0;
 
	/* Hack for broken MSIs on VLV */
//   pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
//   pci_read_config_word(dev->pdev, 0x98, &msid);
//   msid &= 0xff; /* mask out delivery bits */
//   msid |= (1<<14);
//   pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
 
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);
 
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	I915_WRITE(VLV_IER, enable_mask);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(PIPESTAT(0), 0xffff);
	I915_WRITE(PIPESTAT(1), 0xffff);
	POSTING_READ(VLV_IER);
 
	i915_enable_pipestat(dev_priv, 0, pipestat_enable);
	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
	i915_enable_pipestat(dev_priv, 1, pipestat_enable);
 
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
 
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 
	render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
		GEN6_BLITTER_USER_INTERRUPT;
	I915_WRITE(GTIER, render_irqs);
	POSTING_READ(GTIER);
 
	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif
 
	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
 
	return 0;
}
 
static void valleyview_hpd_irq_setup(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
 
	/* Note HDMI and DP share bits */
	if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
		hotplug_en |= PORTB_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
		hotplug_en |= PORTC_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
		hotplug_en |= PORTD_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
		hotplug_en |= SDVOC_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
		hotplug_en |= SDVOB_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
		hotplug_en |= CRT_HOTPLUG_INT_EN;
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
	}
 
 
 
 
	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
}
 
static void valleyview_irq_uninstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
 
	if (!dev_priv)
		return;
 
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
 
	I915_WRITE(HWSTAM, 0xffffffff);
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}
 
static void ironlake_irq_uninstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
	if (!dev_priv)
		return;
 
	I915_WRITE(HWSTAM, 0xffffffff);
 
	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
	I915_WRITE(DEIIR, I915_READ(DEIIR));
 
	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	I915_WRITE(GTIIR, I915_READ(GTIIR));
 
	I915_WRITE(SDEIMR, 0xffffffff);
	I915_WRITE(SDEIER, 0x0);
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
}
 
#if 0
 
static void i8xx_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
 
	atomic_set(&dev_priv->irq_received, 0);
 
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
}
 
static int i8xx_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
	dev_priv->pipestat[0] = 0;
	dev_priv->pipestat[1] = 0;
 
	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
 
	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	I915_WRITE16(IMR, dev_priv->irq_mask);
 
	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);
 
	return 0;
}
 
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u16 iir, new_iir;
	u32 pipe_stats[2];
	unsigned long irqflags;
	int irq_received;
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
 
	atomic_inc(&dev_priv->irq_received);
 
	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;
 
	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);
 
		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);
 
			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
				irq_received = 1;
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */
 
		i915_update_dri1_breadcrumb(dev);
 
		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);
 
		if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
		    drm_handle_vblank(dev, 0)) {
			if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
				intel_prepare_page_flip(dev, 0);
				intel_finish_page_flip(dev, 0);
				flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
			}
		}
 
		if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
		    drm_handle_vblank(dev, 1)) {
			if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
				intel_prepare_page_flip(dev, 1);
				intel_finish_page_flip(dev, 1);
				flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
			}
		}
 
		iir = new_iir;
	}
 
	return IRQ_HANDLED;
}
 
static void i8xx_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
 
	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}
 
#endif
 
static void i915_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
 
	atomic_set(&dev_priv->irq_received, 0);
 
	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}
 
	I915_WRITE16(HWSTAM, 0xeffe);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}
 
static int i915_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 enable_mask;
 
	dev_priv->pipestat[0] = 0;
	dev_priv->pipestat[1] = 0;
 
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
 
	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 
	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		I915_USER_INTERRUPT;
 
	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		POSTING_READ(PORT_HOTPLUG_EN);
 
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}
 
 
	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);
 
//	intel_opregion_enable_asle(dev);
 
	return 0;
}
 
static void i915_hpd_irq_setup(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 hotplug_en;
 
	if (I915_HAS_HOTPLUG(dev)) {
		hotplug_en = I915_READ(PORT_HOTPLUG_EN);
 
		if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
			hotplug_en |= PORTB_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
			hotplug_en |= PORTC_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
			hotplug_en |= PORTD_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
			hotplug_en |= SDVOC_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
			hotplug_en |= SDVOB_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
			hotplug_en |= CRT_HOTPLUG_INT_EN;
			hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
		}
 
		/* Ignore TV since it's buggy */
 
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
	}
 
 
 
 
}
 
static irqreturn_t i915_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
	unsigned long irqflags;
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	u32 flip[2] = {
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
	};
	int pipe, ret = IRQ_NONE;
 
	atomic_inc(&dev_priv->irq_received);
 
	iir = I915_READ(IIR);
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
		bool blc_event = false;
 
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);
 
		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);
 
			/* Clear the PIPE*STAT regs before the IIR */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
				irq_received = true;
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
		if (!irq_received)
			break;
 
		/* Consume port.  Then clear IIR or we'll miss events */
		if ((I915_HAS_HOTPLUG(dev)) &&
		    (iir & I915_DISPLAY_PORT_INTERRUPT)) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 
			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
				  hotplug_status);
			if (hotplug_status & dev_priv->hotplug_supported_mask)
				queue_work(dev_priv->wq,
					   &dev_priv->hotplug_work);
 
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			POSTING_READ(PORT_HOTPLUG_STAT);
		}
 
		I915_WRITE(IIR, iir & ~flip_mask);
		new_iir = I915_READ(IIR); /* Flush posted writes */
 
		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);
 
		for_each_pipe(pipe) {
			int plane = pipe;
			if (IS_MOBILE(dev))
				plane = !plane;
            if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS /* &&
                drm_handle_vblank(dev, pipe) */) {
				if (iir & flip[plane]) {
//					intel_prepare_page_flip(dev, plane);
//					intel_finish_page_flip(dev, pipe);
					flip_mask &= ~flip[plane];
				}
			}
 
			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
		}
 
//		if (blc_event || (iir & I915_ASLE_INTERRUPT))
//			intel_opregion_asle_intr(dev);
 
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		ret = IRQ_HANDLED;
		iir = new_iir;
	} while (iir & ~flip_mask);
 
	i915_update_dri1_breadcrumb(dev);
 
	return ret;
}
 
static void i915_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
 
	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}
 
	I915_WRITE16(HWSTAM, 0xffff);
	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
 
	I915_WRITE(IIR, I915_READ(IIR));
}
 
static void i965_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
 
	atomic_set(&dev_priv->irq_received, 0);
 
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 
	I915_WRITE(HWSTAM, 0xeffe);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}
 
static int i965_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
	u32 enable_mask;
	u32 error_mask;
 
	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
			       I915_DISPLAY_PORT_INTERRUPT |
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 
	enable_mask = ~dev_priv->irq_mask;
	enable_mask |= I915_USER_INTERRUPT;
 
	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
 
	dev_priv->pipestat[0] = 0;
	dev_priv->pipestat[1] = 0;
	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
 
	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);
 
	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);
 
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);
 
//	intel_opregion_enable_asle(dev);
 
	return 0;
}
 
static void i965_hpd_irq_setup(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 hotplug_en;
 
	/* Note HDMI and DP share hotplug bits */
 
	hotplug_en = 0;
	if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
		hotplug_en |= PORTB_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
		hotplug_en |= PORTC_HOTPLUG_INT_EN;
	if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
		hotplug_en |= PORTD_HOTPLUG_INT_EN;
	if (IS_G4X(dev)) {
		if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
			hotplug_en |= SDVOC_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
			hotplug_en |= SDVOB_HOTPLUG_INT_EN;
	} else {
		if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
			hotplug_en |= SDVOC_HOTPLUG_INT_EN;
		if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
			hotplug_en |= SDVOB_HOTPLUG_INT_EN;
	}
	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
		hotplug_en |= CRT_HOTPLUG_INT_EN;
 
		/* Programming the CRT detection parameters tends
		   to generate a spurious hotplug event about three
		   seconds later.  So just do it once.
		   */
		if (IS_G4X(dev))
			hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
	}
 
	/* Ignore TV since it's buggy */
 
	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
 
 
 
 
}
 
static irqreturn_t i965_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	unsigned long irqflags;
	int irq_received;
	int ret = IRQ_NONE, pipe;
 
	atomic_inc(&dev_priv->irq_received);
 
	iir = I915_READ(IIR);
 
	for (;;) {
		bool blc_event = false;
 
		irq_received = iir != 0;
 
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);
 
		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);
 
			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
				irq_received = 1;
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
		if (!irq_received)
			break;
 
		ret = IRQ_HANDLED;
 
		/* Consume port.  Then clear IIR or we'll miss events */
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 
			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
				  hotplug_status);
			if (hotplug_status & dev_priv->hotplug_supported_mask)
				queue_work(dev_priv->wq,
					   &dev_priv->hotplug_work);
 
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}
 
		I915_WRITE(IIR, iir);
		new_iir = I915_READ(IIR); /* Flush posted writes */
 
		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);
		if (iir & I915_BSD_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[VCS]);
 
//		if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
//			intel_prepare_page_flip(dev, 0);
 
//		if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
//			intel_prepare_page_flip(dev, 1);
 
		for_each_pipe(pipe) {
//           if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
//               drm_handle_vblank(dev, pipe)) {
//				i915_pageflip_stall_check(dev, pipe);
//				intel_finish_page_flip(dev, pipe);
//           }
 
			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
		}
 
 
//		if (blc_event || (iir & I915_ASLE_INTERRUPT))
//			intel_opregion_asle_intr(dev);
 
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);
 
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}
 
	i915_update_dri1_breadcrumb(dev);
 
	return ret;
}
 
static void i965_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
 
	if (!dev_priv)
		return;
 
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 
	I915_WRITE(HWSTAM, 0xffffffff);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
 
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}
 
void intel_irq_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
 
//	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
 
 
 
	if (IS_VALLEYVIEW(dev)) {
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev_priv->display.hpd_irq_setup = valleyview_hpd_irq_setup;
	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
		/* Share pre & uninstall handlers with ILK/SNB */
		dev->driver->irq_handler = ivybridge_irq_handler;
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
		dev->driver->irq_postinstall = ivybridge_irq_postinstall;
 
 
 
 
 
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
	} else {
		if (INTEL_INFO(dev)->gen == 2) {
		} else if (INTEL_INFO(dev)->gen == 3) {
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_handler = i915_irq_handler;
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
		} else {
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_handler = i965_irq_handler;
			dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup;
		}
	}
}
 
void intel_hpd_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
}
 
 
irqreturn_t intel_irq_handler(struct drm_device *dev)
{
 
//    printf("i915 irq\n");
 
//    printf("device %p driver %p handler %p\n", dev, dev->driver, dev->driver->irq_handler) ;
 
    return dev->driver->irq_handler(0, dev);
}
 
int drm_irq_install(struct drm_device *dev)
{
    unsigned long sh_flags = 0;
    int irq_line;
    int ret = 0;
 
    char *irqname;
 
    mutex_lock(&dev->struct_mutex);
 
    /* Driver must have been initialized */
    if (!dev->dev_private) {
            mutex_unlock(&dev->struct_mutex);
            return -EINVAL;
    }
 
    if (dev->irq_enabled) {
            mutex_unlock(&dev->struct_mutex);
            return -EBUSY;
    }
    dev->irq_enabled = 1;
    mutex_unlock(&dev->struct_mutex);
 
    irq_line   = drm_dev_to_irq(dev);
 
    DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev));
 
    /* Before installing handler */
    if (dev->driver->irq_preinstall)
            dev->driver->irq_preinstall(dev);
 
    ret = AttachIntHandler(irq_line, intel_irq_handler, (u32)dev);
 
    /* After installing handler */
    if (dev->driver->irq_postinstall)
            ret = dev->driver->irq_postinstall(dev);
 
    if (ret < 0) {
            DRM_ERROR(__FUNCTION__);
    }
 
    u16_t cmd = PciRead16(dev->pdev->busnr, dev->pdev->devfn, 4);
    cmd&= ~(1<<10);
    PciWrite16(dev->pdev->busnr, dev->pdev->devfn, 4, cmd);
 
    return ret;
}
>
>
//>
//>

Rev 3298	Rev 3480
1	/* i915_irq.c -- IRQ support for the I915 -- linux-c --	1	/* i915_irq.c -- IRQ support for the I915 -- linux-c --
2	*/	2	*/
3	/*	3	/*
4	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.	4	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5	* All Rights Reserved.	5	* All Rights Reserved.
6	*	6	*
7	* Permission is hereby granted, free of charge, to any person obtaining a	7	* Permission is hereby granted, free of charge, to any person obtaining a
8	* copy of this software and associated documentation files (the	8	* copy of this software and associated documentation files (the
9	* "Software"), to deal in the Software without restriction, including	9	* "Software"), to deal in the Software without restriction, including
10	* without limitation the rights to use, copy, modify, merge, publish,	10	* without limitation the rights to use, copy, modify, merge, publish,
11	* distribute, sub license, and/or sell copies of the Software, and to	11	* distribute, sub license, and/or sell copies of the Software, and to
12	* permit persons to whom the Software is furnished to do so, subject to	12	* permit persons to whom the Software is furnished to do so, subject to
13	* the following conditions:	13	* the following conditions:
14	*	14	*
15	* The above copyright notice and this permission notice (including the	15	* The above copyright notice and this permission notice (including the
16	* next paragraph) shall be included in all copies or substantial portions	16	* next paragraph) shall be included in all copies or substantial portions
17	* of the Software.	17	* of the Software.
18	*	18	*
19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF	20	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.	21	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR	22	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,	23	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE	24	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.	25	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26	*	26	*
27	*/	27	*/
28		28
29	#define pr_fmt(fmt) ": " fmt	29	#define pr_fmt(fmt) ": " fmt
30		30
31	#include	31	#include
32	#include	32	#include
33	#include	33	#include
34	#include "i915_drv.h"	34	#include "i915_drv.h"
35	#include "i915_trace.h"	35	#include "i915_trace.h"
36	#include "intel_drv.h"	36	#include "intel_drv.h"
37		37
38		38
39	#define pr_err(fmt, ...) \	39	#define pr_err(fmt, ...) \
40	printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)	40	printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
41		41
42		42
43	#define DRM_WAKEUP( queue ) wake_up( queue )	43	#define DRM_WAKEUP( queue ) wake_up( queue )
44	#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )	44	#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )
45		45
46	#define MAX_NOPID ((u32)~0)	46	#define MAX_NOPID ((u32)~0)
47		-
48	/**	-
49	* Interrupts that are always left unmasked.	-
50	*	-
51	* Since pipe events are edge-triggered from the PIPESTAT register to IIR,	-
52	* we leave them always unmasked in IMR and then control enabling them through	-
53	* PIPESTAT alone.	-
54	*/	-
55	#define I915_INTERRUPT_ENABLE_FIX \	-
56	(I915_ASLE_INTERRUPT \| \	-
57	I915_DISPLAY_PIPE_A_EVENT_INTERRUPT \| \	-
58	I915_DISPLAY_PIPE_B_EVENT_INTERRUPT \| \	-
59	I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT \| \	-
60	I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT \| \	-
61	I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)	-
62		-
63	/** Interrupts that we mask and unmask at runtime. */	-
64	#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT \| I915_BSD_USER_INTERRUPT)	-
65		-
66	#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS \|\	-
67	PIPE_VBLANK_INTERRUPT_STATUS)	-
68		-
69	#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE \|\	-
70	PIPE_VBLANK_INTERRUPT_ENABLE)	-
71		-
72	#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A \| \	47
73	DRM_I915_VBLANK_PIPE_B)	48
74		49
75	/* For display hotplug interrupt */	50	/* For display hotplug interrupt */
76	static void	51	static void
77	ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)	52	ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
78	{	53	{
79	if ((dev_priv->irq_mask & mask) != 0) {	54	if ((dev_priv->irq_mask & mask) != 0) {
80	dev_priv->irq_mask &= ~mask;	55	dev_priv->irq_mask &= ~mask;
81	I915_WRITE(DEIMR, dev_priv->irq_mask);	56	I915_WRITE(DEIMR, dev_priv->irq_mask);
82	POSTING_READ(DEIMR);	57	POSTING_READ(DEIMR);
83	}	58	}
84	}	59	}
85		60
86	static inline void	61	static inline void
87	ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)	62	ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
88	{	63	{
89	if ((dev_priv->irq_mask & mask) != mask) {	64	if ((dev_priv->irq_mask & mask) != mask) {
90	dev_priv->irq_mask \|= mask;	65	dev_priv->irq_mask \|= mask;
91	I915_WRITE(DEIMR, dev_priv->irq_mask);	66	I915_WRITE(DEIMR, dev_priv->irq_mask);
92	POSTING_READ(DEIMR);	67	POSTING_READ(DEIMR);
93	}	68	}
94	}	69	}
95		70
96	void	71	void
97	i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)	72	i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
98	{	73	{
99	if ((dev_priv->pipestat[pipe] & mask) != mask) {	74	if ((dev_priv->pipestat[pipe] & mask) != mask) {
100	u32 reg = PIPESTAT(pipe);	75	u32 reg = PIPESTAT(pipe);
101		76
102	dev_priv->pipestat[pipe] \|= mask;	77	dev_priv->pipestat[pipe] \|= mask;
103	/* Enable the interrupt, clear any pending status */	78	/* Enable the interrupt, clear any pending status */
104	I915_WRITE(reg, dev_priv->pipestat[pipe] \| (mask >> 16));	79	I915_WRITE(reg, dev_priv->pipestat[pipe] \| (mask >> 16));
105	POSTING_READ(reg);	80	POSTING_READ(reg);
106	}	81	}
107	}	82	}
108		83
109	void	84	void
110	i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)	85	i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
111	{	86	{
112	if ((dev_priv->pipestat[pipe] & mask) != 0) {	87	if ((dev_priv->pipestat[pipe] & mask) != 0) {
113	u32 reg = PIPESTAT(pipe);	88	u32 reg = PIPESTAT(pipe);
114		89
115	dev_priv->pipestat[pipe] &= ~mask;	90	dev_priv->pipestat[pipe] &= ~mask;
116	I915_WRITE(reg, dev_priv->pipestat[pipe]);	91	I915_WRITE(reg, dev_priv->pipestat[pipe]);
117	POSTING_READ(reg);	92	POSTING_READ(reg);
118	}	93	}
119	}	94	}
120		95
121	#if 0	96	#if 0
122	/**	97	/**
123	* intel_enable_asle - enable ASLE interrupt for OpRegion	98	* intel_enable_asle - enable ASLE interrupt for OpRegion
124	*/	99	*/
125	void intel_enable_asle(struct drm_device *dev)	100	void intel_enable_asle(struct drm_device *dev)
126	{	101	{
127	drm_i915_private_t *dev_priv = dev->dev_private;	102	drm_i915_private_t *dev_priv = dev->dev_private;
128	unsigned long irqflags;	103	unsigned long irqflags;
129		104
130	/* FIXME: opregion/asle for VLV */	105	/* FIXME: opregion/asle for VLV */
131	if (IS_VALLEYVIEW(dev))	106	if (IS_VALLEYVIEW(dev))
132	return;	107	return;
133		108
134	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);	109	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
135		110
136	if (HAS_PCH_SPLIT(dev))	111	if (HAS_PCH_SPLIT(dev))
137	ironlake_enable_display_irq(dev_priv, DE_GSE);	112	ironlake_enable_display_irq(dev_priv, DE_GSE);
138	else {	113	else {
139	i915_enable_pipestat(dev_priv, 1,	114	i915_enable_pipestat(dev_priv, 1,
140	PIPE_LEGACY_BLC_EVENT_ENABLE);	115	PIPE_LEGACY_BLC_EVENT_ENABLE);
141	if (INTEL_INFO(dev)->gen >= 4)	116	if (INTEL_INFO(dev)->gen >= 4)
142	i915_enable_pipestat(dev_priv, 0,	117	i915_enable_pipestat(dev_priv, 0,
143	PIPE_LEGACY_BLC_EVENT_ENABLE);	118	PIPE_LEGACY_BLC_EVENT_ENABLE);
144	}	119	}
145		120
146	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);	121	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
147	}	122	}
148	#endif	123	#endif
149		124
150	/**	125	/**
151	* i915_pipe_enabled - check if a pipe is enabled	126	* i915_pipe_enabled - check if a pipe is enabled
152	* @dev: DRM device	127	* @dev: DRM device
153	* @pipe: pipe to check	128	* @pipe: pipe to check
154	*	129	*
155	* Reading certain registers when the pipe is disabled can hang the chip.	130	* Reading certain registers when the pipe is disabled can hang the chip.
156	* Use this routine to make sure the PLL is running and the pipe is active	131	* Use this routine to make sure the PLL is running and the pipe is active
157	* before reading such registers if unsure.	132	* before reading such registers if unsure.
158	*/	133	*/
159	static int	134	static int
160	i915_pipe_enabled(struct drm_device *dev, int pipe)	135	i915_pipe_enabled(struct drm_device *dev, int pipe)
161	{	136	{
162	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;	137	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
163	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,	138	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
164	pipe);	139	pipe);
165		140
166	return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;	141	return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
167	}	142	}
168		143
169	/* Called from drm generic code, passed a 'crtc', which	144	/* Called from drm generic code, passed a 'crtc', which
170	* we use as a pipe index	145	* we use as a pipe index
171	*/	146	*/
172	static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)	147	static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
173	{	148	{
174	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;	149	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
175	unsigned long high_frame;	150	unsigned long high_frame;
176	unsigned long low_frame;	151	unsigned long low_frame;
177	u32 high1, high2, low;	152	u32 high1, high2, low;
178		153
179	if (!i915_pipe_enabled(dev, pipe)) {	154	if (!i915_pipe_enabled(dev, pipe)) {
180	DRM_DEBUG_DRIVER("trying to get vblank count for disabled "	155	DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
181	"pipe %c\n", pipe_name(pipe));	156	"pipe %c\n", pipe_name(pipe));
182	return 0;	157	return 0;
183	}	158	}
184		159
185	high_frame = PIPEFRAME(pipe);	160	high_frame = PIPEFRAME(pipe);
186	low_frame = PIPEFRAMEPIXEL(pipe);	161	low_frame = PIPEFRAMEPIXEL(pipe);
187		162
188	/*	163	/*
189	* High & low register fields aren't synchronized, so make sure	164	* High & low register fields aren't synchronized, so make sure
190	* we get a low value that's stable across two reads of the high	165	* we get a low value that's stable across two reads of the high
191	* register.	166	* register.
192	*/	167	*/
193	do {	168	do {
194	high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;	169	high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
195	low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;	170	low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
196	high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;	171	high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
197	} while (high1 != high2);	172	} while (high1 != high2);
198		173
199	high1 >>= PIPE_FRAME_HIGH_SHIFT;	174	high1 >>= PIPE_FRAME_HIGH_SHIFT;
200	low >>= PIPE_FRAME_LOW_SHIFT;	175	low >>= PIPE_FRAME_LOW_SHIFT;
201	return (high1 << 8) \| low;	176	return (high1 << 8) \| low;
202	}	177	}
203		178
204	static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)	179	static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
205	{	180	{
206	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;	181	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
207	int reg = PIPE_FRMCOUNT_GM45(pipe);	182	int reg = PIPE_FRMCOUNT_GM45(pipe);
208		183
209	if (!i915_pipe_enabled(dev, pipe)) {	184	if (!i915_pipe_enabled(dev, pipe)) {
210	DRM_DEBUG_DRIVER("trying to get vblank count for disabled "	185	DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
211	"pipe %c\n", pipe_name(pipe));	186	"pipe %c\n", pipe_name(pipe));
212	return 0;	187	return 0;
213	}	188	}
214		189
215	return I915_READ(reg);	190	return I915_READ(reg);
216	}	191	}
-		192
-		193	/*
-		194	* Handle hotplug events outside the interrupt handler proper.
-		195	*/
-		196	static void i915_hotplug_work_func(struct work_struct *work)
-		197	{
-		198	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
-		199	hotplug_work);
-		200	struct drm_device *dev = dev_priv->dev;
-		201	struct drm_mode_config *mode_config = &dev->mode_config;
-		202	struct intel_encoder *encoder;
-		203
-		204	/* HPD irq before everything is fully set up. */
-		205	if (!dev_priv->enable_hotplug_processing)
-		206	return;
-		207
-		208	mutex_lock(&mode_config->mutex);
-		209	DRM_DEBUG_KMS("running encoder hotplug functions\n");
-		210
-		211	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
-		212	if (encoder->hot_plug)
-		213	encoder->hot_plug(encoder);
-		214
-		215	mutex_unlock(&mode_config->mutex);
-		216
-		217	/* Just fire off a uevent and let userspace tell us what to do */
-		218	drm_helper_hpd_irq_event(dev);
217		219	}
218		220
219	static void notify_ring(struct drm_device *dev,	221	static void notify_ring(struct drm_device *dev,
220	struct intel_ring_buffer *ring)	222	struct intel_ring_buffer *ring)
221	{	223	{
222	struct drm_i915_private *dev_priv = dev->dev_private;	224	struct drm_i915_private *dev_priv = dev->dev_private;
223		225
224	if (ring->obj == NULL)	226	if (ring->obj == NULL)
225	return;	227	return;
226		228
227	trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));	229	trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
228		230
229	wake_up_all(&ring->irq_queue);	231	wake_up_all(&ring->irq_queue);
230	// if (i915_enable_hangcheck) {	232	// if (i915_enable_hangcheck) {
231	// dev_priv->hangcheck_count = 0;	233	// dev_priv->hangcheck_count = 0;
232	// mod_timer(&dev_priv->hangcheck_timer,	234	// mod_timer(&dev_priv->hangcheck_timer,
233	// jiffies +	235	// jiffies +
234	// msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));	236	// msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
235	// }	237	// }
236	}	238	}
237		239
238	#if 0	240	#if 0
239	static void gen6_pm_rps_work(struct work_struct *work)	241	static void gen6_pm_rps_work(struct work_struct *work)
240	{	242	{
241	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,	243	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
242	rps.work);	244	rps.work);
243	u32 pm_iir, pm_imr;	245	u32 pm_iir, pm_imr;
244	u8 new_delay;	246	u8 new_delay;
245		247
246	spin_lock_irq(&dev_priv->rps.lock);	248	spin_lock_irq(&dev_priv->rps.lock);
247	pm_iir = dev_priv->rps.pm_iir;	249	pm_iir = dev_priv->rps.pm_iir;
248	dev_priv->rps.pm_iir = 0;	250	dev_priv->rps.pm_iir = 0;
249	pm_imr = I915_READ(GEN6_PMIMR);	251	pm_imr = I915_READ(GEN6_PMIMR);
250	I915_WRITE(GEN6_PMIMR, 0);	252	I915_WRITE(GEN6_PMIMR, 0);
251	spin_unlock_irq(&dev_priv->rps.lock);	253	spin_unlock_irq(&dev_priv->rps.lock);
252		254
253	if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)	255	if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
254	return;	256	return;
255		257
256	mutex_lock(&dev_priv->rps.hw_lock);	258	mutex_lock(&dev_priv->rps.hw_lock);
257		259
258	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)	260	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
259	new_delay = dev_priv->rps.cur_delay + 1;	261	new_delay = dev_priv->rps.cur_delay + 1;
260	else	262	else
261	new_delay = dev_priv->rps.cur_delay - 1;	263	new_delay = dev_priv->rps.cur_delay - 1;
262		264
263	/* sysfs frequency interfaces may have snuck in while servicing the	265	/* sysfs frequency interfaces may have snuck in while servicing the
264	* interrupt	266	* interrupt
265	*/	267	*/
266	if (!(new_delay > dev_priv->rps.max_delay \|\|	268	if (!(new_delay > dev_priv->rps.max_delay \|\|
267	new_delay < dev_priv->rps.min_delay)) {	269	new_delay < dev_priv->rps.min_delay)) {
268	gen6_set_rps(dev_priv->dev, new_delay);	270	gen6_set_rps(dev_priv->dev, new_delay);
269	}	271	}
270		272
271	mutex_unlock(&dev_priv->rps.hw_lock);	273	mutex_unlock(&dev_priv->rps.hw_lock);
272	}	274	}
273		275
274		276
275	/**	277	/**
276	* ivybridge_parity_work - Workqueue called when a parity error interrupt	278	* ivybridge_parity_work - Workqueue called when a parity error interrupt
277	* occurred.	279	* occurred.
278	* @work: workqueue struct	280	* @work: workqueue struct
279	*	281	*
280	* Doesn't actually do anything except notify userspace. As a consequence of	282	* Doesn't actually do anything except notify userspace. As a consequence of
281	* this event, userspace should try to remap the bad rows since statistically	283	* this event, userspace should try to remap the bad rows since statistically
282	* it is likely the same row is more likely to go bad again.	284	* it is likely the same row is more likely to go bad again.
283	*/	285	*/
284	static void ivybridge_parity_work(struct work_struct *work)	286	static void ivybridge_parity_work(struct work_struct *work)
285	{	287	{
286	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,	288	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
287	l3_parity.error_work);	289	l3_parity.error_work);
288	u32 error_status, row, bank, subbank;	290	u32 error_status, row, bank, subbank;
289	char *parity_event[5];	291	char *parity_event[5];
290	uint32_t misccpctl;	292	uint32_t misccpctl;
291	unsigned long flags;	293	unsigned long flags;
292		294
293	/* We must turn off DOP level clock gating to access the L3 registers.	295	/* We must turn off DOP level clock gating to access the L3 registers.
294	* In order to prevent a get/put style interface, acquire struct mutex	296	* In order to prevent a get/put style interface, acquire struct mutex
295	* any time we access those registers.	297	* any time we access those registers.
296	*/	298	*/
297	mutex_lock(&dev_priv->dev->struct_mutex);	299	mutex_lock(&dev_priv->dev->struct_mutex);
298		300
299	misccpctl = I915_READ(GEN7_MISCCPCTL);	301	misccpctl = I915_READ(GEN7_MISCCPCTL);
300	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);	302	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
301	POSTING_READ(GEN7_MISCCPCTL);	303	POSTING_READ(GEN7_MISCCPCTL);
302		304
303	error_status = I915_READ(GEN7_L3CDERRST1);	305	error_status = I915_READ(GEN7_L3CDERRST1);
304	row = GEN7_PARITY_ERROR_ROW(error_status);	306	row = GEN7_PARITY_ERROR_ROW(error_status);
305	bank = GEN7_PARITY_ERROR_BANK(error_status);	307	bank = GEN7_PARITY_ERROR_BANK(error_status);
306	subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);	308	subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
307		309
308	I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID \|	310	I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID \|
309	GEN7_L3CDERRST1_ENABLE);	311	GEN7_L3CDERRST1_ENABLE);
310	POSTING_READ(GEN7_L3CDERRST1);	312	POSTING_READ(GEN7_L3CDERRST1);
311		313
312	I915_WRITE(GEN7_MISCCPCTL, misccpctl);	314	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
313		315
314	spin_lock_irqsave(&dev_priv->irq_lock, flags);	316	spin_lock_irqsave(&dev_priv->irq_lock, flags);
315	dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;	317	dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
316	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);	318	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
317	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);	319	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
318		320
319	mutex_unlock(&dev_priv->dev->struct_mutex);	321	mutex_unlock(&dev_priv->dev->struct_mutex);
320		322
321	parity_event[0] = "L3_PARITY_ERROR=1";	323	parity_event[0] = "L3_PARITY_ERROR=1";
322	parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);	324	parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
323	parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);	325	parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
324	parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);	326	parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
325	parity_event[4] = NULL;	327	parity_event[4] = NULL;
326		328
327	kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,	329	kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
328	KOBJ_CHANGE, parity_event);	330	KOBJ_CHANGE, parity_event);
329		331
330	DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",	332	DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
331	row, bank, subbank);	333	row, bank, subbank);
332		334
333	kfree(parity_event[3]);	335	kfree(parity_event[3]);
334	kfree(parity_event[2]);	336	kfree(parity_event[2]);
335	kfree(parity_event[1]);	337	kfree(parity_event[1]);
336	}	338	}
337		339
338	static void ivybridge_handle_parity_error(struct drm_device *dev)	340	static void ivybridge_handle_parity_error(struct drm_device *dev)
339	{	341	{
340	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;	342	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
341	unsigned long flags;	343	unsigned long flags;
342		344
343	if (!HAS_L3_GPU_CACHE(dev))	345	if (!HAS_L3_GPU_CACHE(dev))
344	return;	346	return;
345		347
346	spin_lock_irqsave(&dev_priv->irq_lock, flags);	348	spin_lock_irqsave(&dev_priv->irq_lock, flags);
347	dev_priv->gt_irq_mask \|= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;	349	dev_priv->gt_irq_mask \|= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
348	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);	350	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
349	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);	351	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
350		352
351	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);	353	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
352	}	354	}
353		355
354	#endif	356	#endif
355		357
356	static void snb_gt_irq_handler(struct drm_device *dev,	358	static void snb_gt_irq_handler(struct drm_device *dev,
357	struct drm_i915_private *dev_priv,	359	struct drm_i915_private *dev_priv,
358	u32 gt_iir)	360	u32 gt_iir)
359	{	361	{
360	// printf("%s\n", __FUNCTION__);	362	// printf("%s\n", __FUNCTION__);
361		363
362	if (gt_iir & (GEN6_RENDER_USER_INTERRUPT \|	364	if (gt_iir & (GEN6_RENDER_USER_INTERRUPT \|
363	GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))	365	GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
364	notify_ring(dev, &dev_priv->ring[RCS]);	366	notify_ring(dev, &dev_priv->ring[RCS]);
365	if (gt_iir & GEN6_BSD_USER_INTERRUPT)	367	if (gt_iir & GEN6_BSD_USER_INTERRUPT)
366	notify_ring(dev, &dev_priv->ring[VCS]);	368	notify_ring(dev, &dev_priv->ring[VCS]);
367	if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)	369	if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
368	notify_ring(dev, &dev_priv->ring[BCS]);	370	notify_ring(dev, &dev_priv->ring[BCS]);
369		371
370	if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT \|	372	if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT \|
371	GT_GEN6_BSD_CS_ERROR_INTERRUPT \|	373	GT_GEN6_BSD_CS_ERROR_INTERRUPT \|
372	GT_RENDER_CS_ERROR_INTERRUPT)) {	374	GT_RENDER_CS_ERROR_INTERRUPT)) {
373	DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);	375	DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
374	i915_handle_error(dev, false);	376	i915_handle_error(dev, false);
375	}	377	}
376		378
377	// if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)	379	// if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
378	// ivybridge_handle_parity_error(dev);	380	// ivybridge_handle_parity_error(dev);
379	}	381	}
380		382
381	static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,	383	static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
382	u32 pm_iir)	384	u32 pm_iir)
383	{	385	{
384	unsigned long flags;	386	unsigned long flags;
385		387
386	/*	388	/*
387	* IIR bits should never already be set because IMR should	389	* IIR bits should never already be set because IMR should
388	* prevent an interrupt from being shown in IIR. The warning	390	* prevent an interrupt from being shown in IIR. The warning
389	* displays a case where we've unsafely cleared	391	* displays a case where we've unsafely cleared
390	* dev_priv->rps.pm_iir. Although missing an interrupt of the same	392	* dev_priv->rps.pm_iir. Although missing an interrupt of the same
391	* type is not a problem, it displays a problem in the logic.	393	* type is not a problem, it displays a problem in the logic.
392	*	394	*
393	* The mask bit in IMR is cleared by dev_priv->rps.work.	395	* The mask bit in IMR is cleared by dev_priv->rps.work.
394	*/	396	*/
395		397
396	spin_lock_irqsave(&dev_priv->rps.lock, flags);	398	spin_lock_irqsave(&dev_priv->rps.lock, flags);
397	dev_priv->rps.pm_iir \|= pm_iir;	399	dev_priv->rps.pm_iir \|= pm_iir;
398	I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);	400	I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
399	POSTING_READ(GEN6_PMIMR);	401	POSTING_READ(GEN6_PMIMR);
400	spin_unlock_irqrestore(&dev_priv->rps.lock, flags);	402	spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
401		403
402	// queue_work(dev_priv->wq, &dev_priv->rps.work);	404	// queue_work(dev_priv->wq, &dev_priv->rps.work);
403	}	405	}
-		406
-		407	static void gmbus_irq_handler(struct drm_device *dev)
-		408	{
-		409	struct drm_i915_private dev_priv = (drm_i915_private_t ) dev->dev_private;
-		410
-		411	wake_up_all(&dev_priv->gmbus_wait_queue);
-		412	}
-		413
-		414	static void dp_aux_irq_handler(struct drm_device *dev)
-		415	{
-		416	struct drm_i915_private dev_priv = (drm_i915_private_t ) dev->dev_private;
-		417
-		418	wake_up_all(&dev_priv->gmbus_wait_queue);
-		419	}
404		420
405	static irqreturn_t valleyview_irq_handler(int irq, void *arg)	421	static irqreturn_t valleyview_irq_handler(int irq, void *arg)
406	{	422	{
407	struct drm_device dev = (struct drm_device ) arg;	423	struct drm_device dev = (struct drm_device ) arg;
408	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;	424	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
409	u32 iir, gt_iir, pm_iir;	425	u32 iir, gt_iir, pm_iir;
410	irqreturn_t ret = IRQ_NONE;	426	irqreturn_t ret = IRQ_NONE;
411	unsigned long irqflags;	427	unsigned long irqflags;
412	int pipe;	428	int pipe;
413	u32 pipe_stats[I915_MAX_PIPES];	429	u32 pipe_stats[I915_MAX_PIPES];
414	bool blc_event;	-
415		430
416	atomic_inc(&dev_priv->irq_received);	431	atomic_inc(&dev_priv->irq_received);
417		432
418	while (true) {	433	while (true) {
419	iir = I915_READ(VLV_IIR);	434	iir = I915_READ(VLV_IIR);
420	gt_iir = I915_READ(GTIIR);	435	gt_iir = I915_READ(GTIIR);
421	pm_iir = I915_READ(GEN6_PMIIR);	436	pm_iir = I915_READ(GEN6_PMIIR);
422		437
423	if (gt_iir == 0 && pm_iir == 0 && iir == 0)	438	if (gt_iir == 0 && pm_iir == 0 && iir == 0)
424	goto out;	439	goto out;
425		440
426	ret = IRQ_HANDLED;	441	ret = IRQ_HANDLED;
427		442
428	snb_gt_irq_handler(dev, dev_priv, gt_iir);	443	snb_gt_irq_handler(dev, dev_priv, gt_iir);
429		444
430	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);	445	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
431	for_each_pipe(pipe) {	446	for_each_pipe(pipe) {
432	int reg = PIPESTAT(pipe);	447	int reg = PIPESTAT(pipe);
433	pipe_stats[pipe] = I915_READ(reg);	448	pipe_stats[pipe] = I915_READ(reg);
434		449
435	/*	450	/*
436	* Clear the PIPE*STAT regs before the IIR	451	* Clear the PIPE*STAT regs before the IIR
437	*/	452	*/
438	if (pipe_stats[pipe] & 0x8000ffff) {	453	if (pipe_stats[pipe] & 0x8000ffff) {
439	if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)	454	if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
440	DRM_DEBUG_DRIVER("pipe %c underrun\n",	455	DRM_DEBUG_DRIVER("pipe %c underrun\n",
441	pipe_name(pipe));	456	pipe_name(pipe));
442	I915_WRITE(reg, pipe_stats[pipe]);	457	I915_WRITE(reg, pipe_stats[pipe]);
443	}	458	}
444	}	459	}
445	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);	460	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
446		461
447	#if 0	462	#if 0
448	for_each_pipe(pipe) {	463	for_each_pipe(pipe) {
449	if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)	464	if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
450	drm_handle_vblank(dev, pipe);	465	drm_handle_vblank(dev, pipe);
451		466
452	if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {	467	if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
453	intel_prepare_page_flip(dev, pipe);	468	intel_prepare_page_flip(dev, pipe);
454	intel_finish_page_flip(dev, pipe);	469	intel_finish_page_flip(dev, pipe);
455	}	470	}
456	}	471	}
457	#endif	472	#endif
458		473
459	/* Consume port. Then clear IIR or we'll miss events */	474	/* Consume port. Then clear IIR or we'll miss events */

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_irq.c – Rev 3298 → 3480