WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem.c


/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt 
 *
 */
 
#include 
#include 
#include 
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
#include 
#include 
//#include 
#include 
#include 
 
extern int x86_clflush_size;
 
#define PROT_READ       0x1             /* page can be read */
#define PROT_WRITE      0x2             /* page can be written */
#define MAP_SHARED      0x01            /* Share changes */
 
 
u64 nsecs_to_jiffies64(u64 n)
{
#if (NSEC_PER_SEC % HZ) == 0
        /* Common case, HZ = 100, 128, 200, 250, 256, 500, 512, 1000 etc. */
        return div_u64(n, NSEC_PER_SEC / HZ);
#elif (HZ % 512) == 0
        /* overflow after 292 years if HZ = 1024 */
        return div_u64(n * HZ / 512, NSEC_PER_SEC / 512);
#else
        /*
         * Generic case - optimized for cases where HZ is a multiple of 3.
         * overflow after 64.99 years, exact for HZ = 60, 72, 90, 120 etc.
         */
        return div_u64(n * 9, (9ull * NSEC_PER_SEC + HZ / 2) / HZ);
#endif
}
 
unsigned long nsecs_to_jiffies(u64 n)
{
    return (unsigned long)nsecs_to_jiffies64(n);
}
 
 
struct drm_i915_gem_object *get_fb_obj();
 
unsigned long vm_mmap(struct file *file, unsigned long addr,
         unsigned long len, unsigned long prot,
         unsigned long flag, unsigned long offset);
 
 
 
 
 
 
#define MAX_ERRNO       4095
 
#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
 
 
static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
						   bool force);
static __must_check int
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly);
static void
i915_gem_object_retire(struct drm_i915_gem_object *obj);
 
static void i915_gem_write_fence(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj);
static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
					 struct drm_i915_fence_reg *fence,
					 bool enable);
 
 
 
static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
 
static bool cpu_cache_is_coherent(struct drm_device *dev,
				  enum i915_cache_level level)
{
	return HAS_LLC(dev) || level != I915_CACHE_NONE;
}
 
static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
	if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
		return true;
 
	return obj->pin_display;
}
 
static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
{
	if (obj->tiling_mode)
		i915_gem_release_mmap(obj);
 
	/* As we do not have an associated fence register, we will force
	 * a tiling change if we ever need to acquire one.
	 */
	obj->fence_dirty = false;
	obj->fence_reg = I915_FENCE_REG_NONE;
}
 
/* some bookkeeping */
static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
				  size_t size)
{
	spin_lock(&dev_priv->mm.object_stat_lock);
	dev_priv->mm.object_count++;
	dev_priv->mm.object_memory += size;
	spin_unlock(&dev_priv->mm.object_stat_lock);
}
 
static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
				     size_t size)
{
	spin_lock(&dev_priv->mm.object_stat_lock);
	dev_priv->mm.object_count--;
	dev_priv->mm.object_memory -= size;
	spin_unlock(&dev_priv->mm.object_stat_lock);
}
 
static int
i915_gem_wait_for_error(struct i915_gpu_error *error)
{
	int ret;
 
#define EXIT_COND (!i915_reset_in_progress(error))
	if (EXIT_COND)
		return 0;
#if 0
	/*
	 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
	 * userspace. If it takes that long something really bad is going on and
	 * we should simply try to bail out and fail as gracefully as possible.
	 */
	ret = wait_event_interruptible_timeout(error->reset_queue,
					       EXIT_COND,
					       10*HZ);
	if (ret == 0) {
		DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
		return -EIO;
	} else if (ret < 0) {
		return ret;
	}
 
#endif
#undef EXIT_COND
 
	return 0;
}
 
int i915_mutex_lock_interruptible(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
 
	ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
	if (ret)
		return ret;
 
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
 
	WARN_ON(i915_verify_lists(dev));
	return 0;
}
 
static inline bool
i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
{
	return i915_gem_obj_bound_any(obj) && !obj->active;
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_get_aperture *args = data;
	struct drm_i915_gem_object *obj;
	size_t pinned;
 
	pinned = 0;
	mutex_lock(&dev->struct_mutex);
	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
		if (i915_gem_obj_is_pinned(obj))
			pinned += i915_gem_obj_ggtt_size(obj);
	mutex_unlock(&dev->struct_mutex);
 
	args->aper_size = dev_priv->gtt.base.total;
	args->aper_available_size = args->aper_size - pinned;
 
	return 0;
}
 
void *i915_gem_object_alloc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	return kmalloc(sizeof(struct drm_i915_gem_object), 0);
}
 
void i915_gem_object_free(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	kfree(obj);
}
 
static int
i915_gem_create(struct drm_file *file,
		struct drm_device *dev,
		uint64_t size,
		uint32_t *handle_p)
{
	struct drm_i915_gem_object *obj;
	int ret;
	u32 handle;
 
	size = roundup(size, PAGE_SIZE);
	if (size == 0)
		return -EINVAL;
 
	/* Allocate the new object */
	obj = i915_gem_alloc_object(dev, size);
	if (obj == NULL)
		return -ENOMEM;
 
	ret = drm_gem_handle_create(file, &obj->base, &handle);
	/* drop reference from allocate - handle holds it now */
	drm_gem_object_unreference_unlocked(&obj->base);
	if (ret)
		return ret;
 
	*handle_p = handle;
	return 0;
}
 
int
i915_gem_dumb_create(struct drm_file *file,
		     struct drm_device *dev,
		     struct drm_mode_create_dumb *args)
{
	/* have to work out size/pitch and return them */
	args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
	args->size = args->pitch * args->height;
	return i915_gem_create(file, dev,
			       args->size, &args->handle);
}
 
/**
 * Creates a new mm object and returns a handle to it.
 */
int
i915_gem_create_ioctl(struct drm_device *dev, void *data,
		      struct drm_file *file)
{
	struct drm_i915_gem_create *args = data;
 
	return i915_gem_create(file, dev,
			       args->size, &args->handle);
}
 
 
#if 0
 
static inline int
__copy_to_user_swizzled(char __user *cpu_vaddr,
			const char *gpu_vaddr, int gpu_offset,
		int length)
{
	int ret, cpu_offset = 0;
 
	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;
 
		ret = __copy_to_user(cpu_vaddr + cpu_offset,
				     gpu_vaddr + swizzled_gpu_offset,
				     this_length);
		if (ret)
			return ret + length;
 
		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}
 
	return 0;
}
 
static inline int
__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
			  const char __user *cpu_vaddr,
			  int length)
{
	int ret, cpu_offset = 0;
 
	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;
 
		ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
			       cpu_vaddr + cpu_offset,
			       this_length);
		if (ret)
			return ret + length;
 
		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}
 
	return 0;
}
 
/* Per-page copy function for the shmem pread fastpath.
 * Flushes invalid cachelines before reading the target if
 * needs_clflush is set. */
static int
shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
		char *vaddr;
		int ret;
 
	if (unlikely(page_do_bit17_swizzling))
		return -EINVAL;
 
		vaddr = kmap_atomic(page);
	if (needs_clflush)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
		ret = __copy_to_user_inatomic(user_data,
				      vaddr + shmem_page_offset,
					      page_length);
		kunmap_atomic(vaddr);
 
	return ret ? -EFAULT : 0;
}
 
static void
shmem_clflush_swizzled_range(char *addr, unsigned long length,
			     bool swizzled)
{
	if (unlikely(swizzled)) {
		unsigned long start = (unsigned long) addr;
		unsigned long end = (unsigned long) addr + length;
 
		/* For swizzling simply ensure that we always flush both
		 * channels. Lame, but simple and it works. Swizzled
		 * pwrite/pread is far from a hotpath - current userspace
		 * doesn't use it at all. */
		start = round_down(start, 128);
		end = round_up(end, 128);
 
		drm_clflush_virt_range((void *)start, end - start);
	} else {
		drm_clflush_virt_range(addr, length);
	}
 
}
 
/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
static int
shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;
 
	vaddr = kmap(page);
	if (needs_clflush)
		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
 
	if (page_do_bit17_swizzling)
		ret = __copy_to_user_swizzled(user_data,
					      vaddr, shmem_page_offset,
					      page_length);
	else
		ret = __copy_to_user(user_data,
				     vaddr + shmem_page_offset,
				     page_length);
	kunmap(page);
 
	return ret ? - EFAULT : 0;
}
 
static int
i915_gem_shmem_pread(struct drm_device *dev,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_pread *args,
			  struct drm_file *file)
{
	char __user *user_data;
	ssize_t remain;
	loff_t offset;
	int shmem_page_offset, page_length, ret = 0;
	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
	int prefaulted = 0;
	int needs_clflush = 0;
	struct sg_page_iter sg_iter;
 
	user_data = to_user_ptr(args->data_ptr);
	remain = args->size;
 
	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 
	ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
	if (ret)
		return ret;
 
	offset = args->offset;
 
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
			 offset >> PAGE_SHIFT) {
		struct page *page = sg_page_iter_page(&sg_iter);
 
		if (remain <= 0)
			break;
 
		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
		shmem_page_offset = offset_in_page(offset);
		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;
 
		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;
 
		ret = shmem_pread_fast(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
		if (ret == 0)
			goto next_page;
 
		mutex_unlock(&dev->struct_mutex);
 
		if (likely(!i915.prefault_disable) && !prefaulted) {
			ret = fault_in_multipages_writeable(user_data, remain);
			/* Userspace is tricking us, but we've already clobbered
			 * its pages with the prefault and promised to write the
			 * data up to the first fault. Hence ignore any errors
			 * and just continue. */
			(void)ret;
			prefaulted = 1;
		}
 
		ret = shmem_pread_slow(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
 
		mutex_lock(&dev->struct_mutex);
 
		if (ret)
			goto out;
 
next_page:
		remain -= page_length;
		user_data += page_length;
		offset += page_length;
	}
 
out:
	i915_gem_object_unpin_pages(obj);
 
	return ret;
}
 
/**
 * Reads data from the object referenced by handle.
 *
 * On error, the contents of *data are undefined.
 */
int
i915_gem_pread_ioctl(struct drm_device *dev, void *data,
		     struct drm_file *file)
{
	struct drm_i915_gem_pread *args = data;
	struct drm_i915_gem_object *obj;
	int ret = 0;
 
	if (args->size == 0)
		return 0;
 
	if (!access_ok(VERIFY_WRITE,
		       to_user_ptr(args->data_ptr),
		       args->size))
		return -EFAULT;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}
 
	/* Bounds check source.  */
	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
		ret = -EINVAL;
		goto out;
	}
 
	/* prime objects have no backing filp to GEM pread/pwrite
	 * pages from.
	 */
	if (!obj->base.filp) {
		ret = -EINVAL;
		goto out;
	}
 
	trace_i915_gem_object_pread(obj, args->offset, args->size);
 
	ret = i915_gem_shmem_pread(dev, obj, args, file);
 
out:
	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
 
/* This is the fast write path which cannot handle
 * page faults in the source data
 */
 
static inline int
fast_user_write(struct io_mapping *mapping,
		loff_t page_base, int page_offset,
		char __user *user_data,
		int length)
{
	void __iomem *vaddr_atomic;
	void *vaddr;
	unsigned long unwritten;
 
	vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
	/* We can use the cpu mem copy function because this is X86. */
	vaddr = (void __force*)vaddr_atomic + page_offset;
	unwritten = __copy_from_user_inatomic_nocache(vaddr,
						      user_data, length);
	io_mapping_unmap_atomic(vaddr_atomic);
	return unwritten;
}
#endif
 
#define offset_in_page(p)       ((unsigned long)(p) & ~PAGE_MASK)
/**
 * This is the fast pwrite path, where we copy the data directly from the
 * user into the GTT, uncached.
 */
static int
i915_gem_gtt_pwrite_fast(struct drm_device *dev,
			 struct drm_i915_gem_object *obj,
			 struct drm_i915_gem_pwrite *args,
			 struct drm_file *file)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	ssize_t remain;
	loff_t offset, page_base;
	char __user *user_data;
	int page_offset, page_length, ret;
 
	ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
	if (ret)
		goto out;
 
	ret = i915_gem_object_set_to_gtt_domain(obj, true);
	if (ret)
		goto out_unpin;
 
	ret = i915_gem_object_put_fence(obj);
	if (ret)
		goto out_unpin;
 
	user_data = to_user_ptr(args->data_ptr);
	remain = args->size;
 
	offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 
	while (remain > 0) {
		/* Operation in this page
		 *
		 * page_base = page offset within aperture
		 * page_offset = offset within page
		 * page_length = bytes to copy for this page
		 */
		page_base = offset & PAGE_MASK;
		page_offset = offset_in_page(offset);
		page_length = remain;
		if ((page_offset + remain) > PAGE_SIZE)
			page_length = PAGE_SIZE - page_offset;
 
        MapPage(dev_priv->gtt.mappable, dev_priv->gtt.mappable_base+page_base, PG_SW);
 
        memcpy((char*)dev_priv->gtt.mappable+page_offset, user_data, page_length);
 
		remain -= page_length;
		user_data += page_length;
		offset += page_length;
	}
 
out_unpin:
	i915_gem_object_ggtt_unpin(obj);
out:
    return ret;
}
 
/* Per-page copy function for the shmem pwrite fastpath.
 * Flushes invalid cachelines before writing to the target if
 * needs_clflush_before is set and flushes out any written cachelines after
 * writing if needs_clflush is set. */
static int
shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
{
	char *vaddr;
	int ret;
 
	if (unlikely(page_do_bit17_swizzling))
		return -EINVAL;
 
	vaddr = kmap_atomic(page);
	if (needs_clflush_before)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	memcpy(vaddr + shmem_page_offset,
						user_data,
						page_length);
	if (needs_clflush_after)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	kunmap_atomic(vaddr);
 
	return ret ? -EFAULT : 0;
}
#if 0
 
/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
static int
shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
{
	char *vaddr;
	int ret;
 
	vaddr = kmap(page);
	if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
	if (page_do_bit17_swizzling)
		ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
						user_data,
						page_length);
	else
		ret = __copy_from_user(vaddr + shmem_page_offset,
				       user_data,
				       page_length);
	if (needs_clflush_after)
		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
	kunmap(page);
 
	return ret ? -EFAULT : 0;
}
#endif
 
 
static int
i915_gem_shmem_pwrite(struct drm_device *dev,
		      struct drm_i915_gem_object *obj,
		      struct drm_i915_gem_pwrite *args,
		      struct drm_file *file)
{
	ssize_t remain;
	loff_t offset;
	char __user *user_data;
	int shmem_page_offset, page_length, ret = 0;
	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
	int hit_slowpath = 0;
	int needs_clflush_after = 0;
	int needs_clflush_before = 0;
	struct sg_page_iter sg_iter;
 
	user_data = to_user_ptr(args->data_ptr);
	remain = args->size;
 
	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 
	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
		/* If we're not in the cpu write domain, set ourself into the gtt
		 * write domain and manually flush cachelines (if required). This
		 * optimizes for the case when the gpu will use the data
		 * right away and we therefore have to clflush anyway. */
		needs_clflush_after = cpu_write_needs_clflush(obj);
		ret = i915_gem_object_wait_rendering(obj, false);
			if (ret)
				return ret;
 
		i915_gem_object_retire(obj);
		}
	/* Same trick applies to invalidate partially written cachelines read
	 * before writing. */
	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
		needs_clflush_before =
			!cpu_cache_is_coherent(dev, obj->cache_level);
 
	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ret;
 
	i915_gem_object_pin_pages(obj);
 
	offset = args->offset;
	obj->dirty = 1;
 
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
			 offset >> PAGE_SHIFT) {
		struct page *page = sg_page_iter_page(&sg_iter);
		int partial_cacheline_write;
 
		if (remain <= 0)
			break;
 
		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
		shmem_page_offset = offset_in_page(offset);
 
		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;
 
		/* If we don't overwrite a cacheline completely we need to be
		 * careful to have up-to-date data by first clflushing. Don't
		 * overcomplicate things and flush the entire patch. */
		partial_cacheline_write = needs_clflush_before &&
			((shmem_page_offset | page_length)
				& (x86_clflush_size - 1));
 
		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;
 
		ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
					user_data, page_do_bit17_swizzling,
					partial_cacheline_write,
					needs_clflush_after);
		if (ret == 0)
			goto next_page;
 
		hit_slowpath = 1;
		mutex_unlock(&dev->struct_mutex);
		dbgprintf("%s need shmem_pwrite_slow\n",__FUNCTION__);
 
//		ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
//					user_data, page_do_bit17_swizzling,
//					partial_cacheline_write,
//					needs_clflush_after);
 
		mutex_lock(&dev->struct_mutex);
 
 
 
		if (ret)
			goto out;
 
next_page:
		remain -= page_length;
		user_data += page_length;
		offset += page_length;
	}
 
out:
	i915_gem_object_unpin_pages(obj);
 
	if (hit_slowpath) {
		/*
		 * Fixup: Flush cpu caches in case we didn't flush the dirty
		 * cachelines in-line while writing and the object moved
		 * out of the cpu write domain while we've dropped the lock.
		 */
		if (!needs_clflush_after &&
		    obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
			if (i915_gem_clflush_object(obj, obj->pin_display))
			i915_gem_chipset_flush(dev);
		}
	}
 
	if (needs_clflush_after)
		i915_gem_chipset_flush(dev);
 
	return ret;
}
 
/**
 * Writes data to the object referenced by handle.
 *
 * On error, the contents of the buffer that were to be modified are undefined.
 */
int
i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
		      struct drm_file *file)
{
	struct drm_i915_gem_pwrite *args = data;
	struct drm_i915_gem_object *obj;
	int ret;
 
	if (args->size == 0)
		return 0;
 
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}
 
	/* Bounds check destination. */
	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
		ret = -EINVAL;
		goto out;
	}
 
	/* prime objects have no backing filp to GEM pread/pwrite
	 * pages from.
	 */
	if (!obj->base.filp) {
		ret = -EINVAL;
		goto out;
	}
 
	trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 
	ret = -EFAULT;
	/* We can only do the GTT pwrite on untiled buffers, as otherwise
	 * it would end up going through the fenced access, and we'll get
	 * different detiling behavior between reading and writing.
	 * pread/pwrite currently are reading and writing from the CPU
	 * perspective, requiring manual detiling by the client.
	 */
 
 
 
 
 
	if (obj->tiling_mode == I915_TILING_NONE &&
	    obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
	    cpu_write_needs_clflush(obj)) {
		ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
		/* Note that the gtt paths might fail with non-page-backed user
		 * pointers (e.g. gtt mappings when moving data between
		 * textures). Fallback to the shmem path in that case. */
	}
 
	if (ret == -EFAULT || ret == -ENOSPC)
       ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 
out:
	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
 
int
i915_gem_check_wedge(struct i915_gpu_error *error,
		     bool interruptible)
{
	if (i915_reset_in_progress(error)) {
		/* Non-interruptible callers can't handle -EAGAIN, hence return
		 * -EIO unconditionally for these. */
		if (!interruptible)
			return -EIO;
 
		/* Recovery complete, but the reset failed ... */
		if (i915_terminally_wedged(error))
			return -EIO;
 
		return -EAGAIN;
	}
 
	return 0;
}
 
/*
 * Compare seqno against outstanding lazy request. Emit a request if they are
 * equal.
 */
int
i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
{
	int ret;
 
	BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 
	ret = 0;
	if (seqno == ring->outstanding_lazy_seqno)
		ret = i915_add_request(ring, NULL);
 
	return ret;
}
 
static void fake_irq(unsigned long data)
{
//	wake_up_process((struct task_struct *)data);
}
 
static bool missed_irq(struct drm_i915_private *dev_priv,
		       struct intel_engine_cs *ring)
{
	return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
}
 
static bool can_wait_boost(struct drm_i915_file_private *file_priv)
{
	if (file_priv == NULL)
		return true;
 
	return !atomic_xchg(&file_priv->rps_wait_boost, true);
}
 
/**
 * __i915_wait_seqno - wait until execution of seqno has finished
 * @ring: the ring expected to report seqno
 * @seqno: duh!
 * @reset_counter: reset sequence associated with the given seqno
 * @interruptible: do an interruptible wait (normally yes)
 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 *
 * Note: It is of utmost importance that the passed in seqno and reset_counter
 * values have been read by the caller in an smp safe manner. Where read-side
 * locks are involved, it is sufficient to read the reset_counter before
 * unlocking the lock that protects the seqno. For lockless tricks, the
 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
 * inserted.
 *
 * Returns 0 if the seqno was found within the alloted time. Else returns the
 * errno with remaining time filled in timeout argument.
 */
int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
			unsigned reset_counter,
			bool interruptible,
			s64 *timeout,
			struct drm_i915_file_private *file_priv)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	const bool irq_test_in_progress =
		ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
	unsigned long timeout_expire;
	s64 before, now;
 
    wait_queue_t __wait;
	int ret;
 
	WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
 
	if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
		return 0;
 
	timeout_expire = timeout ?
		jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
 
	if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
		gen6_rps_boost(dev_priv);
		if (file_priv)
			mod_delayed_work(dev_priv->wq,
					 &file_priv->mm.idle_work,
					 msecs_to_jiffies(100));
	}
 
	if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
		return -ENODEV;
 
    INIT_LIST_HEAD(&__wait.task_list);
    __wait.evnt = CreateEvent(NULL, MANUAL_DESTROY);
 
	/* Record current time in case interrupted by signal, or wedged */
	trace_i915_gem_request_wait_begin(ring, seqno);
 
	for (;;) {
        unsigned long flags;
 
		/* We need to check whether any gpu reset happened in between
		 * the caller grabbing the seqno and now ... */
		if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
			/* ... but upgrade the -EAGAIN to an -EIO if the gpu
			 * is truely gone. */
			ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
			if (ret == 0)
				ret = -EAGAIN;
			break;
		}
 
		if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
			ret = 0;
			break;
		}
 
        if (timeout && time_after_eq(jiffies, timeout_expire)) {
			ret = -ETIME;
			break;
		}
 
        spin_lock_irqsave(&ring->irq_queue.lock, flags);
        if (list_empty(&__wait.task_list))
            __add_wait_queue(&ring->irq_queue, &__wait);
        spin_unlock_irqrestore(&ring->irq_queue.lock, flags);
 
        WaitEventTimeout(__wait.evnt, 1);
 
        if (!list_empty(&__wait.task_list)) {
            spin_lock_irqsave(&ring->irq_queue.lock, flags);
            list_del_init(&__wait.task_list);
            spin_unlock_irqrestore(&ring->irq_queue.lock, flags);
        }
    };
    trace_i915_gem_request_wait_end(ring, seqno);
 
    DestroyEvent(__wait.evnt);
 
	if (!irq_test_in_progress)
        ring->irq_put(ring);
 
//	finish_wait(&ring->irq_queue, &wait);
	return ret;
}
 
/**
 * Waits for a sequence number to be signaled, and cleans up the
 * request and object lists appropriately for that event.
 */
int
i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool interruptible = dev_priv->mm.interruptible;
	unsigned reset_counter;
	int ret;
 
	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
	BUG_ON(seqno == 0);
 
	ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
	if (ret)
		return ret;
 
	ret = i915_gem_check_olr(ring, seqno);
	if (ret)
		return ret;
 
	reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
	return __i915_wait_seqno(ring, seqno, reset_counter, interruptible,
				 NULL, NULL);
}
 
static int
i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
 
{
	if (!obj->active)
		return 0;
 
	/* Manually manage the write flush as we may have not yet
	 * retired the buffer.
	 *
	 * Note that the last_write_seqno is always the earlier of
	 * the two (read/write) seqno, so if we haved successfully waited,
	 * we know we have passed the last write.
	 */
	obj->last_write_seqno = 0;
 
	return 0;
}
 
/**
 * Ensures that all rendering to the object has completed and the object is
 * safe to unbind from the GTT or access from the CPU.
 */
static __must_check int
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly)
{
	struct intel_engine_cs *ring = obj->ring;
	u32 seqno;
	int ret;
 
	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
	if (seqno == 0)
		return 0;
 
	ret = i915_wait_seqno(ring, seqno);
    if (ret)
        return ret;
 
	return i915_gem_object_wait_rendering__tail(obj);
}
 
/* A nonblocking variant of the above wait. This is a highly dangerous routine
 * as the object state may change during this call.
 */
static __must_check int
i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
					    struct drm_i915_file_private *file_priv,
					    bool readonly)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring = obj->ring;
	unsigned reset_counter;
	u32 seqno;
	int ret;
 
	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
	BUG_ON(!dev_priv->mm.interruptible);
 
	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
	if (seqno == 0)
		return 0;
 
	ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
	if (ret)
		return ret;
 
	ret = i915_gem_check_olr(ring, seqno);
	if (ret)
		return ret;
 
	reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
	mutex_unlock(&dev->struct_mutex);
	ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL,
				file_priv);
	mutex_lock(&dev->struct_mutex);
	if (ret)
		return ret;
 
	return i915_gem_object_wait_rendering__tail(obj);
}
 
/**
 * Called when user space prepares to use an object with the CPU, either
 * through the mmap ioctl's mapping or a GTT mapping.
 */
int
i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file)
{
	struct drm_i915_gem_set_domain *args = data;
	struct drm_i915_gem_object *obj;
	uint32_t read_domains = args->read_domains;
	uint32_t write_domain = args->write_domain;
	int ret;
 
	/* Only handle setting domains to types used by the CPU. */
	if (write_domain & I915_GEM_GPU_DOMAINS)
		return -EINVAL;
 
	if (read_domains & I915_GEM_GPU_DOMAINS)
		return -EINVAL;
 
	/* Having something in the write domain implies it's in the read
	 * domain, and only that read domain.  Enforce that in the request.
	 */
	if (write_domain != 0 && read_domains != write_domain)
		return -EINVAL;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}
 
	/* Try to flush the object off the GPU without holding the lock.
	 * We will repeat the flush holding the lock in the normal manner
	 * to catch cases where we are gazumped.
	 */
	ret = i915_gem_object_wait_rendering__nonblocking(obj,
							  file->driver_priv,
							  !write_domain);
	if (ret)
		goto unref;
 
	if (read_domains & I915_GEM_DOMAIN_GTT) {
		ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
 
		/* Silently promote "you're not bound, there was nothing to do"
		 * to success, since the client was just asking us to
		 * make sure everything was done.
		 */
		if (ret == -EINVAL)
			ret = 0;
	} else {
		ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
	}
 
unref:
	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
 
/**
 * Called when user space has done writes to this buffer
 */
int
i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file)
{
	struct drm_i915_gem_sw_finish *args = data;
	struct drm_i915_gem_object *obj;
	int ret = 0;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}
 
	/* Pinned buffers may be scanout, so flush the cache */
	if (obj->pin_display)
		i915_gem_object_flush_cpu_write_domain(obj, true);
 
	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
 
/**
 * Maps the contents of an object, returning the address it is mapped
 * into.
 *
 * While the mapping holds a reference on the contents of the object, it doesn't
 * imply a ref on the object itself.
 *
 * IMPORTANT:
 *
 * DRM driver writers who look a this function as an example for how to do GEM
 * mmap support, please don't implement mmap support like here. The modern way
 * to implement DRM mmap support is with an mmap offset ioctl (like
 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
 * That way debug tooling like valgrind will understand what's going on, hiding
 * the mmap call in a driver private ioctl will break that. The i915 driver only
 * does cpu mmaps this way because we didn't know better.
 */
int
i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
		    struct drm_file *file)
{
	struct drm_i915_gem_mmap *args = data;
	struct drm_gem_object *obj;
	unsigned long addr;
 
	obj = drm_gem_object_lookup(dev, file, args->handle);
	if (obj == NULL)
		return -ENOENT;
 
	/* prime objects have no backing filp to GEM mmap
	 * pages from.
	 */
	if (!obj->filp) {
		drm_gem_object_unreference_unlocked(obj);
		return -EINVAL;
	}
 
    addr = vm_mmap(obj->filp, 0, args->size,
              PROT_READ | PROT_WRITE, MAP_SHARED,
              args->offset);
	drm_gem_object_unreference_unlocked(obj);
    if (IS_ERR((void *)addr))
        return addr;
 
	args->addr_ptr = (uint64_t) addr;
 
    return 0;
}
 
 
 
 
 
 
 
 
 
 
 
 
 
/**
 * i915_gem_release_mmap - remove physical page mappings
 * @obj: obj in question
 *
 * Preserve the reservation of the mmapping with the DRM core code, but
 * relinquish ownership of the pages back to the system.
 *
 * It is vital that we remove the page mapping if we have mapped a tiled
 * object through the GTT and then lose the fence register due to
 * resource pressure. Similarly if the object has been moved out of the
 * aperture, than pages mapped into userspace must be revoked. Removing the
 * mapping will then trigger a page fault on the next user access, allowing
 * fixup by i915_gem_fault().
 */
void
i915_gem_release_mmap(struct drm_i915_gem_object *obj)
{
	if (!obj->fault_mappable)
		return;
 
//	drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
	obj->fault_mappable = false;
}
 
uint32_t
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
{
	uint32_t gtt_size;
 
	if (INTEL_INFO(dev)->gen >= 4 ||
	    tiling_mode == I915_TILING_NONE)
		return size;
 
	/* Previous chips need a power-of-two fence region when tiling */
	if (INTEL_INFO(dev)->gen == 3)
		gtt_size = 1024*1024;
	else
		gtt_size = 512*1024;
 
	while (gtt_size < size)
		gtt_size <<= 1;
 
	return gtt_size;
}
 
/**
 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
 * @obj: object to check
 *
 * Return the required GTT alignment for an object, taking into account
 * potential fence register mapping.
 */
uint32_t
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
			   int tiling_mode, bool fenced)
{
	/*
	 * Minimum alignment is 4k (GTT page size), but might be greater
	 * if a fence register is needed for the object.
	 */
	if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
	    tiling_mode == I915_TILING_NONE)
		return 4096;
 
	/*
	 * Previous chips need to be aligned to the size of the smallest
	 * fence register that can contain the object.
	 */
	return i915_gem_get_gtt_size(dev, size, tiling_mode);
}
 
 
 
int
i915_gem_mmap_gtt(struct drm_file *file,
          struct drm_device *dev,
          uint32_t handle,
          uint64_t *offset)
{
    struct drm_i915_private *dev_priv = dev->dev_private;
    struct drm_i915_gem_object *obj;
    unsigned long pfn;
    char *mem, *ptr;
    int ret;
 
    ret = i915_mutex_lock_interruptible(dev);
    if (ret)
        return ret;
 
    obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
    if (&obj->base == NULL) {
        ret = -ENOENT;
        goto unlock;
    }
 
    if (obj->base.size > dev_priv->gtt.mappable_end) {
        ret = -E2BIG;
        goto out;
    }
 
    if (obj->madv != I915_MADV_WILLNEED) {
		DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
		ret = -EFAULT;
        goto out;
    }
    /* Now bind it into the GTT if needed */
	ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
    if (ret)
        goto out;
 
    ret = i915_gem_object_set_to_gtt_domain(obj, 1);
    if (ret)
        goto unpin;
 
    ret = i915_gem_object_get_fence(obj);
    if (ret)
        goto unpin;
 
    obj->fault_mappable = true;
 
    pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
 
    /* Finally, remap it using the new GTT offset */
 
    mem = UserAlloc(obj->base.size);
    if(unlikely(mem == NULL))
    {
        ret = -ENOMEM;
        goto unpin;
    }
 
    for(ptr = mem; ptr < mem + obj->base.size; ptr+= 4096, pfn+= 4096)
        MapPage(ptr, pfn, PG_SHARED|PG_UW);
 
unpin:
    i915_gem_object_unpin_pages(obj);
 
 
    *offset = mem;
 
out:
    drm_gem_object_unreference(&obj->base);
unlock:
    mutex_unlock(&dev->struct_mutex);
    return ret;
}
 
/**
 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
 * @dev: DRM device
 * @data: GTT mapping ioctl data
 * @file: GEM object info
 *
 * Simply returns the fake offset to userspace so it can mmap it.
 * The mmap call will end up in drm_gem_mmap(), which will set things
 * up so we can get faults in the handler above.
 *
 * The fault handler will take care of binding the object into the GTT
 * (since it may have been evicted to make room for something), allocating
 * a fence register, and mapping the appropriate aperture address into
 * userspace.
 */
int
i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
            struct drm_file *file)
{
    struct drm_i915_gem_mmap_gtt *args = data;
 
    return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
}
 
static inline int
i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
{
	return obj->madv == I915_MADV_DONTNEED;
}
 
/* Immediately discard the backing storage */
static void
i915_gem_object_truncate(struct drm_i915_gem_object *obj)
{
//	i915_gem_object_free_mmap_offset(obj);
 
	if (obj->base.filp == NULL)
		return;
 
	/* Our goal here is to return as much of the memory as
	 * is possible back to the system as we are called from OOM.
	 * To do this we must instruct the shmfs to drop all of its
	 * backing pages, *now*.
	 */
//	shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
	obj->madv = __I915_MADV_PURGED;
}
 
/* Try to discard unwanted pages */
static void
i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
{
	struct address_space *mapping;
 
	switch (obj->madv) {
	case I915_MADV_DONTNEED:
		i915_gem_object_truncate(obj);
	case __I915_MADV_PURGED:
		return;
	}
 
	if (obj->base.filp == NULL)
		return;
 
}
 
static void
i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
{
	struct sg_page_iter sg_iter;
	int ret;
 
	BUG_ON(obj->madv == __I915_MADV_PURGED);
 
	ret = i915_gem_object_set_to_cpu_domain(obj, true);
	if (ret) {
		/* In the event of a disaster, abandon all caches and
		 * hope for the best.
		 */
		WARN_ON(ret != -EIO);
		i915_gem_clflush_object(obj, true);
		obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	}
 
	if (obj->madv == I915_MADV_DONTNEED)
		obj->dirty = 0;
 
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
		struct page *page = sg_page_iter_page(&sg_iter);
 
        page_cache_release(page);
	}
    obj->dirty = 0;
 
	sg_free_table(obj->pages);
	kfree(obj->pages);
}
 
int
i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
{
	const struct drm_i915_gem_object_ops *ops = obj->ops;
 
	if (obj->pages == NULL)
		return 0;
 
	if (obj->pages_pin_count)
		return -EBUSY;
 
	BUG_ON(i915_gem_obj_bound_any(obj));
 
	/* ->put_pages might need to allocate memory for the bit17 swizzle
	 * array, hence protect them from being reaped by removing them from gtt
	 * lists early. */
	list_del(&obj->global_list);
 
	ops->put_pages(obj);
	obj->pages = NULL;
 
	i915_gem_object_invalidate(obj);
 
	return 0;
}
 
 
 
 
 
 
 
 
static int
i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
    int page_count, i;
    struct sg_table *st;
	struct scatterlist *sg;
	struct sg_page_iter sg_iter;
	struct page *page;
	unsigned long last_pfn = 0;	/* suppress gcc warning */
	gfp_t gfp;
 
	/* Assert that the object is not currently in any GPU domain. As it
	 * wasn't in the GTT, there shouldn't be any way it could have been in
	 * a GPU cache
	 */
	BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
	BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
 
	st = kmalloc(sizeof(*st), GFP_KERNEL);
	if (st == NULL)
		return -ENOMEM;
 
	page_count = obj->base.size / PAGE_SIZE;
	if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
		kfree(st);
        FAIL();
		return -ENOMEM;
	}
 
	/* Get the list of pages out of our struct file.  They'll be pinned
	 * at this point until we release them.
	 *
	 * Fail silently without starting the shrinker
	 */
	sg = st->sgl;
	st->nents = 0;
	for (i = 0; i < page_count; i++) {
        page = shmem_read_mapping_page_gfp(obj->base.filp, i, gfp);
		if (IS_ERR(page)) {
            dbgprintf("%s invalid page %p\n", __FUNCTION__, page);
			goto err_pages;
 
		}
#ifdef CONFIG_SWIOTLB
		if (swiotlb_nr_tbl()) {
			st->nents++;
			sg_set_page(sg, page, PAGE_SIZE, 0);
			sg = sg_next(sg);
			continue;
		}
#endif
		if (!i || page_to_pfn(page) != last_pfn + 1) {
			if (i)
				sg = sg_next(sg);
			st->nents++;
		sg_set_page(sg, page, PAGE_SIZE, 0);
		} else {
			sg->length += PAGE_SIZE;
		}
		last_pfn = page_to_pfn(page);
	}
#ifdef CONFIG_SWIOTLB
	if (!swiotlb_nr_tbl())
#endif
		sg_mark_end(sg);
	obj->pages = st;
 
	return 0;
 
err_pages:
	sg_mark_end(sg);
	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
		page_cache_release(sg_page_iter_page(&sg_iter));
	sg_free_table(st);
	kfree(st);
    FAIL();
	return PTR_ERR(page);
}
 
/* Ensure that the associated pages are gathered from the backing storage
 * and pinned into our object. i915_gem_object_get_pages() may be called
 * multiple times before they are released by a single call to
 * i915_gem_object_put_pages() - once the pages are no longer referenced
 * either as a result of memory pressure (reaping pages under the shrinker)
 * or as the object is itself released.
 */
int
i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	const struct drm_i915_gem_object_ops *ops = obj->ops;
	int ret;
 
	if (obj->pages)
		return 0;
 
	if (obj->madv != I915_MADV_WILLNEED) {
		DRM_DEBUG("Attempting to obtain a purgeable object\n");
		return -EFAULT;
	}
 
	BUG_ON(obj->pages_pin_count);
 
	ret = ops->get_pages(obj);
	if (ret)
		return ret;
 
	list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
    return 0;
}
 
static void
i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
			       struct intel_engine_cs *ring)
{
 
 
	u32 seqno = intel_ring_get_seqno(ring);
 
	BUG_ON(ring == NULL);
	if (obj->ring != ring && obj->last_write_seqno) {
		/* Keep the seqno relative to the current ring */
		obj->last_write_seqno = seqno;
	}
	obj->ring = ring;
 
	/* Add a reference if we're newly entering the active list. */
	if (!obj->active) {
		drm_gem_object_reference(&obj->base);
		obj->active = 1;
	}
 
	list_move_tail(&obj->ring_list, &ring->active_list);
 
	obj->last_read_seqno = seqno;
 
 
 
 
 
 
 
 
 
 
 
 
 
}
 
void i915_vma_move_to_active(struct i915_vma *vma,
			     struct intel_engine_cs *ring)
{
	list_move_tail(&vma->mm_list, &vma->vm->active_list);
	return i915_gem_object_move_to_active(vma->obj, ring);
}
 
static void
i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	struct i915_address_space *vm;
	struct i915_vma *vma;
 
	BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
	BUG_ON(!obj->active);
 
	list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
		vma = i915_gem_obj_to_vma(obj, vm);
		if (vma && !list_empty(&vma->mm_list))
			list_move_tail(&vma->mm_list, &vm->inactive_list);
	}
 
	intel_fb_obj_flush(obj, true);
 
	list_del_init(&obj->ring_list);
	obj->ring = NULL;
 
	obj->last_read_seqno = 0;
	obj->last_write_seqno = 0;
	obj->base.write_domain = 0;
 
	obj->last_fenced_seqno = 0;
 
 
	obj->active = 0;
	drm_gem_object_unreference(&obj->base);
 
	WARN_ON(i915_verify_lists(dev));
}
 
static void
i915_gem_object_retire(struct drm_i915_gem_object *obj)
{
	struct intel_engine_cs *ring = obj->ring;
 
	if (ring == NULL)
		return;
 
	if (i915_seqno_passed(ring->get_seqno(ring, true),
			      obj->last_read_seqno))
		i915_gem_object_move_to_inactive(obj);
}
 
static int
i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring;
	int ret, i, j;
 
	/* Carefully retire all requests without writing to the rings */
	for_each_ring(ring, dev_priv, i) {
		ret = intel_ring_idle(ring);
	if (ret)
		return ret;
	}
	i915_gem_retire_requests(dev);
 
	/* Finally reset hw state */
	for_each_ring(ring, dev_priv, i) {
		intel_ring_init_seqno(ring, seqno);
 
		for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
			ring->semaphore.sync_seqno[j] = 0;
	}
 
	return 0;
}
 
int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
 
	if (seqno == 0)
		return -EINVAL;
 
	/* HWS page needs to be set less than what we
	 * will inject to ring
	 */
	ret = i915_gem_init_seqno(dev, seqno - 1);
	if (ret)
		return ret;
 
	/* Carefully set the last_seqno value so that wrap
	 * detection still works
	 */
	dev_priv->next_seqno = seqno;
	dev_priv->last_seqno = seqno - 1;
	if (dev_priv->last_seqno == 0)
		dev_priv->last_seqno--;
 
	return 0;
}
 
int
i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	/* reserve 0 for non-seqno */
	if (dev_priv->next_seqno == 0) {
		int ret = i915_gem_init_seqno(dev, 0);
		if (ret)
			return ret;
 
		dev_priv->next_seqno = 1;
	}
 
	*seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
	return 0;
}
 
int __i915_add_request(struct intel_engine_cs *ring,
		 struct drm_file *file,
		       struct drm_i915_gem_object *obj,
		 u32 *out_seqno)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	struct drm_i915_gem_request *request;
	struct intel_ringbuffer *ringbuf;
	u32 request_ring_position, request_start;
	int ret;
 
	request = ring->preallocated_lazy_request;
	if (WARN_ON(request == NULL))
		return -ENOMEM;
 
	if (i915.enable_execlists) {
		struct intel_context *ctx = request->ctx;
		ringbuf = ctx->engine[ring->id].ringbuf;
	} else
		ringbuf = ring->buffer;
 
	request_start = intel_ring_get_tail(ringbuf);
	/*
	 * Emit any outstanding flushes - execbuf can fail to emit the flush
	 * after having emitted the batchbuffer command. Hence we need to fix
	 * things up similar to emitting the lazy request. The difference here
	 * is that the flush _must_ happen before the next request, no matter
	 * what.
	 */
	if (i915.enable_execlists) {
		ret = logical_ring_flush_all_caches(ringbuf);
		if (ret)
			return ret;
	} else {
   ret = intel_ring_flush_all_caches(ring);
   if (ret)
       return ret;
	}
 
 
 
 
	/* Record the position of the start of the request so that
	 * should we detect the updated seqno part-way through the
    * GPU processing the request, we never over-estimate the
	 * position of the head.
	 */
	request_ring_position = intel_ring_get_tail(ringbuf);
 
	if (i915.enable_execlists) {
		ret = ring->emit_request(ringbuf);
		if (ret)
			return ret;
	} else {
	ret = ring->add_request(ring);
	if (ret)
		return ret;
	}
 
	request->seqno = intel_ring_get_seqno(ring);
	request->ring = ring;
	request->head = request_start;
	request->tail = request_ring_position;
 
	/* Whilst this request exists, batch_obj will be on the
	 * active_list, and so will hold the active reference. Only when this
	 * request is retired will the the batch_obj be moved onto the
	 * inactive_list and lose its active reference. Hence we do not need
	 * to explicitly hold another reference here.
	 */
	request->batch_obj = obj;
 
	if (!i915.enable_execlists) {
	/* Hold a reference to the current context so that we can inspect
	 * it later in case a hangcheck error event fires.
	 */
	request->ctx = ring->last_context;
	if (request->ctx)
		i915_gem_context_reference(request->ctx);
	}
 
	request->emitted_jiffies = jiffies;
	list_add_tail(&request->list, &ring->request_list);
	request->file_priv = NULL;
 
	if (file) {
		struct drm_i915_file_private *file_priv = file->driver_priv;
 
		spin_lock(&file_priv->mm.lock);
		request->file_priv = file_priv;
		list_add_tail(&request->client_list,
			      &file_priv->mm.request_list);
		spin_unlock(&file_priv->mm.lock);
	}
 
	trace_i915_gem_request_add(ring, request->seqno);
	ring->outstanding_lazy_seqno = 0;
	ring->preallocated_lazy_request = NULL;
 
 
//		i915_queue_hangcheck(ring->dev);
 
           queue_delayed_work(dev_priv->wq,
					   &dev_priv->mm.retire_work,
					   round_jiffies_up_relative(HZ));
           intel_mark_busy(dev_priv->dev);
 
 
	if (out_seqno)
		*out_seqno = request->seqno;
	return 0;
}
 
static inline void
i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
{
	struct drm_i915_file_private *file_priv = request->file_priv;
 
	if (!file_priv)
		return;
 
	spin_lock(&file_priv->mm.lock);
		list_del(&request->client_list);
		request->file_priv = NULL;
	spin_unlock(&file_priv->mm.lock);
}
 
static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
				   const struct intel_context *ctx)
{
	unsigned long elapsed;
 
    elapsed = GetTimerTicks()/100 - ctx->hang_stats.guilty_ts;
 
	if (ctx->hang_stats.banned)
		return true;
 
	if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
		if (!i915_gem_context_is_default(ctx)) {
			DRM_DEBUG("context hanging too fast, banning!\n");
			return true;
		} else if (i915_stop_ring_allow_ban(dev_priv)) {
			if (i915_stop_ring_allow_warn(dev_priv))
			DRM_ERROR("gpu hanging too fast, banning!\n");
			return true;
	}
	}
 
	return false;
}
 
static void i915_set_reset_status(struct drm_i915_private *dev_priv,
				  struct intel_context *ctx,
				  const bool guilty)
{
	struct i915_ctx_hang_stats *hs;
 
	if (WARN_ON(!ctx))
		return;
 
	hs = &ctx->hang_stats;
 
	if (guilty) {
		hs->banned = i915_context_is_banned(dev_priv, ctx);
		hs->batch_active++;
        hs->guilty_ts = GetTimerTicks()/100;
	} else {
		hs->batch_pending++;
	}
}
 
static void i915_gem_free_request(struct drm_i915_gem_request *request)
{
	struct intel_context *ctx = request->ctx;
 
	list_del(&request->list);
	i915_gem_request_remove_from_client(request);
 
	if (ctx) {
		if (i915.enable_execlists) {
			struct intel_engine_cs *ring = request->ring;
 
			if (ctx != ring->default_context)
				intel_lr_context_unpin(ring, ctx);
		}
		i915_gem_context_unreference(ctx);
	}
	kfree(request);
}
 
struct drm_i915_gem_request *
i915_gem_find_active_request(struct intel_engine_cs *ring)
{
	struct drm_i915_gem_request *request;
	u32 completed_seqno;
 
	completed_seqno = ring->get_seqno(ring, false);
 
	list_for_each_entry(request, &ring->request_list, list) {
		if (i915_seqno_passed(completed_seqno, request->seqno))
			continue;
 
		return request;
	}
 
	return NULL;
}
 
static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
				       struct intel_engine_cs *ring)
{
	struct drm_i915_gem_request *request;
	bool ring_hung;
 
	request = i915_gem_find_active_request(ring);
 
	if (request == NULL)
		return;
 
	ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
 
	i915_set_reset_status(dev_priv, request->ctx, ring_hung);
 
	list_for_each_entry_continue(request, &ring->request_list, list)
		i915_set_reset_status(dev_priv, request->ctx, false);
}
 
static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
					struct intel_engine_cs *ring)
{
	while (!list_empty(&ring->active_list)) {
		struct drm_i915_gem_object *obj;
 
		obj = list_first_entry(&ring->active_list,
				       struct drm_i915_gem_object,
				       ring_list);
 
		i915_gem_object_move_to_inactive(obj);
	}
 
	/*
	 * Clear the execlists queue up before freeing the requests, as those
	 * are the ones that keep the context and ringbuffer backing objects
	 * pinned in place.
	 */
	while (!list_empty(&ring->execlist_queue)) {
		struct intel_ctx_submit_request *submit_req;
 
		submit_req = list_first_entry(&ring->execlist_queue,
				struct intel_ctx_submit_request,
				execlist_link);
		list_del(&submit_req->execlist_link);
		intel_runtime_pm_put(dev_priv);
		i915_gem_context_unreference(submit_req->ctx);
		kfree(submit_req);
	}
 
	/*
	 * We must free the requests after all the corresponding objects have
	 * been moved off active lists. Which is the same order as the normal
	 * retire_requests function does. This is important if object hold
	 * implicit references on things like e.g. ppgtt address spaces through
	 * the request.
	 */
	while (!list_empty(&ring->request_list)) {
		struct drm_i915_gem_request *request;
 
		request = list_first_entry(&ring->request_list,
					   struct drm_i915_gem_request,
					   list);
 
		i915_gem_free_request(request);
	}
 
	/* These may not have been flush before the reset, do so now */
	kfree(ring->preallocated_lazy_request);
	ring->preallocated_lazy_request = NULL;
	ring->outstanding_lazy_seqno = 0;
}
 
void i915_gem_restore_fences(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;
 
	for (i = 0; i < dev_priv->num_fence_regs; i++) {
		struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
 
		/*
		 * Commit delayed tiling changes if we have an object still
		 * attached to the fence, otherwise just clear the fence.
		 */
		if (reg->obj) {
			i915_gem_object_update_fence(reg->obj, reg,
						     reg->obj->tiling_mode);
		} else {
			i915_gem_write_fence(dev, i, NULL);
		}
	}
}
 
void i915_gem_reset(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring;
	int i;
 
	/*
	 * Before we free the objects from the requests, we need to inspect
	 * them for finding the guilty party. As the requests only borrow
	 * their reference to the objects, the inspection must be done first.
	 */
	for_each_ring(ring, dev_priv, i)
		i915_gem_reset_ring_status(dev_priv, ring);
 
	for_each_ring(ring, dev_priv, i)
		i915_gem_reset_ring_cleanup(dev_priv, ring);
 
	i915_gem_context_reset(dev);
 
	i915_gem_restore_fences(dev);
}
 
/**
 * This function clears the request list as sequence numbers are passed.
 */
void
i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
{
	uint32_t seqno;
 
	if (list_empty(&ring->request_list))
		return;
 
	WARN_ON(i915_verify_lists(ring->dev));
 
	seqno = ring->get_seqno(ring, true);
 
	/* Move any buffers on the active list that are no longer referenced
	 * by the ringbuffer to the flushing/inactive lists as appropriate,
	 * before we free the context associated with the requests.
	 */
	while (!list_empty(&ring->active_list)) {
		struct drm_i915_gem_object *obj;
 
		obj = list_first_entry(&ring->active_list,
				      struct drm_i915_gem_object,
				      ring_list);
 
		if (!i915_seqno_passed(seqno, obj->last_read_seqno))
			break;
 
		i915_gem_object_move_to_inactive(obj);
	}
 
 
	while (!list_empty(&ring->request_list)) {
		struct drm_i915_gem_request *request;
		struct intel_ringbuffer *ringbuf;
 
		request = list_first_entry(&ring->request_list,
					   struct drm_i915_gem_request,
					   list);
 
		if (!i915_seqno_passed(seqno, request->seqno))
			break;
 
		trace_i915_gem_request_retire(ring, request->seqno);
 
		/* This is one of the few common intersection points
		 * between legacy ringbuffer submission and execlists:
		 * we need to tell them apart in order to find the correct
		 * ringbuffer to which the request belongs to.
		 */
		if (i915.enable_execlists) {
			struct intel_context *ctx = request->ctx;
			ringbuf = ctx->engine[ring->id].ringbuf;
		} else
			ringbuf = ring->buffer;
 
		/* We know the GPU must have read the request to have
		 * sent us the seqno + interrupt, so use the position
		 * of tail of the request to update the last known position
		 * of the GPU head.
		 */
		ringbuf->last_retired_head = request->tail;
 
		i915_gem_free_request(request);
	}
 
	if (unlikely(ring->trace_irq_seqno &&
		     i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
		ring->irq_put(ring);
		ring->trace_irq_seqno = 0;
	}
 
	WARN_ON(i915_verify_lists(ring->dev));
}
 
bool
i915_gem_retire_requests(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring;
	bool idle = true;
	int i;
 
	for_each_ring(ring, dev_priv, i) {
		i915_gem_retire_requests_ring(ring);
		idle &= list_empty(&ring->request_list);
		if (i915.enable_execlists) {
			unsigned long flags;
 
			spin_lock_irqsave(&ring->execlist_lock, flags);
			idle &= list_empty(&ring->execlist_queue);
			spin_unlock_irqrestore(&ring->execlist_lock, flags);
 
			intel_execlists_retire_requests(ring);
		}
	}
 
	if (idle)
		mod_delayed_work(dev_priv->wq,
				   &dev_priv->mm.idle_work,
				   msecs_to_jiffies(100));
 
	return idle;
}
 
static void
i915_gem_retire_work_handler(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), mm.retire_work.work);
	struct drm_device *dev = dev_priv->dev;
	bool idle;
 
	/* Come back later if the device is busy... */
	idle = false;
	if (mutex_trylock(&dev->struct_mutex)) {
		idle = i915_gem_retire_requests(dev);
		mutex_unlock(&dev->struct_mutex);
	}
	if (!idle)
		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
				   round_jiffies_up_relative(HZ));
}
 
static void
i915_gem_idle_work_handler(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), mm.idle_work.work);
 
	intel_mark_idle(dev_priv->dev);
}
 
/**
 * Ensures that an object will eventually get non-busy by flushing any required
 * write domains, emitting any outstanding lazy request and retiring and
 * completed requests.
 */
static int
i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
{
	int ret;
 
	if (obj->active) {
		ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
		if (ret)
			return ret;
 
		i915_gem_retire_requests_ring(obj->ring);
	}
 
	return 0;
}
 
/**
 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
 * @DRM_IOCTL_ARGS: standard ioctl arguments
 *
 * Returns 0 if successful, else an error is returned with the remaining time in
 * the timeout parameter.
 *  -ETIME: object is still busy after timeout
 *  -ERESTARTSYS: signal interrupted the wait
 *  -ENONENT: object doesn't exist
 * Also possible, but rare:
 *  -EAGAIN: GPU wedged
 *  -ENOMEM: damn
 *  -ENODEV: Internal IRQ fail
 *  -E?: The add request failed
 *
 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
 * non-zero timeout parameter the wait ioctl will wait for the given number of
 * nanoseconds on an object becoming unbusy. Since the wait itself does so
 * without holding struct_mutex the object may become re-busied before this
 * function completes. A similar but shorter * race condition exists in the busy
 * ioctl
 */
int
i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_wait *args = data;
	struct drm_i915_gem_object *obj;
	struct intel_engine_cs *ring = NULL;
	unsigned reset_counter;
	u32 seqno = 0;
	int ret = 0;
 
	if (args->flags != 0)
		return -EINVAL;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
	if (&obj->base == NULL) {
		mutex_unlock(&dev->struct_mutex);
		return -ENOENT;
	}
 
	/* Need to make sure the object gets inactive eventually. */
	ret = i915_gem_object_flush_active(obj);
	if (ret)
		goto out;
 
	if (obj->active) {
		seqno = obj->last_read_seqno;
		ring = obj->ring;
	}
 
	if (seqno == 0)
		 goto out;
 
	/* Do this after OLR check to make sure we make forward progress polling
	 * on this IOCTL with a timeout <=0 (like busy ioctl)
	 */
	if (args->timeout_ns <= 0) {
		ret = -ETIME;
		goto out;
	}
 
	drm_gem_object_unreference(&obj->base);
	reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
	mutex_unlock(&dev->struct_mutex);
 
	return __i915_wait_seqno(ring, seqno, reset_counter, true,
				 &args->timeout_ns, file->driver_priv);
 
out:
	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
 
/**
 * i915_gem_object_sync - sync an object to a ring.
 *
 * @obj: object which may be in use on another ring.
 * @to: ring we wish to use the object on. May be NULL.
 *
 * This code is meant to abstract object synchronization with the GPU.
 * Calling with NULL implies synchronizing the object with the CPU
 * rather than a particular GPU ring.
 *
 * Returns 0 if successful, else propagates up the lower layer error.
 */
int
i915_gem_object_sync(struct drm_i915_gem_object *obj,
		     struct intel_engine_cs *to)
{
	struct intel_engine_cs *from = obj->ring;
	u32 seqno;
	int ret, idx;
 
	if (from == NULL || to == from)
		return 0;
 
	if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
		return i915_gem_object_wait_rendering(obj, false);
 
	idx = intel_ring_sync_index(from, to);
 
	seqno = obj->last_read_seqno;
	/* Optimization: Avoid semaphore sync when we are sure we already
	 * waited for an object with higher seqno */
	if (seqno <= from->semaphore.sync_seqno[idx])
		return 0;
 
	ret = i915_gem_check_olr(obj->ring, seqno);
	if (ret)
		return ret;
 
	trace_i915_gem_ring_sync_to(from, to, seqno);
	ret = to->semaphore.sync_to(to, from, seqno);
	if (!ret)
		/* We use last_read_seqno because sync_to()
		 * might have just caused seqno wrap under
		 * the radar.
		 */
		from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
 
	return ret;
}
 
static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
{
	u32 old_write_domain, old_read_domains;
 
	/* Force a pagefault for domain tracking on next user access */
//	i915_gem_release_mmap(obj);
 
	if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
		return;
 
	/* Wait for any direct GTT access to complete */
	mb();
 
	old_read_domains = obj->base.read_domains;
	old_write_domain = obj->base.write_domain;
 
	obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
	obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
 
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);
}
 
int i915_vma_unbind(struct i915_vma *vma)
{
	struct drm_i915_gem_object *obj = vma->obj;
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	int ret;
 
    if(obj == get_fb_obj())
        return 0;
 
	if (list_empty(&vma->vma_link))
		return 0;
 
	if (!drm_mm_node_allocated(&vma->node)) {
		i915_gem_vma_destroy(vma);
		return 0;
	}
 
	if (vma->pin_count)
		return -EBUSY;
 
	BUG_ON(obj->pages == NULL);
 
	ret = i915_gem_object_finish_gpu(obj);
	if (ret)
		return ret;
	/* Continue on if we fail due to EIO, the GPU is hung so we
	 * should be safe and we need to cleanup or else we might
	 * cause memory corruption through use-after-free.
	 */
 
	/* Throw away the active reference before moving to the unbound list */
	i915_gem_object_retire(obj);
 
	if (i915_is_ggtt(vma->vm)) {
	i915_gem_object_finish_gtt(obj);
 
	/* release the fence reg _after_ flushing */
	ret = i915_gem_object_put_fence(obj);
	if (ret)
		return ret;
	}
 
	trace_i915_vma_unbind(vma);
 
	vma->unbind_vma(vma);
 
	list_del_init(&vma->mm_list);
 
	if (i915_is_ggtt(vma->vm))
		obj->map_and_fenceable = false;
 
	drm_mm_remove_node(&vma->node);
	i915_gem_vma_destroy(vma);
 
	/* Since the unbound list is global, only move to that list if
	 * no more VMAs exist. */
	if (list_empty(&obj->vma_list)) {
		i915_gem_gtt_finish_object(obj);
		list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
	}
 
	/* And finally now the object is completely decoupled from this vma,
	 * we can drop its hold on the backing storage and allow it to be
	 * reaped by the shrinker.
	 */
	i915_gem_object_unpin_pages(obj);
 
	return 0;
}
 
int i915_gpu_idle(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring;
	int ret, i;
 
	/* Flush everything onto the inactive list. */
	for_each_ring(ring, dev_priv, i) {
		if (!i915.enable_execlists) {
		ret = i915_switch_context(ring, ring->default_context);
		if (ret)
			return ret;
		}
 
		ret = intel_ring_idle(ring);
		if (ret)
			return ret;
	}
 
	return 0;
}
 
static void i965_write_fence_reg(struct drm_device *dev, int reg,
					struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int fence_reg;
	int fence_pitch_shift;
 
	if (INTEL_INFO(dev)->gen >= 6) {
		fence_reg = FENCE_REG_SANDYBRIDGE_0;
		fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
	} else {
		fence_reg = FENCE_REG_965_0;
		fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
	}
 
	fence_reg += reg * 8;
 
	/* To w/a incoherency with non-atomic 64-bit register updates,
	 * we split the 64-bit update into two 32-bit writes. In order
	 * for a partial fence not to be evaluated between writes, we
	 * precede the update with write to turn off the fence register,
	 * and only enable the fence as the last step.
	 *
	 * For extra levels of paranoia, we make sure each step lands
	 * before applying the next step.
	 */
	I915_WRITE(fence_reg, 0);
	POSTING_READ(fence_reg);
 
	if (obj) {
		u32 size = i915_gem_obj_ggtt_size(obj);
		uint64_t val;
 
		val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
				 0xfffff000) << 32;
		val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
		val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
		val |= I965_FENCE_REG_VALID;
 
		I915_WRITE(fence_reg + 4, val >> 32);
		POSTING_READ(fence_reg + 4);
 
		I915_WRITE(fence_reg + 0, val);
		POSTING_READ(fence_reg);
	} else {
		I915_WRITE(fence_reg + 4, 0);
		POSTING_READ(fence_reg + 4);
	}
}
 
static void i915_write_fence_reg(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val;
 
	if (obj) {
		u32 size = i915_gem_obj_ggtt_size(obj);
		int pitch_val;
		int tile_width;
 
		WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
		     (size & -size) != size ||
		     (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
		     "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
		     i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
 
		if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
			tile_width = 128;
		else
			tile_width = 512;
 
		/* Note: pitch better be a power of two tile widths */
		pitch_val = obj->stride / tile_width;
		pitch_val = ffs(pitch_val) - 1;
 
		val = i915_gem_obj_ggtt_offset(obj);
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I830_FENCE_TILING_Y_SHIFT;
		val |= I915_FENCE_SIZE_BITS(size);
		val |= pitch_val << I830_FENCE_PITCH_SHIFT;
		val |= I830_FENCE_REG_VALID;
	} else
		val = 0;
 
	if (reg < 8)
		reg = FENCE_REG_830_0 + reg * 4;
	else
		reg = FENCE_REG_945_8 + (reg - 8) * 4;
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
}
 
static void i830_write_fence_reg(struct drm_device *dev, int reg,
				struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t val;
 
	if (obj) {
		u32 size = i915_gem_obj_ggtt_size(obj);
		uint32_t pitch_val;
 
		WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
		     (size & -size) != size ||
		     (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
		     "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
		     i915_gem_obj_ggtt_offset(obj), size);
 
		pitch_val = obj->stride / 128;
		pitch_val = ffs(pitch_val) - 1;
 
		val = i915_gem_obj_ggtt_offset(obj);
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I830_FENCE_TILING_Y_SHIFT;
		val |= I830_FENCE_SIZE_BITS(size);
		val |= pitch_val << I830_FENCE_PITCH_SHIFT;
		val |= I830_FENCE_REG_VALID;
	} else
		val = 0;
 
	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
	POSTING_READ(FENCE_REG_830_0 + reg * 4);
}
 
inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
{
	return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
}
 
static void i915_gem_write_fence(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	/* Ensure that all CPU reads are completed before installing a fence
	 * and all writes before removing the fence.
	 */
	if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
		mb();
 
	WARN(obj && (!obj->stride || !obj->tiling_mode),
	     "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
	     obj->stride, obj->tiling_mode);
 
	switch (INTEL_INFO(dev)->gen) {
	case 9:
	case 8:
	case 7:
	case 6:
	case 5:
	case 4: i965_write_fence_reg(dev, reg, obj); break;
	case 3: i915_write_fence_reg(dev, reg, obj); break;
	case 2: i830_write_fence_reg(dev, reg, obj); break;
	default: BUG();
	}
 
	/* And similarly be paranoid that no direct access to this region
	 * is reordered to before the fence is installed.
	 */
	if (i915_gem_object_needs_mb(obj))
		mb();
}
 
static inline int fence_number(struct drm_i915_private *dev_priv,
			       struct drm_i915_fence_reg *fence)
{
	return fence - dev_priv->fence_regs;
}
 
static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
					 struct drm_i915_fence_reg *fence,
					 bool enable)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	int reg = fence_number(dev_priv, fence);
 
	i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
 
	if (enable) {
		obj->fence_reg = reg;
		fence->obj = obj;
		list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
	} else {
		obj->fence_reg = I915_FENCE_REG_NONE;
		fence->obj = NULL;
		list_del_init(&fence->lru_list);
	}
	obj->fence_dirty = false;
}
 
static int
i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
{
	if (obj->last_fenced_seqno) {
		int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
			if (ret)
				return ret;
 
		obj->last_fenced_seqno = 0;
	}
 
 
	return 0;
}
 
int
i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	struct drm_i915_fence_reg *fence;
	int ret;
 
	ret = i915_gem_object_wait_fence(obj);
    if (ret)
       return ret;
 
	if (obj->fence_reg == I915_FENCE_REG_NONE)
		return 0;
 
	fence = &dev_priv->fence_regs[obj->fence_reg];
 
	if (WARN_ON(fence->pin_count))
		return -EBUSY;
 
	i915_gem_object_fence_lost(obj);
	i915_gem_object_update_fence(obj, fence, false);
 
	return 0;
}
 
static struct drm_i915_fence_reg *
i915_find_fence_reg(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_fence_reg *reg, *avail;
	int i;
 
	/* First try to find a free reg */
	avail = NULL;
	for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
		reg = &dev_priv->fence_regs[i];
		if (!reg->obj)
			return reg;
 
		if (!reg->pin_count)
			avail = reg;
	}
 
	if (avail == NULL)
		goto deadlock;
 
	/* None available, try to steal one or wait for a user to finish */
	list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
		if (reg->pin_count)
			continue;
 
		return reg;
	}
 
deadlock:
	/* Wait for completion of pending flips which consume fences */
//   if (intel_has_pending_fb_unpin(dev))
//       return ERR_PTR(-EAGAIN);
 
	return ERR_PTR(-EDEADLK);
}
 
/**
 * i915_gem_object_get_fence - set up fencing for an object
 * @obj: object to map through a fence reg
 *
 * When mapping objects through the GTT, userspace wants to be able to write
 * to them without having to worry about swizzling if the object is tiled.
 * This function walks the fence regs looking for a free one for @obj,
 * stealing one if it can't find any.
 *
 * It then sets up the reg based on the object's properties: address, pitch
 * and tiling format.
 *
 * For an untiled surface, this removes any existing fence.
 */
int
i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool enable = obj->tiling_mode != I915_TILING_NONE;
	struct drm_i915_fence_reg *reg;
	int ret;
 
	/* Have we updated the tiling parameters upon the object and so
	 * will need to serialise the write to the associated fence register?
	 */
	if (obj->fence_dirty) {
		ret = i915_gem_object_wait_fence(obj);
		if (ret)
			return ret;
	}
 
	/* Just update our place in the LRU if our fence is getting reused. */
	if (obj->fence_reg != I915_FENCE_REG_NONE) {
		reg = &dev_priv->fence_regs[obj->fence_reg];
		if (!obj->fence_dirty) {
			list_move_tail(®->lru_list,
				       &dev_priv->mm.fence_list);
			return 0;
		}
	} else if (enable) {
		if (WARN_ON(!obj->map_and_fenceable))
			return -EINVAL;
 
		reg = i915_find_fence_reg(dev);
		if (IS_ERR(reg))
			return PTR_ERR(reg);
 
		if (reg->obj) {
			struct drm_i915_gem_object *old = reg->obj;
 
			ret = i915_gem_object_wait_fence(old);
			if (ret)
				return ret;
 
			i915_gem_object_fence_lost(old);
		}
	} else
		return 0;
 
	i915_gem_object_update_fence(obj, reg, enable);
 
	return 0;
}
 
 
static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
				     unsigned long cache_level)
{
	struct drm_mm_node *gtt_space = &vma->node;
	struct drm_mm_node *other;
 
	/*
	 * On some machines we have to be careful when putting differing types
	 * of snoopable memory together to avoid the prefetcher crossing memory
	 * domains and dying. During vm initialisation, we decide whether or not
	 * these constraints apply and set the drm_mm.color_adjust
	 * appropriately.
	 */
	if (vma->vm->mm.color_adjust == NULL)
		return true;
 
	if (!drm_mm_node_allocated(gtt_space))
		return true;
 
	if (list_empty(>t_space->node_list))
		return true;
 
	other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
	if (other->allocated && !other->hole_follows && other->color != cache_level)
		return false;
 
	other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
	if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
		return false;
 
	return true;
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/**
 * Finds free space in the GTT aperture and binds the object there.
 */
static struct i915_vma *
i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
			   struct i915_address_space *vm,
			    unsigned alignment,
			   uint64_t flags)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 size, fence_size, fence_alignment, unfenced_alignment;
	unsigned long start =
		flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
	unsigned long end =
		flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
	struct i915_vma *vma;
	int ret;
 
	fence_size = i915_gem_get_gtt_size(dev,
					   obj->base.size,
					   obj->tiling_mode);
	fence_alignment = i915_gem_get_gtt_alignment(dev,
						     obj->base.size,
						     obj->tiling_mode, true);
	unfenced_alignment =
		i915_gem_get_gtt_alignment(dev,
						    obj->base.size,
						    obj->tiling_mode, false);
 
	if (alignment == 0)
		alignment = flags & PIN_MAPPABLE ? fence_alignment :
						unfenced_alignment;
	if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
		DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
		return ERR_PTR(-EINVAL);
	}
 
	size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
 
	/* If the object is bigger than the entire aperture, reject it early
	 * before evicting everything in a vain attempt to find space.
	 */
	if (obj->base.size > end) {
		DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
			  obj->base.size,
			  flags & PIN_MAPPABLE ? "mappable" : "total",
			  end);
		return ERR_PTR(-E2BIG);
	}
 
	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ERR_PTR(ret);
 
	i915_gem_object_pin_pages(obj);
 
	vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
	if (IS_ERR(vma))
		goto err_unpin;
 
search_free:
	ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
						  size, alignment,
						  obj->cache_level,
						  start, end,
						  DRM_MM_SEARCH_DEFAULT,
						  DRM_MM_CREATE_DEFAULT);
	if (ret) {
 
		goto err_free_vma;
	}
	if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
 
		ret = -EINVAL;
		goto err_remove_node;
	}
 
	ret = i915_gem_gtt_prepare_object(obj);
	if (ret)
		goto err_remove_node;
 
	list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
	list_add_tail(&vma->mm_list, &vm->inactive_list);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
	trace_i915_vma_bind(vma, flags);
	vma->bind_vma(vma, obj->cache_level,
 
		      flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
 
	return vma;
 
err_remove_node:
	drm_mm_remove_node(&vma->node);
err_free_vma:
	i915_gem_vma_destroy(vma);
	vma = ERR_PTR(ret);
err_unpin:
	i915_gem_object_unpin_pages(obj);
	return vma;
}
 
bool
i915_gem_clflush_object(struct drm_i915_gem_object *obj,
			bool force)
{
	/* If we don't have a page list set up, then we're not pinned
	 * to GPU, and we can ignore the cache flush because it'll happen
	 * again at bind time.
	 */
	if (obj->pages == NULL)
		return false;
 
	/*
	 * Stolen memory is always coherent with the GPU as it is explicitly
	 * marked as wc by the system, or the system is cache-coherent.
	 */
	if (obj->stolen || obj->phys_handle)
		return false;
 
	/* If the GPU is snooping the contents of the CPU cache,
	 * we do not need to manually clear the CPU cache lines.  However,
	 * the caches are only snooped when the render cache is
	 * flushed/invalidated.  As we always have to emit invalidations
	 * and flushes when moving into and out of the RENDER domain, correct
	 * snooping behaviour occurs naturally as the result of our domain
	 * tracking.
	 */
	if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
		return false;
 
	trace_i915_gem_object_clflush(obj);
	drm_clflush_sg(obj->pages);
 
	return true;
}
 
/** Flushes the GTT write domain for the object if it's dirty. */
static void
i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
{
	uint32_t old_write_domain;
 
	if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
		return;
 
	/* No actual flushing is required for the GTT write domain.  Writes
	 * to it immediately go to main memory as far as we know, so there's
	 * no chipset flush.  It also doesn't land in render cache.
	 *
	 * However, we do have to enforce the order so that all writes through
	 * the GTT land before any writes to the device, such as updates to
	 * the GATT itself.
	 */
	wmb();
 
	old_write_domain = obj->base.write_domain;
	obj->base.write_domain = 0;
 
	intel_fb_obj_flush(obj, false);
 
	trace_i915_gem_object_change_domain(obj,
					    obj->base.read_domains,
					    old_write_domain);
}
 
/** Flushes the CPU write domain for the object if it's dirty. */
static void
i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
				       bool force)
{
	uint32_t old_write_domain;
 
	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
		return;
 
	if (i915_gem_clflush_object(obj, force))
	i915_gem_chipset_flush(obj->base.dev);
 
	old_write_domain = obj->base.write_domain;
	obj->base.write_domain = 0;
 
	intel_fb_obj_flush(obj, false);
 
	trace_i915_gem_object_change_domain(obj,
					    obj->base.read_domains,
					    old_write_domain);
}
 
/**
 * Moves a single object to the GTT read, and possibly write domain.
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
int
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
	uint32_t old_write_domain, old_read_domains;
	int ret;
 
	/* Not valid to be called on unbound objects. */
	if (vma == NULL)
		return -EINVAL;
 
	if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
		return 0;
 
	ret = i915_gem_object_wait_rendering(obj, !write);
		if (ret)
			return ret;
 
	i915_gem_object_retire(obj);
	i915_gem_object_flush_cpu_write_domain(obj, false);
 
	/* Serialise direct access to this object with the barriers for
	 * coherent writes from the GPU, by effectively invalidating the
	 * GTT domain upon first access.
	 */
	if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
		mb();
 
	old_write_domain = obj->base.write_domain;
	old_read_domains = obj->base.read_domains;
 
	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
	BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
	if (write) {
		obj->base.read_domains = I915_GEM_DOMAIN_GTT;
		obj->base.write_domain = I915_GEM_DOMAIN_GTT;
		obj->dirty = 1;
	}
 
	if (write)
		intel_fb_obj_invalidate(obj, NULL);
 
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);
 
	/* And bump the LRU for this access */
	if (i915_gem_object_is_inactive(obj))
 
 
			list_move_tail(&vma->mm_list,
				       &dev_priv->gtt.base.inactive_list);
 
 
 
	return 0;
}
 
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level)
{
	struct drm_device *dev = obj->base.dev;
	struct i915_vma *vma, *next;
	int ret;
 
	if (obj->cache_level == cache_level)
		return 0;
 
	if (i915_gem_obj_is_pinned(obj)) {
		DRM_DEBUG("can not change the cache level of pinned objects\n");
		return -EBUSY;
	}
 
	list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
		if (!i915_gem_valid_gtt_space(vma, cache_level)) {
			ret = i915_vma_unbind(vma);
		if (ret)
			return ret;
		}
	}
 
	if (i915_gem_obj_bound_any(obj)) {
		ret = i915_gem_object_finish_gpu(obj);
		if (ret)
			return ret;
 
		i915_gem_object_finish_gtt(obj);
 
		/* Before SandyBridge, you could not use tiling or fence
		 * registers with snooped memory, so relinquish any fences
		 * currently pointing to our region in the aperture.
		 */
		if (INTEL_INFO(dev)->gen < 6) {
			ret = i915_gem_object_put_fence(obj);
			if (ret)
				return ret;
            }
 
		list_for_each_entry(vma, &obj->vma_list, vma_link)
			if (drm_mm_node_allocated(&vma->node))
				vma->bind_vma(vma, cache_level,
						vma->bound & GLOBAL_BIND);
	}
 
	list_for_each_entry(vma, &obj->vma_list, vma_link)
		vma->node.color = cache_level;
	obj->cache_level = cache_level;
 
	if (cpu_write_needs_clflush(obj)) {
		u32 old_read_domains, old_write_domain;
 
		/* If we're coming from LLC cached, then we haven't
		 * actually been tracking whether the data is in the
		 * CPU cache or not, since we only allow one bit set
		 * in obj->write_domain and have been skipping the clflushes.
		 * Just set it to the CPU cache for now.
		 */
		i915_gem_object_retire(obj);
		WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
 
		old_read_domains = obj->base.read_domains;
		old_write_domain = obj->base.write_domain;
 
		obj->base.read_domains = I915_GEM_DOMAIN_CPU;
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 
		trace_i915_gem_object_change_domain(obj,
						    old_read_domains,
						    old_write_domain);
    }
 
 
	return 0;
}
 
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file)
{
	struct drm_i915_gem_caching *args = data;
	struct drm_i915_gem_object *obj;
	int ret;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}
 
	switch (obj->cache_level) {
	case I915_CACHE_LLC:
	case I915_CACHE_L3_LLC:
		args->caching = I915_CACHING_CACHED;
		break;
 
	case I915_CACHE_WT:
		args->caching = I915_CACHING_DISPLAY;
		break;
 
	default:
		args->caching = I915_CACHING_NONE;
		break;
	}
 
	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
 
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file)
{
	struct drm_i915_gem_caching *args = data;
	struct drm_i915_gem_object *obj;
	enum i915_cache_level level;
	int ret;
 
	switch (args->caching) {
	case I915_CACHING_NONE:
		level = I915_CACHE_NONE;
		break;
	case I915_CACHING_CACHED:
		level = I915_CACHE_LLC;
		break;
	case I915_CACHING_DISPLAY:
		level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
		break;
	default:
		return -EINVAL;
	}
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}
 
	ret = i915_gem_object_set_cache_level(obj, level);
 
	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
 
static bool is_pin_display(struct drm_i915_gem_object *obj)
{
	struct i915_vma *vma;
 
 
 
 
	vma = i915_gem_obj_to_ggtt(obj);
	if (!vma)
		return false;
 
	/* There are 3 sources that pin objects:
	 *   1. The display engine (scanouts, sprites, cursors);
	 *   2. Reservations for execbuffer;
	 *   3. The user.
	 *
	 * We can ignore reservations as we hold the struct_mutex and
	 * are only called outside of the reservation path.  The user
	 * can only increment pin_count once, and so if after
	 * subtracting the potential reference by the user, any pin_count
	 * remains, it must be due to another use by the display engine.
	 */
	return vma->pin_count - !!obj->user_pin_count;
}
 
/*
 * Prepare buffer for display plane (scanout, cursors, etc).
 * Can be called from an uninterruptible phase (modesetting) and allows
 * any flushes to be pipelined (for pageflips).
 */
int
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
				     struct intel_engine_cs *pipelined)
{
	u32 old_read_domains, old_write_domain;
	bool was_pin_display;
	int ret;
 
	if (pipelined != obj->ring) {
		ret = i915_gem_object_sync(obj, pipelined);
	if (ret)
		return ret;
	}
 
	/* Mark the pin_display early so that we account for the
	 * display coherency whilst setting up the cache domains.
	 */
	was_pin_display = obj->pin_display;
	obj->pin_display = true;
 
	/* The display engine is not coherent with the LLC cache on gen6.  As
	 * a result, we make sure that the pinning that is about to occur is
	 * done with uncached PTEs. This is lowest common denominator for all
	 * chipsets.
	 *
	 * However for gen6+, we could do better by using the GFDT bit instead
	 * of uncaching, which would allow us to flush all the LLC-cached data
	 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
	 */
	ret = i915_gem_object_set_cache_level(obj,
					      HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
	if (ret)
		goto err_unpin_display;
 
	/* As the user may map the buffer once pinned in the display plane
	 * (e.g. libkms for the bootup splash), we have to ensure that we
	 * always use map_and_fenceable for all scanout buffers.
	 */
	ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
	if (ret)
		goto err_unpin_display;
 
	i915_gem_object_flush_cpu_write_domain(obj, true);
 
	old_write_domain = obj->base.write_domain;
	old_read_domains = obj->base.read_domains;
 
	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
	obj->base.write_domain = 0;
	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
 
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);
 
	return 0;
 
err_unpin_display:
	WARN_ON(was_pin_display != is_pin_display(obj));
	obj->pin_display = was_pin_display;
	return ret;
}
 
void
i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
{
	i915_gem_object_ggtt_unpin(obj);
	obj->pin_display = is_pin_display(obj);
}
 
int
i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
{
	int ret;
 
	if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
		return 0;
 
	ret = i915_gem_object_wait_rendering(obj, false);
    if (ret)
        return ret;
 
	/* Ensure that we invalidate the GPU's caches and TLBs. */
	obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
	return 0;
}
 
/**
 * Moves a single object to the CPU read, and possibly write domain.
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
int
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
{
	uint32_t old_write_domain, old_read_domains;
	int ret;
 
	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
		return 0;
 
	ret = i915_gem_object_wait_rendering(obj, !write);
	if (ret)
		return ret;
 
	i915_gem_object_retire(obj);
	i915_gem_object_flush_gtt_write_domain(obj);
 
	old_write_domain = obj->base.write_domain;
	old_read_domains = obj->base.read_domains;
 
	/* Flush the CPU cache if it's still invalid. */
	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
		i915_gem_clflush_object(obj, false);
 
		obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
	}
 
	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
	BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
 
	/* If we're writing through the CPU, then the GPU read domains will
	 * need to be invalidated at next use.
	 */
	if (write) {
		obj->base.read_domains = I915_GEM_DOMAIN_CPU;
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	}
 
	if (write)
		intel_fb_obj_invalidate(obj, NULL);
 
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);
 
	return 0;
}
 
/* Throttle our rendering by waiting until the ring has completed our requests
 * emitted over 20 msec ago.
 *
 * Note that if we were to use the current jiffies each time around the loop,
 * we wouldn't escape the function with any frames outstanding if the time to
 * render a frame was over 20ms.
 *
 * This should get us reasonable parallelism between CPU and GPU but also
 * relatively low latency when blocking on a particular request to finish.
 */
static int
i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_file_private *file_priv = file->driver_priv;
	unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
	struct drm_i915_gem_request *request;
	struct intel_engine_cs *ring = NULL;
	unsigned reset_counter;
	u32 seqno = 0;
	int ret;
 
	ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
	if (ret)
		return ret;
 
	ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
	if (ret)
		return ret;
 
	spin_lock(&file_priv->mm.lock);
	list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
		if (time_after_eq(request->emitted_jiffies, recent_enough))
			break;
 
		ring = request->ring;
		seqno = request->seqno;
	}
	reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
	spin_unlock(&file_priv->mm.lock);
 
	if (seqno == 0)
		return 0;
 
	ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
	if (ret == 0)
		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
 
	return ret;
}
 
static bool
i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
{
	struct drm_i915_gem_object *obj = vma->obj;
 
	if (alignment &&
	    vma->node.start & (alignment - 1))
		return true;
 
	if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
		return true;
 
	if (flags & PIN_OFFSET_BIAS &&
	    vma->node.start < (flags & PIN_OFFSET_MASK))
		return true;
 
	return false;
}
 
int
i915_gem_object_pin(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm,
		    uint32_t alignment,
		    uint64_t flags)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	struct i915_vma *vma;
	unsigned bound;
	int ret;
 
	if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
		return -ENODEV;
 
	if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
		return -EINVAL;
 
	if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
		return -EINVAL;
 
	vma = i915_gem_obj_to_vma(obj, vm);
	if (vma) {
		if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
			return -EBUSY;
 
		if (i915_vma_misplaced(vma, alignment, flags)) {
			WARN(vma->pin_count,
			     "bo is already pinned with incorrect alignment:"
			     " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
			     " obj->map_and_fenceable=%d\n",
			     i915_gem_obj_offset(obj, vm), alignment,
			     !!(flags & PIN_MAPPABLE),
			     obj->map_and_fenceable);
			ret = i915_vma_unbind(vma);
			if (ret)
				return ret;
 
			vma = NULL;
		}
	}
 
	bound = vma ? vma->bound : 0;
	if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
		vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
		if (IS_ERR(vma))
			return PTR_ERR(vma);
	}
 
	if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND))
		vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
 
	if ((bound ^ vma->bound) & GLOBAL_BIND) {
		bool mappable, fenceable;
		u32 fence_size, fence_alignment;
 
		fence_size = i915_gem_get_gtt_size(obj->base.dev,
						   obj->base.size,
						   obj->tiling_mode);
		fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
							     obj->base.size,
							     obj->tiling_mode,
							     true);
 
		fenceable = (vma->node.size == fence_size &&
			     (vma->node.start & (fence_alignment - 1)) == 0);
 
		mappable = (vma->node.start + obj->base.size <=
			    dev_priv->gtt.mappable_end);
 
		obj->map_and_fenceable = mappable && fenceable;
	}
 
	WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
 
	vma->pin_count++;
	if (flags & PIN_MAPPABLE)
		obj->pin_mappable |= true;
 
	return 0;
}
 
void
i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
{
	struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
 
	BUG_ON(!vma);
	BUG_ON(vma->pin_count == 0);
	BUG_ON(!i915_gem_obj_ggtt_bound(obj));
 
	if (--vma->pin_count == 0)
		obj->pin_mappable = false;
}
 
bool
i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
{
	if (obj->fence_reg != I915_FENCE_REG_NONE) {
		struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
 
		WARN_ON(!ggtt_vma ||
			dev_priv->fence_regs[obj->fence_reg].pin_count >
			ggtt_vma->pin_count);
		dev_priv->fence_regs[obj->fence_reg].pin_count++;
		return true;
	} else
		return false;
}
 
void
i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
{
	if (obj->fence_reg != I915_FENCE_REG_NONE) {
		struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
		dev_priv->fence_regs[obj->fence_reg].pin_count--;
	}
}
 
int
i915_gem_pin_ioctl(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_pin *args = data;
	struct drm_i915_gem_object *obj;
	int ret;
 
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}
 
	if (obj->madv != I915_MADV_WILLNEED) {
		DRM_DEBUG("Attempting to pin a purgeable buffer\n");
		ret = -EFAULT;
		goto out;
	}
 
	if (obj->pin_filp != NULL && obj->pin_filp != file) {
		DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
			  args->handle);
		ret = -EINVAL;
		goto out;
	}
 
	if (obj->user_pin_count == ULONG_MAX) {
		ret = -EBUSY;
		goto out;
	}
 
	if (obj->user_pin_count == 0) {
		ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
		if (ret)
			goto out;
	}
 
	obj->user_pin_count++;
	obj->pin_filp = file;
 
	args->offset = i915_gem_obj_ggtt_offset(obj);
out:
	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
 
int
i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
		     struct drm_file *file)
{
	struct drm_i915_gem_pin *args = data;
	struct drm_i915_gem_object *obj;
	int ret;
 
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}
 
	if (obj->pin_filp != file) {
		DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
			  args->handle);
		ret = -EINVAL;
		goto out;
	}
	obj->user_pin_count--;
	if (obj->user_pin_count == 0) {
		obj->pin_filp = NULL;
		i915_gem_object_ggtt_unpin(obj);
	}
 
out:
	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
 
int
i915_gem_busy_ioctl(struct drm_device *dev, void *data,
		    struct drm_file *file)
{
	struct drm_i915_gem_busy *args = data;
	struct drm_i915_gem_object *obj;
	int ret;
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}
 
	/* Count all active objects as busy, even if they are currently not used
	 * by the gpu. Users of this interface expect objects to eventually
	 * become non-busy without any further actions, therefore emit any
	 * necessary flushes here.
	 */
	ret = i915_gem_object_flush_active(obj);
 
	args->busy = obj->active;
	if (obj->ring) {
		BUILD_BUG_ON(I915_NUM_RINGS > 16);
		args->busy |= intel_ring_flag(obj->ring) << 16;
	}
 
	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
 
int
i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
	return i915_gem_ring_throttle(dev, file_priv);
}
 
#if 0
 
int
i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_madvise *args = data;
	struct drm_i915_gem_object *obj;
	int ret;
 
	switch (args->madv) {
	case I915_MADV_DONTNEED:
	case I915_MADV_WILLNEED:
	    break;
	default:
	    return -EINVAL;
	}
 
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}
 
	if (i915_gem_obj_is_pinned(obj)) {
		ret = -EINVAL;
		goto out;
	}
 
	if (obj->pages &&
	    obj->tiling_mode != I915_TILING_NONE &&
	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
		if (obj->madv == I915_MADV_WILLNEED)
			i915_gem_object_unpin_pages(obj);
		if (args->madv == I915_MADV_WILLNEED)
			i915_gem_object_pin_pages(obj);
	}
 
	if (obj->madv != __I915_MADV_PURGED)
		obj->madv = args->madv;
 
	/* if the object is no longer attached, discard its backing storage */
	if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
		i915_gem_object_truncate(obj);
 
	args->retained = obj->madv != __I915_MADV_PURGED;
 
out:
	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
#endif
 
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			  const struct drm_i915_gem_object_ops *ops)
{
	INIT_LIST_HEAD(&obj->global_list);
	INIT_LIST_HEAD(&obj->ring_list);
	INIT_LIST_HEAD(&obj->obj_exec_link);
	INIT_LIST_HEAD(&obj->vma_list);
 
	obj->ops = ops;
 
	obj->fence_reg = I915_FENCE_REG_NONE;
	obj->madv = I915_MADV_WILLNEED;
 
 
 
	i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
}
 
static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
	.get_pages = i915_gem_object_get_pages_gtt,
	.put_pages = i915_gem_object_put_pages_gtt,
};
 
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size)
{
	struct drm_i915_gem_object *obj;
	struct address_space *mapping;
	gfp_t mask;
 
	obj = i915_gem_object_alloc(dev);
	if (obj == NULL)
		return NULL;
 
	if (drm_gem_object_init(dev, &obj->base, size) != 0) {
		i915_gem_object_free(obj);
		return NULL;
	}
 
 
	i915_gem_object_init(obj, &i915_gem_object_ops);
 
	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
 
	if (HAS_LLC(dev)) {
		/* On some devices, we can have the GPU use the LLC (the CPU
		 * cache) for about a 10% performance improvement
		 * compared to uncached.  Graphics requests other than
		 * display scanout are coherent with the CPU in
		 * accessing this cache.  This means in this mode we
		 * don't need to clflush on the CPU side, and on the
		 * GPU side we only need to flush internal caches to
		 * get data visible to the CPU.
		 *
		 * However, we maintain the display planes as UC, and so
		 * need to rebind when first used as such.
		 */
		obj->cache_level = I915_CACHE_LLC;
	} else
		obj->cache_level = I915_CACHE_NONE;
 
	trace_i915_gem_object_create(obj);
 
	return obj;
}
 
void i915_gem_free_object(struct drm_gem_object *gem_obj)
{
	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_vma *vma, *next;
 
	intel_runtime_pm_get(dev_priv);
 
	trace_i915_gem_object_destroy(obj);
 
	list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
		int ret;
 
		vma->pin_count = 0;
		ret = i915_vma_unbind(vma);
		if (WARN_ON(ret == -ERESTARTSYS)) {
		bool was_interruptible;
 
		was_interruptible = dev_priv->mm.interruptible;
		dev_priv->mm.interruptible = false;
 
			WARN_ON(i915_vma_unbind(vma));
 
		dev_priv->mm.interruptible = was_interruptible;
	}
	}
 
	/* Stolen objects don't hold a ref, but do hold pin count. Fix that up
	 * before progressing. */
	if (obj->stolen)
		i915_gem_object_unpin_pages(obj);
 
	WARN_ON(obj->frontbuffer_bits);
 
	if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
	    obj->tiling_mode != I915_TILING_NONE)
		i915_gem_object_unpin_pages(obj);
 
	if (WARN_ON(obj->pages_pin_count))
	obj->pages_pin_count = 0;
	i915_gem_object_put_pages(obj);
//   i915_gem_object_free_mmap_offset(obj);
 
	BUG_ON(obj->pages);
 
 
    if(obj->base.filp != NULL)
    {
//        printf("filp %p\n", obj->base.filp);
        shmem_file_delete(obj->base.filp);
    }
 
	drm_gem_object_release(&obj->base);
	i915_gem_info_remove_obj(dev_priv, obj->base.size);
 
	kfree(obj->bit_17);
	i915_gem_object_free(obj);
 
	intel_runtime_pm_put(dev_priv);
}
 
struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
				     struct i915_address_space *vm)
{
	struct i915_vma *vma;
	list_for_each_entry(vma, &obj->vma_list, vma_link)
		if (vma->vm == vm)
			return vma;
 
	return NULL;
}
 
void i915_gem_vma_destroy(struct i915_vma *vma)
{
	struct i915_address_space *vm = NULL;
	WARN_ON(vma->node.allocated);
 
	/* Keep the vma as a placeholder in the execbuffer reservation lists */
	if (!list_empty(&vma->exec_list))
		return;
 
	vm = vma->vm;
 
	if (!i915_is_ggtt(vm))
		i915_ppgtt_put(i915_vm_to_ppgtt(vm));
 
	list_del(&vma->vma_link);
 
	kfree(vma);
}
 
#if 0
int
i915_gem_suspend(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret = 0;
 
	mutex_lock(&dev->struct_mutex);
 
 
 
	ret = i915_gpu_idle(dev);
	if (ret)
		goto err;
 
	i915_gem_retire_requests(dev);
 
	/* Under UMS, be paranoid and evict. */
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		i915_gem_evict_everything(dev);
 
 
 
 
 
 
 
 
 
	i915_gem_stop_ringbuffers(dev);
	mutex_unlock(&dev->struct_mutex);
 
	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
	cancel_delayed_work_sync(&dev_priv->mm.retire_work);
	flush_delayed_work(&dev_priv->mm.idle_work);
 
	return 0;
 
err:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}
#endif
 
int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
	u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
	int i, ret;
 
	if (!HAS_L3_DPF(dev) || !remap_info)
		return 0;
 
	ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
	if (ret)
		return ret;
 
	/*
	 * Note: We do not worry about the concurrent register cacheline hang
	 * here because no other code should access these registers other than
	 * at initialization time.
	 */
	for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
		intel_ring_emit(ring, reg_base + i);
		intel_ring_emit(ring, remap_info[i/4]);
	}
 
	intel_ring_advance(ring);
 
	return ret;
}
 
void i915_gem_init_swizzling(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	if (INTEL_INFO(dev)->gen < 5 ||
	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
		return;
 
	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
				 DISP_TILE_SURFACE_SWIZZLING);
 
	if (IS_GEN5(dev))
		return;
 
	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
	if (IS_GEN6(dev))
		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
	else if (IS_GEN7(dev))
		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
	else if (IS_GEN8(dev))
		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
	else
		BUG();
}
 
static bool
intel_enable_blt(struct drm_device *dev)
{
	if (!HAS_BLT(dev))
		return false;
 
	/* The blitter was dysfunctional on early prototypes */
	if (IS_GEN6(dev) && dev->pdev->revision < 8) {
		DRM_INFO("BLT not supported on this pre-production hardware;"
			 " graphics performance will be degraded.\n");
		return false;
	}
 
	return true;
}
 
static void init_unused_ring(struct drm_device *dev, u32 base)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	I915_WRITE(RING_CTL(base), 0);
	I915_WRITE(RING_HEAD(base), 0);
	I915_WRITE(RING_TAIL(base), 0);
	I915_WRITE(RING_START(base), 0);
}
 
static void init_unused_rings(struct drm_device *dev)
{
	if (IS_I830(dev)) {
		init_unused_ring(dev, PRB1_BASE);
		init_unused_ring(dev, SRB0_BASE);
		init_unused_ring(dev, SRB1_BASE);
		init_unused_ring(dev, SRB2_BASE);
		init_unused_ring(dev, SRB3_BASE);
	} else if (IS_GEN2(dev)) {
		init_unused_ring(dev, SRB0_BASE);
		init_unused_ring(dev, SRB1_BASE);
	} else if (IS_GEN3(dev)) {
		init_unused_ring(dev, PRB1_BASE);
		init_unused_ring(dev, PRB2_BASE);
	}
}
 
int i915_gem_init_rings(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
 
	/*
	 * At least 830 can leave some of the unused rings
	 * "active" (ie. head != tail) after resume which
	 * will prevent c3 entry. Makes sure all unused rings
	 * are totally idle.
	 */
	init_unused_rings(dev);
 
	ret = intel_init_render_ring_buffer(dev);
	if (ret)
		return ret;
 
    if (HAS_BSD(dev)) {
		ret = intel_init_bsd_ring_buffer(dev);
		if (ret)
			goto cleanup_render_ring;
	}
 
	if (intel_enable_blt(dev)) {
		ret = intel_init_blt_ring_buffer(dev);
		if (ret)
			goto cleanup_bsd_ring;
	}
 
	if (HAS_VEBOX(dev)) {
		ret = intel_init_vebox_ring_buffer(dev);
		if (ret)
			goto cleanup_blt_ring;
	}
 
	if (HAS_BSD2(dev)) {
		ret = intel_init_bsd2_ring_buffer(dev);
		if (ret)
			goto cleanup_vebox_ring;
	}
 
	ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
	if (ret)
		goto cleanup_bsd2_ring;
 
	return 0;
 
cleanup_bsd2_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
cleanup_vebox_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
cleanup_blt_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
cleanup_bsd_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
cleanup_render_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
 
	return ret;
}
 
int
i915_gem_init_hw(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret, i;
 
	if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
		return -EIO;
 
	if (dev_priv->ellc_size)
		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
	if (IS_HASWELL(dev))
		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
	if (HAS_PCH_NOP(dev)) {
		if (IS_IVYBRIDGE(dev)) {
		u32 temp = I915_READ(GEN7_MSG_CTL);
		temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
		I915_WRITE(GEN7_MSG_CTL, temp);
		} else if (INTEL_INFO(dev)->gen >= 7) {
			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
		}
	}
 
	i915_gem_init_swizzling(dev);
 
	ret = dev_priv->gt.init_rings(dev);
	if (ret)
		return ret;
 
	for (i = 0; i < NUM_L3_SLICES(dev); i++)
		i915_gem_l3_remap(&dev_priv->ring[RCS], i);
 
	/*
	 * XXX: Contexts should only be initialized once. Doing a switch to the
	 * default context switch however is something we'd like to do after
	 * reset or thaw (the latter may not actually be necessary for HW, but
	 * goes with our code better). Context switching requires rings (for
	 * the do_switch), but before enabling PPGTT. So don't move this.
	 */
	ret = i915_gem_context_enable(dev_priv);
	if (ret && ret != -EIO) {
		DRM_ERROR("Context enable failed %d\n", ret);
		i915_gem_cleanup_ringbuffer(dev);
 
		return ret;
	}
 
	ret = i915_ppgtt_init_hw(dev);
	if (ret && ret != -EIO) {
		DRM_ERROR("PPGTT enable failed %d\n", ret);
		i915_gem_cleanup_ringbuffer(dev);
	}
 
	return ret;
}
 
int i915_gem_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
 
	i915.enable_execlists = intel_sanitize_enable_execlists(dev,
			i915.enable_execlists);
 
	mutex_lock(&dev->struct_mutex);
 
	if (IS_VALLEYVIEW(dev)) {
		/* VLVA0 (potential hack), BIOS isn't actually waking us */
		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
			      VLV_GTLC_ALLOWWAKEACK), 10))
			DRM_DEBUG_DRIVER("allow wake ack timed out\n");
	}
 
	if (!i915.enable_execlists) {
		dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
		dev_priv->gt.init_rings = i915_gem_init_rings;
		dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
		dev_priv->gt.stop_ring = intel_stop_ring_buffer;
	} else {
		dev_priv->gt.do_execbuf = intel_execlists_submission;
		dev_priv->gt.init_rings = intel_logical_rings_init;
		dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
		dev_priv->gt.stop_ring = intel_logical_ring_stop;
	}
 
//   ret = i915_gem_init_userptr(dev);
//   if (ret) {
//       mutex_unlock(&dev->struct_mutex);
//       return ret;
//   }
 
    i915_gem_init_global_gtt(dev);
 
	ret = i915_gem_context_init(dev);
	if (ret) {
		mutex_unlock(&dev->struct_mutex);
		return ret;
	}
 
	ret = i915_gem_init_hw(dev);
	if (ret == -EIO) {
		/* Allow ring initialisation to fail by marking the GPU as
		 * wedged. But we only want to do this where the GPU is angry,
		 * for all other failure, such as an allocation failure, bail.
		 */
		DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
		atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
		ret = 0;
	}
	mutex_unlock(&dev->struct_mutex);
 
		return ret;
}
 
void
i915_gem_cleanup_ringbuffer(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring;
	int i;
 
	for_each_ring(ring, dev_priv, i)
		dev_priv->gt.cleanup_ring(ring);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
static void
init_ring_lists(struct intel_engine_cs *ring)
{
    INIT_LIST_HEAD(&ring->active_list);
    INIT_LIST_HEAD(&ring->request_list);
}
 
void i915_init_vm(struct drm_i915_private *dev_priv,
			 struct i915_address_space *vm)
{
	if (!i915_is_ggtt(vm))
		drm_mm_init(&vm->mm, vm->start, vm->total);
	vm->dev = dev_priv->dev;
	INIT_LIST_HEAD(&vm->active_list);
	INIT_LIST_HEAD(&vm->inactive_list);
	INIT_LIST_HEAD(&vm->global_link);
	list_add_tail(&vm->global_link, &dev_priv->vm_list);
}
 
void
i915_gem_load(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
    int i;
 
	INIT_LIST_HEAD(&dev_priv->vm_list);
	i915_init_vm(dev_priv, &dev_priv->gtt.base);
 
	INIT_LIST_HEAD(&dev_priv->context_list);
	INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
	INIT_LIST_HEAD(&dev_priv->mm.bound_list);
    INIT_LIST_HEAD(&dev_priv->mm.fence_list);
    for (i = 0; i < I915_NUM_RINGS; i++)
        init_ring_lists(&dev_priv->ring[i]);
	for (i = 0; i < I915_MAX_NUM_FENCES; i++)
        INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
	INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
			  i915_gem_retire_work_handler);
	INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
			  i915_gem_idle_work_handler);
	init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
 
    /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
	if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
		I915_WRITE(MI_ARB_STATE,
			   _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
    }
 
    dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 
	/* Old X drivers will take 0-2 for front, back, depth buffers */
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		dev_priv->fence_reg_start = 3;
 
	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
		dev_priv->num_fence_regs = 32;
	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
        dev_priv->num_fence_regs = 16;
    else
        dev_priv->num_fence_regs = 8;
 
    /* Initialize fence registers to zero */
	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
	i915_gem_restore_fences(dev);
 
    i915_gem_detect_bit_6_swizzle(dev);
 
    dev_priv->mm.interruptible = true;
 
	mutex_init(&dev_priv->fb_tracking.lock);
}
 
int i915_gem_open(struct drm_device *dev, struct drm_file *file)
{
	struct drm_i915_file_private *file_priv;
	int ret;
 
	DRM_DEBUG_DRIVER("\n");
 
	file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
	if (!file_priv)
		return -ENOMEM;
 
	file->driver_priv = file_priv;
	file_priv->dev_priv = dev->dev_private;
	file_priv->file = file;
 
	spin_lock_init(&file_priv->mm.lock);
	INIT_LIST_HEAD(&file_priv->mm.request_list);
//	INIT_DELAYED_WORK(&file_priv->mm.idle_work,
//			  i915_gem_file_idle_work_handler);
 
	ret = i915_gem_context_open(dev, file);
	if (ret)
		kfree(file_priv);
 
	return ret;
}
 
/**
 * i915_gem_track_fb - update frontbuffer tracking
 * old: current GEM buffer for the frontbuffer slots
 * new: new GEM buffer for the frontbuffer slots
 * frontbuffer_bits: bitmask of frontbuffer slots
 *
 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
 * from @old and setting them in @new. Both @old and @new can be NULL.
 */
void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits)
{
	if (old) {
		WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
		WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
		old->frontbuffer_bits &= ~frontbuffer_bits;
	}
 
	if (new) {
		WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
		WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
		new->frontbuffer_bits |= frontbuffer_bits;
	}
}
 
static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
{
	if (!mutex_is_locked(mutex))
		return false;
 
#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
	return mutex->owner == task;
#else
	/* Since UP may be pre-empted, we cannot assume that we own the lock */
	return false;
#endif
}
 
/* All the new VM stuff */
unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
				  struct i915_address_space *vm)
{
	struct drm_i915_private *dev_priv = o->base.dev->dev_private;
	struct i915_vma *vma;
 
 
 
	WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
 
	list_for_each_entry(vma, &o->vma_list, vma_link) {
		if (vma->vm == vm)
			return vma->node.start;
 
	}
	WARN(1, "%s vma for this object not found.\n",
	     i915_is_ggtt(vm) ? "global" : "ppgtt");
	return -1;
}
 
bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
			struct i915_address_space *vm)
{
	struct i915_vma *vma;
 
	list_for_each_entry(vma, &o->vma_list, vma_link)
		if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
			return true;
 
	return false;
}
 
bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
{
	struct i915_vma *vma;
 
	list_for_each_entry(vma, &o->vma_list, vma_link)
		if (drm_mm_node_allocated(&vma->node))
			return true;
 
	return false;
}
 
unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
				struct i915_address_space *vm)
{
	struct drm_i915_private *dev_priv = o->base.dev->dev_private;
	struct i915_vma *vma;
 
 
 
	WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
 
	BUG_ON(list_empty(&o->vma_list));
 
	list_for_each_entry(vma, &o->vma_list, vma_link)
		if (vma->vm == vm)
			return vma->node.size;
 
	return 0;
}
 
 
 
struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
{
	struct i915_vma *vma;
 
 
 
 
 
 
 
	vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
	if (vma->vm != i915_obj_to_ggtt(obj))
		return NULL;
 
	return vma;
}
>

Rev 5060	Rev 5354
1	/*	1	/*
2	* Copyright © 2008 Intel Corporation	2	* Copyright © 2008 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21	* IN THE SOFTWARE.	21	* IN THE SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Eric Anholt	24	* Eric Anholt
25	*	25	*
26	*/	26	*/
27		27
28	#include	28	#include
29	#include	29	#include
30	#include	30	#include
31	#include "i915_drv.h"	31	#include "i915_drv.h"
32	#include "i915_trace.h"	32	#include "i915_trace.h"
33	#include "intel_drv.h"	33	#include "intel_drv.h"
34	#include	34	#include
35	#include	35	#include
36	//#include	36	//#include
37	#include	37	#include
38	#include	38	#include
39		39
40	extern int x86_clflush_size;	40	extern int x86_clflush_size;
41		41
42	#define PROT_READ 0x1 /* page can be read */	42	#define PROT_READ 0x1 /* page can be read */
43	#define PROT_WRITE 0x2 /* page can be written */	43	#define PROT_WRITE 0x2 /* page can be written */
44	#define MAP_SHARED 0x01 /* Share changes */	44	#define MAP_SHARED 0x01 /* Share changes */
45		45
46		46
47	u64 nsecs_to_jiffies64(u64 n)	47	u64 nsecs_to_jiffies64(u64 n)
48	{	48	{
49	#if (NSEC_PER_SEC % HZ) == 0	49	#if (NSEC_PER_SEC % HZ) == 0
50	/* Common case, HZ = 100, 128, 200, 250, 256, 500, 512, 1000 etc. */	50	/* Common case, HZ = 100, 128, 200, 250, 256, 500, 512, 1000 etc. */
51	return div_u64(n, NSEC_PER_SEC / HZ);	51	return div_u64(n, NSEC_PER_SEC / HZ);
52	#elif (HZ % 512) == 0	52	#elif (HZ % 512) == 0
53	/* overflow after 292 years if HZ = 1024 */	53	/* overflow after 292 years if HZ = 1024 */
54	return div_u64(n * HZ / 512, NSEC_PER_SEC / 512);	54	return div_u64(n * HZ / 512, NSEC_PER_SEC / 512);
55	#else	55	#else
56	/*	56	/*
57	* Generic case - optimized for cases where HZ is a multiple of 3.	57	* Generic case - optimized for cases where HZ is a multiple of 3.
58	* overflow after 64.99 years, exact for HZ = 60, 72, 90, 120 etc.	58	* overflow after 64.99 years, exact for HZ = 60, 72, 90, 120 etc.
59	*/	59	*/
60	return div_u64(n * 9, (9ull * NSEC_PER_SEC + HZ / 2) / HZ);	60	return div_u64(n * 9, (9ull * NSEC_PER_SEC + HZ / 2) / HZ);
61	#endif	61	#endif
62	}	62	}
63		63
64	unsigned long nsecs_to_jiffies(u64 n)	64	unsigned long nsecs_to_jiffies(u64 n)
65	{	65	{
66	return (unsigned long)nsecs_to_jiffies64(n);	66	return (unsigned long)nsecs_to_jiffies64(n);
67	}	67	}
68		68
69		69
70	struct drm_i915_gem_object *get_fb_obj();	70	struct drm_i915_gem_object *get_fb_obj();
71		71
72	unsigned long vm_mmap(struct file *file, unsigned long addr,	72	unsigned long vm_mmap(struct file *file, unsigned long addr,
73	unsigned long len, unsigned long prot,	73	unsigned long len, unsigned long prot,
74	unsigned long flag, unsigned long offset);	74	unsigned long flag, unsigned long offset);
75		-
76	static inline void clflush(volatile void *__p)	-
77	{	-
78	asm volatile("clflush %0" : "+m" ((volatile char)__p));	-
79	}	75
80		76
81	#define MAX_ERRNO 4095	77	#define MAX_ERRNO 4095
82		78
83	#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)	79	#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
84		80
85		81
86	static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);	82	static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
87	static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,	83	static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
88	bool force);	84	bool force);
89	static __must_check int	85	static __must_check int
90	i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,	86	i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
91	bool readonly);	87	bool readonly);
92	static void	88	static void
93	i915_gem_object_retire(struct drm_i915_gem_object *obj);	89	i915_gem_object_retire(struct drm_i915_gem_object *obj);
94		90
95	static void i915_gem_write_fence(struct drm_device *dev, int reg,	91	static void i915_gem_write_fence(struct drm_device *dev, int reg,
96	struct drm_i915_gem_object *obj);	92	struct drm_i915_gem_object *obj);
97	static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,	93	static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
98	struct drm_i915_fence_reg *fence,	94	struct drm_i915_fence_reg *fence,
99	bool enable);	95	bool enable);
100		-
-		96
101	static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);	97
102	static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);	98	static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
103		99
104	static bool cpu_cache_is_coherent(struct drm_device *dev,	100	static bool cpu_cache_is_coherent(struct drm_device *dev,
105	enum i915_cache_level level)	101	enum i915_cache_level level)
106	{	102	{
107	return HAS_LLC(dev) \|\| level != I915_CACHE_NONE;	103	return HAS_LLC(dev) \|\| level != I915_CACHE_NONE;
108	}	104	}
109		105
110	static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)	106	static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
111	{	107	{
112	if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))	108	if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
113	return true;	109	return true;
114		110
115	return obj->pin_display;	111	return obj->pin_display;
116	}	112	}
117		113
118	static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)	114	static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
119	{	115	{
120	if (obj->tiling_mode)	116	if (obj->tiling_mode)
121	i915_gem_release_mmap(obj);	117	i915_gem_release_mmap(obj);
122		118
123	/* As we do not have an associated fence register, we will force	119	/* As we do not have an associated fence register, we will force
124	* a tiling change if we ever need to acquire one.	120	* a tiling change if we ever need to acquire one.
125	*/	121	*/
126	obj->fence_dirty = false;	122	obj->fence_dirty = false;
127	obj->fence_reg = I915_FENCE_REG_NONE;	123	obj->fence_reg = I915_FENCE_REG_NONE;
128	}	124	}
129		125
130	/* some bookkeeping */	126	/* some bookkeeping */
131	static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,	127	static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
132	size_t size)	128	size_t size)
133	{	129	{
134	spin_lock(&dev_priv->mm.object_stat_lock);	130	spin_lock(&dev_priv->mm.object_stat_lock);
135	dev_priv->mm.object_count++;	131	dev_priv->mm.object_count++;
136	dev_priv->mm.object_memory += size;	132	dev_priv->mm.object_memory += size;
137	spin_unlock(&dev_priv->mm.object_stat_lock);	133	spin_unlock(&dev_priv->mm.object_stat_lock);
138	}	134	}
139		135
140	static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,	136	static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
141	size_t size)	137	size_t size)
142	{	138	{
143	spin_lock(&dev_priv->mm.object_stat_lock);	139	spin_lock(&dev_priv->mm.object_stat_lock);
144	dev_priv->mm.object_count--;	140	dev_priv->mm.object_count--;
145	dev_priv->mm.object_memory -= size;	141	dev_priv->mm.object_memory -= size;
146	spin_unlock(&dev_priv->mm.object_stat_lock);	142	spin_unlock(&dev_priv->mm.object_stat_lock);
147	}	143	}
148		144
149	static int	145	static int
150	i915_gem_wait_for_error(struct i915_gpu_error *error)	146	i915_gem_wait_for_error(struct i915_gpu_error *error)
151	{	147	{
152	int ret;	148	int ret;
153		149
154	#define EXIT_COND (!i915_reset_in_progress(error))	150	#define EXIT_COND (!i915_reset_in_progress(error))
155	if (EXIT_COND)	151	if (EXIT_COND)
156	return 0;	152	return 0;
157	#if 0	153	#if 0
158	/*	154	/*
159	* Only wait 10 seconds for the gpu reset to complete to avoid hanging	155	* Only wait 10 seconds for the gpu reset to complete to avoid hanging
160	* userspace. If it takes that long something really bad is going on and	156	* userspace. If it takes that long something really bad is going on and
161	* we should simply try to bail out and fail as gracefully as possible.	157	* we should simply try to bail out and fail as gracefully as possible.
162	*/	158	*/
163	ret = wait_event_interruptible_timeout(error->reset_queue,	159	ret = wait_event_interruptible_timeout(error->reset_queue,
164	EXIT_COND,	160	EXIT_COND,
165	10*HZ);	161	10*HZ);
166	if (ret == 0) {	162	if (ret == 0) {
167	DRM_ERROR("Timed out waiting for the gpu reset to complete\n");	163	DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
168	return -EIO;	164	return -EIO;
169	} else if (ret < 0) {	165	} else if (ret < 0) {
170	return ret;	166	return ret;
171	}	167	}
172		168
173	#endif	169	#endif
174	#undef EXIT_COND	170	#undef EXIT_COND
175		171
176	return 0;	172	return 0;
177	}	173	}
178		174
179	int i915_mutex_lock_interruptible(struct drm_device *dev)	175	int i915_mutex_lock_interruptible(struct drm_device *dev)
180	{	176	{
181	struct drm_i915_private *dev_priv = dev->dev_private;	177	struct drm_i915_private *dev_priv = dev->dev_private;
182	int ret;	178	int ret;
183		179
184	ret = i915_gem_wait_for_error(&dev_priv->gpu_error);	180	ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
185	if (ret)	181	if (ret)
186	return ret;	182	return ret;
187		183
188	ret = mutex_lock_interruptible(&dev->struct_mutex);	184	ret = mutex_lock_interruptible(&dev->struct_mutex);
189	if (ret)	185	if (ret)
190	return ret;	186	return ret;
191		187
192	WARN_ON(i915_verify_lists(dev));	188	WARN_ON(i915_verify_lists(dev));
193	return 0;	189	return 0;
194	}	190	}
195		191
196	static inline bool	192	static inline bool
197	i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)	193	i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
198	{	194	{
199	return i915_gem_obj_bound_any(obj) && !obj->active;	195	return i915_gem_obj_bound_any(obj) && !obj->active;
200	}	196	}
201		-
202		-
203	#if 0	-
204		-
205	int	-
206	i915_gem_init_ioctl(struct drm_device dev, void data,	-
207	struct drm_file *file)	-
208	{	-
209	struct drm_i915_private *dev_priv = dev->dev_private;	-
210	struct drm_i915_gem_init *args = data;	-
211		-
212	if (drm_core_check_feature(dev, DRIVER_MODESET))	-
213	return -ENODEV;	-
214		-
215	if (args->gtt_start >= args->gtt_end \|\|	-
216	(args->gtt_end \| args->gtt_start) & (PAGE_SIZE - 1))	-
217	return -EINVAL;	-
218		-
219	/* GEM with user mode setting was never supported on ilk and later. */	-
220	if (INTEL_INFO(dev)->gen >= 5)	-
221	return -ENODEV;	-
222		-
223	mutex_lock(&dev->struct_mutex);	-
224	i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,	-
225	args->gtt_end);	-
226	dev_priv->gtt.mappable_end = args->gtt_end;	-
227	mutex_unlock(&dev->struct_mutex);	-
228		-
229	return 0;	-
230	}	-
231	#endif	-
232		197
233	int	198	int
234	i915_gem_get_aperture_ioctl(struct drm_device dev, void data,	199	i915_gem_get_aperture_ioctl(struct drm_device dev, void data,
235	struct drm_file *file)	200	struct drm_file *file)
236	{	201	{
237	struct drm_i915_private *dev_priv = dev->dev_private;	202	struct drm_i915_private *dev_priv = dev->dev_private;
238	struct drm_i915_gem_get_aperture *args = data;	203	struct drm_i915_gem_get_aperture *args = data;
239	struct drm_i915_gem_object *obj;	204	struct drm_i915_gem_object *obj;
240	size_t pinned;	205	size_t pinned;
241		206
242	pinned = 0;	207	pinned = 0;
243	mutex_lock(&dev->struct_mutex);	208	mutex_lock(&dev->struct_mutex);
244	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)	209	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
245	if (i915_gem_obj_is_pinned(obj))	210	if (i915_gem_obj_is_pinned(obj))
246	pinned += i915_gem_obj_ggtt_size(obj);	211	pinned += i915_gem_obj_ggtt_size(obj);
247	mutex_unlock(&dev->struct_mutex);	212	mutex_unlock(&dev->struct_mutex);
248		213
249	args->aper_size = dev_priv->gtt.base.total;	214	args->aper_size = dev_priv->gtt.base.total;
250	args->aper_available_size = args->aper_size - pinned;	215	args->aper_available_size = args->aper_size - pinned;
251		216
252	return 0;	217	return 0;
253	}	218	}
254		219
255	void i915_gem_object_alloc(struct drm_device dev)	220	void i915_gem_object_alloc(struct drm_device dev)
256	{	221	{
257	struct drm_i915_private *dev_priv = dev->dev_private;	222	struct drm_i915_private *dev_priv = dev->dev_private;
258	return kmalloc(sizeof(struct drm_i915_gem_object), 0);	223	return kmalloc(sizeof(struct drm_i915_gem_object), 0);
259	}	224	}
260		225
261	void i915_gem_object_free(struct drm_i915_gem_object *obj)	226	void i915_gem_object_free(struct drm_i915_gem_object *obj)
262	{	227	{
263	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;	228	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
264	kfree(obj);	229	kfree(obj);
265	}	230	}
266		231
267	static int	232	static int
268	i915_gem_create(struct drm_file *file,	233	i915_gem_create(struct drm_file *file,
269	struct drm_device *dev,	234	struct drm_device *dev,
270	uint64_t size,	235	uint64_t size,
271	uint32_t *handle_p)	236	uint32_t *handle_p)
272	{	237	{
273	struct drm_i915_gem_object *obj;	238	struct drm_i915_gem_object *obj;
274	int ret;	239	int ret;
275	u32 handle;	240	u32 handle;
276		241
277	size = roundup(size, PAGE_SIZE);	242	size = roundup(size, PAGE_SIZE);
278	if (size == 0)	243	if (size == 0)
279	return -EINVAL;	244	return -EINVAL;
280		245
281	/* Allocate the new object */	246	/* Allocate the new object */
282	obj = i915_gem_alloc_object(dev, size);	247	obj = i915_gem_alloc_object(dev, size);
283	if (obj == NULL)	248	if (obj == NULL)
284	return -ENOMEM;	249	return -ENOMEM;
285		250
286	ret = drm_gem_handle_create(file, &obj->base, &handle);	251	ret = drm_gem_handle_create(file, &obj->base, &handle);
287	/* drop reference from allocate - handle holds it now */	252	/* drop reference from allocate - handle holds it now */
288	drm_gem_object_unreference_unlocked(&obj->base);	253	drm_gem_object_unreference_unlocked(&obj->base);
289	if (ret)	254	if (ret)
290	return ret;	255	return ret;
291		256
292	*handle_p = handle;	257	*handle_p = handle;
293	return 0;	258	return 0;
294	}	259	}
295		260
296	int	261	int
297	i915_gem_dumb_create(struct drm_file *file,	262	i915_gem_dumb_create(struct drm_file *file,
298	struct drm_device *dev,	263	struct drm_device *dev,
299	struct drm_mode_create_dumb *args)	264	struct drm_mode_create_dumb *args)
300	{	265	{
301	/* have to work out size/pitch and return them */	266	/* have to work out size/pitch and return them */
302	args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);	267	args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
303	args->size = args->pitch * args->height;	268	args->size = args->pitch * args->height;
304	return i915_gem_create(file, dev,	269	return i915_gem_create(file, dev,
305	args->size, &args->handle);	270	args->size, &args->handle);
306	}	271	}
307		272
308	/**	273	/**
309	* Creates a new mm object and returns a handle to it.	274	* Creates a new mm object and returns a handle to it.
310	*/	275	*/
311	int	276	int
312	i915_gem_create_ioctl(struct drm_device dev, void data,	277	i915_gem_create_ioctl(struct drm_device dev, void data,
313	struct drm_file *file)	278	struct drm_file *file)
314	{	279	{
315	struct drm_i915_gem_create *args = data;	280	struct drm_i915_gem_create *args = data;
316		281
317	return i915_gem_create(file, dev,	282	return i915_gem_create(file, dev,
318	args->size, &args->handle);	283	args->size, &args->handle);
319	}	284	}
320		285
321		286
322	#if 0	287	#if 0
323		288
324	static inline int	289	static inline int
325	__copy_to_user_swizzled(char __user *cpu_vaddr,	290	__copy_to_user_swizzled(char __user *cpu_vaddr,
326	const char *gpu_vaddr, int gpu_offset,	291	const char *gpu_vaddr, int gpu_offset,
327	int length)	292	int length)
328	{	293	{
329	int ret, cpu_offset = 0;	294	int ret, cpu_offset = 0;
330		295
331	while (length > 0) {	296	while (length > 0) {
332	int cacheline_end = ALIGN(gpu_offset + 1, 64);	297	int cacheline_end = ALIGN(gpu_offset + 1, 64);
333	int this_length = min(cacheline_end - gpu_offset, length);	298	int this_length = min(cacheline_end - gpu_offset, length);
334	int swizzled_gpu_offset = gpu_offset ^ 64;	299	int swizzled_gpu_offset = gpu_offset ^ 64;
335		300
336	ret = __copy_to_user(cpu_vaddr + cpu_offset,	301	ret = __copy_to_user(cpu_vaddr + cpu_offset,
337	gpu_vaddr + swizzled_gpu_offset,	302	gpu_vaddr + swizzled_gpu_offset,
338	this_length);	303	this_length);
339	if (ret)	304	if (ret)
340	return ret + length;	305	return ret + length;
341		306
342	cpu_offset += this_length;	307	cpu_offset += this_length;
343	gpu_offset += this_length;	308	gpu_offset += this_length;
344	length -= this_length;	309	length -= this_length;
345	}	310	}
346		311
347	return 0;	312	return 0;
348	}	313	}
349		314
350	static inline int	315	static inline int
351	__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,	316	__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
352	const char __user *cpu_vaddr,	317	const char __user *cpu_vaddr,
353	int length)	318	int length)
354	{	319	{
355	int ret, cpu_offset = 0;	320	int ret, cpu_offset = 0;
356		321
357	while (length > 0) {	322	while (length > 0) {
358	int cacheline_end = ALIGN(gpu_offset + 1, 64);	323	int cacheline_end = ALIGN(gpu_offset + 1, 64);
359	int this_length = min(cacheline_end - gpu_offset, length);	324	int this_length = min(cacheline_end - gpu_offset, length);
360	int swizzled_gpu_offset = gpu_offset ^ 64;	325	int swizzled_gpu_offset = gpu_offset ^ 64;
361		326
362	ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,	327	ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
363	cpu_vaddr + cpu_offset,	328	cpu_vaddr + cpu_offset,
364	this_length);	329	this_length);
365	if (ret)	330	if (ret)
366	return ret + length;	331	return ret + length;
367		332
368	cpu_offset += this_length;	333	cpu_offset += this_length;
369	gpu_offset += this_length;	334	gpu_offset += this_length;
370	length -= this_length;	335	length -= this_length;
371	}	336	}
372		337
373	return 0;	338	return 0;
374	}	339	}
375		340
376	/* Per-page copy function for the shmem pread fastpath.	341	/* Per-page copy function for the shmem pread fastpath.
377	* Flushes invalid cachelines before reading the target if	342	* Flushes invalid cachelines before reading the target if
378	* needs_clflush is set. */	343	* needs_clflush is set. */
379	static int	344	static int
380	shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,	345	shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
381	char __user *user_data,	346	char __user *user_data,
382	bool page_do_bit17_swizzling, bool needs_clflush)	347	bool page_do_bit17_swizzling, bool needs_clflush)
383	{	348	{
384	char *vaddr;	349	char *vaddr;
385	int ret;	350	int ret;
386		351
387	if (unlikely(page_do_bit17_swizzling))	352	if (unlikely(page_do_bit17_swizzling))
388	return -EINVAL;	353	return -EINVAL;
389		354
390	vaddr = kmap_atomic(page);	355	vaddr = kmap_atomic(page);
391	if (needs_clflush)	356	if (needs_clflush)
392	drm_clflush_virt_range(vaddr + shmem_page_offset,	357	drm_clflush_virt_range(vaddr + shmem_page_offset,
393	page_length);	358	page_length);
394	ret = __copy_to_user_inatomic(user_data,	359	ret = __copy_to_user_inatomic(user_data,
395	vaddr + shmem_page_offset,	360	vaddr + shmem_page_offset,
396	page_length);	361	page_length);
397	kunmap_atomic(vaddr);	362	kunmap_atomic(vaddr);
398		363
399	return ret ? -EFAULT : 0;	364	return ret ? -EFAULT : 0;
400	}	365	}
401		366
402	static void	367	static void
403	shmem_clflush_swizzled_range(char *addr, unsigned long length,	368	shmem_clflush_swizzled_range(char *addr, unsigned long length,
404	bool swizzled)	369	bool swizzled)
405	{	370	{
406	if (unlikely(swizzled)) {	371	if (unlikely(swizzled)) {
407	unsigned long start = (unsigned long) addr;	372	unsigned long start = (unsigned long) addr;
408	unsigned long end = (unsigned long) addr + length;	373	unsigned long end = (unsigned long) addr + length;
409		374
410	/* For swizzling simply ensure that we always flush both	375	/* For swizzling simply ensure that we always flush both
411	* channels. Lame, but simple and it works. Swizzled	376	* channels. Lame, but simple and it works. Swizzled
412	* pwrite/pread is far from a hotpath - current userspace	377	* pwrite/pread is far from a hotpath - current userspace
413	* doesn't use it at all. */	378	* doesn't use it at all. */
414	start = round_down(start, 128);	379	start = round_down(start, 128);
415	end = round_up(end, 128);	380	end = round_up(end, 128);
416		381
417	drm_clflush_virt_range((void *)start, end - start);	382	drm_clflush_virt_range((void *)start, end - start);
418	} else {	383	} else {
419	drm_clflush_virt_range(addr, length);	384	drm_clflush_virt_range(addr, length);
420	}	385	}
421		386
422	}	387	}
423		388
424	/* Only difference to the fast-path function is that this can handle bit17	389	/* Only difference to the fast-path function is that this can handle bit17
425	* and uses non-atomic copy and kmap functions. */	390	* and uses non-atomic copy and kmap functions. */
426	static int	391	static int
427	shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,	392	shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
428	char __user *user_data,	393	char __user *user_data,
429	bool page_do_bit17_swizzling, bool needs_clflush)	394	bool page_do_bit17_swizzling, bool needs_clflush)
430	{	395	{
431	char *vaddr;	396	char *vaddr;
432	int ret;	397	int ret;
433		398
434	vaddr = kmap(page);	399	vaddr = kmap(page);
435	if (needs_clflush)	400	if (needs_clflush)
436	shmem_clflush_swizzled_range(vaddr + shmem_page_offset,	401	shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
437	page_length,	402	page_length,
438	page_do_bit17_swizzling);	403	page_do_bit17_swizzling);
439		404
440	if (page_do_bit17_swizzling)	405	if (page_do_bit17_swizzling)
441	ret = __copy_to_user_swizzled(user_data,	406	ret = __copy_to_user_swizzled(user_data,
442	vaddr, shmem_page_offset,	407	vaddr, shmem_page_offset,
443	page_length);	408	page_length);
444	else	409	else
445	ret = __copy_to_user(user_data,	410	ret = __copy_to_user(user_data,
446	vaddr + shmem_page_offset,	411	vaddr + shmem_page_offset,
447	page_length);	412	page_length);
448	kunmap(page);	413	kunmap(page);
449		414
450	return ret ? - EFAULT : 0;	415	return ret ? - EFAULT : 0;
451	}	416	}
452		417
453	static int	418	static int
454	i915_gem_shmem_pread(struct drm_device *dev,	419	i915_gem_shmem_pread(struct drm_device *dev,
455	struct drm_i915_gem_object *obj,	420	struct drm_i915_gem_object *obj,
456	struct drm_i915_gem_pread *args,	421	struct drm_i915_gem_pread *args,
457	struct drm_file *file)	422	struct drm_file *file)
458	{	423	{
459	char __user *user_data;	424	char __user *user_data;
460	ssize_t remain;	425	ssize_t remain;
461	loff_t offset;	426	loff_t offset;
462	int shmem_page_offset, page_length, ret = 0;	427	int shmem_page_offset, page_length, ret = 0;
463	int obj_do_bit17_swizzling, page_do_bit17_swizzling;	428	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
464	int prefaulted = 0;	429	int prefaulted = 0;
465	int needs_clflush = 0;	430	int needs_clflush = 0;
466	struct sg_page_iter sg_iter;	431	struct sg_page_iter sg_iter;
467		432
468	user_data = to_user_ptr(args->data_ptr);	433	user_data = to_user_ptr(args->data_ptr);
469	remain = args->size;	434	remain = args->size;
470		435
471	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);	436	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
472		437
473	ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);	438	ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
474	if (ret)	439	if (ret)
475	return ret;	440	return ret;
476		441
477	offset = args->offset;	442	offset = args->offset;
478		443
479	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,	444	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
480	offset >> PAGE_SHIFT) {	445	offset >> PAGE_SHIFT) {
481	struct page *page = sg_page_iter_page(&sg_iter);	446	struct page *page = sg_page_iter_page(&sg_iter);
482		447
483	if (remain <= 0)	448	if (remain <= 0)
484	break;	449	break;
485		450
486	/* Operation in this page	451	/* Operation in this page
487	*	452	*
488	* shmem_page_offset = offset within page in shmem file	453	* shmem_page_offset = offset within page in shmem file
489	* page_length = bytes to copy for this page	454	* page_length = bytes to copy for this page
490	*/	455	*/
491	shmem_page_offset = offset_in_page(offset);	456	shmem_page_offset = offset_in_page(offset);
492	page_length = remain;	457	page_length = remain;
493	if ((shmem_page_offset + page_length) > PAGE_SIZE)	458	if ((shmem_page_offset + page_length) > PAGE_SIZE)
494	page_length = PAGE_SIZE - shmem_page_offset;	459	page_length = PAGE_SIZE - shmem_page_offset;
495		460
496	page_do_bit17_swizzling = obj_do_bit17_swizzling &&	461	page_do_bit17_swizzling = obj_do_bit17_swizzling &&
497	(page_to_phys(page) & (1 << 17)) != 0;	462	(page_to_phys(page) & (1 << 17)) != 0;
498		463
499	ret = shmem_pread_fast(page, shmem_page_offset, page_length,	464	ret = shmem_pread_fast(page, shmem_page_offset, page_length,

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gem.c – Rev 5060 → 5354